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DESCRIPTION
The WM8581 is a multi-channel audio CODEC with S/PDIF transceiver. The WM8581 is ideal for DVD and surround sound processing applications for home hi-fi, automotive and other audiovisual equipment. Integrated into the device is a stereo 24-bit multi-bit sigma delta ADC with support for digital audio output word lengths from 16-bit to 32-bit, and sampling rates from 8kHz to 192kHz. Also included are four stereo 24-bit multi-bit sigma delta DACs, each with a dedicated oversampling digital interpolation filter. Digital audio input word lengths from 16bits to 32-bits and sampling rates from 8kHz to 192kHz are supported. Each DAC channel has independent digital volume and mute control. Two independent audio data interfaces support I2S, Left Justified, Right Justified and DSP digital audio formats. Each audio interface can operate in either Master Mode or Slave Mode. The S/PDIF transceiver is IEC-60958-3 compatible and supports frame rates from 32k/s to 96k/s. It has four multiplexed inputs and one output. Status and error monitoring is built-in and results can reported over the serial interface or via GPO pins. S/PDIF Channel Block configuration is also supported. The device has two PLLs that can be configured independently to generate two system clocks for internal or external use. Device control and setup is via a 2-wire or 3-wire (SPI compatible) serial interface. The serial interface provides access to all features including channel selection, volume controls, mutes, de-emphasis, S/PDIF control/status, and power management facilities. Alternatively, the device has a Hardware Control Mode where device features can be enabled/disabled using selected pins. The device is available in a 48-lead TQFP package. * * * * * *
WM8581
Multichannel CODEC with S/PDIF Transceiver
FEATURES
* * * Multi-channel CODEC with 4 Stereo DACs and 1 Stereo ADC Integrated S/PDIF / IEC-60958-3 transceiver Audio Performance - - 103dB SNR (`A' weighted @ 48kHz) DAC -90dB THD (48kHz) DAC
- 100dB SNR (`A' weighted @ 48kHz) ADC - -87dB THD (48kHz) ADC DAC Sampling Frequency: 8kHz - 192kHz ADC Sampling Frequency: 8kHz - 192kHz Independent ADC and DAC Sample Rates 2 and 3-Wire Serial Control Interface with readback, or Hardware Control Interface GPO pins allow visibility of user selected status flags Programmable Audio Data Interface Modes - I2S, Left, Right Justified or DSP - 16/20/24/32 bit Word Lengths Four independent stereo DAC outputs with independent digital volume controls Two Independent Master or Slave Audio Data Interfaces Flexible Digital Interface Routing with Clock Selection Control 2.7V to 5.5V Analogue, 2.7V to 3.6V Digital Supply Operation 48-lead TQFP Package
* * * * *
APPLICATIONS
* * * * Digital TV DVD Players and Receivers Surround Sound AV Processors and Hi-Fi systems Automotive Audio
WOLFSON MICROELECTRONICS plc
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Production Data, April 2007, Rev 4.0 Copyright (c)2007 Wolfson Microelectronics plc
WM8581 BLOCK DIAGRAM
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WM8581 TABLE OF CONTENTS
DESCRIPTION ............................................................................................................................................. 1 FEATURES .................................................................................................................................................. 1 APPLICATIONS ........................................................................................................................................... 1 BLOCK DIAGRAM ....................................................................................................................................... 2 TABLE OF CONTENTS............................................................................................................................... 3 PIN CONFIGURATION ................................................................................................................................ 4 ORDERING INFORMATION........................................................................................................................ 4 PIN DESCRIPTION ...................................................................................................................................... 5
MULTI-FUNCTION PINS .......................................................................................................................................... 6
ABSOLUTE MAXIMUM RATINGS .............................................................................................................. 8 RECOMMENDED OPERATING CONDITIONS .......................................................................................... 9 ELECTRICAL CHARACTERISTICS............................................................................................................ 9
TERMINOLOGY...................................................................................................................................................... 15 MASTER CLOCK TIMING ...................................................................................................................................... 15 DIGITAL AUDIO INTERFACE - MASTER MODE .................................................................................................. 16 DIGITAL AUDIO INTERFACE - SLAVE MODE ..................................................................................................... 17 CONTROL INTERFACE TIMING - 3-WIRE MODE ............................................................................................... 18 CONTROL INTERFACE TIMING - 2-WIRE MODE ............................................................................................... 18
DEVICE DESCRIPTION............................................................................................................................. 20
INTRODUCTION..................................................................................................................................................... 20 CONTROL INTERFACE OPERATION ................................................................................................................... 21 DIGITAL AUDIO INTERFACES .............................................................................................................................. 25 AUDIO DATA FORMATS........................................................................................................................................ 27 AUDIO INTERFACE CONTROL ............................................................................................................................. 31 DAC FEATURES .................................................................................................................................................... 33 ADC FEATURES .................................................................................................................................................... 40 DIGITAL ROUTING OPTIONS................................................................................................................................ 41 CLOCK SELECTION .............................................................................................................................................. 43 PHASE-LOCKED LOOPS AND S/PDIF CLOCKING (SOFTWARE MODE) .......................................................... 49 PHASE-LOCKED LOOPS AND S/PDIF CLOCKING (HARDWARE MODE).......................................................... 57 S/PDIF TRANSCEIVER.......................................................................................................................................... 58 S/PDIF TRANSMITTER .......................................................................................................................................... 59 S/PDIF RECEIVER ................................................................................................................................................. 62 POWERDOWN MODES......................................................................................................................................... 71 INTERNAL POWER ON RESET CIRCUIT............................................................................................................. 73 HARDWARE CONTROL MODE............................................................................................................................. 75 REGISTER MAP ..................................................................................................................................................... 78
DIGITAL FILTER CHARACTERISTICS .................................................................................................... 94
DAC FILTER RESPONSES.................................................................................................................................... 94 DIGITAL DE-EMPHASIS CHARACTERISTICS...................................................................................................... 95 ADC FILTER RESPONSES.................................................................................................................................... 95 ADC HIGH PASS FILTER....................................................................................................................................... 96
APPLICATIONS INFORMATION............................................................................................................... 97
RECOMMENDED EXTERNAL COMPONENTS ..................................................................................................... 97
PACKAGE DIMENSIONS .......................................................................................................................... 99 IMPORTANT NOTICE.............................................................................................................................. 100
ADDRESS:............................................................................................................................................................ 100
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WM8581 PIN CONFIGURATION
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ORDERING INFORMATION
DEVICE WM8581AGEFT/V WM8581AGEFT/RV Note: Reel quantity = 2,200 TEMPERATURE RANGE -25 to +85oC -25 to +85oC PACKAGE 48-lead TQFP (Pb-free) 48-lead TQFP (Pb-free, tape and reel) MOISTURE SENSITIVITY LEVEL MSL1 MSL1 PEAK SOLDERING TEMPERATURE 260C 260C
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WM8581
PIN DESCRIPTION
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 NAME VOUT4L VOUT4R PGND PVDD XTI XTO MFP7 MFP6 SPDIFOP MFP5 MFP4 MFP3 SPDIFIN1 CLKOUT DVDD DGND MUTE DIN1 DIN2 DIN3 DIN4 PAIFRX_LRCLK PAIFRX_BCLK MCLK DOUT PAIFTX_LRCLK MFP1 MFP2 HWMODE SWMODE SDO SDIN SCLK CSB AINR AINL ADCREFP VMID AGND AVDD VOUT1L VOUT1R VOUT2L VOUT2R VREFP VREFN TYPE Analogue Output Analogue Output Supply Supply Digital Input Digital Output Digital Input/Output Digital Input/Output Digital Output Digital Input/Output Digital Input/Output Digital Input/Output Digital Input Digital Output Supply Supply Digital Input/Output Digital Input Digital Input Digital Input Digital Input Digital Input/Output Digital Input/Output Digital Input/Output Digital Output Digital Input/Output Digital Input/Output Digital Input/Output Digital Input Digital Input/Output Digital Output Digital Input/Output Digital Input Digital Input Analogue Input Analogue Input Analogue Output Analogue Output Supply Supply Analogue Output Analogue Output Analogue Output Analogue Output Analogue Input Analogue Input DAC channel 4 left output DAC channel 4 right output PLL ground PLL positive supply Crystal or CMOS clock input Crystal output Multi-Function Pin (MFP) 7. See Table 1 for details of all MFP pins. Multi-Function Pin (MFP) 6. See Table 1 for details of all MFP pins. S/PDIF transmitter output Multi-Function Pin (MFP) 5. See Table 1 for details of all MFP pins. Multi-Function Pin (MFP) 4. See Table 1 for details of all MFP pins. Multi-Function Pin (MFP) 3. See Table 1 for details of all MFP pins. S/PDIF Receiver Input 1 PLL or crystal oscillator clock output Digital positive supply Digital ground DAC mute-all input/ All-DAC Infinite Zero Detect (IZD) flag output Primary Audio Interface (PAIF) receiver data input 1 Primary Audio Interface (PAIF) receiver data input 2 Primary Audio Interface (PAIF) receiver data input 3 Primary Audio Interface (PAIF) receiver data input 4 Primary Audio Interface (PAIF) receiver left/right word clock Primary Audio Interface (PAIF) receiver bit clock System Master clock; 256, 384, 512, 768, 1024 or 1152 fs Primary Audio Interface (PAIF) transmitter data output Primary audio interface transmitter left/right word clock Multi-Function Pin (MFP) 1. See Table 1 for details of all MFP pins. Multi-Function Pin (MFP) 2. See Table 1 for details of all MFP pins. Configures control to be either Software Mode or Hardware Mode Configures software interface to be either 2-wire or 3-wire. See note 2. 3-wire control interface data output. See note 3. Control interface data input (and output under 2-wire control) Control interface clock 3-wire control interface latch signal / device address selection ADC Right Channel Input ADC Left Channel Input ADC reference buffer decoupling pin; 10uF external decoupling Midrail divider decoupling pin; 10uF external decoupling Analogue ground Analogue positive supply DAC channel 1 left output DAC channel 1 right output DAC channel 2 left output DAC channel 2 right output DAC and ADC positive reference DAC and ADC ground reference DESCRIPTION
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WM8581
PIN 47 48 Notes : 1. 2. 3. Digital input pins have Schmitt trigger input buffers. Pins 32, 33, 34 are 5V tolerant. In hardware control mode, pin 30 is used for UNLOCK flag output. In hardware control mode, pin 31 is used for NON_AUDIO flag output. NAME VOUT3L VOUT3R TYPE Analogue Output Analogue Output DAC channel 3 left output DAC channel 3 right output DESCRIPTION
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MULTI-FUNCTION PINS
The WM8581 has 7 Multi-Function Input/Output pins (MFP1 etc.). The function and direction (input/output) of these pins reconfigured using the HWMODE input pin and software register control as shown below. If HWMODE is set, the MFPs have the function shown in column 1 of Table 1. If HWMODE is not set, and the register SAIF_EN is set, the MFPs have the function shown in column 2. Otherwise, the GPOnOP registers determine the MFP function as shown in columns 3 and 4.
Y
HWMODE = 1
N
Y
SAIF_EN = 1
N
GPIOnOP
PIN NAME
HARDWARE CONTROL MODE FUNCTION 1 PAIFTX_BCLK ADCMCLK DR1 DR2 DR3 DR4 ALLPD
SECONDARY AUDIO INTERFACE FUNCTION 2 n/a1 n/a
1
S/PDIF INPUT & INDEPENDENT CLOCKING 3 PAIFTX_BCLK2 ADCMCLK3 SPDIFIN2 SPDIFIN3 SPDIFIN4 GPO6 GPO7
GENERAL PURPOSE OUTPUT FUNCTION 4 GPO1 GPO2 GPO3 GPO4 GPO5 GPO6 GPO7
MFP1 MFP2 MFP3 MFP4 MFP5 MFP6 MFP7
n/a1 SAIF_DIN SAIF_DOUT SAIF_BCLK SAIF_LRCLK
Table 1 Multi-Function Pin Configuration Notes: 1. 2. 3. These pins are not used as part of the Secondary Audio Interface, so their function is that of either Column 3 or Column 4. MFP1 can by GPO1 only if ADC_CLKSEL and PAIFTXMS_CLKSEL (if in master mode) source MCLK.Note that by default ADC_CLKSEL sources ADCMCLK pin. MFP2 can be GPO2 if neither ADC_CLKSEL, TX_CLKSEL or SAIFMS_CLKSEL (if in master mode) source ADCMCLK.Note that by default all three ADC_CLKSEL sources ADCMCLK pin.
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WM8581
TYPE Digital Input/Output Digital Input Digital Input Digital Output Digital Input/Output Digital Input/Output Digital Input Digital Output Digital Input Digital Input DESCRIPTION Primary Audio Interface Transmitter (PAIFTX) Bit Clock Master ADC clock; 256fs, 384fs, 512fs ,786fs, 1024fs or 1152fs Secondary Audio Interface (SAIF) Receiver data input Secondary Audio Interface (SAIF) Transmitter data output Secondary Audio Interface (SAIF) Bit Clock Secondary Audio Interface (SAIF) Left/Right Word Clock S/PDIF Receiver Input General Purpose Output Internal Digital Routing Configuration in Hardware Mode Chip Powerdown in Hardware Mode
PIN FUNCTION PAIFTX_BCLK ADCMCLK SAIF_DIN SAIF_DOUT SAIF_BCLK SAIF_LRCLK SPDIFIN2/3/4 GPO1 - GPO7 DR1/2/3/4 ALLPD
Table 2 Multi-Function Pin Description
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WM8581 ABSOLUTE MAXIMUM RATINGS
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Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. The WM8581 has been classified as MSL1, which has an unlimited floor life at <30oC / 85% Relative Humidity and therefore will not be supplied in moisture barrier bags. CONDITION Digital supply voltage Analogue supply voltage PLL supply voltage Voltage range digital inputs (SCLK, CSB & SDIN only) Voltage range digital inputs Voltage range analogue inputs Master Clock Frequency Operating temperature range, TA Storage temperature prior to soldering Storage temperature after soldering Pb Free Package body temperature (soldering 10 seconds) Package body temperature (soldering 2 minutes) Notes: 1. Analogue and digital grounds must always be within 0.3V of each other. Table 3 Absolute Maximum Ratings -25C -65C
1
MIN -0.3V -0.3V -0.3V DGND -0.3V DGND -0.3V AGND -0.3V PGND -0.3V
MAX +3.63V +7V +5V +7V DVDD + 0.3V AVDD +0.3V PVDD +0.3V 37MHz +85C +150C +260C +183C
30C max / 85% RH max
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WM8581
RECOMMENDED OPERATING CONDITIONS
PARAMETER Digital supply range Analogue supply range PLL supply range Ground Difference DGND to AGND/PGND Note: Digital supply DVDD must never be more than 0.3V greater than AVDD. Table 4 Recommended Operating Conditions SYMBOL DVDD AVDD PVDD AGND, VREFN, DGND. PGND -0.3 TEST CONDITIONS MIN 2.7 2.7 3.3 0 0 +0.3 TYP MAX 3.6 5.5 5.5 UNIT V V V V V
ELECTRICAL CHARACTERISTICS
Test Conditions AVDD, PVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN = 0V, PGND, DGND = 0V, TA = +25oC, 1kHz Signal, fs = 48kHz, 24-Bit Data, Slave Mode, MCLK, ADCMCLK = 256fs, 1Vrms Input Signal Level unless otherwise stated. PARAMETER 0dBFs Full scale output voltage 1.0xVREFP/5 Signal to Noise Ratio (See Terminology note 1,2,4) SNR 95 103 dB SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Vrms DAC Performance (Load = 10k, 50pF)
A-Weighted @ fs = 48kHz Unweighted, @ fs = 48kHz 100 99 dB dB
A-Weighted @ fs = 48kHz, AVDD = 3.3V
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Test Conditions AVDD, PVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN = 0V, PGND, DGND = 0V, TA = +25oC, 1kHz Signal, fs = 48kHz, 24-Bit Data, Slave Mode, MCLK, ADCMCLK = 256fs, 1Vrms Input Signal Level unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP 101 MAX UNIT dB
A-Weighted @ fs = 96kHz Unweighted, @ fs = 96kHz 98 99 dB dB
A-Weighted @ fs = 96kHz, AVDD = 3.3V 101 dB
A-Weighted @ fs = 192kHz Unweighted, @ fs = 192kHz 98 99 dB dB
A-Weighted @ fs = 192kHz, AVDD = 3.3V Dynamic Range (See Terminology note 2,4) Total Harmonic Distortion DNR THD A-weighted, -60dB full scale input 1kHz, 0dB Full Scale @ fs = 48kHz 95 103 -90 -85 dB dB
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WM8581
Test Conditions AVDD, PVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN = 0V, PGND, DGND = 0V, TA = +25oC, 1kHz Signal, fs = 48kHz, 24-Bit Data, Slave Mode, MCLK, ADCMCLK = 256fs, 1Vrms Input Signal Level unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS 1kHz, 0dB Full Scale @ fs = 96kHz 1kHz, 0dB Full Scale @ fs = 192kHz DAC Channel separation Mute Attenuation Output Offset Error 1kHz Input, 0dB gain MIN TYP -87 -84 100 100 2 MAX UNIT dB dB dB dB mV
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WM8581
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Test Conditions AVDD, PVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN = 0V, PGND, DGND = 0V, TA = +25oC, 1kHz Signal, fs = 48kHz, 24-Bit Data, Slave Mode, MCLK, ADCMCLK = 256fs, 1Vrms Input Signal Level unless otherwise stated. PARAMETER Power Supply Rejection Ratio (See note 4) ADC Performance Full Scale Input Signal Level (for ADC 0dB Input) Input resistance Input capacitance Signal to Noise Ratio (See Terminology note 1,2,4) SNR 90 Vrms 1.0xVREFP/5 6 10 100 k pF dB SYMBOL PSRR TEST CONDITIONS 1kHz 100mVp-p 20Hz to 20kHz 100mVp-p MIN TYP 50 45 MAX UNIT dB dB
A-Weighted @ fs = 48kHz Unweighted, @ fs = 48kHz 97 97 dB dB
A-Weighted @ fs = 48kHz, AVDD = 3.3V 97 dB
A-Weighted @ fs = 96kHz Unweighted, @ fs = 96kHz 94 94 dB dB
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WM8581
Test Conditions AVDD, PVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN = 0V, PGND, DGND = 0V, TA = +25oC, 1kHz Signal, fs = 48kHz, 24-Bit Data, Slave Mode, MCLK, ADCMCLK = 256fs, 1Vrms Input Signal Level unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
A-Weighted @ fs = 96kHz, AVDD = 3.3V 97 dB
A-Weighted @ fs = 192kHz Unweighted, @ fs = 192kHz 94 94 dB dB
A-Weighted @ fs = 192kHz, AVDD = 3.3V Total Harmonic Distortion THD 1kHz, -1dB Full Scale @ fs = 48kHz 1kHz, -1dB Full Scale @ fs = 96kHz 1kHz, -1dB Full Scale @ fs = 192kHz Dynamic Range ADC Channel Separation Channel Level Matching (See Terminology note 4) Channel Phase Deviation Offset Error Digital Logic Levels (CMOS Levels) Input LOW level Input HIGH level Input leakage current Input capacitance Output LOW Output HIGH Analogue Reference Levels Reference voltage VVMID VREFP/2 - 50mV VREFP/2 VREFP/2 + 50mV V VOL VOH IOL=1mA IOH= -1mA 0.9 x DVDD VIL VIH 0.7 x DVDD -1 0.2 5 0.1 x DVDD +1 0.3 x DVDD V V A pF V V DNR -60dB FS 1kHz Input 1KHz Signal 1kHz Signal HPF On HPF Off 90 -87 -86 -85 100 97 0.1 0.0001 0 100 dB dB Degree LSB LSB -80 dB dB dB
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Test Conditions AVDD, PVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN = 0V, PGND, DGND = 0V, TA = +25oC, 1kHz Signal, fs = 48kHz, 24-Bit Data, Slave Mode, MCLK, ADCMCLK = 256fs, 1Vrms Input Signal Level unless otherwise stated. PARAMETER Potential divider resistance SYMBOL RVMID TEST CONDITIONS VREFP to VMID and VMID to VREFN VMIDSEL = 1 VREFP to VMID and VMID to VREFN VMIDSEL = 0 S/PDIF Transceiver Performance Jitter on recovered clock S/PDIF Input Levels CMOS MODE Input LOW level Input HIGH level Input capacitance Input Frequency S/PDIF Input Levels Comparator MODE Input capacitance Input resistance Input frequency Input Amplitude PLL Period Jitter XTAL Input XTI LOW level Input XTI HIGH level Input XTI capacitance Input XTI leakage Output XTO LOW Output XTO HIGH Supply Current Analogue supply current Analogue supply current Digital supply current Power Down Table 5 Electrical Characteristics Notes: 1. 2. Ratio of output level with 1kHz full scale input, to the output level with all zeros into the digital input, measured `A' weighted. All performance measurements done with 20kHz low pass filter, and where noted an A-weight filter. Failure to use such a filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in the Electrical Characteristics. The low pass filter removes out of band noise; although it is not audible it may affect dynamic specification values. VMID decoupled with 10uF and 0.1uF capacitors (smaller values may result in reduced performance). PSSR measured with VMID set to high impedance AVDD, VREFP = 5V AVDD, VREFP = 3.3V DVDD = 3.3V 45 30 25 500 mA mA mA A VXIL VXIH CXJ IXleak VXOL VXOH 15pF load capacitors 15pF load capacitors 0 853 3.32 28.92 86 1.458 4.491 38.96 278 1.942 557 mV mV pF mA mV V 80 ps(rms) 200 10 23 25 0.5 X DVDD pF k MHz mV VIL VIH 0.7 X DVDD 1.25 36 0.3 X DVDD V V pF MHz 50 ps MIN TYP 14 MAX UNIT k
44
k
3. 4.
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WM8581
TERMINOLOGY
1. 2. Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full scale output and the output with no signal applied. (No Auto-zero or Automute function is employed in achieving these results). Dynamic range (dB) - DNR is a measure of the difference between the highest and lowest portions of a signal. Normally a THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB to it. (e.g. THD+N @ -60dB= -32dB, DR= 92dB). THD (dB) - THD is a ratio, of the rms values, of Distortion/Signal. Stop band attenuation (dB) - Is the degree to which the frequency spectrum is attenuated (outside audio band). Channel Separation (dB) - Also known as Cross-Talk. This is a measure of the amount one channel is isolated from the other. Normally measured by sending a full scale signal down one channel and measuring the other. Pass-Band Ripple - Any variation of the frequency response in the pass-band region.
3. 4. 5. 6.
MASTER CLOCK TIMING
t MCLKL ADCMCLK/ MCLK t MCLKY
t MCLKH
Figure 1 Master Clock Timing Requirements
Test Conditions AVDD, PVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN = 0V, PGND, DGND = 0V, TA = +25oC PARAMETER System Clock Timing Information
ADCMCLK and MCLK System clock pulse width high ADCMCLK and MCLK System clock pulse width low ADCMCLK and MCLK System clock cycle time ADCMCLK and MCLK Duty cycle
SYMBOL tMCLKH tMCLKL tMCLKY
TEST CONDITIONS
MIN 11 11 28 40:60
TYP
MAX
UNIT ns ns ns
60:40
Table 3 Master Clock Timing Requirements
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WM8581
DIGITAL AUDIO INTERFACE - MASTER MODE
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PAIFRX_BCLK/ PAIFTX_BCLK/ SAIF_BCLK (Output) PAIFRX_LRCLK/ PAIFTX_LRCLK/ SAIF_LRCLK (Outputs) DOUT/ SAIF_DOUT DIN1/2/3/4 SAIF_DIN tDST
Figure 2 Digital Audio Data Timing - Master Mode
tDL
tDDA
tDHT
Test Conditions AVDD, PVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN, PGND, DGND = 0V, TA = +25oC, Master Mode, fs = 48kHz, MCLK and ADCMCLK = 256fs unless otherwise stated. PARAMETER PAIFTX_LRCLK/ PAIFRX_LRCLK/ SAIF_LRCLK propagation delay from PAIFTX_BCLK/ PAIFRX_BCLK/ SAIF_BCLK falling edge DOUT/SAIF_DOUT propagation delay from PAIFTX_BCLK/ SAIF_BCLK falling edge DIN1/2/3/4/SAIF_DIN setup time to PAIFRX_BCLK/SAIF_BCLK rising edge DIN1/2/3/4/SAIF_DIN hold time from PAIFRX_BCLK/SAIF_BCLK rising edge SYMBOL tDL TEST CONDITIONS MIN 0 TYP MAX 10 UNIT ns
Audio Data Input Timing Information
tDDA
0
10
ns
tDST
10
ns
tDHT
10
ns
Table 4 Digital Audio Data Timing - Master Mode
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WM8581
DIGITAL AUDIO INTERFACE - SLAVE MODE
Figure 3 Digital Audio Data Timing - Slave Mode Test Conditions AVDD, PVDD = 5V, DVDD = 3.3V, AGND = 0V, PGND,DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK and ADCMCLK = 256fs unless otherwise stated. PARAMETER Audio Data Input Timing Information PAIFTX_BCLK/ PAIFRX_BCLK/SAIF_BCLK cycle time PAIFTX_BCLK/ PAIFRX_BCLK/SAIF_BCLK pulse width high PAIFTX_BCLK/ PAIFRX_BCLK/SAIF_BCLK pulse width low PAIFTX_LRCLK/ PAIFRX_LRCLK/SAIF_BCLK set-up time to PAIFTX_BCLK/ PAIFRX_BCLK/SAIF_BCLK rising edge PAIFTX_LRCLK/ PAIFRX_LRCLK/ SAIF_LRCLK hold time from PAIFTX_BCLK/ PAIFRX_BCLK/SAIF_BCLK rising edge DIN1/2/3/4/SAIF_DIN set-up time to PAIFRX_BCLK/ SAIF_BCLK rising edge DIN1/2/3/4/SAIF_DIN hold time from PAIFRX_BCLK/SAIF_BCLK rising edge DOUT/SAIF_DOUT propagation delay from PAIFTX_BCLK/SAIF_BCLK falling edge tBCY 50 ns SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
tBCH
20
ns
tBCL
20
ns
tLRSU
10
ns
tLRH
10
ns
tDS
10
ns
tDH
10
ns
tDD
0
10
ns
Table 5 Digital Audio Data Timing - Slave Mode
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CONTROL INTERFACE TIMING - 3-WIRE MODE
t
CSS
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t
CSH
CSB t SCLK
SCY
t
SCS
t
CSS
SDIN t SDO t t
LSB
DSU DHO
LSB
DL
Figure 4 SPI Compatible Control Interface Input Timing
Test Conditions AVDD, PVDD = 5V,DVDD = 3.3V, AGND, PGND,DGND = 0V, TA = +25oC, fs = 48kHz, MCLK and ADCMCLK = 256fs unless otherwise stated PARAMETER SCLK rising edge to CSB rising edge SCLK pulse cycle time SCLK duty cycle SDIN to SCLK set-up time SDIN hold time from SCLK rising edge SDO propagation delay from SCLK rising edge CSB pulse width high CSB rising/falling to SCLK rising SCLK glitch suppression tDSU tDHO tDL tCSH tCSS tps 20 20 2 8 SYMBOL tSCS tSCY MIN 60 80 40/60 20 20 5 60/40 TYP MAX UNIT ns ns ns ns ns ns ns ns ns
Table 6 3-wire SPI Compatible Control Interface Input Timing Information
CONTROL INTERFACE TIMING - 2-WIRE MODE
t
3
t
5
t
3
SDIN
t t t t
6
2
4
8
SCLK
t
1
t
9
t
7
Figure 5 Control Interface Timing - 2-Wire Serial Control Mode
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WM8581
AVDD, PVDD = 5V,DVDD = 3.3V, AGND, PGND,DGND = 0V, TA = +25oC, fs = 48kHz, MCLK and ADCMCLK = 256fs unless otherwise stated PARAMETER Program Register Input Information SCLK Frequency SCLK Low Pulse-Width SCLK High Pulse-Width Hold Time (Start Condition) Setup Time (Start Condition) Data Setup Time SDIN, SCLK Rise Time SDIN, SCLK Fall Time Setup Time (Stop Condition) Data Hold Time SCLK glitch suppression Table 7 2-Wire Control Interface Timing Information t1 t2 t3 t4 t5 t6 t7 t8 t9 tps 0 600 900 5 0 1.3 600 600 600 100 300 300 526 kHz us ns ns ns ns ns ns ns ns ns SYMBOL MIN TYP MAX UNIT
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WM8581 DEVICE DESCRIPTION
INTRODUCTION
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WM8581 is a complete mutli-channel CODEC with integrated S/PDIF transceiver. The device comprises four separate stereo DACs and a stereo ADC, in a single package, and controlled by either software or hardware interfaces. The four stereo DAC outputs are ideal to implement a complete 7.1 channel surround system. Each DAC has its own digital volume control (adjustable in 0.5dB steps) with zero cross detection. With zero cross enabled, volume updates occur as a signal transitions through its zero point. This minimises audible clicks and `zipper' noise as the gain values change. Each stereo DAC has its own data input (DIN1/2/3/4) and shared word clock (PAIFRX_LRCLK), bit clock (PAIFRX_BCLK) and master clock (MCLK). The stereo ADC has data output (DOUT), word clock (PAIFTX_LRCLK), and bit clock (PAIFTX_BCLK). This allows the ADC to operate at a different sample rate to the DACs. In addition, a separate ADC master clock (ADCMCLK) can be used instead of MCLK for further flexibility. There are two independent Digital Audio Interfaces, which may be configured to operate in either master or slave mode. In Slave mode, the LRCLKs and BCLKs are inputs. In Master mode, the LRCLKs and BCLKs are outputs. The Audio Interfaces support Right Justified, Left Justified, I2S and DSP formats. Word lengths of 16, 20, 24 and 32 bits are available (with the exception of 32 bit Right Justified). Operation using system clocks of 128fs, 192fs, 256fs, 384fs, 512fs, 768fs or 1152fs is provided. In Slave mode, selection between clock rates is automatically controlled. In master mode, the master clock to sample rate ratio is set by register control. Sample rates (fs) from less than 8ks/s up to 192ks/s are permitted providing the appropriate system clock is input. The S/PDIF Transceiver is IEC-60958-3 compatible with 32k frames/s to 96k frames/s support. S/PDIF data can be input on one of four pins, and routed internally to the Audio Interfaces, DAC1, and S/PDIF transmitter. Error flags and status information can be read back over the serial interface, or output on GPO pins. The S/PDIF Transmitter can source data from the ADC, S/PDIF Receiver or Audio Interfaces. The Transceiver supports Consumer Mode Channel information, and transmitted Channel bits can be configured via register control. The Digital Routing paths between all the interfaces can be configured by the user, as can the corresponding interface clocking schemes. There are two PLLs, which can be independently configured to generate two system clocks for internal or external use. The serial control interface is controlled by pins CSB, SCLK, and SDIN, which are 5V tolerant with TTL input thresholds, allowing the WM8581 to be used with DVDD = 3.3V and be controlled by a controller with 5V output. The WM8581 may also be controlled in hardware mode, selected by the HWMODE pin. In hardware mode, limited control of internal functionality is available via the Multi-Function Pins (MFPs) and CSB, SCLK, SDIN and MUTE pins.
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WM8581
Control of the WM8581 is implemented either in Hardware Control Mode or Software Control Mode. The method of control is determined by the state of the HWMODE pin. If the HWMODE pin is low, Software Control Mode is selected. If the HWMODE pin is high, Hardware Control Mode is selected. The Software Control Interface is described below and Hardware Control Mode is described on page 75. Software control is implemented with a 3-wire (3-wire write, 4-wire read, SPI compatible) or 2-wire (2wire write, 2-wire read) serial interface. The interface configuration is determined by the state of the SWMODE pin. If the SWMODE pin is low, the 2-wire configuration is selected. If SWMODE is high the 3-wire SPI compatible configuration is selected. HWMODE 0 Software Control 1 Hardware Control 0 2-wire control SWMODE 1 3-wire control
CONTROL INTERFACE OPERATION
Table 8 Hardware/Software Mode Setup The control interface is 5V tolerant, meaning that the control interface input signals CSB, SCLK and SDIN may have an input high level of 5V while DVDD is 3V. Input thresholds are determined by DVDD.
3-WIRE (SPI COMPATIBLE) SERIAL CONTROL MODE WITH READ-BACK
SDIN is used to program data, SCLK is used to clock in the program data and CSB is used to latch the program data. SDIN is sampled on the rising edge of SCLK. The 3-wire interface write protocol is shown in Figure 6.
Figure 6 3-Wire SPI Compatible Interface 1. 2. 3. A[6:0] are Control Address Bits D[8:0] are Control Data Bits CSB is edge sensitive - the data is latched on the rising edge of CSB.
REGISTER READ-BACK
The read-only status registers can be read back via the SDO pin. To enable readback the READEN control register bit must be set. The status registers can then be read using one of two methods, selected by the CONTREAD register bit. With CONTREAD set, a single read-only register can be read back by writing to any other register or to a dummy register. The register to be read is determined by the READMUX[2:0] bits. When a write to the device is performed, the device will respond by returning the status byte in the register selected by the READMUX register bits. This 3-wire interface read back method using a write access is shown in.Figure 7
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REGISTER ADDRESS R52 READBACK 34h BIT 2:0 LABEL READMUX [2:0] DEFAULT 000
Production Data DESCRIPTION Determines which status register is to be read back: 000 = Error Register 001 = Channel Status Register 1 010 = Channel Status Register 2 011 = Channel Status Register 3 100 = Channel Status Register 4 101 = Channel Status Register 5 110 = S/PDIF Status Register Continuous Read Enable. 0 = Continuous read-back mode disabled 1 = Continuous read-back mode enabled Read-back mode enable. 0 = read-back mode disabled 1 = read-back mode enabled
3
CONTREAD
0
4
READEN
0
Table 9 Read-back Control Register The 3-wire interface readback protocol is shown below. Note that the SDO pin is tri-state unless CSB is held low; therefore CSB must be held low for the duration of the read.
Figure 7 3-Wire SPI Compatible Interface Continuous Readback If CONTREAD is set to zero, the user can read back directly from the register by writing to the register address, to which the device will respond with data. The protocol for this system is shown in Figure 8 below.
Figure 8 3-Wire SPI Compatible Control Interface Non-Continuous Readback
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2-WIRE SERIAL CONTROL MODE WITH READ-BACK
The WM8581 supports software control via a 2-wire read/write serial bus. Many devices can be controlled by the same bus, and each device has a unique 7-bit address (see Table 10). The controller indicates the start of data transfer with a high to low transition on SDIN while SCLK remains high. This indicates that a device address, DEVA(7:1), and data REG(6:0) will follow. All devices on the 2-wire bus respond to the start condition and shift in the next eight bits on SDIN (7-bit address + Read/Write bit, MSB first). If the device address received matches the address of the WM8581, the WM8581 responds by pulling SDIN low on the next clock pulse (ACK). If the address is not recognised, the WM8581 returns to the idle condition and wait for a new start condition and valid address. Once the WM8581 has acknowledged a correct address, the controller sends the first byte of control data (REGA(6:0), i.e. the WM8581 register address plus the first bit of register data). The WM8581 then acknowledges the first data byte by pulling SDIN low for one clock pulse. The controller then sends the second byte of control data (DIN(7:0), i.e. the remaining 8 bits of register data), and the WM8581 acknowledges by driving SDIN low. The transfer of data is complete when there is a low to high transition on SDIN while SCLK is high. After receiving a complete address and data sequence the WM8581 returns to the idle state and waits for another start condition. If a start or stop condition is detected out of sequence at any point during data transfer (i.e. SDIN changes while SCLK is high), the device returns to the idle condition.
Figure 9 2-Wire Serial Control Interface The WM8581 has two possible device addresses, which can be selected using the CSB pin. CSB STATE Low or Unconnected High DEVICE ADDRESS IN 2WIRE MODE 0011010x 0011011x ADDRESS (X=R/W BIT) X=0 X= 1 0x34 0x36 0x35 0x37
Table 10 2-Wire MPU Interface Address Selection
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REGISTER READBACK
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The WM8581 allows readback of certain registers in 2-wire mode. As in 3-wire mode, there are two methods of reading back data: continuous and non-continuous readback. Continuous readback is set by writing to the Readback Control register (see Table 9) to set READEN and CONTREAD to 1, and to set the READMUX bits to select the register to be read back. The status of this register can then be readback using the protocol shown in Figure 10.
Figure 10 2-Wire Continuous Readback If CONTREAD is set to zero, the user can read back directly from the register by writing to the register address, to which the device will respond with data. The protocol for this system is shown in Figure 11.
Figure 11 2-Wire Non-Continuous Readback
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SOFTWARE REGISTER RESET
Writing to register R53 will cause a register reset, resetting all register bits to their default values. Note that the WM8581 is powered down by default so writing to this register will power down the device.
REGISTER ADDRESS R53 RESET 35h
BIT 8:0
LABEL RESET
DEFAULT n/a
DESCRIPTION Writing any data value to this register will apply a reset to the device registers.
Table 11 Software Reset
DIGITAL AUDIO INTERFACES
Audio data is transferred to and from the WM8581 via the Digital Audio Interfaces. There are two Receive Audio Interfaces and two Transmit Audio Interfaces. The Digital Routing options for these interfaces are described on page 24. Control of the audio interfaces is described below.
MASTER AND SLAVE MODES
The Audio Interfaces require both a left-right-clock (LRCLK) and a bit-clock (BCLK). These can be supplied externally (slave mode) or they can be generated internally (master mode). When in master mode, the BCLKs and LRCLKs for an interface are output on the corresponding BCLK and LRCLK pins. By default, all interfaces operate in slave mode, but can operate in master mode by setting the PAIFTXMS, PAIFRXMS, SAIFMS register bits. In Hardware Control Mode, the PAIF Transmitter can operate in master mode by setting the SDI pin.
Figure 12 Slave Mode
Figure 13 Master Mode
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REGISTER ADDRESS R9 BIT 5 LABEL PAIFRX MS PAIFTX MS SAIFMS DEFAULT 0 DESCRIPTION
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PAIF Rx Master/Slave Mode Select: 0 = Slave Mode 1 = Master Mode PAIF Tx Master/Slave Mode Select: 0 = Slave Mode 1 = Master Mode SAIF Master/Slave Mode Select: 0 = Slave Mode 1 = Master Mode
5 R10 5 R11
0
0
Table 12 Master Mode Registers The frequency of a master mode LRCLK is dependant on system clock and the RATE register control bits. Table 27 shows the settings for common sample rates and system clock frequencies. SAMPLING RATE (LRCLK) 32kHz 44.1kHz 48kHz 88.2kHz 96kHz 176.4kHz 192kHz MCLK CLOCK FREQUENCY (MHZ) 128fs
RATE =000
192fs
RATE =001
256fs
RATE =010
384fs
RATE =011
512fs
RATE =100
768fs
RATE =101
1152fs
RATE =110
4.096 5.6448 6.144 11.2896 12.288 22.5792 24.576
6.144 8.467 9.216 16.9344 18.432 33.8688 36.864
8.192 11.2896 12.288 22.5792 24.576 Unavailable Unavailable
12.288 16.9344 18.432 33.8688 36.864
16.384 22.5792 24.576
24.576 33.8688 36.864
36.864 Unavailable Unavailable
Unavailable Unavailable Unavailable Unavailable Unavailable Unavailable
Unavailable Unavailable Unavailable Unavailable Unavailable Unavailable Unavailable Unavailable
Table 13 Master Mode MCLK / LRCLK Frequency Selection
REGISTER ADDRESS R9 PAIF 1 09h R10 PAIF 2 0Ah R11 SAIF 1 0Bh
BIT 2:0
LABEL PAIFRX_RATE [2:0] PAIFTX_RATE [2:0] SAIF_RATE [2:0]
DEFAULT 010
DESCRIPTION Master Mode MCLK/LRCLK Ratio: 000 = 128fs 001 = 192fs 010 = 256fs 011 = 384fs 100 = 512fs 101 = 768fs 110 = 1152fs
2:0
010
2:0
010
Table 14 Master Mode RATE Registers In master mode, the BCLKSEL register controls the number of BCLKs per LRCLK. If the MCLK:LRCLK ratio is 128fs or 192fs and BCLKSEL = 10, BCLKSEL is overwritten to be 128 BCLKs/LRCLK. Also, if BCLKSEL = 00, and LRCLK is 192fs or 1152fs, the generated BCLK has a mark-space ratio of 1:2.
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Production Data REGISTER ADDRESS R9 PAIF 1 09h R10 PAIF 2 0Ah R11 SAIF 1 0Bh BIT 4:3 LABEL PAIFRX_BCLKSEL [1:0] PAIFTX_BCLKSEL [1:0] SAIF_BCLKSEL [1:0] DEFAULT 00
WM8581
DESCRIPTION Master Mode BCLK Rate: 00 = 64 BCLKs per LRCLK 01 = 32 BCLKs per LRCLK 10 = 16 BCLKs per LRCLK 11 = BCLK = System Clock.
4:3
00
4:3
00
Table 15 Master Mode BCLK Control
AUDIO DATA FORMATS
Five popular interface formats are supported: * * * * * Left Justified mode Right Justified mode I2S mode DSP Mode A DSP Mode B
All five formats send the MSB first and support word lengths of 16, 20, 24 and 32 bits, with the exception of 32 bit right justified mode, which is not supported. Audio Data for each stereo channel is time multiplexed with the interface's Left-Right-Clock (LRCLK), indicating whether the left or right channel is present. The LRCLK is also used as a timing reference to indicate the beginning or end of the data words. In Left Justified, Right Justified and I2S modes, the minimum number of BCLKs per LRCLK period is 2 times the selected word length. LRCLK must be high for a minimum of BCLK periods equivalent to the audio word length, and low for minimum of the same number of BCLK periods. Any mark to space ratio on LRCLK is acceptable provided these requirements are met. In DSP modes A and B, left and right channels must be time multiplexed and input on the input data line on the Audio Interface. For the PAIF Receiver, all four left/right DAC channels are multiplexed on DIN1 (assuming DAC_SEL = 00). LRCLK is used as a frame synchronisation signal to identify the MSB of the first word. The minimum number of BCLKs per LRCLK period is eight times the selected word length. Any mark to space ratio is acceptable on LRCLK provided the rising edge is correctly positioned.
LEFT JUSTIFIED MODE
In Left Justified mode, the MSB of the input data is sampled by the WM8581 on the first rising edge of BCLK following a LRCLK transition. The MSB of the output data changes on the same falling edge of BCLK as LRCLK and may be sampled on the next rising edge of BCLK. LRCLK is high during the left samples and low during the right samples.
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Figure 14 Left Justified Mode Timing Diagram
RIGHT JUSTIFIED MODE
In Right Justified mode, the LSB of input data is sampled on the rising edge of BCLK preceding a LRCLK transition. The LSB of the output data changes on the falling edge of BCLK preceding a LRCLK transition, and may be sampled on the next rising edge of BCLK. LRCLKs are high during the left samples and low during the right samples.
Figure 15 Right Justified Mode Timing Diagram
I S MODE
In I2S mode, the MSB of DIN1/2/3/4 is sampled on the second rising edge of BCLK following a LRCLK transition. The MSB of the output data changes on the first falling edge of BCLK following an LRCLK transition, and may be sampled on the next rising edge of BCLK. LRCLKs are low during the left samples and high during the right samples.
2
Figure 16 I2S Mode Timing Diagram
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DSP MODE A
In DSP Mode A, the MSB of Channel 1 left data is sampled on the second rising edge of BCLK following a LRCLK rising edge. Channel 1 right data then follows. For the PAIF Receiver, Channels 2 , 3 and 4 follow as shown in Figure 17.
Figure 17 DSP Mode A Timing Diagram - PAIF Receiver Input Data For the SAIF receiver, only stereo information is processed.
Figure 18 DSP Mode A Timing Diagram - SAIF Receiver Input Data The MSB of the left channel of the output data changes on the first falling edge of BCLK following a low to high LRCLK transition and may be sampled on the rising edge of BCLK. The right channel data is contiguous with the left channel data.
Figure 19 DSP Mode A Timing Diagram - PAIF/SAIF Transmitter Data
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DSP MODE B
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In DSP Mode B, the MSB of Channel 1 left data is sampled on the first BCLK rising edge following a LRCLK rising edge. Channel 1 right data then follows. For the PAIF Receiver, Channels 2, 3 and 4 follow as shown in Figure 20.
Figure 20 DSP Mode B Timing Diagram - PAIF Receiver Input Data
Figure 21 DSP Mode B Timing Diagram - SAIF Receiver Input Data The MSB of the output data changes on the same falling edge of BCLK as the low to high LRCLK transition and may be sampled on the rising edge of BCLK. The right channel data is contiguous with the left channel data.
Figure 22 DSP Mode B Timing Diagram - PAIF/SAIF Transmitter Data
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The register bits controlling the audio interfaces are summarized below. Dynamically changing the audio data format may cause erroneous operation, and is not recommended. Interface timing is such that the input data and LRCLK are sampled on the rising edge of the interface BCLK. Output data changes on the falling edge of the interface BCLK. By setting the appropriate bit clock polarity control register bits, e.g. PAIFRXBCP, the polarity of BCLK may be reversed, allowing input data and LRCLK to be sampled on the falling edge of BCLK. Setting the bit clock polarity register for a transmit interface results in output data changing on the rising edge of BCLK. Similarly, the polarity of left/right clocks can be reversed by setting the appropriate left right polarity bits, e.g. PAIFRXLRP.
AUDIO INTERFACE CONTROL
REGISTER ADDRESS R12 PAIF 3 0Ch
BIT 1:0
LABEL PAIFRXFMT [1:0]
DEFAULT 10
DESCRIPTION PAIF Receiver Audio Data Format Select 11: DSP Format 2 10: I S Format 01: Left justified 00: Right justified PAIF Receiver Audio Data Word Length 11: 32 bits (see Note 1,2) 10: 24 bits 01: 20 bits 00: 16 bits In LJ/RJ/I2S modes 0 = LRCLK not inverted 1 = LRCLK inverted In DSP Format: 0 = DSP Mode A 1 = DSP Mode B PAIF Receiver BCLK polarity 0 = BCLK not inverted 1 = BCLK inverted PAIF Transmitter Audio Data Format Select 11: DSP Format 2 10: I S Format 01: Left justified 00: Right justified PAIF Transmitter Audio Data Word Length 11: 32 bits (see Note 1,2) 10: 24 bits 01: 20 bits 00: 16 bits In LJ/RJ/I2S modes 0 = LRCLK not inverted 1 = LRCLK inverted In DSP Format: 0 = DSP Mode A 1 = DSP Mode B
3:2
PAIFRXWL [1:0]
10
4
PAIFRXLRP
0
5
PAIFRXBCP
0
R13 PAIF 4 0Dh
1:0
PAIFTXFMT [1:0]
10
3:2
PAIFTXWL [1:0]
10
4
PAIFTXLRP
0
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REGISTER ADDRESS BIT 5 LABEL PAIFTXBCP DEFAULT 0
Production Data DESCRIPTION PAIF Receiver BCLK polarity 0 = BCLK not inverted 1 = BCLK inverted SAIF Audio Data Format Select 11: DSP Format 10: I2S Format 01: Left justified 00: Right justified SAIF Audio Data Word Length 11: 32 bits (see Note 1,2) 10: 24 bits 01: 20 bits 00: 16 bits In LJ/RJ/I S modes 0 = LRCLK not inverted 1 = LRCLK inverted In DSP Format: 0 = DSP Mode A 1 = DSP Mode B SAIF BCLK polarity 0 = BCLK not inverted 1 = BCLK inverted SAIF Enable 0 = SAIF disabled 1 = SAIF enabled
2
R14 SAIF 2 0Eh
1:0
SAIFFMT [1:0]
10
3:2
SAIFWL [1:0]
10
4
SAIFLRP
0
5
SAIFBCP
0
6
SAIF_EN
0
Table 16 Audio Interface Control Notes 1. Right Justified mode does not support 32-bit data. If word length xAIFxxWL=11b in Right Justified mode, the word length is forced to 24 bits. In all modes, the data is signed 2's complement. The digital filters internal signal paths process 24-bit data. If the device is programmed to receive 16 or 20 bit data, the device pads the unused LSBs with zeros. If the device is programmed into 32 bit mode, the 8 LSBs are ignored. 2. In 24 bit I2S mode, any data width of 24 bits or less is supported provided that LRCLK is high for a minimum of 24 BCLK cycles and low for a minimum of 24 BCLK cycles. If exactly 32 bit clocks occur in one full left/right clock period the interface will auto detect and configure a 16 bit data word length.
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DAC FEATURES
DAC INPUT CONTROL
The Primary Audio Interface Receiver has a separate input pin for each stereo DAC. Any input pin can be routed to any DAC using the DACSEL register bits. REGISTER ADDRESS R15 DAC CONTROL 1 0Fh BIT 1:0 3:2 5:4 7:6 LABEL DAC1SEL [1:0] DAC2SEL [1:0] DAC3SEL [1:0] DAC4SEL [1:0] DEFAULT 00 01 10 11 DESCRIPTION DAC digital input select 00 = DAC takes data from 01 = DAC takes data from 10 = DAC takes data from 11 = DAC takes data from DIN1 DIN2 DIN3 DIN4
Table 17 DAC Input Select Register
DAC OVERSAMPLING CONTROL
For sampling clock ratios of 256fs to 1152fs the DACs should be programmed to operate at 128 times oversampling rate. For sampling clock ratios of 128fs and 192fs, the DACs must be programmed to operate at 64 times oversampling rate. The DACOSR register bit selects between 128x and 64x oversampling. REGISTER ADDRESS R12 PAIF 3 0Ch BIT 6 LABEL DACOSR DEFAULT 0 DESCRIPTION DAC Oversampling Rate Control 0= 128x oversampling 1= 64x oversampling
Table 18 DAC Oversampling Register
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DAC OUTPUT CONTROL
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The DAC output control word determines how the left and right inputs to the audio interface are applied to the left and right DACs: REGISTER ADDRESS R16 DAC CONTROL 2 10h BIT 3:0 LABEL PL[3:0] DEFAULT 1001 PL[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Table 19 DAC Attenuation Register (PL) DESCRIPTION Left O/P Mute Left Right (L+R)/2 Mute Left Right (L+R)/2 Mute Left Right (L+R)/2 Mute Left Right (L+R)/2 Right O/P Mute Mute Mute Mute Left Left Left Left Right Right Right Right (L+R)/2 (L+R)/2 (L+R)/2 (L+R)/2
ZERO FLAG OUTPUT
Each DAC channel has a "zero detect circuit" which detects when 1024 consecutive zero samples have been input. Should both channels of a DAC indicate a zero-detect (or if either DACPD or DMUTE is set for that DAC), then the Zero Flag for that DAC is asserted. The DZFM register bits determine which Zero Flag is visible on the MUTE and GPO pins. REGISTER ADDRESS R16 DAC CONTROL 2 10h BIT 6:4 LABEL DZFM[2:0] DEFAULT 000 DESCRIPTION Selects the source for ZFLAG 000 - All DACs Zero Flag 001 - DAC1 Zero Flag 010 - DAC2 Zero Flag 011 - DAC3 Zero Flag 100 - DAC4 Zero Flag 101 - ZFLAG = 0 110 - ZFLAG = 0 111 - ZFLAG = 0
Table 20 DZFM Register
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INFINITE ZERO DETECT
Setting the IZD register bit will enable the internal Infinite Zero Detect function: REGISTER ADDRESS R16 DAC CONTROL 2 10h BIT 7 LABEL IZD DEFAULT 0 DESCRIPTION Infinite zero detection circuit control and automute control 0 = Infinite zero detect automute disabled 1 = Infinite zero detect automute enabled
Table 21 IZD Register With IZD enabled, applying 1024 consecutive zero input samples to a stereo input channel on any DAC will cause that stereo channel output to be muted. Mute will be removed as soon as either of those stereo channels receives a non-zero input.
DAC DIGITAL VOLUME CONTROL
The DAC volume may also be adjusted in the digital domain using independent digital attenuation control registers REGISTER ADDRESS R20 DIGITAL ATTENUATION DACL 1 14h R21 DIGITAL ATTENUATION DACR 1 15h R22 DIGITAL ATTENUATION DACL 2 16h R23 DIGITAL ATTENUATION DACR 2 17h R24 DIGITAL ATTENUATION DACL3 18h R25 DIGITAL ATTENUATION DACR3 19h BIT 7:0 8 LABEL LDA1[7:0] UPDATE DEFAULT 11111111 (0dB) Not latched DESCRIPTION Digital Attenuation control for DAC1 Left Channel (DACL1) in 0.5dB steps. See Table 23 Controls simultaneous update of all Attenuation Latches 0 = Store LDA1 in intermediate latch (no change to output) 1 = Apply LDA1 and update attenuation on all channels Digital Attenuation control for DAC1 Right Channel (DACR1) in 0.5dB steps. See Table 23 Controls simultaneous update of all Attenuation Latches 0 = Store RDA1 in intermediate latch (no change to output) 1 = Apply RDA1 and update attenuation on all channels. Digital Attenuation control for DAC2 Left Channel (DACL2) in 0.5dB steps. See Table 23 Controls simultaneous update of all Attenuation Latches 0 = Store LDA2 in intermediate latch (no change to output) 1 = Apply LDA2 and update attenuation on all channels. Digital Attenuation control for DAC2 Right Channel (DACR2) in 0.5dB steps. See Table 23 Controls simultaneous update of all Attenuation Latches 0 = Store RDA2 in intermediate latch (no change to output) 1 = Apply RDA2 and update attenuation on all channels. Digital Attenuation control for DAC3 Left Channel (DACL3) in 0.5dB steps. See Table 23 Controls simultaneous update of all Attenuation Latches 0 = Store LDA3 in intermediate latch (no change to output) 1 = Apply LDA3 and update attenuation on all channels. Digital Attenuation control for DAC3 Right Channel (DACR3) in 0.5dB steps. See Table 23 Controls simultaneous update of all Attenuation Latches 0 = Store RDA3 in intermediate latch (no change to output) 1 = Apply RDA3 and update attenuation on all channels.
7:0 8
RDA1[6:0] UPDATE
11111111 (0dB) Not latched
7:0 8
LDA2[7:0] UPDATE
11111111 (0dB) Not latched
7:0 8
RDA2[7:0] UPDATE
11111111 (0dB) Not latched
7:0 8
LDA3[7:0] UPDATE
11111111 (0dB) Not latched
7:0 8
RDA3[7:0] UPDATE
11111111 (0dB) Not latched
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REGISTER ADDRESS R26 DIGITAL ATTENUATION DACL4 1Ah R27 DIGITAL ATTENUATION DACR4 1Bh R28 MASTER DIGITAL ATTENUATION 1Ch BIT 7:0 8 LABEL RDA4[7:0] UPDATE DEFAULT 11111111 (0dB) Not latched DESCRIPTION
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Digital Attenuation control for DAC4 Left Channel (DACL4) in 0.5dB steps. See Table 23. Controls simultaneous update of all Attenuation Latches 0 = Store LDA4 in intermediate latch (no change to output) 1 = Apply LDA4 and update attenuation on all channels. Digital Attenuation control for DAC4 Right Channel (DACR4) in 0.5dB steps. See Table 23 Controls simultaneous update of all Attenuation Latches 0 = Store RDA4 in intermediate latch (no change to output) 1 = Apply RDA4 and update attenuation on all channels. Digital Attenuation control for all DAC channels in 0.5dB steps. See Table 23 Controls simultaneous update of all Attenuation Latches 0 = Store gain in intermediate latch (no change to output) 1 = Apply gain and update attenuation on all channels.
7:0 8
MASTDA[7:0] UPDATE
11111111 (0dB) Not latched
7:0 8
MASTDA[7:0] UPDATE
11111111 (0dB) Not latched
Table 22 Digital Attenuation Registers Note: The volume update circuit of the WM8581 has two sets of registers; LDAx and RDAx. These can be accessed individually, or simultaneously by writing to MASTDA - Master Digital Attenuation. Writing to MASTDA will overwrite the contents of LDAx and RDAx. L/RDAx[7:0] 00(hex) 01(hex) : : : FE(hex) FF(hex) ATTENUATION LEVEL - dB (mute) -127.5dB : : : -0.5dB 0dB
Table 23 Digital Volume Control Gain Levels Setting the DACATC register bit causes the left channel attenuation settings to be applied to both left and right channel DACs from the next audio input sample. No update to the attenuation registers is required for DACATC to take effect. REGISTER ADDRESS R19 DAC CONTROL 5 13h BIT 6 LABEL DACATC DEFAULT 0 DESCRIPTION Attenuator Control 0 = All DACs use attenuations as programmed. 1 = Right channel DACs use corresponding left DAC attenuations
Table 24 DAC Attenuation Register The digital volume control also incorporates a zero cross detect circuit which detects a transition through the zero point before updating the digital volume control with the new volume. This mechanism helps prevents pops and clicks during volume transitions, and is enabled by control bit DZCEN.
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Production Data REGISTER ADDRESS R19 DAC CONTROL 5 13h BIT 5 LABEL DZCEN DEFAULT 0
WM8581
DESCRIPTION DAC Digital Volume Zero Cross Enable 0 = Zero Cross detect disabled 1 = Zero Cross detect enabled Table 25 Digital Zero Cross Register
MUTE MODES
The WM8581 has individual mutes for each of the four DAC channels. Setting DMUTE for a channel will apply a `soft-mute' to the input of the digital filters for that channel. DMUTE[0] mutes DAC1 channel, DMUTE[1] mutes DAC2 channel, DMUTE[2] mutes DAC3 channel and DMUTE[3] mutes DAC4 channel. Setting the MUTEALL register bit will apply a `soft-mute' to the input of all the DAC digital filters. The MUTE pin can also be used to apply soft-mute to the DAC selected by the DZFM register bits. However, if the MPDENB register bit is set, the MUTE pin will activate a soft-mute for all DACs. The interaction of the various mute controls is shown in Figure 23.
DMUTE(3:0) PL(3:0) MUTEALL
DACPD(3:0) DZFM (2:0)
DAC_SRC[1:0] = 00 PCM_N or AUDIO_N = 1
MUTE (register) Decode
MPDENB
MUTE (pin) DZFM Selector Channel 1 Softmute
Channel 2 Softmute
Channel 3 Softmute DAC1 i/p DAC2 i/p DAC3 i/p DAC4 i/p 1024 Zeros Detect zflag1 zflag2 zflag3 zflag4 DAC_SRC[1:0] = 00 UNLOCK = 1 Channel 4 Softmute
Channel 1 Analogue Mute Channel 2 Analogue Mute Channel 3 Analogue Mute Channel 4 Analogue Mute
IZD
Decode (register) Volume LDAx/RDAx (Digital volume)
Figure 23 Mute Circuit Diagram
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REGISTER ADDRESS R19 DAC CONTROL 5 13h BIT 3:0 LABEL DMUTE[3:0] DEFAULT 0000
Production Data DESCRIPTION DAC channel soft mute enables: DMUTE[0] = 1, enable softmute on DAC1. DMUTE[1] = 1, enable softmute on DAC2. DMUTE[2] = 1, enable softmute on DAC3. DMUTE[3] = 1, enable softmute on DAC4. DAC channel master soft mute. Mutes all DAC channels: 0 = disable soft-mute on all DACs. 1 = enable soft-mute on all DACs. MUTE pin decode enable: 0 = MUTE activates soft-mute on DAC selected by DZFM 1 = MUTE activates softmute on all DACs
4
MUTEALL
0
7
MPDENB
0
Table 26 Mute Registers
1.5 1 0.5 0 -0.5 -1 -1.5 -2 -2.5 0 0.001 0.002 0.003 Time(s) 0.004 0.005 0.006
Figure 24 Application and Release of Mute Figure 24 shows the application and release of MUTE whilst a full amplitude sinusoid is being played at 48kHz sampling rate. When MUTE (lower trace) is asserted, the output (upper trace) begins to decay exponentially from the DC level of the last input sample. The output will decay towards VMID with a time constant of approximately 64 input samples. If MUTE is applied to all channels for 1024 or more input samples the DAC will be muted if IZD is set. When MUTE is de-asserted, the output will restart immediately from the current input sample. All other means of muting the DAC channels will cause a much more abrupt muting of the output.
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DE-EMPHASIS MODE
A digital de-emphasis filter may be applied to each DAC channel. The de-emphasis filter for each stereo channel is enabled under the control of DEEMP[3:0]. DEEMP[0] enables the de-emphasis filter for DAC 1, DEEMP[1] enables the de-emphasis filter for DAC 2, DEEMP[2] enables the deemphasis filter for DAC 3 and DEEMP[3] enables the de-emphasis filter for DAC 4. REGISTER ADDRESS R17 DAC CONTROL 3 11h BIT 3:0 LABEL DEEMP[3:0] DEFAULT 0000 DESCRIPTION De-emphasis mode select: DEEMP[0] = 1, enable Deemphasis on DAC1. DEEMP[1] = 1, enable Deemphasis on DAC2. DEEMP[2] = 1, enable Deemphasis on DAC3. DEEMP[3] = 1, enable Deemphasis on DAC4. 0 = De-emphasis controlled by DEEMP[3:0] 1 = De-emphasis enabled on all DACs
4
DEEMPALL
0
Table 27 De-emphasis Register Refer to, Figure 41, Figure 42, Figure 43 and Figure 44 for details of the De-Emphasis modes at different sample rates.
DAC OUTPUT PHASE
The DAC Phase control word determines whether the output of each DAC is non-inverted or inverted REGISTER ADDRESS R18 DAC CONTROL 4 12h BIT 7:0 LABEL PHASE [7:0] DEFAULT 11111111 DESCRIPTION Controls phase of DAC outputs 0 = inverted 1 = non-inverted PHASE[0] = 0 inverts phase of DAC1L output PHASE[1] = 0 inverts phase of DAC1R output PHASE[2] = 0 inverts phase of DAC2L output PHASE[3] = 0 inverts phase of DAC2R output PHASE[4] = 0 inverts phase of DAC3L output PHASE[5] = 0 inverts phase of DAC3R output PHASE[6] = 0 inverts phase of DAC4L output PHASE[7] = 0 inverts phase of DAC4R output
Table 28 DAC Output Phase Register
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ADC FEATURES
ADC HIGH-PASS FILTER DISABLE
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The ADC digital filters incorporate a digital high-pass filter. By default, this is enabled but can be disabled by setting the ADCHPD register bit to 1. This allows the input to the ADC to be DC coupled. REGISTER ADDRESS R29 ADC CONTROL 1 1Dh BIT 4 LABEL ADCHPD DEFAULT 0 DESCRIPTION ADC high-pass filter disable 0 = high-pass filter enabled 1 = high-pass filter disabled
Table 29 ADC Functions Register
ADC OVERSAMPLING RATE SELECT
The internal ADC signal processing operates at an oversampling rate of 128fs for all MCLK:LRCLK ratios. The exception to this is for operation with a 128fs or 192fs master clock, where the internal oversampling rate of the ADC is 64fs. For ADC operation at 96kHz in 256fs or 384fs mode it is recommended that the user set the ADCOSR bit. This changes the ADC signal processing oversampling rate from 128fs to 64fs. Similarly, for ADC operation at 192kHz in 128fs or 192fs mode it is recommended that the user set the ADCOSR bit to change the oversampling rate from 64fs to 32fs. REGISTER ADDRESS R29 ADC CONTROL 1 1Dh BIT 3 LABEL ADCOSR DEFAULT 0 DESCRIPTION ADC oversample rate select 0 = 128/64x oversampling 1 = 64/32x oversampling
Table 30 ADC Functions Register
ADC MUTE
As with the DAC, each ADC channel also has a mute control bit, which mutes the inputs to the ADC. REGISTER ADDRESS R29 ADC CONTROL 1 1Dh BIT 0 LABEL AMUTEL DEFAULT 0 DESCRIPTION ADC Mute select 0 : Normal Operation 1: mute ADC left ADC Mute select 0 : Normal Operation 1: mute ADC right ADC Mute select 0 : Normal Operation 1: mute both ADC channels
1
AMUTER
0
2
AMUTEALL
0
Table 31 ADC Mute Register
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DIGITAL ROUTING OPTIONS
The WM8581 has extremely flexible digital interface routing options, which are illustrated in Figure 25. It has a S/PDIF Receiver, S/PDIF Transmitter, four Stereo DACs, a Stereo ADC, a Primary Audio Interface and a Secondary Audio Interface. Each DAC has its own digital input pin DIN1/2/3/4. Internal multiplexers in the Primary Audio Interface Receiver allow the data received on any DIN pin to be routed to any DAC. Any DIN pin routed to DAC1 can also be routed to the S/PDIF transmitter and Secondary Audio Interface Transmitter. DAC1 may also be used to convert received S/PDIF data, or data received from the Secondary Audio Interface. DACs 2-4 take data only from the Primary Audio Interface. The Audio Interfaces can also output ADC data or received S/PDIF data. The S/PDIF transmitter can output S/PDIF received data, ADC data, or data from either Audio Interface.
Figure 25 Digital Routing
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The registers described below configure the digital routing options. REGISTER ADDRESS R12 BIT 8:7 LABEL DAC_SRC [1:0] DEFAULT 11
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DESCRIPTION DAC1 Source: 00 = S/PDIF received data. 10 = SAIF Rx data 11 = PAIF Rx data Note: When DAC_SRC = 00, DAC2/3/4 may be turned off, depending on RX2DAC_MODE. Primary Audio Interface Tx Source: 00 = S/PDIF received data. 01 = ADC digital output data. 10 = SAIF Rx data Secondary Audio Interface Tx Source: 00 = S/PDIF received data. 01 = ADC digital output data. 11 = PAIF Rx data S/PDIF Transmitter Data Source. 00 = S/PDIF received data(`thrupath') 01 = ADC digital output data. 10 = SAIF Rx data 11 = PAIF Rx data S/PDIF Thru Mode Control 0 = SPDIFOP pin sources output of S/PDIF Tx 1 = SPDIFOP pins sources output of S/PDIF IN Mux
R13
8:7
PAIFTX_SRC [1:0]
01
R14
8:7
SAIFTX_SRC [1:0]
00
R30
1:0
TXSRC [1:0]
00
3
REAL_THRU
0
Table 32 Interface Source Select Registers
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WM8581
To accompany the flexible digital routing options, the WM8581 offers a clock configuration scheme for each interface. By default, the user can choose the interface clock from MCLK, ADCMCLK, PLLACLK or PLLBCLK, with some restrictions which are autoconfigured. For example, if the S/PDIF receiver is routed to the DAC, appropriate interface clocks are autoconfigured. These are described in the following sections. For some interfaces, the rate can be controlled either by external LRCLK (slave mode), internal LRCLK (master mode) or by control register. The available options are described below. It is possible to override the autoconfiguration (setting CLKSEL_MAN = bit 6 of Register 8 to a 1), allowing the user to manually select any available clock for any interface using the appropriate CLKSEL register bits.
CLOCK SELECTION
DAC INTERFACE
The DAC_CLKSEL register selects the DAC clock source from MCLK, PLLACLK or PLLBCLK. If the digital routing has been set such that the DAC1 is sourcing the S/PDIF Receiver, then PLLACLK is automatically selected, and DACs 2/3/4 are powered down by default. With RX2DAC_MODE set, DAC1 sources the S/PDIF receiver and DACs 2,3 and 4 source the PAIF (and hence are not powered down). The PAIFRX_LRCLK determines the sampling rate, so the S/PDIF sampling rate must be synchronised with PAIF_LRCLK. Also, use of the S/PDIF receiver means that PLLACLK and PLLBCLK are not available, and the MCLK applied to the DACs must be at a standard audio rate. The rate at which the DACs operate is determined by the DAC Rate module, divided down from the MCLK signal. It calculates the rate based on the digital routing setup, and selects between 128/192/256/384/512/768/1152fs. When sourcing from the PAIF Receiver, PAIFRX_LRCLK (internal or external) is used in the rate calculation. When sourcing from the SAIF Receiver, SAIF_LRCLK (internal or external) is used in the rate calculation. When DAC1 is sourcing directly from the S/PDIF receiver, the sub-frame clock, SFRM_CLK, is used in the rate calculation. However this can be changed by setting the RX2DAC_MODE register bit, allowing the PAIF_LRCLK to determine the sampling rate.
Figure 26 DAC Clock Selection REGISTER ADDRESS R8 BIT 1:0 LABEL DAC_CLKSEL DEFAULT 00 DESCRIPTION DAC clock source 00 = MCLK pin 01 = PLLACLK 10 = PLLBCLK 11 = MCLK pin
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R15 8
RX2DAC_MODE
Production Data 0 DAC Rate and Power down control (only valid when DAC_SRC = 00) 0 = SFRM_CLK determines rate, DACs 2/3/4 powered down 1 = PAIFRX_LRCLK determines rate, DACs 2/3/4 source PAIFRX
Table 33 DAC Clock Control
ADC INTERFACE
The ADC_CLKSEL register selects the ADC clock source from ADCMCLK, PLLACLK, PLLBCLK, or ADCMCLK. However, if the S/PDIF receiver is powered up, the PLLACLK and PLLBCLK are invalid for ADC operation, so the choice is limited to ADCMCLK (default) or MCLK. The rate that the ADC operates at is determined by the ADC Rate module. It calculates the rate based on the digital routing setup. If the ADC is sourced by the PAIF Transmitter, PAIFTX_LRCLK is used in the rate calculation. If the ADC is sourced by the SAIF Transmitter (and PAIF Transmitter has another source), SAIF_LRCLK is used in the rate calculation. If the S/PDIF Transmitter (only) is sourcing the ADC, then the rate is set by the ADC_RATE register bits. The ADC clock source can be independent from the DACs and PLLs, however for optimum performance, it is recommended that where possible, clock sources on the WM8581 are synchronous. Performance may be degraded if this condition is not met.
Figure 27 ADC Clock Selection
REGISTER ADDRESS R8
BIT 3:2
LABEL ADC_CLKSEL
DEFAULT 00
DESCRIPTION ADC clock source 00 = ADCMLCK pin 01 = PLLACLK 10 = PLLBCLK 11 = MCLK pin ADC Rate Control (only used when the S/PDIF Tx is the only interface sourcing the ADC) 000 = 128fs 001 = 192fs 010 = 256fs 011 = 384fs 100 = 512fs 101 = 768fs 110 = 1152fs
R29
7:5
ADCRATE[2:0]
010
Table 34 ADC Clock Control
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S/PDIF INTERFACES
The TX_CLKSEL register selects the clock for the S/PDIF Transmitter from ADCMCLK, PLLACLK, PLLBCLK, or MCLK. The S/PDIF Receiver only uses PLLACLK. If the digital routing has been configured such that the S/PDIF Transmitter is sourcing the S/PDIF Receiver, then PLLACLK is automatically selected. The rate that the S/PDIF Transmitter operates at is determined by the S/PDIF Tx Rate module. It calculates the rate based on the digital routing setup. When sourcing from the S/PDIF Receiver, the SFRM_CLK is used in the rate calculation. When sourcing from the PAIF Receiver, PAIFRX_LRCLK is used in the rate calculation. When sourcing from the SAIF Receiver, SAIFRX_LRCLK is used in the rate calculation. When sourcing the ADC, the rate is determined by either the PAIFTX_LRCLK (if the PAIF Tx also sources the ADC) or the ADC_RATE register.
Figure 28 S/PDIF Clock Selection REGISTER ADDRESS R8 BIT 5:4 LABEL TX_CLKSEL DEFAULT 01 DESCRIPTION S/PDIF TX clock source 00 = ADCMLCK pin 01 = PLLACLK 10 = PLLBCLK 11 = MCLK pin
Table 35 S/PDIF Transmitter Clock Control
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PRIMARY AUDIO INTERFACE RECEIVER (PAIF RX)
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The PAIF Receiver requires a left-right-clock (LRCLK) and a bit-clock (BCLK). These can be supplied externally (slave mode) or they can be generated internally by the WM8581 (master mode). The master mode LRCLK/BCLK are created by the Master Mode Clock Gen module. The control of this module is described on page 34. The clock supplied to this module is selected by the PAIFRXMS_CLKSEL register and can be MCLK, PLLACLK, or PLLBCLK.
Figure 29 PAIF Receiver Clock Selection REGISTER ADDRESS R9 BIT 7:6 LABEL PAIFRXMS_ CLKSEL DEFAULT 00 DESCRIPTION PAIFRX Master Mode clock source 00 = MCLK pin 01 = PLLACLK 10 = PLLBCLK 11 = MCLK pin
Table 36 PAIF Receiver Master Mode Clock Control
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PRIMARY AUDIO INTERFACE TRANSMITTER (PAIF TX)
The PAIF Transmitter requires a left-right-clock (LRCLK) and a bit-clock (BCLK). These can be supplied externally (slave mode) or they can be generated internally by the WM8581 (master mode). The master mode LRCLK/BCLK are created by the Master Mode Clock Gen module. The control of this module is described on page 34. The clock supplied to this module can be ADCMCLK, PLLACLK, PLLBCLK, or MCLK and is selected by the internal signal paiftxms_clksel'. If the PAIF Transmitter is sourcing the S/PDIF Receiver, it is recommended that the interface operate in master mode. For this path, paiftxms_clksel selects PLLACLK. For all other digital routing options, paiftxms_clksel automatically selects whichever clock the adc_clk is using. If in slave mode, and adc_clk is set to be MCLK, then the PAIFRX_BCLK is used as the BCLK for the PAIF Transmitter.
Figure 30 PAIF Transmitter Clock Selection
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SECONDARY AUDIO INTERFACES (SAIF RX AND SAIF TX)
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The Transmit and Receive sides of the Secondary Audio Interface share a common LRCLK and a common BCLK. These can be supplied externally (slave mode) or they can be generated internally by the WM8581 (master mode). The master mode LRCLK/BCLK are created by the Master Mode Clock Gen module. The control of this module is described on page 34. The clock supplied to this module can be ADCMCLK, PLLACLK, PLLBCLK, or MCLK and is selected using the SAIFMS_CLKSEL register. If the digital routing has been configured such that the SAIF Transmitter is sourcing the S/PDIF Receiver, then PLLACLK is automatically selected, and it is recommended that the interface operate in master mode. However, if the SAIF Transmitter sources something other than the S/PDIF Receiver, and the S/PDIF Receiver is powered up, the PLLACLK and PLLBCLK are invalid for SAIF operation, so the choice is limited to ADCMCLK (default) or MCLK.
Figure 31 SAIF Clock Selection
REGISTER ADDRESS R11
BIT 7:6
LABEL SAIFMS_ CLKSEL
DEFAULT 11
DESCRIPTION SAIF Master Mode clock source 00 = ADCMCLK pin 01 = PLLACLK 10 = PLLBCLK 11 = MCLK pin
Table 37 SAIF Master Mode Clock Control
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MANUAL CLOCK SELECTION
It is possible to override all default clocking configuration restrictions by setting CLKSEL_MAN. When CLKSEL_MAN is set, default clocking configurations such as automatic selection of PLLACLK for DAC1 when DACSRC=00 (S/PDIF received data) are not applied. Instead, clock selection is determined only by the relevant CLK_SEL register. REGISTER ADDRESS R8 CLKSEL 08h BIT 6 LABEL CLKSEL_MAN DEFAULT 0 DESCRIPTION Clock selection auto-configuration override 0 = auto-configuration enabled, clock configuration follows restrictions described in page 43 to page 48. 1 = auto-configuration disabled, clock configuration follows relevant CLKSEL bits in R8 to R11.
Table 38 Manual Clock Selection
PHASE-LOCKED LOOPS AND S/PDIF CLOCKING (SOFTWARE MODE)
The WM8581 is equipped with two independent phase-locked loop clock generators and a comprehensive clocking scheme which provides maximum flexibility and function and many configurable routing possibilities for the user in software mode. An overview of the software mode clocking scheme is shown in Figure 32.
Figure 32 PLL and Clock Select Circuit
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OSCILLATOR
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The function of the oscillator is to generate the OSCCLK oscillator clock signal. This signal may be used as: * * * The clock source for the PLLs. A selectable clock source for the MCLK pin, when the pin is configured as an output. A selectable clock source for the CLKOUT pin, when enabled.
Whenever the PLLs or the S/PDIF receiver is enabled, the OSCCLK signal must be present to enable the PLLs to generate the necessary clock signals. The oscillator uses a Pierce type oscillator drive circuit. This circuit requires an external crystal and appropriate external loading capacitors. The oscillator circuit contains a bias generator within the WM8581 and hence an external bias resistor is not required. Crystal frequencies between 10 and 14.4MHz or 16.28MHz and 27MHz can be used in software mode. In this case the oscillator XOUT must be powered up using the OSCPD bit. The recommended circuit is shown in the recommended components diagram, please refer to Figure 49. Alternatively, an external CMOS compatible clock signal can be applied to the XIN pin in the absence of a crystal. This is not recommended when using the PLL as the PLL requires a jitter-free OSCCLK signal for optimum performance. In this case the oscillator XOUT can be powered down using the OSCPD bit. The oscillator XOUT pin has one control bit as shown in Table 39. REGISTER ADDRESS R51 PWRDN 2 33h BIT 0 LABEL OSCPD DEFAULT 0 DESCRIPTION Oscillator XOUT Power Down 0 = Power Up XOUT (crystal mode) 1 = Power Down XOUT (CMOS clock input mode)
Table 39 Oscillator Control PHASE-LOCKED LOOP (PLL) The WM8581 has two on-chip phase-locked loop (PLL) circuits which can be used to synthesise two independent clock signals (PLLACLK and PLLBCLK) from the external oscillator clock. The PLLs can be used to: * * * * * Generate clocks necessary for the S/PDIF receiver to lock on to and recover S/PDIF data from an incoming S/PDIF data stream. Generate clocks which may be used to drive the MCLK and/or CLKOUT pins. Generate clocks which may be used by the S/PDIF transmitter to encode and transmit a S/PDIF data stream. Generate clocks which may be used as the master clock source for the the ADC and DACs. Generate clocks which may be used by the master mode clock generator to generate the BCLK and LRCLK signals for the digital audio interfaces.
The PLLs can be enabled or disabled using the register bits shown in Table 40. REGISTER ADDRESS R51 PWRDN 2 33h BIT 1 2 LABEL PLLAPD PLLBPD DEFAULT 1 1 DESCRIPTION PLL Power Down Control 0 = Power Up PLL 1 = Power Down PLL
Table 40 PLL Power Down Control
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Production Data The PLLs have two modes of operation: * PLL S/PDIF Receive Mode (Selected if S/PDIF Receiver Enabled)
WM8581
In S/PDIF receive mode, PLLA is automatically controlled by the S/PDIF receiver to allow the receiver to use PLLA to track and lock on to the incoming S/PDIF data stream. In this case, CLK1 is automatically maintained at a constant frequency of 256fs relative to the sample rate of the recovered S/PDIF stream. PLLB must be configured to produce CLK2, a specific reference clock for the S/PDIF receiver. PLLACLK may be used as a 256fs or 128fs (selectable - refer to Table 45) master clock source when in S/PDIF receiver mode. PLLBCLK is not available and must not be selected as the clock source for any internal function when the S/PDIF receiver is enabled. If the sample frequency of the incoming stream is changed and PLLA is forced to unlock in order to track to the new sample frequency, the PLLACLK signal will be stopped until the S/PDIF receiver has locked to the incoming stream at the new sample frequency. If the incoming S/PDIF stream stops, the PLLA_ N and PLLA_K values will be frozen and the PLLACLK will continue at the frequency set by the last recovered S/PDIF stream. Refer to Table 41 and Table 43 for details of the registers available for configuration in this mode. Refer to the S/PDIF Receive Mode Clocking section on page 56 for full details. * PLL User Mode (Selected if S/PDIF Receiver Disabled)
In user mode, the user has full control over the function and operation of both PLLA and PLLB. In this mode, the user can accurately specify the PLL N and K multiplier values and the pre and postscale divider values and can hence fully control the generated clock frequencies. Refer to Table 41 and Table 43 for details of the registers available for configuration in this mode. REGISTER ADDRESS R0 PLLA 1/ DEVID1 00h R1 PLLA 2/ DEVID2 01h R2 PLLA 3/ DEVREV 02h BIT 8:0 LABEL PLLA_K[8:0] DEFAULT 100100001 DESCRIPTION Fractional (K) part of PLLA frequency ratio (R) I. Value K is one 22-digit binary number spread over registers R0, R1 and R2 as shown. Reading from these registers will return the device ID. R0 returns 10000001 = 81h R1 returns 10000101 = 85h Device ID readback is not possible in continuous readback mode (CONTREAD=1). 7:4 PLLA_N[3:0] 0111 Integer (N) part of PLLA frequency ratio(R)II. Use values in the range 5 PLLA_N 13 as close as possible to 8. Reading from this register will return the device revision number. R4 PLLB 1 04h R5 PLLB 2 05h R6 PLLB 3 8:0 PLLB_K[8:0] 100100001 Fractional (K) part of PLLB frequency ratioII(R). Value K is one 22-digit binary number spread over registers R4, R5 and R6 as shown. Note: PLLB_K must be set to specific values when the S/PDIF receiver is used. Refer to S/PDIF Receive Mode Clocking section for details. PD Rev 4.0 April 2007 51
8:0
PLLA_K[17:9]
101111110
3:0
PLLA_K[21:18]
1101
8:0
PLLB_K[17:9]
101111110
3:0
PLLB_K[21:18]
1101
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REGISTER ADDRESS 06h BIT 7:4 LABEL PLL_N[3:0] DEFAULT 0111
Production Data DESCRIPTION Integer (N) part of PLLB frequency ratio (R). Use values in the range 5 PLLB_N 13 as close as possible to 8 Note: PLLB_N must be set to specific values when the S/PDIF receiver is used. Refer to S/PDIF Receive Mode Clocking section for details.
Table 41 User Mode PLL_K and PLL_N Multiplier Control
Parameter PRESCALE_A PRESCALE_B PLLA_N PLLA_K PLLB_N PLLB_K FREQMODE_A FREQMODE_B POSTSCALE_A POSTSCALE_B
PLL User Mode Manual Manual Manual Manual Manual Manual Manual Manual Manual Manual
PLL S/PDIF Receiver Mode Write PRESCALE_B Value Configure Specified PLLB Frequency Automatically Controlled Automatically Controlled Configure Specified PLLB Frequency Configure Specified PLLB Frequency Automatically Controlled Not Used 256fs/128fs PLLACLK Select Not Used
Table 42 PLL Control Register Function in PLL User and PLL S/PDIF Receiver Modes PLL CONFIGURATION The PLLs perform a configurable frequency multiplication of the input clock signal (f1). The multiplication factor of the PLL (denoted by `R') is variable and is defined by the relationship: R = (f2 / f1). The multiplication factor for each PLL is set using register bits PLLx_N and PLLx_K (refer to Table 41). The multiplication effect of both the N and K multipliers are additive (i.e. if N is configured to provide a multiplication factor of 8 and K is configured to provide a multiplication factor of 0.192, the overall multiplication factor is 8 + 0.192 = 8.192). In order to choose and configure the correct values for PLLx_N and PLLx_K, multiplication factor R must first be calculated. Once value R is calculated, the value of PLLx_N is the integer (whole number) value of R, ignoring all digits to the right of the decimal point. For example, if R is calculated to be 8.196523, PLL_N is simply 8. Once PLLx_N is calculated, the PLLx_K value is simply the integer value of (222 (R-PLLx_N)). For 22 example, if R is 8.196523 and PLLx_N is 8, PLLx_K is therefore (2 (8.196523-8)), which is 824277 (ignoring all digits to the right of the decimal point). Note: the PLLs are designed to operate with best performance (shortest lock time and optimum stability) when f2 is between 90 and 100MHz and PLLx_N is 8. However, acceptable PLLx_N values lie in the range 5 PLLx_N 13. Each PLL has an output divider to allow the f2 clock signal to be divided to a frequency suitable for use as the source for the MCLK and CLKOUT outputs, the S/PDIF transmitter and the internal ADC and DACs. The divider output is configurable and is set by the FREQMODE_A or FREQMODE_B bits in conjunction with the POSTSCALE_A and POSTSCALE_B bits. Each PLL is also equipped with a pre-scale divider which offers frequency divide by one or two before the OSCCLK signal is input into the PLL. Please refer to Table 43 for details.
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REGISTER ADDRESS R3 PLLA 4 03h R7 PLLB 4 07h BIT 0 LABEL PRESCALE_A DEFAULT 0 DESCRIPTION PLL Pre-scale Divider Select 0 = Divide by 1 (PLL input clock = oscillator clock) 1 = Divide by 2 (PLL input clock = oscillator clock / 2) Note: PRESCALE_A must be set to the same value as PRESCALE_B in PLL S/PDIF receiver mode. PLL Output Divider Select PLL S/PDIF Receiver Mode FREQMODE_A is automatically controlled. FREQMODE_B is not used. PLL User Mode Used in conjunction with the POSTSCALE_x bits. Refer to Table 44. PLL Post-scale Divider Select PLL S/PDIF Receiver Mode POSTSCALE_A is used to configure a 256fs or 128fs PLLACLK, POSTSCALE_B is not used. Refer to Table 45. PLL User Mode Used in conjunction with the FREQMODE_x bits. Refer to Table 44.
0
PRESCALE_B
0
R3 PLLA 4 03h R7 PLLB 4 07h
4:3
FREQMODE_A [1:0] FREQMODE_B [1:0]
10
4:3
10
R3 PLLA 4 03h R7 PLLB 4 07h
1
POSTSCALE_A
0
1
POSTSCALE_B
0
Table 43 Pre and Post PLL Clock Divider Control FREQMODE_x[1:0] f2 TO PLLxCLK DIVISION FACTOR POSTSCALE_x 0 00 01 10 11 /2 /4 /8 /12 1 /4 /8 /16 /24
Table 44 PLL User Mode Clock Divider Configuration
POSTSCALE_A 0 1
PLLACLK FREQUENCY 256fs 128fs
Table 45 PLL S/PDIF Receiver Mode Clock Divider Configuration
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PLL CONFIGURATION EXAMPLE
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Consider the situation where the oscillator clock (OSCCLK) input frequency is fixed at 12MHz and the required PLLBCLK frequency is 12.288MHz. 1. Calculate the f2, FREQMODE_B and POSTSCALE_B Values
The PLL is designed to operate with best performance when the f2 clock is between 90 and 100MHz. The necessary PLLBCLK frequency is 12.288MHz. Choose POSTSCALE_B and FREQMODE_B values to set the f2 frequency in the range of 90 to 100MHz. In this case, the default values (POSTSCALE_B = 0 and FREQMODE_B[1:0] = 10) will configure the f2 to PLLBCLK divider as 8 and hence will set the f2 frequency at 98.304MHz; this value is within the 90 to 100MHz range and is hence acceptable. * * * 2. POSTSCALE_B = 0 FREQMODE_B [1:0] = 10b f2 = 98.304MHz
Calculate R Value
Using the relationship: R = (f2 / f1), the value of R can be calculated. * * * 3. R = (f2 / f1) R = (98.304 / 12) R = 8.192
Calculate PLLB_N Value
The value of PLLB_N is the integer (whole number) value of R, ignoring all digits to the right of the decimal point. In this case, R is 8.192, hence PLLB_N is 8. 4. Calculate PLL_K Value
The PLLB_K value is simply the integer value of (222 (R-PLLB_N)). * * * PLLB_K = integer part of (2
22
x (8.192 - 8))
PLLB_K = integer part of 805306.368 PLLB_K = 805306 (decimal) / C49BA (hex)
A number of example configurations are shown in Table 46. Many other configurations are possible; Table 46 shows only a small number of valid possibilities. As both PLLs are identical, the same configuration procedure applies for both.
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F1 (MHz) F2 (MHz) R PLLx_N (Hex) PLLx_K (Hex) FREQ MODE_x [1:0] 00 01 01 10 10 11 11 00 01 01 10 10 11 11 00 01 00 01 POSTSCALE_x PLLxCLK (MHz)
OSC CLK (MHz) 12 12 12 12 12 12 12 24 24 24 24 24 24 24 27 27 27 27
PRESCALE _x 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1
12 12 12 12 12 12 12 12 12 12 12 12 12 12 13.5 13.5 13.5 13.5
98.304 98.304 98.304 98.304 98.304 98.304 98.304 90.3168 90.3168 90.3168 90.3168 90.3168 90.3168 90.3168 98.304 98.304 90.3168 90.3168
8.192 8.192 8.192 8.192 8.192 8.192 8.192 7.5264 7.5264 7.5264 7.5264 7.5264 7.5264 7.5264 7.2818 7.2818 6.6901 6.6901
8 8 8 8 8 8 8 7 7 7 7 7 7 7 7 7 6 6
C49BA C49BA C49BA C49BA C49BA C49BA C49BA 21B089 21B089 21B089 21B089 21B089 21B089 21B089 1208A5 1208A5 2C2B24 2C2B24
1 0 1 0 1 0 1 1 0 1 0 1 0 1 1 1 1 1
24.576 24.576 12.288 12.288 6.144 8.192 4.096 22.5792 22.5792 11.2896 11.2896 5.6448 7.5264 3.7632 24.576 12.288 22.5792 11.2896
Table 46 User Mode PLL Configuration Examples When considering settings not shown in this table, the key configuration parameters which must be selected for optimum operation are: * * * 90MHz f2 100MHz 5 PLLx_N 13 OSCCLOCK = 10 to 14.4MHz or 16.28 to 27MHz
CLOCK OUTPUT (CLKOUT) AND MCLK OUTPUT (MCLK) The clock output (CLKOUT) pin can be used as a clock output. This pin is intended to be used as a clock source pin for providing the central clock reference for an audio system. The CLKOUT clock source can be selected from OSCCLK, PLLACLK or PLLBCLK. The control bits for the CLKOUT signal are shown in Table 47. The MCLK pin can be configured as an input or output - the WM8581 should be powered down when switching MCLK between an input and an output. As an output, MCLK can be sourced from OSCCLK, PLLACLK or PLLBCLK. REGISTER ADDRESS R7 PLLB 4 07h BIT 6:5 LABEL MCLKOUTSRC DEFAULT 00 DESCRIPTION MCLK pin output source 00 = Input - Source MCLK pin 01 = Output - Source PLLACLK 10 = Output - Source PLLBCLK 11 = Output - Source OSCCLK CLKOUT pin source 00 = No Output (tristate) 01 = Output - Source PLLACLK 10 = Output - Source PLLBCLK 11 = Output - Source OSCCLK
8:7
CLKOUTSRC
11
Table 47 MCLK and CLKOUT Control
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S/PDIF RECEIVE MODE CLOCKING
Production Data
In S/PDIF receive mode, the PLLA_N and PLLA_K values are automatically controlled by the S/PDIF receiver to allow the receiver to use PLLA to lock on to and track the incoming S/PDIF data stream. PLLB must be configured to produce a specific reference clock frequency for the S/PDIF receiver. The S/PDIF receiver has three clocking modes based on the incoming S/PDIF stream sample rate. The modes are: * * * Mode 1: Incoming S/PDIF Sample Rate = 88.2kHz -1% to 96kHz +1% Mode 2: Incoming S/PDIF Sample Rate = 44.1kHz -1% to 48kHz +1% Mode 3: Incoming S/PDIF Sample Rate = 32kHz +/- 1%
Before the S/PDIF receiver is enabled, it is important that the PLLB_N and PLLB_K register values (and the PRESCALE_x values as appropriate) are manually configured in a specific default state. Note that the PRESCALE_A value must always be set to the same value as PRESCALE_B. The specified PLLB f2 frequencies that must be configured using the PLLB_N and PLLB_K register values (and the PRESCALE_x values as appropriate) for reception of specific S/PDIF sample rates are as follows: * Modes 1/2/3 (32/44.1/48/88.2/96kHz Sample Rates): PLLB f2 = 94.3104MHz
The FREQMODE_B[1:0] bits and POSTSCALE_B bit are not used in PLL S/PDIF receiver mode. The PLL register settings are configured by default to allow S/PDIF receiver operation using a 12MHz crystal clock. The appropriate PLLB register values must be updated if any crystal clock frequency other than 12MHz is used. Refer to Table 48 for details of a number of recommended PLLB configurations. Many other configurations are possible; please refer to PLL Configuration section for details regarding how to calculate alternative settings. OSC CLK (MHz) 11.2896 12 12.288 19.2 24 27 0 0 0 1 1 1 32 / 44.1 / 48 / 88.2 / 96 32 / 44.1 / 48 / 88.2 / 96 32 / 44.1 / 48 / 88.2 / 96 32 / 44.1 / 48 / 88.2 / 96 32 / 44.1 / 48 / 88.2 / 96 32 / 44.1 / 48 / 88.2 / 96 11.2896 94.3104 8.3537 12 12.288 9.6 12 13.5 94.3104 7.8592 94.3104 7.675 94.3104 9.824 94.3104 7.8592 94.3104 6.986 8 7 7 9 7 6 16A3B3 36FD21 2B3333 346C6A 36FD21 3F19E5 Set N, K Default Setting Set K Set Prescales, N, K Set Prescales Set Prescales, N, K PRESCALE_X S/PDIF RECEIVER SAMPLE RATE(S) (kHz) F1 (MHz) F2 (MHz) R PLLB_N (Hex) PLLB_K (Hex) COMMENT
Table 48 S/PDIF Receive Mode PLLB Initial Configuration Examples The recommended configuration sequences are as follows: TO INITIALLY CONFIGURE THE SYSTEM FOR S/PDIF RECEIVER STARTUP: 1. 2. 3. Write appropriate calculated values (relative to PRESCALE_A, PRESCALE_B, PLLB_N and PLLB_K. oscillator frequency) to
Enable PLLA and PLLB by clearing the PLLAPD and PLLBPD bits. Enable S/PDIF receiver by clearing the SPDIFRXPD and SPDIFPD bits.
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WM8581
In hardware mode, the user has no access to the internal clocking control registers and hence a default configuration is loaded at reset to provide maximum functionality. The S/PDIF receiver is enabled and hence the PLLs operate in S/PDIF receiver mode and all PLL and S/PDIF receiver control is fully automatic. All supported S/PDIF receiver sample rates can be used. FREQMODE_x and POSTSCALE_x control is fully automatic to ensure that the MCLK output is maintained at 256fs relative to the S/PDIF received sample rate. In hardware mode, the OSCCLK must be 12MHz and hence the external crystal (or applied XIN clock) must be 12MHz. No other OSCCLK frequencies are supported in hardware mode.
PHASE-LOCKED LOOPS AND S/PDIF CLOCKING (HARDWARE MODE)
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S/PDIF TRANSCEIVER
FEATURES
* * * * * * * * IEC-60958-3 compatible with 32k frames/s to 96k frames/s support Support for Reception and Transmission of S/PDIF data Clock synthesis PLL with reference clock input and ultra-low jitter output Input mux with support for up to four S/PDIF inputs Register controlled Channel Status recovery and transmission Register read-back of recovered Channel Status bits and error flags Detection of non-audio data, sample rate, and pre-emphasised data Programmable GPO for error flags, frame status flags and clocks
Production Data
An IEC-60958-3 compatible S/PDIF transceiver is integrated into the WM8581. Operation of the S/PDIF function may be synchronous or asynchronous to the rest of the digital audio circuits. The receiver performs data and clock recovery, and sends recovered data either to an external device such as a DSP (via the Digital Audio Interfaces), or if the data is audio PCM, it can route the stereo recovered data to DAC1. The recovered clock may be routed out of the WM8581 onto a pin for external use, and may be used to clock the internal DAC as required. The transmitter generates S/PDIF frames where audio data may be sourced from the ADC, S/PDIF Receiver, or the Digital Audio Interfaces.
S/PDIF FORMAT
S/PDIF is a serial, bi-phase-mark encoded data stream. An S/PDIF frame consists of two subframes. Each sub-frame is made up of: * * * * * * * Preamble - a synchronization pattern used to identify the start of a 192-frame block or subframe 4-bit Auxiliary Data (AUX) - ordered LSB to MSB 20-bit Audio Data (24-bit when combined with AUX) - ordered LSB to MSB Validity Bit - a 1 indicates invalid data in that sub-frame User Bit - over 192-frames, this forms a User Data Block, Channel Bit - over 192-frames, this forms a Channel Status Block Parity Bit - used to maintain even parity over the sub-frame (except the preamble)
An S/PDIF Block consists of 192 frames. Channel and User blocks are incorporated within the 192frame S/PDIF Block. For Consumer mode only the first 40-frames are used to make up the Channel and User blocks. Figure 33 illustrates the S/PDIF format.
Frame 1
.........
Frame 192
Subframe 1
Subframe 2
0
34
Aux
78
Audio Sample Word
27 28
V U C
31
P
Sync preamble
32 bit Word
Figure 33 S/PDIF Format
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WM8581
The S/PDIF transmitter generates the S/PDIF frames, and outputs on the SPDIFOP pin. The audio data for the frame can be taken from one of four sources, selectable using the TXSRC register. The transmitter can be powered down using the SPDIFTXD register bit. The S/PDIF Transmitter can be bypassed by setting the REAL_THROUGH register control bit. When set, the SPDIFOP pin sources the output of the S/PDIF input mux.
S/PDIF TRANSMITTER
REGISTER ADDRESS R30
SPDTXCHAN 0
BIT 1:0
LABEL TXSRC[1:0]
DEFAULT 00
DESCRIPTION S/PDIF Transmitter Data Source 00 = S/PDIF received data (see REAL_THROUGH) 01 = ADC digital output data. 10 = Secondary Audio Interface 11 = Audio Interface received data Overwrite Channel Status Only used if TXSRC=00. Overwrites the received channel status data using data read from S/PDIF transmitter channel status register 0 = Channel data equal to recovered channel data. 1 = Channel data taken from channel status registers. S/PDIF Through Mode Control 0 = SPDIFOP pin sources output of S/PDIF Transmitter 1 = SPDIFOP pins sources output of S/PDIF IN Mux S/PDIF Transmitter Validity Overwrite Mode 0 = disabled, validity bit is 0 when transmitter sources ADC, PAIF or SAIF, or is matches the S/PDIF input validity when S/PDIF transmitter sources S/PDIF receiver. 1 = enabled, validity bit transmitted for subframe 0 is defined by TXVAL_SF0, validity bit transmitted for subframe 1 is defined by TXVAL_SF1. Overwrite Mode S/PDIF Transmitter Validity SubFrame 0 0 = transmit validity = 0 1 = transmit validity = 1 Overwrite Mode S/PDIF Transmitter Validity SubFrame 1 0 = transmit validity = 0 1 = transmit validity = 1 S/PDIF Transmitter powerdown 0 = S/PDIF Transmitter enabled 1 = S/PDIF Transmitter disabled
1Eh
2
OVWCHAN
0
3
REAL_ THROUGH TXVAL_ OVWR
0
4
0
5
TXVAL_SF0
0
6
TXVAL_SF1
0
R51 PWRDN 2 33h
4
SPDIFTXD
1
Table 49 S/PDIF Transmitter Control The WM8581 also transmits the preamble and VUCP bits (Validity, User Data, Channel Status and Parity bits). Validity Bit By default, set to 0 (to indicate valid data) with the following exceptions: 1. 2. TXSRC=00 (S/PDIF receiver), where Validity is the value recovered from the S/PDIF input stream by the S/PDIF receiver. TXVAL_OVWR=1, where Validity is the value set in registers TXVAL_SF0 and TXVAL_SF1.
User Data
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Production Data Set to 0 as User Data configuration is not supported in the WM8581 - if TXSRC=00 (S/PDIF receiver) User Data is the value recovered from the S/PDIF input stream by the S/PDIF receiver. Channel Status The Channel Status bits form a 192-frame block - transmitted at one bit per sub-frame. Each subframe forms its own 192-frame block. The WM8581 is a consumer mode device and only the first 40 bits of the block are used. All data transmitted from the WM8581 is stereo, so the channel status data is duplicated for both channels. The only exception to this is the channel number bits (23:20) which can be changed to indicate whether the channel is left or right in the stereo image. Bits within this block can be configured by setting the Channel Status Bit Control registers (see Table 50 to Table 54). If TXSRC=00 (S/PDIF receiver), the Channel Status bits are transmitted with the same values recovered by the receiver - unless OVWCHAN is set, in which case they are set by the S/PDIF transmitter channel status registers. Parity Bit This bit maintains even parity for data as a means of basic error detection. It is generated by the transmitter. For further details of all channel status bits, refer to IEC-60958-3.
REGISTER ADDRESS R31
SPDTXCHAN 1
BIT
LABEL
CHANNEL STATUS BIT 0
DEFAULT
DESCRIPTION
0
CON/PRO
0
1Fh 1 AUDIO_N 1 0
0 = Consumer Mode 1 = Professional Mode (not supported by WM8581) 0 = S/PDIF transmitted data is audio PCM. 1 = S/PDIF transmitted data is not audio PCM. 0 = Transmitted data has copyright asserted. 1 = Transmitted data has no copyright assertion. 000 = Data from Audio interface has no preemphasis. 001 = Data from Audio interface has preemphasis. 010 = Reserved (Audio interface has preemphasis). 011 = Reserved (Audio interface has preemphasis). All other modes are reserved and should not be used. 00 = Only valid mode for consumer applications.
2
CPY_N
2
0
5:3
DEEMPH[2:0]
5:3
000
7:6
CHSTMODE [1:0]
7:6
00
Table 50 S/PDIF Transmitter Channel Status Bit Control 1
REGISTER ADDRESS R32
SPDTXCHAN 2
BIT
LABEL
CHANNEL STATUS BIT 15:8
DEFAULT
DESCRIPTION
7:0
CATCODE [7:0]
00000000
20h Table 51 S/PDIF Transmitter Channel Status Bit Control 2
Category Code. Refer to S/PDIF specification IEC60958-3 for details. 00h indicates "general" mode.
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BIT LABEL CHANNEL STATUS BIT 19:16 21:20 DEFAULT DESCRIPTION
REGISTER ADDRESS R33
SPDTXCHAN 3
3:0 5:4
SRCNUM [3:0] CHNUM1[1:0]
0000 00
Source Number. No definitions are attached to data. Channel Number for Subframe 1 CHNUM1 00 01 10 11 Function Do not use channel number Send to Left Channel Send to Right Channel Do not use channel number Function Do not use channel number Send to Left Channel Send to Right Channel Do not use channel number
21h
7:6
CHNUM2[1:0]
23:22
00
Channel Number for Subframe 2 CHNUM2 00 01 10 11
Table 52 S/PDIF Transmitter Channel Status Bit Control 3
REGISTER ADDRESS R34
SPDTXCHAN 4
BIT
LABEL
CHANNEL STATUS BIT 27:24
DEFAULT
DESCRIPTION
3:0
FREQ[3:0]
0001
22h 5:4 CLKACU[1:0] 29:28 11
Sampling Frequency Indicated. See S/PDIF specification IEC60958-3 for details. Clock Accuracy of Transmitted clock. 00 = Level II 01 = Level I 10 = Level III 11 = Interface frame rate not matched to sampling frequency.
Table 53 S/PDIF Transmitter Channel Status Bit Control 4
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REGISTER ADDRESS R35
SPDTXCHAN 5
Production Data BIT LABEL CHANNEL STATUS BIT 32 DEFAULT DESCRIPTION
0
MAXWL
1
23h 3:1 TXWL[2:0] 35:33 101
Maximum Audio sample word length 0 = 20 bits 1 = 24 bits Audio Sample Word Length. 000 = Word Length Not Indicated TXWL[2:0] 001 010 100 101 110 MAXWL==1 20 bits 22 bits 23 bits 24 bits 21 bits MAXWL==0 16 bits 18 bits 19 bits 20 bits 17 bits
All other combinations reserved 7:4 ORGSAMP [3:0] 39:36 0000 Original Sampling Frequency. See S/PDIF specification for details. 0000 = original sampling frequency not indicated
Table 54 S/PDIF Transmitter Channel Status Bit Control 5
S/PDIF RECEIVER
INPUT SELECTOR
The S/PDIF receiver has one dedicated input, SPDIFIN1. This pin is a IEC-60958-3-compatible comparator input by default or, if SPDIFIN1MODE is set, the pin will be a CMOS-compatible input. There are three other pins which can be configured as either S/PDIF inputs or general purpose outputs (GPOs). The four S/PDIF inputs are multiplexed to allow one input to go to the S/PDIF receiver for decoding. The S/PDIF receiver can be powered down using the SPDIFRXD register bit.
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Production Data REGISTER ADDRESS R36 SPDMODE 24h BIT 0 LABEL
SPDIFIN1MODE
WM8581
DEFAULT 1 DESCRIPTION Selects the input circuit type for the SPDIFIN1 input 0 = CMOS-compatible input 1 = Comparator input. Compatible with 500mVpp AC coupled consumer S/PDIF input signals as defined in IEC60958-3. S/PDIF Receiver input mux select. The general purpose inputs must be configured using GPOxOP to be either CMOS or comparator inputs if selected by RXINSEL. 00 = Select SPDIFIN1 01 = Select SPDIFIN2 (MFP3) 10 = Select SPDIFIN3 (MFP4) 11 = Select SPDIFIN4 (MFP5) S/PDIF Receiver Word Length Truncation Mask 0 = disabled, data word is truncated as described in Table 60. 1 = enabled, data word is not truncated. GPO pin Configuration Select. 1110 = Set GPO as S/PDIF input (CMOS-compatible input). 1111 = Set GPO as S/PDIF input (compatible with 500mVpp AC coupled consumer S/PDIF input signals as defined in IEC-60958-3). For GPO defaults, see Table 65. S/PDIF Receiver powerdown 0 = S/PDIF Receiver enabled 1 = S/PDIF Receiver disabled
2:1
RXINSEL[1:0]
00
6
WL_MASK
0
R39 GPO2 26h R40 GPO3 27h R51 PWRDN 2 33h
3:0 7:4 3:0
GPO3OP[3:0] GPO4OP[3:0] GPO5OP[3:0]
0010 0011 0100
5
SPDIFRXD
1
Table 55 S/PDIF Receiver Input Selection Register
AUDIO DATA HANDLING
The S/PDIF receiver recovers the data and VUCP bits from each sub-frame. If the S/PDIF input data is in a non-compressed audio format the data can be internally routed to the stereo data input of DAC1. The WM8581 can detect when the data is in a non-compressed audio format and will automatically mute the DAC. See Non-Audio Detection section for more detail. The received data can also be output over the digital audio interfaces in any of the data formats supported. This can be performed while simultaneously using DAC1 for playback. The received data may also be re-transmitted via the S/PDIF transmitter.
USER DATA
The WM8581 can output recovered user data received using GPO pins. See Table 65 for General Purpose Pin control information.
CHANNEL STATUS DATA
The channel status bits are recovered from the incoming data stream and are used to control various functions of the device. The recovered MAXWL and RXWL bits are used to truncate the recovered 24-bit audio word so that only the appropriate numbers of bits are used by the other interfaces (except the S/PDIF transmitter which always processes the full 24-bit recovered word). Should the recovered DEEMPH channel status be set, and the S/PDIF receiver is routed to DAC1, the de-emphasis filter is activated for DAC1.
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Production Data The S/PDIF receiver reads channel status data from channel 1 only. The channel status data is stored in five read-only status registers which can be read via the serial interface (see Serial Interface Readback). When new channel status data has been recovered and stored in registers, the Channel Status Update (CSUD) bit is set to indicate that the status registers have updated and are ready for readback. After readback, CSUD will be cleared until the registers are next updated. The CSUD flag can be configured to be output on any of the GPO pins. The register descriptions for the channel status bits are given below.
REGISTER ADDRESS R44
SPDRXCHAN 1
BIT
LABEL
CHANNEL STATUS BIT 0
DEFAULT
DESCRIPTION
0
CON/PRO
-
2Ch (read-only) 1 AUDIO_N 1 -
0 = Consumer Mode 1 = Professional Mode The WM8581 is a consumer mode device. Detection of professional mode may give erroneous behaviour. Linear PCM Identification 0 = Data word represents audio PCM samples. 1 = Data word does not represent audio PCM samples. 0 = Copyright is asserted for this data. 1 = Copyright is not asserted for this data. 0 = Recovered S/PDIF data has no preemphasis. 1 = Recovered S/PDIF data has preemphasis. Reserved for additional de-emphasis modes. 00 = Only valid mode for consumer applications.
2 3
CPY_N DEEMPH
2 3
-
5:4 7:6
Reserved CHSTMODE [1:0]
5:4 7:6
-
Table 56 S/PDIF Receiver Channel Status Register 1
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BIT LABEL CHANNEL STATUS BIT 15:8 DEFAULT DESCRIPTION
REGISTER ADDRESS R45
SPDRXCHAN 2
7:0
CATCODE [7:0]
-
2Dh (read-only) Table 57 S/PDIF Receiver Channel Status Register 2
Category Code. Refer to S/PDIF specification IEC60958-3 for details. 00h indicates "general" mode.
REGISTER ADDRESS R46
SPDRXCHAN 3
BIT
LABEL
CHANNEL STATUS BIT 19:16
DEFAULT
DESCRIPTION
3:0
SRCNUM [3:0] CHNUM1[1:0]
-
2Eh (read-only)
S/PDIF source number. Refer to S/PDIF specification IEC60958-3 for details. Channel number for sub-frame 1. 00 = Take no account of channel number (channel 1 defaults to left DAC) 01 = channel 1 to left channel 10 = channel 1 to right channel Channel number for sub-frame 2. 00 = Take no account of channel number (channel 2 defaults to left DAC) 01 = channel 2 to left channel 10 = channel 2 to right channel
5:4
21:20
-
7:6
CHNUM2[1:0]
23:22
Table 58 S/PDIF Receiver Channel Status Register 3
REGISTER ADDRESS R47
SPDRXCHAN 4
BIT
LABEL
CHANNEL STATUS BIT 27:24
DEFAULT
DESCRIPTION
3:0
FREQ[3:0]
-
2Fh (read-only)
Sampling Frequency. Refer to S/PDIF specification IEC60958-3 for details. Clock Accuracy of received clock. 00 = Level II 01 = Level I 10 = Level III 11 = Interface frame rate not matched to sampling frequency.
5:4
CLKACU[1:0]
29:28
-
Table 59 S/PDIF Receiver Channel Status Register 4
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REGISTER ADDRESS R48
SPDRXCHAN 5
Production Data
BIT
LABEL
CHANNEL STATUS BIT 32
DEFAULT
DESCRIPTION
0
MAXWL
-
30h (read-only)
Maximum Audio sample word length 0 = 20 bits 1 = 24 bits Audio Sample Word Length. 000: Word Length Not Indicated RXWL[2:0] 001 010 100 101 110 MAXWL==1 20 bits 22 bits 23 bits 24 bits 21 bits MAXWL==0 16 bits 18 bits 19 bits 20 bits 17 bits
3:1
RXWL[2:0]
35:33
-
All other combinations are reserved and may give erroneous operation. Data will be truncated internally when these bits are set unless WL_MASK is set. 7:4 ORGSAMP [3:0] 39:36 Original Sampling Frequency. Refer to S/PDIF specification IEC60958-3 for details. 0000 = original sampling frequency not indicated
Table 60 S/PDIF Receiver Channel Status Register 5
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S/PDIF RECEIVER STATUS FLAGS
There are several status flags generated by the S/PDIF Receiver, described below. FLAG UNLOCK DESCRIPTION Indicates that the S/PDIF Clock Recovery circuit is unlocked, or the incoming S/PDIF signal is not present. 0 = Locked onto incoming S/PDIF stream. 1 = Not locked to the incoming S/PDIF stream, or incoming stream is not present. Indicates that recovered S/PDIF data is marked as invalid. 0 = Data marked as valid 1 = Data marked as invalid Indicates that recovered S/PDIF frame has parity errors or bi-phase encoding errors, or that sub-frames were recovered out of sequence 0 = No data errors or bi-phase encoding errors detected and subframe sequence correct 1 = Data errors or bi-phase encoding errors detected or subframe sequence incorrect (missing preamble) Recovered Channel Status bit-1. 0 = Data word represents audio PCM samples. 1 = Data word does not represent audio PCM samples. Indicates that non-audio code (defined in IEC-61937) has been detected. 0 = Sync code not detected. 1 = Sync code detected - received data is not audio PCM. Recovered Channel Status bit-2 (active low) 0 = Copyright is asserted for this data. 1 = Copyright is not asserted for this data. Recovered Channel Status bit-3 0 = Recovered S/PDIF data has no pre-emphasis. 1 = Recovered S/PDIF data has pre-emphasis Indicates recovered S/PDIF sample rate. 00 = Invalid 01 = 96kHz / 88.2kHz 10 = 48kHz / 44.1kHz 11 = 32kHz Interrupt signal (see section Interrupt Generation) Recovered validity-bit for current sub-frame Recovered user-bit for current sub-frame Recovered channel-bit for current sub-frame Recovered parity-bit for current sub-frame Indicates current sub-frame: 1 = Sub-frame A 0 = Sub-frame B Indicates start of 192 frame-block. High for duration of frame-0. Indicates that the 192 frame-block of channel status data has updated. Indicates `zero-detection' in DACs. See page 45 for more details Logical OR of PCM_N and AUDIO_N VISIBILITY S/PDIF Status Register, GPO pins, SWMODE pin (when in hardware mode) Interrupt Status Register Interrupt Status Register
INVALID
TRANS_ERR
AUDIO_N
Channel Status Register, S/PDIF Status Register S/PDIF Status Register
PCM_N
CPY_N
Channel Status Register, S/PDIF Status Register, GPO pins Channel Status Register, S/PDIF Status Register, GPO pins S/PDIF Status Register
DEEMPH
REC_FREQ[1:0]
INT_N V U C P SFRM_CLK
GPO pins GPO pins GPO pins GPO pins GPO pins GPO pins
192BLK CSUD ZFLAG NON_AUDIO
GPO pins GPO pins MUTE pin, GPO pins GPO pins, SDO pin (when in hardware mode)
Table 61 Status Flag Description
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HARDWARE INTERRUPT GENERATION (INT_N)
Production Data
The hardware interrupt INT_N flag (active low) indicates that a change in status has occurred on one or more of the UNLOCK, INVALID, TRANS_ERR, NON_AUDIO, CPY_N, DEEMPH, CSUD or REC_FREQ flags. To determine which flag caused the interrupt, the Interrupt Status Register (INTSTAT) should be read when INT_N is asserted. INVALID, TRANS_ERR and CSUD generate an interrupt when the flag transitions from low to high. UNLOCK, NON_AUDIO, CPY_N, DEEMPH and REC_FREQ will generate an interrupt on any change in status. INT_N will remain asserted until it is cleared by reading the interrupt status register. If INVALID, TRANS_ERR or CSUD are still active when the interrupt status register is read, INT_N remains asserted. REGISTER ADDRESS R43 INTSTAT 2Bh (read-only) BIT 0 LABEL UPD_UNLOCK DEFAULT DESCRIPTION UNLOCK flag update signal 0 = INT_N not caused by update to UNLOCK flag 1 = INT_N caused by update to UNLOCK flag INVALID flag interrupt signal 0 = INT_N not caused by INVALID flag 1 = INT_N caused by INVALID flag CSUD flag interrupt signal 0 = INT_N not caused by CSUD flag 1 = INT_N caused by CSUD flag TRANS_ERR flag interrupt signal 0 = INT_N not caused by TRANS_ERR flag 1 = INT_N caused by TRANS_ERR flag NON_AUDIO update signal 0 = INT_N not caused by update to NON_AUDIO flag 1 = INT_N caused by update to NON_AUDIO flag CPY_N update signal 0 = INT_N not caused by update to CPY_N flag 1 = INT_N caused by update to CPY_N flag DEEMPH update signal 0 = INT_N not caused by update to DEEMPH flag 1 = INT_N caused by update to DEEMPH flag REC_FREQ update signal 0 = INT_N not caused by update to REC_FREQ flag 1 = INT_N caused by update to REC_FREQ flag
1
INT_INVALID
-
2
INT_CSUD
-
3
INT_TRANS _ERR
-
4
UPD_NON_AUDIO
-
5
UPD_CPY_N
-
6
UPD_DEEMPH
-
7
UPD_REC_FREQ
-
Table 62 Interrupt Status Register Where the INT_N has been asserted due to an updated status signal (UPD_UNLOCK, UPD_NON_AUDIO, UPD_CPY_N, UPD_DEEMPH, UPD_REC_FREQ) the S/PDIF Status Register SPDSTAT, register R49, can be read to reveal the status of the flag. See Table 63 The SPDSTAT register will update if the received Rx S/PDIF data stream changes their values.
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Production Data REGISTER ADDRESS R49 SPDSTAT 31h (read-only) BIT 0 LABEL AUDIO_N DEFAULT DESCRIPTION
WM8581
Recovered Channel Status bit-1. 0 = Data word represents audio PCM samples. 1 = Data word does not represent audio PCM samples. Indicates that non-audio code (defined in IEC-61937) has been detected. 0 = Sync code not detected. 1 = Sync code detected - received data is not audio PCM. Recovered Channel Status bit-2 (active low). 0 = Copyright is asserted for this data. 1 = Copyright is not asserted for this data. Recovered Channel Status bit-3 0 = Recovered S/PDIF data has no pre-emphasis. 1 = Recovered S/PDIF data has pre-emphasis Indicates recovered S/PDIF clock frequency: 00 = Invalid 01 = 96kHz / 88.2kHz 10 = 48kHz / 44.1kHz 11 = 32kHz Indicates that the S/PDIF Clock Recovery circuit is unlocked or that the input S/PDIF signal is not present. 0 = Locked onto incoming S/PDIF stream. 1 = Not locked to the incoming S/PDIF stream or the incoming S/PDIF stream is not present.
1
PCM_N
-
2
CPY_N
-
3
DEEMPH
-
5:4
REC_FREQ [1:0]
--
6
UNLOCK
-
Table 63 S/PDIF Status Register The interrupt and update signals used to generate INT_N can be masked as necessary. The MASK register bit prevents flags from asserting INT_N and from updating the Interrupt Status Register (R43). Masked flags update the S/PDIF Status Register (R49).
REGISTER ADDRESS R37 INTMASK 25h
BIT 8:0
LABEL MASK[8:0]
DEFAULT
000000000
DESCRIPTION When a flag is masked, it does not update the Interrupt Status Register or assert INT_N. 0 = unmask, 1 = mask. MASK[0] = mask control for UPD_UNLOCK MASK[1] = mask control for INT_INVALID MASK[2] = mask control for INT_CSUD MASK[3] = mask control for INT_TRANS_ERR MASK[4] = mask control for UPD_AUDIO_N MASK[5] = mask control for UPD_PCM_N MASK[6] = mask control for UPD_CPY_N MASK[7] = mask control for UPD_DEEMPH MASK[8] = mask control for UPD_REC_FREQ
Table 64 Interrupt Mask Control Register
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ERROR HANDLING IN SOFTWARE MODE
Production Data
When the TRANS_ERR flag is asserted, the recovered S/PDIF sub-frame is corrupted. When the INVALID flag is asserted, the recovered S/PDIF sub-frame is marked as being invalid. The S/PDIF receiver has two modes of error handling for these errors, manual and automatic. The mechanism for each flag is similar and is described below. MANUAL ERROR HANDLING When the flag is not masked using the MASK register, the recovered S/PDIF data is passed to the digital audio interface and DAC1 or to the S/PDIF transmitter (note 1) irrespective of the state of the flag and the data content of the recovered stream. In this case the application processor will be interrupted via the INT_N signal and appropriate action should be taken by the application processor to handle the error condition. AUTOMATIC ERROR HANDLING When the flag is masked using the MASK register, the WM8581 will automatically overwrite the recovered S/PDIF data with either all-zeros or the last valid data sample depending on the status of FILLMODE. In this case the application processor will not be interrupted via the INT_N signal and appropriate action will be taken by the WM8581 to handle the error condition. The automatic error handling can be disabled for the INVALID flag if the `ALWAYSVALID' bit is set. In this case, recovered data which is marked as invalid will be allowed to pass to the digital audio interface or to the S/PDIF transmitter. Notes 1. For the S/PDIF receiver to S/PDIF transmitter data path, only the INVALID flag will cause data to be overwritten, the TRANS_ERR flag is not used to overwrite data which is passed to the S/PDIF transmitter. LABEL FILLMODE DEFAULT 0 DESCRIPTION Fill Mode Overwrite Configuration Determines S/PDIF receiver action when TRANS_ERR or INVALID flag is masked and error condition sets the flag: 0 = Data from S/PDIF receiver is overwritten with last valid data sample when flag is set. 1 = Data from S/PDIF receiver is overwritten as all zeros when flag is set. Automatic Error Handling Configuration for INVALID Flag 0 = INVALID flag automatic error handling enabled. 1 = INVALID flag automatic error handling disabled.
REGISTER ADDRESS R38 GP01 26h
BIT 8
R39 GP02 27h
8
ALWAYSVALID
0
Table 65 S/PDIF Receiver Automatic Error Handling Configuration Registers
NON-AUDIO DETECTION
Non-Audio data is indicated by the AUDIO_N and PCM_N flags. AUDIO_N is recovered from the Channel Status block. PCM_N is set on detection of the 96-bit IEC-61937 non-audio data sync code, embedded in the data section of the S/PDIF frame. If DAC1 is sourcing the S/PDIF Receiver and either the AUDIO_N or PCM_N flags are asserted, DAC1 is automatically muted using the softmute feature. As described above, any change of AUDIO_N or PCM_N status will cause an INT_N interrupt (UPD_NON_AUDIO) to be generated. If the MASK register bit for AUDIO_N or PCM_N is set, then the associated signal will not generate an interrupt (UPD_NON_AUDIO) but the DAC will be muted.
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WM8581
S/PDIF INPUT/ GPO PIN CONFIGURATION
The WM8581 has seven pins which can be configured as GPOs using the registers shown in Table 65. The GPO pins can be used to output status data decoded by the S/PDIF receiver. These same pins may be used as S/PDIF inputs as described in Table 55.
REGISTER ADDRESS R38 GPO1 26h R39 GPO2 27h R40 GPO3 28h R41 GPO4 29h
BIT 3:0 7:4 3:0 7:4 3:0 7:4 3:0
LABEL GPO1OP[3:0] GPO2OP[3:0] GPO3OP[3:0] GPO4OP[3:0] GPO5OP[3:0] GPO6OP[3:0] GPO7OP[3:0]
DEFAULT 0000 0001 0010 0011 0100 0101 0110
DESCRIPTION 0000 = INT_N 0001 = V 0010 = U 0011 = C 0100 = P 0101 = SFRM_CLK 0110 = 192BLK 0111 = UNLOCK 1000 = CSUD 1001 = Invalid 1010 = ZFLAG 1011 = NON_AUDIO 1100 = CPY_N 1101 = DEEMP 1110 = Set GPO as S/PDIF input (CMOS-compatible input). Only applicable for GPO3/4/5. 1111 = Set GPO as S/PDIF input (`comparator' input for AC coupled consumer S/PDIF signals). Only applicable for GPO3/4/5
Table 65 GPO Control Registers
POWERDOWN MODES
The WM8581 has powerdown control bits allowing specific parts of the chip to be turned off when not in use. The ADC is powered down by setting the ADCPD register bit. The three stereo DACs each have a separate powerdown control bit, DACPD[2:0], allowing individual stereo DACs to be powered down when not in use. DACPD can be overwritten by setting ALLDACPD to powerdown all DACs The S/PDIF transmitter is powered down by setting SPDIFTXD. Setting SPDIFRXD powers down the S/PDIF receiver. The PLL, Oscillator and S/PDIF clock recovery circuits are powered down by setting PLLPD, OSCPD and SPDIFPD respectively. Setting all of ADCPD, DACPD[2:0], SPDIFTXD, SPDIFRXD and OUTPD[3:0] will powerdown everything except the references VMIDADC, ADCREF and VMIDDAC. These may be powered down by setting PWDN. Setting PWDN will override all other powerdown control bits. It is recommended that the ADC and DAC are powered down before setting PWDN. The default is for all powerdown bits to be set except OSCPD and PWDN.
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REGISTER ADDRESS R50 PWRDN 1 32h BIT 0 LABEL PWDN DEFAULT 0
Production Data
DESCRIPTION Master powerdown (overrides all powerdown registers) 0 = All digital circuits running, outputs are active 1 = All digital circuits in power down mode, outputs muted ADC powerdown 0 = ADC enabled 1 = ADC disabled DAC powerdowns 0 = DAC enabled 1 = DAC disabled DACPD[0] = DAC1 DACPD[1] = DAC2 DACPD[2] = DAC3 Overrides DACPD[3:0] 0 = DACs under control of DACPD[3:0] 1= All DACs are disabled. OSC output powerdown 0 = OSC output enabled 1 = OSC output disabled A CMOS input can be applied to the OSC input when powered down. 0 = PLLA enabled 1 = PLLA disabled 0 = PLLB enabled 1 = PLLB disabled S/PDIF Clock Recovery PowerDown 0 = S/PDIF enabled 1 = S/PDIF disabled S/PDIF Transmitter powerdown 0 = S/PDIF Transmitter enabled 1 = S/PDIF Transmitter disabled S/PDIF Receiver powerdown 0 = S/PDIF Receiver enabled 1 = S/PDIF Receiver disabled
1
ADCPD
1
4:2
DACPD[2:0]
111
6
ALLDACPD
1
R51 PWRDN 2 33h
0
OSCPD
0
1 2 3
PLLAPD PLLBPD SPDIFPD
1 1 1
4
SPDIFTXD
1
5
SPDIFRXD
1
Table 66 Powerdown Registers
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WM8581
INTERNAL POWER ON RESET CIRCUIT
Figure 34 Internal Power On Reset Circuit Schematic The WM8581 includes an internal Power-On Reset Circuit, which is used to reset the digital logic into a default state after power up. Figure 34 shows a schematic of the internal POR circuit. The POR circuit is powered from AVDD. The circuit monitors DVDD and VMID and asserts PORB low if DVDD or VMID are below the minimum threshold Vpor_off. On power up, the POR circuit requires AVDD to be present to operate. PORB is asserted low until AVDD, DVDD and VMID voltages have risen above their reset thresholds. When these three conditions have been met, PORB is released high. When PORB is released high, all registers are in their default state and writes to the digital interface may take place. On power down, PORB is asserted low whenever DVDD or VMID drop below the minimum threshold Vpor_off. If AVDD is removed at any time, the internal Power On Reset circuit is powered down and the PORB output will follow the AVDD voltage. In most applications, the time required for the device to release PORB high will be determined by the charge time of the VMID node.
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Production Data
Figure 35 Typical Power up sequence where DVDD is powered before AVDD
Figure 36 Typical Power up sequence where AVDD is powered before DVDD
SYMBOL Vpora Vporr Vpora_off Vpord_off
MIN 0.5 0.5 1.0 0.6
TYP 0.7 0.7 1.4 0.8
MAX 1.0 1.1 2.0 1.0
UNIT V V V V
Table 67 Typical POR Operation In a real application, the designer is unlikely to have control of the relative power up sequence of AVDD and DVDD. Using the POR circuit to monitor VMID ensures a reasonable delay between applying power to the device and Device Ready.
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WM8581
Figure 35 and Figure 36 show typical power up scenarios in a real system. Both AVDD and DVDD must be established, and VMID must have reached the threshold Vporr before the device is ready and can be written to. Any writes to the device before Device Ready will be ignored. Figure 35 shows DVDD powering up before AVDD. Figure 36 shows AVDD powering up before DVDD. In both cases, the time from applying power to Device Ready is dominated by the charge time of VMID. A 4.7F capacitor (minimum) is recommended for decoupling on VMID. The charge time for VMID will dominate the time required for the device to become ready after power is applied. The time required for VMID to reach the threshold is a function of the VMID resistor string and the decoupling capacitor. To reduce transient audio effects during power on, the stereo DACs on the WM8581 have their outputs clamped to VMID at power-on. This increases the capacitive loading of the VMID resistor string, as the DAC output AC coupling capacitors must be charged to VMID, and hence the required charge time. To ensure minimum device startup time, the VMIDSEL bit is set by default, thus reducing the impedance of the resistor string. If required, the VMID string can be restored to a high impedance state to save power once the device is ready. REGISTER ADDRESS R29 ADC CONTROL 1 1Dh BIT 8 LABEL VMIDSEL DEFAULT 1 DESCRIPTION VMID Impedance Selection 0 = High impedance, power saving 1 = Low impedance, fast poweron
DEVICE ID READBACK
Reading from registers R0, R1 and R2 returns the device ID and revision number. R0 returns 80h, R1 returns 85h, R2 returns the device revision number. Device ID readback is not possible in continuous readback mode (CONTREAD=1).
HARDWARE CONTROL MODE
The WM8581 can be controlled in Hardware Control Mode or Software Control Mode. The method of control is determined by the state of the HWMODE pin. If the HWMODE pin is low, Software Control Mode is selected. If the HWMODE pin is high, Hardware Control Mode is selected. In Hardware Control Mode the user has limited control over the features of the WM8581. Most of the features will assume their default settings but some can be modified using external pins. HWMODE 0 1 0 2-wire control Software Control Hardware Control SWMODE 1 3-wire control
Table 68 Hardware/Software Mode Setup
DIGITAL ROUTING CONTROL
See page 25 for a more detailed explanation of the Digital Routing Options within the WM8581. In Software Control Mode, the values of register bits DAC_SRC, PAIFTX_SRC and TXSRC configure the signal path routing between interfaces. In hardware mode, similar control can be achieved via pins DR1, DR2, DR3 and DR4 as detailed in Table 69 and Table 70. PIN DR1 DR2 Table 69 DR1 / DR2 Operation 0 DAC_SRC=S/PDIF receiver PAIFTX_SRC=S/PDIF receiver 1 DAC_SRC=PAIF receiver PAIFTX_SRC=ADC output
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DR4 0 0 1 1 Table 70 DR3 / DR4 Operation The Secondary Audio Interface (SAIF) is not operational in Hardware Mode. DR3 0 1 0 1
Production Data
S/PDIF TRANSMITTER DATA SOURCE S/PDIF received data ADC digital output data Not available. PAIF receiver data
STATUS PINS
In Hardware control mode, SDO and SWMODE pins provide S/PDIF status flag information. PIN SWMODE FLAG UNLOCK DESCRIPTION Indicates that the S/PDIF Clock Recovery circuit is unlocked or that the input S/PDIF signal is not present. 0 = Locked to incoming S/PDIF stream. 1 = Not locked to the incoming S/PDIF stream, or incoming stream not present. Logical OR of PCM_N and AUDIO_N: PCM_N indicates that non-audio code (defined in IEC-61937) has been detected. AUDIO_N is the recovered Channel Status bit-1.
SDO
NON_AUDIO
Table 71 Hardware Mode Status Pins
DIGITAL AUDIO INTERFACE CONTROL
In Hardware Control Mode, CSB and SCLK become controls to configure the Primary Audio Interface data format and word length. The configuration applies to both transmit and receive sides of the interface. Table 72 below shows the options available. CSB 0 0 1 1 SCLK 0 1 0 1 FORMAT & WORD LENGTH 24-bit right justified 20-bit right justified 24-bit left justified 24-bit I2S
Table 72 Audio Interface Hardware Mode Control
DAC MUTE CONTROL
In Hardware Control mode, the MUTE pin activates the softmute function on all the DACs. In Software Control mode, MUTE activates softmute on the DAC selected by the DZFM register (when the MPDENB bit is low). See page 37 for a detailed description of the softmute function and the other methods of activating softmute. When floating, the MUTE pin becomes an output for the ZFLAG flag. MUTE 0 1 Floating Normal Operation Mute DAC channels MUTE is an output to indicate when Zero Detection occurs on all DACs (ZFLAG). H = detected, L = not detected. DESCRIPTION
Table 73 MUTE Pin Control Options PD Rev 4.0 April 2007 76
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WM8581
PRIMARY AUDIO INTERFACE (TX) MASTER MODE CONTROL
In Hardware Control Mode, the SDIN pin is used to enable the master mode function on the Primary Audio Interface transmitter. This has the same operation as the PAIFTX_MS register bit. The PAIFTX_RATE default settings of 256fs, and 64 BCLKs/LRCLK for BCLKSEL, are used in Hardware Control Mode. See page Error! Bookmark not defined. for more information on master mode operation. SDIN 0 1 AUDIO INTERFACE (TX) Slave Master
Table 74 Audio Interface (Transmitter) Master Mode Hardware Mode Control
POWERDOWN CONTROL
In Software Control Mode, the device is powered-down by default. In Hardware Control Mode, the chip is powered-up by default but can be powered down by setting the ALLPD(MFP7) input high. (Note that in Software Control Mode, this pin takes the function of SAIF_LRCLK or GPO7). ALLPD (MFP7) 0 Powerup 1 Powerdown
Table 75 Hardware Mode Powerdown Control
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REGISTER MAP
Production Data
The complete register map is shown below. The detailed description can be found in the relevant text of the device description. The WM8581 can be configured using the Control Interface. All unused bits should be set to `0'.
REGISTER NAME PLLA 1/DEVID1 PLLA 2/DEVID2 PLLA 3/DEVREV PLLA 4 PLLB 1 PLLB 2 PLLB 3 PLLB 4 CLKSEL PAIF 1 PAIF 2 SAIF 1 PAIF 3 PAIF 4 SAIF 2 DAC CONTROL 1 DAC CONTROL 2 DAC CONTROL 3 DAC CONTROL 4 DAC CONTROL 5
DIGITAL ATTENUTATION DACL 1
ADDRESS
B8
B7
B6
B5
B4 PLLA_K[8:0] PLLA_K[17:9]
B3
B2
B1
B0
DEFAULT 100100001 101111110
R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R30 R31 R32 R33 R34 R35
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23
0 CLKOUTSRC[1:0] 0 0 0 0 0 PLLB_N[3:0]
MCLKOUTSRC[1:0]
0 0 0
PLLA_N[3:0] 0 0
FREQMODE_A[1:0]
PLLA_K[21:18]
1
POSTSCALE_A PRESCALE_A
001111101 000010100 100100001 101111110
PLLB_K[8:0] PLLB_K[17:9] PLLB_K[21:18]
FREQMODE_B[1:0] 1
POSTSCALE_B PRESCALE_B
001111101 110010100 000010000 000000010 000000010 011000010 110001010 010001010 000001010 011100100 000001001 000000000 011111111
CLKSEL _MAN
TX_CLKSEL[1:0]
PAIFRXMS
ADC_CLKSEL[1:0]
DAC_CLKSEL[1:0]
PAIFRXMS_CLKSEL[1:0]
PAIFRX_BCLKSEL[1:0] PAIFTX_BCLKSEL[1:0]
PAIFRX_RATE[2:0] PAIFTX_RATE[2:0] SAIF_RATE[2:0] PAIFRXFMT[1:0] PAIFTXFMT[1:0] SAIFFMT[1:0] DAC1SEL[1:0] PL[3:0]
0
0
PAIFTXMS SAIFMS
PAIFRXBCP PAIFTXBCP
SAIFMS_CLKSEL[1:0] DACOSR 0 SAIF_EN
SAIF_BCLKSEL[1:0]
PAIFRXLRP PAIFTXLRP
DAC_SRC[1:0] PAIFTX_SRC[1:0] SAIFTX_SRC[1:0]
RX2 DAC_M ODE
PAIFRXWL[1:0] PAIFTXWL[1:0] SAIFWL[1:0] DAC2SEL[1:0]
SAIFBCP
SAIFLRP
DAC4SEL[1:0] IZD 0 0
DAC3SEL[1:0] DZFM[2:0] 0
DEEMPALL
0 0 0 0 UPDATE
DEEMP[3:0]
PHASE[7:0] MPDENB DACATC DZCEN
MUTEALL
DMUTE[3:0]
000000000 011111111
LDA1[7:0]
DIGITAL ATTENUTATION DACR 1 DIGITAL ATTENUTATION DACL 2 DIGITAL ATTENUTATION DACR 2 DIGITAL ATTENUTATION DACL 3 DIGITAL ATTENUTATION DACR 3 DIGITAL ATTENUTATION DACR 4 DIGITAL ATTENUTATION DACR 4 MASTER DIGITAL ATTENUTATION
UPDATE
RDA1[7:0]
011111111
UPDATE
LDA2[7:0]
011111111
UPDATE
RDA2[7:0]
011111111
UPDATE
LDA3[7:0]
011111111
UPDATE
RDA3[7:0]
011111111
UPDATE
LDA4[7:0]
011111111
UPDATE
RDA4[7:0]
011111111
UPDATE VMIDSEL 0 0 0 0 0 0 CHNUM2[1:0] 0 0 0 ADCRATE[2:0] TXVAL_ SF1 TXVAL_ SF0
MASTDA[7:0] ADCHPD ADCOSR AMUTEALL AMUTER TXVAL_ OVWR
REAL_ OVWCHAN THROUGH
011111111 AMUTEL 101000000 000000010 000000000 000000000 SRCNUM[3:0] FREQ[3:0] TXWL[2:0] MAXWL 000000000 000110001 000001011
ADC CONTROL 1 SPDTXCHAN 0 SPDTXCHAN 1 SPDTXCHAN 2 SPDTXCHAN 3 SPDTXCHAN 4 SPDTXCHAN 5
TXSRC[1:0] AUDIO_N CON/PRO
CHSTMODE[1:0]
DEEMPH[2:0] CATCODE[7:0] CHNUM1[1:0] CLKACU[1:0]
CPY_N
ORGSAMP[3:0]
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Production Data R36 R37 R38 R39 R40 R41 R42 R43 R44 R45 R46 R47 R48 R49 R50 R51 R52 R53
SPDMODE INTMASK GPO1 GPO2 GPO3 GPO4 Reserved INTSTAT SPDRXCHAN 1 SPDRXCHAN 2 SPDRXCHAN 3 SPDRXCHAN 4 SPDRXCHAN 5 SPDSTAT PWRDN 1 PWRDN 2 READBACK RESET
WM8581
24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35
0 0 0 0 0 0 ALLDACPD 0 0
FILLMODE ALWAYSVALID
0
0
WL_MASK
1
1 MASK[8:0]
1
RXINSEL[1:0]
SPDIFIN1MODE
000111001 000000000
GPO2OP[3:0] GPO4OP[3:0] GPO6OP[3:0] 0 1 1 0 1 0 1 1 1
GPO1OP[3:0] GPO30P[3:0] GPO5OP[3:0] GPO70P[3:0] 0 0 0
000010000 000110010 001010100 001110110 010011000 -
0 0 0
Error Flag Interupt Status Register Channel Status Register 1 Channel Status Register 2 Channel Status Register 3 Channel Status Register 4 Channel Status Register 5 S/PDIF Status Register DACPD[3:0] SPDIFRXD SPDIFTXD SPDIFPD 0
READEN
CONTREAD
ADCPD PLLBPD PLLAPD
READMUX[2:0]
PWDN OSCPD
001111110 000111110 000000000 n/a
RESET
REGISTER ADDRESS R0 PLLA 1/ DEVID1 00h R1 PLLA 2/ DEVID2 01h R2 PLLA 3/ DEVREV 02h
BIT 8:0
LABEL PLLA_K[8:0]
DEFAULT 100100001
DESCRIPTION Fractional (K) part of PLLA frequency ratio (R). Value K is one 22-digit binary number spread over registers R0, R1 and R2 as shown. Reading from these registers will return the device ID. R0 returns 10000001 = 81h R1 returns 10000101 = 85h Device ID readback is not possible in continuous readback mode (CONTREAD=1). Integer (N) part of PLLA frequency ratio (R). Use values in the range 5 PLLA_N 13 as close as possible to 8. Reading from this register will return the device revision number.
8:0
PLLA_K[17:9]
101111110
3:0 7:4
PLLA_K[21:18] PLLA_N[3:0]
1101 0111
R3 PLLA 4 03h
0
PRESCALE_A
0
PLL Pre-scale Divider Select 0 = Divide by 1 (PLL input clock = oscillator clock) 1 = Divide by 2 (PLL input clock = oscillator clock / 2) Note: PRESCALE_A must be set to the same value as PRESCALE_B in PLL S/PDIF receiver mode. PLL Post-scale Divider Select PLL S/PDIF Receiver Mode POSTSCALE_A is used to configure a 256fs or 128fs PLLACLK, POSTSCALE_B is not used. Refer to Table 45. PLL User Mode Used in conjunction with the FREQMODE_x bits. Refer to Table 44.
1
POSTSCALE_A
0
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REGISTER ADDRESS BIT 4:3 LABEL FREQMODE_A[ 1:0] DEFAULT 10 DESCRIPTION
Production Data
PLL Output Divider Select PLL S/PDIF Receiver Mode FREQMODE_A is automatically controlled. FREQMODE_B is not used. PLL User Mode Used in conjunction with the POSTSCALE_x bits. Refer to Table 44. Fractional (K) part of PLLB frequency ratio (R). Value K is one 22-digit binary number spread over registers R4, R5 and R6 as shown. Note: PLLB_K must be set to specific values when the S/PDIF receiver is used. Refer to S/PDIF Receive Mode Clocking section for details.
R4 PLLB 1 04h R5 PLLB 2 05h R6 PLLB 3 06h
8:0
PLLB_K[8:0]
100100001
8:0
PLLB_K[17:9]
101111110
3:0 7:4
PLLB_K[21:18] PLLB_N[3:0]
1101 0111 Integer (N) part of PLL B frequency ratio (R). Use values in the range 5 PLLB_N 13 as close as possible to 8 Note: PLLB_N must be set to specific values when the S/PDIF receiver is used. Refer to S/PDIF Receive Mode Clocking section for details. PLL Pre-scale Divider Select 0 = Divide by 1 (PLL input clock = oscillator clock) 1 = Divide by 2 (PLL input clock = oscillator clock / 2) Note: PRESCALE_A must be set to the same value as PRESCALE_B in PLL S/PDIF receiver mode. PLL Post-scale Divider Select PLL S/PDIF Receiver Mode POSTSCALE_A is used to configure a 256fs or 128fs PLLACLK, POSTSCALE_B is not used. Refer to Table 45. PLL User Mode Used in conjunction with the FREQMODE_x bits. Refer to Table 44. PLL Output Divider Select PLL S/PDIF Receiver Mode FREQMODE_A is automatically controlled. FREQMODE_B is not used. PLL User Mode Used in conjunction with the POSTSCALE_x bits. Refer to Table 44. MCLK pin output source 00 = Input - Source MCLK pin 01 = Output - Source PLLACLK 10 = Output - Source PLLBCLK 11 = Output - Source OSCCLK CLKOUT pin source 00 = No Output (tristate) 01 = Output - Source PLLACLK 10 = Output - Source PLLBCLK 11 = Output - Source OSCCLK DAC clock source 00 = MCLK pin 01 = PLLACLK 10 = PLLBCLK 11 = MCLK pin PD Rev 4.0 April 2007 80
R7 PLLB 4 07h
0
PRESCALE_B
0
1
POSTSCALE_B
0
4:3
FREQMODE_B [1:0]
10
6:5
MCLKOUTSRC
00
8:7
CLKOUTSRC
11
R8 CLKSEL 08h
1:0
DAC_CLKSEL
00
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Production Data REGISTER ADDRESS BIT 3:2 LABEL ADC_CLKSEL DEFAULT 00 ADC clock source 00 = ADCMLCK pin 01 = PLLACLK 10 = PLLBCLK 11 = MCLK pin S/PDIF Transmitter clock source 00 = ADCMLCK pin 01 = PLLACLK 10 = PLLBCLK 11 = MCLK pin DESCRIPTION
WM8581
5:4
TX_CLKSEL
01
6
CLKSEL_MAN
0
Clock selection auto-configuration override 0 = auto-configuration enabled, clock configuration follows restrictions described in page 43 to page 48. 1 = auto-configuration disabled, clock configuration follows relevant CLKSEL bits in R8 to R11. Master Mode LRCLK Rate 000 = 128fs 001 = 192fs 010 = 256fs 011 = 384fs 100 = 512fs 101 = 768fs 110 = 1152fs Master Mode BCLK Rate 00 = 64 BCLKs per LRCLK 01 = 32 BCLKs per LRCLK 10 = 16 BCLKs per LRCLK 11 = BCLK = System Clock PAIF Receiver Master/Slave Mode Select 0 = Slave Mode 1 = Master Mode PAIF Receiver Master Mode clock source 00 = MCLK pin 01 = PLLACLK 10 = PLLBCLK 11 = MCLK pin Master Mode LRCLK Rate 000 = 128fs 001 = 192fs 010 = 256fs 011 = 384fs 100 = 512fs 101 = 768fs 110 = 1152fs Master Mode BCLKRate 00 = 64 BCLKs per LRCLK 01 = 32 BCLKs per LRCLK 10 = 16 BCLKs per LRCLK 11 = BCLK = System Clock PAIF Transmitter Master/Slave Mode Select: 0 = Slave Mode 1 = Master Mode
R9 PAIF 1 09h
2:0
PAIFRX_RATE [2:0]
010
4:3 PAIFRX_BCLKSEL [1:0]
00
5
PAIFRXMS
0
7:6
PAIFRXMS_ CLKSEL
00
R10 PAIF 2 0Ah
2:0
PAIFTX_RATE [2:0]
010
4:3 PAIFTX_BCLKSEL [1:0]
00
5
PAIFTXMS
0
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REGISTER ADDRESS R11 SAIF1 0Bh BIT 2:0 LABEL SAIF_RATE [2:0] DEFAULT 010 DESCRIPTION Master Mode LRCLK Rate 000 = 128fs 001 = 192fs 010 = 256fs 011 = 384fs 100 = 512fs 101 = 768fs 110 = 1152fs Master Mode BCLK Rate 00 = 64 BCLKs per LRCLK 01 = 32 BCLKs per LRCLK 10 = 16 BCLKs per LRCLK 11 = BCLK = System Clock SAIF Master/Slave Mode Select 0 = Slave Mode 1 = Master Mode SAIF Master Mode clock source 00 = ADCMCLK pin 01 = PLLACLK 10 = PLLBCLK 11 = MCLK pin PAIF Receiver Audio Data Format Select 11: DSP Format 10: I2S Format 01: Left justified 00: Right justified PAIF Receiver Audio Data Word Length 11: 32 bits (see Note) 10: 24 bits 01: 20 bits 00: 16 bits In LJ/RJ/I2S modes 0 = LRCLK not inverted 1 = LRCLK inverted In DSP Format: 0 = DSP Mode A 1 = DSP Mode B PAIF Receiver BCLK polarity 0 = BCLK not inverted 1 = BCLK inverted DAC Oversampling Rate Control 0= 128x oversampling 1= 64x oversampling
Production Data
4:3
SAIF_BCLKSEL [1:0]
00
5
SAIFMS
0
7:6
SAIFMS_ CLKSEL [1:0]
11
R12 PAIF 3 0Ch
1:0
PAIFRXFMT [1:0]
10
3:2
PAIFRXWL [1:0]
10
4
PAIFRXLRP
0
5
PAIFRXBCP
0
6
DACOSR
0
8:7
DAC_SRC [1:0]
11
DAC1 Source: 00 = S/PDIF received data. 10 = SAIF Receiver data 11 = PAIF Receiver data Note: When DAC_SRC = 00, DAC2/3/4 may be turned off, depending on RX2DAC_MODE
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Production Data REGISTER ADDRESS R13 PAIF 4 0Dh BIT 1:0 LABEL PAIFTXFMT [1:0] DEFAULT 10 DESCRIPTION PAIF Transmitter Audio Data Format Select 11: DSP Format 10: I2S Format 01: Left justified 00: Right justified PAIF Transmitter Audio Data Word Length 11: 32 bits (see Note) 10: 24 bits 01: 20 bits 00: 16 bits In LJ/RJ/I2S modes 0 = LRCLK not inverted 1 = LRCLK inverted In DSP Format: 0 = DSP Mode A 1 = DSP Mode B PAIF Receiver BCLK polarity 0 = BCLK not inverted 1 = BCLK inverted Primary Audio Interface Transmitter Source 00 = S/PDIF received data. 01 = ADC digital output data. 10 = SAIF Receiver data SAIF Audio Data Format Select 11: DSP Format 10: I2S Format 01: Left justified 00: Right justified SAIF Audio Data Word Length 11: 32 bits (see Note) 10: 24 bits 01: 20 bits 00: 16 bits In LJ/RJ/I2S modes 0 = LRCLK not inverted 1 = LRCLK inverted In DSP Format: 0 = DSP Mode A 1 = DSP Mode B SAIF BCLK polarity 0 = BCLK not inverted 1 = BCLK inverted SAIF Enable 0 = SAIF disabled 1 = SAIF enabled Secondary Audio Interface Transmitter Source 00 = S/PDIF received data. 01 = ADC digital output data. 11 = PAIF Receiver data
WM8581
3:2
PAIFTXWL [1:0]
10
4
PAIFTXLRP
0
5
PAIFTXBCP
0
8:7
PAIFTX_SRC [1:0]
01
R14 SAIF 2 0Eh
1:0
SAIFFMT [1:0]
10
3:2
SAIFWL [1:0]
10
4
SAIFLRP
0
5
SAIFBCP
0
6
SAIF_EN
0
8:7
SAIFTX_SRC [1:0]
00
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WM8581
REGISTER ADDRESS R15 DAC CONTROL 1 0Fh BIT 1:0 3:2 5:4 7:6 8 LABEL DAC1SEL [1:0] DAC2SEL [1:0] DAC3SEL [1:0] DAC4SEL [1:0]
RX2DAC_MODE
Production Data DEFAULT 00 01 10 11 0 DAC oversampling rate and power down control (only valid when DAC_SRC = 00, S/PDIF receiver) 0 = SFRM_CLK determines oversampling rate, DACs 2/3 powered down 1 = PAIFRX_LRCLK determines oversampling rate, DACs 2/3 source PAIF Receiver PL[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 6:4 DZFM[2:0] 000 Left O/P Mute Left Right (L+R)/2 Mute Left Right (L+R)/2 Mute Left Right (L+R)/2 Mute Left Right (L+R)/2 Right O/P Mute Mute Mute Mute Left Left Left Left Right Right Right Right (L+R)/2 (L+R)/2 (L+R)/2 (L+R)/2 DESCRIPTION DAC digital input select 00 = DAC takes data from 01 = DAC takes data from 10 = DAC takes data from 11 = DAC takes data from
DIN1 DIN2 DIN3 DIN4
R16 DAC CONTROL 2 10h
3:0
PL[3:0]
1001
Selects the- source for ZFLAG 000 --All-DACs Zero Flag 001 --DAC1 Zero Flag 010 --DAC2 Zero Flag 011 --DAC3 Zero Flag 100 --DAC4 Zero F-ag 101 - ZFLAG - 0-110 - ZFLAG = 0 111 - ZFLAG = 0 Infinite zero detection circuit control and automute control 0 = Infinite zero detect automute disabled 1 = Infinite zero detect automute enabled De-emphasis mode select DEEMP[0] = 1, enable De-emphasis on DAC1 DEEMP[1] = 1, enable De-emphasis on DAC2 DEEMP[2] = 1, enable De-emphasis on DAC3 DEEMP[3] = 1, enable De-emphasis on DAC 4 0 = De-emphasis controlled by DEEMP[3:0] 1 = De-emphasis enabled on all DACs
7
IZD
0
R17 DAC CONTROL 3 11h
3:0
DEEMP[3:0]
0000
4
DEEMPALL
0
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Production Data REGISTER ADDRESS R18 DAC CONTROL 4 12h BIT 7:0 LABEL PHASE [7:0] DEFAULT 11111111 DESCRIPTION Controls phase of DAC outputs 0 = inverted 1 = non-inverted PHASE[0] = 0 inverts phase of DAC1L output PHASE[1] = 0 inverts phase of DAC1R output PHASE[2] = 0 inverts phase of DAC2L output PHASE[3] = 0 inverts phase of DAC2R output PHASE[4] = 0 inverts phase of DAC3L output PHASE[5] = 0 inverts phase of DAC3R output PHASE[6] = 0 inverts phase of DAC4L output PHASE[7] = 0 inverts phase of DAC4R output DAC channel soft mute enables DMUTE[0] = 1, enable soft-mute on DAC1 DMUTE[1] = 1, enable soft-mute on DAC2 DMUTE[2] = 1, enable soft-mute on DAC3 DMUTE[3] = 1, enable soft-mute on DAC4 DAC channel master soft mute. Mutes all DAC channels 0 = disable soft-mute on all DACs 1 = enable soft-mute on all DACs DAC Digital Volume Zero Cross Enable 0 = Zero Cross detect disabled 1 = Zero Cross detect enabled
WM8581
R19 DAC CONTROL 5 13h
3:0
DMUTE[3:0]
0000
4
MUTEALL
0
5
DZCEN
0
6
DACATC
0
Attenuator Control 0 = All DACs use attenuations as programmed. 1 = Right channel DACs use corresponding left DAC attenuations MUTE pin decode enable 0 = MUTE activates soft-mute on DAC selected by DZFM 1 = MUTE activates softmute on all DACs Digital Attenuation control for DAC1 Left Channel (DACL1) in 0.5dB steps. See Table 23 Controls simultaneous update of all Attenuation Latches 0 = Store LDA1 in intermediate latch (no change to output) 1 = Apply LDA1 and update attenuation on all channels Digital Attenuation control for DAC1 Right Channel (DACR1) in 0.5dB steps. See Table 23 Controls simultaneous update of all Attenuation Latches 0 = Store RDA1 in intermediate latch (no change to output) 1 = Apply RDA1 and update attenuation on all channels Digital Attenuation control for DAC2 Left Channel (DACL2) in 0.5dB steps. See Table 23 Controls simultaneous update of all Attenuation Latches 0 = Store LDA2 in intermediate latch (no change to output) 1 = Apply LDA2 and update attenuation on all channels Digital Attenuation control for DAC2 Right Channel (DACR2) in 0.5dB steps. See Table 23 Controls simultaneous update of all Attenuation Latches 0 = Store RDA2 in intermediate latch (no change to output) 1 = Apply RDA2 and update attenuation on all channels Digital Attenuation control for DAC3 Left Channel (DACL3) in 0.5dB steps. See Table 23 Controls simultaneous update of all Attenuation Latches 0 = Store LDA3 in intermediate latch (no change to output) 1 = Apply LDA3 and update attenuation on all channels PD Rev 4.0 April 2007 85
7
MPDENB
0
R20
DIGITAL ATTENUATION DACL 1
7:0 8
LDA1[7:0] UPDATE
11111111 (0dB) Not latched
14h R21
DIGITAL ATTENUATION DACR 1
7:0 8
RDA1[7:0] UPDATE
11111111 (0dB) Not latched
15h R22
DIGITAL ATTENUATION DACL 2
7:0 8
LDA2[7:0] UPDATE
11111111 (0dB) Not latched
16h R23
DIGITAL ATTENUATION DACR 2
7:0 8
RDA2[7:0] UPDATE
11111111 (0dB) Not latched
17h R24
DIGITAL ATTENUATION DACL 3
7:0 8
LDA3[7:0] UPDATE
11111111 (0dB) Not latched
18h
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WM8581
REGISTER ADDRESS R25
DIGITAL ATTENUATION DACR 3
Production Data BIT 7:0 8 LABEL RDA3[7:0] UPDATE DEFAULT 11111111 (0dB) Not latched DESCRIPTION Digital Attenuation control for DAC3 Right Channel (DACR3) in 0.5dB steps. See Table 23 Controls simultaneous update of all Attenuation Latches 0 = Store RDA3 in intermediate latch (no change to output) 1 = Apply RDA3 and update attenuation on all channels Digital Attenuation control for DAC4 Left Channel (DACL4) in 0.5dB steps. See Table 23 Controls simultaneous update of all Attenuation Latches 0 = Store LDA4 in intermediate latch (no change to output) 1 = Apply LDA4 and update attenuation on all channels Digital Attenuation control for DAC4 Right Channel (DACR4) in 0.5dB steps. See Table 23 Controls simultaneous update of all Attenuation Latches 0 = Store RDA4 in intermediate latch (no change to output) 1 = Apply RDA4 and update attenuation on all channels Digital Attenuation control for all DAC channels in 0.5dB steps. See Table 23 Controls simultaneous update of all Attenuation Latches 0 = Store gain in intermediate latch (no change to output) 1 = Apply gain and update attenuation on all channels ADC Mute select 0 : Normal Operation 1: mute ADC left ADC Mute select 0 : Normal Operation 1: mute ADC right ADC Mute select 0 : Normal Operation 1: mute both ADC channels ADC oversample rate select 0 = 128/64 x oversampling 1 = 64/32 x oversampling ADC high-pass filter disable: 0 = high-pass filter enabled 1 = high-pass filter disabled ADC Rate Control (only used when the S/PDIF Transmitter is the only interface sourcing the ADC) 000 = 128fs 001 = 192fs 010 = 256fs 011 = 384fs 100 = 512fs 101 = 768fs 110 = 1152fs 8 VMIDSEL 1 VMID Impedance Selection 0 = High impedance, power saving 1 = Low impedance, fast power-on S/PDIF Transmitter Data Source 00 = S/PDIF received data (see REAL_THROUGH) 01 = ADC digital output data. 10 = Secondary Audio Interface 11 = Audio Interface received data PD Rev 4.0 April 2007 86
19h R26
DIGITAL ATTENUATION DACL 4
7:0 8
LDA4[7:0] UPDATE
11111111 (0dB) Not latched
1Ah R27
DIGITAL ATTENUATION DACR 4
7:0 8
RDA4[7:0] UPDATE
11111111 (0dB) Not latched
1Bh R28
MASTER DIGITAL ATTENUATION
7:0 8
MASTDA[7:0] UPDATE
11111111 (0dB) Not latched
1Ch R29 ADC CONTROL 1 1Dh 0 AMUTEL 0
1
AMUTER
0
2
AMUTEALL
0
3
ADCOSR
0
4
ADCHPD
0
7:5
ADCRATE[2:0]
010
R30
SPDTXCHAN 0
1:0
TXSRC[1:0]
10
1Eh
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Production Data REGISTER ADDRESS BIT 2 LABEL OVWCHAN DEFAULT 0 DESCRIPTION
WM8581
Only used if TXSRC==00. Overwrites the `through-path' Channel Bit with values determined by the channel-bit control registers. 0 = Channel data equal to recovered channel data. 1 = Channel data taken from channel status registers. S/PDIF Through Mode Control 0 = SPDIFOP pin sources output of S/PDIF Transmitter 1 = SPDIFOP pins sources output of S/PDIF IN Mux S/PDIF Transmitter Validity Overwrite Mode 0 = disabled, validity bit is 0 when transmitter sources ADC, PAIF or SAIF, or is matches the S/PDIF input validity when S/PDIF transmitter sources S/PDIF receiver. 1 = enabled, validity bit transmitted for subframe 0 is defined by TXVAL_SF0, validity bit transmitted for subframe 1 is defined by TXVAL_SF1. Overwrite Mode S/PDIF Transmitter Validity Sub-Frame 0 0 = transmit validity = 0 1 = transmit validity = 1 Overwrite Mode S/PDIF Transmitter Validity Sub-Frame 1 0 = transmit validity = 0 1 = transmit validity = 1 0 = Consumer Mode 1 = Professional Mode (not supported by WM8581) 0 = S/PDIF transmitted data is audio PCM. 1 = S/PDIF transmitted data is not audio PCM. 0 = Transmitted data has copyright asserted. 1 = Transmitted data has no copyright assertion. 000 = Data from Audio interface has no pre-emphasis. 001 = Data from Audio interface has pre-emphasis. 010 = Reserved (Audio interface has pre-emphasis). 011 = Reserved (Audio interface has pre-emphasis). All other modes are reserved and should not be used. 00 = Only valid mode for consumer applications. Category Code. Refer to S/PDIF specification for details. 00h indicates "general" mode Source Number. No definitions are attached to data. Channel Number for Subframe 1 CHNUM1 00 01 10 11 Channel Status Bits[21:20] 0000 = Do not use channel number 0001 = Send to Left Channel 0010 = Send to Right Channel 0000 = Do not use channel number Channel Status Bits[23:22] 0000 = Do not use channel number 0001 = Send to Left Channel 0010 = Send to Right Channel 0000 = Do not use channel number
3
REAL_ THROUGH TXVAL_OVWR
0
4
0
5
TXVAL_SF0
0
6
TXVAL_SF1
0
R31
SPDTXCHAN 1
0 1 2 5:3
CON/PRO AUDIO_N CPY_N DEEMPH[2:0]
0 0 0 000
1Fh
7:6 R32
SPDTXCHAN 2
CHSTMODE [1:0] CATCODE [7:0] SRCNUM [3:0] CHNUM1[1:0]
00 00000000
7:0
20h R33
SPDTXCHAN 3
3:0 5:4
0000 00
21h
7:6
CHNUM2[1:0]
00
Channel Number for Subframe 2 CHNUM2 00 01 10 11
R34
SPDTXCHAN 4
3:0
FREQ[3:0]
0001
Sampling Frequency. See S/PDIF specification for details. 0001 = Sampling Frequency not indicated.
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WM8581
REGISTER ADDRESS 22h BIT 5:4 LABEL CLKACU[1:0] DEFAULT 11 DESCRIPTION
Production Data
Clock Accuracy of Generated clock. 00 = Level II 01 = Level I 10 = Level III 11 = Interface frame rate not matched to sampling frequency. Maximum Audio sample word length 0 = 20 bits 1 = 24 bits Audio Sample Word Length. 000 = Word Length Not Indicated TXWL[2:0] 001 010 100 101 110 MAXWL==1 20 bits 22 bits 23 bits 24 bits 21 bits MAXWL== 0 16 bits 18 bits 19 bits 20 bits 17 bits
R35
SPDTXCHAN 5
0
MAXWL
1
23h 3:1 TXWL[2:0] 101
All other combinations reserved 7:4 R36 SPDMODE 24h 0 ORGSAMP [3:0]
SPDIFIN1MODE
0000 1
Original Sampling Frequency. See S/PDIF specification for details. 0000 = original sampling frequency not indicated Selects the input circuit type for the SPDIFIN1 input 0 = CMOS-compatible input 1 = Comparator input. Compatible with 500mVpp AC coupled consumer S/PDIF input signals as defined in IEC-60958-3. S/PDIF Receiver input mux select. Note that the general purpose inputs must be configured using GPOxOP to be either CMOS or comparator inputs if selected by RXINSEL. 00 = SPDIFIN1 01 = SPDIFIN2 (MFP3) 10 = SPDIFIN3 (MFP4) 11 = SPDIFIN4 (MFP5) S/PDIF Receiver Word Length Truncation Mask 0 = disabled, data word is truncated as described in Table 60. 1 = enabled, data word is not truncated. When a flag is masked, it does not update the Error Register or contribute to the interrupt pulse. 0 = unmask, 1 = mask. MASK[0] = mask control for UPD_UNLOCK MASK[1] = mask control for INT_INVALID MASK[2] = mask control for INT_CSUD MASK[3] = mask control for INT_TRANS_ERR MASK[4] = mask control for UPD_AUDIO_N MASK[5] = mask control for UPD_PCM_N MASK[6] = mask control for UPD_CPY_N MASK[7] = mask control for UPD_DEEMPH MASK[8] = mask control for UPD_REC_FREQ 0000 = INT_N
2:1
RXINSEL[1:0]
00
6
WL_MASK
0
R37 INTMASK 25h
8:0
MASK[8:0]
000000000
R38
3:0
GPO1OP[3:0]
0000
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Production Data REGISTER ADDRESS GPO1 26h BIT 7:4 LABEL GPO2OP[3:0] DEFAULT 0001 DESCRIPTION
WM8581
0001 = V 0010 = U 0011 = C 0100 = P 0101 = SFRM_CLK 0110 = 192BLK 0111 = UNLOCK 1000 = CSUD 1001 = Invalid 1010 = ZFLAG 1011 = NON_AUDIO 1100 = CPY_N 1101 = DEEMP 1110 = Set GPO as S/PDIF input (standard CMOS input buffer). Only applicable for GPO3/4/5. 1111 = Set GPO as S/PDIF input (`comparator' input for AC coupled consumer S/PDIF signals). Only applicable for GPO3/4/5 Fill Mode Overwrite Configuration Determines S/PDIF receiver action when TRANS_ERR or INVALID flag is masked and error condition sets the flag: 0 = Data from S/PDIF receiver is overwritten with last valid data sample when flag is set. 1 = Data from S/PDIF receiver is overwritten as all zeros when flag is set. 0000 = INT_N 0001 = V 0010 = U 0011 = C 0100 = P 0101 = SFRM_CLK 0110 = 192BLK 0111 = UNLOCK 1000 = CSUD 1001 = Invalid 1010 = ZFLAG 1011 = NON_AUDIO 1100 = CPY_N 1101 = DEEMP 1110 = Set GPO as S/PDIF input (standard CMOS input buffer). Only applicable for GPO3/4/5. 1111 = Set GPO as S/PDIF input (`comparator' input for AC coupled consumer S/PDIF signals). Only applicable for GPO3/4/5 Automatic Error Handling Configuration for INVALID Flag 0 = INVALID flag automatic error handling enabled. 1 = INVALID flag automatic error handling disabled. 0000 = INT_N 0001 = V
8
FILLMODE
0
R39 GPO2 27h
3:0 7:4
GPO3OP[3:0] GPO4OP[3:0]
0010 0011
8
ALWAYSVALID
0
R40 GPO3 28h
3:0 7:4
GPO5OP[3:0] GPO6OP[3:0]
0100 0101
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WM8581
REGISTER ADDRESS R41 GPO4 29h BIT 3:0 LABEL GPO7OP[3:0] DEFAULT 0110 DESCRIPTION
Production Data
0010 = U 0011 = C 0100 = P 0101 = SFRM_CLK 0110 = 192BLK 0111 = UNLOCK 1000 = CSUD 1001 = Invalid 1010 = ZFLAG 1011 = NON_AUDIO 1100 = CPY_N 1101 = DEEMP 1110 = Set GPO as S/PDIF input (standard CMOS input buffer). Only applicable for GPO3/4/5. 1111 = Set GPO as S/PDIF input (`comparator' input for AC coupled consumer S/PDIF signals). Only applicable for GPO3/4/5 UNLOCK flag update signal 0 = INT_N not caused by update to UNLOCK flag 1 = INT_N caused by update to UNLOCK flag INVALID flag interrupt signal 0 = INT_N not caused by INVALID flag 1 = INT_N caused by INVALID flag CSUD flag interrupt signal 0 = INT_N not caused by CSUD flag 1 = INT_N caused by CSUD flag TRANS_ERR flag interrupt signal 0 = INT_N not caused by TRANS_ERR flag 1 = INT_N caused by TRANS_ERR flag NON_AUDIO update signal 0 = INT_N not caused by update to NON_AUDIO flag 1 = INT_N caused by update to NON_AUDIO flag CPY_N update signal 0 = INT_N not caused by update to CPY_N flag 1 = INT_N caused by update to CPY_N flag DEEMPH update signal 0 = INT_N not caused by update to DEEMPH flag 1 = INT_N caused by update to DEEMPH flag REC_FREQ update signal 0 = INT_N not caused by update to REC_FREQ flag 1 = INT_N caused by update to REC_FREQ flag 0 = Consumer Mode 1 = Professional Mode The WM8581 is a consumer mode device. Detection of professional mode may give erroneous behaviour. Recovered S/PDIF Channel status bit 1. 0 = Data word represents audio PCM samples. 1 = Data word does not represent audio PCM samples. 0 = Copyright is asserted for this data. 1 = Copyright is not asserted for this data. 0 = Recovered S/PDIF data has no pre-emphasis. 1 = Recovered S/PDIF data has pre-emphasis. Reserved for additional de-emphasis modes.
R43 INTSTAT 2Bh
0
UPD_UNLOCK
-
1
INT_INVALID
-
2
INT_CSUD
-
3
INT_TRANS_ERR
-
4
UPD_NON_AUDIO
-
5
UPD_CPY_N
-
6
UPD_DEEMPH
-
7
UPD_REC_FREQ
-
R44
SPDRXCHAN 1
0
CON/PRO
-
2C 1 AUDIO_N -
2 3 5:4
CPY_N DEEMPH Reserved
-
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Production Data REGISTER ADDRESS BIT 7:6 R45
SPDRXCHAN 2
WM8581
LABEL CHSTMODE [1:0] CATCODE [7:0] SRCNUM [3:0] CHNUM1[1:0] DEFAULT DESCRIPTION 00 = Only valid mode for consumer applications. Category Code. Refer to S/PDIF specification for details. 00h indicates "general" mode. Indicates number of S/PDIF source. Channel number for sub-frame 1. 00 = Take no account of channel number (channel 1 defaults to left DAC) 01 = channel 1 to left channel 10 = channel 1 to right channel Channel number for sub-frame 2. 00 = Take no account of channel number (channel 2 defaults to left DAC) 01 = channel 2 to left channel 10 = channel 2 to right channel Sampling Frequency. See S/PDIF specification for details. 0001 = Sampling Frequency not indicated. Clock Accuracy of received clock. 00 = Level II 01 = Level I 10 = Level III 11 = Interface frame rate not matched to sampling frequency. Maximum Audio sample word length 0 = 20 bits 1 = 24 bits Audio Sample Word Length. 000: Word Length Not Indicated RXWL[2:0] 001 010 100 101 110 MAXWL==1 20 bits 22 bits 23 bits 24 bits 21 bits MAXWL== 0 16 bits 18 bits 19 bits 20 bits 17 bits
7:0
2Dh R46
SPDRXCHAN 3
3:0 5:4
-
2Eh
7:6
CHNUM2[1:0]
R47
SPDRXCHAN 4
3:0 5:4
FREQ[3:0] CLKACU[1:0]
2Fh
R48
SPDRXCHAN 5
0
MAXWL
-
30h 3:1 RXWL[2:0] -
All other combinations are reserved and may give erroneous operation. Data will be truncated internally when these bits are set unless WL_MASK is set. 7:4 ORGSAMP [3:0] AUDIO_N Original Sampling Frequency. See S/PDIF specification for details. 0000 = original sampling frequency not indicated Recovered Channel Status bit-1. 0 = Data word represents audio PCM samples. 1 = Data word does not represent audio PCM samples. Indicates that non-audio code (defined in IEC-61937) has been detected. 0 = Sync code not detected. 1 = Sync code detected - received data is not audio PCM. Recovered Channel Status bit-2. 0 = Copyright is asserted for this data. 1 = Copyright is not asserted for this data. Note this signal is inverted and will cause an interrupt on logic 0. PD Rev 4.0 April 2007 91
R49 SPDSTAT 31h
0
-
1
PCM_N
-
2
CPY_N
-
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WM8581
REGISTER ADDRESS BIT 3 LABEL DEEMPH DEFAULT DESCRIPTION Recovered Channel Status bit-3 0 = Recovered S/PDIF data has no pre-emphasis. 1 = Recovered S/PDIF data has pre-emphasis Indicates recovered S/PDIF clock frequency: 00 = Invalid 01 = 96kHz / 88.2kHz 10 = 48kHz / 44.1kHz 11 = 32kHz
Production Data
5:4
REC_FREQ [1:0]
--
6
UNLOCK
-
Indicates that the S/PDIF Clock Recovery circuit is unlocked or that the input S/PDIF signal is not present. 0 = Locked onto incoming S/PDIF stream. 1 = Not locked to the incoming S/PDIF stream or the incoming S/PDIF stream is not present. Chip Powerdown Control (works in tandem with the other powerdown registers): 0 = All digital circuits running, outputs are active 1 = All digital circuits in power save mode, outputs muted ADC powerdown: 0 = ADC enabled 1 = ADC disabled DAC powerdowns (0 = DAC enabled, 1 = DAC disabled) DACPD[0] = DAC1 DACPD[1] = DAC2 DACPD[2] = DAC3 DACPD[3] = DAC4 Overrides DACPD[3:0] 0 = DACs under control of DACPD[3:0] 1= All DACs are disabled. OSC power down 0 = OSC enabled 1 = OSC disabled 0 = PLLA enabled 1 = PLLA disabled 0 = PLLB enable 1 = PLLB disable S/PDIF Clock Recovery PowerDown 0 = S/PDIF enabled 1 = S/PDIF disabled S/PDIF Transmitter powerdown 0 = S/PDIF Transmitter enabled 1 = S/PDIF Transmitter disabled S/PDIF Receiver powerdown 0 = S/PDIF Receiver enabled 1 = S/PDIF Receiver disabled Determines which status register is to be read back: 000 = Error Register 001 = Channel Status Register 1 010 = Channel Status Register 2 011 = Channel Status Register 3 100 = Channel Status Register 4 101 = Channel Status Register 5 110 = S/PDIF Status Register
R50 PWRDN 1 32h
0
PWDN
0
1
ADCPD
1
5:2
DACPD[3:0]
1111
6
ALLDACPD
1
R51 PWRDN 2 33h
0
OSCPD
0
1 2 3
PLLAPD PLLBPD SPDIFPD
1 1 1
4
SPDIFTXD
1
5
SPDIFRXD
1
R52 READBACK 34h
2:0
READMUX [2:0]
000
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Production Data REGISTER ADDRESS BIT 3 LABEL CONTREAD DEFAULT 0 DESCRIPTION Continuous Read Enable. 0 = Continuous read-back mode disabled 1 = Continuous read-back mode enabled Read-back mode enable. 0 = read-back mode disabled 1 = read-back mode enabled
WM8581
4
READEN
0
R53 RESET 35h
8:0
RESET
n/a
Writing to this register will apply a reset to the device registers.
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WM8581 DIGITAL FILTER CHARACTERISTICS
PARAMETER Passband Passband ripple Stopband Stopband Attenuation Passband Passband ripple Stopband Stopband Attenuation Table 76 Digital Filter Characteristics f > 0.555fs 0.555fs -60 dB f > 0.5465fs DAC Filter 0.05 dB -3dB 0.487fs 0.05 dB 0.444fs 0.5465fs -65 dB TEST CONDITIONS ADC Filter 0.01 dB -6dB 0 0.5fs 0.01 dB 0.4535fs MIN TYP MAX UNIT
Production Data
DAC FILTER RESPONSES
0.2 0 0.15 -20 0.1
Response (dB)
Response (dB)
-40
0.05 0 -0.05 -0.1
-60
-80
-100
-0.15 -0.2 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (Fs) 0.35 0.4 0.45 0.5
-120
Figure 37 DAC Digital Filter Frequency Response - 44.1, 48 and 96KHz
Figure 38 DAC Digital Filter Ripple -44.1, 48 and 96kHz
0.2 0 0 -20
Response (dB)
Response (dB)
-0.2
-40
-0.4
-60
-0.6
-0.8 -80 -1 0 0.2 0.4 0.6 Frequency (Fs) 0.8 1 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (Fs) 0.35 0.4 0.45 0.5
Figure 39 DAC Digital Filter Frequency Response - 192KHz
Figure 40 DAC Digital Filter Ripple - 192kHz
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Production Data
WM8581
DIGITAL DE-EMPHASIS CHARACTERISTICS
0
0.4 0.3
-2 0.2
Response (dB)
-4
Response (dB)
0.1 0 -0.1 -0.2
-6
-8 -0.3 -10 0 5 10 Frequency (kHz) 15 20 -0.4 0 5 10 Frequency (kHz) 15 20
Figure 41 De-Emphasis Frequency Response (44.1KHz)
0
Figure 42 De-Emphasis Error (44.1KHz)
1 0.8
-2
0.6 0.4
Response (dB)
-4
Response (dB)
0.2 0 -0.2 -0.4
-6
-8
-0.6 -0.8
-10 0 5 10 15 Frequency (kHz) 20
-1 0 5 10 15 Frequency (kHz) 20
Figure 43 De-Emphasis Frequency Response (48kHz)
Figure 44 De-Emphasis Error (48kHz)
ADC FILTER RESPONSES
0.02 0 0.015 0.01 -20
Response (dB)
-40
Response (dB)
0.005 0 -0.005 -0.01 -0.015 -0.02
-60
-80
0
0.5
1
1.5 Frequency (Fs)
2
2.5
3
0
0.05
0.1
0.15
0.2 0.25 0.3 Frequency (Fs)
0.35
0.4
0.45
0.5
Figure 45 ADC Digital Filter Frequency Response
Figure 46 ADC Digital Filter Ripple
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WM8581
Production Data
ADC HIGH PASS FILTER
The WM8581 has a selectable digital high pass filter to remove DC offsets. The filter response is characterised by the following polynomial.
H(z) =
1 - z-1 1 - 0.9995z-1
0
Response (dB)
-5
-10
-15
0
0.0005
0.001 Frequency (Fs)
0.0015
0.002
Figure 47 ADC Highpass Filter Response
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Production Data
WM8581
APPLICATIONS INFORMATION
RECOMMENDED EXTERNAL COMPONENTS
Figure 48 Recommended-External Components - Hardware
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WM8581
Production Data
Figure 49 Recommended-External Components - Software
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Production Data
WM8581
PACKAGE DIMENSIONS
FT: 48 PIN TQFP (7 x 7 x 1.0 mm) DM004.C
b
e
25
36
37
24
E1
E
48
13
1
12
c
D1 D
L
A A2
A1 -Cccc C
SEATING PLANE
Symbols A A1 A2 b c D D1 E E1 e L ccc REF:
Dimensions (mm) MIN NOM MAX --------1.20 0.05 ----0.15 0.95 1.00 1.05 0.17 0.22 0.27 0.09 ----0.20 9.00 BSC 7.00 BSC 9.00 BSC 7.00 BSC 0.50 BSC 0.45 0.60 0.75 o o o 3.5 7 0 Tolerances of Form and Position 0.08 JEDEC.95, MS-026
NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS. B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM. D. MEETS JEDEC.95 MS-026, VARIATION = ABC. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
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WM8581 IMPORTANT NOTICE
Production Data
Wolfson Microelectronics plc ("Wolfson") products and services are sold subject to Wolfson's terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement.
Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. Customers should therefore obtain the latest version of relevant information from Wolfson to verify that the information is current.
Testing and other quality control techniques are utilised to the extent Wolfson deems necessary to support its warranty. Specific testing of all parameters of each device is not necessarily performed unless required by law or regulation.
In order to minimise risks associated with customer applications, the customer must use adequate design and operating safeguards to minimise inherent or procedural hazards. Wolfson is not liable for applications assistance or customer product design. The customer is solely responsible for its selection and use of Wolfson products. Wolfson is not liable for such selection or use nor for use of any circuitry other than circuitry entirely embodied in a Wolfson product.
Wolfson's products are not intended for use in life support systems, appliances, nuclear systems or systems where malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage. Any use of products by the customer for such purposes is at the customer's own risk.
Wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other intellectual property right of Wolfson covering or relating to any combination, machine, or process in which its products or services might be or are used. Any provision or publication of any third party's products or services does not constitute Wolfson's approval, licence, warranty or endorsement thereof. Any third party trade marks contained in this document belong to the respective third party owner.
Reproduction of information from Wolfson datasheets is permissible only if reproduction is without alteration and is accompanied by all associated copyright, proprietary and other notices (including this notice) and conditions. Wolfson is not liable for any unauthorised alteration of such information or for any reliance placed thereon.
Any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in this datasheet or in Wolfson's standard terms and conditions of sale, delivery and payment are made, given and/or accepted at that person's own risk. Wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed thereon by any person.
ADDRESS:
Wolfson Microelectronics plc Westfield House 26 Westfield Road Edinburgh EH11 2QB United Kingdom
Tel :: +44 (0)131 272 7000 Fax :: +44 (0)131 272 7001 Email :: sales@wolfsonmicro.com
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