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Micrel, Inc.
Precision Edge 2.5V, 2GHz ANY DIFF. IN-TO-LVDS SY89872U (R) PROGRAMMABLE CLOCK DIVIDER/FANOUT Precision Edge SY89872U BUFFER WITH INTERNAL TERMINATION
(R)
FEATURES
Guaranteed AC performance over temperature and voltage: * >2GHz fMAX * < 750ps tPD (matched delay between banks) * < 15ps within-device skew * < 200ps rise/fall time Low jitter design * < 1psRMS cycle-to-cycle jitter * < 10psPP total jitter Unique input termination and VT pin for DC-coupled and AC-coupled inputs: any differential inputs (LVPECL, LVDS, CML, HSTL) Precision differential LVDS outputs Matched delay: all outputs have matched delay, independent of divider setting TTL/CMOS inputs for select and reset/disable Two output banks (matched delay) * Bank A: Buffered copy of input clock (undivided) * Bank B: Divided output (/2, /4, /8, /16), two copies 2.5V power supply Wide operating temperature range: -40C to +85C Available in 16-pin (3mm x 3mm) MLF(R) package Precision Edge(R)
DESCRIPTION
This 2.5V low-skew, low-jitter, precision LVDS output clock divider accepts any high-speed differential clock input (AC or DC-coupled) CML, LVPECL, HSTL or LVDS and divides down the frequency using a programmable divider ratio to create a frequency-locked, lower speed version of the input clock. The SY89872U includes two output banks. Bank A is an exact copy of the input clock (pass through) with matched propagation delay to Bank B, the divided output bank. Available divider ratios are 2, 4, 8 and 16. In a typical 622MHz clock system this would provide availability of 311MHz, 155MHz, 77MHz or 38MHz auxiliary clock components. The differential input buffer has a unique internal termination design that allows access to the termination network through a VT pin. This feature allows the device to easily interface to different logic standards. A VREF-AC reference is included for AC-coupled applications. The SY89872U is part of Micrel's high-speed Precision Edge(R) timing and distribution family. For 3.3V applications, consider the SY89873L. For applications that require an LVPECL output, consider the SY89872U. The /RESET input asynchronously resets the divider outputs (Bank B). In the pass-through function (Bank A) the /RESET synchronously enables or disables the outputs on the next falling edge of IN (rising edge of /IN). Refer to the "Timing Diagram."
APPLICATIONS
OC-3 to OC-192 SONET/SDH applications Transponders Oscillators SONET/SDH line cards
FUNCTIONAL BLOCK DIAGRAM
/RESET, /DISABLE Enable FF
TYPICAL APPLICATION
622MHz/155.5MHz SONET Clock Generator
Enable MUX
QA /QA
622MHz LVPECL Clock In IN /IN
QA 622MHz LVDS /QA Clock Out
QB0
IN 50 VT 50 /IN VREF-AC S1 Decoder S0 Divided by 2, 4, 8 or 16
OC-12 or OC-3 Clock Generator
QB 155.5MHz LVDS /QB Clock Out
/QB0
QB1 /QB1
Bank A: 622MHz for OC-12 line card Bank B: 155.5MHz for OC-3 line card (set to divide-by-4)
Precision Edge is a registered trademark of Micrel, Inc. MicroLeadFrame and MLF are registered trademarks of Amkor Technology, Inc. M9999-020707 hbwhelp@micrel.com or (408) 955-1690
Rev.: D Amendment: /0
1
Issue Date: February 2007
Micrel, Inc.
Precision Edge(R) SY89872U
PACKAGE/ORDERING INFORMATION
VCC GND S0 S1
Ordering Information(1)
Part Number
12 11 10 9
16
15
14
13
Package Operating Type Range MLF-16 MLF-16 MLF-16 MLF-16 Industrial Industrial Industrial Industrial
Package Marking 872U 872U 872U with Pb-Free bar line indicator 872U with Pb-Free bar line indicator
Lead Finish Sn-Pb Sn-Pb NiPdAu Pb-Free NiPdAu Pb-Free
QB0 /QB0 QB1 /QB1
1 2 3 4 5 6 7 8
IN VT VREF-AC /IN
SY89872UMI SY89872UMITR(2) SY89872UMG(3) SY89872UMGTR(2, 3)
/QA
QA
/RESET /DISABLE
VCC
16-Pin MLF(R) (MLF-16)
Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25C, DC Electricals only. 2. Tape and Reel. 3. Pb-Free package is recommended for new designs.
PIN DESCRIPTION
Pin Number 1, 2, 3, 4 5, 6 7, 14 8 Pin Name QB0, /QB0 QB1, /QB1 QA, /QA VCC /RESET, /DISABLE Pin Function Differential LVDS Compatible Outputs: Divide by 2, 4, 8, 16. Unused outputs must be terminated with 100 across the pin (Q, /Q). Differential LVDS Compatible Undivided Output Clock. Positive Power Supply: Bypass with 0.1F/0.01F low ESR capacitors. Output Reset and Output Enable/Disable: Internal 25k pull-up. Input threshold is VCC/2. Logic LOW will reset the divider select, and align Bank A and Bank B edges. In addition, when LOW, Bank A and Bank B will be disabled. Differential Reference Input Clock: Internal 50 termination resistors to VT input. See "Input Interface Applications" section. Reference Voltage: Equal to VCC-1.4V (approx.), and used for AC-coupled applications. Maximum sink/source current is 0.5mA. See "Input Interface Applications" section. Termination Center-Tap: For DC-coupled CML and LVDS inputs, leave this pin floating. See "Input Interface Applications" section. Ground. Select Pins: LVTTL/CMOS logic levels. Internal 25k pull-up resistor. Logic HIGH if left unconnected (divided by 16 mode). S0 = LSB. Input threshold is VCC/2.
12, 9 10 11 13 15, 16
IN, /IN VREF-AC VT GND S1, S0
TRUTH TABLE
/RESET /DISABLE 1 1 1 1 0
S1 0 0 1 1 X
S0 0 1 0 1 X
Bank A Output Input Clock Input Clock Input Clock Input Clock QA = Low, /QA = High(1)
Bank B Outputs Input Clock /2 Input Clock /4 Input Clock /8 Input Clock /16 QB0 = Low, /QB0 = High(2) QB1 = Low, /QB1 = High(2)
Note 1. On the next negative transition of the input signal. Note 2. Asynchronous reset/disable function. (See "Timing Diagram") M9999-020707 hbwhelp@micrel.com or (408) 955-1690
2
Micrel, Inc.
Precision Edge(R) SY89872U
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC) .................................. -0.5V to +6.0V Input Voltage (VIN) ......................................... -0.5V to VCC LVDS Output Current (IOUT) .................................... 10mA Input Current IN, /IN (IIN) .......................................... 50mA VREF-AC Input Sink/Source Current (IVREF-AC),Note 3 . 2mA Lead Temperature (soldering, 20sec.) ...................... 260C Storage Temperature (TS) ....................... -65C to +150C
Operating Ratings(Note 2)
Supply Voltage Range ............................ 2.375V to 2.625V Ambient Temperature (TA) ......................... -40C to +85C Package Thermal Resistance MLF(R) (JA) Still-Air ............................................................. 60C/W 500lfpm ............................................................ 54C/W MLF(R) (JB), Note 4 Junction-to-Board ............................................ 32C/W
Note 1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratlng conditions for extended periods may affect device reliability. Note 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. Note 3. Due to the limited drive capability use for input of the same package only. Note 4. Junction-to-board resistance assumes exposed pad is soldered (or equivalent) to the device's most negative potential on the PCB.
DC ELECTRICAL CHARACTERISTICS(Note 1, 2)
TA= -40C to +85C; Unless otherwise stated. Symbol VCC ICC RIN VIH VIL VIN VDIFF_IN |IIN| VREF-AC
Note 1. Note 2. Note 3. Note 4. Note 5. Note 6.
Parameter Power Supply Voltage Power Supply Current Differential Input Resistance (IN-to-/IN) Input High Voltage IN, /IN Input Low Voltage IN, /IN Input Voltage Swing Differential Input Voltage Swing Input Current IN, /IN Reference Voltage
Condition
Min 2.375
Typ 2.5 75
Max 2.625 110 110 VCC+0.3 VCC+0.2 3.6
Units V mA V V V V
No load, max. VCC 90 Note 3 Note 3 Notes 3, 4 Notes 3, 4, 5 Note 3 Note 6 0.1 -0.3 0.1 0.2
100
45 VCC -1.525VCC-1.425 VCC-1.325
mA V
The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. Specification for packaged product only. Due to the internal termination (see "Input Buffer Structure" section) the input current depends on the applied voltages at IN, /IN and VT inputs. Do not apply a combination of voltages that causes the input current to exceed the maximum limit! See "Timing Diagram" for VIN definition. VIN (max.) is specified when VT is floating. See Figures 1c and 1d for VDIFF definition. Operating using VIN is limited to AC-coupled PECL or CML applications only. Connect directly to VT pin.
M9999-020707 hbwhelp@micrel.com or (408) 955-1690
3
Micrel, Inc.
Precision Edge(R) SY89872U
LVDS OUTPUTS DC ELECTRICAL CHARACTERISTICS(Note 1, 2)
VCC = 2.5V 5%; TA = -40C to +85C; Unless otherwise stated. Symbol VOUT VOH VOL VOCM VOCM
Note 1. Note 2. Note 3. Note 4. Note 5.
Parameter Output Voltage Swing Output High Voltage Output Low Voltage Output Common Mode Voltage Change in Common Mode Voltage
Condition Note 5 Note 3 Note 3 Note 4
Min 250
Typ 350
Max 450 1.475
Units mV V V
0.925 1.125 -50 1.375 50
V mV
The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. Specification for packaged product only. Measured as per Figure 1a, 100 across Q and /Q outputs. Measured as per Figure 1b. See Figure 1c.
LVTTL/CMOS INPUTS DC ELECTRICAL CHARACTERISTICS(Note 1, 2)
VCC = 2.5V 5%; TA = -40C to +85C; Unless otherwise stated. Symbol VIH VIL IIH IIL
Note 1. Note 2.
Parameter Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current
Condition
Min 2.0 0 -125 -
Typ - - - -
Max VCC 0.8 20 -300
Units V V A A
The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. Specification for packaged product only.
M9999-020707 hbwhelp@micrel.com or (408) 955-1690
4
Micrel, Inc.
Precision Edge(R) SY89872U
AC ELECTRICAL CHARACTERISTICS(Note 1, 2)
VCC = 2.5V 5%; TA = -40C to +85C; Unless otherwise stated. Symbol fMAX tPD tSKEW Parameter Maximum Toggle Frequency Maximum Input Frequency Differential Propagation Delay IN to Q Within-Device Skew (differential) (QB0-to-QB1) Within-Device Skew (differential) (Bank A-to-Bank B) Part-to-Part Skew (differential) trr Tjitter tr, tf
Note 1. Note 2. Note 3. Note 4. Note 5. Note 6. Note 7.
Condition Output Swing: 200mV Note 3 Input Swing: <400mV Input Swing: 400mV Note 4 Note 4 Note 4 Note 5 Note 6 Note 7
Min 2 3.2 500 450
Typ
Max
Units GHz GHz
625 575 7 12
750 700 15 30 250
ps ps ps ps ps ps
Reset Recovery Time Cycle-to-Cycle Jitter Total Jitter Rise / Fall Time (20% to 80%)
600 1 10 70 130 200
psRMS psPP ps
Measured with 400mV input signal, 50% duty cycle. 100 termination between Q and /Q, unless otherwise stated. Specification packaged product only. Bank A (pass-through) maximum frequency is limited by the output stage. Bank B (input-to-output /2, /4, /8, /16) can accept an input frequency >3GHz, while Bank A will be slew rate limited. Skew is measured between outputs under identical transitions. See "Timing Diagram." Cycle-to-cycle jitter definition: the variation in period between adjacent cycles over a random sample of adjacent cycle pairs. Tjitter_cc=Tn-Tn+1, where T is the time between rising edges of the output signal. Total jitter definition: with an ideal clock input, of frequency fMAX (device), no more than one output edge in 1012 output edges will deviate by more than the specified peak-to-peak jitter value.
M9999-020707 hbwhelp@micrel.com or (408) 955-1690
5
Micrel, Inc.
Precision Edge(R) SY89872U
LVDS OUTPUT
50 VOUT VOH, VOL VOH, VOL 100 50 VOCM, VOCM
GND
GND
Figure 1a. LVDS Differential Measurement
Figure 1b. LVDS Common Mode Measurement
DEFINITION OF SINGLE-ENDED AND DIFFERENTIAL SWING
VIN, VOUT 350mV (typical)
VDIFF_IN, VDIFF_OUT 700mV (typical)
Figure 1c. Single-Ended Swing
Figure 1d. Differential Swing
TIMING DIAGRAM
/RESET
VCC/2 tRR
IN /IN VIN Swing tPD
/QB VOUT Swing QB
QA /QA
M9999-020707 hbwhelp@micrel.com or (408) 955-1690
6
Micrel, Inc.
Precision Edge(R) SY89872U
TYPICAL OPERATING CHARACTERISTICS
VCC = 2.5V, VIN = 400mV, TA = 25C, unless otherwise stated.
QA Output Amplitude vs. Frequency
400 350 QA AMPLITUDE (mV) 300 250 200 150 100 50 1000 1500 2000 2500 3000 3500 0 0 500 PROPAGATION DELAY (ps)
700
IN to Q Propagation Delay vs. Input Swing
PROPAGATION DELAY (ps)
IN to Q Propagation Delay vs. Temperature
600
650
575
600
550
550
525
1000
1200
FREQUENCY (MHz)
INPUT SWING (mV)
QA @622MHz and QB @155.5MHz (Divide-by-4)
QA
1400
0
500
500 -40 -20 0 20 40 60 80 100 TEMPERATURE (C)
200
400
600
800
1.25GHz Output
622MHz Output
/Q
Output Swing (100mV/div.)
/QA QB0
155.5MHz Output
Output Swing (50mV/div.)
Q
/QB0
TIME (1ns/div.)
TIME (150ps/div.)
2GHz Output
/Q
Output Swing (50mV/div.)
Q
TIME (100ps/div.)
M9999-020707 hbwhelp@micrel.com or (408) 955-1690
7
Micrel, Inc.
Precision Edge(R) SY89872U
INPUT BUFFER STRUCTURE
VCC
VCC
1.86k
1.86k
25k S0 S1 /RESET
R
1.86k IN 50 VT 50 /IN GND
1.86k
R
GND
Figure 2a. Simplified Differential Input Buffer
Figure 2b. Simplified TTL/CMOS Input Buffer
M9999-020707 hbwhelp@micrel.com or (408) 955-1690
8
Micrel, Inc.
Precision Edge(R) SY89872U
INPUT INTERFACE APPLICATIONS
VCC
VCC VCC VCC VCC
VCC
IN
IN CML /IN SY89872U GND NC NC VT VREF-AC 0.01F GND VCC VT VREF-AC CML /IN SY89872U
PECL
IN
/IN SY89872U GND 0.01F VCC
* Bypass with 0.01F to GND
VCC-2V* VT 50 NC VREF-AC
Figure 3a. DC-Coupled CML Input Interface
Figure 3b. AC-Coupled CML Input Interface
Figure 3c. DC-Coupled PECL Input Interface
VCC
VCC
VCC
VCC
VCC
VCC
IN IN PECL /IN 50 50 VCC GND GND 0.01F VT VREF-AC SY89872U GND NC NC VT NC VREF-AC GND LVDS /IN SY89872U GND VT VREF-AC IN HSTL /IN SY89872U
Figure 3d. AC-Coupled PECL Input Interface
Figure 3e. LVDS Input Interface
Figure 3f. HSTL Input Interface
RELATED PRODUCT AND SUPPORT DOCUMENTATION
Part Number SY89871U SY89873L Function 2.5GHz Any Diff. In-to-LVPECL Programmable Clock Divider/Fanout Buffer w/Internal Termination 3.3V, 2GHz Any Diff. In-to-LVDS Programmable Clock Divider/Fanout Buffer MLF(R) HBW Solutions Application Note New Products and Applications Data Sheet Link http://www.micrel.com/product-info/products/sy89871u.shtml http://www.micrel.com/product-info/products/sy89873l.shtml http://www.amkor.com/products/notes_papers/mlf_appnote_0902.pdf http://www.micrel.com/product-info/products/solutions.shtml
M9999-020707 hbwhelp@micrel.com or (408) 955-1690
9
Micrel, Inc.
Precision Edge(R) SY89872U
16-PIN MicroLeadFrame(R) (MLF-16)
Package EP- Exposed Pad
Die
CompSide Island
Heat Dissipation Heat Dissipation VEE Heavy Copper Plane VEE Heavy Copper Plane
PCB Thermal Consideration for 16-Pin MLF(R) Package (Always solder, or equivalent, the exposed pad to the PCB) Package Notes: Note 1. Package meets Level 2 moisture sensitivity classification, and is shipped in dry-pack form. Note 2. Exposed pads must be soldered to a ground for proper thermal management.
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL
+ 1 (408) 944-0800
FAX
+ 1 (408) 944-0970
WEB
http://www.micrel.com
The information furnished by Micrel in this datasheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2005 Micrel, Incorporated. M9999-020707 hbwhelp@micrel.com or (408) 955-1690
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