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Freescale Semiconductor Technical Data
Document Number: MC13783/D Rev. 3.4, 3/2007
MC13783
MC13783
Power Management and Audio Circuit
Device MC13783
Package Information Plastic Package 10 x 10 mm package
Ordering Information Device Marking or Operating Temperature Range -30 to +85C Package MAPBGA-247
1
Introduction
Contents
1 2 3 4 5 6 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Signal Descriptions . . . . . . . . . . . . . . . . . . . . 6 Electrical Characteristics . . . . . . . . . . . . . . 16 Functional Description . . . . . . . . . . . . . . . . 17 Package Information . . . . . . . . . . . . . . . . . . 48 Product Documentation . . . . . . . . . . . . . . . . 49
The MC13783 is a highly integrated power management and audio component dedicated to handset and portable applications covering GSM, GPRS, EDGE, and UMTS standards. The MC13783 implements high-performance audio functions suited to high-end applications such as smartphones and UMTS handsets. The MC13783 provides the following key benefits: * Full power management and audio functionality in one module optimizes system size. * High level of integration reduces the power management and audio system bill of materials. * Versatile solution offers large possibilities of flexibility through simple programming (64 registers of 24-bit data). * Implemented DVS saves significant battery resources in every mode (compatibility with a large number of processors). * Dual channel voice ADC improves intelligibility.
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. (c) Freescale Semiconductor, Inc., 2005, 2006, 2007. All rights reserved.
Introduction
The detailed block diagram of the MC13783 in Figure 1 shows the wide functionality of the MC13783, including the following features: * Battery charger interface for wall charging and USB charging * 10 bit ADC for battery monitoring and other readout functions * Buck switchers for direct supply of the processor cores * Boost switcher for backlight and USB on the go supply * Regulators with internal and external pass devices * Transmit amplifiers for two handset microphones and a headset microphone * Receive amplifiers for earpiece, loudspeaker, headset and line out * 13 bit Voice CODEC with dual ADC channel and both narrow and wide band sampling * 13 bit Stereo recording from an analog input source such as FM radio * 16 bit Stereo DAC supporting multiple sample rates * Dual SSI audio bus with network mode for connection to multiple devices * Power control logic with processor interface and event detection * Real time clock and crystal oscillator circuitry * Dual SPI control bus with arbitration mechanism * Multiple backlight drivers and LED control including funlight support * USB FS/LS transceiver with OTG and CEA-936-A Carkit support * Touchscreen interface The main functions of the MC13783 are described in the following sections. A detailed block diagram is shown in Figure 1, on page 3.
MC13783 Technical Data, Rev. 3.4 2 Freescale Semiconductor
Introduction
CHRGISNSN
CHRGISNSP
CHRGMOD1
CHRGMOD0
CHRGCTRL
CHRGSE1B
GNDLEDTC
GNDATLAS
GNDLEDBL
CHRGRAW
GNDCHRG
CHRGLED
BATTISNS
REFATLAS
LEDMD1 LEDMD2 LEDMD3 LEDMD4
LOBATB
LEDAD1 LEDAD2
LEDKP
LEDR1 LEDG1 LEDB1
LEDR2 LEDG2 LEDB2
LEDR3 LEDG3 LEDB3
GNDSUB1 GNDSUB2 GNDSUB3 GNDSUB4 GNDSUB5 GNDSUB6 GNDSUB7 GNDSUB8 PWR Gate Drive & Chg Pump
BATTFET
VATLAS
BPFET
REFC
REFD
REFA
REFB
BATT
BP
Battery Interface & Protection
Charger Interface and Control: 4 bit DAC, Clamp, Protection, Trickle Generation
Backlight LED Drive
Tri-Color LED Drive
VATLAS Gen
Audio References
PWGT1EN PWGT1DRV PWGT2EN PWGT2DRV
BATTDETB ADREF ADOUT GNDADC ADIN5 ADIN6 ADIN7 ADIN8 ADIN9 ADIN10 ADIN11 TSX1 TSX2 TSY1 TSY2 ADTRIG PRIVCC PRICS PRICLK PRIMOSI PRIMISO SECVCC SECCS SECCLK SECMOSI SECMISO GNDSPI MC2B Voltage / Current Sensing & Translation
From Li Cell Thermal Warning Detection A/D Result A/D Control MUX 10 Bit A/D Trigger Handling A/D Control Touch Screen Interface Shift Register BUCK2B 500 mA Shift Register 4 BOOST 350 mA Combinational Logic Secondary SPI Interface Secondary SPI Registers Shift Register DVS CONTROL Pass FET Pass FET Pass FET Pass FET Pass FET Pass FETs Result Registers To Core Logic O/P Drive O/P Drive A/D Result LOBAT BP + Ref SPI LDO Monitoring and EOL Detection To Interrupt Section O/P Drive To Interrupt Section BUCK 1A 500 mA O/P Drive SW1AIN SW1AOUT GNDSW1A SW1AFB SW1BIN SW1BOUT GNDSW1B SW1BFB SW1ABSPB SW2AIN SW2AOUT GNDSW2A SW2AFB SW2BIN SW2BOUT GNDSW2B SW2BFB SW2ABSPB SW3IN SW3OUT SW3FB GNDSW3 DVSSW1A DVSSW1B DVSSW2A DVSSW2B VAUDIO Rbias Detect Microphone Bias Shift Register VIOLO VIOHI VDIG Input Selector VRFDIG VINAUDIO VAUDIO VINIOLO VIOLO VINIOHI VIOHI VINDIG VDIG VINRFDIG VRFDIG VINRFREF VRFREF VRFCP VRFBG VINSIM VSIM VESIM VINVIB VVIB VINGEN VGEN VINCAM VCAM GNDREG1 GNDREG2 VRF1DRV VRF1 VRF2DRV VRF2 VMMC1DRV VMMC1 VMMC2DRV VMMC2 SIMEN ESIMEN VIBEN REGEN GPO1 To Trimmed Circuits External LDO GPO's GPO2 GPO3 GPO4 PWRFAIL MEMHLDDRV
SPI Arbitra tion
BUCK 1B 500 mA
O/P Drive
LDOs
BUCK 2A 500 mA
Primary SPI Interface
Config Reg
Primary SPI Registers
MC1RB
Rbias
MC1LB
Rbias
MC1LIN
Amc1l
PGA
PGA
A to D
MC1RIN
Amc1r Input Selector
MC13783
5
VRFREF VRFCP VRFBG
MC2IN
Amc2
PGA
PGA
A to D VSIM VESIM Pass FETs
TXIN
Atxin From USB CEA936 Asp VVIB VGEN Voice Codec VCAM Pass FET Pass FET Pass FET
TXOUT SPP
D to A
SPM CDCOUT VINLSP LSPP Alsp LSPM Selector
PGAm
VRF1 VRF2 VMMC1 Stereo D to A VMMC2 Regulator External Enable Control 4 SPI
GNDLSP LSPL HSR HSDET HSPGF HSPGS Phantom Ground Ahsl HSL HSLDET RXOUTR Arx RXOUTL RXINR RXINL PLLLPF GNDPLL BCL1 FS1 RX1 TX1 BCL2 FS2 RX2 TX2 CLIA CLIB 32 kHz Crystal Osc Core Control Logic, Timers, & Interrupts Audio Bus Interface 32 kHz Internal Osc BP To USB CEA936 Detect Router Power Fail Detect LCELL Switch PCUT PLL 32x PLL Monitor Timer RTC SPI Result Registers Interrupt Inputs Enables & Control 32 kHz Buffer USB On-The-Go Switchers To/From Audio Ref + USB Car Kit Detect Ref + Detect Ahsr Mixer & Mono Adder & Selector
PGAst
Arxin
Control Logic
Trim-In-Package
Memory Hold
VBKUP1 VBKUP2 CSOUT
LICELL To Charger Li Cell Charger To Interrupt Section SPARE2 VBUS 5V Pass FET SPARE4
USB/RS-232 Bus
VUSB 3.3V Pass FET GNDUSBA GNDUSBD USBVCC VINBUS UMOD0 UMOD1 UID USBEN VUSB
STANDBYPRI
WDI RESETBMCU
UDATVP
ICTEST ICSCAN PUMS1 PUMS2 PUMS3 CLKSEL
GNDAUD1
GNDAUD2
GNDAUD3
GNDAUD4 GNDAUD5
GNDCTRL
STANDBYSEC
GNDRTC
Figure 1. MC13783 Detailed Block Diagram
MC13783 Technical Data, Rev. 3.4 Freescale Semiconductor 3
ON1B ON2B ON3B CLK32K CLK32KMCU
RESETB PWRRDY USEROFF
USE0VM UTXENB
PRIINT SECINT
URCVD URXVP URXVM UDP UDM
XTAL1
XTAL2
VBUS
Introduction
1.1
Audio
The audio section is composed of microphone amplifiers and speaker amplifiers, a voice CODEC, and a stereo DAC. Three microphone amplifiers are available for amplification of two handset microphones and of the headset microphone. The feedback networks are fully integrated for a current input arrangement. A line input buffer amplifier is provided for connecting external sources. All microphones have their own stabilized supply with an integrated microphone sensitivity setting. The microphone supplies can be disabled. The headset microphone supply has a fully integrated microphone detection. Several speaker amplifiers are provided. A bridged earpiece amplifier is available to drive an earpiece. Also, a battery supplied bridged amplifier with thermal protection is included to drive a low ohmic speaker for speakerphone and alert functionality. The performance of this amplifier allows it to be used as well for earpiece drive to support applications with a single transducer combining earpiece, speakerphone and alert functionality, thus avoiding the use of multiple transducers. A left audio out is provided which in combination with a discrete power amplifier and the integrated speaker amplifier allows for a stereo speaker application. Two, single-ended amplifiers are included for the stereo headset drive including headset detection. The stereo headset return path is connected to a phantom ground which avoids the use of large DC decoupling capacitors. The additional stereo receive signal outputs can be used for connection to external accessories like a car kit. Via a stereo line in, external sources such as an FM radio or standalone midi ringer can be applied to the receive path. A voice CODEC with a dual path ADC is implemented following GSM audio requirements. Both narrow band and wide band voice is supported. The dual path ADC allows for conversion of two microphone signal sources at the same time for noise cancellation or stereo applications as well as for stereo recording from sources like FM radio. A 16-bit stereo DAC is available which supports multi-clock modes. An on-board PLL ensures proper clock generation. The voice CODEC and the stereo DAC can be operated at the same time via two interchangeable busses supporting master and slave mode, network mode, as well as the different protocols like I2S. Volume control is included in both transmit and receive paths. The latter also includes a balance control for stereo. The mono adder in the receive path allows for listening to a stereo source on a mono transducer. The receive paths for stereo and mono are separated to allow the two sources to be played back simultaneously on different outputs. The different sources can be analog mixed and two sources on the SSI configured in network mode can be mixed as well.
1.2
Switchers and Regulators
The MC13783 provides most of the telephone reference and supply voltages. Four down converters and an up converter are included. The down, or buck, converters provide the supply to the processors and to other low voltage circuits such as IO and memory. The four down converters can be combined into two higher power converters. Dynamic voltage scaling is provided on each of the down converters. This allows under close processor control to adapt the output voltage of the converters to minimize processor current drain. The up, or boost, converter supplies the white backlight LEDs and the
MC13783 Technical Data, Rev. 3.4 4 Freescale Semiconductor
Introduction
regulators for the USB transceiver. The boost converter output has a backlight headroom tracking option to reduce overall power consumption. The regulators are directly supplied from the battery or from the switchers and include supplies for IO and peripherals, audio, camera, multi media cards, SIM cards, memory and the transceivers. Enables for external discrete regulators are included as well as a vibrator motor regulator. A dedicated preamplifier audio output is available for multifunction vibrating transducers. Drivers for power gating with external NMOS transistors are provided including a fully integrated charge pump. This will allow to power down parts of the processor to reduce leakage current.
1.3
Battery Management
The MC13783 supports different charging and supply schemes including single path and serial path charging. In single path charging, the phone is always supplied from the battery and therefore always has to be present and valid. In a serial path charging scheme, the phone can operate directly from the charger while the battery is removed or deeply discharged. The charger interface provides linear operation via an integrated DAC and unregulated operation like used for pulsed charging. It incorporates a standalone trickle charge mode in case of a dead battery with LED indicator driver. Over voltage, short circuit and under voltage detectors are included as well as charger detection and removal. The charger includes the necessary circuitry to allow for USB charging and for reverse supply to an external accessory. The battery management is completed by a battery presence detector and an A to D converter that serves for measuring the charge current, battery and other supply voltages as well as for measuring the battery thermistor and die temperature.
1.4
Logic
The MC13783 is fully programmable via SPI bus. Additional communication is provided by direct logic interfacing. Default startup of the device is selectable by hard-wiring the power up mode select pins. Both the call processor and the applications processor have full access to the MC13783 resources via two independent SPI busses. The primary SPI bus is able to allow the secondary SPI bus to control all or some of the registers. On top of this an arbitration mechanism is built in for the audio, the power and ADC functions. This together will avoid programming conflicts in case of a dual processor type of application. The power cycling of the phone is driven by the MC13783. It has the interfaces for the power buttons and dedicated signaling interfacing with the processor. It also ensures the supply of the memory and other circuits from the coin cell in case of brief power failures. A charger for the coin cell is included as well. Several pre-selectable power modes are provided such as SDRAM self refresh mode and user off mode. The MC13783 provides the timekeeping based on an integrated low power oscillator running with a standard watch crystal. This oscillator is used for internal clocking, the control logic, and as a reference for the switcher PLL. The timekeeping includes time of day, calendar and alarm. The clock is put out to the processors for reference and deep sleep mode clocking.
MC13783 Technical Data, Rev. 3.4 Freescale Semiconductor 5
Signal Descriptions
1.5
Miscellaneous Functions
The drivers and comparators for a USB On-the-Go and a CEA-936-A compatible USB carkit including audio routing, as well as RS232 interfaces are provided. Special precautions are taken to allow for specific booting and accessory detection modes. Current sources are provided to drive tricolored funlights and signaling LEDs. The funlights have preprogrammed lighting patterns. The wide programmability of the tricolored LED drivers allows for applications such as audio modulation. Three backlight drivers with auto dimming are included as well for keypad and dual display backlighting. A dedicated interface in combination with the A to D converter allow for precise resistive touchscreen reading. Pen touch wake up is included.
2
Signal Descriptions
Table 1. Pinout Listing
Pin Charger CHRGRAW A18 A19 B19 C18 B15 B17 C14 B13 EHV 1. Charger input 2. Output to battery supplied accessories Driver output for charger path FETs M1 and M2 1. Driver output for dual path regulated BP FET M4 2. Driver output for separate USB charger path FETs M5 and M6 Charge current sensing point 1 Charge current sensing point 2 1. Application supply point 2. Input supply to the MC13783 core circuitry 3. Application supply voltage sense Driver output for battery path FET M3 Battery current sensing point 1 1. Battery positive terminal 2. Battery current sensing point 2 3. Battery supply voltage sense Selection of the mode of charging Location Rating* Function
The below pinout description gives the pin name per functional block with its row-column coordinates, its maximum voltage rating, and a functional description.
CHRGCTRL BPFET CHRGISNSP CHRGISNSN BP
EHV EHV MV MV MV
BATTFET BATTISNS BATT
A12 A14 D15
MV MV MV
CHRGMOD0
D17
LV
* The maximum voltage rating is given per category of pins: * EHV for Extended High Voltage (20 V) * HV for High Voltage (7.5 V) * EMV for Extended Medium Voltage (5.5 V) * MV for Medium Voltage (4.65 V) * LV for Low Voltage (3.1 V)
MC13783 Technical Data, Rev. 3.4 6 Freescale Semiconductor
Signal Descriptions
Table 1. Pinout Listing (continued)
Pin CHRGMOD1 CHRGSE1B CHRGLED GNDCHRG LED Drivers LEDMD1 LEDMD2 LEDMD3 LEDMD4 LEDAD1 LEDAD2 LEDKP LEDR1 LEDG1 LEDB1 LEDR2 LEDG2 LEDB2 LEDR3 LEDG3 LEDB3 GNDLEDBL GNDLEDTC MC13783 Core VATLAS REFATLAS GNDATLAS Switchers SW1AIN K18 MV Switcher 1A input C12 B11 H11 LV LV Regulated supply output for the MC13783 core circuitry Main bandgap reference Ground for the MC13783 core circuitry B8 F9 E9 C9 C8 E8 C7 B10 E11 F11 E10 F10 G10 F8 C10 B9 H10 J10 EMV EMV EMV EMV EMV EMV EMV EMV EMV EMV EMV EMV EMV EMV EMV EMV Main display backlight LED driver output 1 Main display backlight LED driver output 2 Main display backlight LED driver output 3 Main display backlight LED driver output 4 Auxiliary display backlight LED driver output 1 Auxiliary display backlight LED driver output 2 Keypad lighting LED driver output Tricolor red LED driver output 1 Tricolor green LED driver output 1 Tricolor blue LED driver output 1 Tricolor red LED driver output 2 Tricolor green LED driver output 2 Tricolor blue LED driver output 2 Tricolor red LED driver output 3 Tricolor green LED driver output 3 Tricolor blue LED driver output 3 Ground for backlight LED drivers Ground for tricolor LED drivers Location A16 F15 D13 J11 Rating* LV LV EHV Function Selection of the mode of charging Charger forced SE1 detection input Trickle LED driver output Ground for charger interface
* The maximum voltage rating is given per category of pins: * EHV for Extended High Voltage (20 V) * HV for High Voltage (7.5 V) * EMV for Extended Medium Voltage (5.5 V) * MV for Medium Voltage (4.65 V) * LV for Low Voltage (3.1 V)
MC13783 Technical Data, Rev. 3.4 Freescale Semiconductor 7
Signal Descriptions
Table 1. Pinout Listing (continued)
Pin SW1AOUT SW1AFB DVSSW1A GNDSW1A SW1BIN SW1BOUT SW1BFB DVSSW1B GNDSW1B SW2AIN SW1ABSPB SW2AOUT SW2AFB DVSSW2A GNDSW2A SW2BIN SW2BOUT SW2BFB DVSSW2B GNDSW2B SW2ABSPB SW3IN SW3OUT SW3FB GNDSW3 Power Gating PWGT1EN PWGT1DRV PWGT2EN L14 M15 L15 LV EMV LV Power gate driver 1 enable Power gate driver 1 output Power gate driver 2 enable Location K17 L18 J15 L17 N18 N17 M18 K15 M17 P18 P11 R18 P15 H15 P17 U18 T18 R17 J14 T17 R12 J17 H18 H17 J18 Rating* MV LV LV MV MV LV LV MV LV MV LV LV MV MV LV LV LV MV HV HV Switcher 1A output Switcher 1A feedback Dynamic voltage scaling logic input for switcher 1A Ground for switcher 1A Switcher 1B input Switcher 1B output Switcher 1B feedback Dynamic voltage scaling logic input for switcher 1B Ground for switcher 1B Switcher 2A input SW1 mode configuration Switcher 2A output Switcher 2A feedback Dynamic voltage scaling logic input for switcher 2A Ground for switcher 2A Switcher 2B input Switcher 2B output Switcher 2B feedback Dynamic voltage scaling logic input for switcher 2B Ground for switcher 2B SW2 mode configuration Switcher 3 input Switcher 3 output Switcher 3 feedback Ground for switcher 3 Function
* The maximum voltage rating is given per category of pins: * EHV for Extended High Voltage (20 V) * HV for High Voltage (7.5 V) * EMV for Extended Medium Voltage (5.5 V) * MV for Medium Voltage (4.65 V) * LV for Low Voltage (3.1 V)
MC13783 Technical Data, Rev. 3.4 8 Freescale Semiconductor
Signal Descriptions
Table 1. Pinout Listing (continued)
Pin PWGT2DRV Regulators VINAUDIO VAUDIO VINIOLO VIOLO VINIOHI VIOHI VINDIG VDIG VINRFDIG VRFDIG VINRFREF VRFREF VRFCP VRFBG VINSIM VSIM VESIM VINVIB VVIB VINGEN VGEN VINCAM VCAM VRF2DRV VRF2 VRF1DRV VRF1 U12 U10 U13 V13 B7 B6 R11 U11 K5 K2 K7 G3 G2 C11 F2 E3 F3 G5 E2 G17 G18 V12 V11 J6 J5 K8 J3 MV LV MV LV MV LV MV LV MV LV MV LV LV LV MV LV LV MV LV MV LV MV LV MV LV MV LV Input regulator audio Output regulator audio Input regulator low voltage IO Output regulator low voltage IO Input regulator high voltage IO Output regulator high voltage IO Input regulator general digital Output regulator general digital Input regulator transceiver digital Output regulator transceiver digital Input regulator transceiver reference Output regulator transceiver reference Output regulator transceiver charge pump Bandgap reference output for transceiver Input regulator SIM card and eSIM card Output regulator SIM card Output regulator eSIM card Input regulator vibrator motor Output regulator vibrator motor Input regulator graphics accelerator Output regulator graphics accelerator Input regulator camera Output regulator camera Drive output regulator transceiver Output regulator transceiver Drive output regulator transceiver Output regulator transceiver Location K14 Rating* EMV Power gate driver 2 output Function
* The maximum voltage rating is given per category of pins: * EHV for Extended High Voltage (20 V) * HV for High Voltage (7.5 V) * EMV for Extended Medium Voltage (5.5 V) * MV for Medium Voltage (4.65 V) * LV for Low Voltage (3.1 V)
MC13783 Technical Data, Rev. 3.4 Freescale Semiconductor 9
Signal Descriptions
Table 1. Pinout Listing (continued)
Pin VMMC1DRV VMMC1 VMMC2DRV VMMC2 SIMEN ESIMEN VIBEN REGEN GPO1 GPO2 GPO3 GPO4 GNDREG1 GNDREG2 USB/RS232 UDP C2 EMV 1. USB transceiver cable interface, D+ 2. RS232 transceiver cable interface, transmit output or receive input signal 1. USB transceiver cable interface, D2. RS232 transceiver cable interface, receive input or transmit output signal USB on the go transceiver cable ID resistor connection 1. USB processor interface transmit data input (logic level version of D+/D-) or transmit positive data input (logic level version of D+) 2. Optional USB processor interface receive data output (logic level version of D+/D-) 3. RS232 processor interface 1. USB processor interface transmit single ended zero signal input or transmit minus data input (logic level version of D-) 2. Optional USB processor interface received single ended zero output 3. Optional RS232 processor interface 1. USB processor interface transmit enable bar Location L7 K6 J2 K3 D19 F16 E19 E18 G8 F6 E5 G9 N12 K10 Rating* MV LV MV LV LV LV LV LV LV LV LV LV Function Drive output regulator MMC1 module Output regulator MMC1 module Drive output regulator MMC2 module Output regulator MMC2 module VSIM enable input VESIM enable input VVIB enable input Regulator enable input General purpose output 1 to be used for enabling a discrete regulator General purpose output 2 to be used for enabling a discrete regulator General purpose output 3 to be used for enabling a discrete regulator General purpose output 4 to be used for enabling a discrete regulator Ground for regulators 1 Ground for regulators 2
UDM
D2
EMV
UID UDATVP
F7 C5
EMV LV
USE0VM
C6
LV
UTXENB
C4
LV
* The maximum voltage rating is given per category of pins: * EHV for Extended High Voltage (20 V) * HV for High Voltage (7.5 V) * EMV for Extended Medium Voltage (5.5 V) * MV for Medium Voltage (4.65 V) * LV for Low Voltage (3.1 V)
MC13783 Technical Data, Rev. 3.4 10 Freescale Semiconductor
Signal Descriptions
Table 1. Pinout Listing (continued)
Pin URCVD URXVP URXVM Location B5 B3 B2 Rating* LV LV LV Function Optional USB receiver processor interface differential data output (logic level version of D+/D-) Optional USB receiver processor interface data output (logic level version of D+) 1. Optional USB receiver processor interface data output (logic level version of D-) 2. Optional RS232 processor interface USB transceiver operation mode selection at power up 0 USB transceiver operation mode selection at power up 1 Bootmode enable for USB/RS232 interface Input for VBUS and VUSB regulators for USB on the go mode When in common input configuration, shorted to CHRGRAW 1. USB transceiver cable interface VBUS 2. Output VBUS regulator in USB on the go mode When in separate input configuration, not shorted to CHRGRAW 1. USB transceiver cable interface VBUS 2. Output VBUS regulator in USB on the go mode Output VUSB regulator as used by the USB transceiver Supply for processor interface Ground for USB transceiver and USB cable
UMOD0 UMOD1 USBEN VINBUS VBUS
H7 G6 C3 B4 D3
LV LV LV EMV EHV
EMV
VUSB USBVCC GNDUSBA
F5 E7 A1 A2 B1 K9
MV LV -
GNDUSBD Control Logic ON1B ON2B ON3B WDI RESETB RESETBMCU STANDBYPRI STANDBYSEC LOBATB
-
Ground for USB processor interface
E16 E15 G14 F17 G15 F18 H14 J13 N14
LV LV LV LV LV LV LV LV LV
Power on/off button connection 1 Power on/off button connection 2 Power on/off button connection 3 Watchdog input Reset output Reset for the processor Standby input signal from primary processor Standby input signal from secondary processor Low battery indicator signal or end of life indicator signal
* The maximum voltage rating is given per category of pins: * EHV for Extended High Voltage (20 V) * HV for High Voltage (7.5 V) * EMV for Extended Medium Voltage (5.5 V) * MV for Medium Voltage (4.65 V) * LV for Low Voltage (3.1 V)
MC13783 Technical Data, Rev. 3.4 Freescale Semiconductor 11
Signal Descriptions
Table 1. Pinout Listing (continued)
Pin PWRRDY PWRFAIL USEROFF MEMHLDDRV CSOUT LICELL VBKUP1 VBKUP2 GNDCTRL Location U17 F13 E14 G12 G11 C16 E12 F12 J12 Rating* LV LV LV LV LV MV LV LV Function Power ready signal after DVS and power gate transition Powerfail indicator output to processor or system User off signaling from processor Memory hold FET drive for power cut support Chip select output for memory 1. Coincell supply input 2. Coincell charger output Backup output voltage for memory Backup output voltage for processor core Ground for control logic
Oscillator and Real Time Clock XTAL1 XTAL2 CLK32K CLK32KMCU CLKSEL GNDRTC Power Up Select PUMS1 PUMS2 PUMS3 ICTEST ICSCAN SPI Interface PRIVCC PRICLK PRIMOSI PRIMISO PRICS N2 N5 N8 P7 N6 LV LV LV LV LV Supply for primary SPI bus and audio bus 1 Primary SPI clock input Primary SPI write input Primary SPI read output Primary SPI select input H6 J7 H5 F14 U14 LV LV LV LV LV Power up mode supply setting 1 Power up mode supply setting 2 Power up mode supply setting 3 Test mode selection Scan mode selection V16 V14 R14 E13 U16 V15 LV LV LV LV LV 32.768 kHz Oscillator crystal connection 1 32.768 kHz Oscillator crystal connection 2 32 kHz Clock output 32 kHz Clock output to the processor Enables the RC clock routing to the outputs Ground for the RTC block
* The maximum voltage rating is given per category of pins: * EHV for Extended High Voltage (20 V) * HV for High Voltage (7.5 V) * EMV for Extended Medium Voltage (5.5 V) * MV for Medium Voltage (4.65 V) * LV for Low Voltage (3.1 V)
MC13783 Technical Data, Rev. 3.4 12 Freescale Semiconductor
Signal Descriptions
Table 1. Pinout Listing (continued)
Pin PRIINT SECVCC SECCLK SECMOSI SECMISO SECCS SECINT GNDSPI A to D Converter BATTDETB ADIN5 ADIN6 ADIN7 ADIN8 ADIN9 ADIN10 ADIN11 K13 M14 U15 R15 P14 V17 V18 V19 W18 W19 P13 L13 P12 M13 R13 N15 E6 L12 LV LV LV LV LV LV LV LV Battery thermistor presence detect output ADC generic input channel 5, group 1 ADC generic input channel 6, group 1 ADC generic input channel 7, group 1 ADC generic input channel 8, group 2 ADC generic input channel 9, group 2 ADC generic input channel 10, group 2 ADC generic input channel 11, group 2 Location P5 N3 P6 R6 R5 P8 R7 L9 Rating* LV LV LV LV LV LV LV LV Function Interrupt to processor controlling the primary SPI bus Supply for secondary SPI bus and audio bus 2 Secondary SPI clock input Secondary SPI write input Secondary SPI read output Secondary SPI select input Interrupt to processor controlling the secondary SPI bus Ground for SPI interface
TSX1 TSX2 TSY1 TSY2 ADREF ADTRIG ADOUT GNDADC Audio Bus BCL1
LV LV LV LV LV LV LV -
ADC generic input channel 12 or touchscreen input X1, group 2 ADC generic input channel 13 or touchscreen input X2, group 2 ADC generic input channel 14 or touchscreen input Y1, group 2 ADC generic input channel 15 or touchscreen input Y2, group 2 Reference for ADC and touchscreen interface ADC trigger input ADC trigger output Ground for A to D circuitry
M7
LV
Bit clock for audio bus 1. Input in slave mode, output in master mode
* The maximum voltage rating is given per category of pins: * EHV for Extended High Voltage (20 V) * HV for High Voltage (7.5 V) * EMV for Extended Medium Voltage (5.5 V) * MV for Medium Voltage (4.65 V) * LV for Low Voltage (3.1 V)
MC13783 Technical Data, Rev. 3.4 Freescale Semiconductor 13
Signal Descriptions
Table 1. Pinout Listing (continued)
Pin FS1 RX1 TX1 BCL2 FS2 RX2 TX2 CLIA CLIB Audio Transmit MC1RB MC1LB MC2B MC1RIN MC1LIN MC2IN TXIN TXOUT Audio Receive SPP SPM VINLSP LSPP LSPM V9 V10 V6 V5 V4 LV LV MV MV MV Handset earpiece speaker amplifier output positive terminal Handset earpiece speaker amplifier output minus terminal Handset loudspeaker and alert amplifier supply input Handset loudspeaker and alert amplifier positive terminal Handset loudspeaker and alert amplifier minus terminal R2 P3 P2 V2 U2 U3 U4 V3 LV LV LV LV LV LV LV LV Handset primary or right microphone supply output with integrated bias resistor Handset secondary or left microphone supply output with integrated bias resistor Headset microphone supply output with integrated bias resistor and detect Handset primary or right microphone amplifier input Handset secondary or left microphone amplifier input Headset microphone amplifier input General purpose line level transmit input Buffered output of CEA-936-A microphone signal Location M9 L5 M6 M8 M2 M3 M5 L6 L3 Rating* LV LV LV LV LV LV LV LV LV Function Frame synchronization clock for audio bus 1. Input in slave mode, output in master mode Receive data input for audio bus 1 Transmit data output for audio bus 1 Bit clock for audio bus 2. Input in slave mode, output in master mode Frame synchronization clock for audio bus 2. Input in slave mode, output in master mode Receive data input for audio bus 2 Transmit data output for audio bus 2 Clock input for audio bus 1 or 2 Clock input for audio bus 1 or 2
* The maximum voltage rating is given per category of pins: * EHV for Extended High Voltage (20 V) * HV for High Voltage (7.5 V) * EMV for Extended Medium Voltage (5.5 V) * MV for Medium Voltage (4.65 V) * LV for Low Voltage (3.1 V)
MC13783 Technical Data, Rev. 3.4 14 Freescale Semiconductor
Signal Descriptions
Table 1. Pinout Listing (continued)
Pin GNDLSP Location V1 W1 W2 U5 U6 V8 U9 V7 P10 R10 R8 U7 P9 R9 U8 Rating* Function Ground for loudspeaker amplifier
LSPL CDCOUT HSL HSR HSPGF HSPGS HSDET HSLDET RXOUTR RXOUTL RXINR RXINL Audio Other REFA REFB REFC REFD PLLLPF GNDPLL GNDAUD1 GNDAUD2 GNDAUD3 GNDAUD4 GNDAUD5
LV LV LV LV LV LV LV LV LV LV LV LV
Low power output for discrete loudspeaker amplifier, associated to left channel audio Low power output for discrete amplifier, associated to voice CODEC channel Headset left channel amplifier output Headset right channel amplifier output Headset phantom ground power line (force) Headset phantom ground feedback line (sense) Headset sleeve detection input Headset left detection input Low power receive output for accessories right channel Low power receive output for accessories left channel General purpose receive input right channel General purpose receive input left channel
R3 T3 T2 L2 H2 H3 L10 M10 M11 M12 H9
LV LV LV LV LV -
Reference for audio amplifiers Reference for low noise audio bandgap Reference for voice CODEC Reference for stereo DAC Connection for the stereo DAC PLL low pass filter. Dedicated ground for the stereo DAC PLL block. Ground for audio circuitry 1 (analog) Ground for audio circuitry 2 (analog) Ground for audio circuitry 3 (analog) Ground for audio circuitry 4 (digital) Ground for audio circuitry 5 (digital)
* The maximum voltage rating is given per category of pins: * EHV for Extended High Voltage (20 V) * HV for High Voltage (7.5 V) * EMV for Extended Medium Voltage (5.5 V) * MV for Medium Voltage (4.65 V) * LV for Low Voltage (3.1 V)
MC13783 Technical Data, Rev. 3.4 Freescale Semiconductor 15
Electrical Characteristics
Table 1. Pinout Listing (continued)
Pin Location Rating* Function
Thermal Grounds GNDSUB1 GNDSUB2 GNDSUB3 GNDSUB4 GNDSUB5 GNDSUB6 GNDSUB7 GNDSUB8 Future Use SPARE2 SPARE4 H8 H13 TBD TBD Spare ball for future use Spare ball for future use N11 K12 K11 H12 J9 J8 L8 L11 Non critical signal ground and thermal heatsink Non critical signal ground and thermal heatsink Non critical signal ground and thermal heatsink Non critical signal ground and thermal heatsink Non critical signal ground and thermal heatsink Non critical signal ground and thermal heatsink Non critical signal ground and thermal heatsink Non critical signal ground and thermal heatsink
* The maximum voltage rating is given per category of pins: * EHV for Extended High Voltage (20 V) * HV for High Voltage (7.5 V) * EMV for Extended Medium Voltage (5.5 V) * MV for Medium Voltage (4.65 V) * LV for Low Voltage (3.1 V)
3
3.1
Electrical Characteristics
Absolute Maximum Ratings
The below table gives the maximum allowed voltages, current and temperature ratings which can be applied to the IC. Exceeding these ratings could damage the circuit.
Table 2. Absolute Maximum Ratings
Parameter Charger Input Voltage USB Input Voltage if Common to Charger USB Input Voltage if Separate from Charger Battery Voltage Coincell Voltage Ambient Operating Temperature Range Operating Junction Temperature Range Min -0.3 -0.3 -0.3 -0.3 -0.3 -30 -30 Typ Max +20 +20 +5.50 +4.65 +4.65 +85 +125 Units V V V V V
C C
MC13783 Technical Data, Rev. 3.4 16 Freescale Semiconductor
Functional Description
Table 2. Absolute Maximum Ratings (continued)
Parameter Storage Temperature Range ESD Protection Human Body Model Min -65 2.5 Typ Max +150 Units
C
kV
3.2
Current Consumption
The current consumption of the individual blocks is described in detail throughout this specification. For convenience, below a summary table is included with the main characteristics. Note that the external loads are not taken into account.
Table 3. Summary of Current Consumption
Mode RTC OFF Power Cut User OFF ON Standby ON Default ON Audio Call ON Stereo Playback Typ 5 30 35 60 140 570 7.3 9.5 Max 6 45 52 91 215 850 9.9 12.2 Unit A A A A A A mA mA
4
4.1
Functional Description
Logic
The logic portions of the MC13783 includes the following: * Section 4.1.1, "Programmability," on page 18 includes a description of the dual SPI interface. * Section 4.1.2, "Clock Generation and Real Time Clock," on page 22 includes a description of the 32.768 kHz real time clock generation. * Section 4.1.3, "Power Control System," on page 23 describes the power control logic, including interface and operated modes.
MC13783 Technical Data, Rev. 3.4 Freescale Semiconductor 17
Functional Description
4.1.1
4.1.1.1
Programmability
SPI Interface
The MC13783 IC contains two SPI interface ports which allow parallel access by both the call processor and the applications processor to the MC13783 register set. Via these registers the MC13783 resources can be controlled. The registers also provide status information about how the MC13783 IC is operating as well as information on external signals. The SPI interface is comprised of the signals listed below.
Table 4. SPI Interface Pin Description
Description SPI Bus PRICLK PRIMOSI PRIMISO PRICS SECCLK SECMOSI SECMISO SECCS Interrupt PRIINT SECINT Supply PRIVCC SECVCC Primary processor SPI bus supply. Secondary processor SPI bus supply Primary processor interrupt. Secondary processor interrupt. Primary processor clock input line, data shifting occurs at the rising edge. Primary processor serial data input line. Primary processor serial data output line. Primary processor clock enable line, active high. Secondary processor clock input line, data shifting occurs at the rising edge. Secondary processor serial data input line. Secondary processor serial data output line. Secondary processor clock enable line, active high.
Both SPI ports are configured to utilize 32-bit serial data words, using 1 read/write bit, 6 address bits, 1 null bit, and 24 data bits. The SPI ports' 64 registers correspond to the 6 address bits.
MC13783 Technical Data, Rev. 3.4 18 Freescale Semiconductor
Functional Description
4.1.1.2
Register Set
Table 5. Register Set
Register Register Register Register
The register set is given in Table 5.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Interrupt Status 0 Interrupt Mask 0 Interrupt Sense 0 Interrupt Status 1 Interrupt Mask 1 Interrupt Sense 1 Power Up Mode Sense Identification Semaphore Arbitration Peripheral Audio Arbitration Switchers Arbitration Regulators 0 Arbitration Regulators 1 Power Control 0 Power Control 1 Power Control 2
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Regen Assignment Control Spare Memory A Memory B RTC Time RTC Alarm RTC Day RTC Day Alarm Switchers 0 Switchers 1 Switchers 2 Switchers 3 Switchers 4 Switchers 5 Regulator Setting 0 Regulator Setting 1
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Regulator Mode 0 Regulator Mode 1 Power Miscellaneous Power Spare Audio Rx 0 Audio Rx 1 Audio Tx SSI Network Audio Codec Audio Stereo DAC Audio Spare ADC 0 ADC 1 ADC 2 ADC 3 ADC 4
48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
Charger USB 0 Charger USB 1 LED Control 0 LED Control 1 LED Control 2 LED Control 3 LED Control 4 LED Control 5 Spare Trim 0 Trim 1 Test 0 Test 1 Test 2 Test 3
4.1.1.3
4.1.1.3.1
Interface Requirements
SPI Interface Description
The operation of both SPI interfaces is equivalent. Therefore, all SPI bus names without prefix PRI or SEC correspond to both the PRISPI and SECSPI interfaces. The control bits are organized into 64 fields. Each of these 64 fields contains 32 bits. A maximum of 24 data bits is used per field. In addition, there is one "dead" bit between the data and address fields. The remaining bits include 6 address bits to address the 64 data fields and one write enable bit to select whether the SPI transaction is a read or a write. For each SPI transfer, first a one is written to the read/write bit if this SPI transfer is to be a write. A zero is written to the read/write bit if this is to be a read command only. If a zero is written, then any data sent after the address bits are ignored and the internal contents of the field addressed do not change when the 32nd CLK is sent. Next the 6-bit address is written, MSB first. Finally, data bits are written, MSB first. Once all the data bits are written then the data is transferred into the actual registers on the falling edge of the 32nd CLK.
MC13783 Technical Data, Rev. 3.4 Freescale Semiconductor 19
Functional Description
The default CS polarity is active high. The CS line must remain active during the entire SPI transfer. In case the CS line goes inactive during a SPI transfer all data is ignored. To start a new SPI transfer, the CS line must go inactive and then go active again. The MISO line will be tri-stated while CS is low. Note that not all bits are truly writable. Refer to the individual subcircuit descriptions to determine the read/write capability of each bit. All unused SPI bits in each register must be written to a zero. SPI readbacks of the address field and unused bits are returned as zero. To read a field of data, the MISO pin will output the data field pointed to by the 6 address bits loaded at the beginning of the SPI sequence.
CS
CLK
MOSI
Write_En
Address5
Address4
Address3
Address2
Address 1
Address 0
"Dead Bit"
Data 23
Data 22
Data 1
Data 0
MISO
Data 23
Data 22
Data 1
Data 0
Figure 2. SPI Transfer Protocol Single Read/Write Access
CS
Preamble First Address Preamble Another Address
MOSI
24 Bits Data
24 Bits Data
MISO
24 Bits Data
24 Bits Data
Figure 3. SPI Transfer Protocol Multiple Read/Write Access
4.1.1.3.2
SPI Requirements
The requirements for both SPI interfaces are equivalent. Therefore, all SPI bus names without prefix PRI or SEC correspond to both SPI interfaces. The below diagram and table summarize the SPI electrical and timing requirements. The SPI input and output levels are set independently via the PRIVCC and SECVCC pins by connecting those to the proper supply.
MC13783 Technical Data, Rev. 3.4 20 Freescale Semiconductor
Functional Description
CS T selsu CLK T wrtsu MOSI T rden MISO T rdsu
T clkper T clkhigh T clklow T selhld T sellow
T wrthld
T rdhld
T rddis
Figure 4. SPI Interface Timing Diagram Table 6. SPI Interface Timing Specifications
Parameter Tselsu Tselhld Tsellow Tclkper Tclkhigh Tclklow Twrtsu Twrthld Trdsu Trdhld Trden Trddis
1
Description Time CS has to be high before the first rising edge of CLK Time CS has to remain high after the last falling edge of CLK Time CS has to remain low between two transfers Clock period of CLK1 Part of the clock period where CLK has to remain high Part of the clock period where CLK has to remain low Time MOSI has to be stable before the next rising edge of CLK Time MOSI has to remain stable after the rising edge of CLK Time MISO will be stable before the next rising edge of CLK Time MISO will remain stable after the falling edge of CLK Time MISO needs to become active after the rising edge of CS Time MISO needs to become inactive after the falling edge of CS
T min (ns) 20 20 20 50 20 20 5 5 5 5 5 5
Equivalent to a maximum clock frequency of 20 MHz.
Table 7. SPI Interface Logic IO Specifications
Parameter Input High CS, MOSI, CLK Input Low CS, MOSI, CLK Output Low MISO, INT Output High MISO, INT Note: Output sink 100 A Output source 100 A Condition Min 0.7*VCC 0 0 VCC-0.2 Max VCC+0.5 0.3*VCC 0.2 VCC Units V V V V
VCC refers to PRIVCC and SECVCC respectively.
MC13783 Technical Data, Rev. 3.4 Freescale Semiconductor 21
Functional Description
4.1.2
4.1.2.1
Clock Generation and Real Time Clock
Clock Generation
The MC13783 generates a 32.768 kHz clock as well as several 32.768 kHz derivative clocks that are used internally for control. In addition, a 32.768 kHz square wave is output to external pins. 4.1.2.1.1 Clocking Scheme
The MC13783 contains an internal RC oscillator powered from VATLAS that delivers a 32 kHz nominal frequency (20%) at its output when an external 32.768 kHz crystal is not present. The RC oscillator will then be used to run the debounce logic, the PLL for the switchers, the real time clock (RTC) and internal control logic, and can also be output on the CLK32K pin.
4.1.2.2
Real Time Clock
This section provides an overview of the Real Time Clock (RTC). 4.1.2.2.1 Time and Day Counters
The real time clock runs from the 32 kHz clock. This clock is divided down to a 1 Hz time tick which drives a 17 bit time of day (TOD) counter. The TOD counter counts the seconds during a 24 hour period from 0 to 86,399 and will then roll over to 0. When the roll over occurs, it increments the 15-bit DAY counter. The DAY counter can count up to 32767 days. The 1Hz time tick can be used to generate an 1HZI interrupt. The 1HZI can be masked with corresponding 1HZM mask bit. If the TOD and DAY registers are read at a point in time in which DAY is incremented, then care must be taken that, if DAY is read first, DAY has not changed before reading TOD. In order to guarantee stable TOD and DAY data, all SPI reads and writes to TOD and DAY data should happen immediately after the 1HZI interrupt occurs. Alternatively, TOD or DAY readbacks could be double-read and then compared to verify that they haven't changed. This requirement results from the fact that the 32.768 kHz clock is completely independent of the SPI clock and the two cannot be synchronized. 4.1.2.2.2 Time of Day Alarm
A Time Of Day (TOD) alarm function can be used to turn on the phone and alert the processor. If the phone is already on, the processor will be interrupted. The TODA and DAYA registers are used to set the alarm time. When the TOD counter is equal to the value in TODA and the DAY counter is equal to the value in DAYA, the TODAI interrupt will be generated. MC13783 makes it convenient to schedule multiple daily events, where a single list could be used, or to skip any number of days.
MC13783 Technical Data, Rev. 3.4 22 Freescale Semiconductor
Functional Description
4.1.3
Power Control System
The power control system on MC13783 interfaces with the processors via different IO signals and the SPI bus. It also uses on chip signals and detector outputs. It supports a system with different operating modes as described below. Off Only the MC13783 core circuitry at VATLAS is powered as well as the RTC module. To exit the Off mode, a turn on event is required. Cold Start The switchers and regulators are powered up sequentially to limit the inrush current. At the end of the start up phase, the RESETB and RESETBMCU will be made high and the circuit transitions to On. On The circuit is fully powered and under SPI control. To stay in this mode, the WDI pin has to be high and remain high. If not, the part will transition to Off mode. Memory Hold All switchers and regulators are powered off except for VBKUP1 and VBKUP2. The RESETB and RESETBMCU are low. Upon a turn on event, Cold Start mode is entered. User Off All switchers and regulators are powered off except for VBKUP1 and VBKUP2. The RESETB is low and RESETBMCU is kept high. The 32 kHz output signal CLK32KMCU can be maintained in this mode as well. Upon a turn on event, Warm Start mode is entered. Warm Start The switchers and regulators are powered up sequentially to limit the inrush current. The reset signals RESETB is kept low and RESETBMCU is kept high and CLK32KMCU can be kept active. At the end of the warm start up phase, the RESETB will be made high and the circuit transitions to On. Power Cuts A power cut is defined as a momentary loss of power. This can be caused by battery contact bounce or a user-initiated battery swap. The memory and the processor core are automatically backed up in that case by the coin cell depending on the power cut support mode selected. The maximum duration of a power cut as well as the maximum number of power cuts to be supported are programmable. When exiting the power cut mode due to reapplication of power the system will start up again on the main battery and revert back to the battery supplied modes. Turn On Events If the MC13783 is in Off, User Off or Memory Hold mode, the circuit can be powered on via a turn on event. The turn on events are listed below. To indicate to the processor what turn on event caused the system to power on, an interrupt bit is associated with each of the turn on events.
* * * * * ON1B, ON2B or ON3B pulled low, a power on/off button is connected here. CHRGRAW pulled high which is equivalent to plugging in a charger. BP crossing the minimum operating threshold which corresponds to attaching a charged battery to the phone. VBUS pulled high which is equivalent to plugging in a supplied USB cable. Time of day alarm which allows powering up a phone at a preset time.
The default power up state and sequence of the MC13783 is controlled by the power up mode select pins PUMS1, PUMS2 and PUMS3. In total three different sequences and five different default voltage setting
MC13783 Technical Data, Rev. 3.4 Freescale Semiconductor 23
Functional Description
combinations are provided. At power up all regulators and switchers are sequentially enabled at equidistant steps of 2ms to limit the inrush current.
4.2
4.2.1
Switchers and Regulators
Supply Flow
The switch mode power supplies and the linear regulators are dimensioned to support a supply flow based upon Figure 5.
Charger Accessory USB Protect and Detect Voltage and Current Control Battery BP Charge Coincell RTC Memory Backup Memory
USB Transceiver Backlight Drivers RGB LED Drivers
Vusb Vbus
Boost Switcher
Buck 2B DVS Buck 2A DVS Buck 1B DVS Buck 1A DVS
Vdig Vgen
IO and Digital
Modem and Apps Processors
Vatlas
Vaudio
Local Supply
Local Audio
Vvib
Vsim Vesim
Vmmc1 Vmmc2
Vcam
Viohi Violo
Vrf1, Vrf2, Vrfref, Vrfdig, Vrfbg, Vrfcp
Enables for Discrete Regs
Vibrator Motor
(e)SIM Card + interface
Peripherals and MMC
Camera
Peripherals and IO
Transceivers
Figure 5. Supply Distribution
The minimum operating voltage for the supply tree, while maintaining the performance as specified, is 3.0 V. For lower voltages the performance may be degraded. Table 8 summarizes supply output voltages.
Table 8. Regulator Output Voltages
Supply SW1A SW1B SW2A SW2B 0.900 - 1.675 in 25 mV steps, 1.700 - 2.200 in 100 mV steps Output (V) Load (mA) 500 500 500 500 1A 1A
MC13783 Technical Data, Rev. 3.4 24 Freescale Semiconductor
Functional Description
Table 8. Regulator Output Voltages (continued)
Supply SW3 VAUDIO VIOHI VIOLO VDIG VRFDIG VGEN VCAM VRFBG VRFREF VRFCP VSIM VESIM VVIB VUSB VBUS VRF1 VRF2 VMMC1 VMMC2 5.0 / 5.5 2.775 2.775 1.2/1.3/1.5/.18 1.2/1.3/1.5/.18 1.2/1.5/1.8/1.875 1.1/1.2/1.3/1.5/1.8/2.0/2.4/2.775 1.5/1.8/2.5/2.55/2.6/2.75/2.8/3.0 1.250 2.475/2.600/2.700/2.775 2.700/2.775 1.8/2.9 1.8/2.9 1.3/1.8/2.0/3.0 2.775/3.3 5.0 1.5/1.875/2.7/2.775 1.5/1.875/2.7/2.775 1.6/1.8/2.0/2.6/2.7/2.8/2.9/3.0 1.6/1.8/2.0/2.6/2.7/2.8/2.9/3.0 Output (V) Load (mA) 350 200 200 200 200 200 200 150 1 50 50 60 60 200 50 50 350 350 350 350
Table 9 lists characteristics that apply to MC13783 regulators. Table 10 on page 26 lists characteristics that apply only to the buck switchers.
Table 9. Regulator General Characteristics
Parameter Operating Input Voltage Range Vinmin to Vinmax Output Voltage Vout Load Regulation Active Mode Quiescent Current Low Power Mode Quiescent Current Vinmin < Vin < Vinmax ILmin < IL < ILmax 1mA < IL < ILmax For any Vinmin < Vin < Vinmax Vinmin < Vin < Vinmax IL = 0 Vinmin < Vin < Vinmax IL = 0 20 5 Condition Min Vnom + 0.3 Vnom - 3% Vnom Typ Max 4.65 Vnom + 3% 0.20 30 10 Units V V mV/mA A A
MC13783 Technical Data, Rev. 3.4 Freescale Semiconductor 25
Functional Description
Table 9. Regulator General Characteristics (continued)
Parameter PSRR Condition IL = 75% of ILmax 20 Hz to 20 kHz Vin = Vnom + 1V Min 50 Typ 60 Max Units dB
Minimum Bypass Capacitor Value Used as a condition for all other parameters Bypass Capacitor ESR 10 kHz - 1 MHz
-35% 0
2.2
+35% 0.1
F
Table 10. Buck Switcher Characteristics
Parameter Output Voltage Output Accuracy Transient Load Response Effective Quiescent Current Consumption External Components Condition 2.8 V < BP < 4.65 V 0 < IL < 500 mA PWM Mode, including ripple and load regulation IL from 5 mA to 400 mA in 1s IL from 400 mA to 5 mA in 1s PWM MODE PFM MODE Inductor Inductor Resistance Bypass Capacitor Bypass Capacitor ESR -35% 0.005 22 -20% 50 15 10 +20% 0.16 +35% 0.1 Min Typ Max Units V mV mV A A H F
0.900 V to 1.675 V in 25 m V steps 1.700 V to 2.200 V in 100 V steps -50 +50 +/- 25
The buck switchers support dynamic voltage scaling (DVS). The buck switchers are designed to directly supply the processor cores. To reduce overall power consumption, core voltages of processors may be varied depending on the mode the processor is in. The DVS scheme of the buck switchers allows to transition between the different set points in a controlled and smooth manner. For reduced current drain in low power modes, parts of a processor may be power gated, that is to say, the supply to that part of the processor is disabled. To simplify the supply tree and to reduce the number of external components while maintaining flexibility, power gate switch drivers are included.
4.3
4.3.1
4.3.1.1
Audio
Dual Digital Audio Bus
Interface
The MC13783 is equipped with two independent digital audio busses. Both busses consist of a bit clock, word clock, receive data and transmit data signal lines. Both busses can be redirected to either the voice CODEC or the stereo DAC and can be operated simultaneously. In addition to the afore mentioned signal
MC13783 Technical Data, Rev. 3.4 26 Freescale Semiconductor
Functional Description
lines, two system clock inputs are provided which can be selected to drive the voice CODEC or the stereo DAC. In the latter case, a PLL is used to generate the proper internal frequencies. During simultaneous use of the both busses, two different system clocks can be selected by the voice CODEC and the stereo DAC.
4.3.1.2
Voice CODEC protocol
The serial interface protocol for the voice CODEC can be used in master and in slave mode. In both modes, it can operate with a short or a long frame sync and data is transmitted and received in a two's compliment format.
CDCFS[1:0]=01 Short Frame Sync Length = Bit CDCFS[1:0]=10 Long Frame Sync Length = 16 Bit CDCFSINV=0 CDCBCLINV=0
FS FSync
BCL BitCLK TX TX
HIGH Z Don't Care
15 14 13 12 11 10
9
8
7
6
5
4
3
0
00
HIGH Z Don't Care
RX
15 14 13 12 11 10
9
8
7
6
5
4
3
0
0
0
Figure 6. Voice Codec Timing Diagram Example 1
When the voice CODEC is in slave mode, the FS input must remain synchronous to the CLI frequency. In master mode all clocks are internally generated based on the CLI signal. Additional programmability of the interface for both master and slave mode include bus protocol selection and FS and BCL inversion. There is also the possibility to activate the clocking circuitry independent from the voice CODEC.
4.3.1.3
Stereo DAC protocol
The serial interface protocol for the stereo DAC supports the industry standard MSB justified mode and an I2S mode. In industry standard mode, FS will be held high for one 16-bit data word and low for the next 16 bits. I2S mode is similar to industry standard mode except that the serial data is delayed one BCL period. Data is received in a two's compliment format. A network mode is also available where the stereo DAC will operate in its assigned time slot. A total of maximum 4 time slot pairs are supported depending on the settings of the clock speed. In this case, the sync signal is no longer a word select but a short frame sync. In all modes, the polarity of both FS and BCL is programmable by SPI. There is also the possibility to activate the clocking circuitry independent from the stereo DAC.
MC13783 Technical Data, Rev. 3.4 Freescale Semiconductor 27
Functional Description
4.3.1.4
Audio Port Mixing
In network mode, the receive data from two right channel time slots and of two left channel time slots can be added. One left/right time slot pair is considered to represent the main audio flow whereas the other time slot pair represents the secondary flow. The secondary flow can be attenuated with respect to the main flow by 0 dB, 6 dB and 12 dB which should be sufficient to avoid clipping of the composite signal. In addition, the composite signal can be attenuated with 0 dB or 6 dB.
4.3.2
4.3.2.1
Voice CODEC
A/D Converters
The A/D portion of the voice CODEC consists of two A/D converters which convert two incoming analog audio signals into 13-bit linear PCM words at a rate of 8 kHz or 16 kHz. Following the A/D conversion, the audio signal is digitally band pass filtered. The converted voice is available on the audio bus. If both A/D channels are active, the audio bus is operated in a network mode.
Table 11. Telephone CODEC A/D Performance Specifications
Parameter Peak Input (+3 dBm0) CODEC PSRR Total Distortion (noise and harmonic) Idle Channel Noise Inband Spurious single ended with respect to BP, 0 to 20 kHz at 1.02 kHz (linear) 0 dBm0 8.0 kHz measurement BW out 0 db PGA gain incl. microphone amp 0 dBm0 at 1.02 kHz input, 300 Hz to 3.0 kHz (8 kHz sample rate) Condition Min REFC-0.68 80 60 90 70 -72 -48 Typ Max REFC+0.68 Units V dBP dBP dBm0P dB
4.3.2.2
D/A Converter
The D/A portion of the voice CODEC converts 13-bit linear PCM words entering at a rate of 8 kHz and 16 kHz into analog audio signals. Prior to this D/A conversion, the audio signal is digitally band-pass filtered.
Table 12. Telephone CODEC D/A Performance Specifications
Parameter Condition Min REFC - 1 80 65 90 75 Typ Max REFC + 1 Units V dB dB
Peak Output (+3 dBm0) single ended output CODEC PSRR Total Distortion (noise and harmonic) with respect to B+, 20 Hz to 20 kHz, at 1.02 kHz, 0 dBm0, 20 kHz measurement BW out
MC13783 Technical Data, Rev. 3.4 28 Freescale Semiconductor
Functional Description
Table 12. Telephone CODEC D/A Performance Specifications (continued)
Parameter Idle Channel Noise Inband Spurious Condition at CODEC output, BW out = 20 kHz A weighted 0 dBm0 at 1.02 kHz to 3.4 kHz input. 300 Hz to 20.0 kHz Min Typ -78 Max -74 -50 Units dBm0 dB
4.3.2.3
Clock Modes
In master mode the CLI is divided internally to generate the BCL and FS signals. In slave mode these clocks have to be supplied and in that case there is no imposed relationship between BCL and the other clocks as long as it is high enough to support the number of time slots requested. The supported clock rates are 13.0 MHz, 15.36 MHz, 16.8 MHz, 26.0 MHz and 33.6 MHz.
4.3.3
4.3.3.1
Stereo DAC
D/A Converter
Table 13. Stereo DAC Main Performance Specifications
Parameter Absolute Gain L/R Gain Mismatch Dynamic Range Condition Input at 0 dBFS, from 20 Hz to 20 kHz Input at -3 dBFS, 1.02 kHz (SNDR at -60 dBFS and 1.02 kHz) + 60 dB, 20 kHz BW out, A weighted with respect to battery, input at 0 dBFS, from 20 Hz to 20 kHz A weighted input at -3 dBFS, from 20 Hz to 20 kHz, 20 kHz BW out Includes idle tones 92 Min -0.5 0.2 96 Typ Max +0.5 0.3 Units dB dB dB
The stereo DAC is based on a 16-bit linear left and right channel D/A converter with integrated filtering.
Output PSRR
90
dB
Spurious
-75
dB
4.3.3.2
Clock Modes
The stereo DAC incorporates a PLL to generate the proper clocks in master and in slave modes. The PLL requires an external C//RC loop filter. In Master Mode, the PLL of the Stereo DAC generates FS and BCL signal based on the reference frequency applied through one of the CLI inputs. The CLI frequencies supported are 3.6864 MHz, 12
MC13783 Technical Data, Rev. 3.4 Freescale Semiconductor 29
Functional Description
MHz, 13 MHz, 15.36 MHz, 16.8 MHz, 26 MHz and 33.6 MHz. The PLL will also generate its own master clock MCL used by the stereo DAC itself. In Slave Mode, FS and BCL are applied to the MC13783 and the MCL is internally generated by the PLL based on either FS or BCL. A special mode is foreseen where the PLL is bypassed and CLI can be used as the MCL signal. In this mode, MCLK must be provided with the exact ratio to FS, depending on the sample rate selected. In the network mode, it's possible to select up to 8 time slots (4 time slot pairs).
CLIA
STDCSM=1 & STDCCLK=101
CLIB
STDCCLKSEL STDCCLK[3:0]
1 NR
LPF
VCO
1 NF MCL
BCL1 BCL2
STDCSM=0
NS NB 1 NO
FS1 FS2
STDCSM=0
STDCSM=1 & STDCCLK=101
1 NFS
internal master clock MCLint
STDCSSISEL
Figure 7. Stereo DAC PLL Block Diagram Table 14. Stereo DAC Sample Rate Selection SPI Bits
SR3 0 0 0 0 0 0 0 0 1 1 SR2 0 0 0 0 1 1 1 1 0 0 SR1 0 0 1 1 0 0 1 1 0 0 SR0 0 1 0 1 0 1 0 1 0 1 FS 8000 11025 12000 16000 22050 24000 32000 44100 48000 64000 NFS 512 512 512 256 256 256 128 128 128 64 MCL 4096k 5644.8k 6144k 4096k 5644.8k 6144k 4096k 5644.8k 6144k 4096k NB 16 16 16 8 8 8 4 4 4 2 BCL 256k 352.8k 384k 512k 705.6k 768k 1024k 1411.2k 1536k 2048k
MC13783 Technical Data, Rev. 3.4 30 Freescale Semiconductor
Functional Description
Table 14. Stereo DAC Sample Rate Selection SPI Bits (continued)
SR3 1 SR2 0 SR1 1 SR0 0 FS 96000 NFS 64 MCL 6144k NB 2 BCL 3072k
1011 to 1111 are reserved combinations
4.3.4
4.3.4.1
Audio Input Section
Microphone Bias
Two microphone bias circuits are provided. One circuit supplies up to two handset microphones via the two outputs MC1RB and MC1LB. The second circuit supplies the headset microphone via MC2B. The microphone bias resistors of 2.2 kOhm are included. The bias circuits can be enabled and disabled. The bias MC2B includes a microphone detect circuit which monitors the current flow through the output both when the bias is disabled or enabled. This will generate an interrupt to the processor. In this way the attach and removal of a headset microphone is detected. Also it allows to include a send/end series switch with the microphone for signaling purposes. When the output of the MC2B gets out of regulation, an interrupt is generated. This allows for connecting a switch in parallel to the microphone.
Table 15. MC1RB, MC1LB and MC2B Parametric Specifications
Parameter Microphone Bias Internal Voltage Output Current PSRR Output Noise Condition MC1RB, MC1LB IL = 0 MC2B Source only with respect to BP 20 Hz - 10 kHz Includes REFA noise CCITT psophometricly weighted Min 2.23 2.00 0 90 1.5 3.0 Typ 2.38 2.10 Max 2.53 2.20 500 Units V A dB Vrms
4.3.4.2
Microphone Amplifiers
Figure 8 on page 32 shows a block diagram of the microphone amplifier section. A selection can be made between one of the three amplified inputs: the handset microphone connected to MC1RIN, the headset microphone connected to MC2IN, and the line input TXIN. The selected channel can be fed into the receive channel for test purposes. In addition a second amplified input channel can be selected for the second handset microphone connected to MC1LIN. The gain towards to voice CODEC can be programmed in 1 dB steps from -8 dB to +23 dB. In addition to the microphone amplifier paths, there is also the possibility to route the stereo line in signal from RXINR and RXINL to the voice CODEC dual ADC section. This allows for 13-bit, 16 kHz sampled stereo recording of an analog source such as FM radio.
MC13783 Technical Data, Rev. 3.4 Freescale Semiconductor 31
Functional Description
Detect Microphone Bias
Rbias Rbias Rbias
MC2B
MC1RB
MC1LB
PGAtxL
PGAtxL
Input Selector
Amc1L
MC1LIN
From RXINL Voice Codec Input Selector PGAtxR PGAtxR
Atxin
TXIN
Amc1R Amc2
MC1RIN
MC2IN
To Rx
From RXINR
From USB
TXOUT
Figure 8. Audio Input Section Diagram Table 16. Amplifiers Amc1L, Amc1R, Amc2, Atxin Performance Specifications
Parameter Gain (V to V) Input Impedance (V to V) at 1.0 kHz Amc1L, Amc1R, Amc2 Atxin Gain (Atxin) PSRR TXIN to Voice Codec with respect to BP 20 Hz - 10 kHz inputs AC grounded input to REFA CCITT psophometricly weighted -0.2 Condition Vin = 100 mVpp Min 11.8 8.5 Typ 12 10 40 0 90 0.2 Max 12.2 11.7 Units dB k k dB dB
Input Noise
1
VRMS
MC13783 Technical Data, Rev. 3.4 32 Freescale Semiconductor
Functional Description
4.3.5
4.3.5.1
Audio Output Section
Audio Signal Routing
Figure 9 on page 33 shows a block diagram of the audio output section is given indicating the routing possibilities.
Selector
Codec CDCOUTEN
CDCOUT
SPP
Asp
SPM
From Tx
Codec Right
ASPEN
VINLSP
Voice Codec DAC
CDCBYP
ASPSEL ALSPSEL
LSPP
ASPEN ALSPEN
Alsp
LSPM
PGArx
PGARXEN PGARX[3:0]
Codec ALSPEN
GNDLSP
Left LSPLEN
LSPL
Stereo DAC Right Channel DAC Left Channel DAC To Tx
RXINR
Mixer, Adder, Balance PGAst
ADDCDCIN ADDSTIN ADDRXIN Right
Codec
Detect AhsR
HSR HSDET
Right
Mono Adder Balance
Left
AHSSEL Codec
AHSREN
Phantom Ground AhsL
HSPGF HSPGS
PGAst
Left AHSLEN
Detect
HSL HSLDET
PGASTEN PGAST[3:0]
MONO[1:0] BALLR BAL[2:0]
Codec
Arxin
PGArxin
Right ARXOUTSEL ARXOUTREN
ArxoutR
RXOUTR
RXINL
Arxin
PGArxin
Codec Left
ArxoutL
ARXOUTLEN
RXOUTL
ARXINEN ARXIN
ARXINEN PGARXIN[3:0]
To USB
Figure 9. Audio Output Section Diagram
Four signal sources can be used in the receive path. The voice CODEC receive signal, the voice CODEC transmit signal (for test purposes), the stereo DAC and an external stereo source like an FM radio. The latter can also be routed to the voice CODEC ADC section for recording purposes. Each of the input source signals is amplified via an independently programmable gain amplifier. The amplified signals are fed into a mixer where the different signals can be mixed. The mixed signal goes through a mono adder and balance circuit which can create a mono signal out of the stereo input signals, and allows for balance control. Via the selector, the composite signal is then directed to one or more of the outputs. These are the regular phone earpiece (Asp), the loudspeaker for hands free or ringing (Alsp), the stereo headset (Ahsr, Ahsl) and the stereo line out. The voice CODEC output signal can also follow an independent route to all of the amplifiers via the additional selector inputs. In addition to the amplifiers, low power outputs are available at LSPL and CDCOUT.
MC13783 Technical Data, Rev. 3.4 Freescale Semiconductor 33
Functional Description
4.3.5.2
Programmable Gain Amplifiers
The gain of the audio in both left and right channels is independently controlled in the programmable gain amplifiers to allow for balance control. The input level from the external stereo source can be pre-amplified by Arxin of 18 dB and the programmable gain amplifier PGArxin to get it at the same level as the other sources before going into the audio input mixer block. The amplifiers are programmable in 3 dB steps from -33 dB to +6 dB.
4.3.5.3
Balance, Mixer, Mono Adder and Selector Block
The mixer is a summing amplifier where the different input signals can be summed. The relative level between the input signals is to be controlled via the PGArx, PGAst, and PGArxin amplifiers respectively. The mono adder in the stereo channel can be used in four different modes: stereo (right and left channel independent), stereo opposite (left channel in opposite phase), mono (right and left channel added), mono opposite (as mono but with outputs in opposite phase). The balance control allows for attenuating either the right or the left channel with respect to the other channel. The balance control setting is applied independent of which input channel is selected. The selector opens the audio path to the audio amplifiers and can be seen as an analog switch.
4.3.5.4
Earpiece Speaker Amplifier Asp
The Asp amplifier drives the earpiece of the phone in a bridge tied load configuration. The feedback network of the Asp amplifier is fully integrated.
Table 17. Amplifier Asp Performance Specifications
Parameter Differential Output Swing Gain THD (2nd and 3rd) Single Ended, 1.0 kHz 1.0 kHz 1.0 kHz 1.0 kHz PSRR with respect to BP 20 Hz - 20 kHz inputs AC grounded A Weighted A weighted Including PGA Noise 16 Vin = 100 mVpp VOUT = 2 Vp VOUT = 100 mVp VOUT = 10 mVp 90 Condition Min 4.0 3.8 4.0 4.2 0.1 0.1 0.1 Typ Max Units VPP dB % % % dB
Input Noise Load Impedance
20
VRMS
MC13783 Technical Data, Rev. 3.4 34 Freescale Semiconductor
Functional Description
4.3.5.5
Loudspeaker Amplifier Alsp
The concept of the Alsp amplifier is especially developed to be able to drive one loudspeaker during handset, speakerphone and alert modes. It adopts a fully differential topology in order to be able to reach high PSRR performance while Alsp is powered directly by the telephone battery. The feedback network of the Alsp amplifier is fully integrated. Under worst case conditions the dissipation of Alsp is considerable. To protect the amplifier against overheating, a thermal protection is included which shuts down the amplifier when the maximum allowable junction temperature within Alsp is reached.
Table 18. Amplifier Alsp Performance Specifications
Parameter Differential Output Swing BP = 3.05 V BP = 3.4 V in 8 Supply Voltage Gain THD (2nd and 3rd) 1.0 kHz 1.0 kHz, BP = 3.4 V 1.0 kHz, BP = 4 V 1.0 kHz 1.0 kHz PSRR with respect to BP 20 Hz - 20 kHz inputs AC grounded A Weighted A weighted Resistance 6.4 8 Vin = 100 mVpp VOUT = 5 Vpp VOUT = 5 Vpp VOUT = 1 Vpp Vout = 10 mVrms 90 Condition Min 5.0 5.6 3.05 5.8 6 3 1 4.65 6.2 5 3 0.1 0.1 Typ Max Units VPP VPP V dB % % % % dB
Input Noise Load Impedance
20 38
VRMS
4.3.5.6
Headset Amplifiers Ahsr/Ahsl
The Ahsr and Ahsl amplifiers are dedicated for amplification to a stereo headset, the Ahsr for the right channel and Ahsl for the left channel. The feedback networks are fully integrated. The return path of the headset is provided by the phantom ground which is at the same DC voltage as the bias of the headset amplifiers. This avoids the use of large sized capacitors in series with the headset speakers. All outputs withstand shorting to ground or to phantom ground.
Table 19. Amplifiers Ahsr and Ahsl Performance Specifications
Parameter Singled-Ended Output Swing 32 Ohm load 16 Ohm load Gain 1.0 kHz Vin = 100 mVpp Condition Min 2 1.6 -0.2 Typ 2.2 1.8 0 0.2 Max Units VPP dB
MC13783 Technical Data, Rev. 3.4 Freescale Semiconductor 35
Functional Description
Table 19. Amplifiers Ahsr and Ahsl Performance Specifications (continued)
Parameter THD (2nd and 3rd) 1.0 kHz Condition VOUT = 1 VPP VOUT = 10 mVRMS PSRR with respect to BP 20 Hz - 20 kHz inputs AC grounded A Weighted A weighted Resistance 12.8 16 90 Min Typ 0.03 0.03 Max 0.1 0.1 Units % % dB
Input Noise Load Impedance
20 38
VRMS
The MC13783 provides a headset detection scheme based on the sleeve detection, left channel impedance detection and microphone bias detection which is valid for headsets with or without phantom ground connection. It is compatible with mono headsets where the left channel is connected to ground.
4.3.5.7
Line Output Amplifier Arxout
The Arxout amplifier combination is a low power stereo amplifier. It can provide the stereo signal to for instance an accessory connector. The same output of the selector block is used for the internal connection to the USB transceiver for CEA-936-A Carkit support.
Table 20. Arx Performance Specifications
Parameter Gain Single Ended Output Swing PSRR 1.0 kHz Includes reverse bias protection purpose with respect to BP 20 Hz - 20 kHz inputs AC grounded A Weighted gain = 0 dB VOUT = 1 VPP VOUT = 100 mVRMS VOUT = 10 mVRMS (3) External Load Impedance Output Noise gain = 0 dB A weighted 20 Hz - 20 kHz Per output (2) 1 15 20 Condition Vin = 100 mVpp Min -0.2 1.8 90 Typ 0 2 Max +0.2 Units dB Vpp dB
THD (2nd and 3rd)
0.1 0.1 0.1
% % % k VRMS
MC13783 Technical Data, Rev. 3.4 36 Freescale Semiconductor
Functional Description
4.3.6
4.3.6.1
Audio Control
Supply
The audio section is supplied from a dedicated regulator VAUDIO, except for the loudspeaker amplifier Alsp which is directly supplied from the battery. A low power standby mode controlled by the standby pins is provided for VAUDIO in which the bias current is reduced. The output drive capability and performance are limited in this mode. The nominal output voltage for VAUDIO is 2.775 V.
4.3.6.2
Bias and Anti-Pop
The audio blocks have a bias which can be enabled separately from the rest of the MC13783. When enabled, the audio bias voltages can be ramped fast or slow to make any pop sub audio and therefore not audible.
4.3.6.3
Arbitration Logic
The audio functions can be operated by both the primary and secondary SPI.
4.4
4.4.1
Battery Management
Battery Interface and Control
The battery interface is optimized for single charger input coming from a standard wall charger or from a USB bus. The charger has been designed to support three different configurations where the charger and USB bus share the same input pin (CHRGRAW): these are dual path charging, serial path charging, and single path charging. In addition, provisions have been taken for a separate input configuration where the charger and USB supply are on separate inputs. In all cases except for single path charging, the battery interface allows for so called dead battery operation. An example of serial path charging is shown in Section 4.4.1.1, "Serial Path Configuration Example," on page 38. This section includes the following subsections: * Section 4.4.1.1, "Serial Path Configuration Example," on page 38 * Section 4.4.1.2, "Charger Operation," on page 39 * Section 4.4.1.3, "Coin Cell," on page 39 The mode of operation for the charger interface is selected via the CHRGMOD1 and CHRGMOD0 pins as given in Table 21.
Table 21. Charger Mode Selection
CHRGMOD1 Hi Z Hi Z Hi Z CHRGMOD0 GND Hi Z VATLAS Charger Mode Dual Path Single Path Serial Path
MC13783 Technical Data, Rev. 3.4 Freescale Semiconductor 37
Functional Description
Table 21. Charger Mode Selection (continued)
CHRGMOD1 VATLAS VATLAS VATLAS GND GND GND CHRGMOD0 GND Hi Z VATLAS GND Hi Z VATLAS Charger Mode Separate Input Dual Path Separate Input Single Path Separate Input Serial Path Reserved Reserved Reserved
4.4.1.1
Serial Path Configuration Example
In serial path configuration, the current path used for charging the battery is the same as the supply path from charger to radio B+. Refer to the block diagram example in Figure 10 on page 38. Transistors M1 and M2 control the charge current and provide a voltage clamping function in case of no battery or in case of a dead battery to allow the application to operate. In both cases transistor M3 is non-conducting and the battery is charged with a trickle charge current internal to the MC13783. The transistor M3 is conducting in case the battery has to be connected to the application like for normal operation or for standalone trickle charging. Transistor M2 is non-conducting in case the charger voltage is too high. A current can be supplied from the battery to an accessory by having all transistors M1, M2 and M3 conducting.
M1 Charger/USB Input Hi Z M2 R2 0.1 BP M3 R1 20 m BP or CHRGRAW
Vatlas
Battery
CHRGRAW
BATT
To Scaling and A/D
BP Voltage Regulator and OV Protection
FET Switching Ctrl Logic
FETOVRD FETCTRL From Charger Detection Block
Chrg In Error Amp
Chrg In Diff Amp
Voltage Error Amp
To Scaling and A/D
BP Ref Trickle Charge Control
Charger Detection and OV Block
+ Charge Path Regulator with Current Limit and OV Protection
OC Comp
+ 4
+ ICHRG[3:0]
+ -
Bat In Diff Amp
+ -
Curr Out Diff Amp +
OC_REF 3 ICHRGTR[2:0] 3 VCHRG[2:0]
2
To USB
OVCTRL [1:0]
Voltage Error Amp
+ -
To Scaling and A/D
Figure 10. Serial Path Interface Block Diagram
MC13783 Technical Data, Rev. 3.4 38 Freescale Semiconductor
CHRGLED
BATTISNS
CHRGISNSP
BPFET
CHRG ISNSN
CHRGMOD0
CHRGMOD1
VBUS
CHRGCTRL
BP
BATTFET
Functional Description
Table 22. Voltage and Current Settings
Parameter Set Points
Regulated charge voltage at BP Programmable voltage setting of 3.80/4.05/4.15/4.20/4.25/4.30/4.375/4.50V. Regulated charge current through M1M2 Internal trickle charge current Programmable current from 0 to 1600 mA in 14 steps, and fully on mode. Programmable current from 0 to 84mA in steps of 12mA.
4.4.1.2
4.4.1.2.1
Charger Operation
CEA-936-A
The CEA-936-A carkit specification allows a USB connection to be used not only as an USB interface but also as a generic supply plus analog audio interface. The purpose is to standardize the carkit interface over a USB connection. The USB VBUS line in this case is used to provide a supply within the USB voltage limits and with at least 500 mA of current drive capability. However, this also opens the possibility to create a range of USB compatible wall chargers, referred to as CEA-936-A charger in the remainder of this chapter. The CEA-936-A standard also allows providing a supply from the phone to the accessory over the VBUS line, just like in the USB on the go case. 4.4.1.2.2 Standalone Trickle Charging
The MC13783 has a standalone trickle charge mode of operation in order to ensure that a completely discharged battery can be charged without the Microprocessor's control. Upon plugging a valid charger to the phone, the trickle cycle is started. For battery voltages below 2.7 V, the trickle charge current level is set at 100 mA. When the battery voltage increases above the threshold, the trickle charge level is increased to 300 mA. When the battery voltage rises above the threshold sufficient for phone operation, a power up sequence is automatically initiated. Even after the phone has powered up, the Standalone trickle charge will remain on until software enables charging. If the battery voltage was already greater than the voltage needed for phone operation when a charger is attached, the phone will power up immediately without starting a trickle charge cycle. The trickle charge is terminated upon charge completion, time out or by software control.
4.4.1.3
Coin Cell
The coin cell charger circuit will function as a current-limited voltage source, resulting in the CC/CV taper characteristic typically used for rechargeable Lithium-Ion batteries. The output voltage is selectable. The coin cell charger voltage is programmable in the ON state. In the User Off modes, or in the Off state, the coincell charger will continue to charge to the predefined voltage setting but at a lower maximum current. In practice, this means that if in Off state the coin cell is fully charged, the coin cell charger will only provide the leakage current of the coin cell. The RTC will run from VATLAS in this case. A capacitor should be placed from LICELL to ground if no coin cell is used.
MC13783 Technical Data, Rev. 3.4 Freescale Semiconductor 39
Functional Description
4.4.2
4.4.2.1
ADC Subsystem
Converter Core
The ADC core is a 10 bit successive approximation converter.
4.4.2.2
Input Selector
The ADC has two groups of 8 input channels. ADSEL selects between two groups of input signals. If set to zero then group 0 is read and stored, if set to 1 then group 1 is read and stored. This is done to shorten the total read time and to reduce the required storage of converted values. The table below gives an overview of the attribution of the A to D channels.
Table 23. ADC Inputs
Channel 0 1 Group 0 - ADSEL=0 2 3 4 5 6 7 8 9 Group 1 - ADSEL=1 10 11 12 13 14 15 Signal read Battery Voltage (BATT) Battery Current (BATT - BATTISNS) Application Supply (BP) Charger Voltage (CHRGRAW) Charger Current (CHRGISNSP-CHRGISNSN) General Purpose ADIN5 / Battery Pack Thermistor General Purpose ADIN6 / Backup Voltage (LICELL) General Purpose ADIN7 / UID / Die Temperature General Purpose ADIN8 General Purpose ADIN9 General Purpose ADIN10 General Purpose ADIN11 General Purpose TSX1 / Touchscreen X-plate 1 General Purpose TSX2 / Touchscreen X-plate 2 General Purpose TSY1 / Touchscreen Y-plate 1 General Purpose TSY2 / Touchscreen Y-plate 2 Expected Input Range 2.50 - 4.65 V -50 - +50 mV 2.50 - 4.65 V 0 - 10 V / 0 - 20 V -250mV - +250 mV 0 - 2.30 V 0 - 2.30 V / 1.50 - 3.50 V 0 - 2.30 V / 0 - 2.55 V / TBD 0 - 2.30 V 0 - 2.30 V 0 - 2.30 V 0 - 2.30 V 0 - 2.30 V 0 - 2.30 V 0 - 2.30 V 0 - 2.30 V Scaling - 2.40 V x20 - 2.40 V /5 /10 X4 No No / - 1.20 V No / x0.9 / No No No No No No No No No Scaled Version 0.10 - 2.25 V -1.00 - +1.00 V 0.10 - 2.25 V 0 - 2.00 V 0 - 2.00 V -1.00 - 1.00 V 0 - 2.30 V 0 - 2.30 V 0.30 - 2.30 V 0 - 2.30 V 0 - 2.30 V 0 - 2.30 V 0 - 2.30 V 0 - 2.30 V 0 - 2.30 V 0 - 2.30 V 0 - 2.30 V 0 - 2.30 V
4.4.2.3
Control
The ADC parameters are programmed by the processors via SPI. Locally on MC13783, the different ADC requests are arbitrated and executed. When a conversion is finished, an interrupt is generated to the processor which started the conversion.
MC13783 Technical Data, Rev. 3.4 40 Freescale Semiconductor
Functional Description
4.4.2.3.1
Starting Conversions
The ADC will have the ability to start a series of conversions based on a rising edge of the ADTRIG signal or directly initiated by SPI. Once conversion is initiated all 8 channels will be sequentially converted and stored in registers or eight conversions on one channel will be performed and stored. The conversion result can digitally be compared with respect to a preset value for threshold detection. The conversion will begin after a delay set between 0 and 8 ms. The delay between conversions can be made equal to this delay. To avoid that the ADTRIG input involuntarily triggers a conversion, a bit can be set which will make the ADC ignores any transition on the ADTRIG pin. 4.4.2.3.2 Reading Conversions
Once a series of eight A/D conversions is complete, they are stored in one set of eight internal registers and the values can be read out by software.
4.4.2.4
Pulse Generator
A SPI controllable pulse generator is available at ADOUT synchronized with the ADC conversion. This pulse can be used to enable or drive external circuits only during the period of 4 or 8 ADC conversions.
4.4.2.5
4.4.2.5.1
Dedicated Channels Reading
Battery Current
Traditional battery capacity estimation is based on battery terminal voltage reading combined with estimated phone current drain based on emitted PA power. For improved battery capacity estimation, especially in non transmit mode like gaming, this method is too approximate. To improve the estimation, the current out of the battery must be quantified more accurately. For this, on the MC13783, the current flowing out of and into the battery can be read via the ADC by monitoring the voltage drop over the sense resistor between BATT and BATTISNS. 4.4.2.5.2 Charge Current
The charge current is read by monitoring the voltage drop over the charge current sense resistor. 4.4.2.5.3 Battery Thermistor
If a battery is equipped with a battery thermistor, its value can be read out via the ADC input ADIN5. The biasing and sensing circuit is entirely integrated and is only powered during the A to D conversions. 4.4.2.5.4 Die Temperature and UID
The die temperature can be read out on the ADIN7 channel. Alternatively, the UID voltage can be read out on the ADIN7 channel.
MC13783 Technical Data, Rev. 3.4 Freescale Semiconductor 41
Functional Description
4.4.2.6
Touch Screen Interface
The touchscreen interface provides all circuitry required for the readout of a 4-wire resistive touchscreen. The touchscreen X plate is connected to TSX1 and TSX2 while the Y plate is connected to TSY1 and TSY2. A local supply ADREF will serve as a reference. Several readout possibilities are offered. In interrupt mode, a voltage is applied via a high impedance source to only one of the plates, the other is connected to ground. When the two plates make contact both will be at a low potential. This will generate a pen interrupt to the processor. This detection does not make use of the ADC core. A finger will connect both plates over a wider area then a stylus. To distinguish both sources, in the contact resistance mode the resistance between the plates is measured by applying a voltage difference between the X and the Y plate. The current through the plates is measured. Since the plate resistance varies from screen to screen, measuring its value will improve the pressure measurement. Also, it can help in determining if more than 1 spot is touched on the screen. In the plate measurement mode, a potential is applied across one of the plates while the other plate is left floating. The current through the plate is measured. The contact resistance mode and plate measurement mode are together referred to as resistive mode. To determine the XY coordinate pair, in position mode a voltage difference over the X plate is read out via the Y plate for the X-coordinate and vice versa for the Y- coordinate readout. In the MC13783, during the position mode the contact resistance is read as well in addition to the XY coordinate pair. To perform touchscreen readings, the processor will have to set one of the touchscreen interface readout modes, program the delay between the conversions, trigger the ADC via one of the trigger sources, wait for an interrupt indicating the conversion is done, and then read out the data. In order to reduce the interrupt rate and to allow for easier noise rejection, the touchscreen readings are repeated in the readout sequence. In this way, in total eight results are available per readout.
Table 24. Touchscreen Reading Sequence
ADC Trigger 0 1 2 3 4 5 6 7 Signals sampled in Resistive Mode X plate resistance X plate resistance X plate resistance Y plate resistance Y plate resistance Y plate resistance Contact resistance Contact resistance Signals sampled in Position Mode X position X position X position Y position Y position Y position Contact resistance Contact resistance Readout Address 000 001 010 011 100 101 110 111
MC13783 Technical Data, Rev. 3.4 42 Freescale Semiconductor
Functional Description
4.4.2.7
ADC Arbitration
The ADC converter and its control is based on a single ADC converter core. Since the data path is 24 bits wide, results for 2 conversion results (10 bits each) can be read back in each SPI read sequence. For support of queued conversion requests, the SPI has the ability to write to the two sets of ADC control, namely "its own" ADC and "the other" ADC or ADC BIS. The write access to the control of ADC BIS is handled via the ADCBISn bits located at bit position 23 of the ADC control registers. By setting this bit to a 1, the control bits which follow are directed to the ADC BIS. ADCBISn will always read back 0 and there is no read access to the ADCBIS control bits. The read results from the ADC conversions are available in two separate registers ADC result registers ADC0 and ADC1.
4.5
Miscellaneous Functions
Miscellaneous functions are described in the following sections: * Section 4.5.1, "Connectivity on page 43 * Section 4.5.2, "Lighting System on page 46
4.5.1
Connectivity
This section summarizes the following interface information: * Section 4.5.1.1, "USB Interface on page 43 * Section 4.5.1.2, "RS-232 Interface on page 46 * Section 4.5.1.3, "CEA-936-A Accessory Support on page 46 * Section 4.5.1.4, "Booting Support on page 46
4.5.1.1
4.5.1.1.1
USB Interface
Supplies
The USB interface is supplied by the VUSB (3.3 V) and the VBUS (5.0 V) regulators. The VBUS regulator takes the boost supply and regulates it down to the required USBOTG level which is provided to VBUS in the case of a USBOTG connection. The transceiver itself is supplied from VUSB. The VUSB regulator by default is supplied by BP and by SPI programming can be boost or VBUS supplied as well. 4.5.1.1.2 Detect
Comparators are used to detect a valid VBUS, and to support the USB OTG session request protocol. 4.5.1.1.3 Transceiver
The USB transceiver data flow is depicted in below diagram. The processor interface IO level is set to USBVCC.
MC13783 Technical Data, Rev. 3.4 Freescale Semiconductor 43
Functional Description
UDATVP Tx USE0VM Router TO PROCESSOR SEO UTXENB
UDP
UDM
URXVP Rx
URCVD
Diff
URXVM
Rx
DATSEO, BIDIR
Figure 11. USB/RS232 Transceiver Data Flow
Upon a USB legacy host detection, an interrupt is generated but neither the transceiver nor the VUSB regulator are automatically enabled. This must be done by software before data transmission. The transceiver can also be enabled during boot mode. Via SPI bits DATSE0 and BIDIR, one of the four USB operating modes can be selected. However, when starting up in a boot mode, there is no up front SPI programming possible. The default operating mode is then determined by the setting of the UMOD pin as indicated in Table 25.
MC13783 Technical Data, Rev. 3.4 44 Freescale Semiconductor
TO ACCESSORY CONNECTOR
Functional Description
Table 25. USB Mode Selection
Mode Selection USB Mode DATSE0 BIDIR unidirectional (6-wire) bidirectional (4-wire) unidirectional (6-wire) bidirectional (3-wire) 1 0 0 UTXENB = Low UDATVP UDP USE0VM UDM UDATVP UDP USE0VM UDM UDATVP UDP/UDM USE0VM FSE01 UTXENB = High UDP URXVP UDM URXVM UDP/UDM URCVD UDP UDATVP UDM USE0VM UDP/UDM URCVD UDP URXVP UDM URXVM UDP/UDM URCVD Mode Description Corresponding UMOD0/UMOD1 Setting Don't Care / To VATLAS To VATLAS / To Ground To Ground / To Ground Open / To Ground
Differential
1
0
Single Ended
1
UDATVP UDP/UDM UDP/UDM UDATVP (active) USE0VM FSE0 UDP UDATVP (suspend) RSE0 USE0VM
1
FSE0 stands for forced SE0, RSE0 stands for received SE0.
4.5.1.1.4
Full Speed/ Low Speed Configuration
The USB transceiver supports the low speed mode of 1.5 Mbits/second and the full speed mode of 12 Mbits/second. To indicate the speed to the host an internal 1.5 kOhm pull up to VUSB is used. Via SPI this resistor can be connected to UDP to indicate full speed, or to UDM to indicate low speed. 4.5.1.1.5 USB Suspend
USB suspend mode is enabled through SPI. When set, the USB transceiver enters a low power mode which reduces the transceiver current drain to below 500 A. In USB suspend mode, the VUSB regulator remains enabled and the VBUS detect comparators remain enabled, while the single ended receivers are switched from a comparator to a Schmitt-trigger buffer. 4.5.1.1.6 USB On-The-Go
USBOTG support circuitry is added in order to allow a phone to act as a dual-role USBOTG device. In accordance with USBOTG requirements, the pull down resistors on UDP and UDM can be switched in or out individually via SPI. Furthermore, the pulls down resistors are integrated on-chip. The USBOTG specification requires that during the session request protocol, the D+ (full speed) line is pulled up for a duration of 5 to 10 msec. In order to reduce the SPI traffic, the MC13783 has an integrated timer used for this task. To support VBUS pulsing, there is a programmable current limit and timer on the VBUS regulator. During VBUS pulsing, the lower current limit allows for easier detection of a legacy host device on the far end of the USB cable. It is possible to have the transceiver automatically connect the data pull-up to VUSB any time a SE0 is detected. This enables the phone to meet the USBOTG timing requirements without unduly taxing the software.
MC13783 Technical Data, Rev. 3.4 Freescale Semiconductor 45
Functional Description
An ID detector is used to determine if a mini-A or mini-B style plug has been inserted into a mini-AB style receptacle on the phone. The ID voltage can be read out via the ADC channel ADIN7.
4.5.1.2
RS-232 Interface
In RS232 mode, USBVCC is used for the supply of the interface with the microprocessor. VUSB is used as the supply for the RS232 transceiver and the drivers at the cable side. In this mode, the USB transceiver is tri-stated and the USB module IC pins are re-used to pass the RS232 signals from the radio connector to the digital sections of the radio. Flexibility is provided for RS232 Rx and Tx signal swapping at the cable side interface pins UDP and UDM, and the possibility to enable the RS232 receiver while tri-stating the transmitter.
4.5.1.3
CEA-936-A Accessory Support
Support for CEA-936-A is provided, including provision for audio muxing to UDP and UDM and ID interrupt generation. All audio path switches are residing in the USB block and are powered from the VUSB regulator. Please refer to CEA-936-A specification for details.
4.5.1.4
Booting Support
The MC13783 supports booting on USB. The boot mode is entered by the USBEN pin being forced high by the booting equipment which enables the transceiver.
4.5.2
Lighting System
The lighting system of MC13783 is comprised of independent controlled circuitry for backlight drivers and tri-color LED drivers. This integration provides flexible backlighting and fun lighting for products featuring multi-zone and multi-color lighting implementations. Figure 12 illustrates the lighting system utilization for a typical application.
MC13783 Technical Data, Rev. 3.4 46 Freescale Semiconductor
Functional Description
BOOST Key Pad
BOOST
Main Display
Aux Display
BOOST
BOOST
BOOST
P B
P B
P B
1 D M D E L
2 D M D E L
3 D M D E L
4 D M D E L
1 D A D E L
2 D A D E L
P K D E L
L B D E L D N G
1 R D E L
1 G D E L
1 B D E L
2 R D E L
2 G D E L
2 B D E L
3 R D E L
3 G D E L
3 B D E L
C T D E L D N G
BL Drive Main Display
BL Drive Aux Display
BL Drive Keypad
Tri-Color Fun Light Drive
MC13783 IC Lighting System
Figure 12. MC13783 Lighting System
4.5.2.1
Backlight Drivers
The backlight drivers are generally intended for White LED (WLED) backlighting of color LCD displays or white/blue LED backlighting for key pads. The drivers consists of independently programmable current sinking channels. SPI registers control programmable features such as DC current level, auto ramping / dimming and PWM settings. Three zones are provided for typical applications which may include backlighting a main display, auxiliary display, and key pad. However, the drivers can be utilized for other lighting schemes such as an integrated WLED flashlight or even non-LED system applications requiring programmable current sinks. The integrated boost switcher provided on the MC13783 is used to supply the backlights. It automatically adapts its output voltage to allow for power optimized biasing of white and/or blue LEDs. Alternatively, any other available source with sufficient current drive and output voltage for necessary diode headroom may be used (5.5 V should not be exceeded).
4.5.2.2
Tri-Color LED Drivers
The tri-color circuitry provides expanded capability for independent lighting control and distribution that supplements the backlight drivers circuitry. The tri-color drivers have the same basic programmability as the backlight drivers, with similar bit control for current level, duty cycle control, and ramping. A boosted
MC13783 Technical Data, Rev. 3.4 Freescale Semiconductor 47
Package Information
supply such as the on-chip boost switcher should be used to ensure adequate headroom if necessary, such as for driving blue LEDs. The channel naming assignments are R, G, and B representative of applications which use red, green, and blue colored LEDs on each of the respective zones. One set of RGB drivers constitute a tri-color bank, and the MC13783 features three tri-color banks. Each tri-color LED driver is programmable for independent control of timing and current levels. Programmable fun light patterns are also provided to allow initiation of predefined lighting routines with convenient SPI efficiency, reducing the communication burden of running complex lighting sequences.
5
Package Information
The package style is a low profile BGA, pitch 0.5 mm, body 10 x 10mm, semi populated 19 x 19 matrix, ball count 247 including 4 sets of triple corner balls and 4 spare balls.
Figure 13. Package Drawing
MC13783 Technical Data, Rev. 3.4 48 Freescale Semiconductor
Product Documentation
6
Product Documentation
This data sheet is labeled as a particular type: Product Preview, Advance Information, or Technical Data. Definitions of these types are available at: http://www.freescale.com on the Documentation page. Table 26 summarizes revisions to this document since the previous release (Rev. 3.3).
Table 26. Revision History
Location Removed footers Section 4.1.1.3.1, "SPI Interface Description" Throughout document. Updated text. Revision
MC13783 Technical Data, Rev. 3.4 Freescale Semiconductor 49
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Document Number: MC13783/D Rev. 3.4 3/2007

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