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19-3045; Rev 0; 10/03
Parallelable Secondary-Side Synchronous Rectifier Driver and Feedback-Generator Controller ICs
General Description
The MAX5058/MAX5059 enable secondary-side synchronous rectification in isolated power supplies using widely available power MOSFETs. These devices facilitate the commutation of the secondary-side MOSFETs by providing a clean gate-drive signal that is synchronized to the power MOSFET switching in the primary side of the isolation transformer. The MAX5058/MAX5059 complement the MAX5051 and MAX5042/MAX5043 primaryside PWM ICs and enable the design of high-efficiency synchronously rectified isolated power supplies. Simultaneous conduction of the primary side and the freewheeling synchronous rectifier MOSFET is avoided by having a look-ahead signal (before the primary-side MOSFETs turn ON), thus eliminating large current spikes resulting from a shorted transformer secondary. An on-board error amplifier with a versatile current reference output enables virtually unlimited possibilities in reference-voltage generation. Reference voltage for the error amplifier is generated by connecting an appropriate resistor to this output. Low on-resistance margining MOSFETs integrated onchip allow for implementation of a margining circuit without the use of external switches. The MAX5058 provides a 5V LDO output for logic-level MOSFETs while the MAX5059 provides a 10V LDO output for conventional 10V MOSFETs. The MAX5058/MAX5059 are designed to enable paralleling of multiple power supplies for accurate current sharing using a simple 2-wire, differential, current-share bus. Parallelability enables expansion of the power capabilities and simplifies thermal management in highoutput-current applications. When used in conjunction with the MAX5051, the primaries can also be synchronized and operated 180 degrees out of phase. The MAX5058/MAX5059 are available in a 28-pin thermally enhanced TSSOP package and operate over a wide -40C to +125C temperature range. Warning: The MAX5058/MAX5059 are designed to work in circuits that contain high voltages. Exercise caution.
Features
o Clean Drive Waveforms for Synchronous MOSFETs o Utilization of a Look-Ahead Signal from the Primary for Proper Turn-On/Turn-Off Times o Synchronous Rectifier Drivers Capable of Sourcing and Sinking Up to 2A Peak Current o Internal Gate-Voltage Regulator for 5V (MAX5058) or 10V (MAX5059) Gate-Drive Voltage o Internal Error Amplifier o Accurate Differential Current-Share/Force Circuit Allows Paralleling of Several Power Supplies for High Output Current o Internal Remote Voltage-Sense Amplifier o Flexible Reference-Voltage Generation o Output Voltage Regulation Down to 0.5V o Low Quiescent Current Consumption of 2.5mA o Integrated Digital Output Margining Circuit Saves External Parts and Board Space o 30ns Propagation Delay Time from Pulse Input to Output o Automatic Detection of Discontinuous Current Conduction and Turn-Off of the Freewheeling MOSFET o High Efficiency at Low Output Currents and Reverse-Current Protection o Open-Drain Overtemperature Warning Flag o 28-Pin Thermally Enhanced TSSOP Package
MAX5058/MAX5059
Ordering Information
PART MAX5058AUI MAX5058EUI MAX5059AUI MAX5059EUI TEMP RANGE -40C to +125C -40C to +85C -40C to +125C -40C to +85C PINPACKAGE 28 TSSOP-EP* 28 TSSOP-EP* 28 TSSOP-EP* 28 TSSOP-EP* VREG (V) 5 5 10 10
Applications
Isolated Telecom Power Supplies Isolated Networking Power Supplies 48V Power-Supply Modules Industrial Power Supplies 48V/12V Server Power Supplies
*EP = Exposed paddle.
Pin Configuration appears at end of data sheet. ________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Parallelable Secondary-Side Synchronous Rectifier Driver and Feedback-Generator Controller ICs MAX5058/MAX5059
ABSOLUTE MAXIMUM RATINGS
V+ to GND .............................................................-0.3V to +30V PGND to GND .......................................................-0.3V to +0.3V COMPV, VREG, VDR, TSF to GND......................... -0.3V to +14V All Other Pins to GND ..................................-0.3V to (VP + 0.3V) VREG Source Current .........................................................50mA COMPV, RMGU, RMGD, TSF Sink Current ....................... 30mA VP to GND ................................................................-0.3V to +6V VSO, CSO Source/Sink Current ......................................... 5mA SFP Source Current ............................................................. 5mA QREC, QSYNC Continuous Current....................................50mA QREC, QSYNC Current < 500ns..............................................5A Continuous Power Dissipation (TA = +70C) 28-Pin TSSOP (derate 23.8mW/C above +70C). ....1905mW Junction Temperature ......................................................+150C Operating Temperature Ranges MAX5058EUI, MAX5059EUI ............................-40C to +85C MAX5058AUI, MAX5059AUI..........................-40C to +125C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V+ = +12V, GND = PGND = 0, VDR = VREG, CQSYNC = CQREC = 0, ZCP = ZCN = BUFIN = CSP = CSN = SFN = VSN = GND, VIREF = VVSP = 1.785V, CVREG = 2.2F, CVP = 1F, CCOMPS = 0.1F, CSFP = 68nF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER POWER SUPPLY Supply Voltage Range Quiescent Supply Current Switching Supply Current V+ IQ ISW fSW = 250kHz at BUFIN MAX5058 MAX5059 49.2 -0.1 0.5 MAX5058 MAX5059 4.5 9.3 2.5 4.5 6 50 51.1 +0.1 2.5 28.0 28.0 5 mA mA V SYMBOL CONDITIONS MIN TYP MAX UNITS
IREF: REFERENCE CURRENT OUTPUT Reference Current Reference Current Variation Reference Voltage Compliance Range VREG: LOW-DROPOUT REGULATOR Regulator Output Line Regulation VVREG IVREG = 0 to 30mA MAX5058, V+ = 6V to 28V MAX5059, V+ = 11V to 28V MAX5058 Dropout VDROP MAX5059 VP: INTERNAL REGULATOR Regulator Output Setpoint ZC: ZERO-CURRENT COMPARATOR Zero-Current Comparator Threshold Zero-Current Comparator Input Current VZCTH IZC TA = +25C +3.5 -2.5 +5 +6.5 +2.5 mV A VVP IVP = 0 to 5mA 3.8 4.3 V V+ = 4.5V, IVREG = 30mA V+ = 9.3V, IVREG = 30mA 200 200 MAX5058 MAX5059 4.75 9.4 5 10 5.25 10.6 25 25 350 mV 350 V mV IIREF IIREF VIREF = 1.785V VIREF = 0.5V to 2.5V Guaranteed by reference current variation test A %/V V
2
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Parallelable Secondary-Side Synchronous Rectifier Driver and Feedback-Generator Controller ICs
ELECTRICAL CHARACTERISTICS (continued)
(V+ = +12V, GND = PGND = 0, VDR = VREG, CQSYNC = CQREC = 0, ZCP = ZCN = BUFIN = CSP = CSN = SFN = VSN = GND, VIREF = VVSP = 1.785V, CVREG = 2.2F, CVP = 1F, CCOMPS = 0.1F, CSFP = 68nF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Zero-Current Comparator Input Range Zero-Current Comparator Propagation Delay SYMBOL VZC 10mV overdrive, from when VZCP - VZCN is greater than VZCTH to when QSYNC goes low CONDITIONS MIN -0.1 TYP MAX +1.5 UNITS V
MAX5058/MAX5059
tZC
65
ns
BUFIN: SYNCHRONIZING PULSE INPUT BUFIN to Output Propagation Delay BUFIN Input Current BUFIN Input Capacitance BUFIN Input-Logic High BUFIN Input-Logic Low MARGINING INPUTS RMGD Resistance RMGU Resistance MRGD Input-Logic High MRGD Input-Logic Low MRGU Input-Logic High MRGU Input-Logic Low MRGU, MRGD Input Resistance RMGU, RMGD Leakage Current DRIVER OUTPUTS QREC, QSYNC Peak Source Current QREC, QSYNC Output-Voltage High QREC, QSYNC Low-to-High Delay Time QREC, QSYNC Peak Sink Current QREC, QSYNC Output-Voltage Low QREC, QSYNC High-to-Low Delay Time IQREC_SO, IQSYNC_SO VQREC_H, VQSYNC_H tPDLH IQREC_SI, IQSYNC_SI VQREC_L, VQSYNC_L tPDHL Sinking 50mA CQREC = CQSYNC = 0 CQREC = CQSYNC = 5nF MAX5058 MAX5059 Measured with respect to VVDR, sourcing 50mA CQREC = CQSYNC = 0 CQREC = CQSYNC = 5nF MAX5058 MAX5059 2 75 75 30 70 2 50 50 40 70 100 100 150 150 mV A RRMGD RRMGU VHMRGD VLMRGD VHMRGU VLMRGU RMRGD, RMRGU IRMGU, IRMGD 40 -100 +100 2.4 0.8 Sinking 10mA Sinking 10mA 2.4 0.8 6.5 6.5 11 11 V V V V k nA tpd IBUFIN CBUFIN VHBUFIN VLBUFIN 2.4 0.8 BUFIN rising to QREC rising or QSYNC falling -1 10 40 +1 ns A pF V V
ns A mV ns
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3
Parallelable Secondary-Side Synchronous Rectifier Driver and Feedback-Generator Controller ICs MAX5058/MAX5059
ELECTRICAL CHARACTERISTICS (continued)
(V+ = +12V, GND = PGND = 0, VDR = VREG, CQSYNC = CQREC = 0, ZCP = ZCN = BUFIN = CSP = CSN = SFN = VSN = GND, VIREF = VVSP = 1.785V, CVREG = 2.2F, CVP = 1F, CCOMPS = 0.1F, CSFP = 68nF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER ERROR AMPLIFIER Inverting Input Current Error-Amplifier Input Range Error-Amplifier Input Offset Error-Amplifier Output-Voltage Low Error-Amplifier Unity-Gain BW Error-Amplifier Voltage Gain Error-Amplifier PSRR COMPV Output Resistance to Ground REMOTE-SENSE AMPLIFIER (RSA) VSN Input Current VSP Input Current Input Common-Mode Range Input Offset Voltage Output Impedance Amplifier -3dB Frequency Remote-Sense Amplifier Gain CURRENT-SENSE AMPLIFIER (CSA) CSN Input Current CSP Input Current Input Offset Voltage Current-Sense Amplifier Gain Input Differential-Mode Range Input Common-Mode Range Output-Voltage Level Shift Output Voltage Range Amplifier -3dB Frequency SHARE-FORCE AMPLIFIER (SFA) Sink Current Source Current 500 60 A A VLS VCSO(MIN) f-3dB (Note 2) ICSO = -500A to +500A ICSO = -500A to +500A -0.3 0.415 0.1 50 GCSA ICSN ICSP -0.3V VCSN +3.8V, -0.3V VCSP +3.8V -0.3V VCSP +3.8V ICSO = -500A to +500A (Note 2) ICSO = -500A to +500A -150 -40 +20 19.8 +25 20 +150 +150 +30 20.2 100 +3.8 0.570 3.0 A A mV V/V mV V V V kHz GRS IVSO = -0.5mA to +0.5mA IVSO = -0.5mA to +0.5mA 0.9925 VOSRSA IVSO = -0.5mA to +0.5mA IVSN IVSP -100 -20 -0.3 -4 8 1 1 1.0075 +100 +100 +3.8 A A V mV MHz V/V IINV VINV VOS VCOMPV GBW AVOL PSRR (Note 1) ICOMPV = 100A to 5mA ICOMPV = 5mA RCOMP = 220, ICOMP = 5mA RCOMPV = 220, ICOMP = 5mA 1.3 80 60 1 -50 0 -5 +50 2.5 +5 200 nA V mV mV MHz dB dB M SYMBOL CONDITIONS MIN TYP MAX UNITS
4
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Parallelable Secondary-Side Synchronous Rectifier Driver and Feedback-Generator Controller ICs
ELECTRICAL CHARACTERISTICS (continued)
(V+ = +12V, GND = PGND = 0, VDR = VREG, CQSYNC = CQREC = 0, ZCP = ZCN = BUFIN = CSP = CSN = SFN = VSN = GND, VIREF = VVSP = 1.785V, CVREG = 2.2F, CVP = 1F, CCOMPS = 0.1F, CSFP = 68nF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Transconductance Common-Mode Input Voltage Range Output Voltage Range Offset Voltage Open-Loop Gain CURRENT-ADJUST VOLTAGE-TO-CURRENT CONVERTER Input Voltage Range Input Voltage Offset Output Voltage Range Transconductance Maximum Current Adjustment Value THERMAL SHUTDOWN Thermal Warning Flag Level Thermal Warning Flag Hysteresis Internal Thermal-Shutdown Level Internal Thermal-Shutdown Hysteresis TSF Maximum Output Voltage TSF Output Leakage Current ITSF = 5mA When TSF pulls low +125 15 +160 15 120 0.1 C C C C mV A 1.38 0.5 1.15 1.5 1.66 0.75 1.25 2.5 2.75 V V V A/V A TA = +25C 0.45 0.85 20 42 72 SYMBOL CONDITIONS MIN TYP 500 2.55 2.75 65 MAX UNITS A/V V V mV dB
MAX5058/MAX5059
CURRENT-ADJUST AMPLIFIER (CAA)
Note 1: Output resistance to ground used for unity-gain stability. Note 2: VCSO = GCSA(VCSP - VCSN) + VLS.
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Parallelable Secondary-Side Synchronous Rectifier Driver and Feedback-Generator Controller ICs MAX5058/MAX5059
Typical Operating Characteristics
(V+ = +12V, GND = PGND = 0, VDR = VREG, CQSYNC = CQREC = 0, ZCP = ZCN = BUFIN = CSP = CSN = SFN = VSN = GND, VIREF = VVSP = 1.785V, VCOMPS = 0.5V, CVREG = 2.2F, CVP = 1F, CCOMPS = 0.1F, CSFP = 68nF, TA = +25C, unless otherwise noted.)
LDO OUTPUT VOLTAGE (VVREG) vs. INPUT VOLTAGE (MAX5058)
MAX5058/59 toc01
IREF OUTPUT CURRENT vs. TEMPERATURE
MAX5058/59 toc02
LDO OUTPUT VOLTAGE (VVREG) vs. LOAD CURRENT (MAX5059)
10.10 10.08 10.06 10.04 10.02 10.00 9.98 9.96 9.94 9.92 9.90 9.88 9.86 9.84 9.82 9.80 IVREG (mA)
MAX5058/59 toc03
5.0050 5.0045 5.0040 5.0035 VVREG (V) 5.0030 5.0025 5.0020 5.0015 5.0010 5.0005 5.0000 4.9995 4.9990 0 3 6 9 IVREG = 0mA
50.17 50.15 50.13 50.11 IREF (A) 50.09 50.07 50.05 50.03 50.01 49.99 49.97 49.95 49.93 VIREF = 1.785V
12 15 18 21 24 27 30 V+ (V)
-40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C)
VVREG (V)
0 10 20 30 40 50 60 70 80 90 100 110
LDO OUTPUT VOLTAGE (VVREG) vs. LOAD CURRENT (MAX5058)
MAX5058/59 toc04
LDO OUTPUT VOLTAGE (VREG) vs. TEMPERATURE (MAX5058)
5.010 5.008 5.006 5.004 5.002 5.000 4.998 4.996 4.994 4.992 4.990 4.988 4.986 4.984 4.982 4.980 TEMPERATURE (C)
MAX5058/59 toc05
LDO OUTPUT VOLTAGE (VVREG) vs. INPUT VOLTAGE (MAX5059)
10.018 10.016 10.014 VVREG (V) 10.012 10.010 10.008 10.006 10.004 10.002 10.000 9.998
MAX5058/59 toc06
5.04 5.02 5.00 4.98 VVREG (V) 4.96 4.94 4.92 4.90 4.88 4.86
10.020
0 10 20 30 40 50 60 70 80 90 100 110 IVREG (mA)
VVREG (V)
-40 -25 -10 15 20 35 50 65 80 95 110 125
0
3
6
9
12 15 18 21 24 27 30 V+ (V)
LDO OUTPUT VOLTAGE (VVREG) vs. TEMPERATURE (MAX5059)
MAX5058/59 toc07
IREF OUTPUT CURRENT vs. IREF OUTPUT VOLTAGE
50.5 50.0 49.5 IIREF (A) 49.0 48.5 48.0 47.5 47.0 46.5 46.0
MAX5058/59 toc08
10.030 10.025 10.020 10.015 VVREG (V) 10.010 10.005 10.000 9.995 9.990 9.985 9.980
51.0
-40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C)
0
0.5
1.0
1.5
2.0 VIREF (V)
2.5
3.0
3.5
4.0
6
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Parallelable Secondary-Side Synchronous Rectifier Driver and Feedback-Generator Controller ICs
Typical Operating Characteristics (continued)
(V+ = +12V, GND = PGND = 0, VDR = VREG, CQSYNC = CQREC = 0, ZCP = ZCN = BUFIN = CSP = CSN = SFN = VSN = GND, VIREF = VVSP = 1.785V, VCOMPS = 0.5V, CVREG = 2.2F, CVP = 1F, CCOMPS = 0.1F, CSFP = 68nF, TA = +25C, unless otherwise noted.)
QUIESCENT SUPPLY CURRENT vs. INPUT VOLTAGE (MAX5058)
3.0 2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0 3 6 9 V+ (V) 3.0 2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0 3 6 9 V+ (V)
MAX5058/59 toc09
MAX5058/MAX5059
QUIESCENT SUPPLY CURRENT vs. INPUT VOLTAGE (MAX5059)
MAX5058/59 toc10
QUIESCENT SUPPLY CURRENT vs. TEMPERATURE (MAX5058)
2.55 2.50 2.45 IV+ (mA) 2.40 2.35 2.30 2.25 2.20 2.15 2.10 2.05 2.00 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C)
MAX5058/59 toc11
2.60
IV+ (mA)
IV+ (mA)
12 15 18 21 24 27 30
12 15 18 21 24 27 30
QUIESCENT SUPPLY CURRENT vs. TEMPERATURE (MAX5059)
MAX5058/59 toc12
SWITCHING SUPPLY CURRENT vs. INPUT VOLTAGE (MAX5058)
4.5 4.0 3.5 IV+ (mA) 3.0 2.5 2.0 1.5 1.0 0.5 0 fSW = 250kHz
MAX5058/59 toc13 MAX5058/59 toc15
3.0 2.9 2.8 2.7 IV+ (mA) 2.6 2.5 2.4 2.3 2.2 2.1 2.0
5.0
-40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C)
35
7 9 11 13 15 17 19 21 23 25 27 29 V+ (V)
SWITCHING SUPPLY CURRENT vs. TEMPERATURE (MAX5058)
MAX5058/59 toc14
SWITCHING SUPPLY CURRENT vs. INPUT VOLTAGE (MAX5059)
6.0 5.5 5.0 4.5 IV+ (mA) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 3 5 7 9 11 13 15 17 19 21 23 25 27 29 V+ (V) fSW = 250kHz
5.0 4.8 4.6 4.4 IV+ (mA) 4.2 4.0 3.8 3.6 3.4 3.2 3.0 fSW = 250kHz
-40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C)
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Parallelable Secondary-Side Synchronous Rectifier Driver and Feedback-Generator Controller ICs MAX5058/MAX5059
Typical Operating Characteristics (continued)
(V+ = +12V, GND = PGND = 0, VDR = VREG, CQSYNC = CQREC = 0, ZCP = ZCN = BUFIN = CSP = CSN = SFN = VSN = GND, VIREF = VVSP = 1.785V, VCOMPS = 0.5V, CVREG = 2.2F, CVP = 1F, CCOMPS = 0.1F, CSFP = 68nF, TA = +25C, unless otherwise noted.)
SWITCHING SUPPLY CURRENT vs. TEMPERATURE (MAX5059)
MAX5058/59 toc16
REMOTE-SENSE AMPLIFIER (RSA) GAIN vs. TEMPERATURE
MAX5058/59 toc17
RSA GAIN vs. FREQUENCY
5 0 -5 GAIN (dB) -10 -15 -20 -25 -30 -35 -40
MAX5058/59 toc18
6.0 5.8 5.6 5.4 IV+ (mA) 5.2 5.0 4.8 4.6 4.4 4.2 4.0 fSW = 250kHz
0.015 0.014 0.013 VSO OUTPUT (dB) 0.012 0.011 0.010 0.009 0.008 0.007 VVSP = 1.785V
10
-40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C)
-40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C)
0
0.1k
1k
10k
100k
1M
10M 100M
FREQUENCY (Hz)
CURRENT-SENSE AMPLIFIER (CSA) GAIN vs. TEMPERATURE
MAX5058/59 toc19
CSA INPUT OFFSET vs. TEMPERATURE
25.0 24.9 INPUT OFFSET (mV) 24.8 24.7 24.6 24.5 24.4 24.3 24.2 24.1 24.0
MAX5058/59 toc20
20.04 20.03 20.02 CSA GAIN (V/V) 20.01 20.00 19.99 19.98 19.97 19.96 VCSP = 100mV
25.1
-40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C)
-40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C)
CSA GAIN vs. FREQUENCY
25 20 15 GAIN (dB) 10 5 0 -5 -10 -15 -20 0.01 0.1 1 10 100 1k 10k FREQUENCY (Hz)
MAX5058/59 toc21
ZERO-CURRENT COMPARATOR THRESHOLD vs. TEMPERATURE
5.35 ZCP THRESHOLD (mV) 5.30 5.25 5.20 5.15 5.10 5.05 5.00 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C)
MAX5058/59 toc22
30
5.40
8
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Parallelable Secondary-Side Synchronous Rectifier Driver and Feedback-Generator Controller ICs
Typical Operating Characteristics (continued)
(V+ = +12V, GND = PGND = 0, VDR = VREG, CQSYNC = CQREC = 0, ZCP = ZCN = BUFIN = CSP = CSN = SFN = VSN = GND, VIREF = VVSP = 1.785V, VCOMPS = 0.5V, CVREG = 2.2F, CVP = 1F, CCOMPS = 0.1F, CSFP = 68nF, TA = +25C, unless otherwise noted.)
ZERO-CURRENT PROPAGATION DELAY vs. TEMPERATURE
MAX5058/59 toc23
MAX5058/MAX5059
SFA AMPLIFIER MAXIMUM SINK CURRENT vs. TEMPERATURE
33.8 33.6 SFA SINK CURRENT (A) 33.4 33.2 33.0 32.8 32.6 32.4 32.2 32.0 SFP = +2.5V SFN = 0V
MAX5058/59 toc24
CURRENT-ADJUST VOLTAGE TO CURRENTCONVERTER ADJUSTMENT RANGE vs. TEMPERATURE
1.59 ADJUSTMENT RANGE (A) 1.58 1.57 1.56 1.55 1.54 1.53 1.52 1.51 1.50
MAX5058/59 toc25
90 85 ZCP TO QSYNC DELAY (ns) 80 75 70 65 60 55 50 10mV OVERDRIVE
34.0
1.60
-40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C)
-40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C)
-40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C)
BUFIN TO QREC LOW-TO-HIGH PROPAGATION DELAY vs. TEMPERATURE
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 TEMPERATURE (C) 60 58 56 54 52 50 48 46 44 42 40 38 36 34 32 30
MAX5058/59 toc26
BUFIN TO QREC HIGH-TO-LOW PROPAGATION DELAY vs. TEMPERATURE
MAX5058/59 toc27
PROPAGATION DELAY (ns)
-40 -25 -10 5 20 35 50 65 80 95 110 125
PROPAGATION DELAY (ns)
-40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C)
BUFIN TO QSYNC LOW-TO-HIGH PROPAGATION DELAY vs. TEMPERATURE
MAX5058/59 toc28
BUFIN TO QSYNC HIGH-TO-LOW PROPAGATION DELAY vs. TEMPERATURE
38 PROPAGATION DELAY (ns) 36 34 32 30 28 26 24 22 20
MAX5058/59 toc29
60 58 PROPAGATION DELAY (ns) 56 54 52 50 48 46 44 42 40
40
-40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C)
-40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C)
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9
Parallelable Secondary-Side Synchronous Rectifier Driver and Feedback-Generator Controller ICs MAX5058/MAX5059
Pin Description
PIN 1 2 3 4 NAME ZCP ZCN GND SFN FUNCTION Zero-Inductor Current-Sense Comparator Input. The source voltage of the freewheeling FET (N4 in the Typical Application Circuit) is sensed. The gate drive is terminated when this voltage becomes positive during a primary power-OFF cycle. Zero-Inductor Current-Sense Comparator Negative Input Ground Connection Negative Input of the Share-Force Amplifier. Connect the SFN inputs together from all the power-supply secondaries, then connect to the load return terminal (isolated GND). Connect to GND when current sharing is not used. Positive Input of the Share-Force Amplifier. Connect the SFP pins together from all the power-supply secondaries. Leave this pin unconnected when current sharing is not used. Thermal Warning Flag Output Margin-Up Logic Input. When toggled high, the power-supply output voltage is set to the high margin. Margin-Down Logic Input. When toggled high, the power-supply output voltage is set to the low margin. Resistor Connection for Margin-Down Resistor Connection for Margin-Up Reference Current Output. A resistor from this current source output to GND sets the reference voltage used by the error amplifier. Compensation Connection for the Error Amplifier. The feedback optocoupler LED is also connected to this point. This open-drain output is capable of sinking at least 5mA. Inverting Input of the Error Amplifier. A voltage-divider connected to this input scales the power-supply output voltage for regulation. Output of the Remote-Sense Amplifier Negative Input of the Remote-Sense Amplifier. Connect this to the negative terminal of the load. Positive Input of the Remote-Sense Amplifier. Connect this to the positive terminal of the load. Output of the Current-Sense Amplifier. It can be used to monitor the output current. Connect this input to the negative terminal of the output current-sense resistor. Connect to GND when not used. Connect this input to the positive terminal of the output current-sense resistor. Connect to GND when not used. Compensation Pin for Internal +4V Preregulator. A minimum 1F low-ESR capacitor must be connected to this pin for bypassing. Supply Connection for the IC and Input to the Internal 5V (MAX5058) or 10V (MAX5059) Regulator. Maximum voltage on this input is 28V. Regulated +5V (MAX5058) or +10V(MAX5059) Output Used by the Internal Circuitry and the Output Drivers. A minimum 1F capacitor must be connected to this pin for bypassing. Input for the Synchronizing Pulse. This pulse is provided by the primary-side power IC. Supply Connection for the Output Drivers. Can be connected to VREG for 5V (MAX5058) or 10V (MAX5059) operation. Driver Output for the Rectifying MOSFET Power-Ground Connection. Return ground connection for the gate-driver pulse currents. Exposed Pad. This is the exposed pad on the underside of the IC. Connect the exposed paddle to GND and to a large copper ground plane to aid in heat dissipation.
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 --
SFP
COMPS Compensation Output of the Load-Share Transconductance Amplifier TSF MRGU MRGD RMGD RMGU IREF COMPV INV VSO VSN VSP CSO CSN CSP VP V+ VREG BUFIN VDR QREC PGND
QSYNC Driver Output for the Recirculating MOSFET EP
10
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Parallelable Secondary-Side Synchronous Rectifier Driver and Feedback-Generator Controller ICs MAX5058/MAX5059
MARGINING BLOCK MRGU 8 50k
MAX5058/MAX5059
REGULATOR AND THERMAL MANAGEMENT BLOCK SD DRIVERS UVLO AND THERMAL SHUTDOWN LDO 5V/10V PREG 4V 22 V+ 21 VP 23 VREG 7 +125C FLAG TSF
MRGD
9 50k
RMGD 10 QMD CURRENT-SHARE BLOCK R R
RMGU 11 QMU SFA 5 SFP
R ERROR AMPLIFIER BLOCK COMPV 13 INV 14 E/A V TO I 500S CAA 42mV
R 4 SFN
X1
IREF 12
IREF 50A REFERENCE CURRENT BLOCK
I = (1.15 x (VCAA - 1.25))A VCAA 1.25V
0.5V X2
20 CSP
10 CSN 18 CSO
COMPS
6 REMOTE-SENSE AMPLIFIER BLOCK
VSO 15 VSN 16 X1 VSP 17 RSA
GATE-DRIVER BLOCK BUFIN 24 ZCP 1 20ns 5mV
25 VDR 26 QREC
28 QSYNC ZCN GND 2 20ns 3 30ns FALLING EDGE DELAY 27 PGND
SD DRIVERS
Figure 1. MAX5058/MAX5059 Functional Diagram ______________________________________________________________________________________ 11
Parallelable Secondary-Side Synchronous Rectifier Driver and Feedback-Generator Controller ICs MAX5058/MAX5059
Detailed Description
The MAX5058/MAX5059 enable the design of high-efficiency, isolated power supplies using synchronous rectification on the secondary side. These devices commutate the secondary-side MOSFETs by providing a clean gate-drive signal that is synchronized to the power MOSFET switching in the primary side of the isolation transformer. Once fully enhanced, the secondaryside MOSFETs have very low on-resistance, producing a voltage drop much lower than Schottky diodes, resulting in much higher efficiencies. Simultaneous conduction of the synchronous rectifier MOSFETs is avoided by having a look-ahead signal before the primary MOSFETs turn on. This eliminates large current spikes from a shorted transformer secondary. The MAX5058 has a 5V internal gate-drive voltage regulator that can be used with logic-level MOSFETs. The MAX5059 has a 10V internal gate-drive voltage regulator that can be used with high-gate-voltage MOSFETs. In addition to the gate drivers, there are blocks that make the MAX5058/MAX5059 complete secondaryside solutions. These blocks are as follows: * Regulator and thermal-management block * Buffer input and gate-driver block * Reference-current block * Error-amplifier block * Margining block * Remote-sense amplifier block * Current-share block cent supply current of the MAX5058/MAX5059, as well as the current for the MOSFET drivers. Estimate the total required supply current by using the following formula: IV + = ISW + fSW x (QN3 + QN4 ) where IV+ is the current that must be supplied into V+ and QN3, QN4 are the total gate charges of MOSFETs N3 and N4 in the Typical Application Circuit. fSW is the switching frequency and ISW is the switching current of the part. Use high-quality ceramic capacitors to bypass V+ and VREG. Use additional capacitance as required for bypassing switching currents generated by the drivers when driving the chosen MOSFETs. Connect at least a 1F ceramic capacitor at the output of the regulator VREG for stability. The MAX5058/MAX5059 have an exposed pad at the back of the package to enable heatsinking directly to a ground plane. When soldered to a 1in2 copper island, these devices are able to dissipate approximately 1.9W at +70C ambient temperature. Connect the exposed pad to the GND. In addition to the regulators, this block contains a thermal-shutdown circuit that shuts down the gate drivers if the die temperature exceeds +160C. This is a last resort shutdown mechanism. The trigger of this shutdown mechanism must be avoided. Turning off the secondary synchronous rectifier drivers in this manner while the output carries the full load current causes the current to be diverted to the lossy external diodes or body diodes of the MOSFETs. This, in most cases, leads to rectifier failure due to power dissipation. To prevent this, make use of the TSF output (temperature warning flag). TSF is an open-drain output that gets asserted when the die temperature exceeds +125C, well before the actual thermal shutdown at +160C. An optocoupler connected from VREG to the TSF pin can provide a means for shutting down the switching at the primary side, thus avoiding catastrophic failure.
Regulators and Thermal Management
The linear regulators in the MAX5058/MAX5059 provide power for the internal circuitry, as well as power for running the external synchronous MOSFETs. Design is simplified by deriving the power from the secondary winding before the output-filter inductor. The peak voltage at the secondary is at least twice the output voltage, yielding more than 7V peak even for output voltages down to 3.3V. Use a diode and a capacitor to rectify and filter the voltage before applying it to V+ (see D6 and C32 in the Typical Application Circuit). The input for the regulator is V+ and the output is VREG. Connect VDR to VREG to provide the supply for the gate driver's QREC and QSYNC. For logic-level MOSFETs, use the MAX5058. For conventional MOSFETs that require 10V to be fully enhanced, use the MAX5059. The V+ input voltage range is from +4.5V to +28V. Supply enough current to this input to satisfy the quies-
Buffer Input (BUFIN) and MOSFET Drivers
The MAX5058/MAX5059 drive external N-channel MOSFETs at QSYNC and QREC. The QSYNC output drives the gate of the freewheeling MOSFET N4 in the Typical Application Circuit. The QREC output drives the gate of the rectifying MOSFET N3 in the Typical Application Circuit. Each gate-driver output is capable of sinking and sourcing up to 2A peak current, enabling the MAX5058/MAX5059 to drive high-gatecharge MOSFETs.
12
______________________________________________________________________________________
Parallelable Secondary-Side Synchronous Rectifier Driver and Feedback-Generator Controller ICs
The MOSFET drivers are synchronized to the primaryside switching by using the BUFIN input. BUFIN accepts the PWM information from the primary through a high-speed optocoupler or through a small isolation pulse transformer. Figures 2 through 6 show the interface details using an optocoupler or a pulse transformer with two different kinds of primary-side PWM controllers. For proper operation, the MAX5051, MAX5042, and MAX5043 devices generate a look-ahead signal that precedes the actual switching of the primary MOSFETs by a small amount of time, typically less than 100ns. Additional circuitry may be required when the MAX5058/MAX5059 are used with other primary-side controllers not capable of providing a look-ahead signal. When BUFIN goes high, QREC goes high and QSYNC goes low. When BUFIN goes low, QREC goes low and QSYNC goes high. The MAX5058/MAX5059 provide improved efficiency at light loads by allowing discontinuous conduction operation. A zero-crossing comparator with inputs ZCP and ZCN monitors the current through the freewheeling MOSFET using a sense resistor at its source. The freewheeling MOSFET is turned off when the inductor current is near zero. The actual threshold can be externally adjusted. The Typical Application Circuit shows one method for trip-point adjustment using components R31 and R34. BUFIN is internally clamped to 4V. Use a voltage-divider, if necessary, to reduce any external voltage applied to this pin to less than 4V.
MAX5058/MAX5059
MAX5042 MAX5043
REG5 PPWM BSS84 560 330 BUFIN 2k PWMNEG PS9715 OR EQUIVALENT HIGH-SPEED OPTOCOUPLER GND
MAX5058
VREG (5V)
Figure 2. Interface of MAX5058 to MAX5042/MAX5043 Using a High-Speed Optocoupler
MAX5042 MAX5043
REG5 PPWM BSS84 560 MMBT3904
MAX5059
3.10k VREG (10V)
330 BUFIN 2k PWMNEG PS9715 OR EQUIVALENT HIGH-SPEED OPTOCOUPLER 1F 4.42k GND
Figure 3. Interface of MAX5059 to MAX5042/MAX5043 Using a High-Speed Optocoupler ______________________________________________________________________________________ 13
Parallelable Secondary-Side Synchronous Rectifier Driver and Feedback-Generator Controller ICs MAX5058/MAX5059
MAX5051
REG5 LXVDD LXH BSS84 560 330 1F 2k GND 2k PS9715 OR EQUIVALENT HIGH-SPEED OPTOCOUPLER GND BUFIN VREG (5V) 4.7
MAX5058
Figure 4. Interface of MAX5058 to MAX5051 Using a High-Speed Optocoupler
MAX5051
REG5 LXVDD LXH
4.7 3.10k MMBT3904 BSS84 560 330 1F 2k GND 2k PS9715 OR EQUIVALENT HIGH-SPEED OPTOCOUPLER 1F 4.42k GND BUFIN
MAX5059
VREG (10V)
Figure 5. Interface of MAX5059 to MAX5051 Using a High-Speed Optocoupler
MAX5051
REG5 LXVDD
4.7
MAX5058 MAX5059
D1 LXH
1F T1
1N4148
301 BUFIN 2k
LXL D2 GND T1: PULSE ENGINEERING, PE-68386 D1, D2: CENTRAL SIMICONDUCTOR, CMOSH-3
GND
Figure 6. Interface Circuit to MAX5051 Using a Pulse Transformer 14 ______________________________________________________________________________________
Parallelable Secondary-Side Synchronous Rectifier Driver and Feedback-Generator Controller ICs
Reverse-Current Prevention in Synchronous Rectifiers One benefit of secondary-side synchronous rectification is increased efficiency. Another benefit is that it allows the inductor current to remain continuous throughout the operating load range. This results in constant loop dynamics that are easy to compensate. In some cases, it may be necessary to turn off the freewheeling MOSFET when the current through this device attempts to flow from drain to source. Turning off this MOSFET can be done to enhance efficiency at low output current. When multiple power supplies are paralleled, the power supply with the highest output voltage has a tendency to source current into the power-supply outputs with lower output voltage. Turning off the freewheeling MOSFET also prevents this current back-flow. When the inductor current is allowed to become discontinuous, the loop dynamics change and the circuit must be compensated accordingly to accommodate stable continuous and discontinuous mode operation. Turning off the freewheeling MOSFET is accomplished by using the zero-current comparator (pins ZCP and ZCN). Use this comparator to sense reverse current in the freewheeling MOSFET and turn off the device by pulling QSYNC low. An internal latch prevents the freewheeling MOSFET from turning on until the off-time of the next cycle. connected from IREF to GND. INV is the inverting input and connects to the center of a resistive divider from OUT to INV to GND. The output of the error amplifier, COMPV, connects to the cathode of the LED in the optocoupler to control the diode current that transmits the error signal back to the primary-side controller. An open-drain-output error amplifier simplifies interfacing with the feedback optocoupler. Use this error amplifier the same way as the industry-standard TL431 shunt reference. The open-drain output provides flexibility that may be necessary when additional functionality such as secondary current-limit regulation is required. Unlike the TL431, the output of the internal error amplifier of the MAX5058/MAX5059 is guaranteed to be a maximum of 200mV with a 5mA drain current, compared to 2.5V for the TL431 and 1.24V for the TLV431. In some cases, it is possible to avoid the use of the output voltage-divider (R1 and R2) by connecting INV to the output through just R1. This eliminates the voltage tolerance errors caused by R1 and R2. Output voltage in this configuration is set directly by using a suitable resistor at IREF. Figure 7 shows this configuration.
MAX5058/MAX5059
VOUT
Reference Current
The MAX5058/MAX5059 do not have an explicit reference voltage generator. Instead, they contain a 1%accurate trimmed 50A current source. This allows significant flexibility in setting the reference voltage. In some cases, the output-voltage resistive divider, consisting of R1 and R2 in the Typical Application Circuit, can be eliminated by selecting a suitable resistor value at the IREF pin. This reduces the error that the output voltage-divider may add. Use a low-value bypass capacitance at this pin to eliminate noise. Typical values for this capacitance are calculated by considering the pole that it presents with R12. This pole must be placed well beyond the frequency range of interest of the current-share loop. Use values less than 2.2nF.
R1
COMPV 13 INV 14 E/A
C28
VOUT = (50A) x R12 FOR: 0.5V VOUT 2.5V IREF 50A IREF 12 R12
Error Amplifier
The MAX5058/MAX5059 incorporate a 1.3MHz unity gain-bandwidth error amplifier with inputs INV, IREF, and output COMPV. IREF is the noninverting input and also serves as the reference voltage generator with the internal 50A current source and the external resistor
Figure 7. Output Voltage Regulation for 0.5V VOUT 2.5V
______________________________________________________________________________________
15
Parallelable Secondary-Side Synchronous Rectifier Driver and Feedback-Generator Controller ICs MAX5058/MAX5059
VOUT > 2.5V C27 R19
R12
Figure 8 shows a typical configuration with output voltages high enough (V OUT > 2.5V) to allow a typical optocoupler to be fully biased. In this case, there are two feedback paths--one though the error amplifier and one through the output-connected optocoupler. This second feedback path must be considered when compensating the overall feedback loop. Figure 9 shows a typical configuration with an optocoupler for output voltages lower than 2.5V. In this case, the direct connection of the optocoupler to the output is not possible. There is only one feedback path and the error-amplifier feedback network must be designed accordingly. Figure 10 shows the simplified block diagram for the error amplifier.
R12
COMPV 13 INV 14 E/A
C28
Voltage Margining
IREF 12 R12
IREF 50A
Figure 8. Optocoupler Connection for VOUT > 2.5V
VREG (PIN 23) 0.5V < VOUT < 2.5V
C27
R19
Rff
The margining inputs MRGU (margin up) and MRGD (margin down) control two internal MOSFETs with opendrain outputs at RMGU and RMGD, respectively. When margining is used, connect two pullup resistors from RMGU and RMGD to I REF . A logic-high voltage at MRGU causes QMU (see Figure 1) to open, increasing the equivalent resistance at IREF and the reference voltage (VIREF). The error-amplifier inverting input, INV, tracks IREF and forces the primary-side controller to increase the output voltage. MRGD has the opposite effect. When a logic high is applied to MRGD, QMD turns on, decreasing the equivalent resistance at IREF and effectively reducing VIREF. This causes INV to track and force the primary-side controller to reduce the output voltage. The margining inputs MRGU and MRGD are internally pulled to GND with 40k resistors. When margining is not used, the inputs can be left floating or connected to GND to make VIREF = 50A x R12. Calculation Procedure for Output-Voltage Setting Resistors and Margining Use the following step-by-step procedure to calculate the output-voltage setting and margining resistors (see the Typical Application Circuit):
COMPV C28 13 INV 14 E/A
Rf R1 Cf
IREF 50A
IREF 12
INV 14 IREF
R12
COMPV 13
12
Figure 9. Optocoupler Connection for VOUT < 2.5V 16
Figure 10. Simplified Error-Amplifier Diagram
______________________________________________________________________________________
Parallelable Secondary-Side Synchronous Rectifier Driver and Feedback-Generator Controller ICs
1) Select a parallel equivalent resistance Req value to produce the nominal reference voltage. For example, Req = 35.4k gives you VIREF = 1.77V. 2) Select the margin-up percentage value: U = 5% 3) Calculate R32: R32 = Req x 100% + U U Req = 35.24k. 7) Calculate R33: R33 = R12 x (100% + D) - 100% x Req Calculated 100% x Req x R12 5) Select the margin-down percentage value: D = 5% 6) Recalculate Req with the selected values: Req = R12R32 R12 + R32
MAX5058/MAX5059
R32 = 743.4k. Calculated Select the nearest 0.1% value. Selected R32 = 741k. 4) Calculate R12: R x U R12 = 32 100% R12 = 37.05k. Calculated Select the nearest 0.1% value. R12 = 37k. Selected
R33 = 361.186k. Select the nearest 0.1% value:
R33 = 361k. Selected 8) Calculate the reference voltage with the selected chosen values: VIREF = 50A Req. Req from step 6. VIREF = 1.762V.
VOUT
COMPV 13 INV 14 E/A
C28 VSP 17 VSO 15 RSA VSN 16
VOUT = (50A) x R12 FOR: 0.5V VOUT 2.5V IREF 50A IREF 12 R12
Figure 11. Remote-Sense Amplifier Connection for 0.5V VOUT 2.5V ______________________________________________________________________________________ 17
Parallelable Secondary-Side Synchronous Rectifier Driver and Feedback-Generator Controller ICs MAX5058/MAX5059
VOUT
R1
R2
COMPV 13 INV 14 E/A
C28 VSP 17 VSO 15 RSA VSN 16
IREF 50A
IREF 12 R12
R1 VOUT = 1 + R2
(
)
VIREF
VIREF = (50A) R12
Figure 12. Remote-Sense Amplifier Connection for VOUT > 2.5V (or any Other Arbitrary Voltage)
9) Select a value for R1 and calculate R2 for VOUT = 3.3V: R1 = 19.1k R2 = VIREF R1 VOUT - VIREF
11 shows this configuration. Figure 12 shows the use of the remote-sense amplifier with a voltage-divider. The remote-sense amplifier has an input bias current of 100A. The impedance of R1 and R2 must be kept low in this configuration to avoid excessive errors in the output-voltage set point.
Current Sharing
R2 = 21.882k. Select the nearest 1% value. R2 = 21.8k. When margining is not used, substitute R12 for Req in step 8 and go to step 9. When multiple power modules are providing power to the same load, the load current must be shared equally to provide the best reliability and thermal distribution. The MAX5058/MAX5059 contain circuitry that enable current sharing among paralleled power supplies without requiring an explicit controlling master circuit. Current sharing is accomplished by connecting together the current-share bus pins (SFP and SFN) of all paralleled power supplies (see Figure 13), thus creating a current-force/share bus. The voltage level on this differential bus is proportional to the output current of the power supply that has the highest current compared to the other supplies. The number of power supplies that can be paralleled with this method is limited only by practical considerations.
Remote-Sense Amplifier
Use the remote-sense amplifier (RSA in Figure 1) to directly sense the voltage across the load, compensating for voltage drops in PC board tracks or load connection wires. The remote-sense amplifier is a unity-gain amplifier with sufficient bandwidth to not interfere with the normal operation of the voltage-control loop. Direct sensing of the output voltage is possible if the output voltage is between 0.5V to 2.5V. Figure
18
______________________________________________________________________________________
Parallelable Secondary-Side Synchronous Rectifier Driver and Feedback-Generator Controller ICs MAX5058/MAX5059
MRGU POWER MODULE VIN+ VINMRGD CSN CSP VOUT+
MAX5058 MAX5051
AND OR
VSP VSN VOUT-
SYNCIN STARTUP SYNCOUT
MAX5059
SFN SFP
MRGU POWER MODULE VIN+ 36V TO 72V VINVIN+ VIN-
MRGD
CSN CSP VOUT+
MAX5058 MAX5051
AND OR
VSP LOAD VSN VOUT-
SYNCIN STARTUP SYNCOUT
MAX5059
SFN SFP
MRGU POWER MODULE VIN+ VIN-
MRGD CSN CSP VOUT+
MAX5058 MAX5051
AND OR
VSP VSN VOUT-
SYNCIN STARTUP SYNCOUT
MAX5059
SFN SFP
Figure 13. Paralleling Multiple Power-Supply Modules for Current Sharing
When the MAX5051 is used as the primary-side controller, additional benefits are also realized with its special paralleling pins. The MAX5051 allows simultaneous shutdown and wake-up, as well as frequency synchronization and 180 degree out-of-phase operation of each connected primary. The current-share loop consists of the following functional blocks: * A diode ORed force amplifier that connects with the other modules and forces the bus to carry a voltage proportional to the highest current among the modules.
* * * *
A sense amplifier that senses this share-bus voltage and applies it to internal circuitry. A fixed gain of 20, current-sense amplifier that senses the output current through a sense resistor. A current-adjust amplifier that functions as an erroramplifier block in the current-share loop. A voltage-to-current (VtoI) block that adds a small amount of current to the reference current, increasing the reference voltage and enabling the module to share more current.
______________________________________________________________________________________
19
Parallelable Secondary-Side Synchronous Rectifier Driver and Feedback-Generator Controller ICs
V TO I
1.5A
SLOPE = 1.15A/V
VCAA 1.25V
Figure 14. Transfer Function Curve of the V to I Block
FEEDBACK NETWORK
E/A GPS (s)
PWM STAGE AND FILTERS
VOUT
RS
Current-sharing functions follow: The voltage across the current-sense resistor for each module is sensed and compared to the voltage on the current-share bus. The voltage on the current-share bus represents the current from the module that has the highest output current compared to the other modules. Each module compares its current to this maximum current. If its current is less than the maximum, then the module increases its reference current with the VtoI block. This raises the reference voltage presented at the noninverting input of the error amplifier. With a higher reference voltage, the output voltage of the module rises in an attempt to increase its output current. This process continues until the currents balance between the modules. The current-adjust amplifier (see Figure 1) has an offset at its inverting input that requires the share-bus voltage to reach 40mV before the current-share control loop attempts to regulate the output-load-current balance. Thus, the current-share regulation does not begin until the current-sense signals have exceeded 2mV (i.e., 42mV/20). Figure 15 shows the simplified equivalent small-signal circuit of the current-share control loop. The currentadjust amplifier represents the error amplifier in this loop. The command signal, which is the voltage across the SFP and SFN pins, is applied to the noninverting input of this amplifier. For small-signal analysis, the noninverting pin is shown grounded in Figure 15. This is a low-bandwidth loop. Assuming a much smaller unity-gain crossover bandwidth (fCS) for the current-share loop compared to the main output-voltage-regulation loop (i.e., fCS << fC), the open-loop gain of the current-share loop can be written as: GCAA (s) GT (s) = GSFA (s) x x (GVtoI(s) x RIREF ) s x CCOMPS x GPS (s) x RS RS + RLOAD
MAX5058/MAX5059
+ VSENSE RLOAD GCSA (s) CSA
GV TO I (s) V TO I RIREF
GCAA (s) CAA CCOMPS
Figure 15. Small-Signal Equivalent Current-Share Control Loop
The adjustment range and thus the sharing capability of the modules is limited by the amount of additional output voltage boost possible through the VtoI block. The typical voltage boost is +3% (i.e., 1.5A/50A). Figure 14 shows the transfer function of the VtoI block. This adjustment range also sets a limit on the amount of voltage drop allowed for current sharing. For effective current sharing, the sum of all voltage drops must be kept below 3% and the output-to-load connection drop of each power module must be kept equal.
where fCS is the unity-gain crossover frequency of the current-share loop (typically 10Hz to 100Hz), fC is the unity-gain crossover frequency of the main output loop, GPS(s) is the gain of the power stage from the reference voltage input of the error amplifier to the output (GPS = VOUT/VIREF), RS is the current-sense resistor, and RLOAD is the load resistance. Note that the currentshare loop bandwidth is highest for the lowest value of RLOAD (maximum load).
20
______________________________________________________________________________________
Parallelable Secondary-Side Synchronous Rectifier Driver and Feedback-Generator Controller ICs
POWER-STAGE GAIN/PHASE
20 15 GAIN PHASE (DEGREES/div) 10 GAIN (dB/DIV) 5 0 -5 -10 -15 -20 1 10 100 FREQUENCY (Hz) 1k 10k -90 -45 0 PHASE 45 90
GT (s) = 20 x
(500S) x 1.15A / V x R ( ) IREF s x CCOMPS V RS x OUT x VIREF RS + RLOAD (36.61F x Hz / V) x RS x VOUT fCS x (RS + RLOAD )
MAX5058/MAX5059
Equating |GT| = 1 and solving for CCOMPS yields: CCOMPS =
Figure 16. Idealized (with Ideal Power Stage and Optocoupler) Frequency Response (GPS(s)) from Noninverting Input of the Error Amplifier to the Output of the Power Supply for the Typical Application Circuit of Figure 18
The current-sharing loop is compensated with a capacitor from COMPS to GND. This results in a dominant pole that forces the loop gain of the current-share loop to cross 0dB with a single pole (20dB/decade) rolloff. When RLOAD >> RS, the above can be simplified further. CCOMPS = Example: RS = 2m VOUT = 3.3V
(36.61F x Hz / V) x RS x VOUT
fCS x RLOAD
80 60 40 GAIN (dB/DIV) 20 0 -20 -40 -60 -80 1 10 100 FREQUENCY (Hz) 1k 10k GAIN PHASE
180 135 PHASE (DEGREES/div) 90 45 0 -45 -90 -135 -180
fCS = 10Hz RLOAD = 0.22
CCOMPS =
(36.61F x Hz / V) x (0.002) x (3.3V) (10Hz) x (0.22)
0.11F The resulting overall open-loop response of the currentshare control loop is shown in Figure 17.
Figure 17. Overall Open-Loop Response of the Current-Share Loop
Applications Information
Isolated 48V Input Power Supply
Figure 18 shows a complete design of an isolated synchronously rectified power supply with a +36V to +75V telecom input voltage range. This design uses the MAX5051 as the primary-side controller and the MAX5058 as the secondary-side synchronous rectifier driver. Figures 19 though 24 show some of the performance aspects of this power-supply design. This power supply can sustain a continuous short circuit at its output terminals. This circuit is available as a completely built and tested evaluation kit (MAX5058EVKIT).
Figure 16 shows the idealized small-signal response of the Typical Application Circuit from the noninverting input of the error amplifier to the output. This response shows that the unity-gain crossover frequency of the current-share loop can easily be placed between 10Hz and 100Hz, while at the same time avoiding interaction with the main voltage-control loop. For frequencies below 100Hz, GT(s) can be written as (using the DC gain value for GPS(s)):
______________________________________________________________________________________
21
MAX5058/MAX5059
Figure 18. Schematic of a +48V Input, 3.3V at 15A Output, Synchronous Rectified, Isolated Power Supply
Parallelable Secondary-Side Synchronous Rectifier Driver and Feedback-Generator Controller ICs
22
1 RCOSC TP6 R4 1M 1% SYNCIN 27 D2 2 +VIN -VIN 1 4 XFRMRH 24 3 +VIN REG9 2 R29 1 R36 VOUT (CSN) 0.004 1% (CSP) N5 1 23 D1 D6 V+ C8 4.7F XFRMRH DRVB 2 D4 N4 4 1 3 VREG R26 0.002 1 N3 3 2 1 4 C39 220pF ZCP R34 220 C23 1000pF R31 220 1% 2 8T 5 6 5 8 8 7 2T 1 D5 6 4T 10 8 7 6 5 4 1 C20 220pF R14 270 R17 0.027 1% R18 4.7 VOUT C22 2200pF 2kV PVIN R22 15k +VIN R38 10 R10 20 T1 REG9 PVIN DRVDD 11 STT PGND DRVL LXVDD CS IC_PADDLE 13 LXH LXL 14 29 15 16 R9 8.2 N2 3 2 17 C9 1F 18 D3 +VIN C34 330pF 7 8 6 5 R13 47 C13 270F 4V C14 270F 4V C15 270F 4V L1 2.4H XFRMRH R8 8.2 C32 1F R7 0 DRVB 5 6 C10 0.47F 100V C11 0.47F 100V C12 1F 100V C25 0.047F 100V N1 7 ON/OFF R6 R5 1M 38.3k 1% 1% 3 8 26 25 C7 0.22F +VIN +VIN 28 XFRMRH R35 0 2 SYNCOUT RCFF FLTINT 4 CON STARTUP UVLO 3 5 CSS COMP 6 R15 31.6k 1%
REG5
R21 24.9k 1%
C1 100pF
+VIN
TP5
R25 100k
C2 390pF
C5 4700pF GND
D8
U1 MAX5051
AVIN
R16 10.5k 1% 7 FB BST 8 REG5 DRVH 9 REG9 DRVB 10 19 PVIN XFRMRH 20 21 REG9 22 REG5
C4 4.7F
C3 4.7F C33 1F 10V
R20 0.004 1% VOUT
C6 0.1F
C18 1000pF
SGND
REG5 12
LXVDD
R27 10
C19 1F
28 QSYNC
15 VSO 14 INV 2 C28 0.047F ZCN COMPV 13 OPTO_CAT
R1 19.1k 1%
LXH
LXL
R2 19.1k 1% 26 QREC 16 R27 10 IREF 12 R32 698k 0.5% VSN RMGU 11 R12 34.8k 0.5%
REG5
R3 2.2k 1 U2 2 OPTO_CAT REG9 R19 475 C27 0.15F C21 4.7F 80V
U3
17 VOUT VOUT (CSN) TP1 VSP 18 19 (CSP) C30 1F 21 C35 1F V+ VREG VP 22 23 20
4
C24 1000pF
MAX5058
CSO CSN CSP
RMGD MRGD MRGU TSF COMPS
10 9 8 7 6
R33 340k 0.5%
C37 220pF
R11 360
3
TPMD TPMU TP2
TP3
C17 0.33F
C26 0.1F
VDD = 3V RL = 16 fIN = 10kHz V+ D10 VREG
SFP SFN 6 GND
5 4 3
C36 1F TP7 TP8 R23 10 C16 3.3F R24 10 PGND 27 C38 0.068F
LXH D9 1 T2
______________________________________________________________________________________
D7 LXVDD C31 0.1F LXL 3 4 R28 301 1% 25 C29 1F R30 2k 1% VDR IC_PADDLE 24 29
Typical Application Circuit
BUF_IN
Parallelable Secondary-Side Synchronous Rectifier Driver and Feedback-Generator Controller ICs MAX5058/MAX5059
95 90 85 EFFICIENCY (%) 80 75 70 65 R20 = R26 = R36 = 0 60 0 2 4 6 8 10 12 14 LOAD CURRENT (A) POWER DISSIPATION (W) 8 R20 = R26 = R36 = 0 7 6 5 4 3 2 1 0 0 2 4 6 8 10 12 14 LOAD CURRENT (A)
Figure 19. Efficiency at Nominal 3.3V Output Voltage vs. Load Current (48V Nominal Input Voltage)
Figure 20. Power Dissipation at Nominal 3.3V Output Voltage vs. Load Current (48V Nominal Input Voltage)
RL = 0.22
R20 = R26 = R36 = 0 VOUT 1V/div
R20 = R26 = R36 = 0 VOUT 100mV/div
ILOAD 5A/div ILOAD 5A/div
4ms/div
1ms/div
Figure 21. Turn-On Transient at Full Load (Resistive Load) VOUT
Figure 22. Output Voltage Response to Step Change in Load Current (ILOAD from 50%, max to 75%, max)
______________________________________________________________________________________
23
Parallelable Secondary-Side Synchronous Rectifier Driver and Feedback-Generator Controller ICs MAX5058/MAX5059
R20 = R26 = R36 = 0
R20 = R26 = R36 = 0
VOUT 50mV/div
ILOAD 10A/div 1ms/div
ILOAD 10A/div 20ms/div
2s/div
Figure 23. Output Voltage Ripple at +48V Nominal Input Voltage and Full Load Current (Scope Bandwidth = 20MHz)
Figure 24. Load Current (10A/div) as a Function of Time when the Converter Attempts to Turn On into a 50m Short Circuit
Pin Configuration
TOP VIEW
ZCP 1 ZCN 2 GND 3 SFN 4 SFP 5 COMPS 6 TSF 7 MRGU 8 MRGD 9 RMGD 10 RMGU 11 IREF 12 COMPV 13 INV 14 28 QSYNC 27 PGND 26 QREC 25 VDR
Chip Information
TRANSISTOR COUNT: 1762 PROCESS: BiCMOS
MAX5058AUI MAX5059AUI
24 BUFIN 23 VREG 22 V+ 21 VP 20 CSP 19 CSN 18 CSO 17 VSP 16 VSN 15 VSO
TSSOP CONNECT EXPOSED PADDLE TO GND.
24
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Parallelable Secondary-Side Synchronous Rectifier Driver and Feedback-Generator Controller ICs
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
TSSOP 4.4mm BODY.EPS
PACKAGE OUTLINE, TSSOP, 4.40 MM BODY EXPOSED PAD
MAX5058/MAX5059
21-0108
C
1 1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 25 (c) 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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