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NTLTD7900ZR2 Power MOSFET
9 A, 20 V, Logic Level, N-Channel Micro-8 Leadless
EZFETsTM are an advanced series of Power MOSFETs which contain monolithic back-to-back zener diodes. These zener diodes provide protection against ESD and unexpected transients. These miniature surface mount MOSFETs feature ultra low RDS(on) and true logic level performance. EZFET devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dc-dc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones.
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9 AMPERES 20 VOLTS RDS(on) = 26 mW (VGS = 4.5 V, ID = 6.5 A) RDS(on) = 31 mW (VGS = 2.5 V, ID = 5.8 A)
D D
* Zener Protected Gates Provide Electrostatic Discharge Protection * Designed to Withstand 4000 V Human Body Model * Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery * * *
Life Logic Level Gate Drive - Can be Driven by Logic ICs Micro-8 Leadless Surface Mount Package - Saves Board Space IDSS Specified at Elevated Temperature
Steady State 20 12 9.0 6.4 IDM Is PD 3.2 1.7 TJ, Tstg RqJA 1.5 0.79 C C/W 2.9 30 1.4 6.0 4.3 A A W
2.4 kW G1 G2
2.4 kW
MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
N-Channel Unit V V A 1 Micro-8 Leadless CASE 846C A Y WW Rating Drain-to-Source Voltage Gate-to-Source Voltage Continuous Drain Current (Note 1) TA = 25C TA = 85C Pulsed Drain Current (tp v 10 ms) Continuous Source-Diode Conduction (Note 1) Total Power Dissipation (Note 1) TA = 25C TA = 85C Operating Junction and Storage Temperature Range Thermal Resistance (Note 1) Junction-to-Ambient Symbol VDSS VGS ID 10 Secs
S1 N-Channel
S2
MARKING DIAGRAM
1 7900 AYWW = Assembly Location = Year = Work Week
PIN ASSIGNMENT
Drain Drain Drain 38 82 Drain
8 7 1 2
Source 1 Gate 1 Source 2 Gate 2
-55 to 150
Drain
6 5 3 4
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. When surface mounted to 1 x 1 FR-4 board.
(Bottom View)
ORDERING INFORMATION
Device NTLTD7900ZR2 Package Shipping
Micro-8 LL 2500 Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.
(c) Semiconductor Components Industries, LLC, 2004
1
August, 2004 - Rev. 4
Publication Order Number: NTLTD7900ZR2/D
NTLTD7900ZR2
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (Note 2) (VGS = 0 Vdc, ID = 250 mAdc) Zero Gate Voltage Drain Current (VDS = 16 Vdc, VGS = 0 Vdc) (VDS = 16 Vdc, VGS = 0 Vdc, TJ = 85C) Gate-Body Leakage Current (VGS = "4.5 Vdc, VDS = 0 Vdc) (VGS = "12 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 2) Gate Threshold Voltage (Note 2) (VDS = VGS, ID = 250 mAdc) Static Drain-to-Source On-Resistance (Note 2) (VGS = 4.5 Vdc, ID = 6.5 Adc) (VGS = 2.5 Vdc, ID = 5.8 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Gate Charge (VGS = 4.5 Vdc, ID = 6.5 Adc, 4 5 Vdc 6 5 Adc VDS = 10 Vdc) S (Note 2) (VGS = 4.5 Vdc, VDD = 10 Vdc, ID = 1 0 Adc RG = 9 1 W) 1.0 Adc, 9.1 ( (Note 2) ) td(on) tr td(off) tf QT Q1 Q2 - - - - - - - 0.55 1.17 1.87 4.8 12 0.7 3.7 1.0 2.0 3.0 7.0 18 - - nC ms nC ms (VDS = 16 Vdc, VGS = 0 V, f = 1.0 MHz) Ciss Coss Crss - - - 7.4 237 4.1 15 400 10 pF pF VGS(th) 0.4 RDS(on) - - 21 27 26 31 0.67 1.0 mW Vdc V(BR)DSS 20 IDSS - - IGSS - - - - 1.0 500 - - 1.0 20 mAdc mAdc 24 - mAdc Vdc Symbol Min Typ Max Unit
Gate Charge
SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (IS = 1.0 Adc, VGS = 0 Vdc) IS = 1.0 Adc, VGS = 0 Vdc, TJ = 85C) (Note 2) VSD - - 0.69 0.62 0.8 - Vdc
2. Pulse Test: Pulse Width S 300 ms, Duty Cycle S 2%. 3. Switching characteristics are independent of operating junction temperatures.
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NTLTD7900ZR2
TYPICAL ELECTRICAL CHARACTERISTICS
8 IGSS, GATE-CURRENT (mA) 10,000 IGSS, GATE-CURRENT (mA) 1000 100 TJ = 150C 10 1 TJ = 25C 0.1 0.01 0 3 6 9 12 15 VGS, GATE-TO-SOURCE VOLTAGE (V) 18 0 3 6 9 12 VGS, GATE-TO-SOURCE VOLTAGE (V) 15
6
4
2
0
Figure 1. Gate-Current versus Gate-Source Voltage
30 2.4 V ID, DRAIN CURRENT (A) 24 2.8 V 3.5 V 4.5 V 10 V 2.2 V ID, DRAIN CURRENT (A) 24 30
Figure 2. Gate-Current versus Gate-Source Voltage
2.0 V 1.8 V 1.6 V 1.4 V VGS = 1.2 V
18
18
12
12 TC = 25C 6 TC = 125C 0 TC = -55C 1.2 1.6 2.0 2.4
6
0 0 2 4 6 8 10 VDS, DRAIN-TO-SOURCE VOLTAGE (V)
0
0.4
0.8
VGS, GATE-TO-SOURCE VOLTAGE (V)
Figure 3. On-Region Characteristics
RDS(on), DRAIN-TO-SOURCE RESISTANCE (W)
Figure 4. Transfer Characteristics
0.06 0.05 0.04 0.03 0.02 0.01 0 0 6 12 18 24 30 ID, DRAIN CURRENT (A) VGS = 2.5 V
VGS = 4.5 V
Figure 5. On-Resistance versus Drain Current
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NTLTD7900ZR2
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (Dt) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 8) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.
1200 1000 C, CAPACITANCE (pF) 800 Coss 600 400 200 Ciss and Crss are below 10 pF 0 0 5 10 15
TJ = 25C VGS = 0 V
20
GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (V)
Figure 6. Capacitance Variation
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NTLTD7900ZR2
VGS, GATE-TO-SOURCE VOLTAGE (V) 5 TJ = 25C ID = 6.5 A 4 t, TIME (ns) 10,000 tf td(off) tr td(on) VDS = 10 V ID = 6.5 A VGS = 4.5 V 1 10 RG, GATE RESISTANCE (W) 100
3
1000
2
1 0 0 2 4 6 8 10 Qg, TOTAL GATE CHARGE (nC) 12 14 100
Figure 7. Gate-to-Source
Figure 8. Resistive Switching Time Variation versus Gate Resistance
1.8
10 IS, SOURCE CURRENT (A) TJ = 25C VGS = 0 V RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)
1.6 1.4 1.2 1.0
ID = 9 A VGS = 4.5 V
1 TJ = 150C
TJ = 25C 0.1 0 0.2 0.4 0.6 0.8 1 VSD, SOURCE-TO-DRAIN VOLTAGE (V)
-0.8 0.6 -50
-25
0
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (C)
Figure 9. Diode Forward Voltage versus Current
Figure 10. On-Resistance Variation with Temperature
VGS(th), THRESHOLD VARIANCE (V)
0.2 ID = 250 mA 0.1 0 -0.1 -0.2 -0.3 -0.4 -50
RDS(on), DRAIN-TO-SOURCE RESISTANCE (W)
0.040 0.035 0.030 0.025 0.020 0.015 0.010 0.005 0 0 5 10 15 20 25 30 TJ = -55C TJ = 25C TJ = 125C
-25
0
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (C)
ID, DRAIN CURRENT (A)
Figure 11. Threshold Voltage
Figure 12. On-Resistance versus Drain Current and Temperature
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NTLTD7900ZR2
r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED) 1 D = 0.5
0.2 0.1 0.05 0.02 SINGLE PULSE 0.01 10-4 10-3 10-2 10-1 t, TIME (seconds) 1 10 100 1000 P(pk) t2 DUTY CYCLE, D = t1/t2 t1 RqJC(t) = r(t) RqJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RqJC(t)
0.1
Figure 13. Thermal Response
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NTLTD7900ZR2
PACKAGE DIMENSIONS
Micro-8 Leadless CASE 846C-01 ISSUE O
NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETER. 3. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. 4. DIMENSION D APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 MM AND 0.30 MM FROM TERMINAL TIP. DIMENSION L1 IS THE TERMINAL PULL BACK FROM PACKAGE EDGE, UP TO 0.1 MM IS ACCEPTABLE. L1 IS OPTIONAL. 5. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. DIM A B C D E F G H J K L M N P R S U MILLIMETERS MIN MAX 3.20 3.40 3.20 3.40 0.85 0.95 0.28 0.33 1.30 1.50 2.55 2.75 0.65 BSC 0.95 1.15 0.25 BSC 0.00 0.05 0.35 0.45 1.60 1.70 1.60 1.70 1.28 1.38 0.200 0.250 0.18 0.23 0.20 ---
A
PIN 1 I.D. INDEX AREA
M
W Y
-T- J
SEATING PLANE
AA N B
2 PL
0.15 T
2 PL
0.15 T
0.10
M
TWY D
8 PL C4 8 7
G 6 PL
6 5 3 4 C2
DETAIL Z
C3
U 4 PL H
EEE EEE EEE EEE
TOP VIEW E
1 2
8 PL
0.10 T
8 PL
K AA C
L
C1
0.08 T
8 PL
SIDE VIEW
L1 F P
NOTE 5
TERMINAL TIP
S R VIEW AA-AA
DETAIL Z
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NTLTD7900ZR2
EZFET is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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NTLTD7900ZR2/D

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