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| FDS8978 N-Channel PowerTrench(R) MOSFET July 2005 FDS8978 Dual N-Channel PowerTrench(R) MOSFET 30V, 7.5A, 18m Features rDS(ON) = 18m, VGS = 10V, ID = 7.5A rDS(ON) = 21m, VGS = 4.5V, ID = 6.9A High performance trench technology for extremely low rDS(ON) Low gate charge High power and current handling capability 100% Rg Tested RoHS Compliant General Description This N-Channel MOSFET has been designed specifically to improve the overall efficiency of DC/DC converters using either synchronous or conventional switching PWM controllers. It has been optimized for low gate charge, low rDS(ON) and fast switching speed. 5 6 7 8 Q1 Q2 4 3 2 1 MOSFET Maximum Ratings TA = 25C unless otherwise noted Symbol VDSS VGS ID EAS PD TJ, TSTG Parameter Drain to Source Voltage Gate to Source Voltage Drain Current Continuous (TA = 25oC, VGS = 10V, RJA = 78oC/W) Continuous (TA = 25 C, VGS = 4.5V, RJA = 78 C/W) Pulsed Single Pulse Avalanche Energy (Note 1) Power dissipation Derate above 25oC Operating and Storage Temperature o o Ratings 30 20 7.5 6.9 Figure 4 57 1.6 13 -55 to 150 Units V V A A A mJ W mW/oC o C Thermal Characteristics RJC RJA RJA Thermal Resistance, Junction to Ambient (Note 2) Thermal Resistance, Junction to Ambient (Note 3) Thermal Resistance, Junction to Ambient (Note 4) 78 170 183 o C/W C/W oC/W o Package Marking and Ordering Information Device Marking FDS8978 Device FDS8978 Package SO-8 Reel Size 330mm Tape Width 12mm Quantity 2500 units (c)2005 Fairchild Semiconductor Corporation FDS8978 Rev. A 1 www.fairchildsemi.com FDS8978 N-Channel PowerTrench(R) MOSFET Electrical Characteristics TA = 25C unless otherwise noted Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BVDSS IDSS IGSS Drain to Source Breakdown Voltage Zero Gate Voltage Drain Current Gate to Source Leakage Current ID = 250A, VGS = 0V VDS = 24V VGS = 0V VGS = 20V TA = 150oC 30 1 250 100 V A nA On Characteristics VGS(TH) rDS(ON) Gate to Source Threshold Voltage Drain to Source On Resistance VGS = VDS, ID = 250A ID = 7.5A, VGS = 10V ID = 6.9A, VGS = 4.5V ID = 7.5A, VGS = 10V, TA = 150oC 1.2 0.014 0.017 0.022 2.5 0.018 0.021 0.029 V Dynamic Characteristics CISS COSS CRSS RG Qg Qgs Qgs2 Qgd Input Capacitance Output Capacitance Reverse Transfer Capacitance Gate Resistance Total Gate Charge Gate to Source Gate Charge Gate Charge Threshold to Plateau Gate to Drain "Miller" Charge VDS = 15V, VGS = 0V, f = 1MHz f = 1MHz VGS =10V VGS = 5V VDD = 15V ID = 7.5A 907 191 112 1.2 17 9 2.3 1.5 3.3 4.0 26 14 pF pF pF nC nC nC nC nC Switching Characteristics (VGS = 10V) tON td(ON) tr td(OFF) tf tOFF Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time VDD = 15V, ID = 7.5A VGS = 10V, RGS = 16 44 7 37 48 24 72 66 10.5 55.5 72 36 108 ns ns ns ns ns ns Drain-Source Diode Characteristics VSD trr QRR Source to Drain Diode Voltage Reverse Recovery Time Reverse Recovered Charge ISD = 7.5A ISD = 2.1A ISD = 7.5A, dISD/dt=100A/s ISD = 7.5A, dISD/dt=100A/s 19 10 1.25 1.0 25 13 V V ns nC Notes: 1: Starting TJ = 25C, L = 1mH, IAS = 7.5A, VDD = 30V, VGS = 10V. 2: RJA is 78oC/W when mounted on a 0.5 in2 copper pad on FR-4 at 100 seconds. 3: RJA is 191oC/W when mounted on a 0.027 in2 copper pad on FR-4 at 1000 seconds. 4: RJA is 228oC/W when mounted on a 0.006 in2 copper pad on FR-4 at 1000 seconds. 2 FDS8978 Rev. A www.fairchildsemi.com FDS8978 N-Channel PowerTrench(R) MOSFET Typical Characteristics TA = 25C unless otherwise noted 1.2 1.0 8 7 ID, DRAIN CURRENT (A) 6 5 4 3 2 RJA = 78C/W POWER DISSIPATION MULTIPLIER 0.8 0.6 0.4 0.2 0 0 25 50 75 100 125 150 TA , AMBIENT TEMPERATURE (oC) VGS = 4.5V VGS = 10V 1 0 25 50 75 100 125 TA, AMBIENT TEMPERATURE (oC) 150 Figure 1. Normalized Power Dissipation vs Ambient Temperature 2 1 DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 Figure 2. Maximum Continuous Drain Current vs Ambient Temperature RJA=78oC/W ZJA, NORMALIZED THERMAL IMPEDANCE 0.1 PDM t1 SINGLE PULSE t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJA x RJA + TA 10-2 10-1 100 t, RECTANGULAR PULSE DURATION (s) 101 102 103 0.01 0.001 10-5 10-4 10-3 Figure 3. Normalized Maximum Transient Thermal Impedance 1000 TA = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: I = I25 100 VGS = 4.5V 150 - TA 125 TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION VGS = 10V IDM, PEAK CURRENT (A) 10 5 10-5 10-4 10-3 10-2 10-1 t, PULSE WIDTH (s) 100 101 102 103 Figure 4. Peak Current Capability 3 FDS8978 Rev. A www.fairchildsemi.com FDS8978 N-Channel PowerTrench(R) MOSFET Typical Characteristics TA = 25C unless otherwise noted 100 IAS, AVALANCHE CURRENT (A) If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] 18 VDS = 6V 15 ID, DRAIN CURRENT (A) 12 9 6 3 0 1.7 2.0 2.3 2.6 2.9 VGS, GATE TO SOURCE VOLTAGE (V) 3.2 TA = 150oC 10 STARTING TJ = 25oC 25oC -25oC STARTING TJ = 150oC 1 0.01 0.1 1 10 100 tAV, TIME IN AVALANCHE (ms) NOTE: Refer to Fairchild Application Notes AN7514 and AN7515 Figure 5. Unclamped Inductive Switching Capability Figure 6. Transfer Characteristics 15 VGS = 10V 5.0V 50 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX rDS(ON), DRAIN TO SOURCE ON RESISTANCE (m) 40 ID = 7.5A 30 ID, DRAIN CURRENT (A) 12 3.5V 9 3.0V 6 20 ID = 1A 10 3 0 0.0 0.1 0.2 0.3 0.4 0.5 VDS, DRAIN-SOURCE VOLTAGE (V) 0.6 0.7 0 2 4 6 8 10 VGS, GATE TO SOURCE VOLTAGE (V) Figure 7. Saturation Characteristics Figure 8. Drain to Source On Resistance vs Drain Current 1.2 1.6 NORMALIZED DRAIN TO SOURCE ON RESISTANCE PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX NORMALIZED GATE THRESHOLD VOLTAGE VGS = VDS, ID = 250A 1.4 1.0 1.2 0.8 1.0 VGS = 10V, ID = 7.5A 0.8 -80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC) 0.6 -80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC) Figure 9. Normalized Drain to Source On Resistance vs Junction Temperature 4 FDS8978 Rev. A Figure 10. Normalized Gate Threshold Voltage vs Junction Temperature www.fairchildsemi.com FDS8978 N-Channel PowerTrench(R) MOSFET Typical Characteristics TA = 25C unless otherwise noted 1.10 ID = 250A NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE 1000 C, CAPACITANCE (pF) 1.05 2000 CISS = CGS + CGD 1.00 CRSS = CGD COSS CDS + CGD 0.95 VGS = 0V, f = 1MHz 0.90 -80 -40 0 40 80 120 160 TJ , JUNCTION TEMPERATURE (oC) 10 0.1 1 10 VDS , DRAIN TO SOURCE VOLTAGE (V) 30 Figure 11. Normalized Drain to Source Breakdown Voltage vs Junction Temperature 10 VGS , GATE TO SOURCE VOLTAGE (V) Figure 12. Capacitance vs Drain to Source Voltage VDD = 15V 8 6 4 2 WAVEFORMS IN DESCENDING ORDER: ID = 7.5A ID = 1A 0 3 6 9 12 15 18 0 Qg, GATE CHARGE (nC) Figure 13. Gate Charge Waveforms for Constant Gate Currents 5 FDS8978 Rev. A www.fairchildsemi.com FDS8978 N-Channel PowerTrench(R) MOSFET Test Circuits and Waveforms VDS tP L IAS VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP RG + BVDSS VDS VDD VDD - 0V IAS 0.01 0 tAV Figure 14. Unclamped Energy Test Circuit Figure 15. Unclamped Energy Waveforms VDS RL VDD Qg(TOT) VDS Qg(5) VGS VGS = 10V VGS + DUT Ig(REF) VDD Qgs2 VGS = 5V VGS = 1V 0 Qg(TH) Qgs Ig(REF) 0 Qgd Figure 16. Gate Charge Test Circuit Figure 17. Gate Charge Waveforms VDS tON td(ON) RL VDS 90% tr tOFF td(OFF) tf 90% VGS + VDD DUT 0 10% 90% 10% RGS VGS VGS 0 10% 50% PULSE WIDTH 50% Figure 18. Switching Time Test Circuit Figure 19. Switching Time Waveforms 6 FDS8978 Rev. A www.fairchildsemi.com FDS8978 N-Channel PowerTrench(R) MOSFET Thermal Resistance vs. Mounting Pad Area The maximum rated junction temperature, TJM, and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PDM, in an application. Therefore the application's ambient temperature, TA (oC), and thermal resistance RJA (oC/W) must be reviewed to ensure that TJM is never exceeded. Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part. ( T JM - T A ) P DM = -----------------------------RJA maximum transient thermal impedance curve. Thermal resistances corresponding to other copper areas can be obtained from Figure 21 or by calculation using Equation 2. The area, in square inches is the top copper area including the gate and source pads. R JA = 64 + ------------------------------- 26 0.23 + Area (EQ. 2) (EQ. 1) In using surface mount devices such as the SO8 package, the environment in which it is applied will have a significant influence on the part's current and maximum power dissipation ratings. Precise determination of PDM is complex and influenced by many factors: 1. Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board. 2. The number of copper layers and the thickness of the board. 3. The use of external heat sinks. 4. The use of thermal vias. 5. Air flow and board orientation. 6. For non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in. Fairchild provides thermal information to assist the designer's preliminary application evaluation. Figure 21 defines the RJA for the device as a function of the top copper (component side) area. This is for a horizontally positioned FR-4 board with 1oz copper after 1000 seconds of steady state power with no air flow. This graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. Pulse applications can be evaluated using the Fairchild device Spice thermal model or manually utilizing the normalized 150 120 90 60 30 0 10-1 100 COPPER BOARD AREA - DESCENDING ORDER 0.04 in2 0.28 in2 0.52 in2 0.76 in2 1.00 in2 The transient thermal impedance (ZJA) is also effected by varied top copper board area. Figure 22 shows the effect of copper pad area on single pulse transient thermal impedance. Each trace represents a copper pad area in square inches corresponding to the descending list in the graph. Spice and SABER thermal models are provided for each of the listed pad areas. Copper pad area has no perceivable effect on transient thermal impedance for pulse widths less than 100ms. For pulse widths less than 100ms the transient thermal impedance is determined by the die and package. Therefore, CTHERM1 through CTHERM5 and RTHERM1 through RTHERM5 remain constant for each of the thermal models. A listing of the model component values is available in Table 1. 200 RJA = 64 + 26/(0.23+Area) RJA (oC/W) 150 100 50 0.001 0.01 0.1 1 AREA, TOP COPPER AREA (in2) 10 Figure 21. Thermal Resistance vs Mounting Pad Area ZJA, THERMAL IMPEDANCE (oC/W) 101 t, RECTANGULAR PULSE DURATION (s) 102 103 Figure 22. Thermal Impedance vs Mounting Pad Area 7 FDS8978 Rev. A www.fairchildsemi.com FDS8978 N-Channel PowerTrench(R) MOSFET PSPICE Electrical Model .SUBCKT FDS8878 2 1 3 *February 2005 Ca 12 8 7.8e-10 Cb 15 14 7.8e-10 Cin 6 8 .78e-9 Dbody 7 5 DbodyMOD Dbreak 5 11 DbreakMOD Dplcap 10 5 DplcapMOD Ebreak 11 7 17 18 32.9 Eds 14 8 5 8 1 Egs 13 8 6 8 1 Esg 6 10 6 8 1 Evthres 6 21 19 8 1 Evtemp 20 6 18 22 1 It 8 17 1 Lgate 1 9 5.29e-9 Ldrain 2 5 1.0e-9 Lsource 3 7 0.18e-9 RLgate 1 9 52.9 RLdrain 2 5 10 RLsource 3 7 1.8 Mmed 16 6 8 8 MmedMOD Mstro 16 6 8 8 MstroMOD Mweak 16 21 8 8 MweakMOD Rbreak 17 18 RbreakMOD 1 Rdrain 50 16 RdrainMOD 1.6e-3 Rgate 9 20 2.3 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 Rsource 8 7 RsourceMOD 8.9e-3 Rvthres 22 8 RvthresMOD 1 Rvtemp 18 19 RvtempMOD 1 S1a 6 12 13 8 S1AMOD S1b 13 12 13 8 S1BMOD S2a 6 15 14 13 S2AMOD S2b 13 15 14 13 S2BMOD Vbat 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*170),5))} .MODEL DbodyMOD D (IS=2.0E-12 IKF=10 N=1.01 RS=7.0e-3 TRS1=8e-4 TRS2=2e-7 + CJO=3.5e-10 M=0.55 TT=7e-11 XTI=2) .MODEL DbreakMOD D (RS=0.2 TRS1=1e-3 TRS2=-8.9e-6) .MODEL DplcapMOD D (CJO=3.8e-10 IS=1e-30 N=10 M=0.45) .MODEL MstroMOD NMOS (VTO=2.36 KP=150 IS=1e-30 N=10 TOX=1 L=1u W=1u) .MODEL MmedMOD NMOS (VTO=1.95 KP=5.0 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=2.3) .MODEL MweakMOD NMOS (VTO=1.57 KP=0.02 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=23 RS=0.1) .MODEL RbreakMOD RES (TC1=8.3e-4 TC2=-8e-7) .MODEL RdrainMOD RES (TC1=15e-3 TC2=0.1e-5) .MODEL RSLCMOD RES (TC1=1e-4 TC2=1e-6) .MODEL RsourceMOD RES (TC1=1e-3 TC2=3e-6) .MODEL RvtempMOD RES (TC1=-1.8e-3 TC2=2e-7) .MODEL RvthresMOD RES (TC1=-2.0e-3 TC2=-6e-6) MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4 VOFF=-3.5) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3.5 VOFF=-4) .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1.5 VOFF=-1.0) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1.0 VOFF=-1.5).ENDSNote: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. LGATE GATE 1 RLGATE CIN LDRAIN 5 RLDRAIN DBREAK 11 + 17 EBREAK 18 MWEAK MMED MSTRO LSOURCE 8 RSOURCE 12 S1A 13 8 S1B CA 13 + EGS 6 8 EDS S2A 14 13 S2B CB + 5 8 8 RVTHRES 14 IT VBAT + 22 15 17 RBREAK 18 RVTEMP 19 7 RLSOURCE SOURCE 3 DRAIN 2 RSLC1 51 ESLC 50 DPLCAP 10 5 51 ESG + EVTEMP RGATE + 18 22 9 20 6 8 EVTHRES + 19 8 6 8 FDS8978 Rev. A + - RSLC2 RDRAIN 21 16 DBODY www.fairchildsemi.com FDS8978 N-Channel PowerTrench(R) MOSFET TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACExTM ActiveArrayTM BottomlessTM Build it NowTM CoolFETTM CROSSVOLTTM DOMETM EcoSPARKTM E2CMOSTM EnSignaTM FACTTM FACT Quiet SeriesTM FAST(R) FASTrTM FPSTM FRFETTM GlobalOptoisolatorTM GTOTM HiSeCTM I2CTM Across the board. Around the world.TM The Power Franchise(R) Programmable Active DroopTM i-LoTM ImpliedDisconnectTM IntelliMAXTM ISOPLANARTM LittleFETTM MICROCOUPLERTM MicroFETTM MicroPakTM MICROWIRETM MSXTM MSXProTM OCXTM OCXProTM OPTOLOGIC(R) OPTOPLANARTM PACMANTM POPTM Power247TM PowerEdgeTM PowerSaverTM PowerTrench(R) QFET(R) QSTM QT OptoelectronicsTM Quiet SeriesTM RapidConfigureTM RapidConnectTM SerDesTM SILENT SWITCHER(R) SMART STARTTM SPMTM StealthTM SuperFETTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 SyncFETTM TinyLogic(R) TINYOPTOTM TruTranslationTM UHCTM UltraFET(R) UniFETTM VCXTM WireTM DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design First Production Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. I16 Preliminary No Identification Needed Full Production Obsolete Not In Production 10 FDS8978 Rev. A www.fairchildsemi.com |
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