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B
PRELIMINARY
CY82C693UB
hyperCacheTM / Stand-Alone PCI Peripheral Controller with USB
Features
* PCI to ISA bridge * PCI Bus Rev. 2.1 compliant * Supports up to 5 additional PCI masters including the CY82C691 * Integrated DMA controllers with Type A, B, and F support * Integrated Interrupt controllers * Integrated timer/counters * Integrated Real-Time-Clock with 256 bytes of battery-backed SRAM (14 bytes of clock RAM and 242 bytes of CMOS scratch RAM) * Write-only Register Shadowing * Integrated Dual-Channel enhanced IDE controller with -- PCI bus mastering * * * * * * * * * -- CD ROM support -- PIO modes 0 through 4 operation -- Single-word and Multi-word DMA modes 0 through 2 Integrated Keyboard Controller APM compliant power management support through SMM or under hardware control Flash PROM support with write-protection Power-on reset circuitry QuietBusTM support for the PCI and ISA bus interfaces for better noise immunity General-purpose I/O pins and registers USB Host/Hub controller with 2 USB ports Flexible Stand-Alone configuration options Packaged in a 208-pin PQFP
System Block Diagram
Intel Pentium TM Processor, Cyrix M1 or AMD K5, K6 CY82C691 TAG Cypress Clock CY2254ASC-2
DRAMAddress, DRAMControl
CY82C694 Expansion Cache
Control
CY82C692 CACHE
PCI LOCAL BUS
DRAM Data[0:31]
DRAM Data[32:63]
EPROM CY27C010 or Flash BIOS
DRAM Lower 4 Bytes CY82C693UB
DRAM Upper 4 bytes
Standard or EDO DRAMs
USB Bus
ISA Bus
IDE devices
hyperCache and QuietBus are trademarks of Cypress Semiconductor Corporation. Pentium is a trademark of Intel Corporation.
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose * CA 95134 * 408-943-2600 March 25, 1997 - Revised December 10, 1997
PRELIMINARY
TABLE OF CONTENTS
CY82C693UB
Features ................................................................................................................................................... 1 CY82C693UB Signals ........................................................................................................................... 11 Pin Configuration ................................................................................................................................... 12 CY82C693UB Pin Reference (In Numerical Order by Pin Number) ...................................................... 13 CY82C693UB Pin Reference (In Alphabetical Order by Signal Name) ................................................. 14 Introduction ............................................................................................................................................ 17
System Overview ............................................................................................................................................. 17 CY82C693UB Introduction .............................................................................................................................. 17
Functional Overview .............................................................................................................................. 17
PCI Bus Interface ............................................................................................................................................ 17 ISA Bus Interface ............................................................................................................................................. 18 Reset Logic ...................................................................................................................................................... 18 Keyboard Controller ......................................................................................................................................... 19
Operating Frequency ....................................................................................................................................................19 Resetting the Keyboard Controller ...............................................................................................................................19 Host Interface ...............................................................................................................................................................19 PS/2 Compatible Mouse Support .................................................................................................................................19 Keyboard Interface .......................................................................................................................................................19 Maximum Flexibility ......................................................................................................................................................19 Keyboard Self-Test .......................................................................................................................................................19
Power Management Logic ............................................................................................................................... 19 AT Refresh Logic ............................................................................................................................................. 20 Pre-Read/Post-Write Buffers ........................................................................................................................... 20 BIOS ROM Control .......................................................................................................................................... 20 Timer/Counter Logic ........................................................................................................................................ 20 DMA Controllers .............................................................................................................................................. 21
DMA Controller Transfer Modes ...................................................................................................................................21
IDE Controller .................................................................................................................................................. 21 Real-Time-Clock .............................................................................................................................................. 21
RTC Address Map ........................................................................................................................................................22 External RTC Control ...................................................................................................................................................22
Interrupt Controllers ......................................................................................................................................... 22
NMI Sources .................................................................................................................................................................23
Stand-Alone Operation .................................................................................................................................... 23
Use With An External PCI Arbiter .................................................................................................................................23 Splitting GNTBSY .........................................................................................................................................................23 External Reset Control .................................................................................................................................................24 FREQACK Bypassing ..................................................................................................................................................24 32-Bit I/O Space Decode ..............................................................................................................................................24 1 Mbyte ROM Decode ..................................................................................................................................................24
Universal Serial Bus (USB) Host Controller .................................................................................................... 24
CY82C693UB Signal Description .......................................................................................................... 25
Reset Signals .................................................................................................................................................. 25 PCI Interface Signals ....................................................................................................................................... 25 ISA Interface Signals ....................................................................................................................................... 27 Power Management Signals ............................................................................................................................ 33 Keyboard Interface Signals ............................................................................................................................. 33 IDE Interface Signals ....................................................................................................................................... 33 USB Interface Signals ..................................................................................................................................... 34 Miscellaneous Signals ..................................................................................................................................... 34
hyperCache Memory and I/O Map ......................................................................................................... 35 CY82C693UB Control Registers ........................................................................................................... 37
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PRELIMINARY
TABLE OF CONTENTS (continued)
Register 1: Register 2: Register 3: Register 4: Register 5:
CY82C693UB
Peripheral Configuration Register #1 (Read/Write) -- Index=01H ................................................ 37 Peripheral Configuration Register #2 (Read/Write) - Index=02H .................................................. 38 Interrupt Request Level/Edge Control Register #1 (Read/Write) - Index=03H ............................. 38 Interrupt Request Level/Edge Control Register #2 (Read/Write) - Index=04H ............................. 39 Real-Time-Clock Configuration Register (Read/Write) - Index=05H ............................................ 39
Write-Only Shadow Registers ................................................................................................................ 40
Register 80: DMA1 Write Request Shadow Register (Read/Write) - Index=80H ........................................... 40 Register 81: DMA1 Write Single Mask Bit Shadow Register (Read/Write) - Index=81H ................................ 40 Register 82: DMA1 Write Mode Shadow Register (Read/Write) - Index=82H ............................................... 40 Register 83: DMA1 Clear Byte Pointer Shadow Register (Read/Write) - Index=83H ..................................... 40 Register 84: DMA1 Master Clear Shadow Register (Read/Write) - Index=84H ............................................. 40 Register 85: DMA1 Clear Mask Shadow Register (Read/Write) - Index=85H ................................................ 40 Register 86: Timer Counter 1 Command Mode Shadow Register (Read/Write) - Index=86H ....................... 40 Register 87: CMOS Battery-Backed RAM Address and NMI Mask Registers Shadow Register (Read/Write) - Index=87H ............................................................................................................................... 40 Register 88: DMA2 Write Request Shadow Register (Read/Write) - Index=88H ........................................... 40 Register 89: DMA2 Write Single Mask Bit Shadow Register (Read/Write) - Index=89H ................................ 41 Register 8A: DMA2 Write Mode Shadow Register (Read/Write) - Index=8AH ............................................... 41 Register 8B: DMA2 Clear Byte Pointer Shadow Register (Read/Write) - Index=8BH .................................... 41 Register 8C: DMA2 Mask Clear Shadow Register (Read/Write) - Index=8CH .............................................. 41 Register 8D: DMA2 Clear Mask Shadow Register (Read/Write) - Index=8DH .............................................. 41 Register 8E: Coprocessor Error Shadow Register (Read/Write) - Index=8EH ............................................... 41 Register 8F: Extended CMOS RAM address Shadow Register (Read/Write) - Index=8FH ........................... 41
General Purpose I/O Registers .............................................................................................................. 42
Register 90: General Purpose I/O Control Register A (Read/Write) - Index=90H Register 91: General Purpose I/O Input/Output Control Register A (Read/Write) Register 92: General Purpose I/O Control Register B (Read/Write) - Index=92H Register 93: General Purpose I/O Input/Output Control Register B (Read/Write) .......................................... 42 - Index=91H ..................... 42 .......................................... 43 - Index=93H ..................... 43
Power Management Control Registers .................................................................................................. 44
Register 40: Standby Timer Event Detection Control (Read/Write) - Index=40H ........................................... 44 Register 41: Standby Timer Interrupt Request Detection Control #1 (Read/Write) - Index=41H ................... 45 Register 42: Standby Timer Interrupt Request Detection Control #2 (Read/Write) - Index=42H ................... 45 Register 43: Standby Timer DMA Request Detection Control #1 (Read/Write) - Index=43H ......................... 46 Register 44: Suspend Timer Event Detection Control (Read/Write) - Index=44H .......................................... 46 Register 45: Suspend Timer Interrupt Request Detection Control #1 (Read/Write) - Index=45H .................. 47 Register 46: Suspend Timer Interrupt Request Detection Control #2 (Read/Write) - Index=46H .................. 47 Register 47: Suspend Timer DMA Request Detection Control #1 (Read/Write) - Index=47H ........................ 48 Register 48: User Timer 1 Event Detection Control (Read/Write) - Index=48H ............................................. 48 Register 49: User Timer 1 Interrupt Request Detection Control #1 (Read/Write) - Index=49H ...................... 49 Register 4A: User Timer 1 Interrupt Request Detection Control #2 (Read/Write) - Index=4AH ..................... 49 Register 4B: User Timer 1 DMA Request Detection Control #1 (Read/Write) - Index=4BH .......................... 50 Register 4C: Throttle Timer Event Detection Control (Read/Write) - Index=4CH ........................................... 50 Register 4D: Throttle Timer Interrupt Request Detection Control #1 (Read/Write) - Index=4DH ................... 51 Register 4E: Throttle Timer Interrupt Request Detection Control #2 (Read/Write) - Index=4EH ................... 51 Register 4F: Throttle Timer DMA Request Detection Control #1 (Read/Write) - Index=4FH ......................... 52 Register 50: Non-motherboard Memory Address Range Decode for Event Detection Register #1 (Read/Write) - Index=50H ........................................................................................................... 52 Register 51: Non-motherboard Memory Address Range Decode for Event Detection Register #2 (Read/Write) - Index=51H ........................................................................................................... 52 Register 52: Non-motherboard Memory Address Mask for Event Detection Register #1 (Read/Write) - Index=52H ............................................................................................................................... 52
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TABLE OF CONTENTS (continued)
CY82C693UB
Register 53: Non-motherboard Memory Address Mask for Event Detection Register #2 (Read/Write) - Index=53H ............................................................................................................................... 52 Register 54: Programmable I/O Trap 1 Address Range Register #1 (Read/Write) - Index=54H ................... 52 Register 55: Programmable I/O Trap 1 Address Range Register #2 (Read/Write) - Index=55H ................... 53 Register 56: Programmable I/O Trap 1 Address Range Register #3 (Read/Write) - Index=56H ................... 53 Register 57: Programmable I/O Trap 1 Address Range Register #4 (Read/Write) - Index=57H ................... 53 Register 58: Programmable I/O Trap 2 Address Range Register #1 (Read/Write) - Index=58H ................... 53 Register 59: Programmable I/O Trap 2 Address Range Register #2 (Read/Write) - Index=59H ................... 53 Register 5A: Programmable I/O Trap 2 Address Range Register #3 (Read/Write) - Index=5AH .................. 53 Register 5B: Programmable I/O Trap 2 Address Range Register #4 (Read/Write) - Index=5BH .................. 53 Register 5C: Programmable I/O Trap 1 Address Detection Control (Read/Write) - Index=5CH .................... 54 Register 5D: Programmable I/O Trap 2 Address Detection Control (Read/Write) - Index=5DH .................... 54 Register 5E: I/O Trap 1 and 2 Monitoring Control (Read/Write) - Index=5EH ................................................ 55 Register 5F: Standby and Suspend Timer Terminal Count Control Register (Read/Write) - Index=5FH ....... 55 Register 60: User Timer 1 and User Timer 2 Terminal Count Control Register (Read/Write) - Index=60H ... 56 Register 61: User Timer 3 Terminal Count Control Register (Read/Write) - Index=61H ................................ 56 Register 62: Throttle Timer Terminal Count Control Register (Read/Write) - Index=62H .............................. 57 Register 63: Power Management Control Register#1 (Read/Write) - Index=63H .......................................... 57 Register 64: Power Management Control Register#2 (Read/Write) - Index=64H .......................................... 58 Register 65: Power Management Clock Control Register (Read/Write) - Index=65H .................................... 58 Register 66: STOPCLK Control Register (Read/Write) - Index=66H ............................................................. 59 Register 67: Power Management SMI Control Register (Read/Write) - Index=67H ....................................... 59 Register 70: Power Management SMI Enable Register #1 (Read/Write) - Index=70H .................................. 60 Register 71: Power Management SMI Enable Register #2 (Read/Write) - Index=71H .................................. 60 Register 72: Power Management SMI Enable Register #3 (Read/Write) - Index=72H .................................. 61 Register 73: Power Management SMI Enable Register #4 (Read/Write) - Index=73H .................................. 61 Register 74: Power Management SMI Enable Register #5 (Read/Write) - Index=74H .................................. 62 Register 75: Power Management SMI Enable Register #6 (Read/Write) - Index=75H .................................. 62 Register 76: Power Management SMI Status Register #1 (Read/Write) - Index=76H ................................... 63 Register 77: Power Management SMI Status Register #2 (Read/Write) - Index=77H ................................... 64 Register 78: Power Management SMI Status Register #3 (Read/Write) - Index=78H ................................... 65 Register 79: Power Management Interrupt Request Status Register #1 (Read/Write) - Index=79H .............. 66 Register 7A: Power Management Interrupt Request Status Register #2 (Read/Write) - Index=7AH ............. 67 Register 7B: Power Management DMA Request Status Register (Read/Write) - Index=7BH ....................... 68 Register 7C: Reserved - Index=7CH ............................................................................................................... 69 Register 7D: Reserved - Index=7DH .............................................................................................................. 69 Register 7E: Reserved - Index=7EH .............................................................................................................. 69 Register 7F: Reserved - Index=7FH ............................................................................................................... 69
Special I/O Port Registers ..................................................................................................................... 70
Port 61: System Control Port B, NMI (Read/Write) - I/O Address=061H ......................................................... 70 Port 70: RTC/Configuration RAM Address Port, NMI (Write) - I/O Address=070H ......................................... 70 Port 92: PS/2 Reset Control (Read/Write) - I/O Address=092H ...................................................................... 70 Port B2: APM Control Port (Read/Write) - I/O Address=0B2H ........................................................................ 71 Port B3: APM Status Port (Read/Write) - I/O Address=0B3H ......................................................................... 71
CY82C693UB DMA Controller Registers .............................................................................................. 72
DMA DMA DMA DMA DMA DMA DMA Register 0: DMAC1 Channel 0 Current Address Register (Read/Write) - I/O Address=000H ............... 72 Register 1: DMAC1 Channel 0 Current Word Count Register (Read/Write) - I/O Address=001H ......... 72 Register 2: DMAC1 Channel 1 Current Address Register (Read/Write) - I/O Address=002H ............... 72 Register 3: DMAC1 Channel 1 Current Word Count Register (Read/Write) - I/O Address=003H ......... 73 Register 4: DMAC1 Channel 2 Current Address Register (Read/Write) - I/O Address=004H ............... 73 Register 5: DMAC1 Channel 2 Current Word Count Register (Read/Write) - I/O Address=005H ......... 73 Register 6: DMAC1 Channel 3 Current Address Register (Read/Write) - I/O Address=006H ............... 73
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TABLE OF CONTENTS (continued)
CY82C693UB
DMA Register 7: DMAC1 Channel 3 Current Word Count Register (Read/Write) - I/O Address=007H ......... 73 DMA Register 8: DMAC1 Status/Command Register (Read/Write) - I/O Address=008H ............................... 73 Status Register Format (Read Only) ............................................................................................................... 74 Command Register Format (Write Only) ......................................................................................................... 75 DMA Register 9: DMAC1 DMA Request Register (Write Only) - I/O Address=009H ...................................... 75 DMA Request Register Write Format .............................................................................................................. 75 DMA Register 10: DMAC1 DMA Command/Mask Register (Write Only) - I/O Address=00AH ....................... 76 DMA Request Mask Register Write Single Bit Format .................................................................................... 76 DMA Register 11: DMAC1 DMA Mode Register (Write Only) - I/O Address=00BH ........................................ 76 Mode Register Format ..................................................................................................................................... 77 DMA Register 12: DMAC1 Address Space Expansion Flip-Flop Control Register (Write Only) I/O Address=00CH .......................................................................................................................................... 77 DMA Register 13: DMAC1 Master Clear Register (Write Only) - I/O Address=00DH ..................................... 77 DMA Register 14: DMAC1 DMA Mask Clear Register (Write Only) - I/O Address=00EH ............................... 77 DMA Register 15: DMAC1 Request Mask Register Control (Read/Write) - I/O Address=00FH ..................... 78 DMA Request Mask Register Read and Write All Bits Format ........................................................................ 78 DMA Register 16: DMAC2 Channel 0 (Channel 4) Current Address Register (Read/Write) I/O Address=0C0H .......................................................................................................................................... 78 DMA Register 17: DMAC2 Channel 0 (Channel 4) Current Word Count Register (Read/Write) I/O Address=0C2H .......................................................................................................................................... 78 DMA Register 18: DMAC2 Channel 1 (Channel 5) Current Address Register (Read/Write) I/O Address=0C4H .......................................................................................................................................... 78 DMA Register 19: DMAC2 Channel 1 (Channel 5) Current Word Count Register (Read/Write) I/O Address=0C6H .......................................................................................................................................... 79 DMA Register 20: DMAC2 Channel 2 (Channel 6) Current Address Register (Read/Write) I/O Address=0C8H .......................................................................................................................................... 79 DMA Register 21: DMAC2 Channel 2 (Channel 6) Current Word Count Register (Read/Write) I/O Address=0CAH .......................................................................................................................................... 79 DMA Register 22: DMAC2 Channel 3 (Channel 7) Current Address Register (Read/Write) I/O Address=0CCH .......................................................................................................................................... 79 DMA Register 23: DMAC2 Channel 3 (Channel 7) Current Word Count Register (Read/Write) I/O Address=0CEH .......................................................................................................................................... 79 DMA Register 24: DMAC2 Status/Command Register (Read/Write) - I/O Address=0D0H ............................. 79 Status Register Format (Read Only) ............................................................................................................... 80 Command Register Format (Write Only) ......................................................................................................... 81 DMA Register 25: DMAC2 DMA Request Register (Write Only) - I/O Address=0D2H ................................... 81 DMA Request Register Write Format .............................................................................................................. 81 DMA Register 26: DMAC2 DMA Command/Mask Register (Write Only) - I/O Address=0D4H ...................... 82 DMA Request Mask Register Write Single Bit Format .................................................................................... 82 DMA Register 27: DMAC2 DMA Mode Register (Write Only) - I/O Address=0D6H ........................................ 82 Mode Register Format ..................................................................................................................................... 83 DMA Register 28: DMAC2 Address Space Expansion Flip-Flop Control Register (Write Only) I/O Address=0D8H .......................................................................................................................................... 83 DMA Register 29: DMAC2 Master Clear Register (Write Only) - I/O Address=0DAH ..................................... 83 DMA Register 30: DMAC2 DMA Mask Clear Register (Write Only) - I/O Address=0DCH .............................. 83 DMA Register 31: DMAC2 Request Mask Register Control (Read/Write) - I/O Address=0DEH .................... 84 DMA Request Mask Register Read and Write All Bits Format ........................................................................ 84 DMA Register 32: DMAC1 Channel 2 Page Address Register (Read/Write) - Index=081H ........................ 84 DMA Register 33: DMAC1 Channel 3 Page Address Register (Read/Write) - Index=082H ........................ 84 DMA Register 34: DMAC1 Channel 1 Page Address Register (Read/Write) - Index=083H ........................ 84 DMA Register 35: DMAC1 Channel 0 Page Address Register (Read/Write) - Index=087H ........................ 84 DMA Register 36: DMAC2 Channel 6 Page Address Register (Read/Write) - Index=089H ........................ 84
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TABLE OF CONTENTS (continued)
CY82C693UB
DMA Register 37: DMAC2 Channel 7 Page Address Register (Read/Write) - Index=08AH ........................ 84 DMA Register 38: DMAC2 Channel 5 Page Address Register (Read/Write) - Index=08BH ........................ 85 DMA Register 39: DMAC1 Extended Mode Control (Write Only) - I/O Address=40BH .................................. 85 DMAC1 Extended Mode Control Register Format .......................................................................................... 85 DMA Register 40: DMAC1 Channel 2 High Page Address Register (Read/Write) - Index=481H ................ 85 DMA Register 41: DMAC1 Channel 3 High Page Address Register (Read/Write) - Index=482H ................ 85 DMA Register 42: DMAC1 Channel 1 High Page Address Register (Read/Write) - Index=483H ................ 85 DMA Register 43: DMAC1 Channel 0 High Page Address Register (Read/Write) - Index=487H ................ 85 DMA Register 44: DMAC2 Channel 6 High Page Address Register (Read/Write) - Index=489H ................ 86 DMA Register 45: DMAC2 Channel 7 High Page Address Register (Read/Write) - Index=48AH ............... 86 DMA Register 46: DMAC2 Channel 5 High Page Address Register (Read/Write) - Index=48BH ............... 86 DMA Register 47: DMAC2 Extended Mode Control (Write Only) - I/O Address=4D6H .................................. 86 DMAC2 Extended Mode Control Register Format .......................................................................................... 86
CY82C693UB IDE (Bus Mastering) DMA Controller Registers ............................................................. 87
SFF-8038i Registers ........................................................................................................................................ 87 Bus Master IDE Command Register Format (Offset+00H for Primary Channel; Offset +08H for Secondary Channel) .............................................................................................................. 87 Bus Master IDE Status Register Format (Offset+02H for Primary Channel; Offset +0AH for Secondary Channel) .............................................................................................................. 88 Bus Master IDE Descriptor Table Pointer Register Format (Offset+04H-07H for Primary Channel; Offset +0CH-0FH for Secondary Channel) ....................................... 88 Bus Master IDE I/O Base Address Register (PCI Configuration Space, function 1, register address 20-23H) 88 hyperCache Specific (Not Required by SFF-8038i) Registers ........................................................................ 89 Bus Master IDE Channel 0 Configuration Register (I/O Address 22H with Data = 30 (Index Port); I/O Address 23H is the Data Port) ................................................................................................................... 89 Bus Master IDE Channel 1 Configuration Register (I/O Address 22H with Data = 31 (Index Port); I/O Address 23H is the Data Port) ................................................................................................................... 89 Bus Master IDE TimeOut Register (I/O Address 22H with Data = 32 (Index Port); I/O Address 23H is the Data Port) - Write Only ............................................................................................... 89 Bus Master IDE Test Register (I/O Address 22H with Data = 33 (Index Port); I/O Address 23H is the Data Port) ................................................................................................................... 89
CY82C693UB Interrupt Controller Registers ......................................................................................... 90
ICW1: INTC1 Interrupt Initialization Command Word 1 (Write Only) - I/O Address=020H .............................. 91 ICW2: INTC1 Interrupt Initialization Command Word 2 (Write Only) - I/O Address=021H .............................. 91 ICW3: INTC1 Interrupt Initialization Command Word 3 (Write Only) - I/O Address=021H .............................. 92 ICW4: INTC1 Interrupt Initialization Command Word 4 (Write Only) - I/O Address=021H .............................. 92 ICW1: INTC2 Interrupt Initialization Command Word 1 (Write Only) - I/O Address=0A0H ............................. 93 ICW2: INTC2 Interrupt Initialization Command Word 2 (Write Only) - I/O Address=0A1H ............................. 93 ICW3: INTC2 Interrupt Initialization Command Word 3 (Write Only) - I/O Address=0A1H ............................. 93 ICW4: INTC2 Interrupt Initialization Command Word 4 (Write Only) - I/O Address=0A1H ............................. 94 OCW1: INTC1 Interrupt Operational Command Word 1 (Read/Write) - I/O Address=021H ........................... 94 OCW2: INTC1 Interrupt Operational Command Word 2 (Write Only) - I/O Address=020H ............................ 95 OCW3: INTC1 Interrupt Operational Command Word 3 (Write Only) - I/O Address=020H ............................ 95 OCW1: INTC2 Interrupt Operational Command Word 1 (Read/Write) - I/O Address=0A1H ........................... 96 OCW2: INTC2 Interrupt Operational Command Word 2 (Write Only) - I/O Address=0A0H ............................ 96 OCW3: INTC2 Interrupt Operational Command Word 3 (Write Only) - I/O Address=0A0H ............................ 97
CY82C693UB Timer/Counter Registers ................................................................................................ 98
Timer/Counter Register 0: Timer Control Word Register (Write Only) - Address=043H ................................. 98 Timer Control Word Register Format (Not Read-Back Command or Counter Latch Command) .................... 98 Timer Control Word Register Format (Read-Back Command) ........................................................................ 98 Timer Control Word Register Format (Counter Latch Command) ................................................................... 9 9
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TABLE OF CONTENTS (continued)
CY82C693UB
Timer/Counter Register 1: Counter 0 Register (Read/Write Except for Read-Back Status Command) - Address=040H .............................................................................................................................................. 99 Counter 0 Register Format (Read-Back Status Command - Read Only) ....................................................... 99 Timer/Counter Register 2: Counter 1 Register (Read/Write Except for Read-Back Status Command) - Address=041H .............................................................................................................................................. 99 Counter 1 Register Format (Read-Back Status Command - Read Only) ..................................................... 100 Timer/Counter Register 3: Counter 2 Register (Read/Write Except for Read-Back Status Command) - Address=042H ............................................................................................................................................ 100 Counter 2 Register Format (Read-Back Status Command - Read Only) ..................................................... 100
CY82C693UB Real-Time-Clock Registers .......................................................................................... 101
RTC Register 0: Seconds Byte (Read/Write except for bit 7 which is always 0) - Index=00H ..................... 101 RTC Register 1: Seconds Alarm (Read/Write) - Index=01H ........................................................................ 101 RTC Register 2: Minutes Byte (Read/Write) - Index=02H ............................................................................ 101 RTC Register 3: Minutes Alarm (Read/Write) - Index=03H .......................................................................... 101 RTC Register 4: Hours Byte (Read/Write) - Index=04H ............................................................................... 101 RTC Register 5: Hours Alarm (Read/Write) - Index=05H ............................................................................. 101 RTC Register 6: Day-of-the-Week Byte (Read/Write) - Index=06H ............................................................. 101 RTC Register 7: Day-of-the-Month Byte (Read/Write) - Index=07H ............................................................. 102 RTC Register 8: Month Byte (Read/Write) - Index=08H ............................................................................... 102 RTC Register 9: Year Byte (Read/Write) - Index=09H ................................................................................. 102 RTC Register 10: Control/Status Register A (Read/Write except for bit 7 which is Read Only) - Index=0AH .................................................................................................................................................. 102 RTC Register 11: Control/Status Register B (Read/Write) - Index=0BH ...................................................... 103 RTC Register 12: Control/Status Register C (Read Only) - Index=0CH ...................................................... 104 RTC Register 13: Control/Status Register D (Read Only) - Index=0DH ...................................................... 104 RTC Registers 14-127: Battery-Backable Scratch Block 1 (Read/Write) - Indices=0EH-7FH ...................... 104 RTC Registers 128-255: Battery-Backable Scratch Block 2 (Read/Write) - Indices=80H-FFH .................... 104
CY82C693UB Keyboard/Mouse Controller Registers ......................................................................... 105
Keyboard/Mouse Register 0: Status Register (Read Only) - I/O Read to address 64H ................................ 105 Keyboard/Mouse Register 1: Command Byte Register ................................................................................. 106 System to Controller Command Set .............................................................................................................. 107 Controller to System Command Set .............................................................................................................. 108 System to Keyboard Command Set .............................................................................................................. 109 Keyboard to System Command Set .............................................................................................................. 109 System to Mouse Controller Command Set .................................................................................................. 110 Mouse to System Controller Command Set .................................................................................................. 111
CY82C693UB PCI Configuration Registers ......................................................................................... 112 PCI to ISA PCI Configuration Registers (Function 0 during Configuration Cycle) ............................... 112
Register 0: Vendor ID Number (Read Only) - Index=00H with a 16-bit access ............................................ 112 Register 1: Device ID Number (Read Only) - Index=02H with a 16-bit access ............................................ 112 Register 3: Command Register (Read/Write) - Index=04H with a 16-bit access .......................................... 112 Register 4: Status Register (Read/Write) - Index=06H with a 16-bit access ................................................ 113 Register 5: Revision ID Number (Read Only) - Index=08H with an 8-bit access ......................................... 113 Register 6: Programming Interface Revision ID Number (Read Only) - Index=09H with an 8-bit access .... 113 Register 7: Sub Class Code Register (Read Only) - Index=0AH with an 8-bit access ................................. 113 Register 8: Base Class Code Register (Read Only) - Index=0BH with an 8-bit access ............................... 114 Register 9: Header Type Register (Read Only) - Index=0EH with an 8-bit access ...................................... 114 Register 10: PCI Interrupt A Routing Control Register (Read/Write) - Index=40H with an 8-bit access ...... 114 Register 11: PCI Interrupt B Routing Control Register (Read/Write) - Index=41H with an 8-bit access ...... 114 Register 12: PCI Interrupt C Routing Control Register (Read/Write) - Index=42H with an 8-bit access ...... 115 Register 13: PCI Interrupt D Routing Control Register (Read/Write) - Index=43H with an 8-bit access ...... 115 Register 14: PCI Control Register (Read/Write) - Index=44H with an 8-bit access ...................................... 115
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TABLE OF CONTENTS (continued)
CY82C693UB
Register 15: PCI Error Control Register (Read/Write) - Index=45H with an 8-bit access ............................. 116 Register 16: PCI Error Status Register (Read/Write) - Index=46H with an 8-bit access .............................. 116 Register 17: PCI BIOS Control Register (Read/Write) - Index=47H with an 8-bit access ............................ 117 Register 18: ISA/DMA Top of Memory Control (Read/Write) - Index=48H with an 8-bit access .................. 117 Register 19: AT Control Register #1 (Read/Write) - Index=49H with an 8-bit access .................................. 118 Register 20: AT Control Register #2 (Read/Write) - Index=4AH with an 8-bit access .................................. 118 Register 21: PCI IDE Interrupt Request 0 Routing Control Register (Read/Write) Index=4BH with an 8-bit access .................................................................................................................... 119 Register 22: PCI IDE Interrupt Request 1 Routing Control Register (Read/Write) Index=4CH with an 8-bit access .................................................................................................................... 119 Register 23: CY82C693UB Stand-Alone Control and USB Host Controller Control Register (Read/Write) - Index=4DH with an 8-bit access .................................................................................................................. 120 Register 24: CY82C693UB USB Control Register 1 (Read/Write) - Index=4EH with an 8-bit access .......... 121 Register 24: CY82C693UB USB Control Register 2 (Read/Write) - Index=4FH with an 8-bit access .......... 121
Primary Channel IDE PIO (Programmed I/O) PCI Configuration Registers (Function 1 during Configuration Cycle) ................................................. 122
Register 0: Vendor ID Number (Read Only) - Index=00H with a 16-bit access ............................................ 122 Register 1: Device ID Number (Read Only) - Index=02H with a 16-bit access ............................................ 122 Register 2: Command Register (Read/Write) - Index=04H with a 16-bit access .......................................... 122 Register 3: Status Register (Read/Write) - Index=06H with a 16-bit access ................................................ 123 Register 4: Revision ID Number (Read Only) - Index=08H with an 8-bit access ......................................... 123 Register 5: Class Code Register (Read Only) - Index=09H with a 32-bit access ......................................... 123 Register 6: Header Type Register (Read Only) - Index=0EH with an 8-bit access ...................................... 123 Register 7: Primary IDE Command Address Register (Read/Write) - Index=10H with a 32-bit access ....... 123 Register 8: Primary IDE Control Address Register (Read/Write) - Index=14H with a 32-bit access ............ 124 Register 9: Primary Bus Master IDE Control Address Register (Read/Write) Index=20H with a 32-bit access ..................................................................................................................... 124 Register 10: Primary IDE Interrupt INTA Control Register (Read/Write) - Index=3CH with an 8-bit access 124 Register 11: Primary IDE Interrupt Pin Control Register (Read Only) - Index=3DH with an 8-bit access .... 124 Register 12: Primary IDE Control Register (Read/Write) - Index=40H with a 32-bit access ........................ 125 Register 13: Primary IDE Address Setup Control Register (Read/Write) - Index=48H with a 32-bit access 125 Register 14: Primary Master Drive IDE IOR Command Control Register (Read/Write) Index=4CH with an 8-bit access .................................................................................................................... 125 Register 15: Primary Master Drive IDE IOW Command Control Register (Read/Write) Index=4DH with an 8-bit access .................................................................................................................... 126 Register 16: Primary Slave Drive IDE IOR Command Control Register (Read/Write) Index=4EH with an 8-bit access .................................................................................................................... 126 Register 17: Primary Slave Drive IDE IOW Command Control Register (Read/Write) Index=4FH with an 8-bit access .................................................................................................................... 126 Register 18: Primary Master Drive 8-Bit IDE Command Control Register (Read/Write) Index=50H with an 8-bit access ..................................................................................................................... 126 Register 19: Primary Slave Drive 8-Bit IDE Command Control Register (Read/Write) Index=51H with an 8-bit access ..................................................................................................................... 126 Register 20: Primary Master Drive IORDY Control Register (Read/Write) Index=52H with an 8-bit access ..................................................................................................................... 127 Register 21: Primary Slave Drive IORDY Control Register (Read/Write) Index=53H with an 8-bit access ..................................................................................................................... 127
Secondary Channel IDE PIO (Programmed I/O) PCI Configuration Registers (Function 2 during Configuration Cycle) ................................................. 128
Register 0: Vendor ID Number (Read Only) - Index=00H with a 16-bit access ............................................ 128 Register 1: Device ID Number (Read Only) - Index=02H with a 16-bit access ............................................ 128 Register 2: Command Register (Read/Write) - Index=04H with a 16-bit access .......................................... 128
8
PRELIMINARY
TABLE OF CONTENTS (continued)
CY82C693UB
Register 3: Status Register (Read/Write) - Index=06H with a 16-bit access ................................................ 129 Register 4: Revision ID Number (Read Only) - Index=08H with an 8-bit access ......................................... 129 Register 5: Class Code Register (Read Only) - Index=09H with a 32-bit access ......................................... 129 Register 6: Header Type Register (Read Only) - Index=0EH with an 8-bit access ...................................... 129 Register 7: Secondary IDE Command Address Register (Read/Write) - Index=10H with a 32-bit access .. 129 Register 8: Secondary IDE Control Address Register (Read/Write) - Index=14H with a 32-bit access ....... 130 Register 9: Secondary IDE Interrupt INTB Control Register (Read/Write) Index=3CH with an 8-bit access .................................................................................................................... 130 Register 10: Secondary IDE Interrupt Pin Control Register (Read Only) - Index=3DH with an 8-bit access 130 Register 11: Secondary IDE Control Register (Read/Write) - Index=40H with a 32-bit access ................... 130 Register 12: Secondary IDE Address Setup Control Register (Read/Write) Index=48H with a 32-bit access ..................................................................................................................... 131 Register 13: Secondary Master Drive IDE IOR Command Control Register (Read/Write) Index=4CH with an 8-bit access .................................................................................................................... 131 Register 14: Secondary Master Drive IDE IOW Command Control Register (Read/Write) Index=4DH with an 8-bit access .................................................................................................................... 131 Register 15: Secondary Slave Drive IDE IOR Command Control Register (Read/Write) Index=4EH with an 8-bit access .................................................................................................................... 131 Register 16: Secondary Slave Drive IDE IOW Command Control Register (Read/Write) Index=4FH with an 8-bit access .................................................................................................................... 131 Register 17: Secondary Master Drive 8-Bit IDE Command Control Register (Read/Write) Index=50H with an 8-bit access ..................................................................................................................... 132 Register 18: Secondary Slave Drive 8-Bit IDE Command Control Register (Read/Write) Index=51H with an 8-bit access ..................................................................................................................... 132 Register 19: Secondary Master Drive IORDY Control Register (Read/Write) Index=52H with an 8-bit access ..................................................................................................................... 132
USB Host Controller PCI Configuration Registers (Function 3 during Configuration Cycle) ............... 133
Register 0: Vendor ID Number (Read Only) - Index=00H with a 16-bit access ............................................. 133 Register 1: Device ID Number (Read Only) - Index=02H with a 16-bit access ............................................. 133 Register 2: Command Register (Read/Write) - Index=04H with a 16-bit access ........................................... 133 Register 3: Status Registers (Read/Write) - Index=06H with a 16-bit access ............................................... 134 Register 4: Revision ID Number (Read Only) - Index=08H with an 8-bit access .......................................... 134 Register 5: Class Code Register (Read Only) - Index=09H with a 24-bit access .......................................... 135 Register 6: Cache Line Size (Read/Write) - Index=0CH with an 8-bit access ............................................... 135 Register 7: Latency Timer (Read/Write) - Index=0DH with an 8-bit access .................................................. 135 Register 8: Header Type Register (Read Only) - Index=0EH with an 8-bit access ....................................... 135 Register 9: BIST Register (Read Only) - Index=0FH with an 8-bit access .................................................... 135 Register 10: Base Address Register (Read/Write) - Index=10H with a 32-bit access ................................... 135 Register 11: Interrupt LIne Register (Read/Write) - Index=3CH with an 8-bit access ................................... 135 Register 12: Interrupt Pin Register (Read/Write) - Index=3DH with an 8-bit access ..................................... 136 Register 13: Min_Gnt Register (Read Only) - Index=3EH with an 8-bit access ............................................ 136 Register 14: Max_Lat Register (Read Only) - Index=3FD with an 8-bit access ............................................ 136 Register 15: ASIC Test Mode Enable Register (Read/Write) - Index=40H with a 32-bit access ................... 136 Register 16: ASIC Operational Mode Enable Register (Read/Write) - Index=44H with an 8-bit access ....... 136
USB Host Controller Operational Registers ......................................................................................... 137
Register 0: HcRevision (Read Only) - Offset=00H with a 32-bit access ........................................................ 137 Register 1: HcControl (Read/Write) - Offset=04H with a 32-bit access ......................................................... 137 Register 2: HcCommandStatus (Read/Write) - Offset=08H with a 32-bit access .......................................... 138 Register 3: HcInterruptStatus (Read/Write) - Offset=0CH with a 32-bit access ............................................ 138 Register 4: HcInterruptEnable (Read/Write) - Offset=10H with a 32-bit access ............................................ 139 Register 5: HcInterruptDisable (Read/Write) - Offset=14H with a 32-bit access ........................................... 140 Register 6: HcHCCA (Read/Write) - Offset=18H with a 32-bit access .......................................................... 140
9
PRELIMINARY
TABLE OF CONTENTS (continued)
CY82C693UB
Register 7: HcPeriodCurrentED (Read/Write) - Offset=1CH with a 32-bit access ........................................ 140 Register 8: HcControlHeadED (Read/Write) - Offset=20H with a 32-bit access ........................................... 140 Register 9: HcControlCurrentED (Read/Write) - Offset=24H with a 32-bit access ........................................ 141 Register 10: HcBulkHeadED (Read/Write) - Offset=28H with a 32-bit access .............................................. 141 Register 11: HcBulkCurrentED (Read/Write) - Offset=2CH with a 32-bit access .......................................... 141 Register 12: HcDoneHead (Read/Write) - Offset=30H with a 32-bit access ................................................. 141 Register 13: HcFmInterval (Read/Write) - Offset=34H with a 32-bit access ................................................. 141 Register 13: HcFrameRemaining (Read Only) - Offset=38H with a 32-bit access ........................................ 141 Register 14: HcFmNumber (Read Only) - Offset=3CH with a 32-bit access ................................................. 142 Register 15: HcPeriodicStart (Read/Write) - Offset=40H with a 32-bit access .............................................. 142 Register 16: HcLSThreshold (Read/Write) - Offset=44H with a 32-bit access .............................................. 142 Register 17: HcRhDescriptorA (Read/Write) - Offset=48H with a 32-bit access ........................................... 142 Register 18: HcRhDescriptorB (Read/Write) - Index=4CH with a 32-bit access ........................................... 143 Register 19: HcRhStatus (Read/Write) - Index=50H with a 32-bit access .................................................... 144 Register 20: HcRhPortStatus[1:2] (Read/Write) - Index=54H, 58H with a 32-bit access .............................. 145 Register 21: HceControl (Read/Write) - Index=100H with a 32-bit access .................................................... 146 Register 22: HceInput - Index=104H with a 32-bit access ............................................................................. 147 Register 23: HceOutput - Index=108H with a 32-bit access .......................................................................... 147 Register 24: HceStatus (Read/Write) - Index=10CH with a 32-bit access .................................................... 147
Maximum Ratings ................................................................................................................................ 148 Electrical Characteristics ...................................................................................................................... 148 Switching Waveforms .......................................................................................................................... 149 Ordering Information ............................................................................................................................ 163 Package Diagrams .............................................................................................................................. 164
10
PRELIMINARY
CY82C693UB Signals
CY82C693UB
AD[31:0] PCICLK C/BE[3:0] FRAME IRDY TRDY DEVSEL PAR STOP SERR IDSEL INTA INTB INTC INTD GNTBSY/GRANT FREQACK/IRQ8 REQ[3:0]/PGNT/SGNT GNT[3:0]/PREQ/SREQ IRQ8/PSRSTB VCCBAT X2/RTCRD[1] X1/RTCWT[2] ROMCS/ROMMODE SMI/GBSEP STOPCLK/RSTCHG EPMI PWGD CPURST PCIRST INIT USB_CLK USB_D1+/USB_D1- USB_D2+/USB_D2-
SA[19:4]/PCIIDE[15:0],SA[3:0] SD[15:0] XD[7:0]/IDEDMA/IDEIRQ LA[23:17]/PIDECS's/PCIIDEA[2:0] IRQ[15:14],[11:9],[7:3] INTR/KBATMODE NMI ATCLK ALE DREQ[7:5]/GPIO DACK[7:5]/GPIO/Config. REFSH SPKR EOP IGNNE/ROMS1 FERR IOCS16 MCS16 SBHE MRD,MWT,IOR,IOW, SMEMR,SMEMW OSC 0WS AEN IOCHRDY IOCHK KBDATA IRQ1/KBCLK MSDATA/KBDCLK IRQ12/MSCLK KBCS/KYLCK GTA20/ROMS0 IDEIOR,IDEIOW IDEIOCS16 BLKIDE
PCI Signals ISA Signals
RTC/ROM Signals Power Mgmt. Signals Reset Signals
Keyboard/ Mouse Signals
USB Signals
Dedicated IDE Signals
NOTES: 1. RTCRD available only as bond option. 2. RTCWT available only as bond option.
82C693UB-2
11
PRELIMINARY
Pin Configuration
208-pin PQFP Top View
208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167
CY82C693UB
166 165
164 163
162 161
160
159 158
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73
156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105
CY82C693UB
12
97 98 99 100 101 102 103 104 82C693UB-2
74 75 76
77 78 79 80
81 82 83 84 85
86 87 88 89
90 91 92 93
94 95 96
157
PRELIMINARY
CY82C693UB Pin Reference (In Numerical Order by Pin Number)
Pin # Pin Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 GND FRAME IDSEL TRDY IRDY DEVSEL SERR PAR USB_D1+ USB_D1- C/BE3 C/BE2 C/BE1 C/BE0 USB_CLK AD31 AD30 AD29 AD28 +5V GND AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 +5V GND AD17 Pin # 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 Pin Name AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 GND IOCHK IOCHRDY 0WS AEN SMEMW SMEMR IOW IOR LA23/IDECS0 LA22/IDECS1 LA21/SIDECS0 +5V LA20/SIDECS1 GND LA19/IDEA2 LA18/IDEA1 LA17/IDEA0 GND SA19/IDE15 SA18/IDE14 SA17/IDE13 SA16/IDE12 SA15/IDE11 Pin # 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 Pin Name SA7/IDE3 SA6/IDE2 SA5/IDE1 SA4/IDE0 SA3 SA2 SA1 SA0 GND ROMCS/ ROMMODE IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ1/KBCLK REFSH IRQ9 ALE +5V GND IRQ10 ATCLK IRQ11 IRQ12/MSCLK IRQ14 IRQ15 DACK0/TSTM DACK1/TSTM0 DACK2/TSTM1 DACK3/ DISPSEL DACK5/KBSEL/GPIO9 DACK6/RTCSEL/GPIO10 DACK7/EXTBUF/GPIO11 Pin # 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 Pin Name X1/RTCWT(bond option only) PWGD DRQ0 DRQ5/GPIO6/ PWREN DRQ6/GPIO7/ OVRCUR DRQ7/GPIO8/ SMIACT OSC SD0 SD1 +5V GND SD2 SD3 SD4 SD5 SD6 SD7 MRD MWT SD15 SD14 SD13 SD12 SD11 GND SD10 SD9 SD8 XD0/XDIR +5V BLKIDE XD1/XDEN XD2/IACK1 XD3/IREQ1
CY82C693UB
Pin # 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202
Pin Name +3.3V GTA20/ROMS0 GND STOPCLK/ RSTCHG CPURST INIT NMI INTR/ KBATMODE IGNNE/ROMS1 FERR SMI/GBSEP USB_D2+ USB_D2- EPMI MSDATA/ KBDCLK KBCS/KYLCK KBDATA IDEIOCS16 IDEIOW IDEIOR GNTBSY/ GRANT FREQACK/IRQ8 GNT0/PREQ GNT1/SREQ GNT2/SQWV GNT3/DISARB +5V REQ0/PGNT GND REQ1/SGNT REQ2 REQ3 PCIRST INTD
13
PRELIMINARY
CY82C693UB Pin Reference (In Numerical Order by Pin Number) (continued)
Pin # Pin Name 35 36 37 38 39 40 41 42 AD16 AD15 AD14 AD13 AD12 AD11 AD10 GND Pin # 77 78 79 80 81 82 83 84 Pin Name SA14/IDE10 SA13/IDE9 SA12/IDE8 SA11/IDE7 GND SA10/IDE6 SA9/IDE5 SA8/IDE4 Pin # 119 120 121 122 123 124 125 126 Pin Name EOP DRQ1 DRQ3 DRQ2 IRQ8/PSRSTB VCCBAT GND X2/RTCRD (bond option only) Pin # 161 162 163 164 165 166 167 168 Pin Name XD4/IACK0 XD5/IREQ0 XD6/IDEIRQ1/ GPIO1/BUSY XD7/IDEIRQ0/ GPIO0 SBHE MCS16 IOCS16 SPKR
CY82C693UB
Pin # 203 204 205 206 207 208
Pin Name INTC INTB INTA STOP PCICLK +5V
CY82C693UB Pin Reference (In Alphabetical Order by Signal Name)
Pin Name AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 Pin No. 52 51 50 49 48 47 46 45 44 43 41 40 39 38 37 36 35 34 31 30 29 Pin Name C/BE3 CPURST DACK0/TSTM Pin No. 11 173 114 Pin Name INTR/ KBATMODE IOCHK IOCHRDY IOCS16 IOR IOW IRDY IRQ1/KBCLK IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8/PSRSTB IRQ9 IRQ10 IRQ11 IRQ12/MSCLK IRQ14 IRQ15 KBCS/KYLCK Pin No. 176 54 55 167 61 60 5 100 99 98 97 96 95 123 102 106 108 109 110 111 184 SA0 SA1 SA2 SA3 SA4/IDE0 SA5/IDE1 SA6/IDE2 SA7/IDE3 SA8/IDE4 SA9/IDE5 SA10/IDE6 92 91 90 89 88 87 86 85 84 83 82 PWGD REFSH REQ0/ PGNT REQ1/ SGNT REQ2 REQ3 128 101 196 198 199 200 Pin Name Pin No. SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15 SERR SMEMR SMEMW SMI/GBSEP SPKR STOP STOPCLK/ RSTCHG TRDY USB_CLK USB_D1+ USB_D1- USB_D2+ USB_D2- Pin Name Pin No. 154 153 152 150 149 148 147 146 7 59 58 179 168 206 172 4 15 9 10 180 181
DACK1/TSTM0 114 DACK2/TSTM1 114 DACK3 / DISPSEL DACK5/ KBSEL/GPIO9 DACK6/RTCSEL/GPIO10 DACK7/EXTBUF/GPIO11 DEVSEL DRQ0 DRQ1 DRQ2 DRQ3 DRQ5/GPIO6/ PWREN DRQ6/GPIO7/ OVRCUR DRQ7/GPIO8/ SMIACT EOP EPMI FERR FRAME 115 116 117 118 6 129 120 122 121 130 131 132 119 182 178 2
ROMCS/ 94 ROMMODE
14
PRELIMINARY
CY82C693UB Pin Reference (In Alphabetical Order by Signal Name) (continued)
Pin Name AD21 AD22 Pin No. 28 27 Pin Name FREQACK/ IRQ8 GND Pin No. 190 1, 21, 33, 42, 53, 67, 71, 81, 93, 105, 125, 137, 151, 171,197 191 192 193 194 189 Pin Name KBDATA LA17/IDEA0 Pin No. 185 70 Pin Name SA11/IDE7 SA12/IDE8 Pin No. 80 79
CY82C693UB
Pin Name VCCBAT X1/RTCWT (bond option only)
Pin No. 124 127
AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 AEN ALE ATCLK
26 25 24 23 22 19 18 17 16 57 103 107
GNT0/PREQ GNT1/SREQ GNT2/SQWV GNT3/DISARB GNTBSY/ GRANT IDEIOCS16 IDEIOR IDEIOW IDSEL
LA18/IDEA1 LA19/IDEA2 LA20/SIDECS1 LA21/SIDECS0 LA22/IDECS1 LA23/IDECS0
69 68 66 64 63 62
SA13/IDE9
78
X2/RTCRD (bond option only) XD0/XDIR XD1/XDEN XD2/IACK1 XD3/IREQ1 XD4/IACK0 XD5/IREQ0 XD6/IDEIRQ1/ GPIO1/BUSY XD7/IDEIRQ0/ GPIO0 0WS +3.3V +5V
126 155 158 159 160 161 162 163 164 56 169 20,32, 65,104, 136,156, 195,208
SA14/IDE10 77 SA15/IDE11 76 SA16/IDE12 75 SA17/IDE13 74 SA18/IDE14 73 SA19/ IDE15 72 165 134 135 138 139
GTA20/ROMS0 170 186 188 187 3
MCS16 MRD MSDATA/ KBDCLK MWT NMI
166 144 183 145 175
SBHE SD0 SD1 SD2 SD3
IGNNE/ROMS1 177 INIT 174
BLKIDE 157 C/BE0 C/BE1 C/BE2 14 13 12
INTA INTB INTC INTD
205 204 203 202
OSC PAR PCICLK PCIRST
133 8 207 201
SD4 SD5 SD6 SD7
140 141 142 143
15
PRELIMINARY
CY82C693UB
To Keyboard Connector
Reset Circuitry
Keyboard Controller
DMA Controllers
Power Management Logic
Timer/Counter
Pre-Read/ Post-write Buffers
AT Refresh Logic
XD Bus
ROM/Flash Control ISA Bus
ISA Interface USB Bus USB Host Controller
PCI Interface
PCI Bus PCI Arbiter (can be disabled) IDE Controller Interrupt Controllers Real-TimeClock
Figure 1. CY82C693UB Functional Block Diagram
16
PRELIMINARY
Introduction
System Overview The hyperCacheTM family is a family of chips created to provide flexible solutions for today's PC designs. The chipset provides all the functions necessary to implement a 3.3V Pentium-class processor based system with the USB (Universal Serial Bus), PCI (Peripheral Component Interconnect), and the ISA (Industry Standard Architecture) buses. System designers can exploit the advantages of the USB and PCI buses while maintaining access to the large base of ISA cards in the marketplace. The Cypress hyperCache family offers system designers several key advantages. With only three chips, a complete system can be implemented. Cache can be added up to 512 MB with additional CY82C694 devices in 128-KB increments All chipset solutions are pin-compatible and provide flexible upgrade paths through on-board or external cache modules. Six banks of page-mode or EDO DRAM further increase the system designer's options. The chipset also contains concurrent bus support, PCI enhanced IDE with CD-ROM support, integrated RTC, integrated peripheral control (Interrupts/DMA), and integrated keyboard controller. This chipset is flexible enough to provide the system designer with many cost/performance/function options to provide an optimum solution for a given design. CY82C693UB Introduction The CY82C693UB Peripheral Controller provides a highly integrated peripheral solution for PCI-based motherboards. The CY82C693UB contains a PCI to ISA bridge, a PCI IDE controller, DMA controllers, Interrupt controllers, a RealTime-Clock, Keyboard controller and a USB Host Controller.
CY82C693UB
cards to be added to the system. PCI is the predominant local bus for Pentium systems. Master cycles are initiated by driving FRAME LOW with a valid address on AD[31:0], valid even address parity on PAR, and a valid command on C/BE[3:0]. Data phases occur when IRDY (initiator ready) and TRDY (target ready) are both active, valid data is placed on AD[31:0], the PAR signal is driven to reflect even parity, and the correct byte enable combination is present on C/BE[3:0]. Wait states can be inserted into a transaction if the initiator deasserts IRDY or the target deasserts TRDY. A transaction is terminated by the deassertion of FRAME prior to the final data phase. As a PCI master, the CY82C693UB will only perform memory read and write transactions. A read or write cycle consists of a maximum of 4 bytes of data in a single data cycle. The CY82C693UB uses a subtractive decode strategy to determine if a PCI target transaction is destined for the ISA bus. Potential PCI targets decode any valid address during the first cycle of the transaction (FRAME asserted). If a PCI peripheral device (including the integrated IDE controller in the CY82C693UB) detects a transaction to its address space, it will assert DEVSEL. If the CY82C693UB does not detect the assertion of DEVSEL by another target (or its own IDE controller) within 4 PCI clock cycles, it will claim the transaction by asserting DEVSEL. All transactions that are not claimed by a PCI peripheral are, by default, sent to the ISA bus. After asserting DEVSEL, the CY82C693UB will initiate an ISA cycle and assert TRDY to the PCI bus when valid data is available. As a PCI slave, the CY82C693UB will target-terminate the cycle after the first data transfer by asserting STOP with TRDY if FRAME is not deasserted before the data phase. The CY82C693UB does not accept bursts as a target. By not allowing target bursts, PCI bus bandwidth, which would otherwise be quickly consumed by ISA or IDE targets, is conserved. The CY82C693UB supports PCI error reporting through the SERR (system error) signal. Both internally detected and externally generated errors are reported. SERR is asserted for any system error, including address/data parity errors on Special Cycle commands, except for data parity. If the CY82C693UB detects the assertion of SERR, it will assert NMI (non-maskable interrupt) to the CPU. The CY82C693UB will store the source of the NMI (SERR) in an internal configuration register to allow the NMI handler software to determine the cause of the error. The CY82C693UB supports the four PCI interrupt signals (INTA, INTB, INTC, and INTD). The interrupt lines are open-drain and should be routed to all of the PCI slots. For single-function devices, only INTA should be used. The three other interrupt lines can be connected to any set of functions on a multi-function device. Each interrupt signal can be programmed to be level-sensitive (PCI Compliant) or edge-triggered (not PCI Compliant). The assertion of a PCI interrupt request will cause the INTR signal to be asserted to the processor. When the processor performs an interrupt acknowledge cycle, the CY82C693UB will return an interrupt vector based on the level of the PCI interrupt. The PCI interrupt levels are programmable. Interrupt programmability is useful in resolving system conflicts. The CY82C693UB contains the PCI arbiter. The CY82C693UB supports up to five PCI masters, including the CY82C691. There are four dedicated request and grant line pairs, one for each slot, and a special busy and grant for the
Figure 1 shows a block diagram of the CY82C693UB.
Functional Overview
The CY82C693UB Peripheral Controller contains the following functional blocks: * PCI Interface * ISA Interface * Reset Logic * Keyboard Controller * Power Management Logic * AT Refresh Logic * Pre-Read/Post-Write Buffers * BIOS ROM Control * Timer/Counter Logic * DMA Controllers * Dual-Channel Enhanced IDE Controller * Real-Time-Clock with 32-kHz Oscillator * Interrupt Controllers * USB Host Controller PCI Bus Interface The CY82C693UB provides a bridge for transactions between the PCI bus, the ISA bus, and IDE peripherals. PCI bus speeds of 25, 30, or 33 MHz are supported. The PCI interface is master/slave (it can initiate or be a target for transactions). The PCI bus interface in the CY82C693UB is Revision 2.1 compliant. This standard allows for a multitude of high-speed peripheral
17
PRELIMINARY
CY82C691. The CY82C691 is the default owner of the PCI bus. If the CY82C691 requires ownership of PCI and is granted the bus, it will assert the GNTBSY signal. When the CY82C693UB sees another master's request asserted, and no higher priority masters are requesting the bus, the CY82C693UB will remove the grant from the CY82C691 and give the grant to the new master. The CY82C693UB supports rotating priority. In rotating priority, the last master to be granted the bus becomes lowest priority. The CY82C691 is always given highest priority to reduce CPU latency due to arbitration. ISA Bus Interface The CY82C693UB contains an ISA (Industry Standard Architecture) Bus interface. If no other target in the system claims the transaction, it is passed to the ISA bus. The ISA bus interface in the CY82C693UB is full master/slave, allowing a myriad of low-cost peripheral cards to be added to the system. ISA master cycles are performed by the CY82C693UB whenever a PCI master wants to access an ISA peripheral card. The CY82C693UB drives the address onto the ISA address lines and asserts BALE. The accessed resource will then respond with its size by the assertion/negation of the IOCS16 or MEMCS16 signals. The appropriate command signals (SMEMR, SMEMW, MEMR, MEMW, IOR, or IOW) will then be asserted by the CY82C693UB. The deassertion of the active command signal indicates when valid data is on the bus. Wait states can be inserted into an ISA cycle by the target's negation of the IOCHRDY signal. This forces the command signal to stay on the bus until IOCHRDY is asserted again. An ISA peripheral requests ownership of the ISA bus by asserting its DMA request signal. The request can be either a normal ISA transaction controlled by the peripheral itself, or a DMA transaction using transfer parameters (such as starting address and block count) previously set up in the DMA controller inside the CY82C693UB. In a normal ISA transaction, the ISA master begins its transfers after receiving DMA acknowledge from the CY82C693UB. The CY82C693UB differentiates a normal ISA bus request from an ISA DMA request by checking the transfer parameters (in the on-chip DMA controller) corresponding to the above DMA request signal. If no transfer parameters are stored, then the request is a normal ISA transfer. If the ISA request is a DMA transfer, the CY82C693UB outputs the pre-programmed starting address and the control signals onto the ISA bus. It will also assert AEN to the requesting ISA bus master so that it will ignore the address and simply provide the data to be transferred onto the ISA bus. The address on the ISA bus is the memory address used to route the DMA data to the proper memory location. If the target for a DMA/MASTER ISA cycle is on the PCI bus, the PCI bus will be arbitrated for before the CY82C693UB will assert the DMA acknowledge to the ISA master. When either an ISA master request or a DMA request is asserted to the CY82C693UB, system data coherency must be maintained. This is accomplished using two sideband signals between the CY82C691 and the CY82C693UB (FREQACK and GNTBSY). When the CY82C693UB detects the assertion of one of the DMA request signals, it will assert FREQACK for one clock cycle. This is a request to the CY82C691 to flush all write buffers. After driving FREQACK for one cycle, the CY82C693UB will drive the signal deasserted (HIGH) for one PCI clock cycle and float the signal (rescind). After the
CY82C693UB
CY82C691 has flushed its write buffers (causing memory to be coherent with respect to the write buffer contents), the CY82C691 will assert FREQACK for one PCI clock cycle and rescind. This informs the CY82C693UB that the write buffers have been flushed and it is free to take control of the PCI bus and perform the ISA master/DMA transfer. GNTBSY performs the PCI arbitration function between the CY82C691 and the CY82C693UB. The CY82C691 is the default owner of the PCI bus (GNTBSY is asserted LOW by the CY82C693UB in the default state). When the CY82C693UB wants access to the PCI bus, it drives GNTBSY HIGH for one PCI clock cycle and rescinds the signal. If the CY82C691 has a PCI bus cycle pending, it will drive GNTBSY LOW until it is finished with its transaction (PCI bus busy). Once the CY82C691 has finished its pending transaction, it will deassert GNTBSY and rescind. When the CY82C693UB sees GNTBSY deasserted, it is free to grant the PCI bus to another master. The CY82C693UB will leave GNTBSY deasserted as long as a master other than the CY82C691 is on the PCI bus. Once the other PCI masters finish their transactions, the CY82C693UB will assert GNTBSY to inform the CY82C691 that it is free to take the PCI bus again. Because a PCI data transfer is up to 32 bits wide on byte boundaries and ISA data can be eight or sixteen bits wide, the CY82C693UB performs bus steering. Based on the address, the state of the C/BE[3:0] signals and the width of the ISA bus resident, the CY82C693UB will steer data to/from the PCI data bus from/to the ISA data bus. If a PCI read transaction from the ISA bus requires data larger than the 8/16-bit ISA data width, the CY82C693UB can be programmed to perform multiple ISA transactions and pack the data into a single, larger PCI data word. If less than 32 bits are required on the PCI bus (by the assertion of fewer than all 4 byte enables), only the requested data will be packed and presented on the PCI data lines. On an ISA MASTER write, data will be driven onto the PCI bus as it is written (not packed). The ISA bus interface in the CY82C693UB allows for fully synchronous/asynchronous operation. In other words, the ISA clock can be synchronized to a divided-down version of the PCI clock, or the PCI and ISA clocks can be fully independent in frequency and phase. The CY82C693UB can switch the ISA clock to a fixed 7.16-MHz clock if the PCI clock is slowed to conserve system power. The COMMAND recovery time is programmable (either 1.5 or 2.5 ISA clock cycles). Command recovery is the amount of idle ISA cycles between back-to-back ISA transactions. This allows for a trade-off between extra performance and card compatibility. The default is 2.5 ISA clock cycles. However, if the ISA peripheral cards in the system can support 1.5 ISA clocks, the CY82C693UB can be programmed to reduce the overall ISA cycle time. The CY82C693UB contains QuietBus logic. Control and data signals will only be passed from PCI to ISA when the CY82C693UB determines that the ISA bus is the intended target. This reduces the noise and power consumption associated with switching output buffers unnecessarily. It also eliminates some system EMI (Electro-Magnetic Interference). Reset Logic The CY82C693UB provides three signals for resetting system components, CPURST, INIT and RESET.
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CPURST is an active HIGH signal that provides power-on reset functionality for the CPU. CPURST is asserted when the CY82C693UB detects PWGD (power good) asserted from the power supply. CPURST forces the processor to begin execution in a known state. When the Pentium processor detects CPURST, it will immediately abort all bus activity and perform its reset sequence. The CY82C693UB will assert CPURST for a minimum of 1 ms after PWGD is asserted. This is sufficient to ensure a "cold" or "power-on" reset. The assertion of CPURST will cause all internal processor registers, write-buffers, and caches to be reset. The processor will begin execution by reading from address FFFFFFF0H upon the deassertion of CPURST. CPURST is also used to reset ISA peripherals (functions as SYSRESET). For a "warm" reset, INIT will be asserted for a minimum of 15 PCI clock cycles. A "warm" reset is performed whenever the CPU writes Port 92H, bit 0, to "1". The keyboard controller within the CY82C693UB can also issue a fast "warm" reset if the user writes FE (hex) to port 64 (hex). INIT provides CPURST functionality except INIT leaves the CPU's level 1 cache, internal write-buffers, and floating-point registers intact. Only the processor core is reset. INIT can be used to switch the processor from protected to real mode. Once INIT is sampled active, the processor will begin the initialization sequence on the next instruction boundary. The initialization sequence will continue to completion followed by normal reset execution (read from address FFFFFFF0H). INIT will be asserted for a minimum of two CPU clock cycles and will remain active for three CPU clock cycles prior to the BRDY of an I/O write cycle. RESET is used to reset all PCI peripherals (functions as PCIRST). RESET (like CPURST) will be asserted for a minimum of 1 ms after PWGD is asserted. Keyboard Controller The CY82C693UB integrates the essential functions of an 8042 Keyboard Controller including: * operating frequencies from 6 to 16 MHz * support for a PS/2-compatible mouse * complete operating system independence * works with MS-DOS(R), Microsoft Windows(R), OS/2(R), and UNIXTM
CY82C693UB
registers and ports that are user definable. As inputs, they set bits in internal reserved registers. As outputs, they reflect the value of the internal register bits. The general purpose I/Os are multiplexed with some alternate control signals, the XD bus, IDE DMA control, and IDE Interrupt Request signals. Therefore, these system functions will not be available from the CY82C693UB when the pins are programmed as general purpose I/Os. However, not every system will require the additional system functions, and those that do can implement these system functions externally if general purpose I/O is a requirement.
PS/2 Compatible Mouse Support
The CY82C693UB supports a PS/2 compatible mouse. MSCLK and MSDATA should be connected directly to the mouse connector. Mouse interrupt requests are generated internally.
Keyboard Interface
The CY82C693UB provides the KBCLK and KBDATA signals to connect directly to the keyboard controller. There is also a KEYLOCK pin which should be connected to the KEYLOCK connector. If KEYLOCK is active, the keyboard controller will not respond to inputs from the keyboard. The keyboard interrupt request is internally connected to the CY82C693UB's interrupt controller.
Maximum Flexibility
The internal keyboard controller can be disabled if a custom, external keyboard controller solution is desired. All of the signals needed to control and interface to an external keyboard controller are multiplexed with existing keyboard interface signals.
Keyboard Self-Test
The first access to the keyboard controller must be a write of AAH to port 64H. This initiates the keyboard self-test. A subsequent read of port 64H will issue 55H if self-test is passed. Prior to the write of AAH to port 64H, all keyboard controller accessed will be ignored. Power Management Logic The CY82C693UB provides flexible power management to help systems conform to governmental system power consumption guidelines. There are 5 timers within the power management logic (a standby timer, a suspend timer, user timer 1, user timer 2, and user timer 3). There are also 10 programmable event detectors. Events which can be monitored include: * Keyboard Commands * Serial Port Commands * Parallel Port Commands * Hard Disk Commands * DMA/ISA MASTER Requests * A Specific (set of) Interrupt Request(s) * Video Memory Accesses * Floppy Drive Accesses * A PCI Master Request * A Specific I/O Range The CY82C693UB can monitor any combination or all of the above events.
Operating Frequency
The keyboard controller inside the CY82C693UB operates at frequencies between 6 and 16 MHz. The clock is internally selectable.
Resetting the Keyboard Controller
The keyboard controller will be reset when the PWGD (power good) signal is negated. Once PWGD is asserted, the keyboard controller will remain in its reset state for 120 keyboard clock cycles before becoming operational.
Host Interface
PCI or ISA masters communicate with the keyboard controller by performing I/O reads and writes to two eight-bit port locations (0064H and 0060H). I/O Port 0064H is the command/status register and I/O Port 0060H is the data register. There are two host signals that the keyboard controller generates (or are functionally emulated within the CY82C693UB), GTA20 and INIT. These signals initiate the A20 mask and "warm reset" respectively. There are also four keyboard general purpose I/O
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Hardware power management can be selected to ease the power-down software requirements. In the hardware power management mode, the STOPCLK signal may be programmed to automatically assert when the suspend and/or standby timers expire. This signal is used to reduce the power consumption of the processors and peripherals when they are idle. Software power management works with CPU SMM (System Management Mode). All Pentium-class processors have SMM capabilities. SMM is entered through a dedicated System Management Interrupt (SMI). SMM has its own protected address space, which can only be accessed in System Management Mode. All power management software should be embedded in the SMI handler code stored in SMM space. SMM memory control is handled by the CY82C691 (please see CY82C691 datasheet). However, all SMI generation is handled by the CY82C693UB. The CY82C693UB supports Full-Speed, Standby, and Suspend power-down states. Other user-defined power-down states can be implemented. Full-Speed is the normal operating state. When power-management is enabled, the Standby timer will begin counting. The terminal count for the Standby timer can be set to various values between 0.2 seconds and 240 minutes. If any of the monitored events occur before the terminal count is reached, the standby timer will reset to zero and begin counting again. If the standby timer expires without detecting any monitored events, the CY82C693UB will assert SMI, allowing the SMI handler to transition the system into the Standby state. The SMI signal must be cleared (deasserted) by the SMI handler by performing a write to the CY82C693UB's internal SMI clear register (register E7H, bit 6). Once Standby state has been entered, the Suspend timer will begin counting. The terminal counts for the suspend timer can be set to values between 1 second and 480 minutes. If a Standby event is detected by the CY82C693UB before the suspend timer expires, the CY82C693UB will assert SMI, reset all timers (only the Suspend timer will be reset if the event is a Suspend event), and set a status register bit to identify the monitored event. The System Management Interrupt handler must determine the source of the SMI by reading CY82C693UB status registers. The handler code can use the SMI source information to determine which state to transition to. If the suspend timer expires before any monitored event occurs, the CY82C693UB will once again assert SMI so that the handler can transition to the Suspend state The user-definable timers (User timer 1, User timer 2, and User timer 3) can be used to create additional power-down states. They can be enabled or disabled at any time. The user timer terminal count values can be programmed to values between 1 second and 480 minutes. When any of the timers expire, the CY82C693UB will assert SMI (until it is cleared in the handler) and set a configuration register bit to indicate which timer(s) expired. The System Management Interrupt handler must read status registers to determine the source of the SMI. Software can then transition to any power-down state (pre-defined or user-defined). Only User timer 1 is programmable to be reset upon the detection of monitored events. There are two power control signals used by the CY82C693UB (STOPCLK, and EPMI). The first signal (STOPCLK) is register controlled and can be asserted or negated in any state. STOPCLK has been traditionally connected to the CPU's STOPCLK input to disable the clock to the internal CPU's core. When STOPCLK is enabled, it will periodically be asserted
CY82C693UB
and deasserted based on programmable STOPCLK period registers. This signal may also be used to power-down peripherals that support a power-down signal. External logic can force the CY82C693UB to assert SMI by activating the EPMI input. The CY82C693UB contains an internal interrupt/event counter. The terminal count for this timer should be programmed to the longest amount of time it takes to handle any interrupt. Whenever a user-selectable event (typically an interrupt) occurs, the STOPCLK signal will be deasserted for the time period of the interrupt timer. This allows the processor to handle the interrupt. If no other monitored events occur before the interrupt timer expires, STOPCLK will be reasserted. AT Refresh Logic The CY82C693UB contains logic to support refresh cycles on the ISA bus. An internal refresh request is generated every 15.6 microseconds. Upon detecting the refresh request, the CY82C693UB will arbitrate for the ISA bus and generate a refresh cycle. The CY82C693UB contains its own internal refresh counter and refresh address counter. During ISA refresh cycles, the CY82C693UB will not grant the ISA bus to any peripheral cards. If a PCI transaction is targeting ISA, the CY82C693UB will attempt to buffer the transaction. If the internal FIFO buffers are full or the transaction cannot be buffered, the CY82C693UB will negate TRDY until the refresh is completed. Pre-Read/Post-Write Buffers There are 3 FIFOs inside the CY82C693UB. PCI/ISA FIFOs are 1 entry deep and 32 bits wide. There is one 4 entries deep by 32 bit wide FIFO for each IDE channel. PCI to ISA or IDE transactions are buffered to improve system performance. ISA or IDE transactions will likewise be buffered for transmission to the PCI bus. PIO IDE transactions go through their own independent buffers. The buffers eliminate some of the latency due to arbitration for resources. BIOS ROM Control The CY82C693UB provides all of the control signals to support both Flash and conventional ROM. There is also a dedicated XD bus to buffer the ROM data (provided IDE DMA, Independent IDE Interrupt Requests, and several of the general purpose I/O functions are not required). The XD bus can also be externally buffered, which frees pins for other functions. If Flash ROM is used, the CY82C693UB will provide the write-protection through an internal Read Only register bit. Boot-block Flash is supported through hardware strap pins. With boot-block Flash, the boot-block can be write protected and can be used to store recovery code (to rebuild the BIOS from disk, network, etc.). Inverted upper address is normal operating mode. This allows BIOS to begin in non-boot-block memory. If the BIOS is corrupted during an update, the CY82C693UB should be strapped to not invert the upper ROM address bit, thus operating out of the protected boot-block space. Timer/Counter Logic The CY82C693UB contains an 8254-compatible timer/counter. It can be used to generate software time delays, count in binary or BCD, generate interrupts, or generate square-wave patterns. There are three independent, 16-bit counters that can operate in the following six modes: Interrupt
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on terminal count, Hardware retriggerable one-shot, Rate generator, Square wave generator, Software triggered strobe, and Hardware retriggerable strobe. The output of Counter 0 is internal only (can be programmed to generate interrupts). The output of Counter 1 is also internal and works with the AT refresh logic to generate ISA refresh cycles. The output of Counter 2 comes out on the SPKR pin and can be used in any of the modes for a variety of functions, including generating a square wave to an external speaker. DMA Controllers The CY82C693UB contains two 8237-compatible DMA controllers cascaded together to provide seven separate DMA channels. Internally, each controller is a 4-channel DMA device which generates the memory address and control signals necessary to transfer data between an ISA peripheral device and system memory (via the PCI bus). The two DMA controllers (DMACs) are configured to provide four 8-bit DMA channels and three 16-bit DMA channels. Channel 0 of the 16-bit DMAC is used to cascade the two controllers. The DMA controllers support type A, B, and F transfer rates. The DMACs operate in one of three states at all times: IDLE, PROGRAM, or ACTIVE. After the DMACs have been initialized, they remain in IDLE until a DMA request signal is asserted. Once a DMA request is seen, the DMAC that receives the request will enter the ACTIVE state, or if the system is programming the internal configuration registers of a DMAC, it will enter the PROGRAM state. In the IDLE state, the DMACs do nothing aside from sampling the DMA request signals and configuration register decode signals. If a request comes in at the same time as a configuration register access, the register access is executed first. The first thing the DMACs do, after entering the ACTIVE state, is arbitrate for the PCI bus. The CY82C693UB must obtain ownership of the PCI bus regardless of whether the target is on PCI or not. After the PCI bus has been won, the CY82C693UB will issue DMA acknowledge to the highest priority requestor. The DMA transfer is then free to begin. The DMAC is in control of the ISA command signals and IOCHRDY during DMA. The DMACs will enter the PROGRAM state any time a PCI address is decoded to I/O Port 22H. This is the Index Register Port (IRP) for DMAC configuration space. A read or write to Port 23H should immediately follow the write to the IRP. Port 23H is the Data Register Port (DRP).
CY82C693UB
WCR is decremented to zero. This will give the best DMA performance but runs the risk of degrading overall system performance by tying up the PCI bus for long periods. The channel must once again be initialized/autoinitialized after the block transfer has been completed. In Demand Transfer Mode, the DMACs will continue performing transfers until the WCR contains zero or the DMA request is negated. The peripheral will negate its DMA request when it is not ready to transfer data (e.g., an I/O device with its buffer full). When the device is ready to resume the transfer, it must assert its DMA request again and rearbitrate for the ISA and PCI buses. This allows higher priority bus masters to access the buses while the peripheral involved in the DMA cycle is not ready. However, if the device remains ready to transfer data, it can hold its DMA request active and perform back-to-back transfers without arbitrating between transfers. The channel must be initialized/autoinitialized after the block transfer has been completed. Seven DMA channels are available in the CY82C693UB. If additional channels are required, channels may be placed in Cascade Mode. When a channel is in Cascade Mode, external 8237 HOLDREQ and HLDA signals can be routed to the channel's DMA request and DMA acknowledge signals respectively. The arbitration rotating protocol will be maintained. Read, Write, and Verify transfers can be performed in any of the transfer modes. Any channel may also be configured to perform autoinitialization. During autoinitialization, the original values are automatically restored to the Base Address Register and Word Count Register from the Current Address Register and Current Word Count Register when the block transfer is complete (zero in the WCR or an EOP is signalled from the peripheral). The channel will not automatically be masked if autoinitialization is selected. IDE Controller The CY82C693UB contains an integrated, dual-channel PCI to IDE bridge. The IDE controller conforms to ANSI modes 0, 1, 2, 3, and 4 for PIO (Programmed I/O) transfers. Single-word and multi-word DMA transfer modes 0, 1, and 2 are also supported. ATAPI (CD ROM) protocols are allowed with pre-fetching disabled. The controller allows for CHS (Cylinder-Head-Sector) or LBA (Logical Block Address) addressing. Each of the two channels support two devices for a maximum of four IDE devices in the system. The controller allows for PIO pre-fetching, post writing, and DMA PCI mastering in order to increase overall system performance. Real-Time-Clock The CY82C693UB contains 14 bytes for a complete time-of-day clock with alarm, one hundred year calendar, a programmable periodic interrupt generator, and 242 bytes of battery-backed "scratch" RAM. The entire Real-Time-Clock (RTC) remains operational under normal or battery power. A 32 kHz oscillator is integrated as part of the RTC. Only an external crystal and a battery are required to complete the clock circuit.
DMA Controller Transfer Modes
The DMACs can be programmed (on a per channel basis) to transfer data in four modes: Single Transfer Mode, Block Transfer Mode, Demand Transfer Mode, or Cascade Mode. In Single Transfer Mode, the DMACs will transfer one byte/half-word of data (8 or 16 bits) at a time. A DMAC must arbitrate for the PCI bus after each transfer. This ensures that the PCI bus bandwidth will not be completely consumed by an ISA peripheral. The Word Count Register (WCR) will decrement from the block count until zero is reached. If autoinitializing is selected, the channel will reinitialize itself for the next DMA transfer. Otherwise, the channel will be masked until it is initialized. In Block Transfer Mode, the DMACs will hold onto ownership of the PCI bus and continue performing transfers until the
RTC Address Map
The internal RTC contains 256 bytes of battery-backed RAM (14 bytes for clock data and 242 bytes of user-definable RAM). Figure 2 shows the address map.
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Hex Address (Index) Seconds Seconds Alarm Minutes Minutes Alarm Hours Hours Alarm Accessed Using Ports 70H- index and 71H- data Day of the week Numerical date of the month Month Year RegisterA RegisterB RegisterC RegisterD 114 Bytesof User-Defined RAM (Configuration Storage) 128 Bytes of additional UserDefined RAM (Configuration Storage) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 7F 80 FF
CY82C693UB
ing bit will be reset on the second CPU interrupt acknowledge cycle. If AEOI is not selected, it is the responsibility of the software to generate the appropriate end-of-interrupt (EOI) sequence at the end of the interrupt service routine to clear down the interrupt (for example, if a clock interrupt is requested, the system designer may wish the pending interrupt request to remain active through the entire service routine. This allows higher priority interrupts to prematurely force an exit from the clock service routine without causing the loss of the clock interrupt request. If AEOI were programmed, the request to the CPU and the interrupt pending bit would automatically be reset before the clock service routine was entered. If a higher priority interrupt forced the clock routine to be exited, the clock interrupt would be lost.) The interrupt controllers (INTCs) are initialized and programmed using special command words issued by the CPU. Initialization Command Words (ICW1 through ICW4) bring the INTCs to a known state when the system is first powered-up or reset. Operational Command Words (OCW1 through OCW3) setup the various operating modes. The following events occur automatically in the initialization sequence: * The edge sense circuit is reset. Therefore, a request must make a LOW-to-HIGH transition to be detected. If the interrupt request is programmed to be edge-detected, the rising edge must be used (LOW-to-HIGH). High-to-Low transitions will be ignored. * The interrupt mask register is cleared. Interrupts are enabled. * Interrupt Request (IR) 7 is set to the lowest priority on each INTC. * Special Mask Mode is reset. * Status Read is set to return the value in the Interrupt Request Register (IRR). The following options are programmable through the ICWs and OCWs: * Vector Mode operation: The CY82C693UB can generate the vector for an interrupt acknowledge cycle. * The call address interval: The number of cycles to generate an interrupt vector can be chosen to be 4 or 8. * Edge vs. Level Sensitive Interrupt Requests: The interrupt request lines can be programmed to be detected on a rising edge or a fixed level on an individual request basis. * Vector Address Byte: The value can be programmed. * Automatic End-Of-Interrupt: The pending interrupt can be programmed to clear automatically with the acknowledge cycle. If AEOI is not programmed, interrupts must be cleared within the interrupt service routine by the software. * Interrupt Nesting: Interrupt nesting is a programmable option. If interrupt nesting is allowed, interrupts can be asserted within interrupt service routines. * Interrupt Masking: The bits of the Interrupt Mask Register can be set to mask (ignore) certain interrupt requests. * Interrupt Priority: Priority can be programmed to be rotating or fixed. * Polling: When Polling is selected, Interrupt Requests will not issue an interrupt to the CPU. They will merely set bits within the Interrupt Pending Register (IPR). It is the responsibility of the CPU to periodically read (poll) the IPR to determine if an interrupt is pending.
Ports 72H- index and 73H- data
Figure 2. Real-Time-Clock Address Map Update cycles are performed once per second. The update cycle increments the seconds byte and increments the minutes byte on an overflow (followed by hour, day, month, year, etc.). Alarm value comparisons are also made. During the update cycle, data is undefined. However, the CY82C693UB contains an UIP (update in progress) bit to inform the system of updates. If the processor, upon polling the appropriate RTC status register, sees the UIP bit set, an access to the RTC clock data should not be performed. An update-ended interrupt may also be programmed to inform the processor that the update cycle has ended and RTC data is valid.
External RTC Control
To allow for maximum flexibility, an external RTC can be used. The control signals for an external RTC are only used when the internal RTC is disabled. External RTC control is only available as a bond option (separate part number). Please contact Cypress if the use of an external RTC is desired. Interrupt Controllers The CY82C693UB contains two interrupt controllers (INTC1 and INTC2) that provide 82C59A functionality. There are fifteen separate interrupt request inputs (although some of the interrupt requests are only available internally). The two controllers are cascaded to maintain AT interrupt priorities. Interrupt arbitration can be programmed to be rotating or fixed. When interrupt requests come in from the system, the CY82C693UB will store all requests, evaluate the priority, and respond with the appropriate acknowledge vector for the CPU's first interrupt acknowledge cycle. Then, if automatic end-of-interrupt (AEOI) is selected, the internal interrupt pend-
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PCI and IDE interrupts are fully routable internally to independent interrupt levels. The interrupt level of each PCI or IDE interrupt is controlled with configuration registers.
CY82C693UB
CY82C693UB. When the internal PCI arbiter is disabled, the RTC square wave is driven on pin 193.
Splitting GNTBSY
When the PCI arbiter inside the CY82C693UB is enabled, GNTBSY functions as the arbitration signal between the CY82C693UB and the CPU-to-PCI bridge. The CPU-to-PCI bridge is normally granted use of the PCI bus (to reduce the arbitration latency that can hurt CPU performance). The CY82C693UB holds GNTBSY asserted to signal that the bus is granted to the CPU-to-PCI bridge. When another PCI master requests use of the bus, the CY82C693UB takes away the CPU-to-PCI bridge's grant by deasserting GNTBSY for one clock cycle and then placing GNTBSY in a high-impedance state. The CPU-to-PCI bridge must signal busy (by reasserting GNTBSY) in the cycle immediately following the sampling of GNTBSY deasserted if the CPU-to-PCI bridge wishes to retain control of the PCI bus. Otherwise, the CPU-to-PCI bridge must immediately get off of the PCI bus. If GNTBSY is not sampled asserted in the next clock cycle after the original deassertion, the CY82C693UB will grant the PCI bus to the highest priority requesting master. However, if GNTBSY is reasserted by the CPU-to-PCI bridge, the CY82C693UB will not grant the bus to any other PCI masters until GNTBSY is deasserted again by the CPU-to-PCI bridge. Busy must be asserted until the PCI bus is IDLE; otherwise, the CY82C693UB may cause a bus clash. This is because the CY82C693UB will not check for PCI bus IDLE if it sees that busy is deasserted. If the PCI bus has not been signalled busy by the CPU-to-PCI bridge, a maximum of three pending requests will be serviced before GNTBSY is asserted again by the CY82C693UB to grant the bus back to the CPU-to-PCI bridge.
NMI Sources
The CY82C693UB can generate a non-maskable interrupt (NMI) from the following sources: 1. ISA bus IOCHK assertion. 2. PCI SERR assertion. Please refer to port 61H and port 70H description for enable and disable options. Stand-Alone Operation The CY82C693UB was designed to be used as part of the hyperCache chipset or as a stand-alone PCI peripheral controller. The stand-alone option can be used in any PCI system. The system CPU need not be X86-based, provided the PCI specification is followed. Special options were added to the CY82C693UB to make stand-alone operation very flexible. The options include: the ability to disable the integrated PCI arbiter; the ability to split the GNTBSY signaling protocol onto separate GRANT and BUSY signals; the ability to reset both the CY82C693UB and the ISA bus when PCIRST is driven active from an external source; the ability to bypass the FREQACK protocol for DMA transfers into memory; and the ability to decode 32-bit I/O space.
Use With An External PCI Arbiter
When using an external PCI arbiter, GNT3/DISARB (pin 194) should be tied LOW through a 1K Ohm pull-down resistor. This will disable the PCI arbiter that is contained in the CY82C693UB. Pin 191 becomes the PREQ output when the internal arbiter is disabled. PREQ is the primary PCI request signal. In the CY82C693UB, PREQ is used to request the PCI bus for ISA DMA/Master transactions, Bus Master IDE transactions, and USB bus master transactions. PREQ should be connected to one of the request inputs of the external arbiter. Pin 196 becomes the PGNT input when the internal arbiter is disabled. PGNT is the primary PCI grant signal. The external arbiter should assert PGNT to allow the CY82C693UB to take ownership of the PCI bus. PGNT should be connected to the grant output that corresponds to the PREQ request input. If PGNT is asserted to the CY82C693UB without a pending PREQ, the CY82C693UB will follow bus parking rules as specified in the PCI rev. 2.1 specification. Pin 192 becomes the SREQ input when the internal arbiter is disabled. SGNT is the secondary PCI grant signal. Pin 198 becomes the SGNT output when the internal arbiter is disabled. They are used as optional USB arbitration signals. SREQ and SGNT can be programmed to provide separate arbitration for the USB Host Controller. By default, the USB Host Controller requests use of the PCI bus and is granted the bus through PREQ and PGNT. When programmed for separate arbitration (PCI Configuration Registers, Function 0, index=4DH, bit 7), SREQ and SGNT are used to arbitrate for USB, and PREQ and PGNT are used for other bus masters (IDE and ISA DMA). The integrated Real-Time-Clock contains logic to generate a square wave. When the internal PCI arbiter is enabled, the RTC square wave is not available outside of the
PCICLK
GNTBSY
CY82C693UB takes the grant away
CPU-to-PCI bridge signals busy
Figure 3. GNTBSY Arbitration Protocol The GNTBSY protocol is implemented using a single signal. This may cause problems when attempting to interface the CY82C693UB to a CPU-to-PCI bridge that does not support single signal handshaking. Therefore, the CY82C693UB provides the option to separate GNTBSY into a GRANT signal and a BUSY signal. If pin number 179 (SMI/GBSEP) is pulled down through a 1K Ohm resistor, the GNTBSY signalling protocol is split into separate GRANT and BUSY signals. Pin 189 becomes a constantly driving GRANT output. GRANT will be asserted to grant ownership of the PCI bus to the CPU-to-PCI bridge. Pin 163 becomes the BUSY input. BUSY is asserted by the CPU-to-PCI bridge to signal that the PCI bus is busy and should not be granted to any other PCI master.
23
PRELIMINARY
External Reset Control
System reset is normally controlled by the CY82C693UB. When the PWGD signal is deasserted, the CY82C693UB's internal circuitry is reset and CPURST is driven active. PCIRST is placed in high-impedance until the CY82C693UB samples pin 172 HIGH (default with internal pull-up). Then PCIRST is driven active. When PWGD goes active, the CY82C693UB will continue to drive CPURST and PCIRST active for a minimum of 1 ms. If an external reset agent is desired, pin 172 should be pulled to ground through a 1K Ohm resistor. If pin 172 is sampled LOW while PWGD is deasserted, the PCIRST output buffer will be placed in high-impedance. This requires the external agent to drive PCIRST (internal pull-up resistor is used). Once PWGD is asserted, the state of pin 172 will be internally latched into the CY82C693UB. If pin 172 is pulled LOW, PCIRST becomes an input to the CY82C693UB. CPURST will still be driven active for a minimum of 1ms after the assertion of PWGD. After PWGD goes active, the PCIRST input can be driven active by an external agent to reset the internal circuitry of the CY82C693UB. PCIRST will also be inverted and driven out on the CPURST output. ISA bus is also reset by the assertion of PCIRST. PCIRST is a synchronous input (sampled on PCI clock). The minimum active PCIRST must be 80 PCI clock cycles. This insures that AT components inside the CY82C693UB (such as the keyboard controller) are properly reset.
CY82C693UB
When the flush request/acknowledge protocol is bypassed, the RTC interrupt request (IRQ8) may be optionally driven on pin 190. This can be used to provide immediate, non-masked servicing for Real-Time-Clock interrupts. External IRQ8 generation is controlled by PCI configuration register 4DH, bit 5. If bit 5 is "0", IRQ8 from the RTC circuit is only routed internally to the integrated interrupt controller. It is not available on an external CY82C693UB pin. If, however, register 4DH, bit 5 is set to "1", the IRQ8 output from the RTC circuitry is masked to the internal interrupt controller, and IRQ8 is driven on pin 190 of the CY82C693UB. NOTE: If the flush request/acknowledge protocol is not bypassed, FREQACK is driven on pin 190 and if register 4DH, bit 5 is set to "1" the RTC interrupt will only be masked (IRQ8 will not be available externally).
32-Bit I/O Space Decode
As X86 processors only support 64 Kbytes of I/O space, the CY82C693UB's IDE controllers only decode the lower 16 bits of the PCI address. This is sufficient for PC chipset applications. However, for stand-alone operation, it may become necessary to decode 32 address bits (4GB) of I/O space. If PCI configuration register 4DH, bit 4 is set to "1", 32-bits are decoded for I/O space. This effects the format of IDE Base Address Registers in PCI configuration space. When register 4DH, bit 4 is "0", the upper 16-bits of the IDE Base Address Registers (10H, 14H, and 20H) are hardwired to 0000H. When register 4DH, bit 4 is "1", the upper 16-bits are readable and writable. The value written corresponds to the decoded address range (as specified in the PCI specification, revision 2.1).
FREQACK Bypassing
NOTE: Flush Request/Acknowledge signaling must be bypassed if an acknowledge is not sent to the CY82C693UB. Otherwise DMA will not work. The CY82C693UB uses a flush request/acknowledge handshake. The flush request/acknowledge insures that there is a coherent path whenever ISA or IDE DMA masters attempt to access system memory. Data coherency may be violated anytime there is a temporary storage element (such as a post write buffer) that does not monitor transfers of data to provide the most up-to-date copy. In other words, data may be stored in a post-write buffer which is more current than the data in DRAM memory. An ISA/IDE DMA master may get the wrong data if the access is allowed to proceed to main memory "around the post-write buffer." To eliminate a data coherency problem, the CY82C693UB will issue a "flush request" before allowing an ISA/IDE DMA transfer to proceed. Flush request is signalled when the CY82C693UB asserts FREQACK for one PCI clock cycle. The CY82693UB will then deassert FREQACK, place the output in high-impedance, and begin monitoring the input. When all post-write buffers have been emptied, the system controller will assert FREQACK for one PCI clock cycle. This signifies an acknowledge. The CY82C693UB will proceed with the DMA transfer. If a coherent path to memory can be guaranteed without flushing storage elements (i.e., the post-write buffers "snoop" transactions and provide current data, or there are no post-write buffers), the flush request/acknowledge protocol may be bypassed. If PCI configuration register 4DH, bit 6 is set to "1", the flush request will be internally acknowledged. The FREQACK signal (pin 190) will be unused and placed in a high-impedance state.
1 Mbyte ROM Decode
The CY82C693UB can support Extended ROM decoding up to 1 MB at the top of memory space. If bit 3 of the PCI configuration register 4DH is set to "0", 512 KB Extended ROM address decoding is supported (FFF80000H to FFFFFFFFH). If bit 3 is set to "1" 1 MB Extended ROM address decoding is enabled (FFF00000H to FFFFFFFFH). Universal Serial Bus (USB) Host Controller
USB Driver Software Host Controller Driver HCI Host Controller Hardware USB Device USB USB Device Scope of OpenHCI
Figure 4. USB System Domains The CY82C693UB contains a USB host controller. The Host Controller integrates a root hub with two USB ports; therefore, two USB peripheral devices can be connected to the
24
PRELIMINARY
CY82C693UB without any extra logic. An external hub can be connected to any of the two integrated ports in case more devices are required. The Host Controller is connected to system memory via the PCI bus and has bus mastering capability. The USB Host Controller's PCI configuration registers are located in PCI function 3 configuration space in CY82C693UB. The CY82C693UB USB Host Controller fully complies with the USB Open Host Controller Interface (OpenHCI) standard, thus allowing it to be compatible with the available OpenHCI standard software drivers. Figure 4 illustrates different hierarchical domains of a USB system. The domains are the USB Driver (USBD), Host Controller Driver (HCD), Host Controller (HC), and USB Device. The USB Driver and the Host Controller Driver are part of system software, and HCD is typically provided by the operating system. The Host Controller and the USB devices are implemented in hardware. The interface between the software layer (HCD) and the hardware (HC) is called Host Controller Interface (HCI), which is specified in the OpenHCI standard. The basic building block for communication across the interface is called Transfer Descriptor (TD). The Transfer Descriptor contains all necessary information for the Host Controller to process packet transaction with USB devices. The HCD software is responsible for communicating information between the USBD software layer (also typically located in the operating system) and the Host Controller. The HCD receives Transfer Descriptors
CY82C693UB
from the USBD, reformats them as necessary, schedules their execution and enqueues them for the processing by the Host Controller. When the Host Controller finishes the processing of the Transfer Descriptors, the HCD reformats them as necessary, and sends the results back to the USBD. The HCD is also responsible for status and error conditions monitoring. The Host Controller moves data between system memory and devices on the USB by processing Transfer Descriptors enqueued by the HCD and generating transactions on USB. When the Host Controller sends information to a USB device, the data from system memory pointed to by a Transfer Descriptor is converted to the USB serial protocol and transferred on the USB with the appropriate headers. When the Host controller receives information from a USB device, the data is converted from the USB serial protocol and stored in the system memory location pointed to by a Transfer Descriptor. The Host Controller is also responsible for reporting the status of transactions on USB to the HCD. Some other tasks performed by the Host Controller include the maintenance of USB frame generation and the reporting of USB device connection activity to the HCD. For more detailed information on the USB Host Controller, see USB Open Host Controller Interface (OpenHCI) Specification, revision 1.0 available from Microsoft, Compaq and National Semiconductor. For additional information on USB, see USB Specification revision 1.0 from USB Implementers Forum.
CY82C693UB Signal Description
The CY82C693UB signals are divided into eight functional areas: Reset signals, PCI Interface signals, ISA Interface signals, Power Management signals, Keyboard Interface signals, Reset Signals Name PWGD I/O I Description Power Good: This signal is driven active from a combination of the external power supply's power good signal and the external reset switch. This signal is used to qualify initialization signals and reset the internal state of the CY82C693UB. CPU Reset: This signal resets the CPU and the ISA bus. PCI Reset: This signal functions as the PCI bus reset. During normal operation, this signal is an output only (used by the CY82C693UB to reset PCI bus residents). If pin 172 is pulled LOW through a 1K Ohm resistor, PCIRST becomes an input that is used to initiate a CY82C693UB reset and an ISA reset. See the text description for Stand-Alone Operation. This signal will power up in a high-impedance state with an internal pull-up resistor. When pin 172 is sampled, this signal will either begin driving (pin 172 HIGH) or remain a high-Z input (pin 172 LOW). CPU Initialization: This signal is used to reset the core of the CPU without disturbing the state of internal caches or write-buffers. This signal can be used to switch the processor from protected mode to real mode. IDE Interface signals, USB interface signals, and Miscellaneous signals.
CPURST PCIRST
O O
INIT
O
PCI Interface Signals Name AD[31:0] PCICLK I/O I/O I Description PCI Address/Data Bus: Multiplexed bidirectional address/data lines on the PCI bus. The CY82C693UB either drives or samples these lines during PCI cycles. PCI Clock: PCI Clock Input. This signal is used to synchronize the CY82C693UB to the PCI bus. The clock must be within the range 25 MHz to 33 MHz.
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PRELIMINARY
PCI Interface Signals (continued) Name C/BE[3:0] I/O I/O Description
CY82C693UB
PCI Command & Byte Enables: C/BE[3:0] are driven by the current bus master during the address phase to define the transaction and during the data phase as the byte enables. These signals are outputs when the CY82C693UB is a master and inputs when the CY82C693UB is a slave. Cycle Frame: Driven by the current bus master to indicate the start and duration of a transaction. Initiator Ready: The assertion of IRDY indicates the current bus master's ability to complete the current data phase of the transaction. Used in conjunction with TRDY from the target. Target Ready: The assertion of TRDY indicates the current target's ability to complete the current data phase of the transaction. Works in conjunction with IRDY from the master. Device Select: Indicates that a PCI device has decoded that it is the target of the transaction. The target has three options for decoding: fast decoding, medium decoding, or slow decoding. The CY82C693UB will sample DEVSEL, and if it is not asserted by a target within the timeout period, will assert DEVSEL to claim the cycle. Parity: An even parity bit across AD[31:0] and C/BE[3:0]. As a master the CY82C691 generates even parity on PCI write cycles. On read cycles, the CY82C693UB checks parity by sampling PAR. Stop: Indicates that the current target is requesting the master to stop the current transaction. STOP is used in conjunction with DEVSEL and TRDY to indicate disconnect, target abort, and retry cycles. System Error: System error may be asserted by any agent for reporting address parity errors or any other types of errors besides data parity. SERR will cause the CY82C693UB to assert NMI to the processor. PCI ID Select: This signal should be connected to a unique PCI address. It is used to select the CY82C693UB during PCI configuration cycles. PCI Interrupt Requests: These signals allow PCI peripherals to interrupt the processor. CY82C691 Busy/Grant: This signal is the PCI arbitration signal used by the CY82C691. The CY82C691 is the default owner of the PCI bus. In the default state, the CY82C693UB will actively drive this signal asserted (LOW). If another external master requests the bus, the CY82C693UB will deassert this signal for a single clock cycle and then let the signal float. If the CY82C691 asserts this signal within two clock cycles after this signal is seen deasserted, this signal becomes BUSY to the central arbiter. BUSY tells the CY82C693UB that the CY82C691 owns the PCI bus. The CY82C693UB will not grant the PCI bus to any other PCI master until BUSY is deasserted by the CY82C691. When no requests are pending on the PCI bus, this signal reverts to 691 GRANT and is driven active (LOW) to allow the CY82C691 to take possession of the PCI bus. If pin 179 is strapped LOW through a 1K Ohm resistor, this signal becomes a dedicated GRANT output. GRANT is constantly driven by the CY82C693UB. CY82C691 Flush Request/Acknowledge or RTC Interrupt Request: This signal is used to facilitate DMA transfers. The CY82C693UB will drive this signal LOW for one clock cycle to request the CY82C691 flush its internal buffers before a DMA transfer. Once the CY82C691 has flushed its buffers, it will drive this signal for one clock cycle to acknowledge the flush. The CY82C693UB is then free to perform its DMA transfer. If PCI configuration register 4DH, bit 6 is set to "1", all flush requests are immediately acknowledged inside the CY82C693UB. This signal becomes high-impedance. If PCI configuration register 4DH, bit 5 is also set to "1", the Real-Time-Clock interrupt request (IRQ8) is masked to the internal interrupt controller and driven out on this pin. PCI Bus Requests: These signals are connected to the individual bus requests from each PCI peripheral. When a combination of the bus requests is asserted, the CY82C693UB will resolve the priority and give the grant to the highest priority master. If the internal PCI arbiter is disabled (by strapping pin 194 LOW through a 1K Ohm resistor), these signals become UNUSED.
FRAME IRDY
I/O I/O
TRDY
I/O
DEVSEL
I/O
PAR
I/O
STOP
I/O
SERR
I/O
IDSEL INTA/B/C/D GNTBSY/GRANT
I I I/O
FREQACK/IRQ8
I/O
REQ[3:2]
I
26
PRELIMINARY
PCI Interface Signals (continued) Name REQ[1]/SGNT I/O I/O Description
CY82C693UB
PCI Bus Request 1/ Secondary PCI Grant: If the internal PCI arbiter is enabled, this signal is connected to the individual bus request from PCI peripheral number 1. When a combination of the bus requests is asserted, the CY82C693UB will resolve the priority and give the grant to the highest priority master. If the internal PCI arbiter is disabled (by strapping pin 194 LOW through a 1K Ohm resistor), this signal becomes a RESERVED input. In the CY82C693UBU this signal will optionally become the secondary grant input to grant the PCI bus to the USB Host Controller. PCI Bus Request 0/ Primary PCI Grant: If the internal PCI arbiter is enabled, this signal is connected to the individual bus request from PCI peripheral number 0. When a combination of the bus requests is asserted, the CY82C693UB will resolve the priority and give the grant to the highest priority master. If the internal PCI arbiter is disabled (by strapping pin 194 LOW through a 1K Ohm resistor), this signal becomes the PGNT input. PGNT is driven active by the external PCI arbiter to grant ownership of the PCI bus to the CY82C693UB. PCI Bus Grant 3/ PCI Arbiter Disable: This signal is connected to bus grant of PCI peripheral #3. When a combination of the bus requests is asserted, the CY82C693UB will resolve the priority and assert grant to the highest priority master. During power-up, this signal acts as a strapping option to disable the PCI arbiter within the CY82C693UB. An external PCI arbiter must be provided. When the internal arbiter is disabled, several other signals change function to provide the request/grant signals from the CY82C693UB to the external arbiter. PCI Bus Grant 2/ RTC Square Wave Output: This signal is connected to bus grant of PCI peripheral #3. When a combination of the bus requests is asserted, the CY82C693UB will resolve the priority and assert grant to the highest priority master. If the internal PCI arbiter is disabled (pin 194 strapped LOW during power up), this pin drives the output of the square wave generator in the Real-Time-Clock. PCI Bus Grant 1/ Secondary PCI Request: If the internal PCI arbiter is enabled, this signal is connected to the individual bus grant to PCI peripheral number 1. When a combination of the PCI bus requests is asserted, the CY82C693UB will resolve the priority and assert grant to the highest priority master. If the internal PCI arbiter is disabled (by strapping pin 194 LOW through a 1K Ohm resistor), this signal becomes a RESERVED output. In the CY82C693UBU this signal will optionally become the secondary request output to request ownership of the PCI bus for the USB Host Controller. PCI Bus Grant 0/ Primary PCI Request: If the internal PCI arbiter is enabled, this signal is connected to the individual bus grant to PCI peripheral number 0. When a combination of the bus requests is asserted, the CY82C693UB will resolve the priority and assert grant to the highest priority master. If the internal PCI arbiter is disabled (by strapping pin 194 LOW through a 1K Ohm resistor), this signal becomes the PREQ output. PREQ is driven active by the CY82C693UB to request ownership of the PCI bus for ISA or IDE DMA and USB Host Controller (if no separate arbitration used) cycles.
REQ[0]/PGNT
I/O
GNT[3]/DISARB
I/O
GNT[2]/SQWV
O
GNT[1]/SREQ
O
GNT[0]/PREQ
O
ISA Interface Signals Name SA[19:4]/ IDE[15:0] SA[3:0] SD[15:0] XD7/IDEIRQ0 GPIO0 I/O I/O I/O I/O I/O Description ISA Address Bus/PCI IDE Data Bus: These signals provide most of the address for the ISA bus as well as the data path for IDE. ISA Address: These signals provide the rest of the ISA address. System Data Bus: These signals connect directly to the ISA data bus. XD Bus, Bit 7/Programmable Interrupt Request 0/General Purpose I/O 0: If zero TTL is desired for XD bus support (BIOS ROM data, external keyboard controller data, and external RTC data), this is bit 7 of the data bus. Otherwise, this is user-selectable to provide support for a Programmable Interrupt Request or a general purpose I/O. As a GPIO, this signal can either reflect the contents of an internal register bit (output) or set an internal register bit to the value driven on the line (input).
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PRELIMINARY
ISA Interface Signals (continued) Name XD6/IDEIRQ1 GPIO1/BUSY I/O I/O Description
CY82C693UB
XD Bus, Bit 6/Programmable Interrupt Request 1/General Purpose I/O 1/PCI Bus Busy: If zero TTL is desired for XD bus support (BIOS ROM data, external keyboard controller data, and external RTC data), this is bit 6 of the data bus. Otherwise, this is user-selectable to provide support for a Programmable Interrupt Request or a general purpose I/O. As a GPIO, this signal can either reflect the contents of an internal register bit (output) or set an internal register bit to the value driven on the line (input). If pin 179 is strapped LOW during power-up (GNTBSY split), this signal becomes the BUSY input. BUSY is asserted by the CPU-to-PCI bridge to tell the PCI arbiter in the CY82C693UB that the PCI bus is currently busy and may not be granted to any other PCI master. XD Bus, Bit 5/IDE DMA Request 0: If zero TTL is desired for XD bus support (BIOS ROM data, external keyboard controller data, and external RTC data), this is bit 5 of the data bus. Otherwise, this is user-selectable to provide support for IDE DMA.. For IDE DMA support, this signal is DMA request 0 (primary IDE channel DMA request). XD Bus, Bit 4/IDE DMA Acknowledge 0: If zero TTL is desired for XD bus support (BIOS ROM data, external keyboard controller data, and external RTC data), this is bit 4 of the data bus. Otherwise, this is user-selectable to provide support for IDE DMA. For IDE DMA support, this signal is DMA acknowledge 0 (primary IDE channel DMA acknowledge).. XD Bus, Bit 3/IDE DMA Request 1: If zero TTL is desired for XD bus support (BIOS ROM data, external keyboard controller data, and external RTC data), this is bit 3 of the data bus. Otherwise, this is user-selectable to provide support for IDE DMA. For IDE DMA support, this signal is DMA request 1 (secondary IDE channel DMA request). XD Bus, Bit 2/IDE DMA Acknowledge 1: If zero TTL is desired for XD bus support (BIOS ROM data, external keyboard controller data, and external RTC data), this is bit 2 of the data bus. Otherwise, this is user-selectable to provide support for IDE DMA or a general purpose I/O. For IDE DMA support, this signal is DMA acknowledge 1 (secondary IDE channel DMA acknowledge). As a GPIO, this signal can either reflect the contents of an internal register bit (output) or set an internal register bit to the value driven on the line (input). XD Bus, Bit 1/External XD Bus Buffer Enable: If zero TTL is desired for XD bus support (BIOS ROM data, external keyboard controller data, and external RTC data), this is bit 1 of the data bus. Otherwise, this pin provides the enable for a buffer between XD[7:0] and SD[7:0]. XD Bus, Bit 0/External XD Bus Direction Control: If zero TTL is desired for XD bus support (BIOS ROM data, external keyboard controller data, and external RTC data), this is bit 0 of the data bus. Otherwise, this pin provides the direction control for a buffer between XD[7:0] and SD[7:0]. Latched Address 23/ IDE Chip Select0: This signal connects to LA23 on the ISA bus and is used to provide access up to 16 MB. During IDE accesses, this signal provides the chip select 0 for the primary channel. Latched Address 22/ IDE Chip Select1: This signal connects to LA22 on the ISA bus and is used to provide access up to 16 MB. During IDE accesses, this signal provides the chip select 1 for the primary channel. Latched Address 21/ Secondary IDE Chip Select0: This signal connects to LA21 on the ISA bus and is used to provide access up to 16 MB. During IDE accesses, this signal provides the chip select 0 for the secondary channel. Latched Address 20/ Secondary IDE Chip Select1: This signal connects to LA20 on the ISA bus and is used to provide access up to 16 MB. During IDE accesses, this signal provides the chip select 1 for the secondary channel. Latched Address 19 Through 17/ PCI IDE Register Select Address 2 Through 0: These signals connect to LA19 through LA17 on the ISA bus and are used to provide access up to 16 MB. During IDE accesses, these signals provide the register select (or address) to the IDE connectors.
XD5/IREQ0
I/O
XD4/IACK0
I/O
XD3/IREQ1
I/O
XD2/IACK1
I/O
XD1/XDEN
I/O
XD0/XDIR
I/O
LA23/IDECS0
I/O
LA22/IDECS1
I/O
LA21/SIDECS0
I/O
LA20/SIDECS1
I/O
LA[19:17]/ IDEA[2:0]
I/O
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PRELIMINARY
ISA Interface Signals (continued) Name IRQ1/KBCLK I/O I/O Description
CY82C693UB
Keyboard Clock/Interrupt Request 1: This signal is the keyboard clock connected to the keyboard connector if the internal keyboard controller is used. Otherwise, it provides IRQ1 (the keyboard controller interrupt input) if an external keyboard controller is desired. Interrupt Request Inputs: These signals provide interrupt requests for CPU interrupters. Mouse Clock/Interrupt Request 12: This signal is the mouse clock connected to the mouse connector if the internal keyboard controller is used. Otherwise, it provides IRQ12 (the mouse controller interrupt input) if an external keyboard controller is desired. Power Strobe/Interrupt Request 8: If the internal Real-Time-Clock (RTC) is used, this is the power strobe input. If an external RTC is desired, this is interrupt request 8 (traditionally the RTC interrupt). CPU Interrupt/Keyboard AT Mode: This is the INTR (interrupt request) signal that is connected directly to the CPU's INTR pin. When interrupt requests come in to the CY82C693UB, it will assert INTR to the CPU. On power-up this signal should be pulled-down through a 1K Ohm resistor to ground if PS/2 keyboard support is desired. Non-maskable CPU Interrupt: This is the NMI (non-maskable interrupt request) signal that is connected directly to the CPU's NMI pin. When the CY82C693UB detects a fatal error (such as a PCI parity error), it will assert NMI to the CPU. AT Clock: This signal can be used to provide the system ISA (AT) bus clock. It can be internally programmed to generate different ISA frequencies. Bus Address Latch Enable: This signal is the ISA BALE signal used by peripherals to latch the cycle address, AEN, and SBHE. ISA DMA/Master Request Input 7/General Purpose I/O 8/USB Host Controller SMIACT Input: This signal is used by external ISA peripherals to request mastership of the ISA bus for DMA or ISA MASTER cycles. They can be programmed to be GPIO if the DREQ signals are connected to an external ('157 type) TTL device to time multiplex (using the ATCLK as the selector signal) the DMA requests onto DRQ[3:0]. When USB Host Controller is enabled, this signal becomes SMI Active input, which is used to mask the SMI output while in SMM. Pull-up is required for SMIACT if unused. ISA DMA/Master Request Input 6/General Purpose I/O 7/USB Host Controller OVRCUR input: This signal is used by external ISA peripherals to request mastership of the ISA bus for DMA or ISA MASTER cycles. They can be programmed to be GPIO if the DREQ signals are connected to an external ('157 type) TTL device to time multiplex (using the ATCLK as the selector signal) the DMA requests onto DRQ[3:0]. When USB Host Controller is enabled, this signal becomes Over-current Detection input. OVRCUR is asserted when downstream ports exceed their current allocation. This input causes power to be disabled and is reported through the hub and port status register. Pull-up required for OVRCUR if unused. ISA DMA/Master Request Input 5/General Purpose I/O 6/USB Host Controller PWREN output: This signal is used by external ISA peripherals to request mastership of the ISA bus for DMA or ISA MASTER cycles. They can be programmed to be GPIO if the DREQ signals are connected to an external ('157 type) TTL device to time multiplex (using the ATCLK as the selector signal) the DMA requests onto DRQ[3:0]. When USB Host Controller is enabled, this signal becomes Port Power Enable output. The global power to USB ports is controlled by this signal. If NoPowerSwitching in HcRhDescriptorA (USB Host Controller Operational Register) is set, this signal is always active.
IRQ[15:14], IRQ[11:9] IRQ[7:3] IRQ12/MSCLK
I
I/O
IRQ8/PSRSTB
I
INTR/KBATMODE
I/O
NMI
O
ATCLK ALE DRQ7/GPIO8/ SMIACT
O I/O I/O
DRQ6/GPIO7/ OVRCUR
I/O
DRQ5/GPIO6/ PWREN
I/O
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PRELIMINARY
ISA Interface Signals (continued) Name DRQ[3:0] I/O I Description
CY82C693UB
ISA DMA/Master Request Inputs: These signals are used by external ISA peripherals to request mastership of the ISA bus for DMA or ISA MASTER cycles. These signals can also be programmed to be time multiplexed (based on ATCLK) to free DRQ[7:5] for GPIO. If they are multiplexed, the multiplexed version of DREQ3 and DREQ7 (with DREQ3 passed through when ATCLK is LOW) should be connected to the DRQ3 pin, the multiplexed version of DREQ1 and DREQ6 (with DREQ1 active when ATCLK is LOW) should be tied to the DRQ1 pin, the multiplexed version of DREQ0 and DREQ5 (with DREQ0 active when ATCLK is LOW) should be tied to the DRQ0 pin, and DREQ2 should be tied directly to the DRQ2 pin. ISA DMA/Master 0 Acknowledge/Test Mode Enable: This signal is used by the CY82C693UB to grant ISA bus mastership to external ISA peripherals for DMA or ISA MASTER cycles. At power-up, this pin should be pulled-down through a 1K Ohm resistor to enable test mode. For normal operation, this pin should not be pulled-down. This signal can also be programmed to generate a DMA acknowledge code that can be sent to the Input A input of a '138 type TTL 1 of 8 decoder. By programming this input to generate a coded output, DACK[7:5] are free to become GPIO. ISA DMA/Master 1 Acknowledge Input/Test Mode Select 0: This signal is used by the CY82C693UB to grant ISA bus mastership to external ISA peripherals for DMA or ISA MASTER cycles. At power-up, this pin should be pulled-down through a 1K Ohm resistor or not pulled-down to select between the different test modes. This signal can also be programmed to generate a DMA acknowledge code that can be sent to the Input B input of a '138 type TTL 1 of 8 decoder. By programming this input to generate a coded output, DACK[7:5] are free to become GPIO. ISA DMA/Master 2 Acknowledge/Test Mode Select 1: This signal is used by the CY82C693UB to grant ISA bus mastership to external ISA peripherals for DMA or ISA MASTER cycles. At power-up, this pin should be pulled-down through a 1K Ohm resistor not pulled-down to select between the different test modes. This signal can also be programmed to generate a DMA acknowledge code that can be sent to the Input C input of a '138 type TTL 1 of 8 decoder. By programming this input to generate a coded output, DACK[7:5] are free to become GPIO. ISA DMA/Master 3 Acknowledge Input/Display Type Select: This signal is used by the CY82C693UB to grant ISA bus mastership to external ISA peripherals for DMA or ISA MASTER cycles. At power-up, this pin should be pulled-down through a 1K Ohm resistor or left floating to select between CGA and Monochrome monitors (acts as the keyboard controller Mono/Color pin). This signal can also be programmed to generate an enable to a '138 type TTL 1 of 8 decoder. By programming this input to generate the enable, glitches are prevented when the code signals switch. ISA DMA/Master 5 Acknowledge Input/Internal Keyboard Controller Enable/General Purpose I/O 9: This signal is used by the CY82C693UB to grant ISA bus mastership to external ISA peripherals for DMA or ISA MASTER cycles. At power-up, this pin should be pulled-down through a 1K Ohm resistor to disable the internal keyboard controller if an external keyboard controller is desired. This signal can be used as a GPIO if DACK[3:0] are programmed to connect to an external '138 type TTL 1 of 8 decoder. ISA DMA/Master 6 Acknowledge Input/Internal Real Time Clock Enable/General Purpose I/O 10: This signal is used by the CY82C693UB to grant ISA bus mastership to external ISA peripherals for DMA or ISA MASTER cycles. At power-up, this pin should be pulled-down through a 1K Ohm resistor to disable the internal RTC if an external RTC is desired. NOTE: external RTC support is available through bond option (separate part number). Please contact Cypress if the use of an external RTC is desired. This signal can be used as a GPIO if DACK[3:0] are programmed to connect to an external '138 type TTL 1 of 8 decoder.
DACK0/TSTM
I/O
DACK1/TSTM0
I/O
DACK2/TSTM1
I/O
DACK3/DISPSEL
I/O
DACK5/KBSEL /GPIO9
I/O
DACK6/RTCSEL /GPIO10
I/O
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PRELIMINARY
ISA Interface Signals (continued) Name DACK7/EXTBUF /GPIO11 I/O I/O Description
CY82C693UB
ISA DMA/Master 7 Acknowledged Input/Internal IDE Controller Enable/General Purpose I/O 11: This signal is used by the CY82C693UB to grant ISA bus mastership to external ISA peripherals for DMA or ISA MASTER cycles. At power-up, this pin should be pulled-down through a 1K Ohm resistor to enable a direct connection to the XD bus. If IDE Bus Master functions are required, the pin should not be pulled down and an external XD bus buffer should be used. This signal can be used as a GPIO if DACK[3:0] are programmed to connect to an external '138 type TTL 1 of 8 decoder. AT Refresh: Driven when an ISA refresh cycle is in progress. As an input, this signal will force a refresh cycle to be initiated. Speaker Output: This signal is the output of counter 2 in the timer/counter logic. It can be used to drive a speaker. End of Process: This signal is driven by the CY82C693UB to signal the end of a block transfer during a DMA cycle. Ignore Numerical Error: This signal is driven by the CY82C693UB to the CPU and should be connected to the CPU's IGNNE pin. When this signal is asserted, the processor will ignore numerical errors and continue executing non-control, floating-point instructions. At power-up, this signal acts as ROMS1. ROMS1 is used in conjunction with ROMS0 (GTA20) and ROMMODE (ROMCS) to implement boot-block Flash recovery straps. The strapping is defined as follows: ROMMODE ROMS0 ROMS1 Result 1 X X No ROM address bits are inverted. (EPROM or bootblock recovery mode). ROM address bit 16 is inverted (Normal operation w/ 16Kx8 boot-block Flash) ROM address bit 17 is inverted (Normal operation w/ 32Kx8 boot-block Flash) ROM address bit 18 is inverted (Normal operation with 64Kx8 boot-block Flash) ROM address bit 15 is inverted (Normal operation with 8Kx8 boot-block Flash)
REFSH SPKR EOP IGNNE/ROMS1
I/O O O I/O
0
1
1
0
1
1
0
0
1
0
0
0
FERR
I
Floating Point Error: This signal from the processor causes an IRQ13 from the CY82C693UB to occur.
31
PRELIMINARY
ISA Interface Signals (continued) Name GTA20/ROMS0 I/O I/O Description
CY82C693UB
Gate A20: This signal forces memory to wrap-around 1 MB. It is implemented as a fast gate A20. At power-up, this signal acts as ROMS0. ROMS0 is used in conjunction with ROMS1 (IGNNE) and ROMMODE (ROMCS) to implement boot-block Flash recovery straps. The strapping is defined as follows: ROMMODE ROMS0 ROMS1 Result 1 X X No ROM address bits are inverted. (EPROM or bootblock recovery mode) ROM address bit 16 is inverted (Normal operation w/ 16Kx8 boot-block Flash) ROM address bit 17 is inverted (Normal operation with 32Kx8 boot-block Flash) ROM address bit 18 is inverted (Normal operation with 64Kx8 boot-block Flash) ROM address bit 15 is inverted (Normal operation with 8Kx8 boot-block Flash)
0
1
1
0
1
0
0
0
1
0
0
0
X2/RTCRD
O
RTC Crystal Out/RTC Output Enable: If the integrated RTC is used, this signal is the 32.768-kHz crystal output. If an external RTC is desired, this signal is the RTC output enable. NOTE: external RTC is a bond option only. This input must be open if a crystal oscillator with TTL outputs are used to signal 32.768 KHz. The 32.768 KHz oscillator output should be connected to X1. RTC Crystal In/RTC Write Enable: If the integrated RTC is used, this signal is the 32.768-KHz crystal input. If an external RTC is desired, this signal is the RTC write enable.NOTE: external RTC is a bond option only. A TTL level 32.768 KHz oscillator may be connected to this pin. If a oscillator is connected to this pin, X2 should be left open. 16-Bit I/O Chip Select: This signal is driven active by any ISA I/O target that can support 16-bit accesses. 16-Bit Memory Chip Select: This signal is driven active by any ISA MEMORY target that can support 16-bit accesses. During ISA Master cycles, the CY82C693UB will drive this signal. System Byte High Enable: This signal is driven active by the current ISA bus master to indicate that valid data resides on SD[15:8]. ISA Memory Read Command Signal: This signal is driven by the current ISA bus owner to request a memory resource to drive data onto the bus during a cycle. ISA Memory Write Command Signal: This signal is driven by the current ISA bus owner to request a memory resource to accept data presented on the bus during a cycle. ISA I/O Read Command Signal: This signal is driven by the current ISA bus owner to request an I/O resource to drive data onto the bus during a cycle. ISA I/O Write Command Signal: This signal is driven by the current ISA bus owner to request an I/O resource to accept data presented on the bus during a cycle. ISA System Memory Read Command Signal: This signal is driven by the current ISA bus owner to request a memory resource to drive data onto the bus during a cycle. This signal is only active within the first 1 MB of memory space. ISA System Memory Write Command Signal: This signal is driven by the current ISA bus owner to request a memory resource to accept data presented on the bus during a cycle. This signal is only active within the first 1 MB of memory space.
X1/RTCWT
I/O
IOCS16 MCS16
I I/O
SBHE MRD MWT IOR IOW SMEMR
I/O I/O I/O I/O I/O I/O
SMEMW
I/O
32
PRELIMINARY
ISA Interface Signals (continued) Name OSC I/O I Description
CY82C693UB
Oscillator Input: This signal is the 14.318-MHz reference clock input, used by the timer and DMA controller. This reference clock must be connected, because it is used to sample strap options. Zero Wait State Input: When this signal is driven by an ISA peripheral, the CY82C693UB will shorten the ISA cycle to zero wait states and ignore IOCHRDY. Address Enable: This signal is driven active by the CY82C693UB as an indication to the I/O resources not to respond to the address and I/O Command signal lines during a DMA cycle. I/O Channel Ready: When deasserted, this signal indicates to the ISA bus owner that additional cycle time is required to complete the transaction. Used to add ISA wait states. I/O Channel Check: This signal is driven active if the system detects an ISA bus parity error.
0WS AEN
I O
IOCHRDY
I/O
IOCHK
I
Power Management Signals Name SMI/GBSEP I/O I/O Description System Management Interrupt/GNTBSY Separate: Used by the CY82C693UB to send the highest-level, process-transparent interrupt to the CPU. At power up, this signal is sampled to determine the grant/busy protocol for CPU-to-PCI bridge arbitration. If this signal is left floating (sampled HIGH), GNTBSY arbitration is performed on a single signal. If this signal is strapped LOW through a 1K Ohm resistor, GRANT is driven out on pin 189 and BUSY is sampled on pin number 163. CPU Stop Clock/External PCI Reset Generator Present: This signal is used to stop the clock to the CPU's core to reduce power-consumption during idle periods. At power up, this signal is sampled to determine the source of PCI reset in the system. If this signal is left floating (sampled HIGH), PCI reset and CPU/ISA reset signals are output from the CY82C693UB. They are asserted when PWGD is sampled deasserted and will be driven asserted for a minimum period of 1ms after PWGD goes active. If STOPCLK/RSTCHG is strapped LOW through an external 1K Ohm resistor, PCIRST becomes an input. When PCIRST is sampled asserted, all registers/FIFOs/state within the CY82C693UB are cleared to a known reset state. CPURST is driven active for the duration of PCIRST active. There is no minimum guaranteed assertion time for CPURST in this mode. External Power Management Input: This signal is used to force the assertion of an SMI by an external source (e.g., a power-down switch).
STOPCLK/ RSTCHG
I/O
EPMI
I
Keyboard Interface Signals Name KBDATA KBCS/KYLCK I/O I/O I/O Description Keyboard Data: This is the serial data line to/from the keyboard connector. Keyboard Chip Select/Key Lock Input: This signal is the key lock input to lock the keyboard (for system security) if the internal keyboard controller is used. If an external keyboard controller is desired, this is the keyboard controller chip select. Mouse Data/External Keyboard Controller Clock Output: If the internal keyboard controller is used, this is the serial mouse data line to/from the keyboard connector. If an external keyboard controller is desired, this signal drives the state machine clock input (normally ATCLK) of the external keyboard controller.
MSDATA/KBDCLK
I/O
IDE Interface Signals Name IDEIOR IDEIOW IDEIOCS16 I/O O O I Description IDE I/O Read: This signal directly drives the IDEIOR signal on the IDE connector. IDE I/O Write: This signal directly drives the IDEIOW signal on the IDE connector. IDE I/O Chip Select 16: This signal directly drives the IDEIOCS16 signal on the IDE connector. Determines whether the IDE transaction is 8 bits or 16 bits wide.
33
PRELIMINARY
IDE Interface Signals (continued) Name BLKIDE I/O O Description
CY82C693UB
Block IDE: This signal may be used in conjunction with an external Quad OR gate to block the IDE chip selects to the IDE drives during ISA transfers. This prevents older IDE devices from hanging if multiple IDE chip selects are asserted. Newer drives will not have a problem because IDE chip selects will only be sampled when an IDE COMMAND signal (IDEIOW or IDEIOR) is asserted.
USB Interface Signals Name USB_CLK USB_D1+, USB_D1- USB_D2+, USB_D2- I/O I I/O I/O Description USB 48MHz Clock Input USB port 1: This signal pair comprises the differential signal for USB port 1. USB port 2: this signal pair comprises the differential signal for USB port 2.
Miscellaneous Signals Name ROMCS /ROMMODE I/O I/O Description System ROM Chip Select: This signal is used to enable the on-board BIOS ROM. At power-up, this signal acts as ROMMODE. ROMMODE is used in conjunction with ROMS0 (GTA20) and ROMS1 (IGNNE) to implement boot-block Flash recovery straps. The strapping is defined as follows: ROMMODE ROMS0 ROMS1 Result 1 X X No ROM address bits are inverted. (EPROM or bootblock recovery mode). ROM address bit 16 is inverted (Normal operation w/ 16Kx8 boot-block Flash) ROM address bit 17 is inverted (Normal operation with 32Kx8 boot-block Flash) ROM address bit 18 is inverted (Normal operation with 64Kx8 boot-block Flash) ROM address bit 15 is inverted (Normal operation with 8Kx8 boot-block Flash)
0
1
1
0
1
0
0
0
1
0
0
0
VBATT
I
Battery Backup Power: This pin should be connected directly to a battery-driven power source. Used to retain and maintain RTC functionality when the main power supply is disconnected. VCC: These are the +5V power supply pins for the device. They should be maintained within the proper operating limits. 3.3-Volt VCC: This is the +3.3V power supply pin for the device. It should be maintained within the proper operating limits. GROUND: These are the 0V power supply pins for the device. They should be maintained within the proper operating limits.
+5V +3.3V GND
I I I
34
PRELIMINARY
hyperCache Memory and I/O Map
The hyperCache memory and I/O mapping diagrams are shown in this section. The detailed description of I/O registers shown in the I/O map can be found in the next sections.
CY82C693UB
Alias to Conventional System BIOS Alias to Extended System BIOS Extended System BIOS (Up to 1 MB)
FFFFFFFF FFFF0000 FFFEFFFF FFFE0000 FFFDFFFF FFF00000 FFEFFFFF
PCI Memory Space
Top of DRAM Memory
Extended System Memory
00100000 000FFFFF
Conventional System BIOS
000F0000 000EFFFF
Extended System BIOS
000E0000 000DFFFF
Peripheral BIOS (Block D)
000D0000 000CFFFF
Peripheral BIOS (Block C)
000C0000 000BFFFF
Video Memory (Block B)
000B0000 000AFFFF
Video Memory (Block A)
000A0000 0009FFFF
Extended System Memory
00010000 0000FFFF
Conventional System Memory
00000000
Figure 5. hyperCache Memory Map Diagram
35
PRELIMINARY
CY82C693UB
FFFFFFFF
Not Used by x86 Microprocessors
00010000 0000FFFF
User Defined I/O Space DMA Controller Extended Mode and High Page Registers DMA Controller 2 Registers APM Control/Status Registers Interrupt Controller 2 Registers PS/2 Reset Control DMA Page Registers Real Time Clock Registers Keyboard Control & Port B Registers Timer/Counter Config. Registers Chipset Configuration Data Port Chipset Configuration Address Port Interrupt Controller 1 Registers DMA Controller 1 Registers
000004D7 000004D6 0000040B 000000CF 000000C0 000000B3 000000B2 000000A1 000000A0
00000092 0000008B 00000080 00000073 00000070 00000064 00000060 00000043 00000040
00000023 00000022 00000021 00000020 0000001F 00000000
Figure 6. hyperCache CY82C693UB I/O Map Diagram
36
PRELIMINARY
CY82C693UB Control Registers
The control registers for the CY82C693UB are defined in this section. The registers can be accessed through I/O Ports 22H and 23H (PCI I/O Reads or Writes to address 22H and 23H). To access each register, the user must first write the index
CY82C693UB
number of the register into Port 22, which forces the internal decoding logic to point to the selected register. Data can be accessed by then reading/writing to/from Port 23.
.
Register 1: Peripheral Configuration Register #1 (Read/Write) -- Index=01H Bit 7:6 Function I/O Wait State Control: 00: 1 Wait State 01: 2 Wait States 10: 3 Wait States 11: 4 Wait States This register field is used to aid in ISA compatibility. ISA cards that cannot respond fast enough may require wait states to be inserted into each ISA cycle. Wait states are inserted by the deassertion of the IOCHRDY signal. IOCHRDY will remain deasserted for the number of wait states (AT clock cycles) programmed into this register field. 16-bit DMA Wait State Control 00: 1 Wait State 01: 2 Wait States 10: 3 Wait States 11: 4 Wait States This bit field allows wait state control on 16-bit accesses. Wait states are inserted by the deassertion of the IOCHRDY signal. IOCHRDY will remain deasserted for the number of wait states (AT clock cycles) programmed into this register field. 8-bit DMA Wait State Control 00: 1 Wait State 01: 2 Wait States 10: 3 Wait States 11: 4 Wait States This bit field allows wait state control on 8-bit accesses. Wait states are inserted by the deassertion of the IOCHRDY signal. IOCHRDY will remain deasserted for the number of wait states (AT clock cycles) programmed into this register field. MEMR Leading Edge Delay Control: 0: 1 DMA clock delay 1: No delay This bit allows the assertion of the MEMR signal to be delayed during DMA transactions. Normally MEMR is asserted one DMA clock cycle later than IOR during DMA. This delay may be removed so that MEMR and IOR are asserted at the same time. DMA Controller Clock Speed Control: 0: DMA clock is ATCLK divided by two 1: DMA clock is ATCLK This bit allows the clock that controls the DMA controllers to be sped by running directly off of the ATCLK. Normally, the DMA clock is the AT clock divided by two. When this bit changes, internal synchronization logic prevents short clock pulses. Default 11
5:4
00
3:2
00
1
0
0
0
37
PRELIMINARY
Register 2: Peripheral Configuration Register #2 (Read/Write) - Index=02H Bit 7:3 2 Function Reserved Peripheral Controller Test Mode Control: 0: Normal Operation 1: Put Peripheral Controller Into Test Mode
CY82C693UB
Default 000 0
1
Interrupt Request Configuration Control: 0: Normal Operation 1: Enable Interrupt Request Level/Edge Control When this bit is set to 1, interrupt request inputs can be programmed (on an individual basis) to be Edge-triggered (non-sharable) or Level-sensitive (sharable). The selection is made in registers 3 and 4. DMA Extended Mode Control 0: Enable DMA Extended Mode 1: Disable DMA Extended Mode
0
0
0
Register 3: Interrupt Request Level/Edge Control Register #1 (Read/Write) - Index=03H Bit 7 Function IRQ7 Edge-Triggered/Level-Sensitive Selector: 0: Edge-Triggered 1: Level-Sensitive IRQ6 Edge-Triggered/Level-Sensitive Selector: 0: Edge-Triggered 1: Level-Sensitive IRQ5 Edge-Triggered/Level-Sensitive Selector: 0: Edge-Triggered 1: Level-Sensitive IRQ4 Edge-Triggered/Level-Sensitive Selector: 0: Edge-Triggered 1: Level-Sensitive IRQ3 Edge-Triggered/Level-Sensitive Selector: 0: Edge-Triggered 1: Level-Sensitive Reserved Default 0
6
0
5
0
4
0
3
0
2:0
000
38
PRELIMINARY
Register 4: Interrupt Request Level/Edge Control Register #2 (Read/Write) - Index=04H Bit 7 Function IRQ15 Edge-Triggered/Level-Sensitive Selector: 0: Edge-Triggered 1: Level-Sensitive IRQ14 Edge-Triggered/Level-Sensitive Selector: 0: Edge-Triggered 1: Level-Sensitive Reserved, Must be 0 IRQ12 Edge-Triggered/Level-Sensitive Selector: 0: Edge-Triggered 1: Level-Sensitive IRQ11 Edge-Triggered/Level-Sensitive Selector: 0: Edge-Triggered 1: Level-Sensitive IRQ10 Edge-Triggered/Level-Sensitive Selector: 0: Edge-Triggered 1: Level-Sensitive IRQ9 Edge-Triggered/Level-Sensitive Selector: 0: Edge-Triggered 1: Level-Sensitive Reserved, Must be 0
CY82C693UB
Default 0
6
0
5 4
0 0
3
0
2
0
1
0
0
0
Register 5: Real-Time-Clock Configuration Register (Read/Write) Bit 7:3 2:0 Function Reserved
- Index=05H
Default 00000 000
Value programmed into this register is used to fine-tune the 32-kHz Oscillator for greater RTC accuracy. The frequency variation is not linear and changes as the following: 000: +16 ppm 011: 0 ppm 111: -14 ppm Each on bit adds 0.5 pF of capacitance onto the crystal pins internally.
39
PRELIMINARY
Write-Only Shadow Registers
The following registers contain shadowed values for the internal write-only registers. The shadowed values may be used to
CY82C693UB
read, mask-off, and then modify certain fields within the write-only registers.
Register 80: DMA1 Write Request Shadow Register (Read/Write) Bit 7:0 Function
- Index=80H
Default 00000000
This register contains the shadowed value that was written into DMA1's DMA request register. (DMA Register 9)
Register 81: DMA1 Write Single Mask Bit Shadow Register (Read/Write) Bit 7:0 Function
- Index=81H
Default 00000000
This register contains the shadowed value that was written into DMA1 write single mask bit register. (DMA Register 10)
Register 82: DMA1 Write Mode Shadow Register (Read/Write) Bit 7:0 Function
- Index=82H
Default 00000000
This register contains the shadowed value that was written into DMA1 write mode register. (DMA Register 11)
Register 83: DMA1 Clear Byte Pointer Shadow Register (Read/Write) Bit 7:0 Function
- Index=83H
Default 00000000
This register contains the shadowed value that was written into DMA1 Address Space Expansion Flip-Flop Control Register. (DMA Register 12)
Register 84: DMA1 Master Clear Shadow Register (Read/Write) Bit 7:0 Function
- Index=84H
Default 00000000
This register contains the shadowed value that was written into DMA1 master clear register. (DMA Register 13)
Register 85: DMA1 Clear Mask Shadow Register (Read/Write) Bit 7:0 Function
- Index=85H
Default 00000000
This register contains the shadowed value that was written into DMA1 mask clear register. (DMA Register 14)
Register 86: Timer Counter 1 Command Mode Shadow Register (Read/Write) Bit 7:0 Function
- Index=86H
Default 00000000
This register contains the shadowed value that was written into timer counter 1 command mode register. (Timer/Counter Register 0)
Register 87: CMOS Battery-Backed RAM Address and NMI Mask Registers Shadow Register (Read/Write) Bit 7:0 Function This register contains the shadowed value that was written into the NMI mask register and the last accessed address to the CMOS RAM.
- Index=87H
Default 00000000
Register 88: DMA2 Write Request Shadow Register (Read/Write) Bit 7:0 Function
- Index=88H
Default 00000000
This register contains the shadowed value that was written into DMA2's write request register. (DMA Register 25)
40
PRELIMINARY
Register 89: DMA2 Write Single Mask Bit Shadow Register (Read/Write) Bit 7:0 Function
CY82C693UB
- Index=89H
Default 00000000
This register contains the shadowed value that was written into DMA2's write single mask bit register. (DMA Register 26)
Register 8A: DMA2 Write Mode Shadow Register (Read/Write) Bit 7:0 Function
- Index=8AH
Default 00000000
This register contains the shadowed value that was written into DMA2's write mode register. (DMA Register 27)
Register 8B: DMA2 Clear Byte Pointer Shadow Register (Read/Write) Bit 7:0 Function
- Index=8BH
Default 00000000
This register contains the shadowed value that was written into DMA2's Address Space Expansion Flip-Flop Control register. (DMA Register 28)
Register 8C: DMA2 Mask Clear Shadow Register (Read/Write) Bit 7:0 Function
- Index=8CH
Default 00000000
This register contains the shadowed value that was written into DMA2's mask clear register. (DMA Register 29)
Register 8D: DMA2 Clear Mask Shadow Register (Read/Write) Bit 7:0 Function
- Index=8DH
Default 00000000
This register contains the shadowed value that was written into DMA2's clear register. (DMA Register 30)
Register 8E: Coprocessor Error Shadow Register (Read/Write) Bit 7:0 Function
- Index=8EH
Default
This register contains the shadowed value that was written into the coprocessor error register. 00000000
Register 8F: Extended CMOS RAM address Shadow Register (Read/Write) Bit 7:0 Function
- Index=8FH
Default 00000000
This register contains the shadowed value that was written into the extended CMOS RAM address register.
41
PRELIMINARY
General Purpose I/O Registers
The following registers control the operation of GPIO. Register 90: General Purpose I/O Control Register A (Read/Write) Bit 7 Function
CY82C693UB
- Index=90H
Default 0
Internal Keyboard Controller GPIO Port Output Control: 0: Internal Keyboard Controller Ports not available on outputs of the CY82C693UB. 1: Internal Keyboard Controller Ports available on outputs of the CY82C693UB. Reserved GPIO5 Control: This bit value will be driven onto the GPIO5 pin if it is programmed as an output. This bit will contain the value driven onto the GPIO5 pin if it is programmed as an input. GPIO4 Control: This bit value will be driven onto the GPIO4 pin if it is programmed as an output. This bit will contain the value driven onto the GPIO4 pin if it is programmed as an input. GPIO3 Control: This bit value will be driven onto the GPIO3 pin if it is programmed as an output. This bit will contain the value driven onto the GPIO3 pin if it is programmed as an input. GPIO2 Control: This bit value will be driven onto the GPIO2 pin if it is programmed as an output. This bit will contain the value driven onto the GPIO2 pin if it is programmed as an input. GPIO1 Control: This bit value will be driven onto the GPIO1 pin if it is programmed as an output. This bit will contain the value driven onto the GPIO1 pin if it is programmed as an input. GPIO0 Control: This bit value will be driven onto the GPIO0 pin if it is programmed as an output. This bit will contain the value driven onto the GPIO0 pin if it is programmed as an input.
6 5
0 0
4
0
3
0
2
0
1
0
0
0
Register 91: General Purpose I/O Input/Output Control Register A (Read/Write) Bit 7:6 5 Function Reserved GPIO5 Control: 0: Input 1: Output GPIO4 Control: 0: Input 1: Output GPIO3 Control: 0: Input 1: Output GPIO2 Control: 0: Input 1: Output GPIO1 Control: 0: Input 1: Output GPIO0 Control: 0: Input 1: Output
- Index=91H
Default 00 0
4
0
3
0
2
0
1
0
0
0
42
PRELIMINARY
Register 92: General Purpose I/O Control Register B (Read/Write) Bit 7 Function
CY82C693UB
- Index=92H
Default 0
DMA Request Mode: 0: Normal. DMA request pins cannot be used for GPIO. 1: Multiplexed. If external multiplexer is used, several of the DMA Request signals can be used for GPIO. DMA Acknowledge Mode: 0: Normal. DMA acknowledge pins cannot be used for GPIO. 1: Encoded. If external priority decoder is used, several of the DMA Acknowledge signals can be used for GPIO. GPIO11 Control: This bit value will be driven onto the GPIO11 pin if it is programmed as an output. This bit will contain the value driven onto the GPIO11 pin if it is programmed as an input. GPIO10 Control: This bit value will be driven onto the GPIO10 pin if it is programmed as an output. This bit will contain the value driven onto the GPIO10 pin if it is programmed as an input. GPIO9 Control: This bit value will be driven onto the GPIO9 pin if it is programmed as an output. This bit will contain the value driven onto the GPIO9 pin if it is programmed as an input. GPIO8 Control: This bit value will be driven onto the GPIO8 pin if it is programmed as an output. This bit will contain the value driven onto the GPIO8 pin if it is programmed as an input. GPIO7 Control: This bit value will be driven onto the GPIO7 pin if it is programmed as an output. This bit will contain the value driven onto the GPIO7 pin if it is programmed as an input. GPIO6 Control: This bit value will be driven onto the GPIO6 pin if it is programmed as an output. This bit will contain the value driven onto the GPIO6 pin if it is programmed as an input.
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Register 93: General Purpose I/O Input/Output Control Register B (Read/Write) Bit 7:6 5 Function Reserved GPIO11 Control: 0: Input 1: Output GPIO10 Control: 0: Input 1: Output GPIO9 Control: 0: Input 1: Output GPIO8 Control: 0: Input 1: Output GPIO7 Control: 0: Input 1: Output GPIO6 Control: 0: Input 1: Output
- Index=93H
Default 00 0
4
0
3
0
2
0
1
0
0
0
43
PRELIMINARY
Power Management Control Registers
The following registers control the operation of the power management logic within the CY82C693UB. Register 40: Standby Timer Event Detection Control (Read/Write) Bit 7 Function PCI Master Request Detection Control: 0: Disable PCI Master Request Detection 1: Enable PCI Master Request Detection Video Memory Access (Blocks A, B, or 3b0H-3dfH) Detection Control: 0: Disable Video Memory Access Detection 1: Enable Video Memory Access Detection Parallel Port Access (278H-27fH, or 378H-37fH) Detection Control: 0: Disable Parallel Port. Access Detection 1: Enable Parallel Port Access Detection COM Port 2/4 Access (2f8H-2ffH, or 2e8H-2efH) Detection Control: 0: Disable COM Port 2/4 Access Detection 1: Enable COM Port 2/4 Access Detection COM Port 1/3 Access (3f8H-3ffH, or 3e8H-3efH) Detection Control: 0: Disable COM Port 1/3 Access Detection 1: Enable COM Port 1/3 Access Detection Hard Disk Access (170H-177H, or 1f0H-1f7H) Detection Control: 0: Disable Hard Disk Access Detection 1: Enable Hard Disk Access Detection Floppy Disk Access (3f5H) Detection Control: 0: Disable Floppy Disk Access Detection 1: Enable Floppy Disk Access Detection Keyboard Controller Access (60H or 64H) Detection Control: 0: Disable Keyboard Controller Access Detection 1: Enable Keyboard Controller Access Detection
CY82C693UB
- Index=40H
Default 0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
44
PRELIMINARY
Register 41: Standby Timer Interrupt Request Detection Control #1 (Read/Write) Bit 7 Function IRQ7 Monitor Control: 0: Disable IRQ7 Monitoring 1: Enable IRQ7 Monitoring IRQ6 Monitor Control: 0: Disable IRQ6 Monitoring 1: Enable IRQ6 Monitoring IRQ5 Monitor Control: 0: Disable IRQ5 Monitoring 1: Enable IRQ5 Monitoring IRQ4 Monitor Control: 0: Disable IRQ4 Monitoring 1: Enable IRQ4 Monitoring IRQ3 Monitor Control: 0: Disable IRQ3 Monitoring 1: Enable IRQ3 Monitoring INTR Monitor Control (Any Unmasked Interrupt Request): 0: Disable INTR Monitoring 1: Enable INTR Monitoring IRQ1 Monitor Control: 0: Disable IRQ1 Monitoring 1: Enable IRQ1 Monitoring IRQ0 Monitor Control: 0: Disable IRQ0 Monitoring 1: Enable IRQ0 Monitoring
CY82C693UB
- Index=41H
Default 0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Register 42: Standby Timer Interrupt Request Detection Control #2 (Read/Write) Bit 7 Function IRQ15 Monitor Control: 0: Disable IRQ15 Monitoring 1: Enable IRQ15 Monitoring IRQ14 Monitor Control: 0: Disable IRQ14 Monitoring 1: Enable IRQ14 Monitoring IRQ13 Monitor Control: 0: Disable IRQ13 Monitoring 1: Enable IRQ13 Monitoring IRQ12 Monitor Control: 0: Disable IRQ12 Monitoring 1: Enable IRQ12 Monitoring IRQ11 Monitor Control: 0: Disable IRQ11 Monitoring 1: Enable IRQ11 Monitoring IRQ10 Monitor Control: 0: Disable IRQ10 Monitoring 1: Enable IRQ10 Monitoring IRQ9 Monitor Control: 0: Disable IRQ9 Monitoring 1: Enable IRQ9 Monitoring IRQ8 Monitor Control: 0: Disable IRQ8 Monitoring 1: Enable IRQ8 Monitoring
- Index=42H
Default 0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
45
PRELIMINARY
Register 43: Standby Timer DMA Request Detection Control #1 (Read/Write) Bit 7 Function DREQ7 Monitor Control: 0: Disable DREQ7 Monitoring 1: Enable DREQ7 Monitoring DREQ6 Monitor Control: 0: Disable DREQ6 Monitoring 1: Enable DREQ6 Monitoring DREQ5 Monitor Control: 0: Disable DREQ5 Monitoring 1: Enable DREQ5 Monitoring ISA DMA/MASTER Monitor Control (Any DREQ): 0: Disable ISA DMA/MASTER Monitoring 1: Enable ISA DMA/MASTER Monitoring DREQ3 Monitor Control: 0: Disable DREQ3 Monitoring 1: Enable DREQ3 Monitoring DREQ2 Monitor Control: 0: Disable DREQ2 Monitoring 1: Enable DREQ2 Monitoring DREQ1 Monitor Control: 0: Disable DREQ1 Monitoring 1: Enable DREQ1 Monitoring DREQ0 Monitor Control: 0: Disable DREQ0 Monitoring 1: Enable DREQ0 Monitoring
CY82C693UB
- Index=43H
Default 0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Register 44: Suspend Timer Event Detection Control (Read/Write) Bit 7 Function PCI Master Request Detection Control: 0: Disable PCI Master Request Detection 1: Enable PCI Master Request Detection
- Index=44H
Default 0
6
Video Memory Access (Blocks A, B, or 3b0H-3dfH) Detection Control: 0: Disable Video Memory Access Detection 1: Enable Video Memory Access Detection Parallel Port Access (278H-27fH, or 378H-37fH) Detection Control: 0: Disable Parallel Port Access Detection 1: Enable Parallel Port Access Detection COM Port 2/4 Access (2f8H-2ffH, or 2e8H-2efH) Detection Control: 0: Disable COM Port. 2/4 Access Detection 1: Enable COM Port 2/4 Access Detection COM Port 1/3 Access (3f8H-3ffH, or 3e8H-3efH) Detection Control: 0: Disable COM Port 1/3 Access Detection 1: Enable COM Port 1/3 Access Detection Hard Disk Access (170H-177H, or 1f0H-1f7H) Detection Control: 0: Disable Hard Disk Access Detection 1: Enable Hard Disk Access Detection Floppy Disk Access (3f5H) Detection Control: 0: Disable Floppy Disk Access Detection 1: Enable Floppy Disk Access Detection Keyboard Controller Access (60H or 64H) Detection Control: 0: Disable Keyboard Controller Access Detection 1: Enable Keyboard Controller Access Detection
0
5
0
4
0
3
0
2
0
1
0
0
0
46
PRELIMINARY
Register 45: Suspend Timer Interrupt Request Detection Control #1 (Read/Write) Bit 7 Function IRQ7 Monitor Control: 0: Disable IRQ7 Monitoring 1: Enable IRQ7 Monitoring IRQ6 Monitor Control: 0: Disable IRQ6 Monitoring 1: Enable IRQ6 Monitoring IRQ5 Monitor Control: 0: Disable IRQ5 Monitoring 1: Enable IRQ5 Monitoring IRQ4 Monitor Control: 0: Disable IRQ4 Monitoring 1: Enable IRQ4 Monitoring IRQ3 Monitor Control: 0: Disable IRQ3 Monitoring 1: Enable IRQ3 Monitoring INTR Monitor Control (Any Unmasked Interrupt Request): 0: Disable INTR Monitoring 1: Enable INTR Monitoring IRQ1 Monitor Control: 0: Disable IRQ1 Monitoring 1: Enable IRQ1 Monitoring IRQ0 Monitor Control: 0: Disable IRQ0 Monitoring 1: Enable IRQ0 Monitoring
CY82C693UB
- Index=45H
Default 0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Register 46: Suspend Timer Interrupt Request Detection Control #2 (Read/Write) Bit 7 Function IRQ15 Monitor Control: 0: Disable IRQ15 Monitoring 1: Enable IRQ15 Monitoring IRQ14 Monitor Control: 0: Disable IRQ14 Monitoring 1: Enable IRQ14 Monitoring IRQ13 Monitor Control: 0: Disable IRQ13 Monitoring 1: Enable IRQ13 Monitoring IRQ12 Monitor Control: 0: Disable IRQ12 Monitoring 1: Enable IRQ12 Monitoring IRQ11 Monitor Control: 0: Disable IRQ11 Monitoring 1: Enable IRQ11 Monitoring IRQ10 Monitor Control: 0: Disable IRQ10 Monitoring 1: Enable IRQ10 Monitoring IRQ9 Monitor Control: 0: Disable IRQ9 Monitoring 1: Enable IRQ9 Monitoring IRQ8 Monitor Control: 0: Disable IRQ8 Monitoring 1: Enable IRQ8 Monitoring
- Index=46H
Default 0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
47
PRELIMINARY
Register 47: Suspend Timer DMA Request Detection Control #1 (Read/Write) Bit 7 Function DREQ7 Monitor Control: 0: Disable DREQ7 Monitoring 1: Enable DREQ7 Monitoring DREQ6 Monitor Control: 0: Disable DREQ6 Monitoring 1: Enable DREQ6 Monitoring DREQ5 Monitor Control: 0: Disable DREQ5 Monitoring 1: Enable DREQ5 Monitoring ISA DMA/MASTER Monitor Control (Any DREQ): 0: Disable ISA DMA/MASTER Monitoring 1: Enable ISA DMA/MASTER Monitoring DREQ3 Monitor Control: 0: Disable DREQ3 Monitoring 1: Enable DREQ3 Monitoring DREQ2 Monitor Control: 0: Disable DREQ2 Monitoring 1: Enable DREQ2 Monitoring DREQ1 Monitor Control: 0: Disable DREQ1 Monitoring 1: Enable DREQ1 Monitoring DREQ0 Monitor Control: 0: Disable DREQ0 Monitoring 1: Enable DREQ0 Monitoring
CY82C693UB
- Index=47H
Default 0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Register 48: User Timer 1 Event Detection Control (Read/Write) Bit 7 Function PCI Master Request Detection Control: 0: Disable PCI Master Request Detection 1: Enable PCI Master Request Detection
- Index=48H
Default 0
6
Video Memory Access (Blocks A, B, or 3b0H-3dfH) Detection Control: 0: Disable Video Memory Access Detection 1: Enable Video Memory Access Detection Parallel Port Access (278H-27fH, or 378H-37fH) Detection Control: 0: Disable Parallel Port Access Detection 1: Enable Parallel Port Access Detection COM Port 2/4 Access (2f8H-2ffH, or 2e8H-2efH) Detection Control: 0: Disable COM Port 2/4 Access Detection 1: Enable COM Port 2/4 Access Detection COM Port 1/3 Access (3f8H-3ffH, or 3e8H-3efH) Detection Control: 0: Disable COM Port 1/3 Access Detection 1: Enable COM Port 1/3 Access Detection Hard Disk Access (170H-177H, or 1f0H-1f7H) Detection Control: 0: Disable Hard Disk Access Detection 1: Enable Hard Disk Access Detection Floppy Disk Access (3f5H) Detection Control: 0: Disable Floppy Disk Access Detection 1: Enable Floppy Disk Access Detection Keyboard Controller Access (60H or 64H) Detection Control: 0: Disable Keyboard Controller Access Detection 1: Enable Keyboard Controller Access Detection
0
5
0
4
0
3
0
2
0
1
0
0
0
48
PRELIMINARY
Register 49: User Timer 1 Interrupt Request Detection Control #1 (Read/Write) Bit 7 Function IRQ7 Monitor Control: 0: Disable IRQ7 Monitoring 1: Enable IRQ7 Monitoring IRQ6 Monitor Control: 0: Disable IRQ6 Monitoring 1: Enable IRQ6 Monitoring IRQ5 Monitor Control: 0: Disable IRQ5 Monitoring 1: Enable IRQ5 Monitoring IRQ4 Monitor Control: 0: Disable IRQ4 Monitoring 1: Enable IRQ4 Monitoring IRQ3 Monitor Control: 0: Disable IRQ3 Monitoring 1: Enable IRQ3 Monitoring INTR Monitor Control (Any Unmasked Interrupt Request): 0: Disable INTR Monitoring 1: Enable INTR Monitoring IRQ1 Monitor Control: 0: Disable IRQ1 Monitoring 1: Enable IRQ1 Monitoring IRQ0 Monitor Control: 0: Disable IRQ0 Monitoring 1: Enable IRQ0 Monitoring
CY82C693UB
- Index=49H
Default 0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Register 4A: User Timer 1 Interrupt Request Detection Control #2 (Read/Write) Bit 7 Function IRQ15 Monitor Control: 0: Disable IRQ15 Monitoring 1: Enable IRQ15 Monitoring IRQ14 Monitor Control: 0: Disable IRQ14 Monitoring 1: Enable IRQ14 Monitoring IRQ13 Monitor Control: 0: Disable IRQ13 Monitoring 1: Enable IRQ13 Monitoring IRQ12 Monitor Control: 0: Disable IRQ12 Monitoring 1: Enable IRQ12 Monitoring IRQ11 Monitor Control: 0: Disable IRQ11 Monitoring 1: Enable IRQ11 Monitoring IRQ10 Monitor Control: 0: Disable IRQ10 Monitoring 1: Enable IRQ10 Monitoring IRQ9 Monitor Control: 0: Disable IRQ9 Monitoring 1: Enable IRQ9 Monitoring IRQ8 Monitor Control: 0: Disable IRQ8 Monitoring 1: Enable IRQ8 Monitoring
- Index=4AH
Default 0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
49
PRELIMINARY
Register 4B: User Timer 1 DMA Request Detection Control #1 (Read/Write) Bit 7 Function DREQ7 Monitor Control: 0: Disable DREQ7 Monitoring 1: Enable DREQ7 Monitoring DREQ6 Monitor Control: 0: Disable DREQ6 Monitoring 1: Enable DREQ6 Monitoring DREQ5 Monitor Control: 0: Disable DREQ5 Monitoring 1: Enable DREQ5 Monitoring ISA DMA/MASTER Monitor Control (Any DREQ): 0: Disable ISA DMA/MASTER Monitoring 1: Enable ISA DMA/MASTER Monitoring DREQ3 Monitor Control: 0: Disable DREQ3 Monitoring 1: Enable DREQ3 Monitoring DREQ2 Monitor Control: 0: Disable DREQ2 Monitoring 1: Enable DREQ2 Monitoring DREQ1 Monitor Control: 0: Disable DREQ1 Monitoring 1: Enable DREQ1 Monitoring DREQ0 Monitor Control: 0: Disable DREQ0 Monitoring 1: Enable DREQ0 Monitoring
CY82C693UB
- Index=4BH
Default 0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Register 4C: Throttle Timer Event Detection Control (Read/Write) Bit 7 Function PCI Master Request Detection Control: 0: Disable PCI Master Request Detection 1: Enable PCI Master Request Detection
- Index=4CH
Default 0
6
Video Memory Access (Blocks A, B, or 3b0H-3dfH) Detection Control: 0: Disable Video Memory Access Detection 1: Enable Video Memory Access Detection Parallel Port Access (278H-27fH, or 378H-37fH) Detection Control: 0: Disable Parallel Port Access Detection 1: Enable Parallel Port Access Detection COM Port 2/4 Access (2f8H-2ffH, or 2e8H-2efH) Detection Control: 0: Disable COM Port 2/4 Access Detection 1: Enable COM Port 2/4 Access Detection COM Port 1/3 Access (3f8H-3ffH, or 3e8H-3efH) Detection Control: 0: Disable COM Port. 1/3 Access Detection 1: Enable COM Port 1/3 Access Detection Hard Disk Access (170H-177H, or 1f0H-1f7H) Detection Control: 0: Disable Hard Disk Access Detection 1: Enable Hard Disk Access Detection Floppy Disk Access (3f5H) Detection Control: 0: Disable Floppy Disk Access Detection 1: Enable Floppy Disk Access Detection Keyboard Controller Access (60H or 64H) Detection Control: 0: Disable Keyboard Controller Access Detection 1: Enable Keyboard Controller Access Detection
0
5
0
4
0
3
0
2
0
1
0
0
0
50
PRELIMINARY
Register 4D: Throttle Timer Interrupt Request Detection Control #1 (Read/Write) Bit 7 Function IRQ7 Monitor Control: 0: Disable IRQ7 Monitoring 1: Enable IRQ7 Monitoring IRQ6 Monitor Control: 0: Disable IRQ6 Monitoring 1: Enable IRQ6 Monitoring IRQ5 Monitor Control: 0: Disable IRQ5 Monitoring 1: Enable IRQ5 Monitoring IRQ4 Monitor Control: 0: Disable IRQ4 Monitoring 1: Enable IRQ4 Monitoring IRQ3 Monitor Control: 0: Disable IRQ3 Monitoring 1: Enable IRQ3 Monitoring INTR Monitor Control (Any Unmasked Interrupt Request): 0: Disable INTR Monitoring 1: Enable INTR Monitoring IRQ1 Monitor Control: 0: Disable IRQ1 Monitoring 1: Enable IRQ1 Monitoring IRQ0 Monitor Control: 0: Disable IRQ0 Monitoring 1: Enable IRQ0 Monitoring
CY82C693UB
- Index=4DH
Default 0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Register 4E: Throttle Timer Interrupt Request Detection Control #2 (Read/Write) Bit 7 Function IRQ15 Monitor Control: 0: Disable IRQ15 Monitoring 1: Enable IRQ15 Monitoring IRQ14 Monitor Control: 0: Disable IRQ14 Monitoring 1: Enable IRQ14 Monitoring IRQ13 Monitor Control: 0: Disable IRQ13 Monitoring 1: Enable IRQ13 Monitoring IRQ12 Monitor Control: 0: Disable IRQ12 Monitoring 1: Enable IRQ12 Monitoring IRQ11 Monitor Control: 0: Disable IRQ11 Monitoring 1: Enable IRQ11 Monitoring IRQ10 Monitor Control: 0: Disable IRQ10 Monitoring 1: Enable IRQ10 Monitoring IRQ9 Monitor Control: 0: Disable IRQ9 Monitoring 1: Enable IRQ9 Monitoring IRQ8 Monitor Control: 0: Disable IRQ8 Monitoring 1: Enable IRQ8 Monitoring
- Index=4EH
Default 0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
51
PRELIMINARY
Register 4F: Throttle Timer DMA Request Detection Control #1 (Read/Write) Bit 7 Function DREQ7 Monitor Control: 0: Disable DREQ7 Monitoring 1: Enable DREQ7 Monitoring DREQ6 Monitor Control: 0: Disable DREQ6 Monitoring 1: Enable DREQ6 Monitoring DREQ5 Monitor Control: 0: Disable DREQ5 Monitoring 1: Enable DREQ5 Monitoring ISA DMA/MASTER Monitor Control (Any DREQ): 0: Disable ISA DMA/MASTER Monitoring 1: Enable ISA DMA/MASTER Monitoring DREQ3 Monitor Control: 0: Disable DREQ3 Monitoring 1: Enable DREQ3 Monitoring DREQ2 Monitor Control: 0: Disable DREQ2 Monitoring 1: Enable DREQ2 Monitoring DREQ1 Monitor Control: 0: Disable DREQ1 Monitoring 1: Enable DREQ1 Monitoring DREQ0 Monitor Control: 0: Disable DREQ0 Monitoring 1: Enable DREQ0 Monitoring
CY82C693UB
- Index=4FH
Default 0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Register 50: Non-motherboard Memory Address Range Decode for Event Detection Register #1 (Read/Write) - Index=50H Bit 7:0 Function Non-motherboard memory address decode AD[31:24] Default 00000000
Register 51: Non-motherboard Memory Address Range Decode for Event Detection Register #2 (Read/Write) Bit 7:0 Function Non-motherboard memory address decode AD[23:16]
- Index=51H
Default 00000000
Register 52: Non-motherboard Memory Address Mask for Event Detection Register #1 (Read/Write) Bit 7:0 Function Mask bits for non-motherboard memory address decode for event detection AD[31:24]
- Index=52H
Default 00000000
Register 53: Non-motherboard Memory Address Mask for Event Detection Register #2 (Read/Write) Bit 7:0 Function Mask bits for non-motherboard memory address decode for event detection AD[23:16]
- Index=53H
Default 00000000
Register 54: Programmable I/O Trap 1 Address Range Register #1 (Read/Write) Bit 7:0 Function
- Index=54H
Default 00000000
I/O address AD[7:0] which will automatically generate an SMI. The I/O Trap can be used in conjunction with the I/O restart feature of the Pentium.
52
PRELIMINARY
Register 55: Programmable I/O Trap 1 Address Range Register #2 (Read/Write) Bit 7:0 Function I/O address AD[15:8] which will automatically generate an SMI. The I/O Trap can be used in conjunction with the I/O restart feature of the Pentium.
CY82C693UB
- Index=55H
Default 00000000
Register 56: Programmable I/O Trap 1 Address Range Register #3 (Read/Write) Bit 7:0 Function
- Index=56H
Default 00000000
I/O address AD[23:16] which will automatically generate an SMI. The I/O Trap can be used in conjunction with the I/O restart feature of the Pentium.
Register 57: Programmable I/O Trap 1 Address Range Register #4 (Read/Write) Bit 7:0 Function
- Index=57H
Default 00000000
I/O address AD[31:24] which will automatically generate an SMI. The I/O Trap can be used in conjunction with the I/O restart feature of the Pentium.
Register 58: Programmable I/O Trap 2 Address Range Register #1 (Read/Write) Bit 7:0 Function
- Index=58H
Default 00000000
Secondary I/O address AD[7:0] which will automatically generate an SMI. The I/O Trap can be used in conjunction with the I/O restart feature of the Pentium.
Register 59: Programmable I/O Trap 2 Address Range Register #2 (Read/Write) Bit 7:0 Function
- Index=59H
Default 00000000
Secondary I/O address AD[15:8] which will automatically generate an SMI. The I/O Trap can be used in conjunction with the I/O restart feature of the Pentium.
Register 5A: Programmable I/O Trap 2 Address Range Register #3 (Read/Write) Bit 7:0 Function
- Index=5AH
Default 00000000
Secondary I/O address AD[23:16] which will automatically generate an SMI. The I/O Trap can be used in conjunction with the I/O restart feature of the Pentium.
Register 5B: Programmable I/O Trap 2 Address Range Register #4 (Read/Write) Bit 7:0 Function
- Index=5BH
Default 00000000
Secondary I/O address AD[31:24] which will automatically generate an SMI. The I/O Trap can be used in conjunction with the I/O restart feature of the Pentium.
53
PRELIMINARY
Register 5C: Programmable I/O Trap 1 Address Detection Control (Read/Write) Bit 7 Function AD[15:0] I/O Trap 1 Address Mask Control: 0: Disable AD[15:10] I/O Trap 1 Address Masking 1: Enable AD[15:10] I/O Trap 1 Address Masking AD[31:16] I/O Trap 1 Address Mask Control: 0: Disable AD[31:16] I/O Trap 1 Address Masking 1: Enable AD[31:16] I/O Trap 1 Address Masking Reserved Mask bit selection for Programmable I/O Trap 1 Address: 000: No Bits Masked 001: Lowest Order Bit Masked 010: 2 Lowest Order Bits Masked 011: 3 Lowest Order Bits Masked 100: 4 Lowest Order Bits Masked 101: 5 Lowest Order Bits Masked 110: 6 Lowest Order Bits Masked 111: 7 Lowest Order Bits Masked Standby Timer Non-motherboard memory access detection control: 0: Disable Non-motherboard memory access detection 1: Enable Non-motherboard memory access detection Suspend Timer Non-motherboard memory access detection control: 0: Disable Non-motherboard memory access detection 1: Enable Non-motherboard memory access detection
CY82C693UB
- Index=5CH
Default 0
6
0
5 4:2
0 000
1
0
0
0
Register 5D: Programmable I/O Trap 2 Address Detection Control (Read/Write) Bit 7 Function AD[15:0] I/O Trap 2 Address Mask Control: 0: Disable AD[15:10] I/O Trap 1 Address Masking 1: Enable AD[15:10] I/O Trap 1 Address Masking AD[31:16] I/O Trap 2 Address Mask Control: 0: Disable AD[31:16] I/O Trap 1 Address Masking 1: Enable AD[31:16] I/O Trap 1 Address Masking Reserved Mask bit selection for Programmable I/O Trap 2 Address: 000: No Bits Masked 001: Lowest Order Bit Masked 010: 2 Lowest Order Bits Masked 011: 3 Lowest Order Bits Masked 100: 4 Lowest Order Bits Masked 101: 5 Lowest Order Bits Masked 110: 6 Lowest Order Bits Masked 111: 7 Lowest Order Bits Masked User Timer 1 Non-motherboard memory access detection control: 0: Disable Non-motherboard memory access detection 1: Enable Non-motherboard memory access detection Throttle Timer Non-motherboard memory access detection control: 0: Disable Non-motherboard memory access detection 1: Enable Non-motherboard memory access detection
- Index=5DH
Default 0
6
0
5 4:2
0 000
1
0
0
0
54
PRELIMINARY
Register 5E: I/O Trap 1 and 2 Monitoring Control (Read/Write) Bit 7 Function Standby Timer I/O Trap 1 Monitor Control: 0: Disable Monitoring of I/O Trap 1 1: Enable Monitoring of I/O Trap 1 Suspend Timer I/O Trap 1 Monitor Control: 0: Disable Monitoring of I/O Trap 1 1: Enable Monitoring of I/O Trap 1 User Timer 1 I/O Trap 1 Monitor Control: 0: Disable Monitoring of I/O Trap 1 1: Enable Monitoring of I/O Trap 1 Throttle Timer I/O Trap 1 Monitor Control: 0: Disable Monitoring of I/O Trap 1 1: Enable Monitoring of I/O Trap 1 Standby Timer I/O Trap 2 Monitor Control: 0: Disable Monitoring of I/O Trap 2 1: Enable Monitoring of I/O Trap 2 Suspend Timer I/O Trap 2 Monitor Control: 0: Disable Monitoring of I/O Trap 2 1: Enable Monitoring of I/O Trap 2 User Timer 1 I/O Trap 2 Monitor Control: 0: Disable Monitoring of I/O Trap 2 1: Enable Monitoring of I/O Trap 2 Throttle Timer I/O Trap 2 Monitor Control: 0: Disable Monitoring of I/O Trap 2 1: Enable Monitoring of I/O Trap 2
CY82C693UB
- Index=5EH
Default 0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Register 5F: Standby and Suspend Timer Terminal Count Control Register (Read/Write) Bit 7:4 Function Standby Timer Terminal Count: 0000: 0.4 seconds 1000: 0001: 1 second 1001: 0010: 1.8 seconds 1010: 0011: 3.5 seconds 1011: 0100: 7 seconds 1100: 0101: 14 seconds 1101: 0110: 28 seconds 1110: 0111: 56 seconds 1111: Suspend Timer Terminal Count: 0000: 0.2 seconds 1000: 0001: 0.4 seconds 1001: 0010: 1 second 1010: 0011: 1.8 seconds 1011: 0100: 3.5 seconds 1100: 0101: 7 seconds 1101: 0110: 14 seconds 1110: 0111: 28 seconds 1111: 2 minutes 3.8 minutes 7.5 minutes 15 minutes 30 minutes 60 minutes 120 minutes 240 minutes
- Index=5FH
Default 0000
3:0
0000 56 seconds 2 minutes 3.8 minutes 7.5 minutes 15 minutes 30 minutes 60 minutes 120 minutes
55
PRELIMINARY
Register 60: User Timer 1 and User Timer 2 Terminal Count Control Register (Read/Write) Bit 7:4 Function User Timer 1 Terminal Count: 0000: 0.2 seconds 1000: 0001: 0.4 seconds 1001: 0010: 1 second 1010: 0011: 1.8 seconds 1011: 0100: 3.5 seconds 1100: 0101: 7 seconds 1101: 0110: 14 seconds 1110: 0111: 28 seconds 1111: User Timer 2 Terminal Count: 0000: 0.2 seconds 1000: 0001: 0.4 seconds 1001: 0010: 1 second 1010: 0011: 1.8 seconds 1011: 0100: 3.5 seconds 1100: 0101: 7 seconds 1101: 0110: 14 seconds 1110: 0111: 28 seconds 1111: 56 seconds 2 minutes 3.8 minutes 7.5 minutes 15 minutes 30 minutes 60 minutes 120 minutes
CY82C693UB
- Index=60H
Default 0000
3:0
0000 56 seconds 2 minutes 3.8 minutes 7.5 minutes 15 minutes 30 minutes 60 minutes 120 minutes
Register 61: User Timer 3 Terminal Count Control Register (Read/Write) Bit 7:4 Function User Timer 3 Terminal Count: 0000: 0.2 seconds 1000: 0001: 0.4 seconds 1001: 0010: 1 second 1010: 0011: 1.8 seconds 1011: 0100: 3.5 seconds 1100: 0101: 7 seconds 1101: 0110: 14 seconds 1110: 0111: 28 seconds 1111: 56 seconds 2 minutes 3.8 minutes 7.5 minutes 15 minutes 30 minutes 60 minutes 120 minutes
- Index=61H
Default 0000
3:2
SLOWCLK (PMWTCNT) to STOPCLK Transition Delay: 00: 430 microseconds 01: 7 milliseconds 10: 55 milliseconds 11: 1 second Reserved
00
1:0
00
56
PRELIMINARY
Register 62: Throttle Timer Terminal Count Control Register (Read/Write) Bit 7:4 Function Throttle 0000: 0001: 0010: 0011: 0100: 0101: 0110: 0111: Throttle 0000: 0001: 0010: 0011: 0100: 0101: 0110: 0111: Timer Low Time:: 27 microseconds 53.7 microseconds 107 microseconds 215 microseconds 430 microseconds 860 microseconds 1.7 milliseconds 3.4 milliseconds Timer High Time:: 27 microseconds 53.7 microseconds 107 microseconds 215 microseconds 430 microseconds 860 microseconds 1.7 milliseconds 3.4 milliseconds 1000: 1001: 1010: 1011: 1100: 1101: 1110: 1111: 1000: 1001: 1010: 1011: 1100: 1101: 1110: 1111: 7 milliseconds 14 milliseconds 28 milliseconds 55 milliseconds 0.1 seconds 0.2 seconds 0.4 seconds 1 second
CY82C693UB
- Index=62H
Default 0000
3:0
0000 7 milliseconds 14 milliseconds 28 milliseconds 55 milliseconds 0.1 seconds 0.2 seconds 0.4 seconds 1 second
Register 63: Power Management Control Register#1 (Read/Write) Bit 7 Function Power Management Enable Control: 0: Disable Power Management 1: Enable Power Management Hardware Controlled Power Management:: 0: Disable Hardware Power Management 1: Enable Hardware Power Management Software Controlled Power Management:: 0: Disable Software Power Management 1: Enable Software Power Management Reserved User Timer 1 Control: 0: Disable User Timer 1 1: Enable User Timer 1 User Timer 2 Control: 0: Disable User Timer 2 1: Enable User Timer 2 User Timer 3 Control: 0: Disable User Timer 3 1: Enable User Timer 3 Suspend Timer Event Monitor Control: 0: Disable Monitoring of Events 1: Enable Monitoring of Events
- Index=63H
Default 0
6
0
5
0
4 3
0 0
2
0
1
0
0
0
57
PRELIMINARY
Register 64: Power Management Control Register#2 (Read/Write) Bit 7 Function
CY82C693UB
- Index=64H
Default 0
Standby Timer Control: 0: Normal Operation 1: Reset Standby Timer (Value will automatically return to Normal Operation after Standby Timer is reset.) Suspend Timer Control: 0: Enable Suspend Timer 1: Disable Suspend Timer Disabling and reenabling the Suspend Timer allows for additional power-down states. Once the Suspend Timer has expired, it can be disabled and reenabled. When the terminal count expires, SMI will be asserted again. Software can keep track of the number of times that the Suspend Timer has expired to create additional states. Quick Power-down Control: 0: Disable Quick Power-down 1: Enable Quick Power-down Video Access Event Control: 0: Video Access Event consists of accesses to blocks A, B, and I/O 3b0H-3dfH. 1: Video Access Event only consists of accesses to blocks A and B Throttle Timer NMI monitor Control: 0: Disable monitoring of the NMI signal 1: Enable monitoring of the NMI signal User Timer 1 NMI monitor Control: 0: Disable monitoring of the NMI signal 1: Enable monitoring of the NMI signal Suspend Timer NMI monitor Control: 0: Disable monitoring of the NMI signal 1: Enable monitoring of the NMI signal Standby Timer NMI monitor Control: 0: Disable monitoring of the NMI signal 1: Enable monitoring of the NMI signal
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Register 65: Power Management Clock Control Register (Read/Write) Bit 7:6 5 Function Reserved
- Index=65H
Default 00 0
Software STOPCLK Assertion Control: 0: Normal Operation 1: Force Assertion of STOPCLK STOPCLK will remain active after this register is written to one until this register is written to zero. Software STOPCLK Deassertion Control: 0: Normal Operation 1: Force Deassertion of STOPCLK STOPCLK will remain inactive after this register is written to one until this register is written to zero. Hardware Controlled Power Management Control with the expiration of the Standby Timer: 00: Will not automatically assert STOPCLK 01: Reserved 10: Will automatically assert STOPCLK only 11: Will automatically assert STOPCLK
4
0
3:2
00
1:0
Hardware Controlled Power Management Control with the expiration of the Suspend Timer: 00 00: Will not automatically assert STOPCLK 01: Reserved 10: Will automatically assert STOPCLK only 11: Will automatically assert STOPCLK
58
PRELIMINARY
Register 66: STOPCLK Control Register (Read/Write) Bit 7 Function STOPCLK Function Control: 0: Disable STOPCLK 1: Enable STOPCLK STOPCLK Throttling Control: 0: Disable STOPCLK throttling 1: Enable STOPCLK throttling Reserved STOPCLK Automatic Deassertion Control: 0: STOPCLK automatically deasserted when Standby events occur 1: STOPCLK not automatically deasserted when Standby events occur STOPCLK Assertion Delay Timer Control: 0: Disable STOPCLK Assertion Delay Timer 1: Enable STOPCLK Assertion Delay Timer STOPCLK Delay Timer: 00: 430 microseconds 01: 860 microseconds 10: 1.7 milliseconds 11: 7 milliseconds Reserved
CY82C693UB
- Index=66H
Default 0
6
0
5 4
0 00
3
00
2:1
0
0
0
Register 67: Power Management SMI Control Register (Read/Write) Bit 7 Function
- Index=67H
Default 0
Software SMI Assertion Control: 0: Normal Operation 1: Force Assertion of SMI SMI will remain active after this register is written to one until this register is written to zero. Software SMI Deassertion Control: 0: Normal Operation 1: Force Deassertion of SMI SMI will remain inactive after this register is written to one until this register is written to zero. Reserved
6
0
5:0
000000
59
PRELIMINARY
Register 70: Power Management SMI Enable Register #1 (Read/Write) Bit 7 Function Non-motherboard Memory Access 0: Will Not Generate SMI 1: Will Generate SMI Video Memory Access: 0: Will Not Generate SMI 1: Will Generate SMI Parallel Port Access: 0: Will Not Generate SMI 1: Will Generate SMI COM Port 2/4 Access: 0: Will Not Generate SMI 1: Will Generate SMI COM Port 1/3 Access: 0: Will Not Generate SMI 1: Will Generate SMI Hard Disk Access: 0: Will Not Generate SMI 1: Will Generate SMI Floppy Disk Access: 0: Will Not Generate SMI 1: Will Generate SMI Keyboard Controller Access: 0: Will Not Generate SMI 1: Will Generate SMI
CY82C693UB
- Index=70H
Default 0
6
0
5
0
4
0
3
00
2
0
1
0
0
0
Register 71: Power Management SMI Enable Register #2 (Read/Write) Bit 7 Function User Timer 2 Timeout: 0: Will Not Generate SMI 1: Will Generate SMI User Timer 1 Timeout: 0: Will Not Generate SMI 1: Will Generate SMI Suspend Timer Timeout: 0: Will Not Generate SMI 1: Will Generate SMI Standby Timer Timeout: 0: Will Not Generate SMI 1: Will Generate SMI NMI: 0: 1: Will Not Generate SMI Will Generate SMI
- Index=71H
Default 0
6
0
5
0
4
0
3
00
2
PCI Master Request: 0: Will Not Generate SMI 1: Will Generate SMI Programmable I/O Trap 2 Address Access: 0: Will Not Generate SMI 1: Will Generate SMI Programmable I/O Trap 1 Address Access: 0: Will Not Generate SMI 1: Will Generate SMI
0
1
0
0
0
60
PRELIMINARY
Register 72: Power Management SMI Enable Register #3 (Read/Write) Bit 7 6 Function Reserved Automatic STOPCLK Assertion with APM Control Port Read Control: 0: No Automatic STOPCLK Assertion with APM Control Port Read 1: Automatic STOPCLK Assertion with APM Control Port Read DMA Request: 0: Will Not Generate SMI 1: Will Generate SMI This register bit works in conjunction with Register F5H. When this bit is set to 1, any DMA Request that is enabled will generate an SMI.
CY82C693UB
- Index=72H
Default 0 0
5
0
4
Interrupt Request: 0: Will Not Generate SMI 1: Will Generate SMI This register bit works in conjunction with Registers F3H and F4H. When this bit is set to 1, any Interrupt Request that is enabled will generate an SMI. The Assertion of the EPMI Signal: 0: Will Not Generate SMI 1: Will Generate SMI APMC (Advanced Power Management Code) Request: 0: Will Not Generate SMI 1: Will Generate SMI Software SMI Request: 0: Will Not Generate SMI 1: Will Generate SMI User Timer 3 Timeout: 0: Will Not Generate SMI 1: Will Generate SMI
0
3
00
2
0
1
0
0
0
Register 73: Power Management SMI Enable Register #4 (Read/Write) Bit 7 Function Assertion of IRQ7 (Interrupt Request 7) 0: Will Not Generate SMI 1: Will Generate SMI Assertion of IRQ6 (Interrupt Request 6) 0: Will Not Generate SMI 1: Will Generate SMI Assertion of IRQ5 (Interrupt Request 5) 0: Will Not Generate SMI 1: Will Generate SMI Assertion of IRQ4 (Interrupt Request 4) 0: Will Not Generate SMI 1: Will Generate SMI Assertion of IRQ3 (Interrupt Request 3) 0: Will Not Generate SMI 1: Will Generate SMI Assertion of INTR (Any Interrupt Request) 0: Will Not Generate SMI 1: Will Generate SMI Assertion of IRQ1 (Interrupt Request 1) 0: Will Not Generate SMI 1: Will Generate SMI Assertion of IRQ0 (Interrupt Request 0) 0: Will Not Generate SMI 1: Will Generate SMI
- Index=73H
Default 0
6
0
5
0
4
0
3
00
2
0
1
0
0
0
61
PRELIMINARY
Register 74: Power Management SMI Enable Register #5 (Read/Write) Bit 7 Function Assertion of IRQ15 (Interrupt Request 15) 0: Will Not Generate SMI 1: Will Generate SMI Assertion of IRQ14 (Interrupt Request 14) 0: Will Not Generate SMI 1: Will Generate SMI Assertion of IRQ13 (Interrupt Request 13) 0: Will Not Generate SMI 1: Will Generate SMI Assertion of IRQ12 (Interrupt Request 12) 0: Will Not Generate SMI 1: Will Generate SMI Assertion of IRQ11 (Interrupt Request 11) 0: Will Not Generate SMI 1: Will Generate SMI Assertion of IRQ10 (Interrupt Request 10) 0: Will Not Generate SMI 1: Will Generate SMI Assertion of IRQ9 (Interrupt Request 9) 0: Will Not Generate SMI 1: Will Generate SMI Assertion of IRQ8 (Interrupt Request 8) 0: Will Not Generate SMI 1: Will Generate SMI
CY82C693UB
- Index=74H
Default 0
6
0
5
0
4
0
3
00
2
0
1
0
0
0
Register 75: Power Management SMI Enable Register #6 (Read/Write) Bit 7 Function Assertion of DREQ7 (DMA Request 7) 0: Will Not Generate SMI 1: Will Generate SMI Assertion of DREQ6 (DMA Request 6) 0: Will Not Generate SMI 1: Will Generate SMI Assertion of DREQ5 (DMA Request 5) 0: Will Not Generate SMI 1: Will Generate SMI Assertion of DREQ (Any DMA Request) 0: Will Not Generate SMI 1: Will Generate SMI Assertion of DREQ3 (DMA Request 3) 0: Will Not Generate SMI 1: Will Generate SMI Assertion of DREQ2 (DMA Request 2) 0: Will Not Generate SMI 1: Will Generate SMI Assertion of DREQ1 (DMA Request 1) 0: Will Not Generate SMI 1: Will Generate SMI Assertion of DREQ0 (DMA Request 0) 0: Will Not Generate SMI 1: Will Generate SMI
- Index=75H
Default 0
6
0
5
0
4
0
3
00
2
0
1
0
0
0
62
PRELIMINARY
Register 76: Power Management SMI Status Register #1 (Read/Write) Bit 7 Function Non-motherboard Memory Access READ: 0: SMI was not caused by Non-motherboard Memory Access 1: SMI was caused by Non-motherboard Memory Access WRITE: 0: No change to register. 1: Clear Register Video Memory Access READ: 0: SMI was not caused by Video Memory Access 1: SMI was caused by Video Memory Access WRITE: 0: No change to register. 1: Clear Register Parallel Port Access READ: 0: SMI was not caused by Parallel Port Access 1: SMI was caused by Parallel Port Access WRITE: 0: No change to register. 1: Clear Register COM Port 2/4 Access READ: 0: SMI was not caused by COM Port 2/4 Access 1: SMI was caused by COM Port 2/4 Access WRITE: 0: No change to register. 1: Clear Register COM Port 1/3 Access READ: 0: SMI was not caused by COM Port 1/3 Access 1: SMI was caused by COM Port 1/3 Access WRITE: 0: No change to register. 1: Clear Register Hard Disk Access READ: 0: SMI was not caused by Hard Disk Access 1: SMI was caused by Hard Disk Access WRITE: 0: No change to register. 1: Clear Register Floppy Disk Access READ: 0: SMI was not caused by Floppy Disk Access 1: SMI was caused by Floppy Disk Access WRITE: 0: No change to register. 1: Clear Register Keyboard Controller Access READ: 0: SMI was not caused by Keyboard Controller Access 1: SMI was caused by Keyboard Controller Access WRITE: 0: No change to register. 1: Clear Register
CY82C693UB
- Index=76H
Default 0
6
0
5
0
4
0
3
00
2
0
1
0
0
0
63
PRELIMINARY
Register 77: Power Management SMI Status Register #2 (Read/Write) Bit 7 Function User Timer 2 Timeout READ: 0: SMI was not caused by a User Timer 2 Timeout 1: SMI was caused by a User Timer 2 Timeout WRITE: 0: No change to register. 1: Clear Register User Timer 1 Timeout READ: 0: SMI was not caused by a User Timer 1 Timeout 1: SMI was caused by a User Timer 1 Timeout WRITE: 0: No change to register. 1: Clear Register Suspend Timer Timeout READ: 0: SMI was not caused by a Suspend Timer Timeout 1: SMI was caused by a Suspend Timer Timeout WRITE: 0: No change to register. 1: Clear Register Standby Timer Timeout READ: 0: SMI was not caused by a Standby Timer Timeout 1: SMI was caused by a Standby Timer Timeout WRITE: 0: No change to register. 1: Clear Register PCI Master Request READ: 0: SMI was not caused by a PCI Master Request 1: SMI was caused by a PCI Master Request WRITE: 0: No change to register. 1: Clear Register NMI (Non-maskable Interrupt) READ: 0: SMI was not caused by an NMI 1: SMI was caused by an NMI WRITE: 0: No change to register. 1: Clear Register Programmable I/O Trap 2 READ: 0: SMI was not caused by a Programmable I/O Trap 2 1: SMI was caused by a Programmable I/O Trap 2 This Register bit is cleared automatically on a read. Programmable I/O Trap 1 READ: 0: SMI was not caused by a Programmable I/O Trap 1 1: SMI was caused by a Programmable I/O Trap 1 This Register bit is cleared automatically on a read.
CY82C693UB
- Index=77H
Default 0
6
0
5
0
4
0
3
00
2
0
1
0
0
0
64
PRELIMINARY
Register 78: Power Management SMI Status Register #3 (Read/Write) Bit 7 Function Standby Timer Status when in GREENPC Mode: 0: Timer continues to count. 1: Timer expired and GREENPC mode has been entered. Suspend Timer Status when in SUSGREENPC Mode: 0: Timer continues to count. 1: Timer expired and SUSGREENPC mode has been entered.
CY82C693UB
- Index=78H
Default 0
6
0
5
Interrupt Request READ: 0: SMI was not caused by an Interrupt Request 1: SMI was caused by an Interrupt Request This Register bit is cleared automatically on a read. If this bit is 0, registers F9H-FAH can be ignored. However, if this bit is 1, registers F9H-FAH contain valid status and should be cleared after being read. DMA Request READ: 0: SMI was not caused by a DMA Request 1: SMI was caused by a DMA Request This Register bit is cleared automatically on a read. If this bit is 0, register FBH can be ignored. However, if this bit is 1, register FBH contains valid status and should be cleared after being read. EPMI Asserted READ: 0: SMI was not caused by an EPMI Assertion 1: SMI was caused by an EPMI Assertion WRITE: 0: No change to register. 1: Clear Register APMC Write READ: 0: SMI was not caused by an APMC Write 1: SMI was caused by an APMC Write WRITE: 0: No change to register. 1: Clear Register Software SMI Assertion (Through Register E7H) READ: 0: SMI was not caused by a Software SMI Assertion 1: SMI was caused by a Software SMI Assertion WRITE: 0: No change to register. 1: Clear Register User Timer 3 Timeout READ: 0: SMI was not caused by a User Timer 3 Timeout 1: SMI was caused by a User Timer 3 Timeout WRITE: 0: No change to register. 1: Clear Register
0
4
0
3
00
2
0
1
0
0
0
65
PRELIMINARY
Register 79: Power Management Interrupt Request Status Register #1 (Read/Write) Bit 7 Function Assertion of IRQ7 (Interrupt Request 7) 0: SMI was not caused by an IRQ7 1: SMI was caused by an IRQ7 WRITE: 0: No change to register 1: Clear Register Assertion of IRQ6 (Interrupt Request 6) 0: SMI was not caused by an IRQ6 1: SMI was caused by an IRQ6 WRITE: 0: No change to register 1: Clear Register Assertion of IRQ5 (Interrupt Request 5) 0: SMI was not caused by an IRQ5 1: SMI was caused by an IRQ5 WRITE: 0: No change to register 1: Clear Register Assertion of IRQ4 (Interrupt Request 4) 0: SMI was not caused by an IRQ4 1: SMI was caused by an IRQ4 WRITE: 0: No change to register 1: Clear Register Assertion of IRQ3 (Interrupt Request 3) 0: SMI was not caused by an IRQ3 1: SMI was caused by an IRQ3 WRITE: 0: No change to register 1: Clear Register Assertion of INTR (Any Interrupt Request) 0: SMI was not caused by an INTR 1: SMI was caused by an INTR WRITE: 0: No change to register 1: Clear Register Assertion of IRQ1 (Interrupt Request 1) 0: SMI was not caused by an IRQ1 1: SMI was caused by an IRQ1 WRITE: 0: No change to register 1: Clear Register Assertion of IRQ0 (Interrupt Request 0) 0: SMI was not caused by an IRQ0 1: SMI was caused by an IRQ0 WRITE: 0: No change to register 1: Clear Register
CY82C693UB
- Index=79H
Default 0
6
0
5
0
4
0
3
00
2
0
1
0
0
0
66
PRELIMINARY
Register 7A: Power Management Interrupt Request Status Register #2 (Read/Write) Bit 7 Function Assertion of IRQ15 (Interrupt Request 15) 0: SMI was not caused by an IRQ15 1: SMI was caused by an IRQ15 WRITE: 0: No change to register 1: Clear Register Assertion of IRQ14 (Interrupt Request 14) 0: SMI was not caused by an IRQ14 1: SMI was caused by an IRQ14 WRITE: 0: No change to register 1: Clear Register Assertion of IRQ13 (Interrupt Request 13) 0: SMI was not caused by an IRQ13 1: SMI was caused by an IRQ13 WRITE: 0: No change to register 1: Clear Register Assertion of IRQ12 (Interrupt Request 12) 0: SMI was not caused by an IRQ12 1: SMI was caused by an IRQ12 WRITE: 0: No change to register 1: Clear Register Assertion of IRQ11 (Interrupt Request 11) 0: SMI was not caused by an IRQ11 1: SMI was caused by an IRQ11 WRITE: 0: No change to register 1: Clear Register Assertion of IRQ10 (Interrupt Request 10) 0: SMI was not caused by an IRQ10 1: SMI was caused by an IRQ10 WRITE: 0: No change to register 1: Clear Register Assertion of IRQ9 (Interrupt Request 9) 0: SMI was not caused by an IRQ9 1: SMI was caused by an IRQ9 WRITE: 0: No change to register 1: Clear Register Assertion of IRQ8 (Interrupt Request 8) 0: SMI was not caused by an IRQ8 1: SMI was caused by an IRQ8 WRITE: 0: No change to register 1: Clear Register
CY82C693UB
- Index=7AH
Default 0
6
0
5
0
4
0
3
00
2
0
1
0
0
0
67
PRELIMINARY
Register 7B: Power Management DMA Request Status Register (Read/Write) Bit 7 Function Assertion of DREQ7 (DMA Request 7) 0: SMI was not caused by a DREQ7 1: SMI was caused by a DREQ7 WRITE: 0: No change to register 1: Clear Register Assertion of DREQ6 (DMA Request 6) 0: SMI was not caused by a DREQ6 1: SMI was caused by a DREQ6 WRITE: 0: No change to register 1: Clear Register Assertion of DREQ5 (DMA Request 5) 0: SMI was not caused by a DREQ5 1: SMI was caused by a DREQ5 WRITE: 0: No change to register 1: Clear Register Assertion of DREQ (Any DMA Request) 0: SMI was not caused by a DREQ 1: SMI was caused by a DREQ WRITE: 0: No change to register 1: Clear Register Assertion of DREQ3 (DMA Request 3) 0: SMI was not caused by a DREQ3 1: SMI was caused by a DREQ3 WRITE: 0: No change to register 1: Clear Register Assertion of DREQ2 (DMA Request 2) 0: SMI was not caused by a DREQ2 1: SMI was caused by a DREQ2 WRITE: 0: No change to register 1: Clear Register Assertion of DREQ1 (DMA Request 1) 0: SMI was not caused by a DREQ1 1: SMI was caused by a DREQ1 WRITE: 0: No change to register 1: Clear Register Assertion of DREQ0 (DMA Request 0) 0: SMI was not caused by a DREQ0 1: SMI was caused by a DREQ0 WRITE: 0: No change to register 1: Clear Register
CY82C693UB
- Index=7BH
Default 0
6
0
5
0
4
0
3
00
2
0
1
0
0
0
68
PRELIMINARY
Register 7C: Reserved - Index=7CH Bit 7:0 Function Reserved
CY82C693UB
Default 00000000
Register 7D: Reserved Bit 7:0
- Index=7DH
Default 00000000
Function Reserved
Register 7E: Reserved Bit 7:0
- Index=7EH
Default 00000000
Function Reserved
Register 7F: Reserved Bit 7:0
- Index=7FH
Default 00000000
Function Reserved
69
PRELIMINARY
Special I/O Port Registers
The following ports are used for special functions. They are accessed by performing I/O transactions to the address specified.
CY82C693UB
Port 61: System Control Port B, NMI (Read/Write) - I/O Address=061H Bit 7 Function Read Only. PCI System Error (SERR) check: 0: No error 1: PCI SERR detected Read Only. I/O channel check: 0: No error 1: I/O channel error detected (ISA IOCHK signal asserted) Read Only. Timer 2 output: 0: Timer 2 (speaker) output is low 1: Timer 2 output is high Read Only. Refresh detection: 0: Refresh request not detected 1: Refresh request detected Read/Write port. I/O channel check: 0: Enable I/O channel check 1: Disable I/O channel check When enabled an I/O channel error will generate an NMI to the CPU. Read/Write port. PCI System Error (SERR) check: 0: Enable PCI SERR check 1: Disable PCI SERR check When enabled a PCI system error will generate an NMI to the CPU. Read/Write port. Speaker data. Read/Write. Timer 2 speaker gate: 0: Timer 2 speaker gate disabled 1: Timer 2 speaker gate enabled Default 0
6
0
5
0
4
0
3
0
2
0
1 0
0 0
Port 70: RTC/Configuration RAM Address Port, NMI (Write) - I/O Address=070H Bit 7 Function NMI reporting: 0: Enable NMI reporting 1: Disable NMI reporting Sources of NMI can be either from ISA I/O channel error or PCI SERR depending on bits 3 and 2 of register port 61. Extended CMOS RAM See CY82C693UB Real-Time Clock Register section. Default 0
6:0
0000000
Port 92: PS/2 Reset Control (Read/Write) - I/O Address=092H Bit 7:2 1 Function Reserved GTA20 Control: 0: Activate GTA20. 1: Deactivate GTA20. Fast Reset Control: 0: INIT deactivated. Will occur automatically after reset timer expires. 1: Assert INIT. Default 00000000 0
0
0
70
PRELIMINARY
Port B2: APM Control Port (Read/Write) - I/O Address=0B2H Bit 7:0 Function This Read/Write Port can be used for APM software. A write to this register will generate an SMI.
CY82C693UB
Default 00000000
Port B3: APM Status Port (Read/Write) - I/O Address=0B3H Bit 7:0 Function This Read/Write Port can be used for APM software. Default 00000000
71
PRELIMINARY
CY82C693UB DMA Controller Registers
There are two DMA controllers cascaded together inside the CY82C693UB. (DMAC1 and DMAC2). Each DMA Controller contains four channels. DMAC1 controls the 8-bit DMA operations and DMAC2 controls 16-bit DMA operations. Channel 0 of DMAC2 provides the cascade between the two controllers, and therefore, may not be used for DMA data transfers. DMAC1's DMA request and acknowledge signals correspond to the DREQ0-DREQ3 and DACK0-DACK3 signals. DMAC2's DMA request and acknowledge signals correspond to the DREQ5-DREQ7 and DACK5-DACK7 signals. The internal registers for the CY82C693UB DMA controllers are defined in this section. The registers can be accessed by performing I/O reads and writes to Addresses 000H through 00FH (for DMAC1) and Addresses 0C0H through 0CFH (for DMAC2). The DMA Page (Upper Order DMA address bits are controlled using I/O addresses 080H-08FH). All DMAC registers are eight bits (1 byte) wide. Performing I/O accesses to these address ranges will place the corresponding DMA controller into its Program State. The DMA controller register address space has been increased using an additional address flip-flop. The flip-flop toggles every time an access occurs to the DMA word count or DMA address registers. The flip-flop is cleared by the assertion of the CPURST signal (from the CY82C693UB) or a MASTER CLEAR from the DMA registers. The flip-flop can also be programmed by an access to the flip-flop control register. The DMA channels within the controllers should be masked prior to entering the Program State to insure that a DMA access is not attempted to a partially programmed channel. After the DMA controllers are programmed, they should be unmasked. This will allow the DMA controllers to enter the
CY82C693UB
ACTIVE State. The ACTIVE State will be entered when a valid DMA request is recognized by the CY82C693UB. During 8-bit DMA transfers, DMAC1 places the memory address bits on Address 0 through 15. For 16-bit DMA transfers, DMAC2 places the memory address bits on Address 1 through 16 (Address 0 is zero for 16-bit transfers). The page address bits are placed on Address 17 through 23. DMA registers 0 through 7 provide access to each channel's Current Address Register, Current Word Count Register, Base Address Register, and Base Word Count Register. The Current Address Register contains the 16-bit address used during transfers. The value in the Current Address Register is either incremented or decremented (programmable) to provide the transfer addresses. Channel 0 will hold its address (without incrementing or decrementing) by setting the Address Hold Bit in the Command Register. If Autoinitializtion is selected, the Current Address Register is reloaded with the contents of the Base Address Register when the terminal count is reached in the Current Word Count Register. The Current Word Count Register contains the number of transfers to perform. This register is decremented with each transfer. The terminal count will be reached on the transition of this register from 0000H to FFFFH. Therefore, the actual number of transfers will be one more than the value loaded in the Current Word Count Register. When the terminal count is reached, the channel will be suspended and either masked or autoinitialized. The Base Address Register is write-only and is loaded along with the Current Address Register. This register stores the initial value of the Current Address Register and will reload its contents into the Current Address Register when the terminal count is reached if autoinitialization is selected. Likewise, the Base Word Count Register is used to reload the Current Word Count Register with its initial value if autoinitialization is programmed.
-
DMA Register 0: DMAC1 Channel 0 Current Address Register (Read/Write) - I/O Address=000H I/O Read I/O Write Flip-Flop State Function 0 0 1 1 1 1 0 0 0 1 0 1 Read Low Byte of Current Address Register Read High Byte of Current Address Register Write Low Byte of Base Address Register and Current Address Register Write High Byte of Base Address Register and Current Address Register
DMA Register 1: DMAC1 Channel 0 Current Word Count Register (Read/Write) - I/O Address=001H I/O Read I/O Write Flip-Flop State Function 0 0 1 1 1 1 0 0 0 1 0 1 Read Low Byte of Current Word Count Register Read High Byte of Current Word Count Register Write Low Byte of Base Word Count Register and Current Word Count Register Write High Byte of Base Word Count Register and Current Word Count Register
DMA Register 2: DMAC1 Channel 1 Current Address Register (Read/Write) - I/O Address=002H I/O Read I/O Write Flip-Flop State Function 0 0 1 1 1 1 0 0 0 1 0 1 Read Low Byte of Current Address Register Read High Byte of Current Address Register Write Low Byte of Base Address Register and Current Address Register Write High Byte of Base Address Register and Current Address Register
72
PRELIMINARY
I/O Read I/O Write Flip-Flop State Function 0 0 1 1 1 1 0 0 0 1 0 1 Read Low Byte of Current Word Count Register Read High Byte of Current Word Count Register
CY82C693UB
DMA Register 3: DMAC1 Channel 1 Current Word Count Register (Read/Write) - I/O Address=003H
Write Low Byte of Base Word Count Register and Current Word Count Register Write High Byte of Base Word Count Register and Current Word Count Register
DMA Register 4: DMAC1 Channel 2 Current Address Register (Read/Write) - I/O Address=004H I/O Read I/O Write Flip-Flop State Function 0 0 1 1 1 1 0 0 0 1 0 1 Read Low Byte of Current Address Register Read High Byte of Current Address Register Write Low Byte of Base Address Register and Current Address Register Write High Byte of Base Address Register and Current Address Register
DMA Register 5: DMAC1 Channel 2 Current Word Count Register (Read/Write) - I/O Address=005H I/O Read I/O Write Flip-Flop State Function 0 0 1 1 1 1 0 0 0 1 0 1 Read Low Byte of Current Word Count Register Read High Byte of Current Word Count Register Write Low Byte of Base Word Count Register and Current Word Count Register Write High Byte of Base Word Count Register and Current Word Count Register
DMA Register 6: DMAC1 Channel 3 Current Address Register (Read/Write) - I/O Address=006H I/O Read I/O Write Flip-Flop State Function 0 0 1 1 1 1 0 0 0 1 0 1 Read Low Byte of Current Address Register Read High Byte of Current Address Register Write Low Byte of Base Address Register and Current Address Register Write High Byte of Base Address Register and Current Address Register
DMA Register 7: DMAC1 Channel 3 Current Word Count Register (Read/Write) - I/O Address=007H I/O Read I/O Write Flip-Flop State Function 0 0 1 1 1 1 0 0 0 1 0 1 Read Low Byte of Current Word Count Register Read High Byte of Current Word Count Register Write Low Byte of Base Word Count Register and Current Word Count Register Write High Byte of Base Word Count Register and Current Word Count Register
DMA Register 8: DMAC1 Status/Command Register (Read/Write) - I/O Address=008H I/O Read I/O Write Flip-Flop State Function 0 1 1 0 X X Read Status Register Write Command Register
73
PRELIMINARY
Status Register Format (Read Only) Bit 7 Function
CY82C693UB
Default 0
DMA Request for Channel 3: 0: No DMA request is pending for Channel 3 1: DMA request is pending for Channel 3 This bit is cleared by CPURST, Master Clear, or on the deassertion of the DMA Request. This bit will not be masked (even if the channel is masked). DMA Request for Channel 2: 0: No DMA request is pending for Channel 2 1: DMA request is pending for Channel 2 This bit is cleared by CPURST, Master Clear, or on the deassertion of the DMA Request. This bit will not be masked (even if the channel is masked). DMA Request for Channel 1: 0: No DMA request is pending for Channel 1 1: DMA request is pending for Channel 1 This bit is cleared by CPURST, Master Clear, or on the deassertion of the DMA Request. This bit will not be masked (even if the channel is masked). DMA Request for Channel 0: 0: No DMA request is pending for Channel 0 1: DMA request is pending for Channel 0 This bit is cleared by CPURST, Master Clear, or on the deassertion of the DMA Request. This bit will not be masked (even if the channel is masked). Terminal Count Status on Channel 3: 0: Terminal Count Not Reached on Channel 3 1: Terminal Count Reached on Channel 3 This bit is cleared by CPURST, Master Clear, or on a Status Register Read. Terminal Count Status on Channel 2: 0: Terminal Count Not Reached on Channel 2 1: Terminal Count Reached on Channel 2 This bit is cleared by CPURST, Master Clear, or on a Status Register Read. Terminal Count Status on Channel 1: 0: Terminal Count Not Reached on Channel 1 1: Terminal Count Reached on Channel 1 This bit is cleared by CPURST, Master Clear, or on a Status Register Read. Terminal Count Status on Channel 0: 0: Terminal Count Not Reached on Channel 0 1: Terminal Count Reached on Channel 0 This bit is cleared by CPURST, Master Clear, or on a Status Register Read.
6
0
5
0
4
0
3
0
2
0
1
0
0
0
74
PRELIMINARY
Command Register Format (Write Only) Bit 7 Function DMA Acknowledge Signal Active Level Control: 0: DACK signals are active LOW 1: DACK signals are active HIGH DMA Request Signal Active Level Control: 0: DREQ signals are active HIGH 1: DREQ signals are active LOW Reserved, Must be 0
CY82C693UB
Default 0
6
0
5 4
0 0
DMA Priority Control: 0: DMA Requests will be honored according to fixed priority (Channel 0 has highest priority/Channel 7 has lowest priority) 1: DMA Requests will be honored according to rotating priority (Every time a channel is acknowledged, it rotates to lowest priority) DMA Compressed Timing Control: 0: Disable Compressed Timing 1: Enable Compressed Timing Normal DMA word transfers take 4 DMA clock cycles. Compressed timing causes the command signals and the terminal count signal to be asserted one cycle earlier. This allows the entire DMA transfer to be compressed to 3 DMA clock cycles.
3
0
2
DMA Controller Disable Control: 0 0: Normal Operation 1: Disable DMA Controllers Disabling the DMA Controllers prevents DMA cycles from occurring during channel programming. Address Hold Control: 0: Normal Operation 1: Force the value in Channel 0's Current Address Register to remain the same (no increment or decrement). Used for memory to memory transfers. Memory to Memory Transfer Control: 0: Normal Operation 1: Channel 0 and channel 1 will be used for memory to memory transfers. 0
1
0
0
DMA Register 9: DMAC1 DMA Request Register (Write Only) - I/O Address=009H I/O Read I/O Write Flip-Flop State Function 0 1 1 0 X X Undefined Write DMA Request Register
DMA Request Register Write Format. (This Register is used to generate DMA requests through software. Multiple Software requests can be generated with separate writes to this register. Software DMA Requests cannot be masked. Bit 7:3 2 Function Reserved DMA Request Generation Control: 0: Do not generate a DMA Request 1: Force a DMA Request on the channel specified by bits[1:0]. DMA Request Channel Selector: 00: Channel 0 01: Channel 1 10: Channel 2 11: Channel 3 Default 00000 0
1:0
00
75
PRELIMINARY
DMA Register 10: DMAC1 DMA Command/Mask Register (Write Only) - I/O Address=00AH I/O Read I/O Write Flip-Flop State Function 0 1 1 0 X X Undefined
CY82C693UB
Write single-bit in DMA Request Mask Register (leaving the rest unchanged)
DMA Request Mask Register Write Single Bit Format. (This Register is used to mask DMA requests through software. Single-bit Software request masks can be generated with separate writes to this register or all channels can be masked using DMA Register 15.) Bit 7:3 2 Function Reserved DMA Request Mask Generation Control: 0: Clear the mask on the channel specified by bits[1:0] 1: Force a DMA Request on the channel specified by bits[1:0]. DMA Request Mask Channel Selector: 00: Channel 0 01: Channel 1 10: Channel 2 11: Channel 3 Default 00000 0
1:0
00
DMA Register 11: DMAC1 DMA Mode Register (Write Only) - I/O Address=00BH I/O Read I/O Write Flip-Flop State Function 0 1 1 0 X X Undefined Write Mode Register
76
PRELIMINARY
Mode Register Format. (Should be programmed for each channel.) Bit 7:6 Function DMA Mode Selection Control: 00: Demand Transfer Mode 01: Single Transfer Mode 10: Block Transfer Mode 11: Cascade Mode See DMA Controller description for details about each mode. Counter Direction Control: 0: Increment Address Counter After Each Transfer 1: Decrement Address Counter After Each Transfer
CY82C693UB
Default 00
5
0
4
Autoinitialization Control: 0: Disable Autoinitialization 1: Enable Autoinitialization Autoinitialization will restore the initial values into the Current Address Register and Word Count Register when the terminal count is reached. The channel will not automatically be masked if it is autoinitialized. DMA Transfer Type Selection Control: 00: Verify Transfer 01: Write Transfer 10: Read Transfer 11: Undefined (DO NOT USE) See DMA Controller description for details about each transfer type.
0
3:2
00
1:0
Channel Selector: 00 00: Channel 0 01: Channel 1 10: Channel 2 11: Channel 3 Each DMA channel has its own mode register, but they are all accessed through I/O Address 00BH. For Mode Register writes, bits[1:0] control which channel's mode register will be written. To read each channel's mode register, four sequential reads will walk through all of the mode registers. Clearing the Mode Register Counter (DMA Register 14) will start the read sequence at a known state (channel 0). During reads, the channel selector bits will be 11 regardless of the channel.
DMA Register 12: DMAC1 Address Space Expansion Flip-Flop Control Register (Write Only) - I/O Address=00CH I/O Read I/O Write Flip-Flop State Function 0 1 1 0 X X Undefined Clear Flip-Flop (Flip-Flop=0). This is a special command. The data lines are ignored.
DMA Register 13: DMAC1 Master Clear Register (Write Only) - I/O Address=00DH I/O Read I/O Write Flip-Flop State Function 0 1 1 0 X X Undefined Perform Master Clear. This is a special command. The data lines are ignored.
DMA Register 14: DMAC1 DMA Mask Clear Register (Write Only) - I/O Address=00EH I/O Read I/O Write Flip-Flop State Function 0 1 1 0 X X Undefined Clear DMA Request Mask Bits (Unmask all DMA requests). This is a special command. The data lines are ignored.
77
PRELIMINARY
DMA Register 15: DMAC1 Request Mask Register Control (Read/Write) - I/O Address=00FH I/O Read I/O Write Flip-Flop State Function 0 1 1 0 X X Read All bits of DMA Request Mask Register Write All bits of DMA Request Mask Register
CY82C693UB
DMA Request Mask Register Read and Write All Bits Format (This register is cleared on CPURST.) Bit 7:4 3 Function Reserved DMA Channel 3 Request Mask: 0: Channel 3 Not Masked 1: Channel 3 Masked DMA Channel 2 Request Mask: 0: Channel 2 Not Masked 1: Channel 2 Masked DMA Channel 1 Request Mask: 0: Channel 1 Not Masked 1: Channel 1 Masked DMA Channel 0 Request Mask: 0: Channel 0 Not Masked 1: Channel 0 Masked Default 0000 0
2
0
1
0
0
0
DMA Register 16: DMAC2 Channel 0 (Channel 4) Current Address Register (Read/Write) - I/O Address=0C0H I/O Read I/O Write Flip-Flop State Function 0 0 1 1 1 1 0 0 0 1 0 1 Read Low Byte of Current Address Register Read High Byte of Current Address Register Write Low Byte of Base Address Register and Current Address Register Write High Byte of Base Address Register and Current Address Register
DMA Register 17: DMAC2 Channel 0 (Channel 4) Current Word Count Register (Read/Write) - I/O Address=0C2H I/O Read I/O Write Flip-Flop State Function 0 0 1 1 1 1 0 0 0 1 0 1 Read Low Byte of Current Word Count Register Read High Byte of Current Word Count Register Write Low Byte of Base Word Count Register and Current Word Count Register Write High Byte of Base Word Count Register and Current Word Count Register
DMA Register 18: DMAC2 Channel 1 (Channel 5) Current Address Register (Read/Write) - I/O Address=0C4H I/O Read I/O Write Flip-Flop State Function 0 0 1 1 1 1 0 0 0 1 0 1 Read Low Byte of Current Address Register Read High Byte of Current Address Register Write Low Byte of Base Address Register and Current Address Register Write High Byte of Base Address Register and Current Address Register
78
PRELIMINARY
I/O Read I/O Write Flip-Flop State Function 0 0 1 1 1 1 0 0 0 1 0 1 Read Low Byte of Current Word Count Register Read High Byte of Current Word Count Register
CY82C693UB
DMA Register 19: DMAC2 Channel 1 (Channel 5) Current Word Count Register (Read/Write) - I/O Address=0C6H
Write Low Byte of Base Word Count Register and Current Word Count Register Write High Byte of Base Word Count Register and Current Word Count Register
DMA Register 20: DMAC2 Channel 2 (Channel 6) Current Address Register (Read/Write) - I/O Address=0C8H I/O Read I/O Write Flip-Flop State Function 0 0 1 1 1 1 0 0 0 1 0 1 Read Low Byte of Current Address Register Read High Byte of Current Address Register Write Low Byte of Base Address Register and Current Address Register Write High Byte of Base Address Register and Current Address Register
DMA Register 21: DMAC2 Channel 2 (Channel 6) Current Word Count Register (Read/Write) - I/O Address=0CAH I/O Read I/O Write Flip-Flop State Function 0 0 1 1 1 1 0 0 0 1 0 1 Read Low Byte of Current Word Count Register Read High Byte of Current Word Count Register Write Low Byte of Base Word Count Register and Current Word Count Register Write High Byte of Base Word Count Register and Current Word Count Register
DMA Register 22: DMAC2 Channel 3 (Channel 7) Current Address Register (Read/Write) - I/O Address=0CCH I/O Read I/O Write Flip-Flop State Function 0 0 1 1 1 1 0 0 0 1 0 1 Read Low Byte of Current Address Register Read High Byte of Current Address Register Write Low Byte of Base Address Register and Current Address Register Write High Byte of Base Address Register and Current Address Register
DMA Register 23: DMAC2 Channel 3 (Channel 7) Current Word Count Register (Read/Write) - I/O Address=0CEH I/O Read I/O Write Flip-Flop State Function 0 0 1 1 1 1 0 0 0 1 0 1 Read Low Byte of Current Word Count Register Read High Byte of Current Word Count Register Write Low Byte of Base Word Count Register and Current Word Count Register Write High Byte of Base Word Count Register and Current Word Count Register
DMA Register 24: DMAC2 Status/Command Register (Read/Write) - I/O Address=0D0H I/O Read I/O Write Flip-Flop State Function 0 1 1 0 X X Read Status Register Write Command Register
79
PRELIMINARY
Status Register Format (Read Only) Bit 7 Function
CY82C693UB
Default 0
DMA Request for Channel 7: 0: No DMA request is pending for Channel 7 1: DMA request is pending for Channel 7 This bit is cleared by CPURST, Master Clear, or on the deassertion of the DMA Request. This bit will not be masked (even if the channel is masked). DMA Request for Channel 6: 0: No DMA request is pending for Channel 6 1: DMA request is pending for Channel 6 This bit is cleared by CPURST, Master Clear, or on the deassertion of the DMA Request. This bit will not be masked (even if the channel is masked). DMA Request for Channel 5: 0: No DMA request is pending for Channel 5 1: DMA request is pending for Channel 5 This bit is cleared by CPURST, Master Clear, or on the deassertion of the DMA Request. This bit will not be masked (even if the channel is masked). DMA Request for Channel 4: 0: No DMA request is pending for Channel 4 1: DMA request is pending for Channel 4 This bit is cleared by CPURST, Master Clear, or on the deassertion of the DMA Request. This bit will not be masked (even if the channel is masked). Terminal Count Status on Channel 7: 0: Terminal Count Not Reached on Channel 7 1: Terminal Count Reached on Channel 7 This bit is cleared by CPURST, Master Clear, or on a Status Register Read. Terminal Count Status on Channel 6: 0: Terminal Count Not Reached on Channel 6 1: Terminal Count Reached on Channel 6 This bit is cleared by CPURST, Master Clear, or on a Status Register Read. Terminal Count Status on Channel 5: 0: Terminal Count Not Reached on Channel 5 1: Terminal Count Reached on Channel 5 This bit is cleared by CPURST, Master Clear, or on a Status Register Read. Terminal Count Status on Channel 4: 0: Terminal Count Not Reached on Channel 4 1: Terminal Count Reached on Channel 4 This bit is cleared by CPURST, Master Clear, or on a Status Register Read.
6
0
5
0
4
0
3
0
2
0
1
0
0
0
80
PRELIMINARY
Command Register Format (Write Only) Bit 7 Function DMA Acknowledge Signal Active Level Control: 0: DACK signals are active LOW 1: DACK signals are active HIGH DMA Request Signal Active Level Control: 0: DREQ signals are active HIGH 1: DREQ signals are active LOW Reserved, Must be 0
CY82C693UB
Default 0
6
0
5 4
0
DMA Priority Control: 0 0: DMA Requests will be honored according to fixed priority (Channel 0 has highest priority/Channel 7 has lowest priority) 1: DMA Requests will be honored according to rotating priority (Every time a channel is acknowledged, it rotates to lowest priority) DMA Compressed Timing Control: 0: Disable Compressed Timing 1: Enable Compressed Timing Normal DMA word transfers take 4 DMA clock cycles. Compressed timing causes the command signals and the terminal count signal to be asserted one cycle earlier. This allows the entire DMA transfer to be compressed to 3 DMA clock cycles. 0
3
2
DMA Controller Disable Control: 0 0: Normal Operation 1: Disable DMA Controllers Disabling the DMA Controllers prevents DMA cycles from occurring during channel programming. Address Hold Control: 0: Normal Operation 1: Force the value in Channel 0's Current Address Register to remain the same (no increment or decrement). Used for memory to memory transfers. Memory to Memory Transfer Control: 0: Normal Operation 1: Channel 0 and channel 1 will be used for memory to memory transfers. 0
1
0
0
DMA Register 25: DMAC2 DMA Request Register (Write Only) - I/O Address=0D2H I/O Read I/O Write Flip-Flop State Function 0 1 1 0 X X Undefined Write DMA Request Register
DMA Request Register Write Format (This Register is used to generate DMA requests through software. Multiple Software requests can be generated with separate writes to this register. Software DMA Requests cannot be masked.) Bit 7:3 2 Function Reserved DMA Request Generation Control: 0: Do not generate a DMA Request 1: Force a DMA Request on the channel specified by bits[1:0]. DMA Request Channel Selector: 00: Channel 4 01: Channel 5 10: Channel 6 11: Channel 7 Default 00000 0
1:0
00
81
PRELIMINARY
DMA Register 26: DMAC2 DMA Command/Mask Register (Write Only) - I/O Address=0D4H I/O Read I/O Write Flip-Flop State Function 0 1 1 0 X X Undefined
CY82C693UB
Write single-bit in DMA Request Mask Register (leaving the rest unchanged)
DMA Request Mask Register Write Single Bit Format (This Register is used to mask DMA requests through software. Single-bit Software request masks can be generated with separate writes to this register or all channels can be masked using DMA Register 15.) Bit 7:3 2 Function Reserved DMA Request Mask Generation Control: 0: Clear the mask on the channel specified by bits[1:0] 1: Force a DMA Request on the channel specified by bits[1:0]. DMA Request Mask Channel Selector: 00: Channel 4 01: Channel 5 10: Channel 6 11: Channel 7 Default 00000 0
1:0
00
DMA Register 27: DMAC2 DMA Mode Register (Write Only) - I/O Address=0D6H I/O Read I/O Write Flip-Flop State Function 0 1 1 0 X X Undefined Write Mode Register
82
PRELIMINARY
Mode Register Format (Should be programmed for each channel.) Bit 7:6 Function DMA Mode Selection Control: 00: Demand Transfer Mode 01: Single Transfer Mode 10: Block Transfer Mode 11: Cascade Mode See DMA Controller description for details about each mode. Counter Direction Control: 0: Increment Address Counter After Each Transfer 1: Decrement Address Counter After Each Transfer
CY82C693UB
Default 00
5
0
4
Autoinitialization Control: 0: Disable Autoinitialization 1: Enable Autoinitialization Autoinitialization will restore the initial values into the Current Address Register and Word Count Register when the terminal count is reached. The channel will not automatically be masked if it is autoinitialized. DMA Transfer Type Selection Control: 00: Verify Transfer 01: Write Transfer 10: Read Transfer 11: Undefined (DO NOT USE) See DMA Controller description for details about each transfer type.
0
3:2
00
1:0
Channel Selector: 00 00: Channel 0 01: Channel 1 10: Channel 2 11: Channel 3 Each DMA channel has its own mode register, but they are all accessed through I/O Address 00BH. For Mode Register writes, bits[1:0] control which channel's mode register will be written. To read each channel's mode register, four sequential reads will walk through all of the mode registers. Clearing the Mode Register Counter (DMA Register 14) will start the read sequence at a known state (channel 0). During reads, the channel selector bits will be 11 regardless of the channel.
DMA Register 28: DMAC2 Address Space Expansion Flip-Flop Control Register (Write Only) - I/O Address=0D8H I/O Read I/O Write Flip-Flop State Function 0 1 1 0 X X Undefined Clear Flip-Flop (Flip-Flop=0). This is a special command. The data lines are ignored.
DMA Register 29: DMAC2 Master Clear Register (Write Only) - I/O Address=0DAH I/O Read I/O Write Flip-Flop State Function 0 1 1 0 X X Undefined Perform Master Clear. This is a special command. The data lines are ignored.
DMA Register 30: DMAC2 DMA Mask Clear Register (Write Only) - I/O Address=0DCH I/O Read I/O Write Flip-Flop State Function 0 1 1 0 X X Undefined Clear DMA Request Mask Bits (Unmask all DMA requests). This is a special command. The data lines are ignored.
83
PRELIMINARY
DMA Register 31: DMAC2 Request Mask Register Control (Read/Write) - I/O Address=0DEH I/O Read I/O Write Flip-Flop State Function 0 1 1 0 X X Read DMA Request Mask Register Write DMA Request Mask Register
CY82C693UB
DMA Request Mask Register Read and Write All Bits Format (This register is cleared on CPURST.) Bit 7:4 3 Function Reserved DMA Channel 7 Request Mask: 0: Channel 7 Not Masked 1: Channel 7 Masked DMA Channel 6 Request Mask: 0: Channel 6 Not Masked 1: Channel 6 Masked DMA Channel 5 Request Mask: 0: Channel 5 Not Masked 1: Channel 5 Masked DMA Channel 4 Request Mask: 0: Channel 4 Not Masked 1: Channel 4 Masked Default 0000 0
2
0
1
0
0
0
DMA Register 32: DMAC1 Channel 2 Page Address Register (Read/Write) Bit 7:0 Function
- Index=081H
Default 00000000
Page Address (Address bits 23-16) for DMAC1 (8-bit DMA Controller), Channel 2
DMA Register 33: DMAC1 Channel 3 Page Address Register (Read/Write) Bit 7:0 Function
- Index=082H
Default 00000000
Page Address (Address bits 23-16) for DMAC1 (8-bit DMA Controller), Channel 3
DMA Register 34: DMAC1 Channel 1 Page Address Register (Read/Write) Bit 7:0 Function
- Index=083H
Default 00000000
Page Address (Address bits 23-16) for DMAC1 (8-bit DMA Controller), Channel 1
DMA Register 35: DMAC1 Channel 0 Page Address Register (Read/Write) Bit 7:0 Function
- Index=087H
Default 00000000
Page Address (Address bits 23-16) for DMAC1 (8-bit DMA Controller), Channel 0
DMA Register 36: DMAC2 Channel 6 Page Address Register (Read/Write) Bit 7:0 Function
- Index=089H
Default 00000000
Page Address (Address bits 23-16) for DMAC2 (16-bit DMA Controller), Channel 6
DMA Register 37: DMAC2 Channel 7 Page Address Register (Read/Write) Bit 7:0 Function
- Index=08AH
Default 00000000
Page Address (Address bits 23-16) for DMAC2 (16-bit DMA Controller), Channel 7
84
PRELIMINARY
DMA Register 38: DMAC2 Channel 5 Page Address Register (Read/Write) Bit 7:0 Function Page Address (Address bits 23-16) for DMAC2 (16-bit DMA Controller), Channel 5
CY82C693UB
- Index=08BH
Default 00000000
DMA Register 39: DMAC1 Extended Mode Control (Write Only) - I/O Address=40BH I/O Read I/O Write Flip-Flop State Function 0 1 1 0 X X Undefined Write DMA Request Mask Register
DMAC1 Extended Mode Control Register Format (This register is cleared on CPURST.) Bit 7:6 5:4 Function Reserved DMA Cycle Timing Mode: 00: Compatible Timing 01: Type "A" Timing 10: Type "B" Timing 11: Type "F" Timing DMA Channel 3 Select: 0: Channel 3 Not Selected 1: Channel 3 Selected DMA Channel 2 Select: 0: Channel 2 Not Selected 1: Channel 2 Selected DMA Channel 1 Select: 0: Channel 1 Not Selected 1: Channel 1 Selected DMA Channel 0 Select: 0: Channel 0 Not Selected 1: Channel 0 Selected Default 00 00
3
0
2
0
1
0
0
0
DMA Register 40: DMAC1 Channel 2 High Page Address Register (Read/Write) Bit 7:0 Function
- Index=481H
Default 00000000
High Page Address (Address bits 31-24) for DMAC1 (8-bit DMA Controller), Channel 2
DMA Register 41: DMAC1 Channel 3 High Page Address Register (Read/Write) Bit 7:0 Function
- Index=482H
Default 00000000
High Page Address (Address bits 31-24) for DMAC1 (8-bit DMA Controller), Channel 3
DMA Register 42: DMAC1 Channel 1 High Page Address Register (Read/Write) Bit 7:0 Function
- Index=483H
Default 00000000
High Page Address (Address bits 31-24) for DMAC1 (8-bit DMA Controller), Channel 1
DMA Register 43: DMAC1 Channel 0 High Page Address Register (Read/Write) Bit 7:0 Function
- Index=487H
Default 00000000
High Page Address (Address bits 31-24) for DMAC1 (8-bit DMA Controller), Channel 0
85
PRELIMINARY
DMA Register 44: DMAC2 Channel 6 High Page Address Register (Read/Write) Bit 7:0 Function
CY82C693UB
- Index=489H
Default 00000000
High Page Address (Address bits 31-24) for DMAC2 (16-bit DMA Controller), Channel 6
DMA Register 45: DMAC2 Channel 7 High Page Address Register (Read/Write) Bit 7:0 Function
- Index=48AH
Default 00000000
High Page Address (Address bits 31-24) for DMAC2 (16-bit DMA Controller), Channel 7
DMA Register 46: DMAC2 Channel 5 High Page Address Register (Read/Write) Bit 7:0 Function
- Index=48BH
Default 00000000
High Page Address (Address bits 31-24) for DMAC2 (16-bit DMA Controller), Channel 5
DMA Register 47: DMAC2 Extended Mode Control (Write Only) - I/O Address=4D6H I/O Read I/O Write Flip-Flop State Function 0 1 1 0 X X Undefined Write DMA Request Mask Register
DMAC2 Extended Mode Control Register Format (This register is cleared on CPURST.) Bit 7:6 5:4 Function Reserved DMA Cycle Timing Mode: 00: Compatible Timing 01: Type "A" Timing 10: Type "B" Timing 11: Type "F" Timing DMA Channel 7 Select: 0: Channel 7 Not Selected 1: Channel 7 Selected DMA Channel 6 Select: 0: Channel 6 Not Selected 1: Channel 6 Selected DMA Channel 5 Select: 0: Channel 5 Not Selected 1: Channel 5 Selected DMA Channel 4 Select: 0: Channel 4 Not Selected 1: Channel 4 Selected Default 00 00
3
0
2
0
1
0
0
0
86
PRELIMINARY
CY82C693UB IDE (Bus Mastering) DMA Controller Registers
The CY82C693UB supports two channels of DMA for the IDE controller. IDE DMA is compatible with SFF-8038i (the Small Form Factor Committee specification defining bus mastering on IDE). Only 16-bit DMA operation is supported. The IDE DMA controller supports scatter-gather. Scatter-gather operation requires setting up a linked list of DMA information in memory (Physical Region Descriptor Table) and programSFF-8038i Registers Offset from Base Address Register 00H 01H 02H Bus Master IDE Command Register (Primary Channel) Reserved Bus Master IDE Status Register (Primary Channel)
CY82C693UB
ming the starting location of the linked-list into the DMA controller itself. The controller will issue master cycles on PCI to gather and load the DMA information (word count and starting address). After each DMA terminal count is reached, the next entry in the linked-list is loaded until the end of the list is reached. Some DMA IDE Registers are referenced to a Base Address + an offset. The base address should be programmed in PCI configuration space (see the "Bus Master IDE I/O Base Address Register").
R/W Readable/ Writable Do not access Readable/ WritableWriting a 1 clears the corresponding bit. Do not access Readable/ Writable Readable/ Writable Do not access Readable/ WritableWriting a 1 clears the corresponding bit. Do not access Readable/ Writable
03H 04H-07H 08H 09H 0AH
Reserved Bus Master IDE Descriptor Table Pointer Register (Primary Channel) Bus Master IDE Command Register (Secondary Channel) Reserved Bus Master IDE Status Register (Secondary Channel)
0BH 0CH-0FH
Reserved Bus Master IDE Descriptor Table Pointer Register (Secondary Channel)
Bus Master IDE Command Register Format (Offset+00H for Primary Channel; Offset +08H for Secondary Channel) Bit 7:4 3 Function Reserved Bus Master (DMA) Transfer Direction: 0: PCI bus master read. 1: PCI bus master write. NOTE: This bit must NOT be changed when the bus master function is active. Reserved Start/Stop Bus Master Transfer: Bus Master operation begins when this bit is written from a 0 to a 1. The controller will transfer data between the IDE device and memory when this bit is set. Master operation can be halted by writing a 0 to this bit. All state information is lost when a master operation is halted. Therefore, master operations cannot be halted and then resumed. Default 0000 0
2:1 0
00 0
87
PRELIMINARY
CY82C693UB
Bus Master IDE Status Register Format (Offset+02H for Primary Channel; Offset +0AH for Secondary Channel) Bit 7 Function Simplex Status (Read Only): 0: Two channels operate independently and can be used at the same time. 1: Only one channel may be used at a time. Drive 1 DMA Capability Status: 0: Drive 1 is not capable of DMA transfers. 1: Drive 1 is capable of DMA transfers. Drive 0 DMA Capability Status: 0: Drive 0 is not capable of DMA transfers. 1: Drive 0 is capable of DMA transfers. Reserved IDE Interrupt Pending: 0: No IDE Interrupt Pending 1: IDE Interrupt Pending. Writing a `1' to this bit will reset the status to "No IDE Interrupt Pending". IDE DMA Error Encountered: 0: No Error Detected 1: An Error Occurred in the Transfer of Data to/from Memory. Writing a `1' to this bit will reset the status to "No IDE Interrupt Pending". Bus Master IDE Active: 0: There is no bus master active on IDE. 1: The Start Bit has been set in the Command Register. This bit is cleared when the last transfer for a region is performed, where EOT for that region is set in the region descriptor. It is also cleared when the Start Bit is cleared in the Command Register. When this bit is read as '0', all data transferred from the drive during the previous bus master command is visible in system memory, unless the bus master command was aborted. Default 0
6
0
5
0
4:3 2
00 0
1
0
0
0
Bus Master IDE Descriptor Table Pointer Register Format (Offset+04H-07H for Primary Channel; Offset +0CH-0FH for Secondary Channel) Bit 31:2 1:0 Function Base Address of the Descriptor Table. Corresponds to PAD[31:2] of the address that the controller will read from to obtain the first Descriptor Table Entry. Reserved Default 00000000H 00
Bus Master IDE I/O Base Address Register (PCI Configuration Space, function 1, register address 20-23H) Bit 31:16 15:4 Function Reserved Bus Master Interface Base Address: This sets the Base Address (Corresponding to PAD[15:4]) that will be added with an offset value to access the SFF-8038i Registers. Reserved, hardwired to 00 Reserved Resource Type Indicator (Read Only): This bit is hardwired to '1' indicating that the base address field in this register maps to I/O space. Default 0000H 0000H
3:2 1 0
00 0 0
88
PRELIMINARY
hyperCache Specific (Not Required by SFF-8038i) Registers
CY82C693UB
The following registers define options/functions that are not explicitly covered by the SFF-8038i spec. Nonetheless, these registers should be programmed for complete operation. Bus Master IDE Channel 0 Configuration Register (I/O Address 22H with Data = 30 (Index Port); I/O Address 23H is the Data Port) Bit 7:3 2 Function Reserved. Will Return '00000' on read. IDE DMA Transfer Mode: 0: Multiple 1: Single IDE DMA Transfer Speed Mode: 00: Mode 0 01: Mode 1 10: Mode 2 11: Reserved Default 00000 0
1:0
00
Bus Master IDE Channel 1 Configuration Register (I/O Address 22H with Data = 31 (Index Port); I/O Address 23H is the Data Port) Bit 7:3 2 Function Reserved. Will Return '00000' on read. IDE DMA Transfer Mode: 0: Multiple 1: Single IDE DMA Transfer Speed Mode: 00: Mode 0 01: Mode 1 10: Mode 2 11: Reserved Default 00000 0
1:0
00
Bus Master IDE TimeOut Register (I/O Address 22H with Data = 32 (Index Port); I/O Address 23H is the Data Port) - Write Only Bit 7:0 Function IDE DMA time out counter value. This register provides the terminal count on a counter with a 14.318 MHz clock input. Therefore, to find the timeout period, multiply the value in this register by 69.8 ns. Default 28H
Bus Master IDE Test Register (I/O Address 22H with Data = 33 (Index Port); I/O Address 23H is the Data Port) Bit 7:0 Function Undefined on read; Must write 00000000 on writes to this register. Default 00000000
89
PRELIMINARY
CY82C693UB Interrupt Controller Registers
There are two Interrupt controllers cascaded together inside the CY82C693UB. (INTC1 and INTC2). The controllers each accept up to eight requests (from the Interrupt Request pins), resolve interrupt priority, assert the INTR pin to the CPU, and, in response to an interrupt acknowledge cycle, will return the appropriate Interrupt Vector (an address that points to the interrupt service routine). A subset of the interrupt request lines are dedicated for specific system operations. They include: IRQ0 - The output of the system timer inside the CY82C693UB; IRQ1 - The keyboard request interrupt; IRQ2 - The cascade between INTC1 and INTC2; IRQ8 - The alarm from the Real-Time-Clock; IRQ12 The mouse request interrupt; and IRQ13 - The coproccessor error signal. These interrupt requests are not generally available for other interrupt functions. IRQ0 and IRQ2 are not brought out to external CY82C693UB pins (the connection is made internally). The rest of the dedicated interrupts are available when CY82C693UB functions are disabled. IRQ1 is available on the KBCLK (keyboard clock) pin when the internal keyboard controller is disabled. IRQ8 is available on the PSRSTB (power supply to battery source signal for the RTC) when the internal RTC is disabled. IRQ12 is available on the MSCLK (mouse clock) pin when the internal keyboard controller is disabled. IRQ13 is available on the FERR pin IRQ[15:14], IRQ[11:9], and IRQ[7:3] are available for system use. There are traditional functions for these interrupt requests. However, the system designer can configure these inputs for many uses. The traditional uses are as follows: IRQ3 - Serial Port 2 interrupt request; IRQ4 - Serial Port 1 interrupt request; IRQ5 - Parallel Port 2 interrupt request; IRQ6 - Floppy Disk Controller interrupt request; IRQ7 - Parallel Port 1 interrupt request; IRQ9 - ISA/PCI slot interrupt request; IRQ10 ISA/PCI slot interrupt request; IRQ11 - ISA/PCI slot interrupt request; IRQ14 - Hard Disk interrupt request; and IRQ15 ISA/PCI slot interrupt request. When any number of interrupt requests are asserted to the CY82C693UB, bits are set in the Interrupt Request Register (IRR) corresponding to the asserted interrupt requests. The In Service Register (ISR) will store bits corresponding to all interrupt channels that are currently being serviced. The Interrupt Mask Register (IMR) will allow interrupt requests to be gated (masked off) by setting bits corresponding to the channels to be masked. All of the above registers output to priority resolution logic. The resolution logic will evaluate the inputs, determine a priority for interrupt servicing, assert INTR to the CPU, and latch the highest priority (non-masked) channel value into the ISR. A vector corresponding to the highest priority (non-masked) interrupt will be provided to the PCI bus in response to an Interrupt Acknowledge cycle. The sequence for handling a peripheral interrupt is as follows: 1. Interrupt requests (one or multiple) are issued to the CY82C693UB through the IRQ pins, the PCIINT pins, or the internal requestors. This sets the corresponding bit(s) in the IRR. 2. Using the values stored in the IRR, ISR, and IMR, the next interrupt to be serviced is determined. INTR is asserted to the CPU.
CY82C693UB
3. When the CPU recognizes the assertion of INTR, it responds with an Interrupt Acknowledge Cycle. The Interrupt Acknowledge Cycle is passed on to the PCI bus. 4. When the CY82C693UB sees a PCI Interrupt Acknowledge Cycle, it will respond with a vector (address corresponding to the appropriate Interrupt Service Routine). 5. The CPU uses the vector to jump to the Interrupt Service Routine and begins execution of the interrupt handler The ISR will be reset on an End-of-Interrupt (EOI). An EOI is a special command that the interrupt handler code must issue to the CY82C693UB. A specific EOI can be sent to the CY82C693UB to clear a specific bit in the ISR, or the highest priority interrupt can be cleared (non-specific). Masked interrupts will not be cleared for a non-specific EOI. If Automatic End-of-Interrupt (AEOI) is programmed, the highest priority (non-masked) interrupt bit will be cleared in the ISR after the Interrupt Acknowledge cycle The priority can be programmed to be fixed, a specific rotation, or automatic rotation. In fixed priority mode, Interrupt Request 0 (IR0) is the highest priority followed in descending order by IR1, IR8, IR9, IR10, IR11, IR12, IR13, IR14, IR15, IR3, IR4, IR5, IR6, and IR7 (the lowest priority). This priority scheme comes from the fact that INTC2 is cascaded through IR2 of INTC1. Fixed priority is the default. Rotation or interrupt polling must be programmed. If an interrupt has its bit set in the ISR, all lower priority interrupts will not cause the assertion of INTR to the CPU (until the ISR bit is cleared). Specific Rotation allows the highest priority to be changed. All Interrupt Requests wrap-around in priority (e.g., if IR3 is selected to highest priority, the priority changes to IR3-IR7 followed by IR0-IR2 for each controller in descending order.). If Automatic Rotation is programmed, the last Interrupt Request to be serviced is given lowest priority. Polling mode will inhibit the CY82C693UB from generating INTR to the CPU. The CPU must poll (read the IRR register) to determine which interrupt to take. The Interrupt Controllers are programmed using Initialization Command Words (ICWs) and Operational Command Words (OCWs). To initialize each controller, a sequence of four bytes must be sent to the corresponding controller. An I/O write to address 020H (for INTC1) and 0A0H (for INTC2) with 1 on bit 4 of the data bus will begin the initialization sequence. The interrupt controller will automatically reset the Initialization Word Count Register, latch ICW1 into the controller, select Fixed Priority, assign IR7 the highest priority, clear the Interrupt Mask Register, set the Slave mode address to 7 (for cascading), disable Special Mask Mode, and select the IRR for Status Read operations (the contents of the IRR will be returned on a Status Read). The next three I/O writes to address 021H (for INTC1) and 0A1H (for INTC2) will load ICW2 through ICW4 for each controller. Executing an I/O write to 020H (for INTC1) and 0A0H (for INTC2) will cause the ICW writing to terminate and will begin writing OCW2 or OCW3. The OCWs allow the controllers to be reconfigured during normal operation. OCW1 is located at I/O address 021H (for INTC1) and 0A1H (for INTC2) whenever the controller is not being initialized. OCW2 and OCW3 are at I/O location 020H (for INTC1) and 0A0H (for INTC2) with data bit 4 set to zero. Data bit 3 controls whether OCW2 (bit3=0) or OCW3 (bit3=1) is being written.
-
90
PRELIMINARY
ICW1: INTC1 Interrupt Initialization Command Word 1 (Write Only) - I/O Address=020H Bit 7:5 4 Function Reserved, must be 000 Controller Initialization Control: 0: This is an Operational Command Word Write 1: This is an Initialization Command Word Write (and begins the Initialization Sequence.)
CY82C693UB
Default 000 0
3
Controller Interrupt Request Control: 0: Edge-Triggered 1: Level-Sensitive If this bit is set to 1, the interrupt requests must remain active until after the Interrupt Acknowledge Cycle to return the proper vector. If the request goes away early, and no other interrupts are being requested, the vector returned will correspond to IR7. The interrupt request must be removed before the End-of-Interrupt to insure that a second spurious interrupt will not occur. Don't Care Controller Cascade Control: 0: Cascade Mode (for multiple interrupt controllers) 1: Single Mode (There are two controllers in the CY82C693UB. Therefore, this bit should NEVER be programmed to one.) ICW4 Write Status: 0: ICW4 write not required 1: ICW4 write required.
0
2 1
0 0
0
0
ICW2: INTC1 Interrupt Initialization Command Word 2 (Write Only) - I/O Address=021H Bit 7:3 Function Upper 5 bits of the interrupt vector. These will appear on AD[7:3] during the data phase of an interrupt acknowledge cycle. AD[2:0] are driven with the interrupt level that comes out of the priority resolution logic (0 through 7). Interrupt Request Level, Must write to 000. Default 00000
2:0
000
91
PRELIMINARY
ICW3: INTC1 Interrupt Initialization Command Word 3 (Write Only) - I/O Address=021H Bit 7
CY82C693UB
6
5
4
3
2
1
0
Function Slave Control IR7: 0: There is no slave controller connected to Interrupt Request 7 of this controller. 1: There is a slave controller connected to Interrupt Request 7 of this controller. NOTE: Must be set to 0. Slave Control IR6: 0: There is no slave controller connected to Interrupt Request 6 of this controller. 1: There is a slave controller connected to Interrupt Request 6 of this controller. NOTE: Must be set to 0. Slave Control IR5: 0: There is no slave controller connected to Interrupt Request 5 of this controller. 1: There is a slave controller connected to Interrupt Request 5 of this controller. NOTE: Must be set to 0. Slave Control IR4: 0: There is no slave controller connected to Interrupt Request 4 of this controller. 1: There is a slave controller connected to Interrupt Request 4 of this controller. NOTE: Must be set to 0. Slave Control IR3: 0: There is no slave controller connected to Interrupt Request 3 of this controller. 1: There is a slave controller connected to Interrupt Request 3 of this controller. NOTE: Must be set to 0. Slave Control IR2: 0: There is no slave controller connected to Interrupt Request 2 of this controller. 1: There is a slave controller connected to Interrupt Request 2 of this controller. NOTE: This bit should be set to 1 for INTC2 to function properly. Slave Control IR1: 0: There is no slave controller connected to Interrupt Request 1 of this controller. 1: There is a slave controller connected to Interrupt Request 1 of this controller. NOTE: Must be set to 0. Slave Control IR0: 0: There is no slave controller connected to Interrupt Request 0 of this controller. 1: There is a slave controller connected to Interrupt Request 0 of this controller. NOTE: Must be set to 0.
Default 0
0
0
0
0
0
0
0
ICW4: INTC1 Interrupt Initialization Command Word 4 (Write Only) - I/O Address=021H Bit 7:5 4 Function Reserved, Must be set to 000 Multiple Interrupt Control: 0: Disable Multiple Interrupt from the Same Channel 1: Enable Multiple Interrupt from the Same Channel This bit (when set) allows INTC2 to fully nest interrupts, when Cascaded with Fixed Priority, without being blocked by INTC1. Correct handling requires the CPU to issue non-specific EOIs to INTC2 and check its ISR when exiting an interrupt service routine. If the ISR contains zero, a non-specific EOI should be sent to INTC1. If the ISR contains anything other than zero, no command should be issued to INTC1. Buffered Mode: 0: Not Buffered 1: Buffered Master/Slave stored in buffer. Must be set to 0. Automatic End-of-Interrupt (AEOI) Control: 0: Disable AEOI 1: Enable AEOI AEOI should not be enabled if the system supports fully nested interrupts unless this controller is a Cascade Master. Microprocessor Mode: 0: Not x86 1: x86 NOTE: This bit must be set to 1. Default 000 0
3
0
2 1
0 0
0
0
92
PRELIMINARY
ICW1: INTC2 Interrupt Initialization Command Word 1 (Write Only) - I/O Address=0A0H Bit 7:5 4 Function Reserved, Must be 000 Controller Initialization Control: 0: This is an Operational Command Word Write 1: This is an Initialization Command Word Write (and begins the Initialization Sequence.)
CY82C693UB
Default 000 0
3
Controller Interrupt Request Control: 0: Edge-Triggered 1: Level-Sensitive If this is set to 1, the interrupt requests must remain active until after the Interrupt Acknowledge Cycle to return the proper vector. If the request goes away early, and no other interrupts are being requested, the vector returned will correspond to IR7. The interrupt request must be removed before the End-of-Interrupt to insure that a second spurious interrupt will not occur. Don't Care Controller Cascade Control: 0: Cascade Mode (for multiple interrupt controllers) 1: Single Mode (There are two controllers in the CY82C693UB. Therefore, this bit should NEVER be programmed to one.) ICW4 Write Status: 0: ICW4 write not required 1: ICW4 write required.
0
2 1
0 0
0
0
ICW2: INTC2 Interrupt Initialization Command Word 2 (Write Only) - I/O Address=0A1H Bit 7:3 Function Upper 5 bits of the interrupt vector. These will appear on AD[7:3] during the data phase of an interrupt acknowledge cycle. AD[2:0] are driven with the interrupt level that comes out of the priority resolution logic (0 through 7). Interrupt Request Level, Must write to 000. Default 00000
2:0
000
ICW3: INTC2 Interrupt Initialization Command Word 3 (Write Only) - I/O Address=0A1H Bit 7:3 2:0 Function Reserved (These bits must be set to zero) This is the slave mode address that the controller will respond to. This should be written to 02H for proper Cascade mode operation with INTC1. Default 00000 000
93
PRELIMINARY
ICW4: INTC2 Interrupt Initialization Command Word 4 (Write Only) - I/O Address=0A1H Bit 7:5 4 Function Don't Care
CY82C693UB
Default 000 0
Multiple Interrupt Control: 0: Disable Multiple Interrupts from the Same Channel 1: Enable Multiple Interrupts from the Same Channel This bit (when set) allows INTC2 to fully nest interrupts, when Cascaded with Fixed Priority, without being blocked by INTC1. Correct handling requires the CPU to issue non-specific EOIs to INTC2 and check its ISR when exiting an interrupt service routine. If the ISR contains zero, a non-specific EOI should be sent to INTC1. If the ISR contains anything other than zero, no command should be issued to INTC1. Buffered Mode: 0: Not Buffered 1: Buffered Master/Slave stored in buffer. Must be set to 0. Automatic End-of-Interrupt (AEOI) Control: 0: Disable AEOI 1: Enable AEOI AEOI should not be enabled if the system supports fully nested interrupts unless this controller is a Cascade Master. Microprocessor Mode: 0: Not x86 1: x86 NOTE: This bit must be set to 1.
3
0
2 1
0 0
0
0
OCW1: INTC1 Interrupt Operational Command Word 1 (Read/Write) - I/O Address=021H All Mask Bits are cleared by writing ICW1. Bit 7 Function IR7 Mask Control: 0: Not Masked 1: Masked IR6 Mask Control: 0: Not Masked 1: Masked IR5 Mask Control: 0: Not Masked 1: Masked IR4 Mask Control: 0: Not Masked 1: Masked IR3 Mask Control: 0: Not Masked 1: Masked IR2 Mask Control: 0: Not Masked 1: Masked IR1 Mask Control: 0: Not Masked 1: Masked IR0 Mask Control: 0: Not Masked 1: Masked Default 0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
94
PRELIMINARY
OCW2: INTC1 Interrupt Operational Command Word 2 (Write Only) - I/O Address=020H Bit 7:5 Function Command Control: 000: Clear Rotate in Auto EOI 001: Non-specific EOI Command 010: No Command 011: Specific EOI Command 100: Set Rotate on AEOI 101: Rotate on non-specific EOI 110: Specific Rotate Command 111: Rotate on specific EOI Controller Initialization Control: 0: This is an Operational Command Word Write 1: This is an Initialization Command Word Write (and begins the Initialization Sequence.) Operational Command Word Selection Control: 0: This is a write to OCW2 1: This is a write to OCW3
CY82C693UB
Default 000
4
0
3
0
2:0
These three bits select which interrupt channel is controlled by the specific commands. 000: Channel 0 100: Channel 4 001: Channel 1 101: Channel 5 010: Channel 2 110: Channel 6 011: Channel 3 111: Channel 7
000
OCW3: INTC1 Interrupt Operational Command Word 3 (Write Only) - I/O Address=020H Bit 7 6 Function Reserved (Must be set to zero) Set/Reset Special Mask Mode Control: 0: Disable Set/Reset of Special Mask Mode Bit 1: Enable Set/Reset of Special Mask Mode Bit This bit allows the Special Mask Mode bit (bit 5) to be protected. When this bit is disabled, bit 5 will not change. Special Mask Mode Control: 0: Disable Special Mask Mode 1: Enable Special Mask Mode In Special Mask Mode, writing a 1 to any bit position inhibits interrupts on the associated channel. Writing a 0 to any bit position enables interrupts on the associated channel. The mask is handled by causing the priority resolution logic to ignore the condition of the ISR. Controller Initialization Control: 0: This is an Operational Command Word Write 1: This is an Initialization Command Word Write (and begins the Initialization Sequence.) Operational Command Word Selection Control: 0: This is a write to OCW2 1: This is a write to OCW3 Interrupt Polling Control: 0: Disable Polling Cycle 1: Enable Polling Cycle In systems where interrupts are polled, writing a 1 to this bit causes an interrupt status word to be returned on the next I/O read to the controller. Bit 7 of the data will give interrupt pending status (0 for no interrupts pending, 1 for interrupts pending). The level of the highest pending interrupt is encoded on bits 2-0. The IRR will not change until the read cycle is completed. The PM bit will automatically reset. Status Control: 00: Disable Status Read 01: Disable Status Read 10: Contents of the IRR will be read on a status read. 11: Contents of the ISR will be read on a status read. Default 0 0
5
0
4
0
3
0
2
0
1:0
00
95
PRELIMINARY
OCW1: INTC2 Interrupt Operational Command Word 1 (Read/Write) - I/O Address=0A1H All Mask Bits are cleared by writing ICW1. Bit 7 Function IR7 Mask Control: 0: Not Masked 1: Masked IR6 Mask Control: 0: Not Masked 1: Masked IR5 Mask Control: 0: Not Masked 1: Masked IR4 Mask Control: 0: Not Masked 1: Masked IR3 Mask Control: 0: Not Masked 1: Masked IR2 Mask Control: 0: Not Masked 1: Masked IR1 Mask Control: 0: Not Masked 1: Masked IR0 Mask Control: 0: Not Masked 1: Masked
CY82C693UB
Default 0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
OCW2: INTC2 Interrupt Operational Command Word 2 (Write Only) - I/O Address=0A0H Bit 7:5 Function Command Control: 000: Clear Rotate in Auto EOI 001: Non-specific EOI Command 010: No Command 011: Specific EOI Command 100: Set Rotate on AEOI 101: Rotate on non-specific EOI 110: Specific Rotate Command 111: Rotate on specific EOI Controller Initialization Control: 0: This is an Operational Command Word Write 1: This is an Initialization Command Word Write (and begins the Initialization Sequence.) Operational Command Word Selection Control: 0: This is a write to OCW2 1: This is a write to OCW3 These three bits select which interrupt channel is controlled by the specific commands. 000: Channel 0 (IRQ8) 100: Channel 4 (IRQ12) 001: Channel 1 (IRQ9) 101: Channel 5 (IRQ13) 010: Channel 2 (IRQ10) 110: Channel 6 (IRQ14) 011: Channel 3 (IRQ11) 111: Channel 7 (IRQ15) Default 000
4
0
3
0
2:0
000
96
PRELIMINARY
OCW3: INTC2 Interrupt Operational Command Word 3 (Write Only) - I/O Address=0A0H Bit 7 6 Function Reserved (Must be set to zero) Set/Reset Special Mask Mode Control: 0: Disable Set/Reset of Special Mask Mode Bit 1: Enable Set/Reset of Special Mask Mode Bit This bit allows the Special Mask Mode bit (bit 5) to be protected. When this bit is disabled, bit 5 will not change.
CY82C693UB
Default 0 0
5
Special Mask Mode Control: 0: Disable Special Mask Mode 1: Enable Special Mask Mode In Special Mask Mode, writing a 1 to any bit position inhibits interrupts on the associated channel. Writing a 0 to any bit position enables interrupts on the associated channel. The mask is handled by causing the priority resolution logic to ignore the condition of the ISR. Controller Initialization Control: 0: This is an Operational Command Word Write 1: This is an Initialization Command Word Write (and begins the Initialization Sequence.) Operational Command Word Selection Control: 0: This is a write to OCW2 1: This is a write to OCW3 Interrupt Polling Control: 0: Disable Polling Cycle 1: Enable Polling Cycle In systems where interrupts are polled, writing a 1 to this bit causes an interrupt status word to be returned on the next I/O read to the controller. Bit 7 of the data will give interrupt pending status (0 for no interrupts pending, 1 for interrupts pending). The level of the highest pending interrupt is encoded on bits 2-0. The IRR will not change until the read cycle is completed. The PM bit will automatically reset. Status Control: 00: Disable Status Read 01: Disable Status Read 10: Contents of the IRR will be read on a status read. 11: Contents of the ISR will be read on a status read.
0
4
0
3
0
2
0
1:0
00
2CY82C693UB
97
PRELIMINARY
CY82C693UB Timer/Counter Registers
The CY82C693UB contains a timer/counter which can be used to generate a speaker tone, periodic interrupts, and the ISA refresh. There are three, individually operated, 16-bit counters. The output of counter 0 is internally hardwired to the IRQ0 input of DMA controller 1. The output of counter 1 is tied to the refresh request logic for ISA refresh. The output of counter 2 is output on the SPKR (speaker output pin).
CY82C693UB
For proper operation, each counter must be programmed before use. Each counter is programmed by writing to the "Timer Control Register" with an appropriate control word and then writing an initial count to the associated counter's register. A count value may be read by reading the associated counter's register.
Timer/Counter Register 0: Timer Control Word Register (Write Only) - Address=043H Bit 7:0 Function Control Register Default 00000000
Timer Control Word Register Format (Not Read-Back Command or Counter Latch Command) Bit 7:6 Function Counter Select: 00: Counter 0 01: Counter 1 10: Counter 2 11: Read-Back Command (See Timer Control Word Register Format for Read-Back Command) Read/Write Select: 00: Counter Latch Command (See Timer Control Word Register Format for CounterLatch Command) 01: Read/Write Least Significant Byte of Counter 10: Read/Write Most Significant Byte of Counter 11: Read/Write Least Significant Byte followed by Most Significant Byte of Counter Counter Mode Select: 000: Out signal on end of count=0 cycle. 001: Hardware re-triggerable one-shot. X10: Rate Generator (Divide by n counter). X11: Square Wave Output. 100: Software triggered strobe. 101: Hardware triggered strobe. Binary/BCD Countdown Select: 0: Binary countdown 1: BCD countdown Timer Control Word Register Format (Read-Back Command) Bit 7:6 5 Function Counter Select: 11: Read-Back Command (Must be 11 for Read-Back Command) Latch Count of Selected Counter(s) Control: 0: Do not latch current count value 1: Latch current count value Latch Status of Selected Counter(s) Control: 0: Do not latch current status value 1: Latch current status value Counter 2 Select: 0: Counter 2 not selected 1: Counter 2 selected Counter 1 Select: 0: Counter 1 not selected 1: Counter 1 selected Counter 0 Select: 0: Counter 0 not selected 1: Counter 0 selected Reserved Default 11 0 Default 00
5:4
00
3:1
000
0
0
4
0
3
0
2
0
1
0
0
0
98
PRELIMINARY
Timer Control Word Register Format (Counter Latch Command) Bit 7:6 Function
CY82C693UB
Default 00
Counter Select: 00: Latch Counter 0 01: Latch Counter 1 10: Latch Counter 2 11: Read-Back Command (See Timer Control Word Register Format for Read-Back Command) Read/Write Select: 00: Counter Latch Command (Must be 00 for Counter Latch Command) Reserved, Must be 0000
5:4 3:0
00 0000
Timer/Counter Register 1: Counter 0 Register (Read/Write Except for Read-Back Status Command) - Address=040H Bit 7:0 Function Counter 0 Count Value Counter 0 Register Format (Read-Back Status Command - Read Only) Bit 7 6 Function Counter OUT State Count available for reading Status: 0: The count value has not been loaded into the counting element. 1: The count value is available for reading. Read/Write Status: 00: Counter Latch Command 01: Read/Write Least Significant Byte of Counter 10: Read/Write Most Significant Byte of Counter 11: Read/Write Least Significant Byte followed by Most Significant Byte of Counter Counter Mode Status: 000: Out signal on end of count=0 cycle 001: Hardware re-triggerable one-shot X10: Rate Generator (Divide by n counter) X11: Square Wave Output 100: Software triggered strobe 101: Hardware triggered strobe Binary/BCD Countdown Status: 0: Binary countdown 1: BCD countdown Default 0 0 Default 00000000
5:4
00
3:1
000
0
0
Timer/Counter Register 2: Counter 1 Register (Read/Write Except for Read-Back Status Command) - Address=041H Bit 7:0 Function Counter 1 Count Value Default 00000000
99
PRELIMINARY
Counter 1 Register Format (Read-Back Status Command - Read Only) Bit 7 6 Function Counter OUT State Count available for reading Status: 0: The count value has not been loaded into the counting element. 1: The count value is available for reading.
CY82C693UB
Default 0 0
5:4
Read/Write Status: 00: Counter Latch Command 01: Read/Write Least Significant Byte of Counter 10: Read/Write Most Significant Byte of Counter 11: Read/Write Least Significant Byte followed by Most Significant Byte of Counter Counter Mode Status: 000: Out signal on end of count=0 cycle 001: Hardware re-triggerable one-shot X10: Rate Generator (Divide by n counter) X11: Square Wave Output 100: Software triggered strobe 101: Hardware triggered strobe Binary/BCD Countdown Status: 0: Binary countdown 1: BCD countdown
00
3:1
000
0
0
Timer/Counter Register 3: Counter 2 Register (Read/Write Except for Read-Back Status Command) - Address=042H Bit 7:0 Function Counter 2 Count Value Counter 2 Register Format (Read-Back Status Command - Read Only) Bit 7 6 Function Counter OUT State Count available for reading Status: 0: The count value has not been loaded into the counting element. 1: The count value is available for reading. Read/Write Status: 00: Counter Latch Command 01: Read/Write Least Significant Byte of Counter 10: Read/Write Most Significant Byte of Counter 11: Read/Write Least Significant Byte followed by Most Significant Byte of Counter Counter Mode Status: 000: Out signal on end of count=0 cycle 001: Hardware re-triggerable one-shot X10: Rate Generator (Divide by n counter) X11: Square Wave Output 100: Software triggered strobe 101: Hardware triggered strobe Binary/BCD Countdown Status: 0: Binary countdown 1: BCD countdown Default 0 0 Default 00000000
5:4
00
3:1
000
0
0
100
PRELIMINARY
CY82C693UB Real-Time-Clock Registers
The RTC inside the CY82C693UB contains a time-of-day clock, an interrupt generating alarm, a 100 year calendar, a software controlled periodic interrupt, and 242 bytes of battery-backable static RAM (for scratch data). An external battery and a 6 pF or a 12 pF 32.768-kHz crystal in parallel with a 6-pF capacitor are all that must be provided to enable the RTC to keep time in battery-backed mode. Leap-year and daylight savings time will be automatically adjusted. RTC registers are accessed using I/O addresses 070H and 071H. The index address of the register must first be placed in the RTC's Index Address Register. This is loaded through an I/O write to address 070H with the register index as the write data. Following the I/O write to 070H, an I/O access (read or
CY82C693UB
write) to address 071H will read or write the contents of the appropriate RTC register. The scratch data is broken into two separate blocks. Access to the blocks is controlled through I/O accesses to different addresses. The lower 128 register bytes (this includes the Clock Data) are accessed using I/O writes to address 070H (with register index as the write data) followed by I/O reads or writes to address 071H. The data for the I/O access to 071H is the contents of the desired register. For the upper 128 scratch RAM bytes, the scratch RAM address should be written to I/O address 072H followed by a data read or write to I/O address 073H.
PLEASE NOTE: Where the registers are called out BCD (binary coded decimal), the values must be written/read as BCD values (Not Hexadecimal). RTC Register 0: Seconds Byte (Read/Write except for bit 7 which is always 0) Bit 7:0 Function BCD representation of seconds (must be in the range 00-59)
- Index=00H
Default 00000000
RTC Register 1: Seconds Alarm (Read/Write) Bit 7:0 Function
- Index=01H
Default 00000000
BCD representation of seconds alarm (must be in the range 00-59) If bit 7:6=11, then a 1 second periodic interrupt will occur.
RTC Register 2: Minutes Byte (Read/Write) Bit 7:0 Function
- Index=02H
Default 00000000
BCD representation of minutes (must be in the range 00-59)
RTC Register 3: Minutes Alarm (Read/Write) Bit 7:0 Function
- Index=03H
Default 00000000
BCD representation of minutes alarm (must be in the range 00-59)
RTC Register 4: Hours Byte (Read/Write) Bit 7:0 Function
- Index=04H
Default 00000000
BCD representation of hours 12-hour Mode: Must be in the range 01-12 (AM) or 81-92 (PM) 24-hour Mode: Must be in the range 00-23
RTC Register 5: Hours Alarm (Read/Write) Bit 7:0 Function
- Index=05H
Default 00000000
BCD representation of hours alarm 12-hour Mode: Must be in the range 01-12 (AM) or 81-92 (PM) 24-hour Mode: Must be in the range 00-23
RTC Register 6: Day-of-the-Week Byte (Read/Write) Bit 7:0 Function
- Index=06H
Default 00000000
BCD representation of day-of-the-week (must be in the range 01-07); 01=Sunday.
101
PRELIMINARY
RTC Register 7: Day-of-the-Month Byte (Read/Write) Bit 7:0 Function BCD representation of day-of-the-month (must be in the range 01-31)
CY82C693UB
Default 00000000
- Index=07H
RTC Register 8: Month Byte (Read/Write) Bit 7:0 Function
- Index=08H
Default 00000000
BCD representation of month (must be in the range 01-12)
RTC Register 9: Year Byte (Read/Write) Bit 7:0 Function
- Index=09H
Default 00000000
BCD representation of year (must be in the range 00-99)
RTC Register 10: Control/Status Register A (Read/Write except for bit 7 which is Read Only) Bit 7 Function
- Index=0AH
Default 0
Update In Progress (UIP): 0: There is no clock update about to occur (guaranteed for 244 s) 1: An update cycle is about to occur or is occurring. Data read from the clock words will be invalid. This bit goes high 244 s prior to an update and remains active for an additional 2 ms after the update begins. This bit can be cleared by writing a 1 to bit 7 of RTC register 11. Divider/Prescaler on the RTC: 000: 4.194304 MHz Oscillator 001: 1.048576 MHz Oscillator 010: 32.768 kHz Oscillator (Recommended Setting) 1XX: Reset Divider Periodic Interrupt Rate Control: 32.768-KHz Oscillator 0000: No Periodic Interrupts 0001: 3.90526 ms 0010: 7.8125 ms 0011: 122.070 s 0100: 244.141 s 0101: 488.281 s 0110: 976.562 s 0111: 1.953125 ms 1000: 3.90625 ms 1001: 7.8125 ms 1010: 15.625 ms 1011: 31.25 ms 1100: 62.5 ms 1101: 125 ms 1110: 250 ms 1111: 500 ms Other Frequencies No Periodic Interrupts 30.517 s 61.035 s 122.070 s 244.141 s 488.281 s 976.562 s 1.953125 ms 3.90625 ms 7.8125 ms 15.625 ms 31.25 ms 62.5 ms 125 ms 250 ms 500 ms
6:4
000
3:0
0000
102
PRELIMINARY
RTC Register 11: Control/Status Register B (Read/Write) Bit 7 Function Update Cycle Control: 0: Enable Update Cycles 1: Disable Update Cycles, and abort any Update Cycle In Progress This bit is not changed when PSRSTB is asserted. Periodic Interrupt Control: 0: Disable Periodic Interrupt Generation 1: Enable Periodic Interrupt Generation This bit is cleared when PSRSTB is asserted.
CY82C693UB
- Index=0BH
Default 0
6
0
5
Alarm Interrupt Control: 0: Disable Alarm Interrupt Generation 1: Enable Alarm Interrupt Generation Alarm interrupts will be generated when the time matches the values programmed into the alarm register fields. This bit is cleared when PSRSTB is asserted. Update-Ended Interrupt Control: 0: Disable Update-Ended Interrupt Generation 1: Enable Update-Ended Interrupt Generation Update-Ended interrupts will be generated when an update cycle is completed. This can be used to tell the CPU that its data may be read from the clock data registers. This bit is cleared when PSRSTB is asserted. Square Wave Control: 0: Disable Square Wave Generation 1: Enable Square Wave Generation Data Mode: 0: BCD 1: Binary Hour Format Control: 0: 12-hour clock format 1: 24-hour clock format This bit is not changed when PSRSTB is asserted. Daylight Savings Time Control: 0: Disable Daylight Savings Time Change 1: Enable Daylight Savings Time Change Setting this bit will cause the update cycle to change the time automatically for Daylight Savings Time. The changes take place on the last Sunday in April and the last Sunday in October. This bit is not changed when PSRSTB is asserted.
0
4
0
3
0
2
0
1
0
0
0
103
PRELIMINARY
RTC Register 12: Control/Status Register C (Read Only) Bit 7 Function
CY82C693UB
- Index=0CH
Default
Interrupt Request Flag: 0 0: No RTC Interrupts have occurred. 1: An RTC Interrupt has occurred. The specific interrupt flags (bits 6-4 of this register) and the interrupt enable bits (bits 6-4 of RTC Register 11) indicate which event(s) caused the interrupt to occur. This bit is cleared by the assertion of PSRSTB or a read to this register. Periodic Interrupt Flag: 0: The period timer has not reached its terminal count. 1: The period timer has reached its terminal count Note: An interrupt will not be generated and bit 7 will not be set if Periodic Interrupts are disabled. This bit is cleared by the assertion of PSRSTB or a read to this register. Alarm Interrupt Flag: 0: The clock did not match the alarm values. 1: The clock did match the alarm values. Note: An interrupt will not be generated and bit 7 will not be set if Alarm Interrupts are disabled. This bit is cleared by the assertion of PSRSTB or a read to this register. Update-Ended Interrupt Flag: 0: An Update Cycle did not end 1: An Update Cycle did end Note: An interrupt will not be generated and bit 7 will not be set if Update-Ended Interrupts are disabled. This bit is cleared by the assertion of PSRSTB or a read to this register. Reserved (Read as all zeroes). 0
6
5
0
4
0
3:0
0000
RTC Register 13: Control/Status Register D (Read Only) Bit 7 Function
- Index=0DH
Default 0
Valid RAM and Time Flag: 0: The contents of the RAM and Time are not guaranteed to be valid 1: The contents of the RAM and Time are valid Reserved (Read as all zeroes).
6:0
0000000
RTC Registers 14-127: Battery-Backable Scratch Block 1 (Read/Write) - Indices=0EH-7FH Bit 7:0 Function User Defined Default 00000000
RTC Registers 128-255: Battery-Backable Scratch Block 2 (Read/Write) - Indices=80H-FFH NOTE: These Registers are accessed through I/O ports 072H and 073H (not 070H and 071H-the ports for the other RTC registers) Bit 7:0
3CY82C693UB
Function User Defined
4CY82C693UB
Default 00000000
104
PRELIMINARY
CY82C693UB Keyboard/Mouse Controller Registers
The Keyboard controller inside the CY82C693UB is capable of supporting both AT and PS/2 modes of operation. In PS/2 mode, a PS/2 style mouse is supported without the need of an external controller. The keyboard controller processes scan codes whenever a keyboard key is pressed and released. When a key is pressed, a "make" code is sent from the controller in the keyboard to the controller in the CY82C693UB. If the key is not released immediately, "make" codes are continually sent to the system. When the key is finally released, a "break" is recognized by the system. Special function keys (such as the key or the key) are used to set status flags inside the keyboard controller. The status flags can alter the function of other keystrokes.
CY82C693UB
The keyboard controller interrupts the processor through IRQ1 and the mouse controller interrupts the processor through IRQ12. These interrupts will cause the operating systems to enter their scan code interpretation routines. The keyboard/mouse controller control registers are accessed using I/O port locations 64H and 60H. Status is read, by performing a read to I/O port 64H. The keyboard controller's input buffer may be addressed at I/O port 60H or 64H (Data bytes are written to 60H and command bytes are written to 64H). The output buffer can contain scan codes from the keyboard or any requested data bytes from the controller. It can be accessed by reading I/O port 60H.
Keyboard/Mouse Register 0: Status Register (Read Only) - I/O Read to address 64H Bit 7 Function Parity Error Detection: 0: No parity error was transmitted from the keyboard. 1: A parity error was detected in the last byte transmitted. The keyboard must transmit odd parity. Timeout Detection: 0: No timeout was detected. 1: A timeout occurred during the transmission of data between the controller and the keyboard. Mouse Output Buffer Full Flag: 0: No mouse data is present in the output buffer. 1: Mouse data is present in the output buffer. Default 0
6
0
5
0
4
Keyboard Lock Status: 0 0: KEYLOCK is active. The keyboard controller is inhibited from receiving scan codes. 1: KEYLOCK is inactive. Normal operation. Command/Data Flag: 0: Data byte has been written to 60H. 1: command byte has been written to 64H. This bit can be used to indicate to the system whether the byte in the input buffer is a command byte or a data byte. System Flag: This bit will reflect the value written to the Set System Flag bit of the command byte. Input Buffer (Port 60H or 64H) Full Flag: 0: No data is present in the input buffer. 1: Data is present in the input buffer. A read of the input buffer will reset this bit to zero. Output Buffer (Port 60H only) Full Flag: 0: No data is present in the output buffer. 1: Data is present in the output buffer. A read of the output buffer will reset this bit to zero. 0
3
2 1
0 0
0
0
105
PRELIMINARY
CY82C693UB
Keyboard/Mouse Register 1: Command Byte Register. Stored in keyboard RAM at location 20H; A 20H command must be written to the input buffer at 64H, Data is accessed at 60H. Bit 7 6 Function Reserved. Must be set to zero. Scan Code Translation: 0: Do not translate scan codes. 1: Scan codes are translated to AT scan codes. Mouse Interface Control: 0: Enable PS/2 mouse interface. 1: Disable PS/2 mouse interface. Keyboard Interface Control: 0: Enable keyboard interface. 1: Disable keyboard interface. When the keyboard interface is disabled, the KBCLK signal is driven LOW. Nothing can be sent or received. KEYLOCK Override Control: 0: Normal Operation. 1: Override the KEYLOCK signal. This will cause the keyboard to be unlocked regardless of the state of the KEYLOCK signal. System Flag: 0: Report 0 on bit 2 of Status Register during status reads. 1: Report 1 on bit 2 of Status Register during status reads. Output Buffer Filled with Mouse Data Interrupt Control: 0: Will not send IRQ12 whenever the output buffer is filled with mouse data. 1: Will send IRQ12 whenever the output buffer is filled with mouse data. Output Buffer Filled with Keyboard Data Interrupt Control: 0: Will not send IRQ1 whenever the output buffer is filled with keyboard data. 1: Will send IRQ1 whenever the output buffer is filled with keyboard data. Default 0 0
5
0
4
0
3
0
2
0
1
0
0
0
106
PRELIMINARY
CY82C693UB
System to Controller Command Set. These commands are executed by writing them to the input register through I/O port 064H. If data is accompanied with the command, it must be read/written to I/O port 060H. Command 20H Description Read controller's command byte: The controller will put the contents of the current command byte into the output port. The command byte format is given above (Keyboard/Mouse Register 1). Read controller's RAM: The controller will put the contents of the controller's RAM addressed by bits 5 through 0 of the command into the output port. Write controller's command byte: The controller will write the new command byte. It uses the next data written to I/O port 60H for the new command byte data. The command byte format is given above (Keyboard/Mouse Register 1). Write controller's RAM: The controller will write the RAM location addressed by bits 5 through 0 of the command. It uses the next data written to I/O port 60H for the new RAM data. Check for installed password: The controller will test for a password. If a password is installed, FAH will be placed in the output buffer. If no password is installed, F1H is placed in the output buffer. Load password: The keyboard controller will load the contents of the input buffer into a password location and will not stop storing the password until NULL (00H) is detected. NULL will be stored as the last byte of the password. Enable Password Security: The keyboard controller will check the installed password against the keyboard input for a match before allowing scan codes to be passed to the system. Disable Mouse interface: This command will set bit 5 of the command byte to 1. This will cause the MSECLK signal to be driven low, effectively disabling mouse operation. Enable Mouse interface: This command will reset bit 5 of the command byte to 0. Mouse operation will be allowed. Mouse interface test: The controller will test the MSECLK and MSEDATA signals. The following status will be placed in the output buffer: 00H: No Error Detected 01H: MSECLK is stuck low. 02H: MSECLK is stuck high. 03H: MSEDATA is stuck low. 04H: MSEDATA is stuck high. Execute Self-Test: The internal diagnostic self-test will be executed. If no errors are detected, 55H will be placed in the output buffer. Keyboard interface test: The controller will test the KBCLK and KBDATA signals. The following status will be placed in the output buffer: 00H: No Error Detected 01H: KBCLK is stuck low. 02H: KBCLK is stuck high. 03H: KBDATA is stuck low. 04H: KBDATA is stuck high. Disable Keyboard interface: This command will set bit 4 of the command byte to 1. This will cause the KBCLK signal to be driven low, effectively disabling keyboard operation. Enable Keyboard interface: This command will reset bit 4 of the command byte to 0. Keyboard operation will be allowed. Read controller's input port: This command will cause the controller to read its input port and place the contents into the controller's output buffer.
21H-3FH
60H
61H-7FH
A4H
A5H
A6H
A7H
A8H A9H
AAH
ABH
ADH
AEH C0H
107
PRELIMINARY
CY82C693UB
System to Controller Command Set. (continued) These commands are executed by writing them to the input register through I/O port 064H. If data is accompanied with the command, it must be read/written to I/O port 060H. Command D0H Description Read controller's output port: This command will cause the controller to read its output port and place the contents into the controller's input buffer. Write controller's output port: This command will cause the controller to take the next data that is written to 60H and place it into the controller's output port. Write keyboard output buffer: This command will cause the controller to take the next data that is written to 60H and place it into the controller's output buffer. Write mouse output buffer: This command will cause the controller to take the next data that is written to 60H and place it into the controller's mouse output buffer. Write to mouse: This command will cause the controller to take the next data that is written to 60H and transmit it to the mouse. Read Test Inputs: T0 and T1 (KBCLK and KBDATA inputs) are read by the controller and placed in the output buffer. Bit 0 represents T0 and bit 1 represents T1. Active Output Port Flag: Bits 1, 2, and 3 of the output buffer represent the active output port. Pulse Output Port: This command will cause bits 3 through 0 in the controller's output port to pulse low for 6 s based on the command. A 0 in bits 3 through zero will select the bits to be pulsed.
D1H
D2H
D3H
D4H E0H
EXH F0H-FFH
Controller to System Command Set. These commands are written from the controller to the output register. They must be read by the system performing an I/O read to address 60H. Command 55H Description No error detected upon completion of self-test: This command will appear in the output register in response to a successful completion of the self-test initiated by system command AAH. No password installed: This command will appear in the output register in response to no password detection initiated by system command A4H. Password installed: This command will appear in the output register in response to a password detection initiated by system command A4H. Resend Command: This command will appear in the output register in response to an illegal command.
F1H
FAH
FEH
108
PRELIMINARY
CY82C693UB
System to Keyboard Command Set. These commands are written from the controller to the keyboard. The command should be written to the Input Buffer (Port 60H). If data is required along with the command, the system must perform a subsequent dat a write to I/O Port 60H. Command EDH Description Set/Reset Keyboard LED status indicators: Num Lock, Caps Lock, and Scroll Lock LEDs, which are found on most keyboards, can be turned on or off using this command. The system must first write the EDH command to I/O port 60H and get acknowledged. Then the system must write port 60H with the following data: Bits 7-3: 00000 Bit 2: Caps Lock (1 Turns LED on) Bit 1: Num Lock (1 Turns LED on) Bit 0: Scroll Lock (1 Turns LED on) Echo Command: This command can be used to test the keyboard. A present and working keyboard will echo EEH after it receives this command. Read keyboard ID bytes: The keyboard will acknowledge the command and send the two keyboard ID bytes. Set typematic rate and delay period: This command is used to set the typematic rate (make codes/second when a key is pressed and held down) and delay period (number of milliseconds after a key is pressed before typematic starts). INT 16H Function 03H sends the Set Rate command F3H to the keyboard controller followed by the delay and rate values. Begin Operation: This command causes the keyboard to clear its output buffer and begin scanning. Reset and Disable: This command causes the keyboard to reset to its power-on default and disables scanning. Reset and Enable: This command causes the keyboard to reset to its power-on default and enables scanning. Resend: If the system detects an error in the previous transmission, this command will cause the keyboard to send the transmission again. Self-test: This command causes the keyboard to initiate its internal diagnostic self-test.
EEH
F2H F3H
F4H F5H F6H FEH
FFH
Keyboard to System Command Set. These commands are written from the keyboard to the controller. Command 00H Description Overrun character (For scan code sets 2 and 3): When the keyboard exceeds buffer capacity, it places 00H at the bottom of the buffer. When 00H reaches the top of the buffer, it is sent to the system. Low Keyboard ID Byte: The keyboard responds to the Read ID bytes command by first sending the low ID byte. High Keyboard ID Byte: The keyboard responds to the Read ID bytes command by first sending the low ID byte. Then it sends the high ID byte. Power-on Diagnostics Completed: If the power-on diagnostic tests completed successfully (no error detected), this command is sent to the system. Power-on Diagnostics Failed: If the power-on diagnostic tests detected an error, this command is sent to the system. The keyboard controller will wait to be reset or receive some other command from the system. Echo Response: This is the keyboard's response to the system's echo command. Acknowledge (ACK): The keyboard will acknowledge any valid keyboard command that the system transmits with an ACK command. Resend: If the keyboard detects an error in the previous transmission, this command will be sent, requesting the system to send the transmission again. Overrun character (For scan code set 1): When the keyboard exceeds buffer capacity, it places FFH at the bottom of the buffer. When FFH reaches the top of the buffer, it is sent to the system.
83H ABH
AAH
FCH
EEH FAH FEH
FFH
109
PRELIMINARY
CY82C693UB
System to Mouse Controller Command Set. These commands are specific to the mouse controller. The system must first send command D4H to I/O port 64H to tell the controller that the next command is intended for the mouse controller. If D4H is not sent, the controller will interpret the commands as Keyboard commands. Command E6H E7H Description Reset mouse scaling: This command will cause scaling to be reset to 1:1. Set scaling: When the mouse is in Stream Mode, this command will convert Input X,Y coordinates to outputs as follows: Input Output 0 0 1 1 2 1 3 3 4 6 5 9 6 or greater Input x 2 Set Resolution: This is a two byte command. The first byte is E8H (sent to port 64H) to tell the mouse controller to set its resolution. The second byte is data (sent to port 60H). The data must be in one of the following combinations: Data Byte Value Resolution 00H 1 count/mm 01H 2 counts/mm 02H 4 counts/mm 03H 8 counts/mm Status Request: In response to this command, the mouse will send a three byte status report. The first byte is the sampling rate. The second byte is the resolution, and the third byte is defined as follows: Bit Description 7 Reserved 6 0: Stream Mode 1: Remote Mode 5 0: Mouse Disabled 1: Mouse Enabled 4 0: Scaling 1:1 1: Scaling 2:1 (Defined by Set Scaling command) 3 Reserved 2 0: Left mouse button not pressed 1: Left mouse button pressed 1 Reserved 0 0: Right mouse button not pressed 1: Right mouse button pressed. Set Stream Mode: When Stream Mode is selected, the mouse transmits data every time the mouse detects a unit of movement or a mouse button pressed. If no button is pressed or the mouse does not detect movement, no data will be transmitted. Read Mouse Data: This command will force the mouse to transmit one packet of mouse data. Reset Wrap Mode: This command takes the mouse out of wrap mode (the mouse will not echo data back to the system). Set Wrap Mode: This command puts the mouse in wrap mode (the mouse will echo data back to the system). Set Remote Mode: In Remote Mode, mouse data will only be transmitted in response to a Read Mouse Data command. Read device type: The mouse will return 00H (type ID for mouse) in response to this command.
E8H
E9H
EAH
EBH ECH EEH F0H F2H
110
PRELIMINARY
CY82C693UB
System to Mouse Controller Command Set. (continued) These commands are specific to the mouse controller. The system must first send command D4H to I/O port 64H to tell the controller that the next command is intended for the mouse controller. If D4H is not sent, the controller will interpret the commands as Keyboard commands. Command F3H Description Set Sampling Rate: This is a two byte command. The first byte is F3H (sent to port 64H) to tell the mouse controller to set its sampling rate (the number of times per second that the system checks the mouse for data). The second byte is data (sent to port 60H). The data must be in one of the following combinations: Data Byte Value Sampling Rate 0AH 10 samples/second 14H 20 samples/second 28H 40 samples/second 3CH 60 samples/second 50H 80 samples/second 64H 100 samples/second C8H 200 samples/second Enable transmission: This command will enable data transmission if the mouse has been set to Stream Mode. This command has no effect if the controller is in remote mode. Load default settings: This command will load the power-on default settings. They are as follows: 100 samples/second sampling rate Linear Scaling Stream Mode 4 counts/mm resolution Transmission disabled Resend: If the system detects an error in the previous transmission, this command will cause the mouse to send the transmission again. Self-test: This command causes the mouse to initiate its internal diagnostic self-test.
F4H
F6H
FEH
FFH
Mouse to System Controller Command Set. These commands are transferred from the mouse to the mouse controller. Command FAH FEH Description Acknowledge (ACK) Command: The mouse will acknowledge valid commands by returning the ACK command (except for reset commands). Resend: If the mouse detects an error in the previous transmission, this command will cause the mouse controller to send the transmission again.
111
PRELIMINARY
CY82C693UB PCI Configuration Registers
CY82C693UB
The PCI configuration registers for the CY82C693UB are defined in this section. The registers are accessed by performing configuration read and write cycles (C/BE[3:0]=1010b or 1011b) with the IDSEL signal asserted to the CY82C693UB.
PCI to ISA PCI Configuration Registers (Function 0 during Configuration Cycle)
Register 0: Vendor ID Number (Read Only) Bit 15:0 Function Cypress ID Number: 0001000010000000
- Index=00H with a 16-bit access
Default 1080H
Register 1: Device ID Number (Read Only) Bit 15:0 Function
- Index=02H with a 16-bit access
Default C693H
CY82C693UB Device ID Number: 1100011010010011
Register 3: Command Register (Read/Write) Bit 15:10 9 8 Function Reserved
- Index=04H with a 16-bit access
Default 000000 0
Fast Back-to-Back Enable. This bit is forced to 0 (Fast Back-to-Back Accesses are Disabled) 0 SERR Reporting Enable: 0: SERR Reporting Disabled 1: SERR Reporting Enabled Reserved Enable Special Cycle Decoding: 0: Disable Special Cycle Decoding 1: Enable Special Cycle Decoding Bus Master Enable. This bit is forced to 1 (Bus Mastering is Always Enabled) Memory Access Enable. This bit is forced to 1 (Memory Access is Always Enabled) I/O Access Enable. This bit is forced to 1 (I/O Access is Always Enabled)
7:4 3
0000 0
2 1 0
1 1 1
112
PRELIMINARY
Register 4: Status Register (Read/Write) Bit 15 14 Function Not implemented: Read as 0 PCI System Error READ: 0: No PCI System Error Occurred 1: PCI System Error Occurred WRITE: 0: No change to register 1: Clear Register PCI Master-Abort READ: 0: No PCI Master-Abort Occurred 1: PCI Master-Abort Occurred WRITE: 0: No change to register 1: Clear Register CY82C693UB Detection of Target-Abort (from another PCI target) READ: 0: No PCI Target-Abort Occurred 1: PCI Target-Abort Occurred WRITE: 0: No change to register 1: Clear Register CY82C693UB Assertion of Target-Abort (CY82C693UB is the target) READ: 0: No PCI Target-Abort Occurred 1: PCI Target-Abort Occurred WRITE: 0: No change to register 1: Clear Register DEVSEL Timing Status. These register bits are Read Only and will always return 01 (medium timing) Not implemented: Read as 0 Fast Back-to-Back Transfer Occurred. This Read Only bit will always return 1 Reserved
CY82C693UB
- Index=06H with a 16-bit access
Default 0 0
13
0
12
0
11
0
10:9 8 7 6:0
01 0 1 0000000
Register 5: Revision ID Number (Read Only) Bit 7:0 Function
- Index=08H with an 8-bit access
Default 00H
Current Revision of the Part (00000000)
Register 6: Programming Interface Revision ID Number (Read Only) Bit 7:0 Function
- Index=09H with an 8-bit access
Default 00H
Current Revision of the Programming Interface (00000000)
Register 7: Sub Class Code Register (Read Only) Bit 7:0 Function Sub Class Code (00000001)
- Index=0AH with an 8-bit access
Default 01H
113
PRELIMINARY
Register 8: Base Class Code Register (Read Only) Bit 7:0 Function Base Class Code (00000110)
CY82C693UB
- Index=0BH with an 8-bit access
Default 06H
Register 9: Header Type Register (Read Only) Bit 7:0 Function
- Index=0EH with an 8-bit access
Default 80H
Device Type - multi-function device
Register 10: PCI Interrupt A Routing Control Register (Read/Write) Bit 7 Function Interrupt A Routing Control: 0: Interrupt A Routing Enabled 1: Interrupt A Routing Disabled Reserved Interrupt Request Level that PCI INTA is Routed to: 0000: Reserved 1000: Reserved 0001: Reserved 1001: IRQ9 0010: Reserved 1010: IRQ10 0011: IRQ3 1011: IRQ11 0100: IRQ4 1100: IRQ12 0101: IRQ5 1101: Reserved 0110: IRQ6 1110: IRQ14 0111: IRQ7 1111: IRQ15
- Index=40H with an 8-bit access
Default 0
6:4 3:0
000 0000
Register 11: PCI Interrupt B Routing Control Register (Read/Write) Bit 7 Function Interrupt B Routing Control: 0: Interrupt B Routing Enabled 1: Interrupt B Routing Disabled Reserved Interrupt Request Level that PCI INTB is Routed to: 0000: Reserved 1000: Reserved 0001: Reserved 1001: IRQ9 0010: Reserved 1010: IRQ10 0011: IRQ3 1011: IRQ11 0100: IRQ4 1100: IRQ12 0101: IRQ5 1101: Reserved 0110: IRQ6 1110: IRQ14 0111: IRQ7 1111: IRQ15
- Index=41H with an 8-bit access
Default 0
6:4 3:0
000 0000
114
PRELIMINARY
Register 12: PCI Interrupt C Routing Control Register (Read/Write) Bit 7 Function Interrupt C Routing Control: 0: Interrupt C Routing Enabled 1: Interrupt C Routing Disabled Reserved Interrupt Request Level that PCI INTC is Routed to: 0000: Reserved 1000: Reserved 0001: Reserved 1001: IRQ9 0010: Reserved 1010: IRQ10 0011: IRQ3 1011: IRQ11 0100: IRQ4 1100: IRQ12 0101: IRQ5 1101: Reserved 0110: IRQ6 1110: IRQ14 0111: IRQ7 1111: IRQ15
CY82C693UB
- Index=42H with an 8-bit access
Default 0
6:4 3:0
000 0000
Register 13: PCI Interrupt D Routing Control Register (Read/Write) Bit 7 Function Interrupt D Routing Control: 0: Interrupt D Routing Enabled 1: Interrupt D Routing Disabled Reserved Interrupt Request Level that PCI INTD is Routed to: 0000: Reserved 1000: Reserved 0001: Reserved 1001: IRQ9 0010: Reserved 1010: IRQ10 0011: IRQ3 1011: IRQ11 0100: IRQ4 1100: IRQ12 0101: IRQ5 1101: Reserved 0110: IRQ6 1110: IRQ14 0111: IRQ7 1111: IRQ15
- Index=43H with an 8-bit access
Default 0
6:4 3:0
000 0000
Register 14: PCI Control Register (Read/Write) Bit 7 6:5 Function Reserved
- Index=44H with an 8-bit access
Default 0 0
PCI Master Grant Arbitration Time 00: Reevaluate Grants after every PCI clock 01: Reevaluate Grants after 16 PCI clocks 10: Reevaluate Grants after 32 PCI clocks 11: Reevaluate Grants after 64 PCI clocks Retry on excessive delay control: 0: Disable Retry if delay will be longer than 16 PCI clock cycles 1: Enable Retry if delay will be longer than 16 PCI clock cycles (Rev 2.1 Compliant) Reserved Reserved. Must be set to 0. Reserved. Must be set to 0. Reserved. Must be set to 0.
4
0
3 2 1 0
0 0 0 0
115
PRELIMINARY
Register 15: PCI Error Control Register (Read/Write) Bit 7 Function SERR Reporting on Target-Abort Control: 0: Disable SERR Assertion on Target-Abort 1: Enable SERR Assertion on Target-Abort SERR Reporting on Special Cycle Data Parity Errors Control: 0: Disable SERR Assertion on Special Cycle Data Parity Errors 1: Enable SERR Assertion on Special Cycle Data Parity Errors SERR Reporting on Address Parity Errors Control: 0: Disable SERR Assertion on Address Parity Errors 1: Enable SERR Assertion on Address Parity Errors Reserved ISA Master Post-Write Enable: 0: Disable ISA Master Post-Write Buffering 1: Enable ISA Master Post-Write Buffering DMA Post-Write Enable: 0: Disable DMA Post-Write Buffering 1: Enable DMA Post-Write Buffering
CY82C693UB
- Index=45H with an 8-bit access
Default 0
6
0
5
0
4:2 1
000 0
0
0
Register 16: PCI Error Status Register (Read/Write) Bit 7:5 4 Function Reserved
- Index=46H with an 8-bit access
Default 000 0
Shutdown Cycle READ: 0: No Shutdown Cycle Detected 1: Shutdown Cycle Detected WRITE: 0: No change to register. 1: Clear Register Reserved ISA/DMA 0-512K Forwarding: 0: Enable Forwarding 1: Disable Forwarding ISA/DMA 640K-768K Forwarding: 0: Disable Forwarding 1: Enable Forwarding
3:2 1
00 0
0
0
116
PRELIMINARY
Register 17: PCI BIOS Control Register (Read/Write) Bit 7 Function Extended BIOS Control (Addresses FFF80000H-FFFDFFFFH): 0: Disable ROM Address Mapping from FFF80000H to FFFDFFFFH 1: Generate ROMCS for addresses between FFF80000H-FFFDFFFFH
CY82C693UB
- Index=47H with an 8-bit access
Default 0
6
Low BIOS Control (Addresses 000E0000H-000EFFFFH and FFFE0000H-FFFEFFFFH): 0: Disable Low ROM Address Mapping 1: Generate ROMCS for Low ROM addresses ROM Write-protect Control: 0: ROMCS will only become active on ROM reads (ROM is Read Only). 1: ROMCS will become active on ROM reads and writes. Block D BIOS Control (Addresses 000D0000H-000DFFFFH): 0: Disable ROM Address Mapping from 000D0000H-000DFFFFH 1: Generate ROMCS for addresses between 000D0000H-000DFFFFH Block C BIOS Control (Addresses 000C0000H-000CFFFFH): 0: Disable ROM Address Mapping from 000C0000H-000CFFFFH 1: Generate ROMCS for addresses between 000C0000H-000CFFFFH External Keyboard Controller Status (This bit is Read Only): 0: Internal Keyboard Controller is in use. 1: External Keyboard Controller is in use. (Internal Keyboard Controller is disabled.) External Real-Time-Clock Status (This bit is Read Only): 0: Internal RTC is in use. 1: External RTC is in use. (Internal RTC is disabled.) External XD Buffer Status (This bit is Read Only): 0: CY82C693UB XD Bus is in use. 1: External buffer is in use to buffer the XD bus.
0
5
0
4
0
3
0
2
0
1
0
0
0
Register 18: ISA/DMA Top of Memory Control (Read/Write) Bit 7:4 Function Top of ISA Memory: 0000: 1 MByte 0001: 2 MByte 0010: 3 MByte 0011: 4 MByte 0100: 5 MByte 0101: 6 MByte 0110: 7 MByte 0111: 8 MByte 1000: 1001: 1010: 1011: 1100: 1101: 1110: 1111: 9 MByte 10 MByte 11 MByte 12 MByte 13 MByte 14 MByte 15 MByte 16 MByte
- Index=48H with an 8-bit access
Default 0
3
ISA/DMA Low BIOS Forwarding Control 0: Disable ISA/DMA Low BIOS Forwarding 1: Enable ISA/DMA Low BIOS Forwarding ISA/DMA 512K-640K BIOS Forwarding Control 0: Disable ISA/DMA 512K-640K BIOS Forwarding 1: Enable ISA/DMA 512K-640K BIOS Forwarding ISA/DMA 832K-896K BIOS Forwarding Control 0: Disable ISA/DMA 832K-896K BIOS Forwarding 1: Enable ISA/DMA 832K-896K BIOS Forwarding ISA/DMA 768K-832K BIOS Forwarding Control 0: Disable ISA/DMA 768K-832K BIOS Forwarding 1: Enable ISA/DMA 768K-832K BIOS Forwarding
0
2
0
1
0
0
0
117
PRELIMINARY
Register 19: AT Control Register #1 (Read/Write) Bit 7 6 Function Reserved
CY82C693UB
- Index=49H with an 8-bit access
Default 0 0
PIO IDE Routable Interrupt Request Control 0: IDE Interrupt Requests are available on XD bus pins to support Interrupt routing 1: IDE Interrupt Requests must be hardwired to IRQ14 and IRQ15 IDE DMA Status (This bit is Read Only) 0: IDE DMA is disabled 1: IDE DMA is enabled Keyboard Controller Status (This bit is Read Only) 0: PS/2 Keyboard Controller 1: Standard AT Keyboard Controller 16-bit I/O Recovery Control 0: Disable 16-bit I/O Recovery 1: Enable 16-bit I/O Recovery 8-bit I/O Recovery Control 0: Disable 8-bit I/O Recovery 1: Enable 8-bit I/O Recovery ATCLK Control 00: PCICLK divided by four 01: PCICLK divided by three 10: 14.318 MHz Clock divided by two (7.16 MHz) 11: Reserved
5
0
4
0
3
0
2
0
1:0
00
Register 20: AT Control Register #2 (Read/Write) Bit 7 Function Wait for Halt Control: 0: Enable Wait for Halt 1: Disable Wait for Halt
- Index=4AH with an 8-bit access
Default 0
6
Keyboard Controller Fast Reset Emulation Control: 0: Enable Fast Reset Emulation 1: Disable Fast Reset Emulation Keyboard Controller Fast Gate A20 Emulation Control: 0: Enable Fast Gate A20 Emulation 1: Disable Fast Gate A20 Emulation Port 92 Emulation Control: 0: Enable Port 92 Emulation 1: Disable Port 92 Emulation AT Refresh Cycle Control 0: Refresh is four ATCLK cycles 1: Refresh is four ATCLK/2 cycles AT Refresh Control 0: Disable AT Refresh 1: Enable AT Refresh Keyboard Controller Clock Speed Control PCICLK Speed 25 MHz 33 MHz 00: 6.25 MHz 8.25 MHz 01: 12.5 MHz 16.5 MHz 10: 8.33 MHz 11 MHz 11: 16.67 MHz 22 MHz
0
5
0
4
0
3
0
2
0
1:0
00
118
PRELIMINARY
Register 21: PCI IDE Interrupt Request 0 Routing Control Register (Read/Write) Bit 7 Function IDE Interrupt 0 Routing Control: 0: Interrupt 0 Routing Enabled 1: Interrupt 0 Routing Disabled Reserved Interrupt Request Level that PCI IDE IRQ0 is Routed to: 0000: Reserved 1000: Reserved 0001: Reserved 1001: IRQ9 0010: Reserved 1010: IRQ10 0011: IRQ3 1011: IRQ11 0100: IRQ4 1100: IRQ12 0101: IRQ5 1101: Reserved 0110: IRQ6 1110: IRQ14 0111: IRQ7 1111: IRQ15
CY82C693UB
- Index=4BH with an 8-bit access
Default 0
6:4 3:0
000 0000
Register 22: PCI IDE Interrupt Request 1 Routing Control Register (Read/Write) Bit 7 Function IDE Interrupt 1 Routing Control: 0: Interrupt 0 Routing Enabled 1: Interrupt 0 Routing Disabled Reserved Interrupt Request Level that PCI IDE IRQ1 is Routed to: 0000: Reserved 1000: Reserved 0001: Reserved 1001: IRQ9 0010: Reserved 1010: IRQ10 0011: IRQ3 1011: IRQ11 0100: IRQ4 1100: IRQ12 0101: IRQ5 1101: Reserved 0110: IRQ6 1110: IRQ14 0111: IRQ7 1111: IRQ15
- Index=4CH with an 8-bit access
Default 0
6:4 3:0
000 0000
119
PRELIMINARY
CY82C693UB
- Index=4DH
Default 0
Register 23: CY82C693UB Stand-Alone Control and USB Host Controller Control Register (Read/Write) with an 8-bit access Bit 7 Function External PCI Arbiter Protocol Control: 0: All CY82C693UB masters arbitrate for the PCI bus using the PREQ/PGNT signal pair. 1: This setting is used to allow USB master arbitration to use the SREQ/SGNT signal pair. All other CY82C693UB masters use PREQ/PGNT. Note: This register bit is only for use when the internal PCI arbiter is disabled. If the internal PCI arbiter is used (pin 194 HIGH at power-up), this register bit does not effect CY82C693UB operation. 6:5 Flush Request/Acknowledge Handshake Control: 00: Normal Operation: Flush request/acknowledge handshake is performed using the FREQACK signal. 01: Flush request/acknowledge handshake is performed using the FREQACK signal. However, IRQ8 (the RTC interrupt) is masked internally and will not be seen by the interrupt controller. 10: Flush request is automatically acknowledged internally. The FREQACK signal will remain in high impedance. 11: Flush request is automatically acknowledged internally. IRQ8 (the RTC interrupt) is masked internally and will not be seen by the interrupt controller. IRQ8 is driven out on the FREQACK pin (pin 190). If a Flush Acknowledge is not sent externally (by the system northbridge), bit 6 must be set to "1." Otherwise DMA will not work correctly. Note: Flush request may not be automatically acknowledged internally if a coherent path to memory is not guaranteed. 4 IDE Controller Decode Control: 0: IDE Controller decode will only use lower 16 address bits (64KB). 1: IDE Controller decode will use all 32-bits (4GB). Note: If I/O transactions are allowed above 64KB, this bit should be set to 1. Otherwise, system conflicts may occur. See IDE Controller Configuration Registers 7, 8, &9. 3 ROM Space Decode: 0: 512KB ROM space decode 1: 1MB ROM space decode Reserved. Reserved. USB Interface Control: 0: Disable USB interface 1: Enable USB interface
00
0
0
2 1 0
0
120
PRELIMINARY
Bit 7:6 5 4 Function USB Host Controller Test Mode Selection USB Host Controller Test Mode Enable USB Host Controller IRQ1 Enable: 0: Disabled 1: Enabled USB Host Controller IRQ12 Enable: 0: Disabled 1: Enabled This bit is write-only. Undefined on read. USB Host Controller FA20 Enable: 0: Disabled 1: Enabled This bit is write-only. Undefined on read. USB Host Controller SMI Enable: 0: Disabled 1: Enabled This bit is write-only. Undefined on read. Reserved
CY82C693UB
Default 00 0 0
Register 24: CY82C693UB USB Control Register 1 (Read/Write) - Index=4EH with an 8-bit access
3
0
2
0
1
0
0
0
Register 24: CY82C693UB USB Control Register 2 (Read/Write) - Index=4FH with an 8-bit access Bit 7 Function USB Host Controller SMIACT Enable: 0: Disabled 1: Enabled USB Host Controller PWREN Enable: 0: Disable 1: Enabled USB Host Controller Interrupt Mapping: 00: PCI INTAN 01: PCI INTBN 10: PCI INTCN 11: PCI INTDN Reserved. Default 0
6
0
5:4
00
3:0
0000
121
PRELIMINARY
Primary Channel IDE PIO (Programmed I/O) PCI Configuration Registers (Function 1 during Configuration Cycle)
Register 0: Vendor ID Number (Read Only) Bit 15:0 Function Cypress ID Number: 0001000010000000
CY82C693UB
- Index=00H with a 16-bit access
Default 1080H
Register 1: Device ID Number (Read Only) Bit 15:0 Function
- Index=02H with a 16-bit access
Default C693H
CY82C693UB Device ID Number: 1100011010010011
Register 2: Command Register (Read/Write) Bit 15:10 9 8 Function Reserved. Reserved, Must be set to 0.
- Index=04H with a 16-bit access
Default 000000 0 0
SERR Reporting Enable: 0: SERR Reporting Disabled 1: SERR Reporting Enabled Reserved, Must be set to 0. Reserved. Bus Master Enable. 0 Bus Master Disabled 1 Bus Master Enabled Memory Access Enable. This bit is forced to 0 (Memory Access is not allowed to IDE Controller). I/O Access Enable.: 0: Primary IDE controller disabled. 1: Primary IDE controller enabled. The Primary IDE Controller will respond to PIO I/O accesses when this bit is set.
7 6:3 2
0 0000 0
1 0
0 0
122
PRELIMINARY
Register 3: Status Register (Read/Write) Bit 15 14 13 Function Reserved. Read as 0. PCI System Error This bit is not used by the IDE controllers. PCI Master-Abort READ: 0: No PCI Master-Abort Occurred 1: PCI Master-Abort Occurred WRITE: 0: No change to register 1: Clear Register CY82C693UB Detection of Target-Abort (from another PCI target) READ: 0: No PCI Target-Abort Occurred 1: PCI Target-Abort Occurred WRITE: 0: No change to register 1: Clear Register CY82C693UB Assertion of Target-Abort (CY82C693UB is the target) READ: 0: No PCI Target-Abort Occurred 1: PCI Target-Abort Occurred WRITE: 0: No change to register 1: Clear Register DEVSEL Timing Status These register bits are Read Only and will always return 01 (medium timing). Reserved. Read as 0. Fast Back-to-Back Transfer Capable. This Read Only bit will always return 1. Reserved.
CY82C693UB
- Index=06H with a 16-bit access
Default 0 0 0
12
0
11
0
10:9 8 7 6:0
01 0 1 0000000
Register 4: Revision ID Number (Read Only) Bit 7:0 Function
- Index=08H with an 8-bit access
Default 00H
Current Revision of the Part (00000000)
Register 5: Class Code Register (Read Only) Bit 7:0 Function
- Index=09H with a 32-bit access
Default 00010180H
Sub Class Code - IDE mass storage disk controller w/ bus mastering support
Register 6: Header Type Register (Read Only) Bit 7:0 Function
- Index=0EH with an 8-bit access
Default 00H
Device Type, single-function device
Register 7: Primary IDE Command Address Register (Read/Write) Bit 31:0 Function
- Index=10H with a 32-bit access
Default
Primary IDE Command Address Register: 00000000H This register specifies the amount of I/O space required for the primary IDE command registers. The IDE command block requires 8 bytes of I/O space (Bits [2:0] are hardwired to 001). Bits [15:3] are programmable. Bits [31:16] are hard-wired to 0000H. See stand-alone description for 32-bit decode option.
123
PRELIMINARY
Register 8: Primary IDE Control Address Register (Read/Write) Bit 31:0 Function
CY82C693UB
- Index=14H with a 32-bit access
Default 00000000H
Primary IDE Control Address Register: This register specifies the amount of I/O space required for the primary IDE control registers. The IDE control block requires 2 bytes of I/O space (Bits [1:0] are hardwired to 01). Bits [15:2] are programmable. Bits [31:16] are hard-wired to 0000H. See stand-alone description for 32-bit decode option.
Note: Register Indices 18H-1FH will return all zeroes when read. Register 9: Primary Bus Master IDE Control Address Register (Read/Write) Bit 31:0 Function Bus Master IDE Control Address Register: This register specifies the amount of I/O space required for the bus master IDE control registers. The bus master IDE control block requires 16 bytes of I/O space (Bits [3:0] are hardwired to 0001). Bits [15:4] are programmable. Bits [31:16] are hard-wired to 0000H. See stand-alone description for 32-bit decode option.
- Index=20H with a 32-bit access
Default 00000000H
Register 10: Primary IDE Interrupt INTA Control Register (Read/Write) Bit 7:0 Function
- Index=3CH with an 8-bit access
Default 14H
Primary IDE Interrupt Control Register: This register is written by the POST software to inform the system which interrupt level the primary IDE controller is connected.
Register 11: Primary IDE Interrupt Pin Control Register (Read Only) Bit 7:0 Function
- Index=3DH with an 8-bit access
Default 01H
Primary IDE Interrupt Pin Control Register: 01H: The Primary IDE Channel Interrupt is connected to PCI INTA internally.
Note: Register Indices 3EH-3FH will return all zeroes when read.
124
PRELIMINARY
Register 12: Primary IDE Control Register (Read/Write) Bit 31:18 17 16 15:14 13 Function Reserved Reserved Reserved Reserved Retry I/O Accesses Not Completed by 16 PCI Clocks Control: 0: I/O Accesses Not Completed by 16 PCI Clocks will not be retried. 1: I/O Accesses Not Completed by 16 PCI Clocks will be retried. Reserved Slave Drive Prefetch Control: 0: Disable Prefetch (Must be 0 for CDROM accesses). 1: Enable Prefetch Post Write Control: 0: One level FIFO for Posted Writes 1: Four levels of FIFO for Posted Writes Master Drive Prefetch Control: 0: Disable Prefetch (Must be 0 for CDROM accesses). 1: Enable Prefetch Reserved
CY82C693UB
Default 00000000000 000 0 0 00 0
- Index=40H with a 32-bit access
12:11 10
00 0
9
0
8
0
7:6 5:4
00 00
Post Write Length Control: The value programmed into this register+1 will be the length of the Post Write Bursts that the IDE write state machine will attempt to the IDE drive when the AT bus grant is received. Reserved Prefetch Length Control: The value programmed into this register+1 will be the length of the Prefetch Bursts that the IDE read state machine will attempt to the IDE drive when the AT bus grant is received.
3:2 1:0
00 00
Note: Register Indices 44H-47H will return all zeroes when read. Register 13: Primary IDE Address Setup Control Register (Read/Write) Bit 31:8 7:4 Function Reserved Slave Drive IDE Address Set-up Time: The value programmed into this register +1 will be the setup (in PCI Clock cycles) from address valid to IOR or IOW valid. Master Drive IDE Address Set-up Time: The value programmed into this register +1 will be the setup (in PCI Clock cycles) from address valid to IOR or IOW valid.
- Index=48H with a 32-bit access
Default 000000H 0011
3:0
0011
Register 14: Primary Master Drive IDE IOR Command Control Register (Read/Write) Bit 7:4 Function
- Index=4CH with an 8-bit access
Default 0011
16-Bit Master Drive IDE IOR Command Pulse Width Time: The value programmed into this register +1 will be the duration (in AT Clock cycles) of the asserted IOR signal. 16-Bit Master Drive IDE IOR Command Recovery Time: The value programmed into this register +1 will be the duration (in AT Clock cycles) that IOR must be deasserted between transfers.
3:0
0011
125
PRELIMINARY
Register 15: Primary Master Drive IDE IOW Command Control Register (Read/Write) Bit 7:4 Function
CY82C693UB
- Index=4DH with an 8-bit access
Default 0110
16-Bit Master Drive IDE IOW Command Pulse Width Time: The value programmed into this register +1 will be the duration (in PCI Clock cycles) of the asserted IOW signal. 16-Bit Master Drive IDE IOW Command Recovery Time: The value programmed into this register +1 will be the duration (in PCI Clock cycles) that IOW must be deasserted between transfers.
3:0
1110
Register 16: Primary Slave Drive IDE IOR Command Control Register (Read/Write) Bit 7:4 Function
- Index=4EH with an 8-bit access
Default 0011
16-Bit Slave Drive IDE IOR Command Pulse Width Time: The value programmed into this register +1 will be the duration (in PCI Clock cycles) of the asserted IOR signal. 16-Bit Slave Drive IDE IOR Command Recovery Time: The value programmed into this register +1 will be the duration (in PCI Clock cycles) that IOR must be deasserted between transfers.
3:0
0011
Register 17: Primary Slave Drive IDE IOW Command Control Register (Read/Write) Bit 7:4 Function
- Index=4FH with an 8-bit access
Default 0110
16-Bit Slave Drive IDE IOW Command Pulse Width Time: The value programmed into this register +1 will be the duration (in PCI Clock cycles) of the asserted IOW signal. 16-Bit Slave Drive IDE IOW Command Recovery Time: The value programmed into this register +1 will be the duration (in PCI Clock cycles) that IOW must be deasserted between transfers.
3:0
1110
Register 18: Primary Master Drive 8-Bit IDE Command Control Register (Read/Write) Bit 7:4 Function
- Index=50H with an 8-bit access
Default 1010
8-Bit Master Drive IDE Command Pulse Width Time: The value programmed into this register +1 will be the duration (in PCI Clock cycles) of the asserted IOW or IOR signal. 8-Bit Master Drive IDE IOW Command Recovery Time: The value programmed into this register +1 will be the duration (in PCI Clock cycles) that IOW must be deasserted between transfers.
3:0
1010
Register 19: Primary Slave Drive 8-Bit IDE Command Control Register (Read/Write) Bit 7:4 Function
- Index=51H with an 8-bit access
Default 1010
8-Bit Slave Drive IDE Command Pulse Width Time: The value programmed into this register +1 will be the duration (in PCI Clock cycles) of the asserted IOW or IOR signal. 8-Bit Slave Drive IDE IOW Command Recovery Time: The value programmed into this register +1 will be the duration (in PCI Clock cycles) that IOW must be deasserted between transfers.
3:0
1010
Note: The 8-bit IDE Command Registers are used for mode 0, 1, and 2 drives. For mode 3 and 4 drives, the 8 and 16 bit timings are the same.
126
PRELIMINARY
Register 20: Primary Master Drive IORDY Control Register (Read/Write) Bit 7:4 3:2 Function Reserved
CY82C693UB
- Index=52H with an 8-bit access
Default 0000 01
Read Synchronization Control: The value in this register selects the number of PCI clocks used to synchronize the rising edge of IORDY during read transactions. Write Synchronization Control: The value in this register selects the number of PCI clocks used to synchronize the rising edge of IORDY during write transactions.
1:0
01
Register 21: Primary Slave Drive IORDY Control Register (Read/Write) Bit 7:4 3:2 Function Reserved
- Index=53H with an 8-bit access
Default 0000 01
Read Synchronization Control: The value in this register selects the number of PCI clocks used to synchronize the rising edge of IORDY during read transactions. Write Synchronization Control: The value in this register selects the number of PCI clocks used to synchronize the rising edge of IORDY during write transactions.
1:0
01
127
PRELIMINARY
Secondary Channel IDE PIO (Programmed I/O) PCI Configuration Registers (Function 2 during Configuration Cycle)
Register 0: Vendor ID Number (Read Only) Bit 15:0 Function Cypress ID Number: 0001000010000000
CY82C693UB
- Index=00H with a 16-bit access
Default 1080H
Register 1: Device ID Number (Read Only) Bit 15:0 Function
- Index=02H with a 16-bit access
Default C693H
CY82C693UB Device ID Number: 1100011010010011
Register 2: Command Register (Read/Write) Bit 15:10 9 8 Function Reserved. Reserved, must be set to 0
- Index=04H with a 16-bit access
Default 000000 0 0
SERR Reporting Enable: 0: SERR Reporting Disabled 1: SERR Reporting Enabled Reserved, must be set to 0. Reserved Reserved I/O Access Enable.: 0: Secondary IDE controller disabled 1: Secondary IDE controller enabled The Secondary IDE Controller will respond to PIO I/O accesses when this bit is set.
7 6 5:1 0
0 0 00000 0
128
PRELIMINARY
Register 3: Status Register (Read/Write) Bit 15 14 13 Function Not Implemented. Read as 0. PCI System Error This bit is not used by the IDE controllers. PCI Master-Abort READ: 0: No PCI Master-Abort Occurred 1: PCI Master-Abort Occurred WRITE: 0: No change to register 1: Clear Register CY82C693UB Detection of Target-Abort (from another PCI target) READ: 0: No PCI Target-Abort Occurred 1: PCI Target-Abort Occurred WRITE: 0: No change to register 1: Clear Register CY82C693UB Assertion of Target-Abort (CY82C693UB is the target) READ: 0: No PCI Target-Abort Occurred 1: PCI Target-Abort Occurred WRITE: 0: No change to register 1: Clear Register DEVSEL Timing Status. These register bits are Read Only and will always return 01 (medium timing) Not Implemented. Read as 0. Fast Back-to-Back Transfer Capable. This Read Only bit will always return 1. Reserved
CY82C693UB
- Index=06H with a 16-bit access
Default 0 0 0
12
0
11
0
10:9 8 7 6:0
01 0 1 0000000
Register 4: Revision ID Number (Read Only) Bit 7:0 Function
- Index=08H with an 8-bit access
Default 00H
Current Revision of the Part (00000000)
Register 5: Class Code Register (Read Only) Bit 7:0 Function
- Index=09H with a 32-bit access
Default 00010100H
Sub Class Code - IDE mass storage disk controller
Register 6: Header Type Register (Read Only) Bit 7:0 Function
- Index=0EH with an 8-bit access
Default 00H
Device Type, single-function device
Register 7: Secondary IDE Command Address Register (Read/Write) Bit 31:0 Function
- Index=10H with a 32-bit access
Default 00000000H
Secondary IDE Command Address Register: This register specifies the amount of I/O space required for the secondary IDE command registers. The IDE command block requires 8 bytes of I/O space (Bits [2:0] are hardwired to 001). Bits [15:3] are programmable. Bits [31:16] are hard-wired to 0000H. See stand-alone description for 32-bit decode option description.
129
PRELIMINARY
Register 8: Secondary IDE Control Address Register (Read/Write) Bit 31:0 Function
CY82C693UB
- Index=14H with a 32-bit access
Default 00000000H
Secondary IDE Control Address Register: This register specifies the amount of I/O space required for the secondary IDE control registers. The IDE control block requires 2 bytes of I/O space (Bits [1:0] are hardwired to 01). Bits [15:2] are programmable. Bits [31:16] are hard-wired to 0000H. See stand-alone description for 32-bit decode option description.
Note: Register Indices 18H-3BH will return all zeroes when read. Register 9: Secondary IDE Interrupt INTB Control Register (Read/Write) Bit 7:0 Function Secondary IDE Interrupt Control Register: This register is written by the POST software to inform the system which interrupt level the secondary IDE controller is connected.
- Index=3CH with an 8-bit access
Default 15H
Register 10: Secondary IDE Interrupt Pin Control Register (Read Only) Bit 7:0 Function
- Index=3DH with an 8-bit access
Default 02H
Secondary IDE Interrupt Pin Control Register: 02H: The secondary IDE Channel Interrupt is connected to PCI INTB internally.
Note: Register Indices 3EH-3FH will return all zeroes when read. Register 11: Secondary IDE Control Register (Read/Write) Bit 31:16 15:14 13 Function Reserved Reserved Retry I/O Accesses Not Completed by 16 PCI Clocks Control: 0: I/O Accesses Not Completed by 16 PCI Clocks will not be retried 1: I/O Accesses Not Completed by 16 PCI Clocks will be retried Reserved Slave Drive Prefetch Control: 0: Disable Prefetch (Must be 0 for CDROM accesses). 1: Enable Prefetch Post Write Control: 0: One level FIFO for Posted Writes 1: Four levels of FIFO for Posted Writes Master Drive Prefetch Control: 0: Disable Prefetch (Must be 0 for CDROM accesses) 1: Enable Prefetch Reserved Post Write Length Control: The value programmed into this register+1 will be the length of the Post Write Bursts that the IDE write state machine will attempt to the IDE drive when the AT bus grant is received. Reserved Prefetch Length Control: The value programmed into this register+1 will be the length of the Prefetch Bursts that the IDE read state machine will attempt to the IDE drive when the AT bus grant is received.
- Index=40H with a 32-bit access
Default 00000000000 00000 00 0
12:11 10
00 0
9
0
8
0
7:6 5:4
00 00
3:2 1:0
00 00
Note: Register Indices 44H-47H will return all zeroes when read.
130
PRELIMINARY
Register 12: Secondary IDE Address Setup Control Register (Read/Write) Bit 31:8 7:4 Function Reserved
CY82C693UB
- Index=48H with a 32-bit access
Default 000000H 0011
Slave Drive IDE Address Setup Time: The value programmed into this register +1 will be the setup (in PCI Clock cycles) from address valid to IOR or IOW valid. Master Drive IDE Address Setup Time: The value programmed into this register +1 will be the setup (in PCI Clock cycles) from address valid to IOR or IOW valid.
3:0
0011
Register 13: Secondary Master Drive IDE IOR Command Control Register (Read/Write) Bit 7:4 Function
- Index=4CH with an 8-bit access
Default 0011
16-Bit Master Drive IDE IOR Command Pulse Width Time: The value programmed into this register +1 will be the duration (in PCI Clock cycles) of the asserted IOR signal. 16-Bit Master Drive IDE IOR Command Recovery Time: The value programmed into this register +1 will be the duration (in PCI Clock cycles) that IOR must be deasserted between transfers.
3:0
0011
Register 14: Secondary Master Drive IDE IOW Command Control Register (Read/Write) Bit 7:4 Function
- Index=4DH with an 8-bit access
Default 0110
16-Bit Master Drive IDE IOW Command Pulse Width Time: The value programmed into this register +1 will be the duration (in PCI Clock cycles) of the asserted IOW signal. 16-Bit Master Drive IDE IOW Command Recovery Time: The value programmed into this register +1 will be the duration (in PCI Clock cycles) that IOW must be deasserted between transfers.
3:0
1110
Register 15: Secondary Slave Drive IDE IOR Command Control Register (Read/Write) Bit 7:4 Function
- Index=4EH with an 8-bit access
Default 0011
16-Bit Slave Drive IDE IOR Command Pulse Width Time: The value programmed into this register +1 will be the duration (in PCI Clock cycles) of the asserted IOR signal. 16-Bit Slave Drive IDE IOR Command Recovery Time: The value programmed into this register +1 will be the duration (in PCI Clock cycles) that IOR must be deasserted between transfers.
3:0
0011
Register 16: Secondary Slave Drive IDE IOW Command Control Register (Read/Write) Bit 7:4 Function
- Index=4FH with an 8-bit access
Default 0110
16-Bit Slave Drive IDE IOW Command Pulse Width Time: The value programmed into this register +1 will be the duration (in PCI Clock cycles) of the asserted IOW signal. 16-Bit Slave Drive IDE IOW Command Recovery Time: The value programmed into this register +1 will be the duration (in PCI Clock cycles) that IOW must be deasserted between transfers.
3:0
1110
131
PRELIMINARY
Register 17: Secondary Master Drive 8-Bit IDE Command Control Register (Read/Write) Bit 7:4 Function
CY82C693UB
- Index=50H with an 8-bit access
Default 1010
8-Bit Master Drive IDE Command Pulse Width Time: The value programmed into this register +1 will be the duration (in PCI Clock cycles) of the asserted IOW or IOR signal. 8-Bit Master Drive IDE IOW Command Recovery Time: The value programmed into this register +1 will be the duration (in PCI Clock cycles) that IOW must be deasserted between transfers.
3:0
1010
Register 18: Secondary Slave Drive 8-Bit IDE Command Control Register (Read/Write) Bit 7:4 Function
- Index=51H with an 8-bit access
Default 1010
8-Bit Slave Drive IDE Command Pulse Width Time: The value programmed into this register +1 will be the duration (in PCI Clock cycles) of the asserted IOW or IOR signal. 8-Bit Slave Drive IDE IOW Command Recovery Time: The value programmed into this register +1 will be the duration (in PCI Clock cycles) that IOW must be deasserted between transfers.
3:0
1010
Note: The 8-bit IDE Command Registers are used for mode 0, 1, and 2 drives. For mode 3 and 4 drives, the 8 and 16 bit timings are the same. Register 19: Secondary Master Drive IORDY Control Register (Read/Write) Bit 7:4 3:2 Function Reserved Read Synchronization Control: The value in this register selects the number of PCI clocks used to synchronize the rising edge of IORDY during read transactions. Write Synchronization Control: The value in this register selects the number of PCI clocks used to synchronize the rising edge of IORDY during write transactions.
- Index=52H with an 8-bit access
Default 0000 01
1:0
01
132
PRELIMINARY
CY82C693UB
USB Host Controller PCI Configuration Registers (Function 3 during Configuration Cycle)
Register 0: Vendor ID Number (Read Only) - Index=00H with a 16-bit access Bit 15:0 Function Cypress ID Number: 0001000010000000 Default 1080H
Register 1: Device ID Number (Read Only) - Index=02H with a 16-bit access Bit 15:0 Function CY82C693UB Device ID Number: 1100011010010011 Default C693H
Register 2: Command Register (Read/Write) - Index=04H with a 16-bit access Bit 15:10 9 Function Reserved. Always 0. Fast Back-to-Back enable: 0: Disabled 1 Enabled The USB Host Controller always generates fast back-to-back access. Therefore, this bit must be set to 1. SERR Reporting Enable: 0: Disabled 1: Enabled Wait Cycle Control. Always 0. PERR Detection Enabled. Not supported by CY82C693UB. VGA Palette Snooping. Always 0 Memory Write and Invalidate Command Enable Special Cycle Enable. Always 0. Default 000000 0
8
0
7 6 5 4 3 2
0 0 0 0 0
PCI Master Enable: 0 0: Bus Master Disabled 1: Bus Master Enabled This bit enables the USB Host Controller to act as a PCI master. If set to 0, no PCI access will be generated by the USB Host Controller. This bit must be set to 1 before USB transactions can start. Memory Access Enable: 0: Memory Access Disabled 1: Memory Access Enabled This bit must be set to 1 for the USB Host Controller to perform memory acces. I/O Access Enable: 0: I/O Access Disabled 1: I/O Access Enabled This bit must be set to 1 for the USB Host Controller to perform I/O access 0
1
0
0
133
PRELIMINARY
Register 3: Status Registers (Read/Write) - Index=06H with a 16-bit access Bit 15 Function
CY82C693UB
Default 0
Detected Parity Error: READ: 0: No Parity Error Detected 1: Parity Error Detected WRITE: 0: No change to register 1: Clear register This bit is set to 1 whenever the USB Host Controller detects a parity error, even if the Parity Error Detection Enable bit (command register, bit 6) is disabled. PCI SERR Status: READ: 0: No Parity Error Detected 1: Parity Error Detected WRITE: 0: No change to register 1: Clear register This bit is set to 1 when the USB Host Controller detects a PCI address parity error. PCI Master-Abort READ: 0: No PCI Master-Abort occurred 1: PCI Master-Abort occurred WRITE: 0: No change to register 1: Clear register CY82C693UB Detection of Target-Abort (from another PCI target) READ: 0: No PCI Target-Abort occurred 1: PCI Target-Abort occurred WRITE: 0: No change to register 1: Clear register CY82C693UB Assertion of Target-Abort (CY82C693UB is the target) READ: 0: No PCI Target-Abort occurred 1: PCI Target-Abort occurred WRITE: 0: No change to register 1: Clear register DEVSEL Timing Status: These register bits are Read Only and will always read as 01 (medium timing) Data Parity Reported. Not supported by CY82C693UB (PERR) Fast Back-to-Back Transfer Capable. This Read Only bit will always return 1 Reserved. Always 0.
14
0
13
0
12
0
11
0
10:9 8 7 6:0
01 0 1 0
Register 4: Revision ID Number (Read Only) - Index=08H with an 8-bit access Bit 7:0 Function Current Revision of the Part (00000000) Default 00H
134
PRELIMINARY
Register 5: Class Code Register (Read Only) - Index=09H with a 24-bit access Bit 23:0 Function Sub Class Code: Base Class Code: Serial Bus Controller (OCH) Sub Class Code: Universal Serial Bus (03H) Programming Interface: USB OpenHCI (10H)
CY82C693UB
Default 0C0310H
Register 6: Cache Line Size (Read/Write) - Index=0CH with an 8-bit access Bit 7:0 Function Cache Line Size. This register identifies the system cache line size in units of 32-bit words. The USB Host Controller will only store the value of bit 3 in this register since the cache line size of 32 bytes is the only value applicable to the design. Any value other than 08H written to this register will be read back as 00H Default 00H
Register 7: Latency Timer (Read/Write) - Index=0DH with an 8-bit access Bit 7:0 Function Latency Timer. This register identifies the value of the latency timer in PCI clocks for PCI bus master cycles. Default 00H
Register 8: Header Type Register (Read Only) - Index=0EH with an 8-bit access Bit 7:0 Function Header Type. This register identifies the type of the predefined header in the configuration space. Since the USB Host Controller is a single function device and not a PCI-to-PCI bridge, this byte should be read as 00H. Default 00H
Register 9: BIST Register (Read Only) - Index=0FH with an 8-bit access Bit 7:0 Function Built-In Self Test. This register identifies the control and status of Built-In Self Test. The USB Host Controller does not implement BIST, so this register is read only Default 00H
Register 10: Base Address Register (Read/Write) - Index=10H with a 32-bit access Bit 31:12 11:4 3 2:1 0 Function Base Address. POST writes the value of the memory base address to this register. Always 0. Indicates a 4K byte address range is requested. Always 0. Indicates there is no support for prefetchable memory. Always 0. Indicates that the base register is 32-bit wide and can be placed anywhere in 32-bit memory space. Default 00000H 00H 0 00
Always 0. Indicates that the USB Host Controller operational registers are mapped into mem- 0 ory space.
Note: The Base Address Register contains the base address of the memory-mapped USB Host Controller Operational Registers, which are defined in the next section. Register 11: Interrupt LIne Register (Read/Write) - Index=3CH with an 8-bit access Bit 7:0 Function Interrupt Line. This register identifies which of the system interrupt controllers the device's interrupt pin is connected to. The value of this register is used by the device drivers and has no direct meaning to the USB Host Controller. Default 00H
135
PRELIMINARY
Register 12: Interrupt Pin Register (Read/Write) - Index=3DH with an 8-bit access Bit 7:0 Function
CY82C693UB
Default 01H
Interrupt Pin Register. This register identifies which interrupt pin a device uses. Since the USB Host Controller uses INTA, this register is set to 01H.
Register 13: Min_Gnt Register (Read Only) - Index=3EH with an 8-bit access Bit 7:0 Function PCI Min_Gnt. This register specifies how long of a burst the USB Host Controller needs assuming a clock rate of 33 MHz. The value specifies a period of time in units of 1/4 microsecond. Default 00H
Register 14: Max_Lat Register (Read Only) - Index=3FD with an 8-bit access Bit 7:0 Function PCI Max. Latency. This register specifies how often the USB Host Controller needs access to the PCI bus assuming a clock rate of 33 MHz. The value specifies a period of time in units of 1/4 microsecond. Default 00H
Register 15: ASIC Test Mode Enable Register (Read/Write) - Index=40H with a 32-bit access Bit 31:0 Function ASIC Test Mode Enable. For normal USB Host Controller operation this register must be set to 0. Default 0XXXXXXXH
Register 16: ASIC Operational Mode Enable Register (Read/Write) - Index=44H with an 8-bit access Bit 7:0 Function ASIC Operational Mode Enable. For normal USB Host Controller operation this register must remain as 0. Default 00H
136
PRELIMINARY
USB Host Controller Operational Registers
The USB Host Controller Operational Registers are accessed using memory-mapped I/O. The address of each operational register is given by the Base Address (specified in the Base
CY82C693UB
Address Register in the USB Host Controller PCI Configuration Registers) and the offset value of the register.
Register 0: HcRevision (Read Only) - Offset=00H with a 32-bit access Bit 31:8 7:0 Function Reserved. Revision Number. Indicates the OpenHCI Specification revision number implemented by the hardware. Default 000000H 10H
Register 1: HcControl (Read/Write) - Offset=04H with a 32-bit access Bit 31:11 10 Function Reserved. Remote Wakeup Connected Enable: If a remote wakeup signal is supported, this bit is used to enable that operation. Since there is no remote wakeup signal supported, this bit is ignored. Remote Wakeup Connected: This Read Only bit indicated whether the Host Controller supports a remote wakeup signal. This implementation does not support any such signal. The bit is hard-coded to 0. Interrupt Routing: This bit is used for interrupt routing: 0: Interrupt routed to normal interrupt mechanism (INT) 1: Interrupt routed to SMI Host Controller Functional State: This field is used to set the Host Controller state. The state encoding are: 00: USBReset 01: USBResume 10: USBOperational 11: USBSuspend The USB Host Controller may force a state change from USBSuspend to USBResume after detecting resume signaling from a downstream port. Bulk List Enable: When set this bit enables processing of the Bulk list. Control List Enable: When set this bit enables processing of the Control list. Isochronous Enable: When cleared, this bit disables the Isochronous List when the Periodic List is enabled (so Interrupt EDs may be serviced). While processing the Periodic List, the Host Controller will check this bit when it finds an isochronous ED. Periodic List Enable: When set, this bit enables processing of the Periodic (interrupt and isochronous) list. The Host Controller checks this bit prior to attempting any periodic transfer in a frame. Control Bulk Service Ratio: Specifies the number of Control Endpoints serviced for every Bulk Endpoint. Encoding is N-1 where N is the number of Control Endpoints (i.e., `00' = 1 Control Endpoint; `11' = 4 Control Endpoints). Default 0H 0
9
0
8
0
7:6
00
5 4 3
0 0 0
2
0
1:0
00
137
PRELIMINARY
Register 2: HcCommandStatus (Read/Write) - Offset=08H with a 32-bit access Bit 31:18 17:16 Function Reserved.
CY82C693UB
Default 00
Schedule Overrun Count: This field increments every time the SchedulingOverrun bit in HcInterruptStatus is set. The count wraps from `11' to `00'. Reserved. Ownership Change Request: When set by software, this bit sets the OwnershipChange field in HcInterruptStatus. The bit is cleared by software. Bulk List Filled: When set, this bit indicates there is an active ED on the Bulk List. the bit may be set by either software or the Host Controller. The bit is cleared by the Host Controller each time it begins processing the head of the Bulk List Control List Filled: When set, this bit indicates there is an active ED on the Control List. The bit may be set by either software or the Host Controller. The bit is cleared by the Host Controller each time it begins processing the head of the Control List Host Controller Reset: This bit is set to initiate a software reset. This bit is cleared by the Host Controller upon completion of the reset operation
15:4 3
0H 0
2
0
1
0
0
0
Register 3: HcInterruptStatus (Read/Write) - Offset=0CH with a 32-bit access Bit 31 30 29:7 6 Function Reserved. Ownership Change: This bit is set when the OwnershipChangeRequest bit of HcCommandStatus is set. Reserved. Root Hub Status Change: This bit is set when the content of HcRhStatus or the content of any HcRhPortStatus register has changed FrameNumber Overflow: This bit is set when bit 15 of FrameNumber changes value from `0' to `1' or from `1' to `0'. Unrecoverable Error: Read Only. This event is not implemented and is hard-coded to `0'. All writes are ignored. Resume Dectected: This bit is set when the Host Controller detects resume signaling on a downstream port. Start Of Frame: This bit is set when the Frame Management block signals a `Start of Frame' event. Writeback Done Head: This bit is set after the Host Controller has written HcDoneHead to HccaDoneHead. Scheduling Overrun: This bit is set when the List Processor determines a Schedule Overrun has occurred. Default 0 0 0H 0
5 4 3 2 1 0
0 0 0 0 0 0
138
PRELIMINARY
Register 4: HcInterruptEnable (Read/Write) - Offset=10H with a 32-bit access Bit 31 Function
CY82C693UB
Default 0
Master Interrupt Enable: This bit is a global interrupt enable. A write of `1' allows interrupts to be enabled via the specific enable bits listed below. Ownership Change Enable: 0: Ignore 1: Enable interrupt generation due to Ownership Change Reserved. Root Hub Status Change Enable: 0: Ignore 1: Enable interrupt generation due to Root Hub Status Change Frame Number Overflow Enable: 0: Ignore 1: Enable interrupt generation due to Frame Number Overflow Unrecoverable Error Enable: This event is not implemented. All writes to this bit will be ignored. Resume Detected Enable: 0: Ignore 1: Enable interrupt generation due to Resume Detected Start Of Frame Enable: 0: Ignore 1: Enable interrupt generation due to Start of Frame Writeback Done Head Enable: 0: Ignore 1: Enable interrupt generation due to Writeback Done Head Scheduling Overrun Enable: 0: Ignore 1: Enable interrupt generation due to Scheduling Overrun
30
0
29:7 6
0H 0
5
0
4 3
0 0
2
0
1
0
0
0
139
PRELIMINARY
Register 5: HcInterruptDisable (Read/Write) - Offset=14H with a 32-bit access Bit 31 30 Function Master Interrupt Enable: This bit is a global interrupt disable. A write of `1' disables all interrupts. Ownership Change Enable: 0: Ignore 1: Disable interrupt generation due to Ownership Change Reserved. Root Hub Status Change Enable: 0: Ignore 1: Disable interrupt generation due to Root Hub Status Change Frame Number Overflow Enable: 0: Ignore 1: Disable interrupt generation due to Frame Number Overflow Unrecoverable Error Enable: This event is not implemented. All writes to this bit will be ignored. Resume Detected Enable: 0: Ignore 1: Disable interrupt generation due to Resume Detected Start Of Frame Enable: 0: Ignore 1: Disable interrupt generation due to Start of Frame Writeback Done Head Enable: 0: Ignore 1: Disable interrupt generation due to Writeback Done Head Scheduling Overrun Enable: 0: Ignore 1: Disable interrupt generation due to Scheduling Overrun
CY82C693UB
Default 0 0
29:7 6
0H 0
5
0
4 3
0 0
2
0
1
0
0
0
Register 6: HcHCCA (Read/Write) - Offset=18H with a 32-bit access Bit 31:8 7:0 Function HCCA: Pointer to HCCA base address. Reserved. Default 0H 0H
Register 7: HcPeriodCurrentED (Read/Write) - Offset=1CH with a 32-bit access Bit 31:4 3:0 Function Period Current ED: Pointer to the current Periodic List ED. Reserved. Default 0H 0H
Register 8: HcControlHeadED (Read/Write) - Offset=20H with a 32-bit access Bit 31:4 3:0 Function Control Head ED: Pointer to the Control List Head ED. Reserved. Default 0H 0H
140
PRELIMINARY
Register 9: HcControlCurrentED (Read/Write) - Offset=24H with a 32-bit access Bit 31:4 3:0 Function Control Current ED: Pointer to the current Control List ED. Reserved.
CY82C693UB
Default 0H 0H
Register 10: HcBulkHeadED (Read/Write) - Offset=28H with a 32-bit access Bit 31:4 3:0 Function Bulk Head ED: Pointer to the Bulk List Head ED. Reserved. Default 0H 0H
Register 11: HcBulkCurrentED (Read/Write) - Offset=2CH with a 32-bit access Bit 31:4 3:0 Function Bulk Current ED: Pointer to the current Bulk List ED. Reserved. Default 0H 0H
Register 12: HcDoneHead (Read/Write) - Offset=30H with a 32-bit access Bit 31:4 3:0 Function Done Head: Pointer to the current Done List Head ED. Reserved. Default 0H 0H
Register 13: HcFmInterval (Read/Write) - Offset=34H with a 32-bit access Bit 31 30:16 Function Frame Interval Toggle: This bit is toggled by Host Controller Driver whenever it loads a new value into FrameInterval. FS Largest Data Packet: This field specifies a value which is loaded into the Largest Data Packet Counter at the beginning of each frame. Reserved. Frame Interval: This field specifies the length of a frame as (bit times - 1). For 12,000 bit times in a frame, a value of 11,999 is stored here. 0H 2EDFH Default
15:14 13:0
Register 13: HcFrameRemaining (Read Only) - Offset=38H with a 32-bit access Bit 31 30:14 13:0 Function Frame Remaining Toggle: This bit is loaded with FrameIntervalToggle when FrameRemaining is loaded. Reserved. Default 0 0H
Frame Remaining: 0H This field is a 14 bit decrementing counter used to time a frame. When the Host Controller is in the USBOperational state the counter decrements each 12 MHz clock period. When the count reaches 0, the end of a frame has been reached. The counter reloads with FrameInterval at that time. In addition, the counter loads when the Host Controller transitions into USBOperational state.
141
PRELIMINARY
Register 14: HcFmNumber (Read Only) - Offset=3CH with a 32-bit access Bit 31:16 15:0 Function Reserved.
CY82C693UB
Default 0H 0H
Frame Number: This field is a 16 bit incrementing counter. The count is incremented coincident with the loading of FrameRemaining. The count will roll over from `FFFFH' to `0H.'
Register 15: HcPeriodicStart (Read/Write) - Offset=40H with a 32-bit access Bit 31:14 13:0 Function Reserved. Periodic Start: This field contains a value used by the List Processor to determine where in a frame the Periodic List processing must begin. Default 0H 0H
Register 16: HcLSThreshold (Read/Write) - Offset=44H with a 32-bit access Bit 31:12 11:0 Function Reserved. LS Threshold: This field contains a value used by the Frame Management block to determine whether or not a low speed transaction can be started in the current frame. Default 0H 0H
Register 17: HcRhDescriptorA (Read/Write) - Offset=48H with a 32-bit access Bit 31:24 Function Power On To Power Good Time: Host Controller power switching is effective within 2 ms. The field value is represented as the number of 2 ms intervals. Only bits [25:24] are implemented as Read/Write. The remaining bits are Read Only as `0'. It is not expected that these bits be written to anything other than 1H, but limited adjustment is provided. This field should be written to support the system implementation. This field should always be written to a non-zero value. Reserved. No Over Current Protection: The Host Controller implements global over-current reporting 0: Over-current status is reported 1: Over-current status is not reported This bit should be written to support the external system port over-current implementation. Default 01H
23:13 12
0H 0H
11
Over Current Protection Mode: 0 The Host Controller implements global over-current reporting 0: Global Over-Current 1: Individual Over-Current This bit is only valid when NoOverCurrentProtection is cleared. This bit should be written `0'. Device Type: Read Only. The CY82C693UB USB Host Controller is not a compound device. 0
10 9
No Power Switching: 0 The Host Controller implements a global power switching mode. 0: Ports are power switched 1: Ports are always powered on This bit should be written to support the external system port power switching implementation. Power Switching Mode: The Host Controller implements a global power switching mode. 0: Global Switching 1: Individual Switching This bit is only valid when NoPowerSwitching is cleared. this bit should be written `0'. Number Downstream Ports: Read Only. The CY82C693UB USB Host Controller supports two downstream ports. 0
8
7:0
02H
142
PRELIMINARY
CY82C693UB
Note: This register is only reset by a power-on reset (PCIRST). It is written during system initialization to configure the Root Hub. These bit should not be written during normal operation. Register 18: HcRhDescriptorB (Read/Write) - Index=4CH with a 32-bit access Bit 31:16 Function Port Power Control Mask: The Host Controller implements global-power switching. This field is only valid if NoPowerSwitching is cleared and PowerSwitchingMode is set (individual port switching). When set, the port only responds to individual port power switching commands (Set/ClearPortPower). When cleared, the port only responds to global power switching commands (Set/ClearGlobalPower). 0: Device not removable 1: Global-power mask Port bit relationship: bit 16: Reserved bit 17: Port 1 bit 18: Port 2 ... bit 31: Port 15 Unimplemented ports are reserved, read/write `0'. Device Removable: The Host Controller ports default to removable devices. 0: Device not removable 1: Device removable Port Bit relationship: 0: Reserved 1: Port 1 2: Port 2 ... 15: Port 15 Unimplemented ports are reserved, read/write `0'. Default 0000H
15:0
0000H
Note: THis register is only reset by power-on reset (PCIRST). It is written during system initialization to configure the Root Hub. These bits should not be written during normal configuration.
143
PRELIMINARY
Register 19: HcRhStatus (Read/Write) - Index=50H with a 32-bit access Bit 31 Function
CY82C693UB
Default 0
Clear Remote Wakeup Enable: Write Only. Writing a `1' to this bit clears DeviceRemoteWakeupEnable. Writing a `0' has no effect. Reserved. Over Current Indicator Change: This bit is set when OverCurrentIndicator changes. Writing a `1' clears this bit. Writing a `0' has no effect. READ: Local Power Status Change. Not supported. Always read `0'. WRITE: Set Global Power. Writing a `1' issues a SetGlobalPower command to the ports. Writing a `0' has no effects. READ: Device Remote Wakeup Enable. This bit enables ports' ConnectStatusChange as a remote wakeup event: 0: Disabled 1: Enabled WRITE: Set Remote Wakeup Enable. Writing a `1' sets DeviceRemoteWakeupEnable. Writing a `0' has no effect. Reserved.
30:18 17
0H 0
16
0
15
0
14:2 1
0H
Over Current Indicator: This bit reflects the state of the OVRCUR pin. This field is only valid if NoOverCurrentProtection and OverCurrentProtectionMode are cleared. 0: No over-current condition 1: Over-current condition READ: Local Power Status. Not supported. Always read `0'. WRITE: Clear Global Power. Writing a `1' issues a ClearGlobalPower command to the ports. Writing a `0' has no effect. 0
0
Note: This register is reset by the USBReset state.
144
PRELIMINARY
Register 20: HcRhPortStatus[1:2] (Read/Write) - Index=54H, 58H with a 32-bit access Bit 31:21 20 Function Reserved. Port Reset Status Change: This bit indicates that the port reset signal has completed. 0: Port reset is not complete 1: Port reset is complete
CY82C693UB
Default 0H 0
19
Port Over Current Indicator Change: This bit is set when OverCurrentIndicator changes. Writing a `1' clears this bit. Writing a `0' has no effect. Port Suspend Status Change: This bit indicates the completion of the selective resume sequence for the port. 0: Port is not resumed 1: Port resume is complete Port Enable Status Change: This bit indicates that the port has been disabled due to a hardware event (cleared PortEnableStatus). 0: Port has not been disabled 1: PortEnableStatus has been cleared Connect Status Change: This bit indicates a connect or disconnect event has been detected. Writing a `1' clears this bit. Writing a `0' has no effect. 0: No connect/disconnect event 1: Hardware detection of connect/disconnect event Note: If DeviceRemovable is set, this bit resets to `1'. Reserved.
0
18
0
17
0
16
0
15:10 9
0H
READ: 0 Low Speed Device Attached. This bit defines the speed (and bus idle) of the attached device. It is only valid when CurrentConnectStatus is set. 0: Full Speed device 1: Low Speed device WRITE: Clear Port Power. Writing a `1' clears PortPowerStatus. Writing a `0' has no effect. READ: Port Power Status. This bit reflects the power state of the port regardless of the power switching mode. 0: Port power is off 1: Port power is on Note: if NoPowerSwitching is set, this bit is always read as `1'. WRITE: Set Port Power. Writing a `1' sets PortPowerStatus. Writing a `0' has no effect. Reserved. READ: Port Reset Status. 0: Port reset signal is not active 1: Port reset signal is active WRITE: Set Port Reset. Writing a `1' sets PortResetStatus. Writing a `0' has no effect. READ: Port Over Current Indicator. The Host Controller supports global over-current reporting. This bit reflects the state of the OVRCUR pin dedicated to this port. This field is only valid if NoOverCurrentProtection is cleared and OverCurrentProtectionMode is set. 0: No over-current condition 1: Over-current condition WRITE: Clear Port Suspend. Writing a `1' initiates the selective resume sequence for the port. Writing a `0' has no effect. 0
8
7:5 4
0H 0
3
0
145
PRELIMINARY
CY82C693UB
Default 0
Register 20: HcRhPortStatus[1:2] (Read/Write) - Index=54H, 58H with a 32-bit access (continued) Bit 2 Function READ: Port Suspend Status. 0: Port is not suspended 1: Port is selectively suspended WRITE: Set Port Suspend. Writing a `1' sets PortSuspendStatus. Writing a `0' has no effect READ: Port Enable Status. 0: Port disabled 1: Port enabled WRITE: Set Port Enable. Writing a `1' sets PortEnableStatus. Writing a `0' has no effect. READ: Current Connect Status. 0: No device connected 1 Device connected Note: If DeviceRemovable is set (not removable) this bit is always `1'. WRITE: Clear Port Enable. Writing a `1' clears PortEnableStatus. Writing a `0' has no effect.
1
0
0
0
Note: This register is reset by the USBReset state. Register 21: HceControl (Read/Write) - Index=100H with a 32-bit access Bit 31:9 8 Function Reserved. A20 State: Indicates current state of Gate A20 on keyboard controller. Used to compare against value written to 60H when GateA20Sequence is active. Default 0H 0
7
IRQ12 Active: 0 Indicates that a positive transition on IRQ12 from keyboard controller has occurred. Software may write a `1' to this bit to clear it (set it to `0'). Software write of a `0' to this bit has no effect. IRQ1 Active: 0 Indicates that a positive transition on IRQ1 from keyboard controller has occurred. Software may write a `1' to this bit to clear it (set it to `0'). Software write of a `0' to this bit has no effect. Gate A20 Sequence: Set by the Host Controller when a data value of D1H is written to I/O port 64H. Cleared by the Host Controller on write to I/O port 64H of any value other than D1H. 0
6
5
4
External IRQEn: 0 When set to `1', IRQ1 and IRQ12 from the keyboard controller will cause an emulation interrupt. The function controlled by this bit is independent of the setting of the EmulationEnable bit in this register. IRQEn: When set the Host Controller will generate IRQ1 or IRQ12 as long as the OutputFull bit in HceStatus is set to `1'. If the AuxOutputFull bit of HceStatus is `0' then IRQ1 is generated and if it is `1', then an IRQ12 is generated. Character Pending: When set, an emulation interrupt will be generated when the OutputFull bit of the HceStatus register is set to `0'. Emulation Interrupt: This bit is a static decode of the emulation interrupt condition. 0
3
2
0
1 0
0
Emulation Enable: 0 When set to `1' the Host Controller will be enabled for legacy emulation. The Host Controller will decode accesses to I/O registers 60H and 64H and generate IRQ1 and/or IRQ12 when appropriate. Additionally, the Host Controller will generate an emulation interrupt at appropriate times to invoke the emulation software.
Note: This register is used to enable and control the legacy keyboard and mouse emulation hardware and report various status information.
146
PRELIMINARY
Register 22: HceInput - Index=104H with a 32-bit access Bit 31:8 7:0 Function Reserved. Input Data: This register holds data that is written to I/O ports 60H and 64H.
CY82C693UB
Default 0H -
Note: This register is the emulation side of the legacy Input Buffer Register. Register 23: HceOutput - Index=108H with a 32-bit access Bit 31:8 7:0 Function Reserved. Default 0H
Output Data: This register hosts data that is returned when an I/O read of port 60H is performed by application software.
Note: This register is the emulation side of the legacy Output Buffer register where keyboard and mouse data is to be read by software. Register 24: HceStatus (Read/Write) - Index=10CH with a 32-bit access Bit 31:8 7 6 5 Function Reserved. Parity: Indicates parity error on keyboard/mouse data. Timeout: Used to indicate a time-out. Aux Output Full: IRQ12 is asserted whenever this bit is set to `1' and OutputFull is set to `1' and the IRQEn bit is set. Inhibit Switch: This bit reflects the state of the keyboard inhibit switch and is set if the keyboard is NOT inhibited. Cmd Data: The Host Controller will set this bit to `0' on an I/O write to port 60H and on an I/O write to port 64H the Host Controller will set this bit to `1'. Flag: Nominally used as a system flag by software to indicate a warm or cold boot. Input Full: Except for the case of a Gate A20 sequence, this bit is set to `1' on an I/O write to address 60H or 64H. While this bit is set to `1' and emulation is enabled, an emulation interrupt condition exists. Output Full: The Host Controller will set this bit to `0' on a read of I/O port 60H. If IRQEn is set and AuxOutputFull is set to `0' then an IRQ1 is generated as long as this bit is set to `1'. If IRQEn is set and AuxOutputFull is set to `1' then an IRQ12 will be generated as long as this bit is set to `1'. While this bit is `0' and CharacterPending in HceControl is set to `1', an emulation interrupt condition exists. Default 0H 0 0 0
4
0
3
0
2 1
0 0
0
0
Note: This register is the emulation side of the legacy Status register.
147
PRELIMINARY
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Supply Voltage (VCC) ......................................................+7 V Ambient Storage Temperature ........................ -40C to 125C DC Voltage Applied to Outputs ............................ -0.5V to VDD
CY82C693UB
Operating Range
Range Commercial Ambient Temperature 0C to +70C VDD VDDQ
5V 5% 3.3V 0.3V
Extended Temp -40C to +85C 5V 5% 3.3V 0.3V
Electrical Characteristics Over the Operating Range (TA=0C to 70C)
Parameter VCC VDD VIL VIH VOL VOH IIL IOL CIN COUT ICC Core Supply Voltage 3.3V I/O Supply Voltage Input LOW Voltage Input HIGH Voltage Output LOW Voltage Output HIGH Voltage Input Leakage Current Output Leakage Input Capacitance Output Capacitance Power Supply Current 66 MHz 2.4 10 10 10 10 TBD Description Min. 4.5 3.0 -0.5 2.0 Max. 5.5 VCC 0.8 VDD+0.5 0.4 Unit V V V V V V A A pF pF mA
148
PRELIMINARY
Switching Waveforms
PCI to ISA RD Cycle - No Data Packing (Part 1 of 2)
SUBTRACTIVE DECODE
CY82C693UB
CLK EDGE A
PCICLK
FRAME
VALIDI SA ADDRESS
PAD[31:0]
PC/BE[31:0] DEVSEL
MEMORY READ
VALID BYTEENABLES
IRDY TRDY
ATCLK
BALE
LA[17:23] SA[19:0]SBHE
VALID ADDRESS
VALID ADDRESS
MRD OR IOR
SD[15:0] IOCHRDY (STANDARD OR 0WS) IOCHRDY (WAIT STATES) 0WS (STANDARD OR WAIT STATES) 0WS (0WS)
149
PRELIMINARY
Switching Waveforms (continued)
PCI to ISA RD Cycle - No Data Packing (Part 2 of 2)
CLK EDGE A
CY82C693UB
PCICLK
FRAME
PAD[31:0]
VALID DATA
PC/BE[31:0] DEVSEL
VALID BYTE ENABLES
IRDY TRDY
ATCLK
BALE
VALID ADDRESS
LA[17:23] SA[19:0]SBHE
VALID ADDRESS
MRD OR IOR
SD[15:0] IOCHRDY (STANDARD OR 0WS) IOCHRDY (WAIT STATES) 0WS (STANDARD OR WAIT STATES) 0WS (0WS)
VALID DATA
150
PRELIMINARY
Switching Waveforms (continued)
PCI Write to ISA Post Write Buffer (Subtractive Decode Set to 6 CLKS)
CY82C693UB
FRAME
ISA ADDRESS MEM WRITE
PAD[31:0]
VALID DATA
PC/BE[31:0] DEVSEL
OR IO WRITE
VALID BYTE ENABLES
IRDY TRDY
151
PRELIMINARY
Switching Waveforms (continued)
DMA/Master Operation (Memory Read/IO Write)
CY82C693UB
ATCLK
DRQX
DACKX
AEN, BALE LA[17:23] SA[19:0] SBHE IOCHRDY
VALID MEMORY ADDRESS
MRD IOW
SD[15:0]
VALID DATA
PCICLK
FREQACK
693
691
GNTBSY
FRAME
MEM ADDR
PAD[31:0]
DATA
PC/BE[3:0] IRDY
MEM RD
BYTE ENABLES
TRDY
152
PRELIMINARY
Switching Waveforms (continued)
DMA/Master Operation (IO Read/Memory Write)
ATCLK
CY82C693UB
DRQX
DACKX
AEN, BALE LA[17:23] SA[19:0] SBHE IOCHRDY
VALID MEMORY ADDRESS
MWT IOR
SD[15:0]
VALID DATA
PCICLK
FREQACK
693
691
GNTBSY
FRAME
PAD[31:0]
ADDR
VALID DATA
PC/BE[3:0] IRDY
MEM WR
BYTE ENABLES
TRDY
153
PRELIMINARY
Switching Waveforms (continued)
Reset
IMS
CY82C693UB
OSC
PWGD
TRESETD
COLD RESET
PCIRST
CPURST
TRESETSU
PCICLK INIT (WARM RESET)
TWRESETDR TWRESETDF
154
PRELIMINARY
Switching Waveforms (continued)
Power Management (Hardware Controlled)
CY82C693UB
ATCLK
PCICLK
STOPCLK
STOP CLK THROTTLE LOW TIME
STOP CLK THROTTLE HIGH TIME
Power Management (Software Controlled)
tSMEH
CPUCLK
tSMEH
SMI
tSMISU tSMIH
155
PRELIMINARY
Switching Waveforms (continued)
IDE PIO Transfer
PIDE t0
CY82C693UB
PIDEt9 PIDECSO/I,PCIIDEA[2:0] PIDEt1 IDEIOR/IDEIOW PIDEt2i PCIIDE[15:0](WRITE) PIDEt2 PCIIDE[15:0](READ) PIDEt7 IDEIOCS16(MODE 0, 1, 2 ONLY) PIDEtA PIDEt5 PIDEt6 PIDEt6Z PIDEt4
VALID IDE ADDRESS
PIDEt2
PIDEt8
IOCHRDY (NO WAIT STATES) PIDEtRD
IOCHRDY (GENERATED WAIT) PIDEtB
Single Word DMA Transfer
t0* DMARQ tC* DMACK tI* IDEIOR/IDEIOW tD* READ PCIIDE(15:0) tE* WRITE PCIIDE(15:0) tG* tH* tS* tF* tJ*
*Preface all of these indices with SWIPEDMA (e.g. TH becomes SWPIDEDMA tH)
156
PRELIMINARY
Switching Waveforms (continued)
Multiword DMA Transfer
t0* DMARQ tL* DMACK tI* IDEIOR/IDEIOW tE* READ PCIIDE(15:0) tGr* WRITE PCIIDE(15:0) tGw* tH* tF* tD* tK* tJ*
CY82C693UB
tZ*
157
PRELIMINARY
Switching Waveforms (continued)
AT Refresh Timing
CY82C693UB
ATCLK T118 REFSH T120
MEMR SMEMR
T119
XA [10:0]
ROW ADDRESS
Interrupt Acknowledge Cycle
PCICLK
FRAME PAD[31:0]
INTERRUPT VECTOR
PC/BE[3:0]
INTERRUPT ACKNOWLEDGE
LOW ORDER BYTE ENABLED
IRDY
TRDY
158
PRELIMINARY
Switching Waveforms (continued)
CY82C693 Configuration Access
CY82C693UB
PCICLK
FRAME PAD[31:0]
CONFIG ADDRESS CONFIG DATA
IDSEL PIN OF 693 PC/BE[3:0]
CONFIG RD OR WR VALID BYTEENABLES
IRDY
TRDY
DEVSEL
159
PRELIMINARY
Switching Waveforms (continued)
CY82C693UB
693 Generated Retry (For Accesses Requiring More Than 16 PCI Clock Cycles to Complete)
16 PCI CLOCK CYCLES
PCICLK RETRY CYCLE FRAME
693 ADDRESS 693 ADDRESS
PAD[31:0]
PC/BE[3:0]
WR OR RD
VALID BYTE ENABLES
WR OR RD
IRDY
TRDY
STOP
DEVSEL
160
PRELIMINARY
Switching Waveforms (continued)
693 PCI Disconnect on a NON-Burst Cycle (If Initiator does not Deassert Frame)
CY82C693UB
PCICLK
FRAME
693 ADDRESS
PAD[31:0]
VALID DATA
PC/BE[3:0]
WR OR RD
VALID BYTE ENABLES
IRDY
TRDY
STOP
DEVSEL
161
PRELIMINARY
Switching Waveforms (continued)
ISA Master Memory Pre-Read
CY82C693UB
PCICLK FRAME
IRDY DEVSEL
TRDY
A/D
A
D0
D1
A D0
D1
A
D0
D1
A+1
D0
C/BE
C
BE0
BE1
C BE0 BE1
C
BE0 BE1
C
BE0 STOP
1WS BURST WRITE WITH FASTEST TARGET
0 WS BURST WRITE WITH FASTEST TARGET
0WS BURST WRITE DISCONNECT & RETRY WITH FASTEST TARGET
82C693UB-4
162
PRELIMINARY
Switching Waveforms (continued)
PCI Master Subtractive Decode "DEVSEL" Timing
CY82C693UB
PCI Master Subtractive Decode "DEVSEL" Timing
5
5 PCICLK
PCICLK FRAME
FRAME IRDY IRDY DEVSEL DEVSEL TRDY/ STOP TRDY/ STOP (SUB-DECODE=6PCICLK)
82C693UB-5
(SUB-DECODE=5PCICLK)
82C693UB-6
PCI Master Subtractive Decode "DEVSEL" Timing
5 PCICLK FRAME IRDY
PCI Master Subtractive Decode "DEVSEL" Timing
5 PCICLK FRAME IRDY
DEVSEL TRDY/ STOP (SUB-DECODE=4PCICLK)
82C693UB-7
DEVSEL TRDY/ STOP (SUB-DECODE=3PCICLK)
82C693UB-8
Ordering Information
Ordering Code CY82C693UB-NC CG4973AT Document #: 38-00684 Package Name N208 N208 Package Type 208-Lead Plastic Quad Flat Pack 208-Lead Plastic Quad Flat Pack Operating Range Commercial Extended Temp
163
PRELIMINARY
Package Diagram
208-Lead Plastic Quad Flatpack N208
CY82C693UB
(c) Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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