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DS8908B AM FM Digital Phase-Locked Loop Frequency Synthesizer
June 1990
DS8908B AM FM Digital Phase-Locked Loop Frequency Synthesizer
General Description
The DS8908B is a PLL synthesizer designed specifically for use in AM FM radios It contains the reference oscillator a phase comparator a charge pump an operational amplifier a 120 MHz ECL I2L dual modulus programmable divider and a 19-bit shift register latch for serial data entry The device is designed to operate with a serial data controller generating the necesary division codes for each frequency and logic state information for radio function inputs outputs A 3 96 MHz pierce oscillator and divider chain generate a 1 98 MHz external controller clock a 20 kHz 10 kHz 9 kHz and a 1 kHz reference signals and a 50 Hz time-of-day signal The oscillator and divider chain are sourced by the VCCM pin thus providing a low power controller clock drive and time-of-day indication when the balance of the PLL is powered down The 21-bit serial data steram is transferred between the frequency synthesizer and the controller via a 3-wire bus system comprised of a data line a clock line and an enable line The first 2 bits in the serial data stream address the synthesizer thus permitting other devices such as display drivers to share the same bus The next 14 bits are used for the PLL(N a 1) divide code The 15th bit is used internally to select the AM or FM local oscillator input A high level on this bit enables the FM input and a low level enables the AM input The 16th and 17th bits are used to select one of the 4 reference frequencies The 18th and 19th bits are connected via latches to open collector outputs These outputs can be used to drive radio functions such as gain mute AM FM or charge pump current source levels The PLL consists of a 14-bit programmable I2L divider an ECL phase comparator an ECL dual modulus (p p a 1) prescaler a high speed charge pump and an operational amplifier The programmable divider divides by (N a 1) N being the number loaded into the shift register The programmable divider is clocked through a d prescaler by the AM input or through a d prescaler by the FM input The AM input will work at frequencies up to 15 MHz while the FM input works up to 120 MHz The VCO can be tuned with a frequency resolution of either 1 kHz 9 kHz 10 kHz or 20 kHz The buffered AM and FM inputs are self-biased and can be driven directly by the VCO through a capacitor The ECL phase comparator produces very accurate resolution of the phase difference between the input signal and the reference oscillator The high speed charge pump consists of a switchable constant current source and sink The charge pump can be programmed to deliver from 75 mA to 750 mA of constant current by connection of an external resistor from pin RPROGRAM to ground or the open collector bit outputs Connection of programming resistors to the bit outputs enables the controller to adjust the loop gain for the particular reference frequency selected The charge pump will source current if the VCO frequency is high and sink
TRI-STATE is a registered trademark of National Semiconductor Corp C1995 National Semiconductor Corporation TL F 5111 RRD-B30M105 Printed in U S A
current if the VCO frequency is low The low noise operational amplifier provided has a high impedance JFET input and a large output voltage range The op amp's negative input is common with the charge pump output and its positive input is internally biased
Features
Y Y
Y
Y Y
Y
Y
Y
Y
Uses inexpensive 3 96 MHz reference crystal FIN capability greater than 120 MHz allows direct synthesis at FM frequencies FM resolution of either 10 kHz or 20 kHz allows usage of 10 7 MHz ceramic filter distribution Serial data entry for simplified control 50 Hz output for time-of-day reference driven from separate low power VCCM 2 open collector buffered outputs for controlling various radio functions or loop gain Separate AM and FM inputs AM input has 15 mV (typical) hysteresis Programmable charge pump current sources enable adjustment of system loop gain Operational amplifier provides high impedance load to charge pump output and a wide voltage range for the VCO input
Connection Diagram
Dual-In-Line Package
Top View Order Number DS8908BN See NS Package Number N20A
TL F 5111 - 1
Absolute Maximum Ratings (Note 1)
If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage (VCC1) (VCCM) (VCC2) Input Voltage Output Voltage 7V 17V 7V 7V
b 65 C to a 150 C Storage Temperature Range Lead Temperature (Soldering 4 seconds) 260 C
Operating Conditions
VCC1 VCC2 VCCM Temperature TA Min 45 VCC1 a 1 5 35 b 40 Max 55 15 0 55 a 85 Units V V V C
DC Electrical Characteristics (Notes 2 and 3)
Symbol VIH IIH VIL IIL IOH Parameter Logical ``1'' Input Voltage Logical ``1'' Input Current Logical ``0'' Input Voltage Logical ``0'' Input Current Logical ``1'' Output Current All Bit Outputs 50 Hz Output 1 98 MHz Output VOL Logical ``0'' Output Voltage All Bit Outputs 50 Hz Output 1 98 MHz Output 1 98 MHz Output ICC1 ICCM IOUT Supply Current (VCC1) VCCM Supply Current Charge Pump Ougtput Current Data Clock and ENABLE Inputs VIN e 0V VOH e 5 5V VOH e 2 4V VCCM e 4 5V IOL e 5 mA IOL e 250 mA IOL e 20 mA TA l 70 C IOL e 20 mA TA s 70 C All Bit Outputs High VCCM e 5 5V All Other Pins Open 3 33k s RPROG s 33 3k IOUT Measured between Pin 17 and Pin 18 IPROG e VCC1 2 RPROG Pump Up Pump Down TRI-STATE
b 20 b 20 b5
Conditions
Min 20
Typ
Max
Units V
VIN e 2 7V
0
10 08
b 25
mA V mA mA mA V V V V mA mA % % nA mA V
50
b 250
05 05 03 04 160 25 IPROG IPROG 0 67 VCC2 b0 4 06 100 40
a 20 a 20
11 11
ICC2 OPVOH OPVOL CPOBIAS
VCC2 Supply Current Op Amp Minimum High Level Op Amp Maximum Low Level Charge Pump Bias Voltage Delta
VCCM e 5V VCC1 e 5 5V VCC2 e 15V All Other Pins Open VCC1 e 4 5V IOH e b750 mA VCC1 e 5 5V IOL e 750 mA CPO Shorted to Op Amp Output CPO e TRI-STATE Op Amp IOL 750 mA vs b750 mA TA e 25 C tr s 10 ns tf s 10 ns Conditions AM and FM Inputs b40 C s TA s 85 C AM and FM Inputs b40 C s TA s 85 C VIN e 100 mV rms b 40 C s TA s 85 C 120 MHz VIN e 100 mV rms 15 MHz VIN e 100 mV rms VIN e 120 MHz (FM) 15 MHz (AM) AM FM 1000 05 80 600 1000 3 6 625 Min
V mV
AC Electrical Characteristics VCC e 5V
Symbol VIN(MIN)(F) VIN(MAX)(F) FOPERATE RIN(FM) RIN(AM) CIN tEN1 Parameter FIN Minimum Signal Input FIN Maximum Signal Input Operating Frequency Range (Sine Wave Input) AC Input Resistance FM AC Input Resistance AM Input Capacitance FM and AM Minimum ENABLE High Pulse Width
Typ 20 1500
Max 100
Units mV(rms) mV(rms)
15 120
MHz MHz X X
10 1250
pF ns
2
AC Electrical Characteristics VCC e 5V
Symbol tEN0 tCLKEN0 Parameter Minimum ENABLE Low Pulse Width Minimum Time before ENABLE Goes Low That CLOCK Must Be Low Minimum Time after ENABLE Goes Low That CLOCK Must Remain Low Minimum Time before ENABLE Goes High That Last Positive CLOCK Edge May Occur Minimum Time after ENABLE Goes High before an Unused Positive CLOCK Edge May Occur Minimum CLOCK High Pulse Width Minimum CLOCK Low Pulse Width Minimum DATA Set-Up Time Minimum Time before CLOCK That DATA Must Be Valid Minimum DATA Hold Time Minimum Time after CLOCK That DATA Must Remain Valid
TA e 25 C tr s 10 ns tf s 10 ns (Continued) Conditions Min Typ 375 Max 750 Units ns
b 50
0
ns
tEN0CLK
275
550
ns
tCLKEN1
300
600
ns
tEN1CLK
175
350
ns
tCLKH tCLKL tDS
275 400
550 800
ns ns
150
300
ns
tDH
400
800
ns
Note 1 ``Absolute Maximum Ratings'' are those values beyond which the safety of the device cannot be guaranteed Except for ``Operating Temperature Range'' they are not meant to imply that the devices should be operated at these limits The table of ``Electrical Characteristics'' provides conditions for actual device operation Note 2 Unless otherwise specified min max limits apply across the b 40 C to a 85 C temperature range for the DS8908B Note 3 All currents into device pins shown as positive out of device pins as negative all voltage referenced to ground unless otherwise noted All values shown as max or min on absolute value basis
Schematic Diagrams (DS8908B AM
FM PLL Typical Input Output Schematics)
TL F 5111 - 4
TL F 5111-2
TL F 5111 - 3
3
Schematic Diagrams (Continued)
TL F 5111 - 6
TL F 5111 - 7 TL F 5111-5
TL F 5111 - 8
4
Schematic Diagrams (Continued)
TL F 5111 - 9
Timing Diagrams
ENABLE vs CLOCK
TL F 5111 - 10
CLOCK vs DATA
TL F 5111 - 11
5
Timing Diagrams
(Continued) AM FM Frequency Synthesizer (Scan Mode)
TL F 5111 - 12
Timing diagrams are not drawn to scale Scale within any one drawing may not be consistent and intervals are defined positive as drawn
SERIAL DATA ENTRY INTO THE DS8908B Serial information entry into the DS8908B is enabled by a low level on the ENABLE input One binary bit is then accepted from the DATA input with each positive transition of the CLOCK input The CLOCK input must be low for the specified time preceding and following the negative transition of the ENABLE input The first two bits accepted following the negative transition of the ENABLE input are interpreted as address If these address bits are not 1 1 no further information will be accepted fromt he DATA inputs and the internal data latches will not be changed when ENABLE returns high If these first two bits are 1 1 then all succeeding bits are accepted as data and are shifted successively into the internal shift register as long as ENABLE remains low Any data bits preceding the 19th to last bit will be shifted out and thus are irrelevant Data bits are counted as any bits following two valid address bits (1 1) with the ENABLE low When the ENABLE input returns high any further serial data entry is inhibited Upon this positive transition the data in the internal shift register is transferred into the internal data latches Note that until this time the states of the internal data latches have remained unchanged
These data bits are interpreted as follows Data Bit Position Data Interpretation Last Bit 19 Output (Pin 2) 2nd to Last Bit 18 Output (Pin 1) 3rd to Last Ref Freq Select Bit(1)17 4th to Last Ref Freq Select Bit(1)16 5th to Last AM FM Select Bit 15 6th to Last (213) 7th to Last (212) 8th to Last (211) 9th to Last (210) 10th to Last (29) 11th to Last (28) 12th to Last (27) d N(2) 13th to Last (26) 5) 14th to Last (2 15th to Last (24) 16th to Last (23) 17th to Last (22) 18th to Last (21) 19th to Last LSB of d N(20)
Note 1 See Reference Frequency Select Truth Table
-
Note 2 The actual divide code is N a 1 ie the number loaded plus 1
Truth Table
Reference Frequency Selection Truth Table Serial Data Bit 16 1 1 0 0 Bit 17 1 0 1 0 Reference Frequency (kHz) 20 10 9 1
6
Typical Application Additional application notes are located at the back of section 11
Electronically Tuned Radio Controller System Direct Drive LED
TL F 5111 - 13
7
Logic Diagram
AM FM PLL Synthesizer (Serial Data 20-Pin Package)
8
Sections operating from VCCM supply Address (1 1)
TL F 5111 - 14
9
DS8908B AM FM Digital Phase-Locked Loop Frequency Synthesizer
Physical Dimensions inches (millimeters)
Molded Dual-In-Line Package (N) Order Number DS8908BN NS Package Number N20A
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2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness
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National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications
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