View 74LCX14SJ_1060349.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

74LCX14 Low Voltage Hex Inverter with 5V Tolerant Schmitt Trigger Inputs
March 1995 Revised February 2005
74LCX14 Low Voltage Hex Inverter with 5V Tolerant Schmitt Trigger Inputs
General Description
The LCX14 contains six inverter gates each with a Schmitt trigger input. They are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. In addition, they have a greater noise margin than conventional inverters. The LCX14 has hysteresis between the positive-going and negative-going input thresholds (typically 1.0V) which is determined internally by transistor ratios and is essentially insensitive to temperature and supply voltage variations. The inputs tolerate voltages up to 7V allowing the interface of 5V, 3V and 2.5V systems. The 74LCX14 is fabricated with advanced CMOS technology to achieve high speed operation while maintaining CMOS low power dissipation.
Features
s 5V tolerant inputs s 2.3V-3.6V VCC specifications provided s 6.5 ns tPD max (VCC
3.3V), 10 PA ICC max 3.0V)
s Power down high impedance inputs and outputs s r24 mA output drive (VCC s Implements patented noise/EMI reduction circuitry s Latch-up performance exceeds JEDEC 78 conditions s ESD performance:
Machine model ! 200V Human model ! 2000V
s Leadless Pb-Free DQFN package
Ordering Code:
Order Number 74LCX14M 74LCX14MX_NL (Note 2) 74LCX14SJ 74LCX14BQX (Note 1) 74LCX14MTC 74LCX14MTCX_NL (Note 2) Package Number M14A M14A M14D MLP014A MTC14 MTC14 Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Pb-Free 14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC MO-241, 2.5 x 3.0mm 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code. Pb-Free package per JEDEC J-STD-020B. Note 1: DQFN package available in Tape and Reel only. Note 2: "_NL" indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
(c) 2005 Fairchild Semiconductor Corporation
DS012412
www.fairchildsemi.com
74LCX14
Logic Symbol
IEEE/IEC
Connection Diagrams
Pin Assignments for SOIC, SOP, and TSSOP
Pin Descriptions
Pin Names In On Description Inputs Outputs
Pad Assignments for DQFN
Truth Table
Input A L H Output O H L
(Top View)
www.fairchildsemi.com
2
74LCX14
Absolute Maximum Ratings(Note 3)
Symbol VCC VI VO IIK IOK IO ICC IGND TSTG Parameter Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Source/Sink Current DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature Value Conditions Units V V Output in HIGH or LOW State (Note 4) VI GND VO GND VO ! VCC V mA mA mA mA mA
0.5 to 7.0 0.5 to 7.0 0.5 to VCC 0.5 50 50 50 r50 r100 r100 65 to 150
qC
Recommended Operating Conditions (Note 5)
Symbol VCC VI VO IOH/IOL Supply Voltage Input Voltage Output Voltage Output Current HIGH or LOW State VCC VCC VCC 3.0V 3.6V 2.7V 3.0V 2.3V 2.7V Parameter Operating Data Retention Min 2.0 1.5 0 0 Max 3.6 3.6 5.5 VCC Units V V V mA
r24 r12 r8
Note 3: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Note 4: IO Absolute Maximum Rating must be observed. Note 5: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol Vt Vt VH VOH Parameter Positive Input Threshold Negative Input Threshold Hysteresis HIGH Level Output Voltage IOH IOH IOH IOH VOL LOW Level Output Voltage IOL IOL IOL IOL II IOFF ICC Input Leakage Current Power-Off Leakage Current Quiescent Supply Current Increase in ICC per Input Conditions VCC (V) 2.5 3.0 2.5 3.0 2.5 3.0 TA
40qC to 85qC
Max 1.7 2.2 1.1 1.5 1.0 1.2
Min 0.9 1.2 0.4 0.6 0.3 0.4 VCC - 0.2 1.8 2.2 2.4 2.2
Units V V V
100PA 12 mA 18 mA 24 mA
100PA 12 mA 16 mA 24 mA 5.5V
2.3 3.6 2.3 2.7 3.0 3.0 2.3 3.6 2.3 2.7 3.0 3.0 2.3 3.6 0 2.3 3.6 2.3 3.6 2.3 3.6
IOH = -8 mA
V
0.2 0.6 0.4 0.4 0.55 V
IOL = 8mA
0 d VI d 5.5V VI or VO VI VIH VCC or GND VCC 0.6V
r5.0
10 10
PA PA PA PA
3.6V d VI d 5.5V
r10
500
'ICC
3
www.fairchildsemi.com
74LCX14
AC Electrical Characteristics
TA Symbol Parameter VCC 3.3V r 0.3V
40qC to 85qC, RL
VCC CL Min 1.5 1.5 2.7V 50 pF Max 7.5 7.5
500 : VCC CL Min 1.5 1.5 2.5V r 0.2V 30 pF Max 7.8 7.8 ns ns Units
CL 50 pF Min tPHL tPLH tOSHL tOSLH Output to Output Skew (Note 6) Propagation Delay Time 1.5 1.5 Max 6.5 6.5 1.0 1.0
Note 6: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
Dynamic Switching Characteristics
Symbol VOLP VOLV Parameter Quiet Output Dynamic Peak VOL Quiet Output Dynamic Valley VOL CL CL CL CL Conditions 50 pF, VIH 3.3V, VIL 30 pF, VIH 50 pF, VIH 2.5V, VIL 3.3V, VIL 0V 0V 0V 0V VCC (V) 3.3 2.5 3.3 2.5 TA 25qC Typical 0.8 0.6 Units V V
0.8 0.6
30 pF, VIH 2.5V, VIL
Capacitance
Symbol CIN COUT CPD Input Capacitance Output Capacitance Power Dissipation Capacitance Parameter VCC VCC VCC Open, VI 3.3V, VI 3.3V, VI Conditions 0V or VCC 0V or VCC 0V or VCC, f 10 MHz Typical 7 8 25 Units pF pF pF
www.fairchildsemi.com
4
74LCX14
AC Loading and Waveforms Generic for LCX Family
FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance) Test tPLH, tPHL tPZL, tPLZ tPZH,tPHZ Switch Open 6V at VCC 3.3 r 0.3V VCC x 2 at VCC 2.5 r 0.2V GND
Waveform for Inverting and Non-Inverting Functions
3-STATE Output Low Enable and Disable Times for Logic
Propagation Delay, Pulse Width and trec Waveforms
Setup Time, Hold TIme and Recovery TIme for Logic
3-STATE Output High Enable and Disable TImes for Logic
trise and tfall
FIGURE 2. Waveforms (Input Pulse Characteristics; f = 1MHz, tr = tf = 3ns) VCC Symbol Vmi Vmo Vx Vy 3.3V r 0.3V 1.5V 1.5V VOL 0.3V VOH 0.3V 2.7V 1.5V 1.5V VOL 0.3V VOH 0.3V 2.5V r 0.2V VCC/2 VCC/2 VOL 0.15V VOH 0.15V
5
www.fairchildsemi.com
74LCX14
Schematic Diagram Generic for LCX Family
www.fairchildsemi.com
6
74LCX14
Tape and Reel Specification
Tape Format for DQFN Package Designator BQX Tape Section Leader (Start End) Carrier Trailer (Hub End) TAPE DIMENSIONS inches (millimeters) Number Cavities 125 (typ) 2500/3000 75 (typ) Cavity Status Empty Filled Empty Cover Tape Status Sealed Sealed Sealed
REEL DIMENSIONS inches (millimeters)
Tape Size 12 mm
A 13.0 (330)
B 0.059 (1.50)
C 0.512 (13.00)
D 0.795 (20.20)
N 7.008 (178)
W1 0.488 (12.4)
W2 0.724 (18.4)
7
www.fairchildsemi.com
74LCX14
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M14A
www.fairchildsemi.com
8
74LCX14
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D
9
www.fairchildsemi.com
74LCX14
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC MO-241, 2.5 x 3.0mm Package Number MLP014A
www.fairchildsemi.com
10
74LCX14 Low Voltage Hex Inverter with 5V Tolerant Schmitt Trigger Inputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC14
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 11 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
www.fairchildsemi.com

▲Up To Search▲

Price & Availability of 74LCX14SJ

	To Download 74LCX14SJ Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .