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VECANA01
VECA NA01
www.ti.com
10-Channel, 12-Bit DATA ACQUISITION SYSTEM
FEATURES
q 10 FULLY DIFFERENTIAL INPUTS q 5 SIMULTANEOUS SAMPLED CHANNELS PLUS 2 SYNCHRONIZED SAMPLING CHANNELS q 3 SYNCHRONIZED 12-BIT ADCs q 12.8s THROUGHPUT RATE q DIGITALLY SELECTABLE INPUT RANGES q 5V POWER SUPPLIES q SERIAL DIGITAL INPUT/OUTPUTS q 7 SIGN AND 3 DIGITALLY PROGRAMMABLE WINDOW COMPARATOR
IUP/N 2 A1P/N 2 A2P/N 2 IVP/N 2 B1P/N 2 B2P/N MUX2 2 IWP/N 2 AN1P/N AN2P/N AN3P/N 2 2 MUX3 Input Select Gain Select ADIN SH3 PGA3 ADC3 12-Bit ADOUT3 SH2 PGA2 ADC2 12-Bit ADOUT2 MUX1 SH1 PGA1 ADC1 12-Bit ADOUT1 2
APPLICATIONS
q q q q AC MOTOR SPEED CONTROLS THREE PHASE POWER CONTROL UNINTERRUPTABLE POWER SUPPLIES VIBRATION ANALYSIS
DESCRIPTION
The VECANA01 consists of three 12-bit analog-todigital converters preceded by five simultaneously operating sample-hold amplifiers, and multiplexers for 10 differential inputs. The ADCs have simultaneous serial outputs for high speed data transfer and data processing. The VECANA01 also offers a programmable gain amplifier with programmable gains of 1.0V/V, 1.25V/V, 2.5V/V, and 5.0V/V. Channel selection and gain selection are selectable through the serial input control word. The high through put rate is maintained by simultaneously clocking in the 13-bit input control word for the next conversion while the present conversions are clocked out. The part also contains an 8-bit digital-to-analog converter whose digital input is supplied as part of the input control word.
2.5V Ref
Control Logic
Input Setup Register
DAC REFOUT
DAC 8-Bit
DAOUT ADCLK ADCONV ADBUSY
7 7
COMP
3
ILIM
DAIN
Copyright (c) 2000, Texas Instruments Incorporated
SBAS155
Printed in U.S.A. October, 2000
SPECIFICATIONS
At VANA+ = +5V, VANA- = -5V, VDIG+ = +5V, VDIG- = -5V, and TA = -40C to +85C, using internal reference, fCLOCK = 1.25MHz.
ANALOG-TO-DIGITAL CONVERTER CHANNELS
VECANA01N PARAMETER RESOLUTION ANALOG INPUT Full Scale Voltage, Differential CONDITIONS MIN 12 2.5 2.0 1.0 0.5 See Table VII 1012 20 10.4 12.8 78 0.1 0.5 50 50 3 0.5 0.5 12 0.5 0.5 G = 1.0V/V G G G G G = = = = = 1.0V/V 2.5V/V 1.0V/V 1.0V/V 1.0V/V 10 10 0.5 0.5 0.5 3 3 2 4 100 100 15 20 2 2 TYP MAX UNITS Bit
G = 1.0V/V G = 1.25V/V G = 2.5V/V G = 5.0V/V 0.5
Common-Mode Voltage Impedance Capacitance THROUGHPUT SPEED Conversion Time Complete Cycle Throughput Rate SAMPLING DYNAMICS S/H Droop Rate S/H Acquisition Time S/H Aperture Delay S/H Aperture Jitter Sampling Skew, Channel-to-Channel DC ACCURACY Integral Linearity - ADC Differential Linearity - ADC No Missing Codes Integral Linearity - Asynchronous, Synchronous Differential Linearity - Asynchronous, Synchronous Full Scale Error Full Scale Error Other Gains Full Scale Error Drift Zero Error - ADC Zero Error - Asynchronous, Synchronous Zero Error Drift AC ACCURACY Total Harmonic Distortion fIN = 1kHz fIN = 1MHz CMR REFERENCE Internal Reference Voltage Internal Reference Accuracy Internal Reference Drift Internal Reference Source Current External Reference Voltage Range for Specified Linearity External Reference Current Drain DIGITAL INPUTS Logic Levels VIL VIH IIL IIH Input Capacitance DIGITAL OUTPUTS Data Format Data Coding VOL VOH Leakage Current Output Capacitance CLK = 1.25MHz Acquire and Convert
V V V V V pF s s kHz V/s s ns ps ns LSB LSB Bits LSB LSB % of FSR % of FSR ppm/C ppm/C LSB LSB ppm/C
VCM = 0.5V, fCM = 1MHz
92 70 50 2.5 0.25 10 10 2.5 10
dB dB dB V % ppm/C A V A
2
2.25
2.75
0 +3.5
At All Digital Input Pins 12-Bit Serial BTC ISINK = 1.6mA ISOURCE = 500A At All Digital Output Pins 0 4.2
1.5 +5 10 10 15
V V A A pF
0.4 5 5 15
V V A pF
2
VECANA01
SBAS155
SPECIFICATIONS
(Cont.)
At VANA+ = +5V, VANA- = -5V, VDIG+ = +5V, VDIG- = -5V, and TA = -40C to +85C, using internal reference, fCLOCK = 1.25MHz.
ANALOG-TO-DIGITAL CONVERTER CHANNELS
VECANA01N PARAMETER POWER SUPPLIES VANA+ VANA- VDIG+ VDIG- IANA+ IANA- IDIG+ IDIG- Power Dissipation TEMPERATURE RANGE Specified Performance Derated Performance Storage CONDITIONS Specified Performance +4.75 -4.75 +4.75 -4.75 +5.0 -5.0 +5.0 -5.0 15 -8 12 -10 225 +5.25 -5.25 +5.25 -5.25 V V V V mA mA mA mA mW C C C MIN TYP MAX UNITS
-40 -55 -65
+85 +125 +150
DIGITAL-TO-ANALOG CONVERTER
VECANA01N PARAMETER RESOLUTION Output Range Output Settling Time Linearity Error Differential Linearity Output Current Offset Error Full Scale Error (including REF) CONDITIONS MIN 8-Bits 0 0.5LSB 0.2 TYP MAX +2.5 1 1 1 10 2 UNITS V s LSB LSB A mV %
200 1
SIGN AND WINDOW COMPARATORS
VECANA01 PARAMETER Differential Input Voltage Range of the Window Comparators Offset Error of the Window Comparators Hysteresis of the Window Comparators Offset Error of the Sign Current Comparators Hysteresis of the Sign Current Comparators Offset Error of the Sign Sensor Signal Comparators Hysteresis of the Sign Sensor Signal Comparators Absolute Input Range of the Comparators Delay Time of the Sign Comparators Delay Time of the Window Comparators 20 60 5 10 5 75 2.9 25 250 CONDITIONS MIN TYP MAX 2.5 80 100 20 30 30 90 3.2 150 1500 UNITS V mV mV mV mV mV mV V ns ns
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.
VECANA01
SBAS155
3
ABSOLUTE MAXIMUM RATINGS
Ground Voltage Difference: AGND and DGND ................................ 0.3V Power Supply Voltages: VANA+ ................................................................................................. +7V VANA- ................................................................................................. -7V VDIG+ ................................................................................................. +7V VDIG- ................................................................................................. -7V Digital Inputs .............................................................. -0.3V to VDIG +0.3V Maximum Junction Temperature ................................................... +165C Internal Power Dissipation ............................................................. 825mW Lead Temperature (soldering, 10s) .............................................. +300C
ELECTROSTATIC DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. BurrBrown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
CONVERSION AND DATA TIMING
SYMBOL tCONV CLK t1 t2 t3 t4 t5 DESCRIPTION A/D Conversion Time A/D Conversion Clock Setup Time for Conversion Before Rising Edge of Clock Hold Time for Conversion After Rising Edge of Clock Setup Time for Serial Out Setup Time for Serial Input Hold Time for Serial Input 30 30 MIN TYP MAX UNITS 10.4 1.25 50 50 125 6.2 2.1 s MHz ns ns ns ns ns
PACKAGE/ORDERING INFORMATION
PACKAGE DRAWING NUMBER 312 SPECIFIED TEMPERATURE RANGE -40C to +85C PACKAGE MARKING VECANA01 ORDERING NUMBER VECANA01 TRANSPORT MEDIA Rails
PRODUCT VECANA01
PACKAGE PLCC-68
PIN CONFIGURATION
REFGND REFOUT DAOUT REFIN AGND AN1N AN2N AN3N UN5V AN1P AN2P AN3P UP5V DAIN
IWN
IWP
9 NC 10 IVN 11 IVP 12 NC 13 B1N 14 B1P 15 NC 16 B2N 17 B2P 18 NC 19 NC 20 B_2 21 B_1 22 V_ILIM 23 V_COMP 24 W_ILIM 25 W_COMP 26
NC
8
7
6
5
4
3
2
1 68 67 66 65 64 63 62 61 60 NC 59 IUN 58 IUP 57 NC 56 A1N 55 A1P 54 NC 53 A2N
VECANA01
52 A2P 51 NC 50 NC 49 A_2 48 A_1 47 U_ILIM 46 U_COMP 45 NC 44 NC
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
TP1 TP2 UDP5V UDN5V ADOUT2 ADOUT3 ADOUT1 ADCLK ADCONV ADBUSY DATACLK DGND NC NPSH ADIN NC NC
4
VECANA01
SBAS155
PIN DEFINITIONS
PIN NO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 NAME AN3N AN3P AN2N AN2P AN1N AN1P NC IWN IWP NC IVN IVP NC B1N B1P NC B2N B2P NC NC B_2 TYPE(1) AI AI AI AI AI AI -- AI AI -- AI AI -- AI AI -- AI AI -- -- DO DESCRIPTION Auxiliary analog input channel 3, Negative Side Auxiliary analog input channel 3, Positive Side Auxiliary analog input channel 2, Negative Side Auxiliary analog input channel 2, Positive Side Auxiliary analog input channel 1, Negative Side Auxiliary analog input channel 1, Positive Side No Connection Analog input of phase W current, Negative Side Analog input of phase W current, Positive Side No Connection Analog input of phase V current, Negative Side Analog input of phase V current, Positive Side No Connection Signal B analog input of position sensor 1, Negative Side Signal B analog input of position sensor 1, Positive Side No Connection Signal B analog input of position sensor 2, Negative Side Signal B analog input of position sensor 2, Positive Side No Connection No Connection Sign of signal B position sensor 2 (B2P, B2N). If the value is positive (B2P > B2N) B_2 is 1, if the value is negative (B2P < B2N) B_2 is 0. Sign of signal B position sensor 1 (B1P, B1N). If the value is positive (B1P > B1N) B_1 is 1, if the value is negative (B1P < B1N) B_1 is 0. Over-current output of phase V, active low. If IVP-IVN is greater then the positive limiting value or less than the negative limiting value, U_ILIM becomes 0. Sign of phase V current signal (IVP, IVN). If the value is positive (IVP > IVN) V_COMP is 1, if the value is negative (IVP < IVN) V_COMP is 0. Over-current output of phase W, active low. If IWP-IWN is greater then the positive limiting value or less than the negative limiting value, U_ILIM becomes 0. Sign of phase W current signal (IWP, IWN). If the value is positive (IWP > IWN) W_COMP is 1, if the value is negative (IWP < IWN) W_COMP is 0. Test pin, do not connect to in normal operation. Test pin, do not connect to in normal operation. Digital Supply Voltage, +5V Digital Supply Voltage, Ground Digital Supply Voltage, -5V No Connection Serial output signal of A/D converter 2. Rising clock edges of ADCLK outputs the bits of the A/D converter with MSB first. Serial output signal of A/D converter 3. Rising clock edges of ADCLK outputs the bits of the A/D converter with MSB first. Serial output signal of A/D converter 1. Rising clock edges of ADCLK outputs the bits of the A/D converter with MSB first. 63 64 65 66 67 68 REFOUT REFIN REFGND UN5V AGND UP5V AO AI P P P P 48 A_1 DO 40 41 42 43 44 45 46 ADBUSY DATACLK NC NC NC NC U_COMP DO -- -- -- -- -- DO 39 ADIN DI 38 NPSH DI 37 ADCONV DI PIN NO 36 NAME ADCLK TYPE(1) DI DESCRIPTION Clock for the A/D converters. The nominal clock frequency is 1.25MHz. Start signal for the A/D converter, active low. The first rising clock edge of ADCLK, when ADCONV is 0, starts the conversion. Sample/hold control for sampling the position sensor signals. If the value is 1, the signals are sampled, if it is 0 they are stored. Serial input signal for programming the D/A converter for setting the limit value of the current signals for the input voltage range of the A/D converters and for the input multiplexer of the A/D converters. Conversion is executing, active low Test pin, do not connect to in normal operation. No Connection No Connection No Connection No Connection Sign of phase U current signal (IUP, IUN). If the value is positive (IUP > IUN) U_COMP is 1, if the value is negative (IUP < IUN) U_COMP is 0. Over-current output of phase U, active low. If IUP-IUN is greater then the positive limiting value or less than the negative limiting value, U_ILIM becomes 0. Sign of signal A position sensor 1 (A1P, A1N). If the value is positive (A1P > A1N) A_1 is 1, if the value is negative (A1P < A1N) A_1 is 0. Sign of signal A position sensor 2 (A2P, A2N). If the value is positive (A2P > A2N) A_2 is 1, if the value is negative (A2P < A2N) A_2 is 0. No Connection No Connection Signal A analog input of position sensor 2, Negative Side Signal A analog input of position sensor 2, Positive Side No Connection Signal A analog input of position sensor 1, Positive Side Signal A analog input of position sensor 1, Negative Side No Connection Analog input of phase U current, Positive Side Analog input of phase U current, Negative Side No Connection Input for setting the over-current value. Normally connected to DAOUT Output of the D/A converter for programming the over-current limit. Output is programmable from 0V to +2.5V. Output pin of the integrated reference source, nominal voltage 2.5V. Input pin for an external reference voltage. Ground pin of the reference source. Analog Supply Voltage, -5V Analog Supply Voltage, Ground Analog Supply Voltage, +5V
47
U_ILIM
DO
22
B_1
DO
49
A_2
DO
23
V_ILIM
DO
50 51 52 53 54 55 56 57 58 59 60 61 62
NC NC A2P A2N NC A1P A1N NC IUP IUN NC DAIN DAOUT
-- -- AI AI -- AI AI -- AI AI -- AI AO
24
V_COMP
DO
25
W_ILIM
DO
26
W_COMP
DO
27 28 29 30 31 32 33
TP1 TP2 UDP5V DGND UDN5V NC ADOUT2
-- -- P P P -- DO
34
ADOUT3
DO
35
ADOUT1
DO
NOTE: (1) AI is Analog Input, AO is Analog Output, DI is Digital Input, DO is Digital Output, P is Power Supply Connection.
VECANA01
SBAS155
5
TYPICAL PERFORMANCE CURVES
At VANA+ = +5V, VANA- = -5V, VDIG+ = +5V, VDIG- = -5V and TA = 25C, using internal reference, fCLOCK = 1.25MHz.
OFFSET vs TEMPERATURE 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.2 0 -55 -40 -25 0 25 70 85 125 Temperature (C) 0.1 0 -55 -40
Full Scale (%)
FULL SCALE vs TEMPERATURE 0.9 0.8 0.7
Offset (LSB)
0.6 0.5 0.4 0.3
-25
0
25
70
85
125
Temperature (C)
DIFFERENTIAL LINEARITY (MIN) vs TEMPERATURE 0.000 -0.100 -0.200 -0.300 -0.400 -0.500 -0.600 -0.700 -55 -40 -25 0 25 70 85 125 Temperature (C) 0.40 0.35 Differential Linearity (LSB) 0.30 0.25 0.20 0.15 0.10 0.05 0 -55
DIFFERENTIAL LINEARITY (MAX) vs TEMPERATURE
Differential Linearity (LSB)
-40
-25
0
25
70
85
125
Temperature (C)
INTEGRAL LINEARITY (MIN) vs TEMPERATURE 0.000 -0.050 0.45 0.40 Integral Linearity (LSB) 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 -55 -40 -25 0 25 70 85 125 -55
INTEGRAL LINEARITY (MAX) vs TEMPERATURE
Integral Linearity (LSB)
-0.100 -0.150 -0.200 -0.250 -0.300 -0.350 -0.400 -0.450 Temperature (C)
-40
-25
0
25
70
85
125
Temperature (C)
6
VECANA01
SBAS155
TYPICAL PERFORMANCE CURVES (Cont.)
At VANA+ = +5V, VANA- = -5V, VDIG+ = +5V, VDIG- = -5V and TA = 25C, using internal reference, fCLOCK = 1.25MHz.
DAC OFFSET vs TEMPERATURE 3.5 3.0
DAC FULL SCALE vs TEMPERATURE 0 -0.05 -0.10
DAC Full Scale (%)
DAC Offset (mV)
2.5 2.0 1.5 1.0 0.5 0 -55 -40 -25 0 25 70 85 125 Temperature (C)
-0.15 -0.20 -0.25 -0.30 -0.35 -0.40 -0.45 -55 -40 -25 0 25 70 85 125 Temperature (C)
VECANA01
SBAS155
7
FUNCTIONAL DESCRIPTION
The VECAN01 is a triple 12-bit SAR A/D converter that operates from dual 5V power supplies. The part contains three 12-bit successive approximation ADCs, multiplexer for 10 fully differential inputs, 5 differential input synchronized sample-and-hold amplifiers, plus two asynchronous
2 2 2 MUX1 2 SH2 2 SH1
sample-and-hold amplifier. It communicates over three synchronous SPI/SSI serial output and one input ports. The VECANA01 operates on external clock that also determines the output data rate (see Figure 2).
IUP/N A1P/N A2P/N
2 2 2 MUX6
2
PGA1
2
ADC1
ADOUT1
SH6 MUX2 NPSH IVP/N B1P/N B2P/N 2 2 2 MUX3
2
Ref Conv
2
SH3 2 2 2 MUX7
2
SH4
2
PGA2
2 ADC2
ADOUT2
SH7 MUX4 NPSH IWP/N AN1P/N AN2P/N AN3P/N 2 2 2 2 MUX5 Ref REFOUT REFIN 2.5V Ref 2
2
Ref Conv
AN1 Through AN3
SH5
2
PGA3
2 IW Only
ADC3
ADOUT3
Input Gain Select Select Decoder Conv 3 Sample 2 Input Setup Register DAC Input 8
Ref Conv
ADIN
Control Logic
DAC 8-Bit
DAOUT NPSH ADCLK ADCONV ADBUSY DATACLK
2 U_COMP 2 A_1 2 A_2 2 V_COMP 2 B_1 2 B_2
2 W_COMP
U_ILIM
V_ILIM
W_ILIM
DAIN
FIGURE 1. Functional Diagram. 8
VECANA01
SBAS155
MULTIPLEXERS The VECANA01 has several input multiplexers that are used to select the desired analog inputs and connect the proper sample-and-hold outputs to the PGAs and A/D converters. A decoder receives its inputs from the Input Setup Register and drives the MUXs (see Table VII and Table VIII for information on selecting the input channel). The input multiplexers can take full differential or single-ended signals (see Figure 4 and Table III). The analog signals stay differential through the sample holds and the PGAs all the way to the inputs of the A/D converter. This provides the best possible noise rejection. SAMPLE-AND-HOLD The VECANA01 contains seven sample-and-hold amplifiers. Five of them (SH1 through SH5) sample simultaneously and have their sample-and-hold timing internally synchronized (the timing is shown in Figure 2). Three of the sample-andholds (SH1, SH3, and SH5) are connected to the input multiplexers so that they can provide simultaneous sampling for all of their channel inputs. In addition, SH 2 and SH 4 simultaneously sample the third input of their channel (A2 and B2, respectively). This is useful in motor control applications where A1 and B1 are the quadrature inputs for one position sensor, and A2 and B2 are the quadrature inputs for a second position sensor (see Figure 9). In that application, it is desir-
able to sample the quadrature inputs of a given position sensor at the same time (even though they are converted on successive conversion cycles) (see Table VII), so that their values are captured at the same shaft position. The VECANA01 also has the capability for limited asynchronous sampling. The sampling of SH 6 and SH 7 is controlled asynchronously by the control signal NPSH (see Table VII). This allows two inputs, each on Channel 1 and Channel 2 (see Table VIII) to be sampled asynchronously from the timing of the other sample holds. This can be useful in motor control applications where the two inputs for each channel need to be sampled asynchronously to a reference point. ADCS AND PGAS The VECANA01 contains three signal channels each with a 12-bit A/D converter output. The A/D converters operate synchronously and their serial outputs occur simultaneously (Table IX gives the analog input/digital output relationships). Programmable gain amplifiers precede the A/D converters (Table IX gives gain select information). For channels one and two, the PGAs are effective for all three analog inputs. For the third channel, only the IW input is gain changed by the PGA. Inputs AN1, AN2, and AN3 are connected to the A/D converter three at a fixed gain of 1.0V/V regardless of the gain select value.
CLOCK AND CONTROL SIGNALS(1) Clock Pulse Reference No. ADCLK (Input)(2) DATACLK (Output)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
1
2
t1 t2 ADCONV (Input)
SAMPLE (Internal) ADBUSY (Output) A-to-D CONVERTER OUTPUTS ADOUT1 ADOUT2 ADOUT3 t4 t3 Bit 0 MSB Bit 0 MSB Bit 0 MSB t5 Bit 1 6 Bit 2 5 Bit 3 4 Bit 4 3 Bit 5 2 Bit 6 1 Bit 7 0 Bit 8 1 Bit 9 Bit 10 Bit 11 Bit 12 0 2 1 Input Select0-2 0 Bit 0 Bit 1 Bit 1 Bit 1 Bit 2 Bit 2 Bit 2 Bit 3 Bit 3 Bit 3 Bit 4 Bit 4 Bit 4 Bit 5 Bit 5 Bit 5 Bit 6 Bit 6 Bit 6 Bit 7 Bit 7 Bit 7 Bit 8 Bit 8 Bit 8 Bit 9 Bit 10 Bit 11 LSB Bit 9 Bit 10 Bit 11 LSB Bit 9 Bit 10 Bit 11 LSB tCONV tSAMPLE Bit 0 Bit 0 Bit 0
CONTROL WORD INPUT ADIN
Bit 0 7
How Used
DAC Input 0-7
Gain Select0-1
NOTE: (1) See the specification table for timing specifications. (2) 50% duty cycle.
FIGURE 2. Timing Diagram.
VECANA01
SBAS155
9
VOLTAGE REFERENCE The VECANA01 contains an internal 2.5V voltage reference. It is available externally through an output buffer amplifier. If it is desired to use an external reference, one may be connected at the REFIN pin. The output resistance of this pin for the external reference voltage is typically 7k. This then overrides the internal 2.5V reference and is connected to the A/D converter. It is also available as a buffered output at the REFOUT pin. The reference voltage shall be buffered by an external capacitor (approx. 2.2F) on the REFIN pin and also on the REFOUT pin (see Figure 3), as close as possible to the pin.
input. This allows the conversion to be synchronous with system timing so that transient noise effects can be minimized. The ADCLK signal may run continuously or may be supplied only during convert sequences. The ADBUSY and DATACLK signals are internally generated and are supplied to make interfaces with microprocessors easier (see Figures 2 and 9). POWER-UP INITIALIZATION When power is applied to the VECANA01, two conversion cycles are required for initialization before valid digital data is transmitted on the third cycle. The first conversion, after power is applied, is performed with indeterminate configuration values in the double buffer output of the Input Setup Register. The second conversion cycle loads the desired values into the register. The third conversion uses those values to perform proper conversions and output valid digital data from each of the A/D converters.
CLOCK POSITIONS(1) 2-9
Internal Connection
7k
2.5V Reference
REFOUT + 2.2F +
REFIN 2.2F
REFGND
DESCRIPTION DAC Input0-7 Gain Select0-1 Input Select0-2 Conditions
FUNCTIONS Sets DAC Output Voltage Sets PGA Gains Determines Multiplexers
10-11 12-14
FIGURE 3. Reference Voltage Connection. DIGITAL-TO-ANALOG CONVERTER An 8-bit DAC provides 256 output voltage levels from 0V to 2.499V (see Table I for input/output relationships). The DAC is controlled by the DAC Input portion of the input setup word. The DAC Input portion of the word is strobed into the DAC at the end of the conversion cycle (14th CLK pulse in Figure 2).
DIGITAL INPUT DAC INPUT0-7 HEX CODE 00H 01H
* * *
NOTE: (1) See Figure 2, "Clock Pulse Reference No."
TABLE II. Description of Configurable Parameters. CONFIGURABLE PARAMETERS Configurable parameters are: * PGA Gain * Input Multiplexer and Sample-and-Hold Selection * DAC Output Voltage Configuration information for these parameters is contained in the ADIN word (see Figure 2). As one conversion is taking place, the configuration for the next conversion is being loaded into the buffered Input Setup Register via the ADIN word. Tables I, VII, VIII and X shows information regarding these parameters.
ANALOG OUTPUT
BINARY CODE 0000 0000 0000 0001
* * *
0V +0.0098V
* * *
FFH
1111 1111
+2.499
TABLE I. DAC Input/Output Relationships. DAC OUTPUT VOLTAGE The value of the DAC output voltage is determined by the DAC Input portion of the ADIN word (bits 0 through 7, see Figure 2). The 8-bit DAC has 256 possible output steps from 0V to +2.499V. The value of 1LSB is 0.0098V. OTHER DIGITAL INPUTS AND OUTPUTS Sampling and conversion is controlled by the ADCONV and ADCLK input (see Figure 2). The VECANA01 is designed to operate from an external clock supplied at the ADCLK
ANALOG-TO-DIGITAL CONVERTERS
ARCHITECTURE The A/D converters are 12-bit, successive approximation types implemented with a switched capacitor circuitry. CLOCK RATE The clock for the A/D converter conversion is supplied externally at the ADCLK pin. Typical clock frequency for specified accuracy is 1.25MHz. This results in a complete conversion cycle (S/H acquisition and A/D conversion) of 10.4s.
10
VECANA01
SBAS155
INPUT/OUTPUT The VECANA01 is designed for bipolar input voltages and uses a binary two's complement digital output code. A programmable gain function is associated with each A/D converter. This changes the full-scale analog input range and the analog resolution of the converter. Details are shown in Table IX. DIFFERENTIAL AND COMMON-MODE INPUT VOLTAGES The VECANA01 is designed with full differential signal paths all the way from the multiplexer inputs through to the input of the A/D converters. This was done to provide superior high frequency noise rejection. As is common with most differential input semiconductor devices, there are compound restrictions on the combination of differential and common-mode input voltages. This matter is made slightly more complicated by the fact that most of the analog inputs are capable of being affected by the programmable gain function. The possible differential and single-ended configurations are shown in Figures 4a and 4b. The maximum differential and common-mode restrictions are shown in Table III.
GAIN SELECT CODE Gain Full Scale Range (VD with VCM = 0) Largest Positive Common Mode Voltage, VCM+ Largest Negative Common Mode Voltage, VCM- 0 5.0V/V 0.5V 1 2.5V/V 1.0V 2 1.25V/V 2.0V 3 1.0V/V 2.5V
INPUT SETUP As the A/D converters are converting and transmitting their serial digital data for one conversion cycle, a setup word is received to be used for the next conversion cycle. The 13-bit word is supplied at the ADIN pin (see Figure 1), and is stored in the buffered Input Setup Register. The Input Select and Gain Select portions of the word are decoded and determine the state of the multiplexers and PGAs (see CONFIGURABLE PARAMETERS section). INPUT MULTIPLEXER AND SAMPLE HOLD SELECTION The Input Select portion of the ADIN word (bits 10, 11 and 12) (see Figure 2) are decoded and determine the open/ closed condition of the multiplexer switches. This in turn determines which input signals are connected to the sample and holds and which sample and holds are connected to the PGAs/ADCs. SIGN OF THE INPUT SIGNALS The VECANA01 contains seven comparators, which acquire the signals of the first seven input analog signals. The digital outputs of the sign comparators are the signals X_COMP. If the positive input value is greater than the negative input value, the X-COMP output becomes High (logic "1") or if the reverse, the X-COMP output is Low (logic "0"), (see Table IV).
IUP - IUN U_COMP A_1 A_2 V_COMP B_1 B_2 W_COMP 1 0
+2.7V
+2.4V
+1.9V
+1.6V
A1P - A1N A2P - A2P IVP - IVN B1P - B1N B2P - B2N IWP - IWN >0 <0
-2.7V
-2.4V
-1.9V
-1.6V
TABLE III. Differential and Common Mode Voltage Restrictions.
(A) IUP + VD 2 - + VD 2 - IUN VCM + -
IUP VD 2 IUN VCM
TABLE IV. Input - Output Relation. The typical hysteresis value of comparators U_COMP, V_COMP and W_COMP is 10mV. The typical hysteresis value of comparators A_1, A_2, B_1, and B_2 is 50mV. AC motor control applications will typically use 10mV hysteresis for phase current measurement and 50mV hysteresis for positioning sensor measurement. OVER RANGE RECOGNITION The VECANA01 also includes three window comparators for the three input signals IU, IV and IW. Each window comparator is composed of two comparators that are monitoring the input value on the positive range limit (UPLIM) and negative range limit (UNLIM). The output values of the window comparators are output via the pins U_ILIM, V_ILIM and W_ILIM. The two range limiting values are symmetrical to the zero point (UNLIM = -UPLIM) and are determined by pin
VD 2
VCM
(B) IUP + VD - IUN + VCM -
IU VD VCM
FIGURE 4. (a) Differential Signal Source. (b) Single-ended Input.
VECANA01
SBAS155
11
DAIN. See Figure 5 for graphical view of the over limit set function (typically used for setting the current protection value), The DAIN value will determine the fixed range. Normally this pin is connected to DAOUT (the DAC output). In order to be able to program the range value through the control value DAC Input word, the DAC Input is an 8-bit wide unsigned value (controls the digital-to-analog converter output voltage (DAOUT)). This D/A converter has an output voltage range of 0V to 2.5V (see Table I).
DAC INPUT 0H 1H 2H 0FEH 0FFH UPLIM 0V +0.0098V +0.0195V +2.4805V +2.4902V UNLIM 0V -0.0098V -0.0195V -2.4805V -2.4902V
= Hysteresis IUP - IUN UPLIM
UNLIM
U_COMP
U_ILIM
TABLE V. Over-Current Limit as a Function DAC Input. If the input voltage exceeds the positive range limit (IXP - IXN > UPLIM) or it remains under the negative range (IXP - IXN < UNLIM), then the corresponding window comparator output is Low (logic "0") (U_ILIM, V_ILIM, or W_ILIM). If the input value is within the limits, the comparator output is High (logic "1"). The input signal and output X_ILIM signals are shown in Table VI.
IUP - IUN IVP - IVN IWP - IWN (IXP - IXN) > UPLIM UPLIM > (IXP - IXN) > UNLIM UNLIM > (IXP - IXN) U_ILIM V_ILIM W_ILIM 0 1 0
FIGURE 5. Acquisition of the Current Sign and of the OverCurrent.
INPUT SELECT0-2 HEX CODE 0H 1H 2H 3H 4H 5H 6H 7H BINARY CODE 000 001 010 011 100 101 110 111 ANALOG SIGNAL CONNECTED TO PGAX/ADCX PGA1 /ADC1 Undefined A_X via SH6(1) A_2 via SH1 A_2 via SH2 A1 A1 A1 IU PGA2 /ADC2 Undefined B_X via SH7(1) B_2 via SH3 B_2 via SH4 B1 B1 B1 IV PGA3 /ADC2 AN3 AN3 AN2 AN2 AN1 AN1 AN1 IW
NOTE: (1) See Table VIII for Operation.
TABLE VII. Input Controls for Synchronous Sample Holds. Input Select = 4H, 5H, 6H--Synchronously sample and convert input signals A1, B1, and AN1. These codes also cause SH2 and SH4 to sample their inputs. Values 4H, 5H, 6H have different effects on the inputs to SH6 and SH7 (see Table VIII).
INPUT SELECT0-2 HEX CODE 0H 1H 2H 3H 4H 5H 6H 7H BINARY CODE 000 001 010 011 100 101 110 111 ANALOG SIGNAL CONNECTED TO SH6 No Effect No Effect No Effect No Effect Open A1 A2 No Effect SH7 No Effect No Effect No Effect No Effect Open B1 B2 No Effect
TABLE VI. The Limiting Value as Function of DAC Input. The input voltage range of the comparators is the same as the A/D converter when the Gain Select is 3. The typical value of the hysteresis of the comparators is 50mV. Figure 5 shows the Logic State of the U_COMP and U_ILIM outputs for the input signal IVP - IUN. The output resistance of the D/A converter is approximately 10k. The output voltage, DAOUT should be buffered by a capacitor of approximately 100nF (see Figure 6) The resulting time constant is approximately 1ms and typical does not disturb most applications. INPUT SIGNALS FOR PGAS/ADCS Table VII shows the relationships between the value of Input Select0-2 and the signals that are converted. Input Select = 7H--Synchronously sample and convert input signals IU, IV, and IW.
TABLE VIII. Input Controls for Asynchronous Sample Holds. Input Select = 3H--Convert A2 via SH2, B2 via SH4, and AN2 (A2 and B2 are from the value sampled in a preceding conversion cycle with Input Select = 4H, 5H or 6H). Input Select = 2H --Convert A2 via SH1, B2 via SH3, and AN2.
12
VECANA01
SBAS155
+5V
GND
-5V
GND
4.7F
4.7F
2.2F
100nF
100nF
2.2F 100nF
REFGND
REFOUT
DAOUT
REFIN
AGND
AN1N
AN2N
AN3N
UN5V
AN1P
AN2P
AN3P
UP5V
9 NC 10 IVN 11 IVP 12 NC 13 B1N 14 B1P 15 NC 16 B2N 17 B2P 18 NC 19 NC 20 B_2 21 B_1 22 V_ILIM 23 V_COMP 24 W_ILIM 25 W_COMP 26
8
7
6
5
4
3
2
1
68 67 66 65 64 63 62 61 60 NC 59 IUN 58 IUP 57 NC 56 A1N 55 A1P 54 NC 53 A2N IN- IN+
DAIN
52 A2P 51 NC 50 NC 49 A_2 48 A_1 47 U_ILIM 46 U_COMP 45 NC 44 NC
IWN
IWP
NC
VECANA01
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
TP1
TP2
UDP5V
DGND
UDN5V
NC
ADOUT2
ADOUT3
ADOUT1
ADCLK
ADCONV
NPSH
ADIN
ADBUSY
DATACLK
NC
4.7F
4.7F + 100nF Ground Plane
100nF
+5V
GND
-5V
FIGURE 6. Basic Circuit Configuration.
VECANA01
SBAS155
NC
13
DESCRIPTION GAIN SELECT CODE GAIN FULL SCALE RANGE +Full Scale (FS -1LSB) One Bit above Mid-Scale Mid-Scale One Bit Below Mid-Scale -Full Scale 0 5V/V 0.5V +0.49976 +0.244mV 0V -0.244V -0.500V 1
ANALOG INPUT 2 1.25V/V 2.0V +1.999V +0.976mV 0V -0.976mV -2.000V 3 1.0V/V 2.5V +2.499 +1.22mV 0V -1.22mV -2.500V
DIGITAL OUTPUT
2.5V/V 1.0V +0.9995V +0.488mV 0V -0.488mV -1.000V
BINARY TWO'S COMPLIMENT FORMAT HEX CODE 7FFH 001H 000H FFFH 800H BINARY CODE 0111 0000 0000 1111 1000 1111 0000 0000 1111 0000 1111 0001 0000 1111 0000
NOTE: The programmable gain function applies to all three input channels for ADC1 and ADC 2. However, the programmable gain function only applies to the first input (IW) for ADC3. The other three inputs (AN1, AN2, and AN3) are not affected by the GAIN SEL input. They operate at a fixed gain of 1V/V and thus have a fixed 2.5V full scale input range.
TABLE IX. Analog Input - Digital Output Relationships. Input Select = 1H--Input AN3 is converted by ADC3. The output of the asynchronous sample holds, SH6 and SH7, are converted by PGA1/ADC1 and PGA2/ADC2, respectively. Note that the inputs to SH6 and SH7 are determined by previous Input Select values (see Table VIII). Thus, to properly convert the output of one of the asynchronous sample holds it is first necessary to choose its input with a previous conversion cycle. Also, the output of SH6 or SH7 will only be converted if NPSH goes low before the ADCONV command is received. Input Select = 0 H--AN3 is converted by ADC3. The inputs to PGA1/ADC1 and PGA2/ADC2 are undefined. PGA GAIN The PGA gain is determined by the Gain Select portion (bits 8 and 9) in the ADIN word (see Figure 2). There is one gain input that sets the same gain for all three PGAs. The gain values and allowable full-scale inputs are shown in Table X.
GAIN SELECT0-1 0H 1H 2H 3H GAIN SETTING 5.0V/V 2.5V/V 1.25V/V 1.0V/V FULL SCALE INPUT 0.5V 1.0V 2.0V 2.5V
being 4, 5, or 6. The "No Effect" states indicate that these values of Input Select have no effect on the multiplexers at the input of SH6 and SH7. When one of the "No Effect" values of Input Select is presented, the multiplexers will not be changed (i.e., their condition is determined by the last 4, 5, or 6 value of Input Select that existed prior to the "No Effect" state). Note that Input Select = 1H presents the output of SH6 and SH7 to PGA1/ADCl and PGA2/ADC2, respectively (see Table VII). Therefore, in order to properly convert the asynchronous sampled signals, it is first necessary to choose an input signal (Input Select equal 5 or 6 in Table VIII) with one load/convert cycle and then convert the sample hold output (Input Select = 4 in Table VII) in a following conversion cycle. POWER SUPPLY The VECANA01 requires an analog and digital supply voltage of 5V. The substrate is connected to UP5V. The voltage difference between the analog and digital supply pin is not allowed to exceed a maximal value of 300mV. For this reason the circuit shown in Figure 7 is recommended for the power supply. The analog and digital power supplies are driven by a common source. Intermediate resistors provide for decoupling. Local current-limited voltage regulators generate the 5V from the analog supply voltages UB. This guarantees a further noise reduction. The diodes are responsible for protecting the regulation and prevent polarity inversion. The zener diode protects against over-voltage possible from over-voltages to the analog inputs. Typical values for the resistors and capacitors are: * RA 3 * RD 3 * CD 22F * CA 22F * CB 100nF * CR 2.2F
TABLE X. Gain Select Information. For channels one and two the PGAs set the gain for all three analog inputs. For the third channel, only the IW input is gain changed by the PGA. Inputs AN1, AN2, and AN3 are connected to A/D converter three at a fixed gain of 1.0V/V regardless of the Gain Select value. CONVERSIONS FROM THE ASYNCHRONOUS SAMPLE HOLDS Decoding the Input Select value also determines which inputs are applied to the two asynchronously controlled sample holds (SH6 and SH7) (see Table VIII.) One of the three possible inputs is selected by the Input Select value
14
VECANA01
SBAS155
CR CR RA +5V +UB IN OUT + 5.6V + -UB IN OUT 5.6V -5V RA Voltage Regulator, Current Limited Ground Plane CA CA RD + + CD CD CB CB + + CA CA CB CB
VECANA01 REFIN
REFOUT UP5V UDP5V AGND DGND
RD
REFGND UDN5V UN5V
FIGURE 7. Power Supply of VECANA01.
CONNECTION BETWEEN VECANA01 AND DSP The interface between the VECANA01 and dSMC101 comprises the control signals for the A/D converters (ADCLK, ADCONV, ADIN, ADOUT1-3, NPSH, ADBUSY and DATACLK) and the comparator signals (X_COMP and X_ILIM). The signal levels and the driver capacity of the two chips are compatible. In order to avoid noise injection of the digital power supply into the analog VECANA01 chip, it is recommended to damp all digital lines with an intermediate resistor of approximately 100 as near as possible to the analog chip.
SICAN dSMC101 INTERFACE The internal logic of the VECANA01 is designed for easy control and data interface with DSPs. Figure 9 shows the interface for loading the input control word from the DSP data bus into the serial input of the VECANA01.
IUP/N PhaseCurrents IVP/N IWP/N
U/V/W_COMP U/V/W_ILIM A_1, B_1
Encoder1
A1P/N B1P/N A2P/N
A_2, B_2 ADCLK VECANA01 ADCONV ADOUT1-3 ADIN NPSH Sican dSMC101
Encoder2
B2P/N
VECANA01
100
Motor Control DSP
AN1P/N Auxillary AN2P/N Inputs AN3P/N
FIGURE 8. Damping of All Digital Lines.
FIGURE 9. DSP Interface for Sican dSMC101.
VECANA01
SBAS155
15
IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 2000, Texas Instruments Incorporated

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