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V350EPC Rev. A0 / A1
LOCAL BUS TO PCI BRIDGE FOR MULTIPLEXED A/D PROCESSORS
* Glueless interface to Intel's i960Jx and IBM's PowerPC TM 401Gx processors * Configurable for primary master, bus master or target operation. * Type 0 and type 1 configuration cycles. * Up to 1Kbyte burst access on PCI or local. * Large, 640-byte FIFOs using V3's unique DYNAMIC BANDWIDTH ALLOCATIONTM architecture * 64-byte read FIFO per aperture. * Enhanced support for 8/16-bit local bus devices with programmable region sizes. * 3.3 volt support * Dual bi-directional address space remapping * Fully compliant with PCI 2.1 specification V350EPC is a high-performance and low-cost generic solution for interfacing both 32-bit and 16-bit multiplexed local bus applications to the PCI bus. V350EPC directly connects to i960Jx or i960Sx proces sors with out a ny glue logic . Mi ni ma l g lue lo gi c i s re qu ire d fo r hi gh performance interfacing to other multiplexed processors like Motorola ColdFireTM. V350EPC is the second generation of V3's I2O ready PCI bridges - fully backward compatible with both V961PBC and V960PBC Rev B2 devices - and is supporting powerful features like Hot Swap and DMA chaining. The PCI bus can be run at the full 33MHz frequency, independent of local bus clock rate. The overall throughput of the syste m is dramati ca lly improved by increasing the FIFO depths and utilizing the u ni q u e D Y N A M I C B A N D W I D T H A L L O C AT I O N TM
* On-the-fly byte order (endian) conversion * I2O ATU and messaging unit including hardware controlled circular queues * 2 channel DMA controller plus multiprocessor DMA chaining and demand mode DMA * Hot swapping capability * 16 8-bit bi-directional mailbox registers with doorbell interrupts * Flexible PCI and local interrupt management * Optional power-on serial EEPROM initialization * 33MHz and 40MHz local bus versions * Industrials temperature grade -40 to +85'C * Low cost 160-pin EIAJ PQFP package
architecture. Access to the PCI bus can be performed through two programmable address apertures. Two more apertures are provided for PCI-to-local bus accesses. There are 64-bytes of read FIFOs in each direction, 32-byte dedicated for each aperture . Two high-performance DMA channels with chaining and demand mode capabilities provide a powerful data transfer engine for bulk data transfers. Mailbox registers and flexible PCI interrupt controllers are also included to provide a simple mechanism to emulate PCI device control ports. The part is available in 160-pin low cost PQFP packages in 33MHz and 40MHz versions.
i960Jx CPU
V96BMC MEMORY CONTROL
D R A M
ROM
TYPICAL APPLICATION
V350EPC
LOCAL TO PCI BRIDGE
PCI SLOT or EDGE CONNECTOR PCI PERIPHERAL
Copyright (c) 1998, V3 Semiconductor Corp.
V350EPC Data Sheet Rev 1.1
1
V3 Semiconductor reserves the right to change the specifications of this product without notice. V350EPC and V96BMC are trademarks of V3 Semiconductor. All other trademarks are the property of their respective owners.
V350EPC
This document contains the product codes, pinouts, package mechanical information, DC characteristics, and AC characteristics for the V350EPC. Detailed functional information is contained in the User's Manual. V3 Semiconductor retains the rights to change documentation, specifications, or device functionality at any time without notice. Please verify that you have the latest copy of all documents before finalizing a design.
1.0 Product Codes
Table 1: Product Codes
Product Code V350EPC-33 REV A0 / A1 V350EPC-40 REV A0 / A1 Processors i960Jx/Sx Bus Type 32/16-bit multiplexed Package 160-pin EIAJ PQFP Frequency 33MHz
i960Jx/Sx
32/16-bit multiplexed
160-pin EIAJ PQFP
40MHz
2.0 Pin Description and Pinout
Table 2 below lists the pin types found on the V350EPC. Table 3 describes the function of each pin on the V350EPC. Table 5 lists the pins by pin number. Figure 1 shows the pinout for the 160-pin EIAJ PQFP package and Figure 2 shows the mechanical dimensions of the package.
Table 2: Pin Types
Pin Type PCI I PCI O PCI I/O PCI I/OD I/O4 I O4 PCI input only pin. PCI output only pin. PCI tri-state I/O pin. PCI input with open drain output. TTL I/O pin with 4mA output drive. TTL input only pin. TTL output pin with 4mA output drive. Description
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V350EPC Data Sheet Rev 1.1
Copyright (c) 1998, V3 Semiconductor Inc.
V350EPC
Table 3: Signal Descriptions
PCI Bus Interface Signal AD[31:0] C/BE[3:0] PAR FRAME Type PCI I/O PCI I/O PCI I/O PCI I/O Ra Z Z Z Z Description Address and data, multiplexed on the same pins. Bus Command and Byte Enables, multiplexed on the same pins. Parity represents even parity across AD[31:0] and C/BE[3:0]. Cycle Frame indicates the beginning and burst length of an access. Initiator Ready indicates the initiating agent's (bus master's) ability to complete the current data phase of the transaction. Target Ready indicates the target agent's (selected device's) ability to complete the current data phase of the transaction. Stop indicates the current target is requesting the master to stop the current transaction (retry or disconnect). Device Select, when actively driven by a target, indicates the driving device has decoded its address as the target of the current access. As an input to the initiator, DEVSEL indicates whether any device on the bus has been selected. Initialization Device Select is used as a chip select during configuration read and write transactions. It must be driven high in order to access the chip's internal configuration space. Z Request indicates to the arbiter that this agent requests use of the bus. Grant indicates to the agent that access to the bus has been granted. PCLK provides timing for all transactions on the PCI bus. Acts as an input when RDIR is high, an output when RDIR is low. As an input it is asserted low to bring all internal EPC operation to a reset state. Parity Error is used to report data parity errors during all PCI transactions except a Special Cycle. System Error is used to report address parity errors, data parity errors on the Special Cycle command, or any other system error where the result will be catastrophic. Level-sensitive interrupt requests may be received or generated.
IRDY
PCI I/O
Z
TRDY
PCI I/O
Z
STOP
PCI I/O
Z
DEVSEL
PCI I/O
Z
IDSEL
PCI I
REQ
PCI O
GNT PCLK
PCI I PCI I
PRST
PCI I/O
Z/L
PERR
PCI I/O
Z
SERR
PCI I/OD
Z
INT[A:D]
PCI I/OD
Z
Copyright (c) 1998, V3 Semiconductor Corp.
V350EPC Data Sheet Rev 1.1
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V350EPC
Table 3: Signal Descriptions (cont'd)
Local Bus Interface Signal LAD[31:0] LAD[15:0]b LA[31:16]b LA[5:2] ALE BE[3:0] BE[1:0]b W/R ADS ASb RDYRCV READYb HOLD HOLDA LPAR[3:0] LPAR[1:0]b BLAST BTERMc LINT LRST LCLK Type I/O4 I/O4 O4 I/O4 Z R Z Z Description Local multiplexed address and data bus. Local address bus. Lower local address bus (non-multiplexed version). Address Latch Enable: used to latch the address during the address phase. Local bus byte enables. Write/Read. Asserted low to indicate the beginning of a bus cycle.
I/O4 I/O4 I/O4
Z Z Z
I/O4
Z
Local Bus data ready Local bus hold request: asserted by the chip to initiate a local bus master cycle. Local bus hold acknowledge.
O4 I I/O4 I/O4 I/O4 O4 I/O4 I
L
Z Z Z H L/Z
Local bus parity. Burst last. Bus Time-out. Burst terminate. Local interrupt request. Local bus RESET signal. Local bus clock.
Serial EEPROM Interface Signal SCL/LPERR SDA Type O4 I/O4 R X X Description EEPROM clock. Local parity error. EEPROM data.
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V350EPC Data Sheet Rev 1.1
Copyright (c) 1998, V3 Semiconductor Inc.
V350EPC
Table 3: Signal Descriptions (cont'd)
Configuration Signal RDIR Type I R Description Reset direction. Tie low to drive PRST out and LRST in, high to drive LRST out and PRST in. Selects 5V (EN5V driven low) or 3.3V (EN5V driven high) device operation modes. Power and Ground Signals Signal V CC GND Type R Description POWER leads intended for external connection to a VCC board plane. GROUND leads intended for external connection to a GND board plane.
EN5V
I
-
a. R indicates state during reset. b. Applies to i960Sx mode. c. Applies to i960Jx mode.
2.1
Test Mode Pins
Several device pins are used during manufacturing test to put the V350EPC device into various test modes. These pins must be maintained at proper levels during reset to insure proper operation. This is typically handled through pull-up or pull-down resistors (typically 1K to 10K) on the signal pins if they are not guaranteed to be at the proper level during reset. Table 4 below shows the reset states for test mode pins:
Table 4: RESET State for Test Mode Pins
Mode i960Jx i960Sx Pin 134 Pull-Down Pull-Down Pin 135 Pull-Up Pull-Down Pin 153 Pull-Down Pull-Down
Copyright (c) 1998, V3 Semiconductor Corp.
V350EPC Data Sheet Rev 1.1
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V350EPC
Table 5: Pin Assignments
PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Signal VCC INTD PRST PCLK GNT REQ AD31 AD30 AD29 AD28 GND AD27 AD26 AD25 AD24 PIN # 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 Signal VCC AD14 AD13 AD12 AD11 AD10 AD9 AD8 C/BE0 VCC GND AD7 AD6 AD5 AD4 PIN # 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 Signal VCC NC LAD8 NC LAD9 NC LAD10 NC LAD11 NC LAD12 NC LAD13 NC LAD14 PIN # 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 Signal VCC NC LA(Da)25 LA5 LA(Da)26 LA4 LA(Da)27 LA3 LA(Da)28 LA2 LA(Da)29 LA(Da)30 LA(Da)31 ALE '0' BTERMa READY RDYRCVa HOLD HOLDA AS ADSa VCC GND LCLK EN5V VCC
16 17 18 19 20 21 22 23 24
C/BE3 IDSEL AD23 AD22 VCC GND AD21 AD20 AD19
56 57 58 59 60 61 62 63 64
AD3 AD2 AD1 AD0 VCC GND LAD0 NC LAD1
96 97 98 99 100 101 102 103 104
NC LAD15 NC LA(Da)16 VCC GND NC LA(D )17 NC
a
136 137 138 139 140 141 142 143 144
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V350EPC Data Sheet Rev 1.1
Copyright (c) 1998, V3 Semiconductor Inc.
V350EPC
Table 5: Pin Assignments (cont'd)
PIN # 25 Signal AD18 PIN # 65 Signal NC PIN # 105 Signal LA(Da)18 PIN # 145 Signal LA1b BE3a NC BE2a BE1 BE0 BLAST W/R RDIR LRST '0' LINT SDA SCL/LPERR INTA
26 27 28 29 30 31 32 33 34 35 36 37
AD17 AD16 C/BE2 FRAME GND IRDY TRDY DEVSEL STOP PERR SERR PAR
66 67 68 69 70 71 72 73 74 75 76 77
LAD2 NC LAD3 NC LAD4 NC LAD5 NC LAD6 NC LAD7 NC
106 107 108 109 110 111 112 113 114 115 116 117
NC LA(Da)19 NC LA(Da)20 NC LA(Da)21 NC LA(Da)22 NC LA(Da)23 NC NC LPAR2a NC LPAR3a LA(Da)24 GND
146 147 148 149 150 151 152 153 154 155 156 157
38 39 40
C/BE1 AD15 GND
78 79 80
LPAR0 LPAR1 GND
118 119 120
158 159 160
INTB INTC GND
a. Applies to i960Jx mode. b )Applies to i960Sx mode
Copyright (c) 1998, V3 Semiconductor Corp.
V350EPC Data Sheet Rev 1.1
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V350EPC
Figure 1: Pinout for 160-pin EIAJ PQFP (top view)
GND LA(D)24 NC(LPAR3) NC(LPAR2) NC LA(D)23 NC LA(D)22 NC LA(D)21 NC LA(D)20 NC LA(D)19 NC LA(D)18 NC LA(D)17 NC GND Vcc LA(D)16 NC LAD15 NC LAD14 NC LAD13 NC LAD12 NC LAD11 NC LAD10 NC LAD9 NC LAD8 NC Vcc Vcc NC LA(D)25 LA5 LA(D)26 LA4 LA(D)27 LA3 LA(D)28 LA2 LA(D)29 LA(D)30 LA(D)31 ALE '0'(BTERM#)
DY#(RDYRCV#)
120 121
81 80
HOLD HOLDA AS#(ADS#) Vcc GND LCLK EN5V# Vcc LA1(BE3#) NC(BE2#) BE1# BE0# BLAST# W/R# RDIR LRST# '0' LINT# SDA SCL/LPERR# INTA# INTB# INTC# GND
V350EPC
160 1 41 40
GND LPAR1 LPAR0 NC LAD7 NC LAD6 NC LAD5 NC LAD4 NC LAD3 NC LAD2 NC LAD1 NC LAD0 GND Vcc AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 GND Vcc C/BE0# AD8 AD9 AD10 AD11 AD12 AD13 AD14 Vcc
8
Vcc INTD# PRST# PCLK GNT# REQ# AD31 AD30 AD29 AD28 GND AD27 AD26 AD25 AD24 C/BE3# IDSEL AD23 AD22 Vcc GND AD21 AD20 AD19 AD18 AD17 AD16 C/BE2# FRAME# GND IRDY# TRDY# DEVSEL# STOP# PERR# SERR# PAR C/BE1# AD15 GND
V350EPC Data Sheet Rev 1.1 Copyright (c) 1998, V3 Semiconductor Inc.
V350EPC
Figure 2: 160-pin EIAJ PQFP mechanical details
Unit of Measurement = millimeters
Copyright (c) 1998, V3 Semiconductor Corp.
V350EPC Data Sheet Rev 1.1
9
V350EPC 3.0 DC Specifications
The DC specifications for the PCI bus signals match exactly those given in the PCI Specification, Rev. 2.1, Section 4.2.1.1. For more information on the PCI DC specifications, see the PCI Specification.
Table 6: Absolute Maximum Ratings
Symbol VCC VIN IIN Tj TSTG Parameter Supply voltage DC input voltage DC input current Junction temperature Storage temperature range Value -0.3 to +7 -0.3 to VCC+0.3 10 125 -40 to +125 Units V V mA C C
Table 7: Guaranteed Operating Conditions
Symbol VCC VCC Parameter Supply voltage 5 volt Supply voltage 3.3 volt Value 4.50 to 5.50 3.0 to 3.60 50 -40 to 85 Units V V C/w C
Theta Ja Thermal resistance TA Ambient temperature range
3.1
PCI Bus DC Specifications Table 8: PCI Bus Signals DC Operating Specifications
Symbol VIH VIL IIH IIL VOH VOL CIN
Parameter Input high voltage Input low voltage Input high leakage current Input low leakage current Output high voltage Output low voltage Input pin capacitance
Condition
Min 2.0 -0.5
Max VCC+0.5 0.8 70 -70
Units V V A A V
Notes
VIN = 2.7V VIN = 0.5V IOUT = -2mA IOUT = 3mA, 6mA 2.4
1 1
0.55 10
V pF
2 3
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V350EPC Data Sheet Rev 1.1
Copyright (c) 1998, V3 Semiconductor Inc.
V350EPC
Table 8: PCI Bus Signals DC Operating Specifications
Symbol CCLK C IDSEL LPIN Parameter PCLK pin capacitance IDSEL pin capacitance Pin inductance Condition Min 5 Max 12 8 20 Units pF pF nH 4 Notes
Notes: 1. Input leakage currents include high impedance output leakage for all bi-directional buffers with tri-state outputs. 2. Signals without pull-up resistors have greater than 3mA low output current. Signals requiring pull resistors have greater than 6mA output current. The latter include FRAME, TRDY, IRDY, STOP, SERR, PERR. 3. Absolute maximum pin capacitance for a PCI unit is 10pF (except for CLK). 4. Lower capacitance on this input-only pin allows for non-resistive coupling to AD[xx].
3.2
Local Bus DC Specifications
Table 9: Local Bus Signals DC Operating Specifications for Vcc = 5 volt
Symbol VIL VIH IIL IIH VOL4 VOH4 IOZL IOZH ICC (max) ICC (typ) CIO Description Low level input voltage High level input voltage Low level input current High level input current Low level output voltage for 4 mA outputs and I/O pins High level output voltage for 4 mA outputs and I/O pins Low level float input leakage High level float input leakage Maximum supply current Conditions VCC = 4.75V VCC = 5.25V VIN =GND, VCC=5.25V VIN = VCC = 5.25V IOL = -4 mA IOH = 4 mA VIN = GND VIN = VCC VCC = 5.25V PCLK = LCLK = 33MHz VCC = 5.0V PCLK = LCLK = 33MHz 2.4 -10 10 150 2.0 -10 10 0.4 Min Max 0.8 Units V V A A V
V A A mA
Typical supply current Input and output capacitance
120 10
mA pF
Copyright (c) 1998, V3 Semiconductor Corp.
V350EPC Data Sheet Rev 1.1
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V350EPC
Table 10: Local Bus Signals DC Operating Specifications for Vcc =3.3 volt
Symbol VIL VIH IIL IIH VOL4 VOH4 IOZL IOZH ICC (max) ICC (typ) CIO Description Low level input voltage High level input voltage Low level input current High level input current Low level output voltage for 4 mA outputs and I/O pins High level output voltage for 4 mA outputs and I/O pins Low level float input leakage High level float input leakage Maximum supply current Conditions VCC = 3.0V VCC = 3.6V VIN =GND, VCC =3.6V VIN = VCC = 3.6V IOL = -4 mA IOH = 4 mA VIN = GND VIN = VCC VCC = 3.6V PCLK = LCLK = 33MHz VCC = 3.3V PCLK = LCLK = 33MHz 2.4 -10 10 150 2.0 -10 10 0.4 Min Max 0.8 Units V V A A V
V A A mA
Typical supply current Input and output capacitance
120 10
mA pF
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V350EPC Data Sheet Rev 1.1
Copyright (c) 1998, V3 Semiconductor Inc.
V350EPC 4.0 AC Specifications
The AC specifications for the PCI bus signals match exactly those given in the PCI Specification, Rev. 2.1, Section 4.2.1.2. For more information on the PCI AC specifications, including the V/I curves for 5V signalling, see section 4.2.1.2 of Rev 2.1 PCI Specification.
4.1
PCI Bus Timings Table 11: PCI Bus Signals AC Operating Specifications
Symbol
Parameter Switching current high (Test point) Switching current low (Test point)
Condition 0VVOUT >0.55 VOUT =0.71 -5Min -44 -44+(VOUT-1.4)/0.024
Max
Units mA
Notes 1 1, 2, 3 3 1 1, 3 3
IOH(AC)
Equation A -142
mA mA mA
95 VOUT/0.023 Equation B 206 -25+(VIN+1)/0.015
IOL(AC)
mA mA mA
ICL
Low clamp current Unloaded output rise time Unloaded output fall time
tR
0.4V to 2.4V
1
5
V/ns
4
tF
2.4V to 0.4V
1
5
V/ns
4
Notes: 1. Refer to the V/I curves in Section 4.2.1 of the PCI Specification. This specification does not apply to CLK and RST which are system outputs. "Switching Current High" specifications are not relevant to open drain outputs such as SERR and INTA-INTD. 2. Note that this segment of the minimum current curve is drawn from the AC drive point directly to the DC drive point rather than toward the voltage rail (as it does in the pull-down curve). This difference is intended to allow for an optional N-channel pull-up. 3. Maximum current requirements are met as drivers pull beyond the first step voltage (AC drive point). Equations defining these maximums (A and B) are provided with the respective V/I curves given in the PCI Spec. The equation defined maxima is met by design. 4. The minimum slew rate (slowest signal edge) is met by the PCI drivers. The maximum slew rate (fastest signal edge) is a guideline. Motherboard designers must bear in mind that rise and fall times faster than this maximum guideline could occur, and should ensure that signal integrity modeling accounts for this. Equation A: IOH = 11.9*(VOUT - 5.25V)*(VOUT + 2.45V) for VCC > VOUT > 3.1V Equation B: IOL = 78.5*VOUT(4.4V - VOUT) for 0V < VOUT < 0.71V
Copyright (c) 1998, V3 Semiconductor Corp.
V350EPC Data Sheet Rev 1.1
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V350EPC
4.2 Local Bus Timings Table 12: Local Bus AC Test Conditions
Symbol VCC VCC VIN COUT Parameter Supply voltage 5 volt Supply voltage 3.3 volt Input low and high voltages Capacitive load on output and I/O pins Limits 4.50 to 5.50 3.0 to 3.6 0.4 and 2.0 50 Units V V V pF
Table 13: Capacitive Derating for Output and I/O Pins
Output Drive Limit 4mA 4mA Supply voltage 5 volt 3.3 volt Derating 0.058 ns/pF for loads > 50pF 0.099 ns/pF for loads > 50pF
Figure 3: Clock and Synchronous Signals
TC TCH TSU TH TCL
LOCAL CLOCK INPUT SETUP/HOLD OUTPUT VALID OUTPUT DRIVE OUTPUT FLOAT
VALID
TCOV(max)
TCOV(min)
Tczo
;;;;;;;;;;; ;;;;;;;;;;;
TCOZ ;;;;;;
VALID
;;;;;;
VALID
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V350EPC Data Sheet Rev 1.1
Copyright (c) 1998, V3 Semiconductor Inc.
V350EPC
Table 14: Local Bus Timing Parameters for Vcc = 5 Volts +/- 5%
33MHz # 1 2 3 4 4a 4b 4c 4d Symbol TC TCH TCL TSU TSU TSU TSU TSU TSU TH TCOV TCOV TCZO TCOZ TRST LCLK period LCLK high time LCLK low time Synchronous input setup Synchronous input setup (BLAST) Synchronous input setup (W/R, BTERM) Synchronous input setup (ADS/AS) Synchronous input setup (address, data, byte enables) Synchronous input setup for read data when in local bus master mode Synchronous input hold LCLK to output valid delay LCLK to output valid delay (address, data, byte enable, parity) LCLK to output driving delay LCLK to high impedance delay Reset period when LRST used as input 4 3 3 3 3 3 16*TC 1 1 2 Description Notes Min 30 12 12 7 8 4 6 9 Max 40MHz Min 25 11 11 6 7 4 5 8 Max Units ns ns ns ns ns ns ns ns
4e 5 6 6a 7 8 9
5 2 14 15 15 15
5 2 3 3 3 3 16*TC 12 14 14 14
ns ns ns ns ns ns ns
Copyright (c) 1998, V3 Semiconductor Corp.
V350EPC Data Sheet Rev 1.1
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V350EPC
Table 15: Local Bus Timing Parameters for Vcc = 3.3 Volts +/- 5%
33MHz # 1 2 3 4 4a 4b 4c 4d Symbol TC TCH TCL TSU TSU TSU TSU TSU TSU TH TCOV TCOV TCZO TCOZ TRST LCLK period LCLK high time LCLK low time Synchronous input setup Synchronous input setup (BLAST) Synchronous input setup (W/R, BTERM) Synchronous input setup (ADS/AS) Synchronous input setup (address, data, byte enables) Synchronous input setup for read data when in local bus master mode Synchronous input hold LCLK to output valid delay LCLK to output valid delay (address, data, byte enable, parity) LCLK to output driving delay LCLK to high impedance delay Reset period when LRST used as input 4 3 4 4 4 4 16*TC 1 1 2 Description Notes Min 30 12 12 8 9 7 8 7 Max Units ns ns ns ns ns ns ns ns
4e 5 6 6a 7 8 9
5 3 14 16 16 16
ns ns ns ns ns ns ns
Notes: 1. Measured at 1.5V. 2. All local bus signals except those in 4a, 4b, 4c, 4d and 4e. 3. All local bus signals except those in 6a. 4. READY, BLAST, ADS are driven to high impedance at the falling edge of LCLK.
Table 16: PCI Bus Timing Parameters for Vcc = 5 or 3.3 Volts +/- 5%
# 1 2 2a Symbol TC TSU TSU PCLK period Synchronous input setup to PCLK Synchronous input setup to PCLK (GNT) 1 Description Notes Min 30 7 10 Max Units ns ns ns
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V350EPC Data Sheet Rev 1.1
Copyright (c) 1998, V3 Semiconductor Inc.
V350EPC
Table 16: PCI Bus Timing Parameters for Vcc = 5 or 3.3 Volts +/- 5%
3 4 4a 5 6 7 TH TCOV TCOV TCZO TCOZ TRST Synchronous input hold from PCLK PCLK to output valid delay PCLK to output valid delay (REQ) PCLK to output driving delay PCLK to high impedance delay Reset period when PRST used as input 2 0 3 4 4 5 16*TC 11 12 11 18 ns ns ns ns ns
Notes: 1. All PCI bus signals except those in 2a. 2. All PCI bus signals except those in 4a.
4.3
Serial EEPROM Port TImings
The clock for the serial EEPROM interface is derived by dividing the PCI bus clock. The waveforms generated are shown in Figure 4.
Figure 4: Serial EEPROM Waveforms and Timings
512 PCI BUS CLOCKS STOP CONDITION
START CONDITION
SCL
SDA
256 PCI BUS CLOCKS
256 PCI BUS CLOCKS
Copyright (c) 1998, V3 Semiconductor Corp.
V350EPC Data Sheet Rev 1.1
17
V350EPC 5.0 Revision History
Table 17: Revision History
Revision Number 1.2 1.1 1.0 Date Comments and Changes
4/99 5/98 8/97
Updated for Rev. A1 Addition of 3.3 volt information. First revision of preliminary data sheet.
USA: 2348G Walsh Ave. Santa Clara CA 95051 Phone: (408)988-1050 Fax: (408)988-2601 Toll Free: (800)488-8410 (Canada and U.S. only) World Wide Web: http://www.vcubed.com
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V350EPC Data Sheet Rev 1.1
Copyright (c) 1998, V3 Semiconductor Inc.

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