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User's Manual
OSD LSIs
PD6461 PD6462 PD6464A PD6465 PD6466
Document No. S13197EJ1V0UM00 (1st Edition) Publication Date May 1998 N CP(K)
(c)
Printed in Japan
1998
[MEMO]
2
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
MS-DOS, Windows, and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. PC/AT and PC DOS are trademarks of International Business Machines Corporation.
3
The application circuits and their parameters are for reference only and are not intended for use in actual design-ins.
The information in this document is subject to change without notice. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product.
M7 96.5
4
PREFACE
Target users
This user's manual is intended for users who understand the functions of the PC6461,
PD6462, PD6464A, PD6465, and PD6466 on-screen character display CMOS
LSIs (OSD LSIs) and who will design and develop application systems for them. Purpose The purpose of this user's manual is to help users understand the basic functions of OSD LSIs. Hardware configurations that appear in this manual are illustrative examples only, and there is no plan for their mass production. Configuration This user's manual consists of the following chapters. * CHAPTER 1 OVERVIEW * CHAPTER 2 BASIC OPERATION * CHAPTER 3 APPLICATION EXAMPLES * CHAPTER 4 FAQ * CHAPTER 5 DEVELOPMENT TOOLS How to read this manual Readers of this manual should have a general understanding of electrical and logic circuits, microcontrollers, and video signal processing. Legend Data significance Note Caution Remark : Higher digits on the left and lower digits on the right : Footnote for item marked with Note in the text : Information requiring particular attention : Supplementary information Decimal ............ xxxx Hexadecimal .... 0xxxxx
Active low representation : xxx (overscore over pin or signal name)
Numerical representation : Binary ............... xxxx or 0bxxxx
5
Related documents
The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such.
Data sheets
PD6461 PD6462 PD6464A, PD6465 PD6466
User's manuals OSD LSIs
(Document number: S12588E) (Document number: S12593E) (Document number: S11043E) (Document number: S10991E)
(This manual) (To be prepared) (Document number: S10153E)
OSD LSI Character Pattern Editor for WindowsTM Character Pattern Editor for On-Screen Display LSINote Note Information ROM Code Ordering Method Note
This manual is for MS-DOSTM (for PC-9801) and PC DOSTM (for IBM PC/ATTM).
(Document number: C10302J)Note
This document number is that of Japanese version.
Caution The related documents listed above may be changed without notice. Be sure to use the latest documents for design and other purposes.
6
CONTENTS
CHAPTER 1 OVERVIEW ................................................................................................................... 1.1 1.2 1.3 1.4 List of OSD LSIs ................................................................................................................ Ordering Information ........................................................................................................ Pin Configurations ............................................................................................................ Block Diagrams .................................................................................................................
13 14 15 16 24 27 27
27 29 29 30 30 31 31 31
CHAPTER 2 BASIC OPERATION ..................................................................................................... 2.1 OSD LSI Configuration .....................................................................................................
2.1.1 2.1.2 2.1.3 2.1.4 2.1.5 2.1.6 2.1.7 2.1.8 2.2.1 2.2.2 2.2.3 2.3.1 2.3.2 2.3.3 Dot clock oscillation circuit ..................................................................................................... Timing generator ..................................................................................................................... Horizontal control section ....................................................................................................... Vertical control section ............................................................................................................ Video RAM control section ..................................................................................................... Video RAM .............................................................................................................................. Character generator ROM ...................................................................................................... Output controller ..................................................................................................................... Quadruple/4fsc crystal oscillation circuit ................................................................................ Synchronization separation circuit ......................................................................................... Video signal output section .................................................................................................... Synchronization protection circuit .......................................................................................... R, G, B, and BLK outputs when RGB + VC1 + VC2 is selected ............................................. R, G, B, and BLK outputs when RGB + blanking corresponding to RGB (3BLK) is selected .....................................................................................................
2.2 Basic Operation of a Video-System OSD LSI ...............................................................
32
32 34 39
2.3 Basic Operation of an RGB-System OSD LSI ...............................................................
41
41 45 47
2.4 Characters ..........................................................................................................................
2.4.1 2.4.2 2.5.1 2.5.2 Character display .................................................................................................................... Character patterns .................................................................................................................. Command format .................................................................................................................... Command list ..........................................................................................................................
49
49 50
2.5 Commands .........................................................................................................................
50
50 51
2.6 OSD LSI Power-ON Initialization .................................................................................... CHAPTER 3 APPLICATION EXAMPLES ......................................................................................... 3.1 Video-System OSD LSI Application Examples .............................................................
3.1.1 3.1.2 3.1.3 3.1.4 Sample PD6464A or PD6465 application circuits ............................................................. Composite synchronization signal (Csync) separation circuit .............................................. Sample application for separate video signal input .............................................................. Sample application for NTSC direct mode ............................................................................
56 57 57
57 60 63 64
7
3.2 RGB-System OSD LSI Application Examples ...............................................................
3.2.1 3.2.2 Sample PD6461A or PD6462 application circuit ............................................................... Sample PD6466 application circuit ......................................................................................
66
66 67
3.3 External Clock Forced Input to LC Oscillation Circuit Section ................................. CHAPTER 4 FAQ ............................................................................................................................... 4.1 All OSD LSIs ...................................................................................................................... 4.2 Video-System OSD LSIs (PD6464A and PD6465) ..................................................... 4.3 RGB-System OSD LSIs (PD6461, PD6462, and PD6466) ...................................... CHAPTER 5 DEVELOPMENT TOOLS ............................................................................................. 5.1 Overview of Development Tools ..................................................................................... 5.2 Concerning OSD LSI Mask ROM Ordering ....................................................................
68 69 69 73 76 79 79 83
8
LIST OF FIGURES (1/2)
Figure No. 1-1 1-2 1-3 1-4 1-5 1-6 1-7 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 2-18 2-19 2-20 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8
Title Sample Uses of OSD LSIs (RGB-System OSD LSI: Camcorder) ..................................................
Page 13 16 18 21 24 25 26 27 28 29 30 30 33 35 36 39 40 42 43 43 44 44 45 46 47 48 49
PD6464A or PD6465 Pin Configuration (Top View) ...................................................................... PD6461 or PD6462 Pin Configuration (Top View) ........................................................................ PD6466 Pin Configuration (Top View) ............................................................................................. PD6464A and PD6465 Block Diagram .......................................................................................... PD6461 and PD6462 Block Diagram ............................................................................................ PD6466 Block Diagram ....................................................................................................................
OSD LSI Basic Block Diagram ........................................................................................................... Dot Clock Oscillation Equivalent Circuit ............................................................................................ Horizontal Control Section .................................................................................................................. Vertical Control Section ...................................................................................................................... Video RAM Control Section ................................................................................................................ Quadruple/4fsc Crystal Oscillation Circuit ......................................................................................... Synchronization Separation Circuit Section ...................................................................................... Sample Horizontal Synchronization Signal Correction Circuit Timing Charts .................................. Video Signal Output Section Equivalent Circuit ................................................................................ VSYT and VPED Levels of Composite Video Signal ............................................................................. Display Character Vertical Jitter Generation Mechanism ................................................................. Synchronization Protection Circuit Operation (Mode 1) .................................................................... Synchronization Protection Circuit Operation (Mode 2) .................................................................... Synchronization Protection Circuit Operation (Mode 3) .................................................................... Synchronization Protection Circuit Operation (Mode 4) .................................................................... Display Character Vertical Jitter Prevention Mechanism .................................................................. Output Pins: Sample R, G, B, and BLK Output Images When RGB + VC1 + VC2 Is Selected ....... Sample R, G, B, and BLK Output Images When RGB + 3BLK Is Selected .................................... Sample Use of Blanking Signals Corresponding to RGB ................................................................. Character Display ............................................................................................................................... Sample PD6464A or PD6465 Application Circuit (When Quadruple Oscillation Is Selected)......................................................................................... Sample PD6464A or PD6465 Application Circuit (When 4fsc Crystal Oscillation Is Selected) ...................................................................................... Composite Synchronization Signal Separation Circuit ...................................................................... Sample Application Circuit for Separate Video Signal Input ............................................................. Sample Application Circuit for NTSC Direct Mode ............................................................................ Sample PD6461 or PD6462 Application Circuit ............................................................................ Sample PD6466 Application Circuit ................................................................................................. Timing Chart for External Clock Forced Input ...................................................................................
58 59 60 63 65 66 67 68
9
LIST OF FIGURES (2/2)
Figure No. 4-1 4-2 4-3 5-1 5-2 5-3 5-4 5-5
Title Character Display Area Image 1 - When NTSC and PAL Signals Are Input (for Equivalent Display Start Position and Dot Clock Frequency) .................................................... Character Display Area Image 2 - When NTSC and PAL Signals Are Input (for Center Display) ............................................................................................................................. Sample Display Using Character Inversion ....................................................................................... ROM Verification Board Connection Diagram for RGB Display ....................................................... ROM Verification Board Connection Diagram for VCR Display ....................................................... Video-System OSD LSI Evaluation Board Connection Diagram ...................................................... RGB-System OSD LSI Evaluation Board Connection Diagram ....................................................... OSD LSI Mask ROM Code Ordering Procedure (for FD Order Reception) ....................................
Page
72 72 77 80 81 82 82 83
10
LIST OF TABLES
Table No. 1-1 1-2 1-3 1-4 1-5 2-1 2-2 2-3 2-4 2-5 2-6 2-7 3-1
Title List of OSD LSIs ................................................................................................................................. Ordering Information ........................................................................................................................... List of PD6464A and PD6465 Pin Functions ................................................................................ List of PD6461 and PD6462 Pin Functions ................................................................................... List of PD6466 Pin Functions ...........................................................................................................
Page 14 15 17 20 23 40 50 51 52 53 54 55 64
PD6464A or PD6465 Internal Video Signal Level .........................................................................
Command Data Transfer Format .......................................................................................................
PD6464A or PD6465 Command Tables ........................................................................................ PD6461 or PD6462 Command Tables (MSB First) ....................................................................... PD6461 or PD6462 Command Tables (LSB First) ........................................................................ PD6466 Command Tables (MSB First) ............................................................................................ PD6466 Command Tables (LSB First) .............................................................................................
NTSC Direct Mode Setting Command ...............................................................................................
11
[MEMO]
12
CHAPTER 1 OVERVIEW
The on-screen character display CMOS LSI (OSD LSI) is used to display character data on various types of monitor screens. The size of one character is 12 (horizontal) by 18 (vertical) dots, and up to 12 lines of 24 columns (288 characters) can be displayed. The character types are determined by the ROM capacity of each product. NEC has 128-character (PD6462, PD6464A), 256-character (PD6461, PD6465), and 512-character (PD6466) OSD LSIs. Also, the NEC OSD LSIs are broadly divided into video-system OSD LSIs (PD6464A, PD6465) and RGB-system OSD LSIs (PD6461, PD6462, PD6466) according to their use. By combining it with a microcontroller, a videosystem OSD LSI controls not only the program screen of a deck-type VCR or LD player, but also various indicators (such as the tape counter). An RGB-system OSD LSI controls the display of the counter, time, date, and other indicators on the viewfinder of a camcorder, the transcription of the time, date, and other indicators on a video tape, and the display of the channel or other indicators on a TV screen. This user's manual describes the operation of OSD LSIs and presents several practical examples of their use. Figure 1-1. Sample Uses of OSD LSIs (RGB-System OSD LSI: Camcorder)
LCD (color) Lens
Camera section, synchronization Image signal Character MIX separation section, RGB decoder color signal processing section, etc.
REC
TAPE BATT
Hsync, Vsync
VR, VG, VB, VBLK OSD VC1, BLK1 Viewfinder (black and white) REC Character MIX TAPE BATT
Microcontroller VC2, BLK2
Recording system (deck)
Character MIX
Recorded contents
PM 1:30 1997.12
13
CHAPTER 1 OVERVIEW
1.1 List of OSD LSIs
Table 1-1. List of OSD LSIs
Video-system Sample uses Product name Character type TV, video, video CD RGB-system Camcorder, DVD, LCD TV, digital still camera
PD6464A
128
PD6465
256
PD6461
256
PD6462
128
PD6466
512
Number of display characters 12 lines x 24 columns (288 characters) Dot matrix Character color 12 (horizontal) x 18 (vertical) dots Single color (white) (select brightness 8 colors level for the screen from 75IRE/95IRE) 1x and 2x (simultaneous horizontal and vertical specification) 1x, 2x, 3x, and 4x (independent horizontal and vertical specifications) Black characters (framing control disabled) White characters (framing control enabled) Available (cannot be used when blinking is specified)
Character size (unit: lines)
Character color inversion (unit: characters)
None
Black characters (no framing)
Character left-right inversion None (unit: characters)
Blinking (unit: characters)
Blinking ratio is 1:1 (blinking frequency can be selected for the entire screen from the three options corresponding to approximately 0.5, 1, and 2 Hz)
Internal video signal color
White, black, blue, or green
None
White or blue (effective only for RGB-system output)
Background (unit: screen) Background color (unit: screen) Framing color (unit: screen) Supported video signal method Video signal input/output Character signal output
No background, black framing, black-on-white, black filling Single color (black) 8 colors (RGB-system output) or single color (black: VC1 and VC2 system output) 2 colors (white and black) --
Single color (black) NTSC, PSL, PAL-M, SECAM, or PAL-N (PD6464A only) Composite video signal Character signal and blanking signal
No input/output system RGB + 3BLK or RGB + VC1 + VC2 (for PD6461 and PD6462, select according to mask code option; for PD6466, select according to command)
Video RAM data clear
Video RAM data can be cleared by the video RAM batch clear command and the power-ON clear function
Interface with microcontroller Serial input type of 8-bit variable word length Operation power supply range 4.5 to 5.5 V Packages 24-pin SDIP 24-pin SOP 2.7 to 5.5 V 20-pin SSOP 24-pin SOP 20-pin SSOP 20-pin SSOP 24-pin SOP
14
CHAPTER 1 OVERVIEW
1.2 Ordering Information
Table 1-2. Ordering Information
Part Number Videosystem Package 24-pin plastic shrink DIP (300 mils) 24-pin plastic SOP (375 mils) 24-pin plastic shrink DIP (300 mils) 24-pin plastic SOP (375 mils) 20-pin plastic shrink SOP (300 mils) 001 101 001 101 101: MSB first, 3-line unit setting, RBG + 3BLK, option B, LC oscillation 102: MSB first, 3-line unit setting, RBG + VC1 + VC2, option B, LC oscillation -- 001: MSB first, 3-line unit setting, RBG + VC1 + VC2, option C, LC oscillation 001 201 NEC standard ROM code number
PD6464ACS-xxx PD6464AGT-xxx PD6465CS-xxx PD6465GT-xxx
RGBsystem
PD6461GS-xxx
PD6461GT-xxx PD6462GS-xxx PD6466GS-xxx PD6466GT-xxx
24-pin plastic SOP (375 mils) 20-pin plastic shrink SOP (300 mils)
20-pin plastic shrink SOP (300 mils) 24-pin plastic SOP (375 mils)
Remarks 1. 2.
xxx indicates ROM code suffix. For the PD6461 and PD6462, the following are selected according to the mask code option (for the
PD6466, they can be selected according to the initialization command or the CMDCT pin). For details,
refer to the data sheet for each product. * Data transfer * Pin selection * Output selection * Dot clock : LSB first or MSB first : RBG + VC1 + VC2 or RGB + 3BLK : Option A, option B, or option C : LC oscillation or external clock input * Vertical display start position : 3-line unit setting or 9-line unit setting
15
CHAPTER 1 OVERVIEW
1.3 Pin Configurations
Figure 1-2. PD6464A or PD6465 Pin Configuration (Top View) 24-pin plastic shrink DIP (300 mils)
PD6464ACS-xxx PD6465CS-xxx
24-pin plastic SOP (375 mils)
PD6464AGT-xxx PD6465GT-xxx
CLK CS DATA VDD OSCOUT OSCIN PCL GND FSCI FSCO XOSO XOSI
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
VBSI VCNT SECAM VBSO NRE TEST N.C. CSYIN VSYO HSYO VBLK VC
Remark xxx indicates ROM code suffix. CLK CS DATA FSCI FSCO GND HSYO N.C. NRE OSCIN : Clock Input : Chip Select Input : Serial Data Input : fSC Signal Input : Frequency Error Output : Ground : Horizontal Synchronization Signal Output : No Connection : Noise Reduction Constant Append : LC Oscillation Input PCL TEST VBLK VBSI VBSO VC VCNT VDD VSYO XOSI XOSO : Power-on Clear : Test Pin : Blanking Signal Output : Composite Video Signal Input : Composite Video Signal Output : Character Signal Output : Video Signal Output Level Adjustment : Power Supply : Vertical Synchronization Signal Output : Quadruple Oscillation Input : Quadruple Oscillation Output
SECAM : SECAM subcarrier Input
CSYIN : Composite Synchronization Signal Input
OSCOUT : LC Oscillation Output
16
CHAPTER 1 OVERVIEW
Table 1-3. List of PD6464A and PD6465 Pin Functions
Pin No. Pin Symbol 1 CLK Pin Name Clock Input Function Inputs clock for data read. Data input to the DATA pin is read at the rising edge of the clock input to this pin. Serial transfer can be acknowledged by making this CS pin low. Inputs control data. Data is read in synchronization with the clock input to the CLK pin. Supplies power to the IC. These are input and output pins of an oscillator that generates dot clocks. Connect a coil and a capacitor to these pins for oscillation. Power-ON clear pin. Make this pin high on power application. It initializes the internal circuitry of the IC. Ground pin of the IC. Inputs color subcarrier signal (fsc) when quadruple oscillation is selected. Connect it to GND or VCC when 4fsc crystal oscillation is selected. Frequency error output signal of the x4 multiplier. Leave it open when 4fsc crystal oscillation is selected. The quadruple oscillator LC for internal video signal generation is connected to these pins. A crystal oscillator also can be connected. Character signal output pin, which is high active. This pin outputs a blanking signal that cuts the video signal. It corresponds to VC output and is high active. Outputs a horizontal synchronization signal separated from the composite synchronization signal. Outputs a vertical synchronization signal separated from the composite synchronization signal. Inputs a composite synchronization signal for synchronization separation. Always input this signal when external video signal mode is used. The input polarity is positive synchronization. Free pin. Leave this pin open. Test mode select pin. Generally, connect this pin to GND. Constant append pin for noise reduction.
2 3
CS DATA
Chip Select Input Serial Data Input
4 5 6 7
VDD OSCOUT OSCIN PCL
Power Supply LC Oscillation Output LC Oscillation Input Power-ON Clear
8 9
GND FSCI
Ground fsc Signal Input
10
FSCO
Frequency Error Output
11 12 13 14
XOSO XOSI VC VBLK
Quadruple Oscillation Output Quadruple Oscillation Input Character Signal Output Blanking Signal Output
15
HSYO
Horizontal Synchronization Signal Output
16
VSYO
Vertical Synchronization Signal Output Composite Synchronization Signal Input
17
CSYIN
18 19 20
N.C. TEST NRE
No Connection Test Pin Noise Reduction Constant Append
21
VBSO
Composite Video Signal Output Outputs a composite video signal with which the character signal is mixed. SECAM subcarrier Input SECAM subcarrier signal mixing pin. When a mode other than SECAM is selected, leave this pin open. Adjusts the output level adjustment of the composite video signal and luminance signal. Inputs a composite video signal. Inputs a signal with the leading edge clamped, consisting of a negative synchronization and positive video signal.
22
SECAM
23
VCNT
Video Signal Output Level Adjustment Composite Video Signal Input
24
VBSI
17
CHAPTER 1 OVERVIEW
Figure 1-3. PD6461 or PD6462 Pin Configuration (Top View) 20-pin plastic shrink SOP (300 mils)
PD6461GS-xxx PD6462GS-xxx
CLK CS DATA PCL VDD CKOUT OSCOUT OSCIN TEST GND
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
Hsync Vsync VB VG VR VBLK (BBLK) VC2 (GBLK) BLK2 (RBLK) VC1 BLK1
24-pin plastic SOP (375 mils)
PD6461GT-xxx
CLK CS N.C. DATA PCL VDD CKOUT OSCOUT OSCIN TEST GND N.C.
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
Hsync Vsync N.C. VB VG VR VBLK (BBLK) VC2 (GBLK) BLK2 (RBLK) VC1 BLK1 N.C.
Remarks 1. 2.
xxx indicates ROM code suffix. The symbols enclosed in parentheses are set by the mask code option (RGB + Blanking corresponding to RGB).
18
CHAPTER 1 OVERVIEW
BBLK CKOUT CLK CS DATA GBLK GND Hsync N.C. OSCIN OSCOUT PCL RBLK TEST VB VBLK VC1, VC2 VDD VG VR Vsync
: Blanking B : Clock Output : Clock Input : Chip Select : Data Input : Blanking G : Ground : Horizontal Synchronous Signal Input : No Connection : Oscillator Input : Oscillator Output : Power-on Clear : Blanking R : Test : Character Signal Output : Blanking Signal Output for VR, VG, and VB : Character Signal output 1, 2 : Power supply : Character Signal Output : Character Signal Output : Vertical Synchronous Signal Input
BLK1, BLK2 : Blanking Output 1, 2
19
CHAPTER 1 OVERVIEW
Table 1-4. List of PD6461 and PD6462 Pin Functions
Pin No.Note 1 1
Note 2
Pin Symbol CLK
Pin NameNote 2 Clock Input
Function Inputs clock for data read. Data input to the DATA pin is read at the rising edge of the clock input to this pin. Serial transfer can be acknowledged by making this CS pin low. Inputs control data. Data is read in synchronization with the clock input to the CLK pin. Power-ON clear pin. Make this pin high on power application. It initializes the internal circuitry of the IC. Supplies power to the IC. Checks the oscillation frequency. It uses N-channel open-drain output. These are input and output pins of an oscillator that generates dot clocks. Connect a coil and a capacitor to these pins for oscillation. (When external clock input is selected by the mask option, the external clock (clock synchronized with Hsync) is input. OSCOUT is left open.) IC test pin. Connect this pin to GND. Connect this pin to the system GND. This pin outputs a blanking signal that cuts the video signal. It corresponds to VC1 output and is high active. (When blanking corresponding to RGB is selected by the mask option, the logical sum of RBLK, GBLK, and BBLK is output.)
2 3 (4)
CS DATA
Chip Select Input Serial Data Input
4 (5)
PCL
Power-ON Clear
5 (6) 6 (7)
VDD CKOUT
Power Supply Clock Output
7 (8) 8 (9)
OSCOUT OSCIN
LC Oscillation Input/Output (OSCIN: External clock input)
9 (10) 10 (11) 11 (14)
TEST GND BLK1
Test Pin Ground Blanking Signal Output 1
12 (15)
VC1
Character Signal Output 1
Outputs the character signal. It is high active. (When blanking corresponding to RGB is selected by the mask option, the logical sum of VR, VG, and VB is output.) This pin outputs a blanking signal that cuts the video signal. It corresponds to VC2 output and is high active. (The blanking signal corresponding to VR output is output. It is high active.) Outputs the character signal. It is high active. (The blanking signal corresponding to VG output is output. It is high active.) This pin outputs a blanking signal that cuts the video signal. It corresponds to VR, VG, and VB output and is high active. (The blanking signal corresponding to VB output is output. It is high active.) Character signal output pin, which is high active.
13 (16)
BLK2 (RBLK)
Blanking Signal Output 2 (Blanking R)
14 (17)
VC2 (GBLK)
Character Signal Output 2 (Blanking G)
15 (18)
VBLK (BBLK)
Blanking Signal Output (Blanking B)
16 (19) 17 (20) 18 (21) 19 (23)
VR VG VB Vsync
Character Signal Output
Vertical Synchronization Signal Input Horizontal Synchronization Signal Input No Connection
Inputs the vertical synchronization signal. Input using negative synchronization. Inputs the horizontal synchronization signal. Input using negative synchronization. Free pin.
20 (24)
Hsync
(3,12,13,22)
N.C.
Notes 1. The numbers enclosed in parentheses are pin numbers for the PD6461GT-xxx. 2. The symbols and names enclosed in parentheses are set by the mask code option (RGB + Blanking corresponding to RGB).
20
CHAPTER 1 OVERVIEW
Figure 1-4. PD6466 Pin Configuration (Top View) 20-pin plastic shrink SOP (300 mils)
PD6466GS-xxx
CLK CS DATA PCL VDD CMDCT OSCOUT OSCIN TEST GND
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
Hsync Vsync VB VG VR VBLK (BBLK) VC2 (GBLK) BLK2 (RBLK) VC1 BLK1
24-pin plastic SOP (375 mils)
PD6466GT-xxx
CLK CS N.C. DATA PCL VDD CMDCT OSCOUT OSCIN TEST GND N.C.
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
Hsync Vsync N.C. VB VG VR VBLK (BBLK) VC2 (GBLK) BLK2 (RBLK) VC1 BLK1 N.C.
Remarks 1. 2.
xxx indicates ROM code suffix. The symbols enclosed in parentheses are set by the initialization command (RGB + Blanking corresponding to RGB).
21
CHAPTER 1 OVERVIEW
BBLK CLK CMDCT CS DATA GBLK GND Hsync N.C. OSCIN OSCOUT PCL RBLK TEST VB VBLK VC1, VC2 VDD VG VR Vsync
: Blanking B : Clock : Command Control : Chip Select : Data Input : Blanking G : Ground : Horizontal Synchronous Signal Input : No Connection : Oscillator Input : Oscillator Output : Power-on Clear : Blanking R : Test : Character Signal Output : Blanking Signal Output for VR, VG, and VB : Character Signal output 1, 2 : Power supply : Character Signal Output : Character Signal Output : Vertical Synchronous Signal Input
BLK1, BLK2 : Blanking Output 1, 2
22
CHAPTER 1 OVERVIEW
Table 1-5. List of PD6466 Pin Functions
Pin No.Note 1 1
Note 2
Pin Symbol CLK
Pin NameNote 2 Clock Input
Function Inputs clock for data read. Data input to the DATA pin is read at the rising edge of the clock input to this pin. Serial transfer can be acknowledged by making this CS pin low. Inputs control data. Data is read in synchronization with the clock input to the CLK pin. Power-ON clear pin. Make this pin high on power application. It initializes the internal circuitry of the IC. Supplies power to the IC. Switches between LSB-first and MSB-first input for commands. When this pin is low, LSB-first input is used. When it is high, MSBfirst input is used. When using LSB-first input, this pin can be left open. These are input and output pins of an oscillator that generates dot clocks. Connect a coil and a capacitor to these pins for oscillation. (When external clock input is selected by the initialization command, the external clock (clock synchronized with Hsync) is input. OSCOUT is left open.) IC test pin. Connect this pin to GND. Connect this pin to the system GND. This pin outputs a blanking signal that cuts the video signal. It corresponds to VC1 output and is high active. (When blanking corresponding to RGB is selected by the command, the logical sum of RBLK, GBLK, and BBLK is output.)
2 3 (4)
CS DATA
Chip Select Input Serial Data Input
4 (5)
PCL
Power-ON Clear
5 (6) 6 (7)
VDD CMDCT
Power Supply Command Control
7 (8) 8 (9)
OSCOUT OSCIN
LC Oscillation Input/Output (OSCIN: External clock input)
9 (10) 10 (11) 11 (14)
TEST GND BLK1
Test Ground Blanking Signal Output 1
12 (15)
VC1
Character Signal Output 1
Outputs the character signal. It is high active. (When blanking corresponding to RGB is selected by the command, the logical sum of VR, VG, and VB is output.) This pin outputs a blanking signal that cuts the video signal. It corresponds to VC2 output and is high active. (The blanking signal corresponding to VR output is output. It is high active.) Outputs the character signal. It is high active. (The blanking signal corresponding to VG output is output. It is high active.) This pin outputs a blanking signal that cuts the video signal. It corresponds to VR, VG, and VB output and is high active. (The blanking signal corresponding to VB output is output. It is high active.) Character signal output pin, which is high active.
13 (16)
BLK2 (RBLK)
Blanking Signal Output 2 (Blanking R)
14 (17)
VC2 (GBLK)
Character Signal Output 2 (Blanking G)
15 (18)
VBLK (BBLK)
Blanking Signal Output (Blanking B)
16 (19) 17 (20) 18 (21) 19 (23)
VR VG VB Vsync
Character Signal Output
Vertical Synchronization Signal Input Horizontal Synchronization Signal Input No Connection
Inputs the vertical synchronization signal. Input using negative synchronization. Inputs the horizontal synchronization signal. Input using negative synchronization. Free pin.
20 (24)
Hsync
(3,12,13,22)
N.C.
Notes 1. The numbers enclosed in parentheses are pin numbers for the PD6466GT-xxx. 2. The names enclosed in parentheses are set by the initialization command (RGB + Blanking corresponding to RGB).
23
Data selector
24
DATA 3 CLK 1 Data input shift register CS 2 Data buffer register External/ internal register
NTSC/ PAL/ PAL-M/ SECAM/ PAL-NNote register
1.4 Block Diagrams
Figure 1-5. PD6464A and PD6465 Block Diagram
4 VDD Instruction decoder Control signal 8 GND 19 TEST 7 PCL
Character size register
Horizontal address register
Write address counter
Video RAM
Character data 7 bits ( PD6464A) or 8 bits ( PD6465) x 288 words
Blink data 1 bit
x
Horizontal size counter
Horizontal position counter
Horizontal address counter
288 words
Background control data register
Display control data register
CHAPTER 1 OVERVIEW
Vertical address register OSCIN 6 Losc OSCOUT 5 Oscillation circuit Timing generator Vertical size counter Vertical position counter Vertical address counter
Character generator ROM 12 x 18 bits x 128 words ( PD6464A) or 256 words ( PD6465)
CoscIN
CoscOUT
Synchronization signal separation circuit Synchronization signal generator
Mode selection
Quadruple/4fsc crystal oscillation circuit
Output controller
17 CSYIN Note PD6464A only
15 16 HSYO VSYO
10
9
11 12
13
14
20
21
22
23
24
FSCO FSCI XOSO XOSI
VC VBLK
VBSO VCNT VBSI NRE SECAM
Figure 1-6. PD6461 and PD6462 Block Diagram
TEST VDD DATA CLK Data input shift register Instruction decoder Control signal GND PCL CS Display position horizontal address register
Character size register
Write address counter
Video RAM
Background control data register Display control data register
CHAPTER 1 OVERVIEW
Data selector CKOUT Horizontal size counter Horizontal position counter Horizontal address counter
Chara- Color Blink Invert Output data specifidata data cter 1 bit cation data 3 bits 1 bit data x x x 8 bits 1 bit 288 288 288 x x 288 words words words 288 words words
OSCIN Oscillation circuit
OSCOUT
Display position vertical address register
256 words ( PD6461) or 128 words ( PD6462) Synchronization protection circuit
Character generator ROM 12 x 18 bits x
Hsync Vsync
Vertical size counter
Vertical position counter
Vertical address counter Output controller
Remark The symbols enclosed in parentheses are set by the mask code option (RGB + Blanking corresponding to RGB).
VR VG VB VBLK VC1 BLK1 VC2 BLK2 (BBLK) (GBLK) (RBLK)
25
...
26
CMDCT DATA CLK CS Data input shift register Display control register Character size register Horizontal size counter OSCIN OSCOUT Oscillation circuit Hsync Vsync Synchronization protection circuit Vertical size counter
Figure 1-7. PD6466 Block Diagram
TEST VDD Instruction decoder Control signal GND PCL
Horizontal address register
Write address counter Character data 9 bits x 288 words
Video RAM
Color data 3 bits x 288 words Blink data 1 bit x 288 words Invert Output data specifi1 bit cation x data 288 1 bit words x 288 words
Horizontal position counter
Horizontal address counter
Data selector
Background control data register
CHAPTER 1 OVERVIEW
Vertical address register
Character generator ROM 12 x 18 bits x 512 words
Vertical address counter
Vertical position counter
Output controller
VR VG VB VBLK (BBLK) Remark The symbols enclosed in parentheses are set by the initialization command (RGB + Blanking corresponding to RGB).
VC1 BLK1 VC2 BLK2 (GBLK) (RBLK)
CHAPTER 2 BASIC OPERATION
This chapter describes the basic operation of an OSD LSI.
2.1 OSD LSI Configuration
An OSD LSI consists of a dot clock oscillation circuit, timing generator, horizontal control section, vertical control section, video RAM control section, video RAM, character generator ROM, display/background control register section, and output controller. The OSD LSI, which is controlled by command data sent from a microcontroller, displays the character data stored in the character generator ROM (PD6462 and PD6464A: 128 characters; PD6461 and PD6465: 256 characters;
PD6466: 512 characters) on the display screen.
Figure 2-1. OSD LSI Basic Block Diagram
Command data
Horizontal control section
Vertical control section Dot clock oscillation ON/OFF Timing generator
Video RAM control section
Video RAM
Display/background control register section
Character generator ROM 12 x 18 bits x
Number of characters
Output controller
Output of various types of signals
Dot clock oscillation circuit
Hsync
Vsync
Video-system : Input from synchronization separation circuit RGB-system : Input from synchronization separation protection circuit
2.1.1 Dot clock oscillation circuit The dot clock oscillation circuit consists of the OSD LSI and an externally connected LC circuit. With an RGBsystem OSD LSI, external clock input can be selected (For the PD6461 and PD6462, this is selected by the mask code option; for the PD6466, it is selected by the initialization command).

27
CHAPTER 2 BASIC OPERATION
Figure 2-2. Dot Clock Oscillation Equivalent Circuit (a) When LC oscillation is selected (b) When external clock input is selected (PD6461, PD6462, or PD6466)
High level when oscillation is OFF (from timing generator) To timing generator
Always high level (from timing generator) To timing generator
OSCIN
OSCOUT
OSCIN
OSCOUT Open
External clock input
Remark When LC oscillation is ON, the dot clock oscillation circuit is controlled as follows by the timing generator while Hsync is low. When display is ON : Dot clock oscillation stopped When display is OFF : Dot clock oscillation The dot clock frequency (fosc) when LC oscillation is ON can be calculated using the following formulas. 1 (2LC)
fosc =
[Hz]
C=
Cin * Cout (Cin + Cout)
[F]
By setting L = 33 H, Cin = 5 to 30 pF (trimmer capacitor), and Cout = 30 pF, the circuit can be used in the LC oscillation frequency range (fosc = 6 to 8 MHz) recommended by NEC for operation. The actual circuit will have a lower frequency than the calculated value due to effects such as the stray capacitance of the pins or delay within the LSI.
28
CHAPTER 2 BASIC OPERATION
2.1.2 Timing generator The timing generator generates various types of timing signals according to horizontal/vertical synchronization signals input from the dot clock oscillation circuit, synchronization separation circuit, synchronization signal generator (video-system OSD LSI) or synchronization protection circuit (RGB-system OSD LSI) commands from the microcontroller (such as LC oscillation ON/OFF, crystal oscillation ON/OFF, or display ON/OFF, etc.). 2.1.3 Horizontal control section The horizontal display start position of a character is determined by counting dot clocks from the rising edge of the horizontal synchronization signal (Hsync). The character is displayed at the position corresponding to this horizontal display start position and the specified video RAM column address. Each block reset is synchronized with Hsync. If Hsync is not supplied within the OSD LSI, the character is not displayed correctly, since no reset occurs. Figure 2-3. Horizontal Control Section
Command data
Character size register
Horizontal address register
Dot clock From timing generator Hsync
Horizontal size counter
Horizontal position counter
Horizontal address counter
To video RAM control section
To vertical control section
29
CHAPTER 2 BASIC OPERATION
2.1.4 Vertical control section The vertical display start position of a character is determined by counting rising edges of the horizontal synchronization signal (Hsync) from the rising edge of the vertical synchronization signal (Vsync). The character is displayed at the position corresponding to this vertical display start position and the specified video RAM line address. The character type to be displayed is set by the character generator ROM line address control. Figure 2-4. Vertical Control Section
Command data
From character size register
Vertical address register
Hsync From timing generator Vsync
Vertical size counter
Vertical position counter
Vertical address counter
To video RAM control section
2.1.5 Video RAM control section The video RAM control section controls video RAM addresses. When a video RAM batch clear command is executed, the Display Off Code is written to all addresses (288 words) of video RAM. Figure 2-5. Video RAM Control Section
Video RAM batch clear command
Data
Video RAM batch clear control circuit
Write-address control command Display-address data from horizontal and vertical control sections
Video RAM write-address counter Data selector
Video RAM
30
CHAPTER 2 BASIC OPERATION
2.1.6 Video RAM The video RAM maintains data set in character units corresponding to a 12 line by 24 column display area. 2.1.7 Character generator ROM The character generator ROM stores a character font. The number of characters is determined by the ROM capacity. The character generator ROM for a video-system OSD LSI can have a capacity of 128 characters (PD6464A) or 256 characters (PD6465). For an RGB-system OSD LSI, can have a capacity of 128 characters (PD6462), 256 characters (PD6461), or 512 characters (PD6466). 2.1.8 Output controller The output controller controls the display of characters, backgrounds, and other output.
31
CHAPTER 2 BASIC OPERATION
2.2 Basic Operation of a Video-System OSD LSI
This section describes the basic operation of the circuits of a video-system OSD LSI (PD6464A or PD6465). 2.2.1 Quadruple/4fSC crystal oscillation circuit Figure 2-6 shows a block diagram of a quadruple/4fSC crystal oscillation circuit. With the PD6464A or PD6465, quadruple oscillation or 4fSC crystal oscillation is selected according to the externally connected circuit and oscillation mode control command. Since the 4fSC signal generated by the oscillation circuit is used as the reference clock for synchronization signal generation when internal video signal mode is set and the fSC signal is used as the reference clock for internal video signal generation and for synchronization separation in the synchronization separation circuit, a crystal oscillation control command must be used to set crystal oscillation to ON when generating characters. The operation of this circuit when each mode is selected is explained below. (1) When quadruple oscillation is selected The fSC signal must be input from the FSCI pin (pin 9) (see Figure 3-1 Sample PD6464A or PD6465 Application Circuit (When Quadruple Oscillation Is Selected)). The 4fSC signal is generated by an externally connected LC oscillator and internal circuits of the PD6464A or PD6465. Also, the phase of the signal obtained by dividing the 4fSC signal generated by LC oscillation into 4 parts is compared with the phase of the fSC signal input to the FSCI pin, and the phase differential is converted to a voltage value and output from the FSCO pin (pin 10). A 4fSC signal that is synchronized with the external fSC signal is generated by varying the varactor diode capacitance according to this voltage. Selecting this mode reduces the crystal oscillator and enables the installation area and cost to be reduced. (2) When 4fSC crystal oscillation is selected Connect a crystal resonator (frequency: 4fSC) between the XOSO pin (pin 11) and XOSI pin (pin 12) and connect a capacitor (approx. 30 pF) between the XOSO pin (pin 11) and ground (GND) and connect a trimmer capacitor (5 to 30 pF) between the XOSI pin (pin 12) and ground (GND) (see Figure 3-2 Sample PD6464A or PD6465 Application Circuit (When 4fSC Crystal Oscillation Is Selected)). This crystal oscillator generates the 4fSC signal, and the fSC signal is generated by dividing this 4fSC signal into four parts.
32
CHAPTER 2 BASIC OPERATION
Figure 2-6. Quadruple/4fsc Crystal Oscillation Circuit (a) When quadruple oscillation is selected
To synchronization separation circuit or internal video signal generation circuit fSC 1/4
To synchronization signal generator 4fSC
Crystal oscillation ON/OFF
Phase detector
FSCI 9 5.1 k
FSCO 10
XOSO 11 4.7 H
XOSI 12
0.01 F
100 k
47 pF 1000 pF 20 k VD 18 pF 20 k
2200 pF fSC
1.5 k + 1 F
NTSC, PAL-M : H PAL, SECAM : L
(b) When 4fsc crystal oscillation is selected
To synchronization separation circuit or internal video signal generation circuit fSC 1/4
To synchronization signal generator 4fSC
Crystal oscillation ON/OFF
Phase detector
FSCI 9
FSCO 10 Open
XOSO 11
XOSI 12
4fSC VCC or GND 30 pF 5 to 30 pF
33
CHAPTER 2 BASIC OPERATION
2.2.2 Synchronization separation circuit When external video signal mode is selected, the synchronization separation circuit uses the fsc signal generated by the quadruple/4fsc crystal oscillation circuit to separate the horizontal synchronization signal (Hsync) and vertical synchronization signal (Vsync) from the composite synchronization signal (Csync). The vertical synchronization signal sampling circuit uses the fsc signal to sample Vsync from Csync by counting down when Csync is high and counting up when it is low. Also, the horizontal synchronization signal sampling circuit can prevent synchronization signals from being omitted or noise from being generated due to invalid signals because it contains an on-chip horizontal synchronization signal correction (Hsync autogeneration) circuit. When internal video signal mode is selected, Vsync and Hsync are generated by the synchronization signal generator by using the 4fsc signal generated by the quadruple/4fsc crystal oscillation circuit section. The operation of the horizontal synchronization signal correction (Hsync autogeneration) circuit is outlined below (see Figure 2-8 for sample timing charts). (1) Hsync width The PD6464A recognizes a signal of at least 0.2 sec as Hsync, and the PD6465 recognizes a signal of at least 0.8 sec. Signals having smaller widths are ignored. (2) Hsync cycle No external signal can be sampled for an interval of 61.2 sec after Hsync is sampled. (3) Hsync autogeneration The Hsync cycle is monitored, and if no external Hsync is input in a 61.2 to 64.5 sec interval after Hsync is sampled, a pseudo Hsync is autogenerated and output. The sampling of signals is not inhibited after the autogeneration of the pseudo Hsync. The external signal that is input next is treated as Hsync to accelerate the move back to the regular Hsync (If the sampling of signals were inhibited after the autogeneration of the pseudo Hsync, the auto-generation interval would continue, resulting in a loss of synchronization between the external Hsync and the Hsync used for display inside the OSD LSI). According to the operation described above, the pseudo Hsync is output even if no external Csync is input. However, no pseudo Vsync is autogenerated.
34
CHAPTER 2 BASIC OPERATION
Figure 2-7. Synchronization Separation Circuit Section
Composite synchronization signal positive synchronization input
Vertical synchronization signal negative synchronization input
Horizontal synchronization signal negative synchronization input
17 CSYIN
16 VSYO
15 HSYO To timing generator Hsync
Internal/external mode selection
Mode selection Vsync Vertical synchronization signal sampling circuit up/down counting circuit Vsync
Synchronization signal separation circuit section
Synchronization signal generator
Hsync
4fSC From quadruple/crystal fSC oscillation circuit
Horizontal synchronization signal sampling circuit counter, horizontal synchronization correction (autogeneration) circuit
Video signal mode selection
35
CHAPTER 2 BASIC OPERATION
Figure 2-8. Sample Horizontal Synchronization Signal Correction Circuit Timing Charts (1/3) (a) When regular signals are input Odd fields
3H Csync Input mask
4H
5H
6H
7H
8H
9H
10H
11H
12H
61.2 s (0) Hsync output Vsync output (0) (0) (1) (2) (3) (4) (5)
Even fields
266H (3) Csync Input mask
268H (5)
270H (7)
272H (9)
274H (11)
61.2 s (0) Hsync output Vsync output (0) (0) (1) (2) (3) (4) (5)
Remark The numbers enclosed in parentheses are vertical display counter values within the PD6464A or
PD6465.
36
CHAPTER 2 BASIC OPERATION
Figure 2-8. Sample Horizontal Synchronization Signal Correction Circuit Timing Charts (2/3) (b) Hsync autogeneration example Odd fields
3H Csync
Note 1
4H
5H
6H
7H
8H
9H
10H
11H
12H
Input mask 61.2 s (0) Hsync output
Note 2 Note 2
(0)
(0) (1)
(2)
(3)
(4) (5)
(6)
64.5 s Vsync output
Even fields
266H (3) Csync
268H (5)
270H (7)
Note 1
272H (9)
274H (11)
Input mask 61.2 s (0) Hsync output
Note 2 Note 2
(0)
(0) (1)
(2)
(3) (4)
(5)
(6)
Vsync output
64.5 s
Notes 1. Indicates that one pulse within the Csync signal is missing. 2. This is an autogenerated Hsync signal within the PD6464A or PD6465. Remark The numbers enclosed in parentheses are vertical display counter values within the PD6464A or
PD6465.
37
CHAPTER 2 BASIC OPERATION
Figure 2-8. Sample Horizontal Synchronization Signal Correction Circuit Timing Charts (3/3) (c) Change in Hsync output due to input mask after autogeneration When no masking is performed after autogeneration
Csync Input mask Hsync output Auto- Return generation
when masking is performed after autogeneration
Csync Input mask Hsync output AutoAutoAutogenera- genera- generation tion tion ......................
38
CHAPTER 2 BASIC OPERATION
2.2.3 Video signal output section The video signal output section mixes character information with a video signal input from an external source or with an internally generated video signal and outputs the mixed signal. With the PD6464A or PD6465, set the VCNT pin voltage to 2.5 V to use the internal/external video signal amplitude level at 1 Vp-p, and set the VCNT pin voltage to 5 V to use it at 2 Vp-p. In addition, the corresponding sync-chip level and pedestal level of the composite video signal input from an external source must match the internal video signal level (see Table 2-1). If the video signal amplitude level, sync-chip level, and pedestal level are not matched with the internal/external video signal, the character levels will differ in external video signal mode and internal video signal mode. For details about the adjustment method, refer to the data sheet. Figure 2-9. Video Signal Output Section Equivalent Circuit
VDD 5 k VCNT SW0
Note
SW2 NRE
100 pF VDD VDD
VBSI
VBSO
SW1 SECAM
Note
Set the VCNT pin voltage to 5 V when the internal video signal amplitude level is 2 Vp-p, and set the voltage to 2.5 V when the amplitude level is 1 Vp-p.
Remark The switch operations are as follows. SW0: Controlled by the output control section according to the character/background level, color burst/ color phase (for internal video signal mode), etc. SW1: This is ON when the SECAM method is set for the external video signal mode. SW2: This is ON during the video signal output interval when internal video signal mode is selected.
39
CHAPTER 2 BASIC OPERATION
Table 2-1. PD6464A or PD6465 Internal Video Signal Level
VCNT Pin Voltage Output Level Control Command Specifies 1 Vp-p Specifies 2 Vp-p Internal video Signal Amplitude Level 1 Vp-p 2 Vp-p Sync-Chip Level: VSYT 1V 1V Pedestal Level: VPED 1.29 V 1.58 V
2.5 V 5.0 V
Remark VDD = 5.0 V Figure 2-10. VSYT and VPED Levels of Composite Video Signal
VBSO VPED
VSYT GND
40
CHAPTER 2 BASIC OPERATION
2.3 Basic Operation of an RGB-System OSD LSI
This section describes the basic operation of the circuits of an RGB-system OSD LSI (PD6461, PD6462, or
PD6466).
2.3.1 Synchronization protection circuit An OSD LSI determines the vertical display start position of a character by counting rising edges of the horizontal synchronization signal (Hsync) from the rising edge of the vertical synchronization signal (Vsync). As shown in Figure 2-11 (a), when the Vsync and Hsync rising edges overlap and Vsync has jitter, the display start position is indefinite depending on whether or not the Hsync rising edge that overlaps Vsync is counted as the first Hsync after the Vsync rising edge. If a count error occurs, since the display start position shifts 1H, vertical jitter of the display character occurs (the character on the screen shifts in 1H units; see Figure 2-11 (c)). The synchronization protection circuit eliminates Hsync counting errors by autogenerating a pseudo Hsync signal internally so that no vertical jitter of the display character is caused by a shift of the display starting position. This circuit sets certain areas (areas A, B, C, and DNote in Figures 2-12 to 2-15) according to the character dot clock after the Hsync rising edge and generates a pseudo Hsync signal to prevent vertical jitter corresponding to the Hsync and Vsync signals input within their range. By counting the pseudo Hsync signal, display output is performed with no vertical jitter (the circuit operates so that the Hsync and Vsync status is always kept fixed). Note The area widths in the PD6461, PD6462, or PD6466 are as follows. Area A width: Hsync width + 12/fosc (PD6461 or PD6462) With the PD6466, the area A width is as follows according to the horizontal display start position. Hsync width + 7/fosc (horizontal display start position = 28 + 12n: n = 0,1,2,...) Hsync width + 10/fosc (horizontal display start position = 25 + 12n: n = 0,1,2,...) Hsync width + 13/fosc (horizontal display start position = 22 + 12n: n = 0,1,2,...) Hsync width + 16/fosc (horizontal display start position = 31 + 12n: n = 0,1,2,...) Area B width: 48/fosc Area C width: 12/fosc Area D width: Other than areas A, B, and C fosc: Dot clock frequency The synchronization protection circuit operates as described below.
41
CHAPTER 2 BASIC OPERATION
Figure 2-11. Display Character Vertical Jitter Generation Mechanism (a) Relationship between Hsync and Vsync when vertical jitter occurs
Display character vertical jitter occurs according to whether or not this Hsync signal is counted as the first Hsync signal due to Vsync vibration. 1 Hsync 1' 2' 2 3
Count number when a counting omission occurred Vsync Vsync shift
(b) Character pattern
(c) Display character vertical jitter generation model (when the count error occurs at the first of an odd field)
Vsync 1 Hsync Odd field line No. 1 2 3 4 5 6 7 8 9 Even field line No. 264 265 266 267 268 269 270 271 2 3
Vsync 1 Hsync Odd field line No. 1 2 3 4 5 6 7 8 9 Even field line No. 264 265 266 267 268 269 270 271 2

Occurrence of display character vertical jitter

: Odd field display character : Even field display character
Remark If Vsync shifts in the vicinity of the Hsync rising edge, display character vertical jitter occurs according to whether or not the first Hsync signal of the odd fields is counted as the first signal.
42
CHAPTER 2 BASIC OPERATION
(1) Mode 1 Figure 2-12. Synchronization Protection Circuit Operation (Mode 1)
D' Vsync 1
A
B
C
D
Hsync
Pseudo Hsync 1'Note
Note
This is output only when a pseudo Hsync signal has been output by the previous field.
If the Vsync rising edge is input before the Hsync rising edge (area D'), the count begins with the Hsync(1) rising edge. However, if a pseudo Hsync signal has been output by the previous field, the pseudo Hsync (1') signal is also output by the current field in area C. The count begins with this pseudo Hsync (1') rising edge, and then subsequent Hsync signals are counted. (2) Mode 2 Figure 2-13. Synchronization Protection Circuit Operation (Mode 2)
D' Vsync 1
A
B
C
D
Hsync
Pseudo Hsync 1'
If a Vsync signal is input in the period (area A) determined by the Hsync Low period and a certain number of dot clocks from Hsync rising edge, a pseudo Hsync (1') signal is output within the internal circuitry of the OSD LSI in area C, the count begins with this rising edge, and then subsequent Hsync signals are counted.
43
CHAPTER 2 BASIC OPERATION
(3) Mode 3 Figure 2-14. Synchronization Protection Circuit Operation (Mode 3)
D' Vsync 1
A
B
C
D
Hsync
Pseudo Hsync 1'Note
Note
This is output only when a pseudo Hsync signal has been output by the previous field.
When the Vsync rising edge is input in area B, if a pseudo Hsync signal has been output by the previous field, the pseudo Hsync(1') signal is also output by this field in area C. The count begins with this pseudo Hsync (1') rising edge, and then subsequent Hsync signals are counted. However, if a pseudo Hsync signal has not been output by the previous field, no pseudo Hsync signal is output by this field, and the count begins with the next Hsync rising edge that was input. (4) Mode 4 Figure 2-15. Synchronization Protection Circuit Operation (Mode 4)
D' Vsync
A
B
C
D
1Note 1 Hsync
Pseudo Hsync 1'Note 2
Notes 1. This is not counted. The count begins with the next Hsync. 2. No pseudo Hsync signal is output regardless of the status in the previous field. When the Vsync rising edge is input in area C, the pseudo Hsync(1') signal is not output regardless of the status in the previous field, and the count begins with the Hsync rising edge that was input next.
44
CHAPTER 2 BASIC OPERATION
Figure 2-16. Display Character Vertical Jitter Prevention Mechanism (a) Character pattern
(b) Display character vertical jitter prevention model (when the Vsync shift occurs at the first of an odd field)
Vsync 1 Hsync Pseudo Hsync 2 3
Vsync 2 Hsync 1 Pseudo Hsync 3
Odd field line No. 1 2 3 4 5 6 7 8 9
Even field line No. 264 265 266 267 268 269 270 271

Odd field line No. 1 2 3 4 5 6 7 8 9
Even field line No. 264 265 266 267 268 269 270 271
Prevention of display character vertical jitter

: Odd field display character : Even field display character
Remark Even if Vsync shifts in the vicinity of the Hsync rising edge, the pseudo Hsync signal is generated by the action of the synchronization protection circuit, and no display character vertical jitter occurs. 2.3.2 R, G, B, and BLK outputs when RGB + VC1 + VC2 is selected Figure 2-17 shows the relationships among the R, G, B, and BLK outputs when the mask option (for the PD6461 or PD6462) or initialization command (for the PD6466) is used to set the output pins to RGB + VC1 + VC2 mode.
45
CHAPTER 2 BASIC OPERATION
Figure 2-17. Output Pins: Sample R, G, B, and BLK Output Images When RGB + VC1 + VC2 Is Selected
No framing, no background
With framing, no background
No framing, with background
With framing, with background White character Black framing Red background
White character
White character Black framing
White character Red background
VR VG VB VBLK
VR VG VB VBLK
VR VG VB VBLK
VR VG VB VBLK
No framing, no background
With framing, no background
No framing, with background
With framing, with background Red character White framing Red background
Red character
Red character Black framing
Red character Red background
VR VG VB VBLK
VR VG VB VBLK
VR VG VB VBLK
VR VG VB VBLK
No framing, no background
With framing, no background
No framing, with background
With framing, with background Black character White framing Blue background
Black character
Black character White framing
Blue character Blue background
VR VG VB VBLK
VR VG VB VBLK
VR VG VB VBLK
VR VG VB VBLK
Remark The waveform of each output pin represents the output on the dashed line (horizontal) in the middle of the character.
46
CHAPTER 2 BASIC OPERATION
2.3.3 R, G, B, and BLK outputs when RGB + blanking corresponding to RGB (3BLK) is selected Figure 2-18 shows the relationships among the R, G, B, and BLK outputs when the mask option (for the PD6461 or PD6462) or initialization command (for the PD6466) is used to set the output pins to RGB + 3BLK mode. Figure 2-18. Sample R, G, B, and BLK Output Images When RGB + 3BLK Is Selected
No framing, with background With framing, with background
R G
,, ,, ,, , ,
,, ,, ,, ,,,
R
G
,, ,, ,, ,,
R B R R+G B
Red character: I Green character: J Background: Blue
B
B
Red character: I Green character: J Background: Blue Black framing
With framing, with background
G
Red character: I Green character: J Background: Blue White framing
,, , , ,, ,, , ,,
,,, ,, , , ,, ,, , ,,
H H
,,, ,, , , ,, ,, , ,,
VR RBLK VG GBLK VB BBLK VC1 BLK1
VR RBLK VG GBLK VB BBLK VC1 BLK1
H
VR RBLK VG GBLK VB BBLK VC1 BLK1
H H
No framing, with background
,, ,,,,, ,
,,,,,, ,,,
R
G
R
G
,,,,,, ,,
Red character: I Green character: J Background: Yellow
With framing, with background
R+G
R+G
Red character: I Green character: J Background: Yellow Black framing
With framing, with background
G
Red character: I Green character: J Background: Yellow White framing
,, , , ,,,,, ,,
,, ,, , , ,,,,, ,,
L L H H
B
,, ,, , , ,,,,, ,,
VR RBLK VG GBLK VB BBLK VC1 BLK1
VR RBLK VG GBLK VB BBLK VC1 BLK1
L L H
VR RBLK VG GBLK VB BBLK VC1 BLK1
L H H
No framing, with background
Black character: I White character: J Background: Blue
With framing, with background
B
Black character: I White character: J Background: Blue Black framing
With framing, with background
Black character: I White character: J Background: Blue White framing
VR RBLK VG GBLK VB BBLK VC1 BLK1
H H
VR RBLK VG GBLK VB BBLK VC1 BLK1
H H
VR RBLK VG GBLK VB BBLK VC1 BLK1
H H
Remarks 1. 2.
The waveform of each output pin represents the output on the dashed line (horizontal) in the middle of the character. VC1 is the logical sum of VR, VG, and VB, and BLK1 is the logical sum of RBLK, GBLK, and BBLK.
47
CHAPTER 2 BASIC OPERATION
To provide the same image data to two screens and simultaneously display different characters for each of them (such as displaying only red characters on the viewfinder in a camcorder and transcribing only green characters onto the video tape), use blanking signals corresponding to RGB as shown in Figure 2-19 (a). By using blanking signals corresponding to RGB even when white framing is set, you can display only single-color characters. However, the colors of the character portion and framing portion are identical as shown in Figure 2-19 (b). Figure 2-19. Sample Use of Blanking Signals Corresponding to RGB (a) When no framing is set
No framing, with background (use BLK1)
R
G
,,,,, ,,,,,
R
,, ,,,,,
Red character: I Green character: J Background: Blue
Display only red character (use RBLK)
Display only green character (use GBLK)
,,,,,, ,,,,,, ,,
,,, ,,,,,, ,,,
B
G
VR RBLK VG GBLK VB BBLK VC1 BLK1
VR RBLK VG GBLK
H H
(b) When white framing is set
With framing, with background (use BLK1)
R
G
,, ,,,,, ,, , ,
R
,, ,,,,, ,
B
Red character: I Green character: J Background: Blue White framing
Display only red character (use RBLK)
Display only green character (use GBLK)
G
,,,,,,, ,,,,,,, ,,,
,,, ,,,,,, ,,,
H H
VR RBLK VG GBLK VB BBLK VC1 BLK1
VR RBLK
VG GBLK
48
CHAPTER 2 BASIC OPERATION
2.4 Characters
2.4.1 Character display An OSD LSI displays the character generator ROM contents in a 12-line by 24-column display area. Figure 2-20 shows an image of the display area. Figure 2-20. Character Display (a) Character position control
Horizontal synchronization signal (Hsync)
A
B
Display area (12 lines x 24 columns)
Vertical synchronization signal (Vsync)
Remark The horizontal display start position (A) and vertical display start position (B) are controlled by the character position control command. (b) Sample display image when interlace is used (when A = 3H is set)
Odd field line No. 1 2 3 4 5 6 7 8 9
Even field line No. 264 265 266 267 268 269 270 271
Character pattern

: Odd field display character : Even field display character
49
CHAPTER 2 BASIC OPERATION
2.4.2 Character patterns Characters can be designed by using a character pattern editor (for details, see CHAPTER 5 DEVELOPMENT TOOLS) that can be rented from NEC. For inquiries related to character pattern editor rental, contact an NEC distributor or NEC sales representative. For information about the character patterns of NEC standard products, refer to the data sheet of each product.
2.5 Commands
2.5.1 Command format OSD LSI control commands are of variable word length in 8-bit units and are input in serial. Three types of commands are available: 1-byte commands consisting of 8 bits for the instruction and data combined, 2-byte commands, and 2-byte contiguous commands that enable abbreviated input to be performed. Table 2-2 shows the command data transfer format of each product. Table 2-2. Command Data Transfer Format
Product Name Video-system RGB-system Command Data Transfer Format MSB first MSB first or LSB first can be selected by using mask option MSB first or LSB first can be selected by using CMDCT pin
PD6464A, 6465 PD6461, 6462 PD6466
50
CHAPTER 2 BASIC OPERATION
2.5.2 Command list This section introduces the command tables of each product. For details about commands, refer to the data sheet of each product. Table 2-3. PD6464A or PD6465 Command Tables 1-byte commands
Function Video RAM batch clear Display control Internal video signal color control Background control Internal/external mode control, crystal oscillation control Video signal method control Oscillation method control (MSB) D7 0 0 0 0 0 0 0 D6 0 0 0 0 1 1 1 D5 0 0 1 1 0 0 0 D4 0 1 0 1 0 0 1 D3 0 D0 R 0 0 1 0 D2 0 LC G BS1 E/I D1 0 BL1 B BS0 0 D0 0 BL0 0 0 XOSC
N/P2 N/P1 N/P0 0 XfC 0
2-byte commands
Function Display position control Write address control Output level control Character size control Test modeNote
(MSB) D15 D14 D13 D12 D11 D10 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 0 1 1 1 0 1 0 1 0 0 0 0 0 0 D9 V4 0 0 0 0 D8 V3 D7 V2 D6 V1 D5 V0 D4 H4 D3 H3 D2 H2 D1 H1 D0 H0
AR3 AR2 AR1 AR0 AC4 AC3 AC2 AC1 AC0 VPD 0 0 0 0 T7 0 S0 T6 0 0 T5 0 0 T4 0 1 VC1 VC0
AR3 AR2 AR1 AR0 T3 T2 T1 T0
Note Cannot be used
2-byte contiguous command (MSB)
Function Display character control D15 D14 D13 D12 D11 D10 1 1 0 0 0 0 D9 BL D8 0 D7 C7Note D6 C6 D5 C5 D4 C4 D3 C3 D2 C2 D1 C1 D0 C0
Note
Fixed to "0" (PD6464A)
51
CHAPTER 2 BASIC OPERATION
Table 2-4. PD6461 or PD6462 Command Tables (MSB First) 1-byte commands
Function Video RAM batch clear Character display control Background color/framing color control 3-system independent display ON/OFF Character inversion ON/OFF (MSB) D7 0 0 0 0 0 D6 0 0 0 1 0 D5 0 0 1 1 1 D4 0 1 0 1 1 D3 0 DO R 0 1 D2 0 LC G DOA 0 D1 0 BL1 B DOB 0 D0 0 BL0 BFC DOC BCRE
2-byte commands
Function Character display position control Write address control Output pin control Character size control 3-system background control Test modeNote
(MSB) D15 D14 D13 D12 D11 D10 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 1 1 0 1 1 1 0 0 0 0 1 0 0 0 D9 V4 0 0 0 1 0 D8 V3 D7 V2 D6 V1 D5 V0 D4 H4 D3 H3 D2 H2 D1 H1 D0 H0
AR3 AR2 AR1 AR0 AC4 AC3 AC2 AC1 AC0 0 0 VC2 0 VC1 S 0 0 0 0 AR3 AR2 AR1 AR0 AR3 AR2 AR1 AR0
BA1 BA0 BFA BB1 BB0 BFB BC1 BC0 BFC T8 T7 T6 T5 T4 T3 T2 T1 T0
Note
Cannot be used
2-byte contiguous command (MSB)
Function Display character control D15 D14 D13 D12 D11 D10 1 1 RV R G B D9 BL D8 VC2 D7 C7Note D6 C6 D5 C5 D4 C4 D3 C3 D2 C2 D1 C1 D0 C0
Note
With the PD6462, character bit 7 is fixed to "Don't care."
52
CHAPTER 2 BASIC OPERATION
Table 2-5. PD6461 or PD6462 Command Tables (LSB First) 1-byte commands
Function Video RAM batch clear Character display control Background color/framing color control 3-system independent display ON/OFF Character inversion ON/OFF (LSB) D0 0 BL0 BFC DOC BCRE D1 0 BL1 B DOB 0 D2 0 LC G DOA 0 D3 0 DO R 0 1 D4 0 1 0 1 1 D5 0 0 1 1 1 D6 0 0 0 1 0 D7 0 0 0 0 0
2-byte commands
Function Character display position control Write address control Output pin control Character size control 3-system background control Test modeNote
(LSB) D0 V3 AR3 0 0 BA1 T8 D1 V4 0 0 0 1 0 D2 0 0 1 0 0 0 D3 0 1 1 1 0 0 D4 0 0 1 1 1 1 D5 0 0 0 0 1 1 D6 0 0 0 0 0 0 D7 1 1 1 1 1 1 D8 H0 D9 H1 D10 D11 D12 D13 D14 D15 H2 H3 H4 V0 V1 V2
AC0 AC1 AC2 AC3 AC4 AR0 AR1 AR2 AR0 AR1 AR2 AR3 AR0 AR1 AR2 AR3 0 0 0 0 VC1 S VC2 0
BFC BC0 BC1 BFB BB0 BB1 BFA BA0 T0 T1 T2 T3 T4 T5 T6 T7
Note
Cannot be used
2-byte contiguous command (LSB)
Function Display character control D0 VC2 D1 BL D2 B D3 G D4 R D5 RV D6 1 D7 1 D8 C0 D9 C1 D10 D11 D12 D13 D14 D15 C2 C3 C4 C5 C6 C7Note
Note
With the PD6462, character bit 7 is fixed to "Don't care."
53
CHAPTER 2 BASIC OPERATION
Table 2-6. PD6466 Command Tables (MSB First) 1-byte commands
Function Video RAM batch clear Display control Background color/framing color control 3-system independent display ON/OFF Character color inversion ON/OFF Blue back ON/OFF Character address bank switching Output switch control (MSB) D7 0 0 0 0 0 0 0 0 D6 0 0 0 1 1 1 1 1 D5 0 0 1 1 1 1 1 0 D4 0 1 0 1 1 1 1 S3A D3 0 DO R 0 1 1 1 S3B D2 0 LC G DOA 0 CLR 1 SW4 D1 0 BL1 B DOB 0 0 1 SW2 D0 0 BL0 BFC DOC BCRE BB BC SW1
2-byte commands
Function Character display position control Write address control Output pin control Character size control 3-system background control Initial settings Test modeNote
(MSB) D15 D14 D13 D12 D11 D10 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 1 1 1 1 0 1 1 1 0 0 0 0 0 1 0 0 1 0 D9 V4 0 0 D8 V3 D7 V2 D6 V1 D5 V0 D4 H4 D3 H3 D2 H2 D1 H1 D0 H0
AR3 AR2 AR1 AR0 AC4 AC3 AC2 AC1 AC0 0 OD1 OD0 0 0 0 0 AR3 AR2 AR1 AR0 AR3 AR2 AR1 AR0
SV1 SV0 SH1 SH0 1 0 0
BA1 BA0 BFA BB1 BB0 BFB BC1 BC0 BFC 0 0 0 T7 BR T6 RS OP1 OP0 COC VST OSC T5 T4 T3 T2 T1 T0
Note
Cannot be used
2-byte contiguous command (MSB)
Function Display character control D15 D14 D13 D12 D11 D10 1 1 RV R G B D9 BL D8 VC2 D7 C7 D6 C6 D5 C5 D4 C4 D3 C3 D2 C2 D1 C1 D0 C0
54
CHAPTER 2 BASIC OPERATION
Table 2-7. PD6466 Command Tables (LSB First) 1-byte commands
Function Video RAM batch clear Display control Background color/framing color control 3-system independent display ON/OFF Character color inversion ON/OFF Blue back ON/OFF Character address bank switching Output switch control (LSB) D0 0 BL0 BFC DOC BCRE BB BC SW1 D1 0 BL1 B DOB 0 0 1 SW2 D2 0 LC G DOA 0 CLR 1 SW4 D3 0 DO R 0 1 1 1 S3B D4 0 1 0 1 1 1 1 S3A D5 0 0 1 1 1 1 1 0 D6 0 0 0 1 0 1 1 1 D7 0 0 0 0 0 0 0 0
2-byte commands
Function Character display position control Write address control Output pin control Character size control 3-system background control Initial settings Test modeNote
(LSB) D0 V3 AR3 0 D1 V4 0 0 D2 0 0 1 0 0 1 0 D3 0 1 1 1 0 0 0 D4 0 0 1 1 1 1 1 D5 0 0 0 0 1 1 1 D6 0 0 0 0 0 0 0 D7 1 1 1 1 1 1 1 D8 H0 D9 H1 D10 D11 D12 D13 D14 D15 H2 H3 H4 V0 V1 V2
AC0 AC1 AC2 AC3 AC4 AR0 AR1 AR2 AR0 AR1 AR2 AR3 AR0 AR1 AR2 AR3 0 0 0 0 OD0 OD1 SH0 SH1
SV0 SV1 BA1 0 0 1 0 0
BFC BC0 BC1 BFB BB0 BB1 BFA BA0 OSC VST COC OP0 OP1 RS T0 T1 T2 T3 T4 T5 BR T6 0 T7
Note
Cannot be used
2-byte contiguous command (LSB)
Function Display character control D0 VC2 D1 BL D2 B D3 G D4 R D5 RV D6 1 D7 1 D8 C0 D9 C1 D10 D11 D12 D13 D14 D15 C2 C3 C4 C5 C6 C7
55
CHAPTER 2 BASIC OPERATION
2.6 OSD LSI Power-ON Initialization
Because the internal status of the OSD LSI is indefinite on power application, initialize the OSD LSI by making the PCL pin low for a fixed interval and executing a power-ON clear operation. When the power-ON clear operation has been performed, the various control register settings are as follows. * Test mode is cleared. * All character data of the video RAM (12 lines by 24 columns) are set to Display Off Data. * Blinking data are set to OFF. * Video RAM write address is set to line 0, column 0. * Character size is set to x1 (standard size) on all lines. * Display is set to OFF, and LC oscillation is set to ON. * The line specification set by output pin control is cleared (PD6461, PD6462, or PD6466). * Initial defaults are set (PD6466). * Display ON/OFF setting of each output system is set to OFF (PD6466). * No background and no framing are set for all 3 systems (PD6466). * Blue back is set to OFF (PD6466). * Character address bank is set to the low-order (0) bank (PD6466). The time required for the power-ON clear operation can be calculated by using the following expression. t (time required for power-ON clear) = tPCLL + {video RAM clear time} = 10 (s MIN.) + {10 (s) + 12/fosc (MHz) x 288 [s]} fosc (MHz): LC oscillation frequency or external clock frequency Remarks 1. 2. 3. Do not input a command during execution of the power-ON clear operation. A dot clock is required to clear video RAM. When external clock input is selected, input a dot clock from the OSCIN pin before executing the power-ON clear or video RAM batch clear operation. The power-ON clear operation, which is a hardware reset due to a signal input to the PCL pin, performs initialization that includes video RAM clear and test mode clear operations. In contrast, the video RAM batch clear operation, which is a software reset that performs initialization according to a command (software), does not execute a test mode clear operation.
56
CHAPTER 3 APPLICATION EXAMPLES
3.1 Video-System OSD LSI Application Examples
3.1.1 Sample PD6464A or PD6465 application circuits
57
CHAPTER 3 APPLICATION EXAMPLES
Figure 3-1. Sample PD6464A or PD6465 Application Circuit (When Quadruple Oscillation Is Selected)
5.1 k
VCC = 5 V
2.2 k
Video-IN 10 F 2 Vp-p
+
1.2 k
100 k
VCC = 5 V
1 CLK 2 CS 3 DATA
1 2 3 4
CLK CS DATA VDD OSCOUT OSCIN PCL GND FSCI FSCO XOSO
VBSI VCNT SECAM VBSO NRE TEST N.C. CSYIN VSYO HSYO VBLK VC
24 23 22
VCC = 5 V
2.2 k Video OUT
VDD = 5 V + 10 F
10 H 21 100 pF 5 39 H 6 5 to 30 pF + 300 mVp-p (min) 10 F 8 17 16 15 14 13 7 20 19 18 0.01 F
100 pF
2 Vp-p
30 pF
Csync
fSC input 2200 pF + 1F VD 1.5 k
0.01 F 5.1 k 100 k 1000 pF
9 10 11
18 pF
4.7 H 12 XOSI
47 pF NTSC, PAL-M: H PAL, SECAM: L 20 k 20 k
Cautions 1. The clamp circuit is not necessary when the sync-chip level (1 V DC) can be directly input to pin 24. 2. Pin 20 is connected so as to reject unwanted radiation. 3. This application circuit is assumed to input 2-Vp-p video signals. 4. A product equivalent to 1SV163 can be used as a VD (varactor diode).
58
CHAPTER 3 APPLICATION EXAMPLES
Figure 3-2. Sample PD6464A or PD6465 Application Circuit (When 4fsc Crystal Oscillation Is Selected)
5.1 k
VCC = 5 V
2.2 k
Video-IN 10 F 2 Vp-p
+
1.2 k
100 k
VCC = 5 V
1 CLK 2 CS 3 DATA
1 2 3 4
CLK CS DATA VDD OSCOUT OSCIN PCL GND FSCI FSCO XOSO XOSI
VBSI VCNT SECAM VBSO NRE TEST N.C. CSYIN VSYO HSYO VBLK VC
24 23 22
VCC = 5 V
2.2 k Video OUT
VDD = 5 V + 10 F
10 H 21 100 pF 5 39 H 6 7 8 VCC or GND Open 30 pF 11 4fSC 5 to 30 pF 12 13 14 9 10 20 19 18 17 16 15 0.01 F
100 pF
2 Vp-p
30 pF
5 to 30 pF + 10 F
Csync
Cautions 1. The clamp circuit is not necessary when the sync-chip level (1 V DC) can be directly input to pin 24. 2. Pin 20 is connected so as to reject unwanted radiation. 3. This application circuit is assumed to input 2-Vp-p video signals. 4. Connect pin 9 to GND or VCC (it cannot be left open). Leave pin 10 open.
59
CHAPTER 3 APPLICATION EXAMPLES
3.1.2 Composite synchronization signal (Csync) separation circuit Figure 3-3. Composite synchronization signal separation circuit (a) Sample composite synchronization signal separation circuit
VDD = 5 R6 c R1 Composite video signal (2 Vp-p) C1 + R2 a b Q1 C2 + IX R5 R8 R9 R3 VC Isp R4 Q2 0.3 VDD (MAX.) Input to pin 17 of the PD6464A or PD6465 C3 R7 Composite synchronization signal (positive synchronization) Q3 0.7 VDD (MIN.)
R1 = 5.1 k, R2 = 1.2 k, R3 = 1 k, R4 = 220 , R5 = 100 k, R6 = 10 k, R7 = 1 k, R8 = 2.2 k, R9 = 10 k, C1 = 10 F, C2 = 1 F, C3 = 1000 pF (b) Composite signal separation waveform image
T1 4.7 s
T2 58.86 s
VC
VC VC1 VC2 VC3
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CHAPTER 3 APPLICATION EXAMPLES
The operation of the circuit shown in Figure 3-3 and the method of determining the slice level are described below. The voltages at points a, b, and c in Figure 3-3 (a) are given as follows. a = VL, b = VL + VC, c = VH Remark VL: Sync-chip voltage at point a VH: Threshold voltage of Q2 Let R5 >> R4 and let C2 be sufficiently large. Then from the relationship V = capacitor is charged and discharged are as follows. VH - (VL + VC1) R4 VL + VC2 R5 1 C2 1 idt, the values of VC when the c
When charged: VC =
x T1 x
When discharged: VC =
x T2 x
1 C2
VC is stabilized at a location where the values of VC when the capacitor is charged and discharged are the same (let the average voltage of VC = VC3). From a macro viewpoint, the synchronization base is clamped at VC3, and the comparison is performed at the Q2 threshold voltage (VH). Therefore, the slice level VS is as follows. VS = VH - (VC3 + VL) Letting the values of VC be equal here (VC1 VC2 VC1) gives the following equation. VH - (VL + VC1) R4 x T1 = VL + VC2 R5 x T2
Substituting VS = VH - (VL + VC3) and eliminating common terms gives the following equation. 1 R4 1 R4 T2 R5T1 T2 R5T1 VH R5 T2 T1
VS
+
=
x
Letting
>>
here gives the following equation.
VS = VH x
R4 R5
x
T2 T1
In Figure 3-3, since VH = 2.7 V, R4 = 220 , R5 = 100 k, since T1 = 4.7 s and T2 = 58.86 s, the slice level VS is as follows. 220 100000 58.86 4.7
VS = 2.7 x
x
74 mV
61
CHAPTER 3 APPLICATION EXAMPLES
Making VS small is advantageous for horizontal synchronization separation, but disadvantageous for vertical synchronization separation. Conversely, making VS large causes synchronization aberrations (jitter) due to noise in horizontal synchronization separation. Therefore, the constants must be optimized depending on the signal that is input. Although a sufficiently large value is selected for the C2 capacitance value compared with the charge/discharge current, if it is set too large, the transient response characteristic worsens, and it will not be able to follow a sudden APL fluctuation of the input signal. In the circuit shown in Figure 3-3 (a), the input is set to a capacitor combination to simplify measurement. As a result, it is weak relative to APL fluctuation. Therefore, when the circuit is actually configured, using a sync-chip clamp circuit to establish the electric potential of the leading edge of synchronization before inputting it to Q1 in Figure 33 (a) makes it strong relative to APL fluctuation. Caution With the circuit shown in Figure 3-3, the Hsync synchronization signal width after composite synchronization signal separation may be large compared with the input signal due to the circuit configuration. As a result, when calculating the command continuous input enable times according to the formulas shown in the Data Sheet for each product, the Hsync synchronization signal width after composite synchronization signal separation in the circuit shown in Figure 3-3 must be used for the Hsync synchronization signal width (tHWL1 or tHWL2).
62
CHAPTER 3 APPLICATION EXAMPLES
3.1.3 Sample application for separate video signal input Figure 3-4. Sample Application Circuit for Separate Video Signal Input (a) Sample application circuit (b) Pin waveform models
PD6464A, 6465 VBSI
VBSO
24
Clamp circuit
Y: Brightness signal Y + VC + VBLK
Y C
21
CSYIN 17
Composite synchronization signal separation circuit
VC
Chrominance and VBLK signal mixing circuit
VBLK VC 14 13
C + VBLK
VBLK
Y + VC + VBLK
C: Chrominance signal
C + VBLK
63
CHAPTER 3 APPLICATION EXAMPLES
3.1.4 Sample application for NTSC direct mode For NTSC mode, using the command shown in Table 3-1 sets and clears NTSC direct mode. When NTSC direct mode is used, the IC can be used only with fsc input. When NTSC direct mode is not used (or is cleared), the IC is in normal mode (quadruple/crystal oscillation). Figure 3-5 shows a sample application circuit when this command is used. The usage method shown here is a reference example only and is not recommended by NEC. Table 3-1. NTSC Direct Mode Setting Command
D15 1
D14 0
D13 1
D12 1
D11 0
D10 0
D9 0
D8 0
D7 1
D6 1
D5 1
D4 1
D3 DI1
D2 DI0
D1 0
D0 0
NTSC direct mode control bits DI1 0 1 0 1 DI0 0 1 1 0 Function Clear NTSC direct mode Set NTSC direct mode Setting prohibited (invalid operation will occur)
Caution Note the following when setting NTSC direct mode. 1. Set the fsc input amplitude to 500 mVp-p (MIN.). 2. Set the crystal oscillation command to oscillation OFF. 3. Set the video signal method control command to NTSC. 4. The internal video signal colors are the three colors; white, black, and blue (green cannot be displayed).
64
CHAPTER 3 APPLICATION EXAMPLES
Figure 3-5. Sample Application Circuit for NTSC Direct Mode
5.1 k
VCC = 5 V
2.2 k
Video-IN 10 F 2 Vp-p
+
1.2 k
100 k
VCC = 5 V
1 CLK 2 CS 3 DATA
1 2 3 4
CLK CS DATA VDD OSCOUT OSCIN PCL GND FSCI FSCO XOSO XOSI
VBSI VCNT SECAM VBSO NRE TEST N.C. CSYIN VSYO HSYO VBLK VC
24 23 22 21
VCC = 5 V
2.2 k Video OUT
VDD = 5 V +
2 Vp-p
10 F 0.01 F
30 pF
100 pF 5 39 H 6 7 8 20 19 18 17 16 15 14 13 Csync
5 to 30 pF + 500 mVp-p (min) fSC input 0.01 F 10 F
9 10 11 12
Cautions 1. The clamp circuit is not necessary when the sync-chip level (1 V DC) can be directly input to pin 24. 2. Pin 20 is connected so as to reject unwanted radiation. 3. This application circuit is assumed to input 2-Vp-p video signals. 4. To set NTSC direct mode, the NTSC direct mode control command must be input. 5. For the internal video signal color, select from the three colors; white, black, and blue (green cannot be displayed). 6. Input an fsc signal having an amplitude of at least 500 mVp-p to pin 9.
65
CHAPTER 3 APPLICATION EXAMPLES
3.2 RGB-System OSD LSI Application Examples
3.2.1 Sample PD6461A or PD6462 application circuit Figure 3-6. Sample PD6461 or PD6462 Application Circuit
PD6461GS/GT, 6462GS
Connect to microcontroller 1 (1) 2 (2) 10 F 3 (4) 4 (5) 5 (6) 6 (7) Note 2 LC module pin number <1> 7 (8)Note 3 CLK CS DATA PCL VDD CKOUT OSCOUT OSCIN TEST GND Hsync Vsync VB VG VR VBLK (BBLK)Note 4 VC2 (GBLK)Note 4 BLK2 (RBLK)Note 4 VC1 BLK1 20 (24) 19 (23) 18 (21) 17 (20) 16 (19) 15 (18) 14 (17) 13 (16) 12 (15) 11 (14) Input Hsync and Vsync using negative synchronization Output
VDD
Note 1 + 100 k
10 F +
0.01 F
LC module Note 3 33 H pin number <3> 8 (9) 5 to 30 pF 30 pF 10 (11) 9 (10)
Notes 1. Set the CR constant so that the power-ON clear standards are satisfied. 2. This circuit enables the number of external components to be reduced and the oscillation frequency to be easily adjusted by using an LC module manufactured by Toukou Co., Ltd. (Part No.: Q285NCIS11181). 3. Set the following when using external clock input. OSCIN pin: External clock input, OSCOUT pin: Open 4. The symbols enclosed in parentheses are set by the mask code option (RGB + Blanking corresponding to RGB). Remarks 1. 2. The numbers enclosed in parentheses are the pin numbers for the PD6461GT-xxx. With the PD6461GT-xxx, the effect of noise through the lead frame can be reduced by connecting the N.C. pins (pin numbers 3, 12, 13, and 22) to GND.
66
CHAPTER 3 APPLICATION EXAMPLES
3.2.2 Sample PD6466 application circuit Figure 3-7. Sample PD6466 application circuit
PD6466GS/GT
Connect to microcontroller 1 (1) 2 (2) 10 F 3 (4) 4 (5) 5 (6) 6 (7) Note 2 VDD MSB first LSB first Note 5 LC module pin number <1> 7(8)Note 3 CLK CS DATA PCL VDD CMDCT OSCOUT OSCIN TEST GND Hsync Vsync VB VG VR VBLK (BBLK)Note 4 VC2 (GBLK)Note 4 BLK2 (RBLK)Note 4 VC1 BLK1 20 (24) 19 (23) 18 (21) 17 (20) 16 (19) 15 (18) 14 (17) 13 (16) 12 (15) 11 (14) Input Hsync and Vsync using negative synchronization Output
VDD
Note 1 + 100 k
10 F +
0.01 F
LC module Note 3 33 H pin number <3> 8(9) 5 to 30 pF 30 pF 10 (11) 9 (10)
Notes 1. Set the CR constant so that the power-ON clear standards are satisfied. 2. This circuit enables the number of external components to be reduced and the oscillation frequency to be easily adjusted by using an LC module manufactured by Toukou Co., Ltd. (Part No.: Q285NCIS11181). 3. Set the following when using external clock input. OSCIN pin: External clock input, OSCOUT pin: Open 4. The symbols enclosed in parentheses are set by the initialization command (RGB + Blanking corresponding to RGB). 5. When this is open, LSB first is used. Remarks 1. 2. The numbers enclosed in parentheses are the pin numbers for the PD6466GT-xxx. With the PD6466GT-xxx, the effect of noise through the lead frame can be reduced by connecting the N.C. pins (pin numbers 3, 12, 13, and 22) to GND.
67
CHAPTER 3 APPLICATION EXAMPLES
3.3 External Clock Forced Input to LC Oscillation Circuit Section
The external clock input conditions shown in this section are given as a reference example only and are not recommended by NEC. This is a reference example for using the PD6461 or PD6462 with LC oscillation specified by the mask option or for using the PD6464A or PD6465. For external clock input conditions when external clock input is selected for the PD6461 or PD6462 mask option or when using the PD6466, refer to the data sheet of each product. Since an LC oscillation circuit is used to generate dot clocks in an OSD LSI (with an RGB-system OSD LSI, external clock input can be selected), to forcibly input an external clock, you must make the timing similar to when LC oscillation is used (oscillation stopped during Hsync period). Figure 3-8 shows the timing chart when an external clock is forcibly input. Figure 3-8. Timing Chart for External Clock Forced Input
Hsync
Dot clocks
A
4 clocks
A
Cautions The following restrictions apply when an external clock is used. 1. An interval of period A plus several clocks (4 clocks for the minimum character size) from the Hsync falling edge is required to stop the dot clocks. Typical period A values for each product are as follows.
PD6461, PD6462, PD6464A : 200 ns (TYP.) PD6465
: 500 ns (TYP.) The number of clocks, excluding period A, from the Hsync falling edge until the dot clocks are stopped depends on the character size in the horizontal direction. For the minimum character size, this value is 4 clocks. For the double character size, this value is 8 clocks. 2. When the Hsync rising edge occurs, stabilize Hsync with the dot clocks stopped. Start the dot clock oscillation after period A elapses from the Hsync rising edge. 3. Make sure the phase relationship between the external clock and Hsync is always fixed. 4. Connect the OSCIN and OSCOUT as follows. OSCIN : Input external clock OSCOUT : Open
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CHAPTER 4 FAQ
4.1 All OSD LSIs
Q1-1. A1-1. Can external clock input be used? When using the PD6461 or PD6462 with LC oscillation specified by the mask option or when using the
PD6464A or PD6465, NEC does not recommend the input of external clocks.
If continuous external clocks are input, there is a risk that the external buffer that supplies the external clock during the Hsync period and the transistor for forcibly stopping oscillation, which is inside the device, in (a) of Figure 2-2 Dot Clock Oscillation Equivalent Circuit may short, an abnormal current may flow in this circuit, and the transistor may be damaged. Dot clock LC oscillation or external clock input can be selected by using the mask option for the PD6461 or PD6462 or the initialization command for the PC6466. For details, see 3.3 External Clock Forced Input to LC Oscillation Circuit Section. Q1-2. A1-2. Must the serial data and Hsync or Vsync be synchronized? The serial data and Hsync or Vsync are not synchronized. However, when transferring video RAM write data, the command continuous input enable time must be strictly observed. After serial data is transferred, if that data is related to video RAM writing, the data is written to video RAM by using the dot clock. Also, since the dot clock stops and data cannot be written to video RAM during the Hsync period when character display is ON, the data is written to video RAM after the dot clock oscillation begins again after the Hsync period ends. The time required for writing video RAM data is as follows for the PD6461 or PD6462. 12 fosc 21 fosc x Character size
When display is OFF :
When display is ON :
x Character size + tHWL
For details related to the command continuous input enable time, refer to section about command continuous input enable time (PD6461, PD6462, or PD6465) or BUSY period for command input (PD6464A or
PD6465) in the Data Sheet of each version.
Q.1-3. Regarding a power-ON reset, (1) When the PCL pin is connected to VDD before the power is turned on with high level (power-ON clear rating (tPCLL) is not satisfied), and the PCL pin is switched from high level to low level after the power has been turned on, what happens to output from the time the power is turned on until the powerON clear operation is executed? (2) Does the OSD LSI have any kind of internal switch so that no invalid data is output when the power is turned on in the situation described in (1)?
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CHAPTER 4 FAQ
A.1-3.
(1) The output cannot be predicted. Consider the following examples. Example 1. If the mode register is PAL internal mode when NTSC is used, the black and white diagonal striped pattern may appear since the power-ON clear operation is not executed. Example 2. Since the power-ON clear operation is not executed when external video signal mode is established in a video-system OSD LSI, when character display is set to ON, abnormal screen data may appear according to the video RAM contents (which had not been cleared). It may also occur to the output for the background. However, since the external video signal mode display is set to OFF when the PCL pin is at the low level, the character display output is stopped. (2) The OSD LSI contains no kind of internal switch. All NEC OSD LSIs are designed so that the power-ON clear operation is executed simultaneously when the power is turned on. Since no abnormal data is output if the power-ON clear operation is executed, we decided that no switch was required.
Q1-4. A1-4.
How do you decide the LC oscillation constants? NEC recommends L = 33 H, Cin = 5 to 30 pF (trimmer capacitor), and Cout = 30 pF. For details, see 2.1.1 Dot Clock Oscillation Circuit.
Q1-5.
What is the difference between initialization by the video RAM batch clear command and that by the powerON clear operation?
A1-5.
The video RAM batch clear command is a software reset, and the power-ON clear operation is a hardware reset. For details, see 2.6 OSD LSI Power-ON Initialization.
Q1-6. A1-6. Q1-7. A1-7.
Are fields distinguished? An OSD LSI does not distinguish fields. Is data that has been set in video RAM maintained as long as the setting is not changed? Since an OSD LSI has an on-chip refresh timer, video RAM data is maintained as long as character data is not written to video RAM, the power-ON clear operation or video RAM batch clear command is not executed, or the power is not turned off.
Q1-8. A1-8.
What is a 2-byte contiguous command? A 2-byte contiguous command is a command for writing characters to video RAM. For details, refer to the "Transferring Commands" section of the Data Sheet of each version.
Q1-9. A1-9.
Are there any limitations concerning the Hsync and dot clock timing relationship? As long as the command continuous input enable time is satisfied, there are no specific limitations. For information about the command continuous input enable time, refer to the Data Sheet of each version.
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CHAPTER 4 FAQ
Q1-10
When transferring a 2-byte contiguous command, why does the command continuous input enable time when display is ON include the horizontal synchronization signal (Hsync) width?
A1-10. In an OSD LSI, when display is ON, Hsync triggers resets for the internal system timing and controls the display position. Since the dot clock oscillation is stopped during the Hsync period due to these operations, no data is written to video RAM. As a result, the command continuous input enable time when display is ON includes Hsync synchronization signal width. Q1-11. When a PAL signal is input with equivalent settings for the horizontal/vertical display start positions and dot clock frequency as those used for NTSC signal input, the vertical size of the characters is compressed and space appears at the lower portion of the display screen. What causes this? Also, can the same display be output in both the NTSC and PAL signal modes? A1-11. This occurs because the number of scan lines differs in the NTSC and PAL modes, as shown in Figure 4-1. As a result, when a PAL signal is input, the horizontal/vertical display start positions and dot clock frequency must be adjusted, and the display area must be moved (the horizontal/vertical display start positions and dot clock frequency are adjusted in the signal mode units). Also, since a character nondisplay area is generated consisting of 53 scan lines per frame (equivalent to approximately 1.5 lines with the smallest size character) when an NTSC signal is input and 143 scan lines per frame (equivalent to approximately 4 lines with the smallest size character) when a PAL signal is input (see Figure 4-2), the same display cannot be output in both signal modes.
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CHAPTER 4 FAQ
Figure 4-1. Character Display Area Image 1 - When NTSC and PAL Signals Are Input (for Equivalent Display Start Position and Dot Clock Frequency)
When NTSC signal is input (number of effective scan lines: 485) 24 Character display area Maximum: 12 lines x 24 columns Number of scan lines in character display area Maximum: 432 (= 18 dots x 12 lines x 2 fields) Character display area Maximum: 12 lines x 24 columns Number of scan lines in character display area Maximum: 432 (= 18 dots x 12 lines x 2 fields) When PAL signal is input (number of effective scan lines: 575) 24
432
485
432
575
29
119
Set the display start position and dot clock frequency so that the character is displayed in the center of the screen.
Set the display start position and dot clock frequency equivalent to those used for NTSC signal input. Space appears at the bottom and right side, and the characters are compressed in the vertical direction.
Figure 4-2. Character Display Area Image 2 - When NTSC and PAL Signals Are Input (for Center Display)
When NTSC signal is input (number of effective scan lines: 485) 24 Character display area Maximum: 12 lines x 24 columns Number of scan lines in character display area Maximum: 432 (= 18 dots x 12 lines x 2 fields)
When PAL signal is input (number of effective scan lines: 575)
72 Character display area Maximum: 12 lines x 24 columns Number of scan lines in character display area Maximum: 432 (= 18 dots x 12 lines x 2 fields)
432
485
432
575
29
71
Set the vertical display start position to 12H, and set the horizontal display start position and dot clock frequency so that the character display area is in the center of the screen.
Set the vertical display start position to 36H, and set the horizontal display start position and dot clock frequency so that the character display area is in the center of the screen.
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CHAPTER 4 FAQ
4.2 Video-System OSD LSIs (PD6464A and PD6465)
Q2-1. A2-1. Is a crystal oscillator required? It is required when 4fsc crystal oscillation is selected according to the oscillation mode control command. This is because the 4fsc signal generated by the oscillator and VCO is used as the reference clock for synchronization signal generation when internal video signal mode is set, and the fsc signal generated by dividing this 4fsc signal into four parts is used as the reference clock for internal video signal generation and for the synchronization separation circuit (when external video signal mode is set). Use the crystal oscillation control command to set crystal oscillation to ON when displaying characters. Q2-2. A2-2. Is fsc input required? It is required when quadruple oscillation is selected according to the oscillation mode control command. This is because the 4fsc signal generated according to the fsc input is used as the reference clock for synchronization signal generation when internal video signal mode is set, and the fsc signal generated by dividing this 4fsc signal into four parts is used as the reference clock for internal video signal generation and for the synchronization separation circuit (when external video signal mode is set). Use the crystal oscillation control command to set crystal oscillation to ON when displaying characters. With the PD6464A or PD6465, the on-chip quadruple oscillation circuit enables the mounting area and cost to be reduced by using the LC oscillator instead of an expensive crystal oscillator. Also, in the LC oscillator only, since the oscillation precision is decreased due to the scattering of each element, a phase locked loop (PLL) is formed by inputting fsc, and the 4fsc signal is synchronized with the external fsc signal. Q2-3. A2-3. When fsc input is not used, are there limitations concerning the FSCI pin (pin 9) processing? Connect it to GND or VDD and do not leave it open. Also, use the oscillation control command to select 4fsc crystal oscillation. Q2-4. A2-4. When SECAM is not used, are there limitations concerning the SECAM pin (pin 22) processing? If the video signal mode control command is used to select an option other than SECAM, the SECAM pin (pin 22) is disconnected from the internal circuits by an internal analog switch. Therefore, it makes no difference whether something (such as GND or VDD) is connected to this pin or it is left open. However, if something is connected, note the absolute maximum rating of the input pin voltage (VIN: -0.3 to VDD + 0.3 V). Q2-5. Are there limitations concerning pin processing when the VC, VBLK, HSYO, VSYO, CSYIN, and N.C. pins (pins 13 through 18) are not used? A2-5. Q2-6. Leave them open. When only the internal video signal is used with the PD6464A or PD6465, must the composite synchronization signal (Csync) be input? A2-6. The composite synchronization signal (Csync) need not be input when internal video signal mode is used. With the PD6464A or PD6465, the synchronization signal is autogenerated by using the 4fsc signal generated according to 4fSC crystal oscillation or quadruple oscillation.
73
CHAPTER 4 FAQ
Q2-7. A2-7.
What is the scanning method when internal video signal mode is used? When internal video signal mode is used, the scanning method is not interlaced. The number of horizontal scan lines is 263 lines per field for NTSC or PAL-M mode and 312 lines per field for PAL or PAL-N mode.
Q2-8.
What are the voltage levels of the composite synchronization signal (Csync) input to the CSYIN pin (pin 17)?
A2-8.
The CSYIN pin (pin 17) has normal logic input. Therefore, the input levels are as follows according to CMOS input regulations. Input high level voltage : 0.7 VDD (MIN.) Input low level voltage : 0.3 VDD (MAX.)
Q2-9. A2-9.
When display is set to OFF in the PD6464A or PD6465, is the VBSIVBSO status data through? When display is OFF in external video signal mode, the status is data through. Also, when display is OFF in internal video signal mode, a single screen color is displayed of the color used as the screen background color.
Q2-10. If the CSYIN pin (pin 17) is at high level when external video signal mode is used, what is the output status of the HSYO pin (pin 15: horizontal synchronization signal output) and the VSYO pin (pin 16: vertical synchronization signal output)? Also, if a 2-byte contiguous command is transferred at this time, is the data written correctly to video RAM if the command continuous input enable time (TB2, TB2') is observed? A2-10. The HSYO pin and VSYO pin both remain at low level. Also, when a 2-byte contiguous command is transferred, if the CSYIN pin is at high level, since the IC is always in SYNC status, the tHWL of the command continuous input enable time becomes infinitely large, and data cannot be written if display is ON (since LC oscillation stops, no clock for writing is supplied). Therefore, in this situation, data writing to video RAM stops when display is ON and operates when display is OFF. Q2-11. What kind of drive capacity does the VBSO pin (pin 21: composite video signal output) have? A2-11. Since the VBSO pin of the PD6464A or PD6465 only performs through output via an analog switch of the video signal that has been input to the VBSI pin (pin 24: composite video signal input pin), the VBSO pin has no drive capacity. Therefore, an emitter/follower circuit (buffer) according to a transistor must be added to the VBSO pin as shown in 3.1.1 Sample PD6464A or PD6465 Application Circuits so that it can drive subsequent circuits. Q2-12. What criteria are used when selecting a varactor diode? A2-12. Use a varactor diode for which the capacitance changes in the range of approximately 2 to 10 pF with a voltage range on the order of 1 to 4 V. Also, since the capacitance of the capacitor connected to pin 12 in Figure 3-1 Sample PD6464A or PD6465 Application Circuit (When Quadruple Oscillation Is Selected) is the value when 1SV163 is used, be sure to re-evaluate the capacitance of the capacitor when the varactor diode is changed.
74
CHAPTER 4 FAQ
Q2-13. How do the PD6464 and PD6464A differ? A2-13. The PD6464A has PAL-N mode in addition to the video signal modes (NTSC, PAL, PAL-M, and SECAM) corresponding to the PD6464. Q2-14. Is a pull-up resistor required for the PCL pin (pin 7)? A2-14. It is not required. The PD6464A or PD6465 has an on-chip resistor of approximately 50 k between the PCL pin and VDD. Q2-15. If display is set to ON after a power-ON clear operation is executed and no characters are displayed on the screen even when various types of commands are transferred, what adjustments should be made? A2-15. Check the following points and make the corresponding adjustments. * Is the dot clock oscillating? An OSD LSI uses the dot clock when writing data to video RAM. If the dot clock oscillation is stopped, since the data that is supposed to have been transferred is not written to video RAM, the characters are not displayed normally. * Is a composite synchronization signal (Csync) being input? In external video signal mode, the PD6464A or PD6465 timing generator resets the horizontal control section, vertical control section, and output controller by using the horizontal synchronization signal (Hsync) and vertical synchronization signal (Vsync) obtained by synchronization separation of Csync. It also generates reference signals for counting. If no Csync is being input, since the timing generator is not generating these reference signals, the characters are not displayed normally. In internal video signal mode, since Hsync and Vsync are autogenerated within the device, the characters are displayed even if no Csync is being input. * Is 4fsc oscillation occurring? In the PD6464A or PD6465, the 4fsc or fsc signal generated by 4fsc crystal oscillation or quadruple oscillation is used for synchronization separation of Csync (when external video signal mode is selected) or for generation of the internal video signal and internal synchronization signal (when internal video signal mode is selected). If no 4fsc oscillation is occurring, since signal separation or generation is not being performed, the characters are not displayed normally.
75
CHAPTER 4 FAQ
4.3 RGB-System OSD LSIs (PD6461, PD6462, and PD6466)
Q3-1. A3-1. Can the dot clock be checked in the PD6466? Although the dot clock frequency can be measured by using the CLKOUT pin in the PD6461 or PD6462, the PD6466 does not have this kind of pin. With the PD6466, the dot clock can be output from the BLK1 pin by connecting the TEST pin to VDD and transferring the test mode command shown below. 2-byte command (MSB)
D15 1 D14 0 D13 1 D12 1 D11 0 D10 0 D9 0 D8 0 D7 0 D6 0 D5 0 D4 0 D3 1 D2 1 D1 0 D0 0
2-byte command (LSB)
D0 0 D1 0 D2 0 D3 0 D4 1 D5 1 D6 0 D7 1 D8 0 D9 0 D10 1 D11 1 D12 0 D13 0 D14 0 D15 0
Caution Use this command only for checking the dot clock. Q3-2. When external clock input timing is used, what happens if tH-C is less than 30 ns (MIN.) (for example, when the Hsync rising edge and the external clock falling edge overlap (tH-C 0 ns))? A3-2. An OSD LSI uses Hsync for the horizontal control counter reset signal and uses the external clock for the horizontal control counter clock. If the tH-C 30 ns rating cannot be satisfied, the Hsync rising edge and the external clock falling edge may overlap within the horizontal control counter depending on the arrival delay time difference of Hsync and the clock to the horizontal control counter (due to manufacturing variations and conditions of the usage environment such as power source voltage or temperature). If the edges overlap, the timing of the cancellation of a counter reset due to Hsync and the count increment will overlap. Therefore, an unstable condition occurs in which the edge overlapped by the clock may or may not be counted as the first edge. Actually, since both Hsync and the clock have a slight amount of jitter, the condition in which that edge is or is not counted is repeated. As a result, the horizontal display position shifts by one clock (one-dot horizontal jitter occurs). Q3-3. A3-3. What does the synchronization protection circuit do? The synchronization protection circuit prevents vertical jitter of the display character by generating a pseudo Hsync signal. For details, see 2.3.1 Synchronization Protection Circuit. Q3-4. In the PD6461 or PD6462, when the dot clock's external clock input is selected by using the mask option, can LC oscillation occur? A3-4. When the dot clock's external clock input is selected by using the mask option, no dot clock LC oscillation can occur. When external clock input is selected, since the oscillation stage of the LC oscillation circuit is completely disconnected from the pin (see (b) in Figure 2-2 Dot Clock Oscillation Equivalent Circuit), even if an external LC oscillator is attached, it cannot be made to oscillate.
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CHAPTER 4 FAQ
Q3-5. A3-5.
Are there any limitations concerning the clocks that are input when an external clock is selected? As criteria for the external clock, input the following amplitude and duty rate. Input amplitude : Input high level voltage = 0.7 VDD (MIN.) Input low level voltage = 0.3 VDD (MAX.) Duty rate : Set at 50% (TYP.) Also, make the dispersion range within 40 to 60%.
For information about the external clock fallSynchronization signal rise time (tC-H), Synchronization signal riseexternal clock fall time (tH-C), and rise slew rate (ts), refer to the Electrical Specifications in the Data Sheet. Q3-6. A3-6. What is the approximate output impedance of each output pin? The PD6461, PD6462, and PD6466 have a CMOS configuration, and the output impedance is approximately 100 or less. Q3-7. A3-7. Is it possible to change the background color of a specific area? It is possible. Since the background color is set in terms of screens, first set the character inversion ON/ OFF specification command (which is set in terms of screens; for the PD6466, character color inversion ON/OFF specification command), to ON. Then, set the character inversion specification bit (for the PD6466, character color inversion specification bit) of the display character control command, which is set in terms of characters, to ON (See Figure 4-3). Figure 4-3. Sample Display Using Character Inversion
TV
Character inversion ON
NAVIGATION
VIDEO CD MD
Remark The background color of the characters for which inversion is ON will be the character color (which can be set in terms of characters). The character color when inversion is ON is black (for or the PD6466, white also can be specified).
77
CHAPTER 4 FAQ
Q3-8. A3-8.
If the character display is corrupted or if no character is displayed, what adjustments should be made? Check the following points and make the corresponding adjustments. * Is the dot clock oscillating? An OSD LSI uses the dot clock when writing data to video RAM. If the dot clock oscillation is stopped, since the data that is supposed to have been transferred is not written to video RAM, the characters are not displayed. * Are the Hsync and Vsync input? The timing generator resets the horizontal control section, vertical control section, and output controller by using the Hsync and Vsync that were input, and generates reference signals for counting. If Hsync and Vsync are not being input, since the timing generator is not generating reference signals, the characters are not displayed. * Is the command executed within the command continuous input enable time? If the command continuous input enable time is not observed, the data that is supposed to have been transferred is not written to video RAM, and the character display is corrupted.
78
CHAPTER 5 DEVELOPMENT TOOLS
5.1 Overview of Development Tools
NEC provides the OSD LSI development tools introduced below. These all are available for short-term rental. When necessary, contact an NEC distributor or NEC sales representative. * Character Pattern Editor for Windows * Character ROM Verification and Evaluation Board * OSD LSI Evaluation Board Overviews of each tool are presented below. (1) Character Pattern Editor for Windows This is a tool for creating the character data to be installed in the character generator ROM. Its main features are described below. For details, refer to the OSD LSI Character Pattern Editor User's Manual. * Supports Windows 3.1 and Windows 95 * Supports FD order reception Floppy disks are used for the mask ROM code ordering media. Use *.out for data save files. The following table shows the floppy disk physical format when ordering mask ROM code from NEC.
Size Number of Number of tracks Number of sectors recording surfaces Double sided 77 tracks/side 8 sectors/track Record length Recording capacity 1261568 bytes
3.5 inch
1024 bytes/sector
Remarks
MS-DOS PC DOS Windows 3.1 Windows Windows 95
: Floppy disk formatting capacity: Select 1 MB (FORMAT d: /M) : Floppy disk formatting capacity: Select 1.2 MB (FORMAT12)Note : Floppy disk formatting (F) capacity (C): Select 1 MB Floppy disk formatting (F) capacity (C): Select 1.25 MB : Floppy disk formatting (F) capacity (C): Select 1.2 MB NTTM :
Note
The floppy disk drive must support 1.2-MB diskettes. Register $FDD12.SYS in CONFIG.SYS. For details, refer to a PC DOS manual.
For details related to mask ROM code ordering, refer to the information document, "ROM Code Ordering Method". * Maintains upward compatibility with DOS-version environment Data save files (*.out and *.sav) created by the conventional DOS-version editor can be used, and compatibility with the DOS-version editor is maintained. * Provides simple operations and an excellent user interface By using the toolbar, you can execute frequently used functions by clicking a single button. Also, by using multi-document interface (MDI) mode, you can manipulate multiple files (data) on the same screen.
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CHAPTER 5 DEVELOPMENT TOOLS
(2) Character ROM verification and evaluation board This is a tool for verifying the character that was created by the character pattern editor (using *.out for data files) on an actual monitor screen before ordering the mask ROM. Use this board with the connections shown in Figures 5-1 and 5-2. Remark MS-DOS 3.3 is required to run the character ROM verification and evaluation board system software. In addition, the character ROM verification and evaluation board must be connected to a personal computer by using the supplied interface (I/F) board. When evaluating character data, a PC-98 or PC-98-compatible computer (equipped with an expansion slot) must be used as the personal computer where this software can be activated and this I/F board can be connected. Figure 5-1. ROM Verification Board Connection Diagram for RGB Display
TV monitor
I/F board
PC98xx
Insert in expansion slot
CN1&3
,,,, ,,,, ,,,, ,,,,
Logic section
33
123456789 A BCDE FGH I NEC
Video signal input
CN2
CN6
RGB 21-pin multi-connector and cable
CN9
System software (OS: MS-DOS 3.3)
RAM section
CN8 Video out CN7 Video in
CN5 CN4
,,, ,,,
Analog Connect to VCC & GND power supply Digital VCC = VDD = 5.5 V VDD & GND
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CHAPTER 5 DEVELOPMENT TOOLS
Figure 5-2. ROM Verification Board Connection Diagram for VCR Display
TV monitor
I/F board
PC98xx
Insert in expansion slot
CN1&3
,,,, ,,,, ,,,, ,,,, ,,,,
Logic section
33
123456789 A BCDE FGH I NEC
CN2
CN6
RGB 21-pin multi-connector and cable
CN9
System software (OS: MS-DOS 3.3)
CN8 Video out
RAM section
CN7 Video signal input
CN5 CN4
,,,
Video in
Analog VCC & GND Digital VDD & GND
Connect to power supply VCC = VDD = 5.5 V
(4) OSD LSI evaluation board This is a tool for evaluating the functions of NEC standard products or of engineering samples (ES), etc. after the mask ROM has been ordered. There are two types of OSD LSI evaluation boards. The PD6464A and PD6465 evaluation board is for videosystem OSD LSIs and the PD6461, PD6462, and PD6466 evaluation board is for RGB-system OSD LSIs. Use these boards with the connections shown in Figures 5-3 and 5-4. Remark MS-DOS 3.3 is required to run the OSD LSI evaluation board system software. When evaluating OSD LSIs, a PC-98 or PC-98-compatible computer must be used as the personal computer where this software can be activated.
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CHAPTER 5 DEVELOPMENT TOOLS
Figure 5-3. Video-System OSD LSI Evaluation Board Connection Diagram
TV monitor
PC98xx Printer cable
123456789 A BCDE FGH I just imagine NEC MULTIMEDIA
+5-V power supply
PD6464A and PD6465 evaluation board
VBSI VBSO
Video signal input VCR, LD, SG, etc.
System software (OS: MS-DOS 3.3)
Figure 5-4. RGB-System OSD LSI Evaluation Board Connection Diagram
TV monitor
PC98xx
123456789 A BCDE FGH I just imagine NEC MULTIMEDIA
Printer cable +5-V power supply
Video signal input VCR, LD, SG, etc.
PD6461, PD6462, and PD6466 evaluation board
RGB 21-pin multi-cable
System software (OS: MS-DOS 3.3)
PD6461, PD6462, and PD6466 conversion board
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CHAPTER 5 DEVELOPMENT TOOLS
5.2 Concerning OSD LSI Mask ROM Ordering
The tools described in 5.1 Overview of Development Tools can be used for ordering mask ROM code according to the procedure shown in Figure 5-5. For details related to mask ROM code ordering, refer to the information document, "ROM Code Ordering Method". Figure 5-5. OSD LSI Mask ROM Code Ordering Procedure (for FD Order Reception)
Select product to be used
Create characters using the Character Pattern EditorNote supporting Windows 3.1 or Windows 95 and FD order reception
Use the character ROM evaluation boardNote to evaluate the created characters on the screen
Record the final character data (*.out file) on the ROM ordering media (FD) and send it to NEC NEC receives the media, creates the return media, and returns it Verify whether the contents of the return media match the final character data
Order mask
Note
These tools are rented. For details, contact an NEC distributor or NEC sales representative.
83
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