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U6224B
Frequency Synthesizer for TV and VCR Tuner with Universal Bus
Description
The U6224B is a single chip frequency synthesizer with bi-directional I2C-bus control and an unidirectional 3-wire bus control, developed for TV-tuner applications. This IC contains an integrated preamplifier, a high frequency prescaler, a reference divider with programmable divider ratios, a crystal oscillator, a phase/ frequency detector together with a charge pump and a tuning amplifier. It perform also a EASY LINK interface to MOSMIC and Mixer IC.
Features
D 1.3 GHz divide-by-8 prescaler integrated (can be bridged) D Easy-link interface to MOSMIC and MIXER-IC D Universal bus: I2C-bus or 3-wire-bus D I2C-bus mode: 3 bidirectional ports (open collector) 5 level ADC or unidirectional port (open collector) 3 addresses selectable at Pin 10 and 1 address fixed for multituner application D Low-power consumption (typ. 5 V / 35 mA) D Electrostatic protection according to MIL-STD 883 D SO16 small package
D 3-wire-bus mode: 3 unidirectional output ports (open collector) lock output (open collector)
Block Diagram
AS / ENA 10 SCL 5 SDA 4 4-bit Latch UNI-BUS Control T1 I/O Ports ADC 7-bit Latch Vs 12 GND 15 Power-on POR reset Sync LOCK SET RFi 14 13 div. by 8 Prescaler 15-bit counter Phase detector Oscillator divide by 512 / 640 / 1024 Charge pump FRFD FPRD 16VD 1 PD 15-bit Latch PSC T0 5I RD1,2 OS 8-bit Latch 7-bit Latch 6 P1 7 P2 8 P0 9 P6 / ADC / Lock 11 MS
RDS 3 XTAL 2
Figure 1. Block diagram
Ordering Information
Extended Type Number U6224B-MFP U6224B-MFPG3 Package SO16 SO16 Taped and reeled Remarks
Rev. A2, 11-Apr-00
1 (15)
U6224B
Pin Description
PD Q1 RDS SDA SCL P1 P2 P0 1 2 3 4 5 6 7 8
Figure 2. Pinning
16 VD 15 GND 14 RFi 13 RFi 12 VS 11 MS 10 AS/ENA 9 P6/ADC /Lock
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Symbol PD Q1 RDS SDA SCL P1 P2 P0 P6/ADC/ Lock AS/ENA MS Vs RFi RFi GND VD
Function Charge pump output XTAL Reference divider select input Data input / output Clock input Input / output port Input / output port Input / output port Port output / ADC-input / Lock output Address select / Enable input Mixer switch output Supply voltage RF input RF input Ground Active filter output
Description
The U6224B is a single chip-PLL designed for TV and VCR receiver systems. It consists of a bridgeable divide-by-8 prescaler with an integrated preamplifier, a 15-bit programmable divider, a crystal oscillator and a reference divider with three selectable divider ratios ( 512/ 640/ 1024), and phase/ frequency detector with a charge-pump which is driving the tuning amplifier. Only one external transistor is required for varactor line driving. The device can be controlled via the I2C-bus or the 3-wire-bus format. It detects automatically which bus format is received, therefore, there is no need for a bus selection pin. In I2C-bus mode, the device has one fixed I2C-bus address and three programmable addresses. Programming is carried out by applying a specific input voltage to the address select input, enabling the use of up to three synthesizers in a system. This pin serves in 3-wire-bus mode as the enable signal input. Four opencollector outputs are available for switching functions. In 3-wire-bus mode, there are three open-collector outputs. One of them serves as Lock signal output. The logic of the output ports P0-2 is inverted in order to drive gate 1 of MOSMIC prestages directly without change in software. This feature removes the formerly external pnp switching transistors. All open collector outputs are capable of sinking at least 10 mA. The MS output is provided to control directly a mixer-oscillator IC in combination with the output port P0-2 state.
In I2C-bus mode, an Analog-to-Digital Converter is available for digital AFC control applications and the ports P0-2 can be used as inputs.
Functional Description
The U6224B is programmed via the 2-wire I2C-bus or the 3-wire-bus depending on the received data format. The three bus inputs Pins 4, 5 and 10 are used as SDA, SCL and address select inputs in I2C-bus mode or as data, clock and enable inputs in 3-wire-bus mode. The data includes the scaling factor SF and switching output information. In I2C-bus mode, are some additional functions are available (ADC, bidirectional ports, etc.). Oscillator frequency calculation: fVCO = PSF SPF frefosc/SRF fVCO: PSF: SPF: SRF: Locked frequency of voltage controlled oscillator Scaling factor of prescaler ( 1 or 8 in I2C-/ 8 in 3-wire-bus mode) Scaling factor of programmable divider (15 bit in I2C-/14 bit in 3-wire-bus mode) Scaling factor of ( 512/ 640/ 1024) reference divider
frefosc: Reference oscillator frequency: 3.2/4 MHz crystal or external reference frequency
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Rev. A2, 11-Apr-00
U6224B
The input amplifier together and the divide-by-8 prescaler enable an excellent sensitivity (see figures 7 and 8). The input impedance is shown in the figure 16. When a new divider ratio according to the requested fVCO is entered, the phase detector and charge pump together with the tuning amplifier adjust the control voltage of the VCO until the output signals of the programmable divider and the reference divider are in frequency and phase locked. The reference frequency may be provided by an external source capacitively coupled into Pin 2, or by using an on-board crystal with an 18-pF capacitor in series. The crystal operates in series resonance mode. The reference divider division ratio is selectable to 512/ 640/ 1024. Using a 4-MHz crystal and the nominal division ratio of 512 of the reference divider, the comparison frequency is 7.8125 kHz, resulting in 62.5-kHz steps for the VCO. Using a 3.2-MHz crystal results in 6.25 kHz comparison frequency and 50-kHz VCO step size. In I2C-bus mode, the division ratio may be set via two bits, in 3-wire-bus mode via a voltage at Pin 3. In addition, port outputs for band switching and other purposes are available.
Application
A typical application is shown on page 14. All input/output interface circuits are shown on pages 12 and 13. Some special features related to test- and alignment procedures for tuner production are explained in the following bus-mode description.
Absolute Maximum Ratings
All voltages are referred to GND (Pin 15). Parameters Supply voltage RF input voltage Xtal input voltage Charge pump output voltage Active filter output voltage Bus input/output voltage SDA output current Address select/ENA input Port output current Total port output current Port input/output voltage Port output voltage Junction temperature Storage temperature Test Conditions / Pins Pin 12 Pin 13, 14 Pin 2 Pin 1 Pin 16 Pin 4, 5 Pin 4 Pin 10 Pin 6-9 Pin 6-9 Pin 6-9 Pin 6-9 Symbol Vs RFi Q1 PD VD VSDA, VSCL ISDA VAS/ENA P0-2, P6 P0-2, P6 P0-2, P6 P0-2, P6 Tjmax Tstg Min. -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -1 -0.3 -1 -1 -0.3 -0.3 -40 -40 Typ. Max. 6 Vs+0.3 Vs+0.3 Vs+0.3 Vs+0.3 6 5 Vs+0.3 15 50 15 6 125 125 Unit V V V V V V mA V mA mA V V C C
open collector open collector open collector in off-state in on-state
Operating Range
All voltages are referred to GND (Pin 15). Parameters Supply voltage Ambient temperature Input frequency Input frequency Programmable divider Programmable divider Xtal oscillator Test Conditions / Pins Pin 12 PSC = 1 Pin 13, 14 PSC = 0 Pin 13, 14 I2C-bus mode 3-wire-bus mode Pin 2 Symbol Vs Tamb RFi RFi SF SF fXtal Min. 4.5 0 80 1 256 256 3 Typ. 5 Max. 5.5 70 1300 220 32767 16383 4.48 Unit V C MHz MHz
4
MHz
Rev. A2, 11-Apr-00
3 (15)
U6224B
Thermal Resistance
All voltages are referred to GND (Pin 15). Parameters Thermal resistance Test Conditions / Pins SO16 small Symbol RthJA Min. Typ. Max. 110 Unit K/W
Electrical Characteristics
Test conditions (unless otherwise specified): Vs = 5 V, Tamb = 25 C Parameters Supply current (prescaler on) Supply current (prescaler off) Test Conditions / Pins P0-2 = 1; P6 = 0; PSC =1 Pin 12 P0-2 = 1; P6 = 0; PSC =0 Pin 12 Symbol Is Is Min. Typ. 35 21 Max. Unit mA mA
Input sensitivity fRFi = 80-1000 MHz PSC =1 Pin 13 Vi 1) 10 fRFi = 1300 MHz PSC =1 Pin 13 Vi 1) 40 1) fRFi = 10-220 MHz PSC =0 Pin 13 Vi 10 Crystal oscillator Recommended crystal series 10 resistance Crystal oscillator drive level Pin 2 Crystal oscillator source imNominal spread 15 % pedance Pin 2 External reference input freAC-coupled sinewave 3 quency Pin 2 External reference input ampli- AC-coupled sinewave 70 tude Pin 2 Port outputs/lock output (open collector), Lock condition: low, P0-2, P6, Lock Leakage current VH = 13.5 V Pins 6-9 IL Saturation voltage IL = 10 mA Pins 6-9 VSL 2) Port inputs (P0-2) Input voltage high Pins 6-8 Vi`H' 2.7 Input voltage low Pins 6-8 Vi`L' Input current high Vi`H' = 13.5 V Pins 6-8 Ii`H' Input current low Vi`L' = 0 V Pins 6-8 Ii`L' -10 ADC input (ADC), see page 7 for ADC-levels Input current high Vi`H' = 13.5 V Pin 9 Ii`H' Input current low Vi`L' = 0 V Pin 9 Ii`L' -10 Charge pump output (PD) Charge pump current `H' 5I = 1, VPD = 1.7 V IPDH Pin 1 Charge pump current `L' 5I = 0, VPD = 1.7 V IPDL Pin 1 Charge pump leakage current TO = 1, VPD = 1.7 V IPDTRI Pin 1 Charge pump amplifier gain Pins 1, 16
315 315 315 200 50 -650 4.5 200
mVrms mVrms mVrms W mVrms W MHz mVrms
10 0.5
mA V V V mA mA mA mA mA mA nA
0.8 10
10
180 50 5 6400
Notes: 1) RMS-voltage calculated from the available power measured at 50 W. 2) Tested with one port active. The collector voltage of an active port may not exceed 6 V.
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U6224B
Parameters Test Conditions / Pins Bus inputs (SDA, SCL) Input voltage high Pin 4, 5 Input voltage low Pin 4, 5 Input current high Vi`H' = Vs Pin 4, 5 Input current low Vi`L' = 0 V Pin 4, 5 Output voltage SDA (open ISDA`L' = 3 mA Pin 4 collector) Address selection/Enable input (AS/ENA) Input current high Vi`H' = Vs Pin 10 Input current low Vi`L' = 0 V Pin 10 Mixer switch output (MS) Output voltage band A I MS = -20 mA Pin 11 Output voltage band B I MS = -20 mA Pin 11 Output voltage band C I MS = -20 mA Pin 11 Symbol Vi`H' Vi`L' Ii`H' Ii`L' VSDA `L' Ii`H' Ii`L' V MSA V MSB V MSC Min. 3 Typ. Max. 5.5 1.5 10 0.4 Unit V V mA mA V
-20
10 -10 0 1.6 Vs-1 0.25 0.4*Vs Vs-.75 1 2.4 Vs
mA mA V V V
I2C-Bus Description
Functional Description
When the U6224B is controlled via the 2-wire I2C-bus format, then data and clock signals are fed into the SDA and SCL lines respectively. Depending on the LSB of the address byte, the device can either accept new data (write mode: LSB = 0) or send data (read mode: LSB = 1). The device has one fixed and three programmable I2C-bus addresses. The tables `I2C-BUS WRITE DATA FORMAT' and `I2C-BUS READ DATA FORMAT' describe the format of the data and show how to select the device address by applying a voltage at Pin 10. divider. They are loaded in a 15 bit latch after the 8th clock pulse of the second divider byte PDB2, the control and the port register latches are loaded after the 8th clock pulse of the control byte CB1 resp. port byte CB2. The control byte CB1 allows to control the following special functions: D 5I-bit switches between low and high charge pump current D T1-bit enables divider test mode when it is set to logic 1 D T0-bit allows to disable the charge pump when it is set to logic 1 D PSC-bit switches prescaler off when it is set to logic 0 D RD1 and RD2-bit allow to select the reference divider ratio D OS-bit disables the charge pump drive amplifier output when it is set to logic 1. The charge pump current can be controlled in I2C-bus mode only. The OS-bit function disables the complete PLL function. This allows the tuner alignment by supplying the tuning voltage directly through the 30 V supply voltage of the tuner. The control byte CB2 programs the port outputs P0-2 and P6; for the MOSMIC ports P0-2 a logic 1 for high impedance output (off) or a logic 0 for low impedance output and for the standard port P6 a logic 0 for high impedance output (off) or a logic 1 for low impedance output (on). At power-on the MOSMIC ports P0-2 are set to low impedance state and the standard port P6 to high impedance state. 5 (15)
Write Mode (Address byte LSB = 0)
When write mode is activated and the correct address is received, the SDA line is pulled low by the device during the acknowledge period, and then also during the acknowledge periods, when additional data bytes are programmed. After the address transmission (first byte), data bytes can be sent to the device. There are four data bytes requested to fully program the device. Once the correct address is received and acknowledged, the first bit of the following byte determines whether that byte is interpreted as byte 2 or 4; a logic 0 for divider information and a logic 1 for control and port output information. When byte 2 was received the device always expects byte 3 next. Likewise when byte 4 was received, byte 5 is expected. Additional data bytes can be entered without the need to re-address the device to the device until an I2C-bus stop condition is recognized. This allows a smooth frequency sweep for fine tuning AFC purposes. The table `I2C-BUS PULSE DIAGRAM' shows some possible data transfer examples. The programmable divider bytes PDB1 and PDB2 are controlling the division ratio of the 15 bit programmable Rev. A2, 11-Apr-00
U6224B
Description I2C Bus Write Data Format A A A A A MSB LSB Address byte 1 1 0 0 0 AS1 AS2 0 Progr. divider byte 1 0 n14 n13 n12 n11 n10 n9 n8 Progr. divider byte 2 n7 n6 n5 n4 n3 n2 n1 n0 Control byte 1 1 5I T1 T0 PSC RD2 RD1 OS Control byte 2 X P6 X X X P2 P1 P0 A = Acknowledged; X = not used; unused bits of control byte 2 should be 0 for lowest power consumption n0 ... n14: PSC: T0, T1: Scaling factor (SF) Prescaler on/off Test mode selection SF = 16384 n14 + 8192 n13 + ... + 2 n1 + n0
PSC = 1: prescaler on
PSC = 0: prescaler off
T1 = 1: divider test mode on fPRD at Pin 6, fRFD at Pin 7 T1 = 0: divide test mode off T0 = 1: charge pump disable T0 = 0: charge pump enable P0, 1, 2 = 0: open collector active for MOSMIC gate 1 logic P6 = 1: open collector active 5I = 1: high current OS = 1: varicap drive disable 5I = 0: low current OS = 0: varicap drive enable
P0-2: P6: 5I: OS:
Port outputs (for MOSMIC'S) Port outputs Charge pump current switch Output switch
RD1, RD2: Reference Divider Selection
RD2 X 0 1
RD1 0 1 1
Reference Divider Ratio 640 1024 512
AS1, AS2: Address Selection Pin 10
AS1 0 0 1 1
AS2 1 0 0 1
Address Dec. Value 1 2 3 4 194 192 196 198
Voltage at Pin 10 always valid 0 to 10 % Vs 40 to 60 % Vs 90 % Vs to 13.5 V
Mixer-Switch Output Levels
P2 0 1 0
P1 1 0 0
P0 0 0 1
MS Output Voltage < 0.25 V 0.4 Vs Vs - 0.75 V
Band Selection Band A Band B Band C
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U6224B
Read Mode (Address byte LSB = 1)
After the address transmission (first byte), the status byte can be read from the device on the SDA line (MSB first). Data is valid on the SDA line during logic high of the SCL signal. The controller accepting the data has to pull the SDA line to low-level during all status byte acknowledge periods to read another status byte. If the controller fails to pull the SDA line to low-level during this period, the device will release the SDA line to allow the controller to generate a STOP condition. The POR-bit (power-on-reset) is set to a logic 1 when the supply voltage Vs of the device has dropped below 3 V (at 25 C) and also when the device is initially turned on. The POR-bit is reset to a logic 0 when the read sequence is terminated by a STOP condition. When POR-bit is set high (at low Vs) it is indicated that all programmed informaDescription Address byte Status byte POR: Power-on-reset flag: FL: in-lock flag: MSB 1 POR 1 FL 0 I2 tion is lost and the port outputs are all set to high impedance state. The FL-bit indicates whether the loop is in phase lock condition (logic 1) or not (logic 0). If the ADC or the ports are to be used as inputs, the corresponding outputs must be programmed to a high impedance state (logic 1). The bits I2, I1 and I0 show the status of the I/O ports P0, P1 and P2 respectively. A logic 0 indicates a LOW level and a logic 1 a HIGH level (TTL levels). The bits A2, A1 and A0 represent the digital information of the 5-level ADC. This converter can be used to feed AFC information to the controller from the IF section of the receiver, as shown in the typical application circuit on page 14. I2C Bus Read Data Format 0 I1 0 I0 AS1 A2 AS2 A1 LSB 1 A0 A -
POR = 1 on power on FL = 1, when loop is phase locked
I2, I1, I0: digital information of I/O-ports P0, P1 and P2 respectively A2, A1, A0: digital data of the 5-level ADC. see next table
A/D Converter Levels
A2 1 0 0 0 0
A1 0 1 1 0 0
A0 0 1 0 1 0
Input Voltage to ADC Pin 9 60 % Vs to 13.5 V 45 % to 60 % Vs 30 % to 45 % Vs 15 % to 30 % Vs 0 V to 15 % Vs
Rev. A2, 11-Apr-00
7 (15)
U6224B
I2C-Bus Pulse Diagram
ADDRESS BYTE / A / 1.BYTE /A/ 2.BYTE /A/ 3.BYTE /A/ 4.BYTE /A/
SDA
SCL START 1 2 3 4 5 6 7 8 9 1... 8 9 1... 8 9 1... 8 9 1... 8 9 STOP
Figure 3. Pulse diagram
Data transfer examples START - ADR - PDB1 - PDB2 - CB1 - CB2 - STOP START - ADR - CB1 - CB2 - PDB1 - PDB2 - STOP START - ADR - PDB1 - PDB2 - CB1 - STOP START - ADR -PDB1 - PDB2 -STOP START -ADR - CB1 - CB2 - STOP START - ADR - CB1 -STOP START = ADR = PDB1 = PDB2 = CB1 = CB2 = STOP =
Description Start condition Address byte Progr. divider byte 1 Progr. divider byte 2 Control byte 1 Control byte 2 Stop condition
I2C-Bus Timing
t
W STT
SDA
t S STT
SCL
t LOW
t HIGH
tR
tF
t S STP
t H STT
START CLOCK
t S DAT
t H DAT
STOP
DATACHANGE
Figure 4. Bus timing
Parameters Rise time SDA, SCL Fall time SDA, SCL Clock frequency SCL Clock `H' pulse Clock `L' pulse Hold time start Waiting time start Setup time start Setup time stop Setup time data Hold time data
Test Conditions / Pins
Symbol tR tF fSCL tHIGH tLOW tH STT tW STT tS STT tS STP tS DAT tH DAT
Min.
0 4 4 4 4 4 4 0.3 0
Max. 15 15 100
Unit ms ms kHz ms ms ms ms ms ms ms ms
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Rev. A2, 11-Apr-00
U6224B
3-Wire-Bus Description
When the U6224B is controlled via 3-wire-bus format, then data, clock and enable signals are fed into the SDA, SCL and AS/ENA lines respectively. Figure 5 shows the data format. The data consists of a single word which contains the programmable divider (14 bit) and port information. Bit no. 15 of the programmable divider is always zero when 3-wire-bus mode is active. Only during the enable high period, the data is clocked into the internal data shift register on the negative clock transition. During enable low periods, the clock input is disabled. New data words are only accepted by the internal data latches from the shift register on a negative transition of the enable signal when exactly eighteen clock pulses were sent during the high period of the enable. The data sequence and the timing is described in the following diagrams. In 3-wire-bus mode, Pin 9 becomes automatically the Lock signal output. An improved lock detect circuit generates a flag when the loop has attained lock. `In lock' is indicated by a low impedance at on state of the open collector output. RDS: Reference Divider Selection Pin 3 In 3-wire-bus mode, the following conditions are set internally: D 5I = 1: tive D T1 = 0: D T0 = 0: always high, charge pump current acdivider test mode off charge pump enable
D RD1, 2 = X: reference divider ratio is selected through RDS input D PSC = 1: D OS = 0: prescaler on varicap enable
In 3-wire-bus mode, the division ratio of the reference divider may be selected by applying an appropriate voltage at the RDS input Pin 3. The complete PLL function can be disabled by programming a normally not used division ratio of zero. This allows the tuner alignment by supplying the tuning voltage directly through the 30-V supply voltage of the tuner. Reference Divider Ratio 1024 512 640 Voltage at Pin 3 0% to 10% Vs open or 40% to 60% Vs 90% to 100% Vs
Rev. A2, 11-Apr-00
9 (15)
U6224B
3-Wire-Bus Pulse Diagram
3 Bit Ports P1 P2 P0 SDA 14 Bit scaling factor SF X MSB LSB
SCL
AS / ENA
Figure 5. Pulse diagram
3-Wire-Bus Timing
SDA LSB
SCL
AS / ENA
TL
TS
TC
TH TSL
TT
Figure 6. Bus timing
Parameters Setup time Enable hold time Clock width Enable setup time Enable between two transmissions Data hold time
Test Conditions / Pins
Symbol TS TSL TC TL TT TH
Min. 2 2 2 10 10 2
Typ.
Max.
Unit ms ms ms ms ms ms
10 (15)
Rev. A2, 11-Apr-00
U6224B
Typical Prescaler Input Sensitivity (Prescaler on: PSC = 1)
Vi (mV RMS on 50 Ohm) 1000
100 OPERATING WINDOW 10
1
0,1 0 200 400 600 800 1000 1200 1400 1600 1800 2000
Frequency (MHz)
Figure 7.
Typical Prescaler Input Sensitivity (Prescaler off: PSC = 0)
Vi (mV RMS on 50 Ohm) 1000
100 OPERATING WINDOW 10
1
0,1 0 50 100 150 200 250 Frequency (MHz)
Figure 8.
300
350
400
Rev. A2, 11-Apr-00
11 (15)
U6224B
Input/Output Interface Circuits
Vref
Vs
1.5K RF1 RF2
1.5K
Port Vref
Figure 9. RF Input
Figure 12. Ports
Vs
Vs
60
2K PD
AS / ENA
Vref
OS (O/P Disable) 45K
VD
Figure 13. Address select/ Enable input Figure 10. Loop amplifier
Vs Vs
25k SDA / SCL RDS 25k SDA only ACK
Figure 11. SCL and SDA input
Figure 14. Reference divider select input
12 (15)
Rev. A2, 11-Apr-00
U6224B
Vs
XTAL Q1
Figure 15. Reference oscillator
Typical Input Impedance
j
0.5j
2j
0.2j
5j
0
-0.2j
Rev. A2, 11-Apr-00
AAA AAA AAAA AAAA AAAA AAAA AA AA AA AA AA AA AA AA AA
0.2 0.5 1 2 5 100 MHz 500 MHz 1 GHz -0.5j 1.5 GHz -2j -j
1
-5j
Figure 16.
AAAA AAAA
Z0 = 50 W
13 (15)
U6224B
Application Circuit
MOSMIC AGC ANT 10k 4n7 OSC MX / OSC f IF IF-Section f VCO 30 V RDS 22 k 39 n PD 1 22 k 180 n 16 VD MS P1 11 6 P2 3 4 MHz 1n 18 p RFi 1 n ADC 13 14 9 2 12 15 AFC
Vs GND AS / ENA from/to m C SCL SDA
U6224B
7 P0 8
10 5 4
Figure 17. Application circuit
Package Information
Package SO16
Dimensions in mm
10.0 9.85 5.2 4.8 3.7
1.4 0.4 1.27 8.89 16 9 0.25 0.10 0.2 3.8 6.15 5.85
technical drawings according to DIN specifications
1
8
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U6224B
Ozone Depleting Substances Policy Statement
It is the policy of TEMIC Semiconductor GmbH to 1. Meet all present and future national and international statutory requirements. 2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances (ODSs). The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs and forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these substances. TEMIC Semiconductor GmbH has been able to use its policy of continuous improvements to eliminate the use of ODSs listed in the following documents. 1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively 2. Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental Protection Agency (EPA) in the USA 3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively. TEMIC Semiconductor GmbH can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances.
18
We reserve the right to make changes to improve technical design and may do so without further notice. Parameters can vary in different applications. All operating parameters must be validated for each customer application by the customer. Should the buyer use TEMIC Semiconductors products for any unintended or unauthorized application, the buyer shall indemnify TEMIC Semiconductors against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. Data sheets can also be retrieved from the Internet: http://www.temic-semi.com
TEMIC Semiconductor GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany Telephone: 49 (0)7131 67 2594, Fax number: 49 (0)7131 67 2423
Rev. A2, 11-Apr-00
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