 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| U3745BM UHF ASK Receiver Description The U3745BM is a multi-chip PLL receiver device supplied in an SO20 package. It has been specially developed for the demands of RF low-cost data transmission systems with low data rates from 1 kBaud to 10 kBaud in Manchester or Bi-phase code. The receiver is well suited to operate with Atmel Wireless & Microcontrollers' PLL RF transmitter U2745B. It can be used in the frequency receiving range of f0 = 310 MHz to 440 MHz for ASK data transmission. All the statements made below refer to 433.92-MHz and 315-MHz applications. The main applications of the U3745BM are in the areas of outside temperature metering, socket control, garage door opener, consumption metering, light/ fan or air-condition control, jalousies, wireless keyboard and various other consumer market applications. Features D Supply voltage 4.5 V to 5.5 V, operating temperature range -40C to 85C D Minimal external circuitry requirements, no RF components on the PC board except matching to the receiver antenna D High sensitivity, especially at low data rates D Sensitivity reduction possible even while receiving D Fully integrated VCO D Low power consumption due to configurable self polling with a programmable timeframe check D Single-ended RF input for easy matching to l/4 antenna or printed antenna on PCB D Low-cost solution due to high integration level D ESD protection according to MIL-STD. 883 (4KV HBM) except Pin POUT (2KV HBM) D High image frequency suppression due to 1 MHz IF in conjunction with a SAW front-end filter. Up to 40 dB is thereby achievable with newer SAWs. D Programmable output port for sensitivity selection or for controlling external periphery D Communication to mC possible via a single, bi-directional data line D Power management (polling) is also possible by means of a separate pin via the mC System Block Diagram UHF ASK Remote control transmitter UHF ASK Remote control receiver 1 Li cell U2745B PLL U3745BM Demod. Control 1...3 mC Keys Encoder M44Cx9x XTO IF Amp Antenna Antenna VCO PLL XTO Power amp. LNA VCO Figure 1. System block diagram Rev. A2, 28-Sep-00 1 (24) U3745BM Ordering Information Extended Type Number U3745BM-MFL U3745BM-MFLG3 Package SO20 SO20 Remarks Tube Taped and reeled Pin Description n.c. ASK CDEM AVCC AGND DGND MIXVCC LNAGND LNA_IN n.c. 1 20 DATA ENABLE TEST POUT MODE DVCC XTO LFGND LF LFVCC 2 3 19 18 4 17 5 16 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Symbol n.c. ASK CDEM AVCC AGND DGND MIXVCC LNAGND U3745BM 6 15 7 14 8 9 13 12 10 11 Figure 2. Pinning SO20 17 18 19 20 Function Not connected ASK high Lower cut-off frequency data filter Analog power supply Analog ground Digital ground Power supply mixer High-frequency ground LNA and mixer LNA_IN RF input n.c. Not connected LFVCC Power supply VCO LF Loop filter LFGND Ground VCO XTO Crystal oscillator DVCC Digital power supply MODE Selecting 433.92 MHz /315 MHz Low: 4.90625 MHz (USA) High: 6.76438 (Europe) POUT Programmable output port TEST Test pin, during operation at GND ENABLE Enables the polling mode Low: polling mode off (sleep mode) H: polling mode on (active mode) DATA Data output / configuration input 2 (24) Rev. A2, 28-Sep-00 U3745BM Block Diagram VS ASK CDEM AVCC Demodulator and data filter RSSI DEMOD_OUT 50 kW DATA Limiter out ENABLE IF Amp Sensitivity reduction Polling circuit and control logic TEST POUT MODE FE CLK DVCC AGND DGND 4. Order MIXVCC LPF 3 MHz Standby logic LFGND LNAGND IF Amp LFVCC LPF 3 MHz VCO XTO XTO f LNA_IN LNA 64 15011 LF Figure 3. Block diagram RF Front End The RF front end of the receiver is a heterodyne configuration that converts the input signal into a 1-MHz IF signal. According to figure 3, the front end consists of an LNA (low noise amplifier), LO (local oscillator), a mixer and RF amplifier. The LO generates the carrier frequency for the mixer via a PLL synthesizer. The XTO (crystal oscillator) generates the reference frequency fXTO. The VCO (voltage-controlled oscillator) generates the drive voltage frequency fLO for the mixer. fLO is dependent on the voltage at Pin LF. fLO is divided by factor 64. The divided frequency is compared to fXTO by the phase frequency detector. The current output of the phase frequency detector is connected to a passive loop filter and thereby generates the control voltage VLF for the VCO. By means of that configuration, VLF is controlled in a way that fLO/64 is equal to fXTO. If fLO is determined, fXTO can be calculated using the following formula: fXTO = fLO/64 The XTO is a one-pin oscillator that operates at the series resonance of the quartz crystal. According to figure 4, the crystal should be connected to GND via a capacitor CL. The value of that capacitor is recommended by the crystal supplier. The value of CL should be optimized for the individual board layout to achieve the exact value of fXTO and hereby of fLO. When designing the system in terms of receiving bandwidth, the accuracy of the crystal and the XTO must be considered. Rev. A2, 28-Sep-00 3 (24) U3745BM VS DVCC CL XTO MODE + 0 (USA) f IF + fLO 314 f LO 432.92 MODE + 1 (Europe) f IF + R1 = 820 W C9 = 4.7 nF C10 = 1 nF LFGND LF VS R1 C9 C10 LFVCC The relation is designed to achieve the nominal IF frequency of fIF = 1 MHz for most applications. For applications where fRF = 315 MHz, MODE must be set to `0'. In the case of fRF = 433.92 MHz, MODE must be set to `1'. For other RF frequencies, fIF is not equal to 1 MHz. fIF is then dependent on the logical level at Pin MODE and on fRF. Table 1 summarizes the different conditions. The RF input either from an antenna or from a generator must be transformed to the RF input Pin LNA_IN. The input impedance of that pin is provided in the electrical parameters. The parasitic board inductances and capacitances also influence the input matching. The RF receiver U3745BM exhibits its highest sensitivity at the best signal-to-noise ratio in the LNA. Hence, noise matching is the best choice for designing the transformation network. A good practice when designing the network is to start with power matching. From that starting point, the values of the components can be varied to some extent to achieve the best sensitivity. If a SAW is implemented into the input network, a mirror frequency suppression of DPRef = 40 dB can be achieved. There are SAWs available that exhibit a notch at Df = 2 MHz. These SAWs work best for an intermediate frequency of IF = 1 MHz. The selectivity of the receiver is also improved by using a SAW. In typical automotive applications, a SAW is used. Figure 5 shows a typical input matching network for fRF = 315 MHz and fRF = 433.92 MHz using a SAW. Figure 6 illustrates an according input matching to 50 W without a SAW. The input matching networks shown in figure 6 are the reference networks for the parameters given in the electrical characteristics. Figure 4. PLL peripherals The passive loop filter connected to Pin LF is designed for a loop bandwidth of BLoop = 100 kHz. This value for BLoop exhibits the best possible noise performance of the LO. Figure 4 shows the appropriate loop filter components to achieve the desired loop bandwidth. If the filter components are changed for any reason, please note that the maximum capacitive load at Pin LF is limited. If the capacitive load is exceeded, a bitcheck may no longer be possible since fLO cannot settle in time before the bitcheck starts to evaluate the incoming data stream. Self polling does therefore also not work in that case. fLO is determined by the RF input frequency fRF and the IF frequency fIF using the following formula: fLO = fRF - fIF To determine fLO, the construction of the IF filter must be considered at this point. The nominal IF frequency is fIF = 1 MHz. To achieve a good accuracy of the filter's corner frequencies, the filter is tuned by the crystal frequency fXTO. This means that there is a fixed relation between fIF and fLO. that depends on the logic level at pin mode. This is described by the following formulas: Table 1. Calculation of LO and IF frequency AAAAAAAAAAAAA A AAAAAAAAAAAAA AAAAAAAAAAAAA A AAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAA A AAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAA 300 MHz < fRF < 365 MHz, MODE = 0 365 MHz < fRF < 450 MHz, MODE = 1 f LO + fRF 1 1 ) 432.92 f IF + f RF 432.92 4 (24) Rev. A2, 28-Sep-00 Conditions fRF = 315 MHz, MODE = 0 fRF = 433.92 MHz, MODE = 1 Local Oscillator Frequency fLO = 314 MHz fLO = 432.92 MHz fRF f LO + 1 1 ) 314 Intermediate Frequency fIF = 1 MHz fIF = 1 MHz f f IF + LO 314 U3745BM 8 LNAGND 8 LNAGND U3745BM C3 22p L 25n 9 LNA_IN C3 47p L 25n 9 U3745BM LNA_IN C16 100p C17 8.2p TOKO LL2012 F27NJ C16 100p C17 22p TOKO LL2012 F47NJ fRF = 433.92 MHz L2 TOKO LL2012 F33NJ C2 8.2p 33n L3 27n fRF = 315 MHz L2 TOKO LL2012 F82NJ C2 10p 82n L3 47n RFIN 1 IN 2 IN_GND OUT OUT_GND CASE_GND 3,4 7,8 B3555 5 6 RFIN 1 IN 2 IN_GND OUT OUT_GND CASE_GND 3,4 7,8 B3551 5 6 Figure 5. Input matching network with SAW filter fRF = 433.92 MHz 8 LNAGND fRF = 315 MHz 8 LNAGND U3745BM 9 15p 25n LNA_IN 9 33p 25n U3745BM LNA_IN RFIN 3.3p 22n 100p TOKO LL2012 F22NJ RFIN 3.3p 39n 100p TOKO LL2012 F39NJ Figure 6. Input matching network without SAW filter Please note that for all coupling conditions (see figures 5 and 6), the bond wire inductivity of the LNA ground is compensated. C3 forms a series resonance circuit together with the bond wire. L = 25 nH is a feed inductor to establish a DC path. Its value is not critical but must be large enough not to detune the series resonance circuit. For cost reduction, this inductor can be easily printed on the PCB. This configuration improves the sensitivity of the receiver by about 1 dB to 2 dB. RF input frequencies, refer to table 1 to determine the center frequency. The receiver U3745BM employs an IF bandwidth of BIF = 600 kHz. This IC can be used together with the U2745B. SAW transmitters exhibit much higher transmit frequency tolerances compared to PLL transmitters. Generally, it is necessary to use BIF = 600 kHz together with such transmitters. Analog Signal Processing IF Amplifier The signals coming from the RF front end are filtered by the fully integrated 4th-order IF filter. The IF center frequency is fIF = 1 MHz for applications where fRF = 315 MHz or fRF = 433.92 MHz is used. For other Rev. A2, 28-Sep-00 5 (24) U3745BM RSSI Amplifier The subsequent RSSI amplifier enhances the output signal of the IF amplifier before it is fed into the demodulator. The dynamic range of this amplifier is DRRSSI = 60 dB. If the RSSI amplifier is operated within its linear range, the best S/N ratio is maintained in ASK mode. If the dynamic range is exceeded by the transmitter signal, the S/N ratio is defined by the ratio of the maximum RSSI output voltage and the RSSI output voltage due to a disturber. The dynamic range of the RSSI amplifier is exceeded if the RF input signal is about 60 dB higher compared to the RF input signal at full sensitivity. Since different RF input networks may exhibit slightly different values for the LNA gain, the sensitivity values given in the electrical characteristics refer to a specific input matching. This matching is illustrated in figure 6 and exhibits the best possible sensitivity. figuration of the Receiver'). BR_Range must be set in accordance to the used baudrate. The U3745BM is designed to operate with data coding where the DC level of the data signal is 50%. This is valid for Manchester and Bi-phase coding. If other modulation schemes are used, the DC level should always remain within the range of VDC_min = 33% and VDC_max = 66%. The sensitivity may be reduced by up to 1.5 dB in that condition. Each BR_Range is also defined by a minimum and a maximum edge-to-edge time (tee_sig). These limits are defined in the electrical characteristics. They should not be exceeded to maintain full sensitivity of the receiver. Receiving Characteristics The RF receiver U3745BM can be operated with and without a SAW front end filter. The selectivity with and without a SAW front end filter is illustrated in figure 7. This example relates to ASK mode of the U3745BM. Note that the mirror frequency is reduced by 40 dB. The plots are printed relatively to the maximum sensitivity. If a SAW filter is used, an insertion loss of about 4 dB must be considered. When designing the system in terms of receiving bandwidth, the LO deviation must be considered as it also determines the IF center frequency. The total LO deviation is calculated to be the sum of the deviation of the crystal and the XTO deviation of the U3745BM. Lowcost crystals are specified to be within 100 ppm. The XTO deviation of the U3745BM is an additional deviation due to the XTO circuit. This deviation is specified to be 50 ppm. If a crystal of 100 ppm is used, the total deviation is 150 ppm in that case. Note that the receiving bandwidth and the IF-filter bandwidth are equivalent in ASK mode. 0 -10 -20 -30 dP (dB ) -40 -50 -60 -70 -80 -90 -100 16564 Demodulator and Data Filter The signal coming from the RSSI amplifier is converted into the raw data signal by the ASK demodulator. In ASK mode, an automatic threshold control circuit (ATC) is employed to set the detection reference voltage to a value where a good signal-to-noise ratio is achieved. This circuit also implies the effective suppression of any kind of inband noise signals or competing transmitters. If the S/N ratio exceeds 10 dB, the data signal can be detected properly. The output signal of the demodulator is filtered by the data filter before it is fed into the digital signal processing circuit. The data filter improves the S/N ratio as its passband can be adopted to the characteristics of the data signal. The data filter consists of a 1st-order highpass and a 1st-order lowpass filter. The highpass filter cut-off frequency is defined by an external capacitor connected to Pin CDEM. The cut-off frequency of the highpass filter is defined by the following formula: fcu_DF + 2 p 1 30 kW CDEM without SAW In self-polling mode, the data filter must settle very rapidly to achieve a low current consumption. Therefore, CDEM cannot be increased to very high values if self polling is used. On the other hand, CDEM must be large enough to meet the data filter requirements according to the data signal. Recommended values for CDEM are given in the electrical characteristics. The cut-off frequency of the lowpass filter is defined by the selected baudrate range (BR_Range). BR_Range is defined in the OPMODE register (refer to chapter `Con- with SAW -6 -5 -4 -3 -2 -1 0 1 2 df ( MHz ) 3 4 5 6 Figure 7. Receiving frequency response 6 (24) Rev. A2, 28-Sep-00 U3745BM Polling Circuit and Control Logic The receiver is designed to consume less than 1 mA while being sensitive to signals from a corresponding transmitter. This is achieved via the polling circuit. This circuit enables the signal path periodically for a short time. During this time the bitcheck logic verifies the presence of a valid transmitter signal. Only if a valid signal is detected the receiver remains active and transfers the data to the connected C. If there is no valid signal present, the receiver is in sleep mode most of the time resulting in low current consumption. This condition is called polling mode. A connected C is disabled during that time. All relevant parameters of the polling logic can be configured by the connected C. This flexibility enables the user to meet the specifications in terms of current consumption, system response time, data rate etc. Regarding the number of connection wires to the mC, the receiver is very flexible. It can be either operated by a single bi-directional line to save ports to the connected mC. Or it can be operated by up to three uni-directional ports. Pin MODE can now be set in accordance with the desired clock cycle TClk. TClk controls the following applicationrelevant parameters: D Timing of the polling circuit including bitcheck D Timing of the analog and digital signal processing D Timing of the register programming D Frequency of the reset marker D IF filter center frequency (fIF0) Most applications are dominated by two transmission frequencies: fSend = 315 MHz is mainly used in USA, fSend = 433.92 MHz in Europe. In order to ease the usage of all TClk-dependent parameters, the electrical characteristics display three conditions for each parameter. D Application USA (fXTO = 4.90625 MHz, MODE = L, TClk = 2.0383 s) D Application Europe (fXTO = 6.76438 MHz, MODE = H, TClk = 2.0697 s) D Other applications (TClk is dependent on fXTO and on the logical state of Pin MODE. The electrical characteristic is given as a function of TClk). The clock cycle of some function blocks depends on the selected baud rate range (BR_Range) which is defined in the OPMODE register. This clock cycle TXClk is defined by the following formulas for further reference: BR_Range = BR_Range0: BR_Range1: BR_Range2: BR_Range3: TXClk = 8 x TClk TXClk = 4 x TClk TXClk = 2 x TClk TXClk = 1 x TClk Basic Clock Cycle of the Digital Circuitry The complete timing of the digital circuitry and the analog filtering is derived from one clock. According to figure 8, this clock cycle TClk is derived from the crystal oscillator (XTO) in combination with a divider. The division factor is controlled by the logical state at Pin MODE. According to chapter `RF Front End', the frequency of the crystal oscillator (fXTO) is defined by the RF input signal (fRFin) which also defines the operating frequency of the local oscillator (fLO). Polling Mode According to figure 5, the receiver stays in polling mode in a continuous cycle of three different modes. In sleep mode, the signal processing circuitry is disabled for the time period TSleep while consuming low current of IS = ISoff. During the start-up period, TStartup, all signal processing circuits are enabled and settled. In the following bitcheck mode, the incoming data stream is analyzed bit by bit contra a valid transmitter signal. If no valid signal is present, the receiver is set back to sleep mode after the period TBitcheck. This period varies check by check as it is a statistical process. An average value for TBitcheck is given in the electrical characteristics. During TStartup and TBitcheck the current consumption is IS = ISon. The average current consumption in polling mode is dependent on the duty cycle of the active mode and can be calculated as: I Spoll + ISoff T Sleep ) ISon (T Startup ) T Bitcheck) T Sleep ) T Startup ) T Bitcheck 7 (24) TClk MODE Divider :14/:10 f XTO 16 DVCC 15 XTO XTO 14 L : USA(:10) H: Europe(:14) Figure 8. Generation of the basic clock cycle Rev. A2, 28-Sep-00 U3745BM During TSleep and TStartup, the receiver is not sensitive to a transmitter signal. To guarantee the reception of a transmitted command, the transmitter must start the telegram with an adequate preburst. The required length of the preburst is dependent on the polling parameters TSleep, TStartup, TBitcheck and the startup time of a connected C (TStart,C). TBitcheck thus depends on the actual bitrate and the number of bits (NBitcheck) to be tested. The following formula indicates how to calculate the preburst length. TPreburst w TSleep + TStartup + TBitcheck + TStart_mC Sleep Mode The length of period TSleep is defined by the 5-bit word Sleep of the OPMODE register, the extension factor XSleep, according to table 10, and the basic clock cycle TClk. It is calculated to be: TSleep = Sleep XSleep 1024 TClk extended to almost half a second by setting XSleep to 8. XSleep can be set to 8 by bit XSleepStd or by bit XSleep Temp resulting in a different mode of action as described below: XSleep Std = 1 implies the standard extension factor. The sleep time is always extended. XSleep Temp = 1 implies the temporary extension factor. The extended sleep time is used as long as every bitcheck is OK. If the bitcheck fails once, this bit is set back to 0 automatically resulting in a regular sleep time. This functionality can be used to save current in presence of a modulated disturber similar to an expected transmitter signal. The connected C is activated rarely in that condition. If the disturber disappears, the receiver switches back to regular polling and is again sensitive to appropriate transmitter signals. According to table 7, the highest register value of Sleep sets the receiver a permanent sleep condition. The receiver remains in that condition until another value for Sleep is programmed into the OPMODE register. This function is desirable where several devices share a single data line. In US- and European applications, the maximum value of TSleep is about 60 ms if XSleep is set to 1. The time resolution is about 2 ms in that case. The sleep time can be 8 (24) Rev. A2, 28-Sep-00 U3745BM Sleep mode: All circuits for signal processing are disabled. Only XTO and Polling logic are enabled. IS = ISon TSleep = Sleep x XSleep x 1024 x TClk Sleep: XSleep: TClk: Start-up mode: The signal processing circuits are enabled. After the start-up time (TStartup) all circuits are in stable condition and ready to receive. IS = ISon TStartup TStartup: 5-bit word defined by Sleep0 to Sleep4 in OPMODE register Extension factor defined by XSleep Std and XSleepTemp according to table 8 Basic clock cycle defined by fXTO and Pin MODE Is defined by the selected baud rate range and TClk. The baud rate range is defined by Baud0 and Baud1 in the OPMODE register. NO Bitcheck mode: The incomming data stream is analyzed. If the timing indicates a valid transmitter signal, the receiver is set to receiving mode. Otherwise it is set to Sleep mode. IS = ISon TBitcheck Bitcheck OK ? YES Receiving mode: The receiver is turned on permanently and passes the data stream to the connected mC. It can be set to Sleep mode through an OFF command via Pin DATA or ENABLE. IS = ISon OFF command TBitcheck: Depends on the result of the bitcheck If the bitcheck is ok, TBitcheck depends on the number of bits to be checked (NBitcheck) and on the utilized data rate. If the bitcheck fails, the average time period for that check depends on the selected baud rate range and on TClk. The baud rate range is defined by Baud0 and Baud1 in the OPMODE register. Figure 9. Polling mode flow chart ( Number of checked Bits: 3 ) Enable IC Bitcheck ok Bitcheck Dem_out 1/2 Bit 1/2 Bit 1/2 Bit 1/2 Bit 1/2 Bit 1/2 Bit DATA Polling - Mode Receiving mode Figure 10. Timing diagram for complete successful bitcheck Rev. A2, 28-Sep-00 9 (24) U3745BM Bitcheck Mode In bitcheck mode, the incoming data stream is examined to distinguish between a valid signal from a corresponding transmitter and signals due to noise. This is done by subsequent time frame checks where the distances between 2 signal edges are continuously compared to a programmable time window. The maximum count of this edge-to-edge tests before the receiver switches to receiving mode is also programmable. Configuring the Bitcheck Assuming a modulation scheme that contains 2 edges per bit, two time frame checks are verifying one bit. This is valid for Manchester, Bi-phase and most other modulation schemes. The maximum count of bits to be checked can be set to 0, 3, 6 or 9 bits via the variable NBitcheck in the OPMODE register. This implies 0, 6, 12 and 18 edgeto-edge checks respectively. If NBitcheck is set to a higher value, the receiver is less likely to switch to receiving mode due to noise. In the presence of a valid transmitter signal, the bitcheck takes less time if NBitcheck is set to a lower value. In polling mode, the bitcheck time is not dependent on NBitcheck. Figure 10 shows an example where 3 bits are tested successfully and the data signal is transferred to Pin DATA. According to figure 11, the time window for the bitcheck is defined by two separate time limits. If the edge-to-edge time tee is in between the lower bitcheck limit TLim_min and the upper bitcheck limit TLim_max, the check will be continued. If tee is smaller than TLim_min or tee exceeds TLim_max, the bitcheck will be terminated and the receiver switches to sleep mode. 1/fSig For best noise immunity it is recommended to use a low span between TLim_min and TLim_max. This is achieved using a fixed frequency at a 50% duty cycle for the transmitter preburst. A `11111...' or a `10101...' sequence in Manchester or Bi-phase is a good choice concerning that advice. A good compromise between receiver sensitivity and susceptibility to noise is a time window of 25% regarding the expected edge-to-edge time tee. Using preburst patterns that contain various edge-to-edge time periods, the bitcheck limits must be programmed according to the required span. The bitcheck limits are determined by means of the formula below: TLim_min = Lim_min x TXClk TLim_max = (Lim_max -1) x TXClk Lim_min and Lim_max are defined by a 5-bit word each within the LIMIT register. Using above formulas, Lim_min and Lim_max can be determined according to the required TLim_min, TLim_max and TXClk. The time resolution when defining TLim_min and TLim_max is TXClk. The minimum edge-to-edge time tee (tDATA_L_min, tDATA_H_min) is defined according to the chapter `Receiving Mode'. Due to this, the lower limit should be set to Lim_min 10. The maximum value of the upper limit is Lim_max = 63. Figures 12, 13 and 14 illustrate the bitcheck for the default bitcheck limits Lim_min = 14 and Lim_max = 24. When the IC is enabled, the signal processing circuits are enabled during TStartup. The output of the demodulator (Dem_out) is undefined during that period. When the bitcheck becomes active, the bitcheck counter is clocked with the cycle TXClk. Figure 12 shows how the bitcheck proceeds if the bitcheck counter value CV_Lim is within the limits defined by Lim_min and Lim_max at the occurrence of a signal edge. In figure 14, the bitcheck fails as the value CV_lim is lower than the limit Lim_min. The bitcheck also fails if CV_Lim reaches Lim_max. This is illustrated in figure 15. Bitcheck ok Bitcheck ok Dem_out t ee TLim_min TLim_max Figure 11. Valid time window for bitcheck ( Lim_min = 14, Lim_max = 24 ) Enable IC TStartup Bitcheck 1/2 Bit Dem_out 1/2 Bit 1/2 Bit Bitcheck-Counter 0 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1234 TXClk Figure 12. Timing diagram during bitcheck 10 (24) Rev. A2, 28-Sep-00 U3745BM ( Lim_min = 14, Lim_max = 24 ) Enable IC Bitcheck failed ( CV_Lim < Lim_min ) Bitcheck Dem_out 1/2 Bit Bitcheck-Counter 0 1 2 3 4 5 6 1 2 3 4 5 6 7 8 9 10 11 12 0 Startup - Mode Bitcheck - Mode Sleep-Mode Figure 13. Timing diagram for failed bitcheck (condition: CV_Lim < Lim_min) ( Lim_min = 14, Lim_max = 24 ) Enable IC Bitcheck failed ( CV_LimwLim_max ) Bitcheck Dem_out 1/2 Bit Bitcheck-Counter 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 0 Startup - Mode Bitcheck - Mode Sleep-Mode Figure 14. Timing diagram for failed bitcheck (condition: CV_Lim Lim_max) Duration of the Bitcheck If no transmitter signal is present during the bitcheck, the output of the demodulator delivers random signals. The bitcheck is a statistical process and TBitcheck varies for each check. Therefore, an average value for TBitcheck is given in the electrical characteristics. TBitcheck depends on the selected baudrate range and on TClk. A higher baudrate range causes a lower value for TBitcheck resulting in a lower current consumption for polling mode. In the presence of a valid transmitter signal, TBitcheck is dependant on the frequency of that signal, fSig and the count of the checked bits, NBitcheck. A higher value for NBitcheck thereby results in a longer period for TBitcheck requiring a higher value for the transmitter pre-burst TPreburst. Receiving Mode If the bitcheck has been successful for all bits specified by NBitcheck, the receiver switches to receiving mode. According to figure 11, the internal data signal is switched to Pin DATA in that case. A connected C can be woken up by the negative edge at Pin DATA. The receiver stays in that condition until it is switched back to polling mode explicitly. Digital Signal Processing The data from the demodulator (Dem_out) is digitally processed in different ways and as a result converted into the output signal data. This processing depends on the selected baudrate range (BR_Range). Figure 15 illustrates how Dem_out is synchronized by the extended clock cycle TXClk. This clock is also used for the Bitcheck counter. Data can change its state only after TXClk elapsed. The edge-to-edge time period tee of the Data signal as a result is always an integral multiple of TXClk. The minimum time period between two edges of the data signal is limited to tee TDATA_min. This implies an efficient suppression of spikes at the DATA output. At the same time, it limits the maximum frequency of edges at DATA. This eases the interrupt handling of a connected C. TDATA_min is to some extent affected by the preceding edge-to-edge time interval tee as illustrated in figure 16. If tee is in between the specified bitcheck limits, the following level is frozen for the time period TDATA_min = tmin1, in case of tee being outside that bitcheck limits TDATA_min = tmin2 is the relevant stable time period. The maximum time period for DATA to be Low is limited to TDATA_L_max. This function ensures a finite response time during programming or switching off the receiver via Pin DATA. TDATA_L_max is thereby longer than the maximum time period indicated by the transmitter data stream. Figure 17 gives an example where Dem_out remains Low after the receiver has switched to receiving mode. Rev. A2, 28-Sep-00 11 (24) U3745BM T XClk Clock Bitcheck counter Dem_out DATA t ee Figure 15. Synchronization of the demodulator output Dem_out DATA Lim_min CV_Lim < Lim_max t ee CV_Lim < Lim_min or CV_Lim Lim_max t ee tmin2 tmin1 Figure 16. Debouncing of the demodulator output Enable IC Bitcheck Dem_out DATA Sleep - Mode Bitcheck - Mode Receiving mode tmin2 t DATA_L_max Figure 17. Steady L state limited DATA output pattern after transmission After the end of a data transmission, the receiver remains active and random noise pulses appear at Pin DATA. The edge-to-edge time period tee of the majority of these noise pulses is equal to or slightly higher than TDATA_min. Switching the Receiver Back to Sleep Mode The receiver can be set back to polling mode via Pin DATA or via Pin ENABLE. When using Pin DATA, this pin must be pulled to Low for the period t1 by the connected C. Figure 18 illustrates the timing of the OFF command (see also figure 22). The minimum value of t1 depends on BR_Range. The maximum value for t1 is not limited but it is recommended not to exceed the specified value to prevent erasing the reset marker. This item is explained in more detail in the chapter `Configuration of the Receiver'. Setting the receiver to sleep mode via DATA is achieved by programming bit 1 of the OPMODE register to be `1'. Only one sync pulse (t3) is issued. The duration of the OFF command is determined by the sum of t1, t2 and t10. After the OFF command, the sleep time TSleep elapses. Note that the capacitive load at Pin DATA is limited. The resulting time constant t together with an optional external pull-up resistor may not be exceeded to ensure proper operation. If the receiver is set to polling mode via Pin ENABLE, an `L' pulse (TDoze) must be issued at that pin. Figure 19 illustrates the timing of that command. After the positive edge of this pulse, the sleep time TSleep elapses. The receiver remains in sleep mode as long as ENABLE is held to `L'. If the receiver is polled exclusively by a C, TSleep can be programmed to 0 to enable a instantaneous response time. This command is the faster option than via Pin DATA at the cost of an additional connection to the C. 12 (24) Rev. A2, 28-Sep-00 U3745BM t1 t2 t3 t4 t10 t7 t5 Out1 (mC) DATA (U3745BM) X X Serial bi-directional data line X Bit 1 ("1") (Startbit) T Sleep OFF Command X Receiver on Startup mode Figure 18. Timing diagram of the OFF-command via Pin DATA TDoze TSleep toff ENABLE DATA (U3745BM) X X Serial bi-directional data line X X Receiver on Startup mode Figure 19. Timing diagram of the OFF-command via Pin ENABLE Configuration of the Receiver The U3745BM receiver is configured via two 12-bit RAM registers called OPMODE and LIMIT. The registers can be programmed by means of the bi-directional DATA port. If the register contents have changed due to a voltage drop, this condition is indicated by a certain output pattern called reset marker (RM). The receiver must be reprogrammed in that case. After a power-on reset (POR), the registers are set to default mode. If the receiver is operated in default mode, there is no need to program the registers. Table 3 shows the structure of the registers. According to table 2, bit 1 defines if the receiver is set back to polling mode via the OFF command, (see chapter `Receiving Mode') or if it is programmed. Bit 2 represents the register address. It selects the appropriate register to be programmed. Table 2. Effect of Bit 1 and Bit 2 in programming the registers Bit 1 Bit 2 1 0 0 x 1 0 Action The receiver is set back to polling mode (OFF command) The OPMODE register is programmed The LIMIT register is programmed Table 4 and the following illustrate the effect of the individual configuration words. The default configuration is highlighted for each word. BR_Range sets the appropriate baud rate range. At the same time it defines XLim. XLim is used to define the bitcheck limits TLim_min and TLim_max as shown in table 4. POUT can be used to control the sensitivity of the receiver. In that application, POUT is set to 1 to reduce the sensitivity. This implies that the receiver operates with full sensitivity after a POR. Rev. A2, 28-Sep-00 13 (24) U3745BM Table 3. Effect of the configuration words within the registers Bit1 1 OPMODE register 0 0 1 1 0 BR_Range Baud1 Baud0 0 1 Lim_min Lim_min5 0 Lim_min4 0 Lim_min3 1 Lim_min2 1 Lim_min1 1 Lim_min0 0 Lim_max5 0 Lim_max4 1 1 NBitcheck BitChk1 BitChk0 0 VPOUT POUT 0 Sleep4 0 Sleep3 1 Sleep Sleep2 0 Sleep1 1 Lim_max Lim_max3 Lim_max2 0 Lim_max1 0 Lim_max0 0 Sleep0 1 0 XSleep XSleep Std XSleep Temp 0 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit8 Bit9 Bit10 Bit11 Bit12 Bit13 Bit14 OFF command (Default) LIMIT register 0 0 0 0 (Default) Table 4. Effect of the configuration word BR_Range BR_Range Baudrate Range / Extension Factor for Bitcheck Limits (XLim) Baud1 Baud0 0 0 BR_Range0 (application USA / Europe: BR_Range0 = 1.0 kBaud to 1.8 kBaud) (Default) 0 1 1 1 0 1 XLim = 8 (Default) BR_Range1 (application USA / Europe: BR_Range1 = 1.8 kBaud to 3.2 kBaud) XLim = 4 BR_Range2 (application USA / Europe: BR_Range2 = 3.2 kBaud to 5.6 kBaud) XLim = 2 BR_Range3 (Application USA / Europe: BR_Range3 = 5.6 kBaud to 10 kBaud) XLim = 1 Table 5. Effect of the configuration word NBitcheck NBitcheck BitChk1 0 0 1 1 BitChk0 0 1 0 1 Number of Bits to be Checked 0 3 6 (Default) 9 Table 6. Effect of the configuration Bit VPOUT VPOUT POUT 0 1 Level of the Multi-Purpose Output Port POUT 0 (Default) 1 14 (24) Rev. A2, 28-Sep-00 U3745BM Table 7. Effect of the configuration word Sleep Sleep Sleep4 0 0 0 0 . . . 0 . . . 1 1 1 Sleep3 0 0 0 0 . . . 1 . . . 1 1 1 Sleep2 0 0 0 0 . . . 0 . . . 1 1 1 Sleep1 0 0 1 1 . . . 1 . . . 0 1 1 Sleep0 0 1 0 1 . . . 1 . . . 1 0 1 Start Value for Sleep Counter (TSleep = Sleep x Xsleep x 1024 x TClk) 0 (Receiver is continuously polling until a valid signal occurs) 1 (TSleep 2ms for XSleep =1 in US- / European applications) 2 3 . . . 11 (USA: TSleep = 22.96 ms, Europe: TSleep = 23.31 ms) (Default) . . . 29 30 31 (Permanent sleep mode) Table 8. Effect of the configuration word XSleep XSleep XSleepStd XSleepTemp 0 0 0 1 1 0 1 1 Extension Factor for Sleep Time (TSleep = Sleep x Xsleep x 1024 x TClk) 1 (Default) 8 (XSleep is reset to 1 if bitcheck fails once) 8 (XSleep is set permanently) 8 (XSleep is set permanently) Table 9. Effect of the configuration word Lim_min Lim_min Lim_min < 10 is not applicable 0 0 1 0 0 0 1 0 0 0 1 1 0 0 1 1 0 0 1 1 . . . 1 1 1 . . . 1 1 1 . . . 1 1 1 . . . 1 1 1 1 1 0 0 1 . . . 0 1 1 0 1 0 1 0 . . . 1 0 1 Lower Limit Value for Bitcheck (TLim_min = Lim_min x XLim x TClk) 10 11 12 13 14 (Default) (USA: TLim_min = 228 s, Europe: TLim_min = 232 s) 61 62 63 Rev. A2, 28-Sep-00 15 (24) U3745BM Table 10. Effect of the configuration word Lim_max Lim_max Lim_max < 12 is not applicable 0 0 1 1 0 0 1 1 0 0 1 1 . . . . . . 0 . . . 1 1 1 . . 1 . . . 1 1 1 . . 1 . . . 1 1 1 . . 0 . . . 1 1 1 0 0 1 . . . 0 . . . 0 1 1 0 1 0 . . . 0 . . . 1 0 1 61 62 63 24 (Default) (USA: TLim_max = 375 s, Europe: TLim_max = 381 s) Upper Limit Value for Bitcheck (TLim_max = (Lim_max -1) x XLim x TClk) 12 13 14 Conservation of the Register Information The U3745BM has an integrated power-on reset and brown-out detection circuitry to provide a mechanism to preserve the RAM register information. According to figure 20, a power-on reset (POR) is generated if the supply voltage VS drops below the threshold voltage VThReset. The default parameters are programmed into the configuration registers in that condition. Once VS exceeds VThReset, the POR is canceled after the minimum reset period tRst. A POR is also generated when the supply voltage of the receiver is turned on. To indicate that condition, the receiver displays a reset marker (RM) at Pin DATA after a reset. The RM is repre- sented by the fixed frequency fRM at a 50% duty cycle. RM can be canceled via an `L' pulse t1 at Pin DATA. The RM implies the following characteristics: D fRM is lower than the lowest feasible frequency of a data signal. By this means, RM cannot be misinterpreted by the connected C. D If the receiver is set back to polling mode via pin DATA, RM cannot be canceled by accident if t1 is applied according to the proposal in the section `Programming the configuration registers'. By means of that mechanism, the receiver cannot lose its register information without communicating that condition via the reset marker RM. V S V ThReset POR t Rst DATA (U3745BM) X 1 / f RM Figure 20. Generation of the power-on reset 16 (24) Rev. A2, 28-Sep-00 U3745BM t1 t2 t3 t4 t6 t7 t5 t8 t9 TSleep Out1 (mC) DATA (U3745BM) X X Serial bi-directional data line X Bit 1 ("0") (Startbit) Bit 2 ("1") (Register- select) Programming Frame Bit 13 ("0") (Poll8) Bit 14 ("1") (Poll8R) X Receiver on Startup mode Figure 21. Timing of the register programming Programming the Configuration Register The configuration registers are programmed serially via the bi-directional data line according to figure 21 and figure 22. U3741BM mC Programming of a register is possible both during sleep- and active mode of the receiver. During programming, the LNA, LO, lowpass filter, IFamplifier and the demodulator are disabled. The programming start pulse t1 initiates the programming of the configuration registers. If bit 1 is set to `1', it represents the OFF-command to set the receiver back to polling mode at the same time. For the length of the programming start pulse t1, the following convention should be considered: internal pull-up resistor bi-directional data-line DATA Data (U3741BM) I/O Out1 ( m C) D t1(min) < t1 < 1535 x TClk: [t1(min) is the minimum specified value for the relevant BR_Range] Programming (respectively OFF-command) is initiated if the receiver is not in reset mode. If the receiver is in reset mode, programming (respectively Off-command) is not initiated, and the reset marker RM is still present at Pin DATA. This period is generally used to switch the receiver to polling mode. In a reset condition, RM is not canceled by accident. D t1 > 5632 x TClk Programming (respectively OFF-command) is initiated in any case. RM is canceled if present. This period is used if the connected C detected RM. If a configuration register is programmed, this time period for t1 can generally be used. Note that the capacitive load at Pin DATA is limited. The resulting time constant t together with an optional external pull-up resistor may not be exceeded to ensure proper operation. 17 (24) Figure 22. One wire connection to a mC To start programming, the serial data line DATA is pulled to `L' for the time period t1 by the C. When DATA has been released, the receiver becomes the master device. When the programming delay period t2 has elapsed, it emits 14 subsequent synchronization pulses with the pulse length t3. After each of these pulses, a programming window occurs. The delay until the program window starts is determined by t4, the duration is defined by t5. Within the programming window, the individual bits are set. If the C pulls down Pin DATA for the time period t7 during t5, the according bit is set to `0'. If no programming pulse t7 is issued, this bit is set to `1'. All 14 bits are subsequently programmed in this way. The time frame to program a bit is defined by t6. Bit 14 is followed by the equivalent time window t9. During this window, the equivalent acknowledge pulse t8 (E_Ack) occurs if the just programmed modeword is equivalent to the modeword that was already stored in that register. E_Ack should be used to verify that the modeword was correctly transferred to the register. The register must be programmed twice in that case. Rev. A2, 28-Sep-00 U3745BM Absolute Maximum Ratings Parameters Supply voltage Power dissipation Junction temperature Storage temperature Ambient temperature Maximum input level, input matched to 50 W Symbol VS Ptot Tj Tstg Tamb Pin_max Min. Typ. Max. 6 450 150 +125 +85 10 Unit V mW C C C dBm -55 -40 Thermal Resistance Parameters Junction ambient Symbol RthJA Value 100 Unit K/W Electrical Characteristics All parameters refer to GND, VS = 5 V, Tamb = 25C, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. The possible operating range refer to different circuit conditions: VS = 4.5 V to 5.5 V, Tamb = -40C to +85C Parameters Current consumption Test Conditions / Pins Sleep mode (XTO and polling logic active) IC active (startup-, bitcheck-, receiving mode) Pin DATA = H Symbol ISoff ISon Min. Typ. 190 7.0 Max. 350 8.6 Unit A AAAAAAAAAAAAAA AA AA A AAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAA AAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAA A A AAAA A A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A AA AA AA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AA AA AA A AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A AA AA A AAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AA A mA LNA mixer Third-order intercept point LNA/ mixer/ IF amplifier input matched according to figure 6 IIP3 -28 dBm LO spurious emission @ RFIn Input matched according to figure 6, required according to I-ETS 300220 ISLORF -73 -57 dBm Noise figure LNA and mixer (DSB) LNA_IN input impedance Input matching according to figure 6 @ 433.92 MHz @ 315 MHz NF 7 dB ZiLNA_IN IP1db 1.0 || 1.56 1.3 || 1.0 -40 k || pF k || pF dBm 1 dB compression point (LNA, mixer, IF amplifier) Maximum input level Input matched according to figure 6, referred to RFin Input matched according to figure 6, BER 10-3, ASK mode Pin_max -23 dBm dBm Local oscillator Operating frequency range VCO fVCO 309 439 MHz 18 (24) Rev. A2, 28-Sep-00 AAA AA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA A A A AA A A AA A AAAAAAAAAAAAAAAAAAAAAA AAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A Capacitive load at Pin LF Loop bandwidth of the PLL Parameters The capacitive load at Pin LF is limited if bitcheck is used. The limitation therefore also applies to self polling. For best LO noise (design parameter) R1 = 820 W C9 = 4.7 nF C10 = 1 nF Test Conditions / Pins Symbol CLF_tot BLoop Min. Typ. 100 Rev. A2, 28-Sep-00 Max. 10 U3745BM 19 (24) Unit kHz nF AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A AAA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAA A A A AAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AA AA A AA AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AA AA AAAAAAAAAAA AAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAA AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAA AAAAAAAAAAAA AA A A AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA All parameters refer to GND, VS = 5 V, Tamb = 25C, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. The possible operating range refer to different circuit conditions: VS = 4.5 V to 5.5 V, Tamb = -40C to +85C Electrical Characteristics (continued) U3745BM 20 (24) Minimum edge-to-edge time period of the input data signal for full sensitivity Maximum edge-to-edge time BR_Range0 (Default) period of the input data BR_Range1 signal for full sensitivity BR_Range2 BR_Range3 Recommended CDEM for best performance Lower cut-off frequency of the data filter Dynamic range RSSI ampl. S/N ratio to suppress inband noise signals Sensitivity variation ASK for full operating range including IF filter compared to Tamb = 25C, VS = 5 V Input sensitivity ASK 600-kHz IF filter Analog signal processing Static capacitance at Pin XT0 Series resonance resistor of the crystal XTO operating frequency Parameters fcu_DF + BR_Range0 (Default) BR_Range1 BR_Range2 BR_Range3 CDEM = 33 nF ASK mode BR_Range0 (Default) BR_Range1 BR_Range2 BR_Range3 ASK mode 600-kHz version fin = 433.92 MHz/ 315 MHz fIF = 0.81 MHz to 1.19 MHz fIF = 0.75 MHz to 1.25 MHz PASK = PRef_ASK + DPRef BR_Range3 BR_Range2 BR_Range1 BR_Range0 Input matched according to figure 6 ASK (level of carrier) BER 10-3, B = 600 kHz fin = 433.92 MHz/ 315 MHz T = 25C, VS = 5 V fIF = 1 MHz fXTO = 6.764 MHz 4.906 MHz 4.90625 MHz XTO crystal frequency, appropriate load capacitance must be connected to XTAL 6.764375 MHz Test Conditions / Pins 2 p 1 30kW CDEM PRef_ASK SNRASK DRRSSI Symbol CDEM DPRef fcu_DF tee_sig tee_sig CXT0 fXTO RS 6.764375 -50 ppm 4.90625 -50 ppm -104.5 -102 -104 -106 Min. 0.11 +3 +5 6.764375 4.90625 -108.5 -106 -108 -110 0.16 Typ. 39 22 12 8.2 60 11 6.764375 +50 ppm 4.90625 +50 ppm Rev. A2, 28-Sep-00 -109.5 -111.5 -113.5 1000 560 320 180 0.20 150 220 6.5 Max. -112 270 156 89 50 MHz MHz dBm dBm dBm dBm Unit kHz dB dB dB dB nF nF nF nF pF ms ms ms ms ms ms ms ms W W U3745BM Electrical Characteristics (continued) All parameters refer to GND, VS = 5 V, Tamb = 25C, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. The possible operating range refer to different circuit conditions: VS = 4.5 V to 5.5 V, Tamb = -40C to +85C A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA AAAAA A AAAA A AAAAAAAA AAAA A AAA A AAAAAAAAAAA AA A A A A A AA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A A A AA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A AAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAA A AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A A AAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA AA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A Threshold voltage for reset VThRESET 1.95 2.8 3.75 V Parameters Test Conditions / Pins Symbol Min. Typ. Max. Unit Digital ports Data output - Saturation voltage LOW - Internal pull-up resistor - Maximum time constant - Maximum capacitive load POUT output - Saturation voltage LOW - Saturation voltage HIGH ASK input - High-level input voltage ENABLE input - Low-level input voltage - High-level input voltage MODE input - Low-level input voltage - High-level input voltage TEST input - Low-level input voltage Parameter Iol = 1 mA t = CL (Rpup//RExt) without ext. pull-up resistor Rext = 5 kW VOI RPup t CL CL VOl VOh VIh VIl VIh VIl VIh VIl 39 0.08 50 0.3 61 2.5 41 540 0.3 V kW ms pF pF V V V V V V V V IPOUT = 1 mA IPOUT = -1 mA ASK VS-0.3V 0.8 x VS 0.08 VS-0.14V Idle mode Active mode 0.8 x VS 0.2 x VS Division factor = 10 Division factor = 14 0.8 x VS 0.2 x VS Test input must always be set to LOW Symbol 6.76438-MHz Osc. (MODE: 1) Min. Typ. Max. 0.2 x VS Test Condition 4.90625-MHz Osc. (MODE: 0) Min. Typ. Max. 2.0383 Variable Oscillator Typ. Unit Min. Max. Basic clock cycle of the digital circuitry Basic clock MODE = 0 (USA) TClk cycle MODE = 1 (Europe) Extended BR_Range0 TXClk basic clock BR_Range1 cycle BR_Range2 BR_Range3 Polling mode Sleep time Sleep and XSleep are defined in the OPMODE register BR_Range0 BR_Range1 BR_Range2 BR_Range3 Average bitcheck time while polling BR_Range0 BR_Range1 BR_Range2 BR_Range3 Bitcheck time for a valid input signal fSig NBitcheck = 0 NBitcheck = 3 NBitcheck = 6 NBitcheck = 9 TSleep 2.0697 16.6 8.3 4.1 2.1 Sleep x XSleep x 1024 x 2.0697 1855 1061 1061 663 16.3 8.2 4.1 2.0 Sleep x XSleep x 1024 x 2.0383 1827 1045 1045 653 1/(f XTO/10) 1/(f XTO/14) 8 x TClk 4 x TClk 2 x TClk 1 x TClk Sleep x XSleep x 1024 x TClk 896.5 512.5 512.5 320.5 x TClk s s s s s s ms Start-up time TStartup s s s s s Time for Bitcheck TBitcheck 0.45 0.24 0.14 0.14 TBitcheck TXClk 3/fSig 6/fSig 9/fSig 3.5/fSig 6.5/fSig 9.5/fSig 3/fSig 6/fSig 9/fSig 3.5/fSig 6.5/fSig 9.5/fSig 3.5/fSig 6.5/fSig 9.5/fSig 0.47 0.26 0.16 0.15 ms ms ms ms ms ms ms ms Rev. A2, 28-Sep-00 21 (24) U3745BM Electrical Characteristics (continued) All parameters refer to GND, VS = 5 V, Tamb = 25C, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. The possible operating range refer to different circuit conditions: VS = 4.5 V to 5.5 V, Tamb = -40C to +85C Parameter Test Condition Symbol 6.76438-MHz Osc. (MODE: 1) Min. Typ. Max. 4.90625-MHz Osc. (MODE: 0) Min. Typ. Max. Variable Oscillator Min. Typ. Max. Unit Receiving mode Intermediate frequency fIF MODE=0 (USA) MODE=1 (Europe) BR_Range0 BR_Range1 BR_Range2 BR_Range3 1.0 1.0 BR_Range 1.0 1.8 3.2 5.6 1.8 3.2 5.6 10.0 1.0 1.8 3.2 5.6 1.8 3.2 5.6 10.0 fXTO x 64 / 314 fXTO x 64 / 432.92 BR_Range0 x 2 s / TClk BR_Range1 x 2 s / TClk BR_Range2 x 2 s / TClk BR_Range3 x 2 s / TClk MHz MHz kBau d kBau d kBau d kBau d s s s s s s s s s s s s s Baud rate range Minimum time period BR_Range0 between edges at Pin DATA BR_Range1 (figure 16) BR_Range2 BR_Range3 Maximum BR_Range0 low period at BR_Range1 DATA BR_Range2 (figure 17) BR_Range3 OFF command at Pin ENABLE (figure 19) Configuration of the receiver Frequency of the reset marker (figure 20) Programming start pulse (figure 18, figure 21) Programming delay period (figure 18, figure 21) Synchroni- zation pulse (figure 18, figure 21) Delay until the program window starts (figure 18, figure 21) Programming window (figure 18, figure 21) Time frame of a bit (figure 21) Programming pulse (figure 18, figure 21) TDATA_min tmin1 tmin2 tmin1 tmin2 tmin1 tmin2 tmin1 tmin2 TDATA_L_ max 149 182 75 91 37.3 45.5 18.6 22.8 2169 1085 542 271 3.1 3.05 147 179 73 90 36.7 44.8 18.3 22.4 2136 1068 534 267 1.5 x TClk 9 x TXClk 11 x TXCl 9 x TXClk 11 x TXClk 9 x TXClk 11 x TXClk 9 x TXClk 11 x TXClk 131 x TXClk 131 x TXClk 131 x TXClk 131 x TXClk tDoze fRM 117.9 119.8 1 4096 T Clk 1535 x TClk 1535 x TClk 1535 x TClk 1535 x TClk 385.5 x TClk 128 x TClk Hz BR_Range0 BR_Range1 BR_Range2 BR_Range3 after POR t1 t2 2188 1104 561 290 11656 795 3176 3176 3176 3176 798 2155 1087 553 286 11479 783 3128 3128 3128 3128 786 1057 x TClk 533 x TClk 271 x TClk 140 x TClk 5632 x TClk 384.5 x TClk s s t3 265 261 s t4 131 129 63.5 x TClk s t5 530 522 256 x TClk s t6 1060 1044 512 x TClk s t7 133 529 131 521 64 x TClk 256 x TClk s 22 (24) Rev. A2, 28-Sep-00 U3745BM Electrical Characteristics (continued) All parameters refer to GND, VS = 5 V, Tamb = 25C, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. The possible operating range refer to different circuit conditions: VS = 4.5 V to 5.5 V, Tamb = -40C to +85C Parameter Test Condition Symbol 6.76438 MHz Osc. (MODE: 1) Min. Typ. Max. 265 4.90625 MHz Osc. (MODE: 0) Min. Typ. Max. 261 Variable Oscillator Min. Typ. 128 x TClk Max. s Unit Equivalent acknowledge pulse: E_Ack (figure 21) Equivalent time window (figure 21) OFF-bit programming window (figure 18) t8 t9 534 526 258 x TClk s t10 930 916 449.5 x TClk s Package Information Package SO20 Dimensions in mm 12.95 12.70 9.15 8.65 7.5 7.3 2.35 0.4 1.27 11.43 20 11 0.25 0.10 0.25 10.50 10.20 technical drawings according to DIN specifications 13038 1 10 Rev. A2, 28-Sep-00 23 (24) U3745BM Ozone Depleting Substances Policy Statement It is the policy of Atmel Germany GmbH to 1. Meet all present and future national and international statutory requirements. 2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances (ODSs). The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs and forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these substances. Atmel Germany GmbH has been able to use its policy of continuous improvements to eliminate the use of ODSs listed in the following documents. 1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively 2. Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental Protection Agency (EPA) in the USA 3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively. Atmel Germany GmbH can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances. 12. We reserve the right to make changes to improve technical design and may do so without further notice. Parameters can vary in different applications. All operating parameters must be validated for each customer application by the customer. Should the buyer use Atmel Wireless & Microcontrollers products for any unintended or unauthorized application, the buyer shall indemnify Atmel Wireless & Microcontrollers against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. Data sheets can also be retrieved from the Internet: http://www.atmel-wm.com Atmel Germany GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany Telephone: 49 (0)7131 67 2594, Fax number: 49 (0)7131 67 2423 24 (24) Rev. A2, 28-Sep-00 |
Price & Availability of U3745BM
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |