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TVP5154 4 Channel Low Power PAL/NTSC/SECAM Video Decoder With Independent Scalers, Fast Lock
SLES163 - MARCH 2006
1
1.1
*
Introduction
Features
* Internal Phase-Locked Loop (PLL) for Line-Locked Clock (separate for each channel) and Sampling Sub-Carrier Genlock Output for Synchronizing Color Sub-Carrier of External Encoder Standard Programmable Video Output Format - ITU-R BT.656, 8-bit 4:2:2 With Embedded Syncs - 8-Bit 4:2:2 With Discrete Syncs Advanced Programmable Video Output Formats - 2x Over-Sampled Raw VBI Data During Active Video - Sliced VBI Data During Horizontal Blanking or Active Video VBI Modes Supported - Teletext (NABTS, WST) - Closed-Caption Decode With FIFO, and Extended Data Services (EDS) - Wide Screen Signaling (WSS), Video Program System (VPS), CGMS, Vertical Interval Time Code (VITC) - Gemstar 1x/2x Electronic Program Guide Compatible Mode - Custom Configuration Mode That Allows the User to Program the Slice Engine for Unique VBI Data Signals Improved Fast Lock Mode Which can be Used When the Input VideoStandard is Known, and the Signals on the Switching Channels are Clean 4 Possible I2C Addresses Allowing 16 Decoder Channels on a Single I2C Bus
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4 Separate Video Decoder Channels Having the Following Features for Each Channel. - Accepts NTSC (M, 4.43), PAL (B,D,G,H,I,M,N) and SECAM (B, D, G, K, K1, L) Video Data - Supports ITU-R BT.601 Standard Sampling - High-Speed 9-Bit ADC - Two Composite Inputs or One S-video Input (for each channel) - Fully Differential CMOS Analog Preprocessing Channels With Clamping and Automatic Gain Control (AGC) for Best Signal to Noise (SNR) Performance - Brightness, Contrast, Saturation, Hue, and Sharpness Control Through I2C - Complementary 4-line (3-H delay) Adaptive Comb Filters for Both Cross-Luminance and Cross-Chrominance Noise Reduction - Patented Architecture for Locking to Weak, Noisy, or Unstable Signals 4 Independent Polymorphic Scalers Single or Concurrent Scaled and Unscaled Outputs via Dual Clocking Data, Interleaved 54 MHz Data or Single 27 MHz Clock Scaled/Unscaled Image Toggle Mode Giving Variable Field Rate for Both Scaled and Unscaled Video Low Power Consumption: 700 mW Typical 128-Pin TQFP Package Single 14.31818-MHz Crystal for all Standards and all Channels
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1.2
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Applications
The following is a partial list of suggested applications: - Security Camera Systems - Large Format Video Wall Displays - Games Systems
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this document.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 2006, Texas Instruments Incorporated
TVP5154 4 Channel Low Power PAL/NTSC/SECAM Video Decoder With Independent Scalers, Fast Lock
SLES163 - MARCH 2006
www.ti.com
1.3
Description
The TVP5154 device is a 4 channel, low power NTSC/PAL/SECAM video decoder. Available in a space saving 128-pin TQFP package, each channel of the TVP5154 decoder converts NTSC, PAL, or SECAM video signals to 8-bit ITU-R BT.656 format. Discrete syncs are also available. All 4 channels of the TVP5154 are independently controllable. The decoders share one crystal for all channels and for all supported standards. The TVP5154 can be programmed using a single I2C serial interface. The decoder uses a 1.8-V supply for its analog and digital supplies, and a 3.3-V supply for its I/O. The optimized architecture of the TVP5154 decoder allows for low-power consumption. The decoder consumes less than 720 mW of power in typical operation. Each channel of the TVP5154 is an independent video decoder with a programmable polymorphic scaler. Each channel converts baseband analog video into digital YCbCr 4:2:2 component video which can then be scaled down to any resolution to 1/256 vertical and 15-bit horizonal in 2 pixel decrements. Composite and S-video inputs are supported. Each channel includes one 9-bit analog-to-digital converter (ADC) with 2x sampling. Sampling is ITU-R BT.601 (27.0 MHz, generated from a single 14.31818-MHz crystal or oscillator input) and is line-locked. The output formats can be 8-bit 4:2:2 with discrete syncs or 8-bit ITU-R BT.656 with embedded synchronization. The TVP5154 utilizes Texas Instruments patented technology for locking to weak, noisy, or unstable signals. A real-time control (RTC) output is generated for each channel for synchronizing downstream video encoders. Complementary 4-line adaptive comb filtering is available per channel for both the luma and chroma data paths to reduce both cross-luma and cross-chroma artifacts; a chroma trap filter is also available. An improved fast lock mode can be used when the input video standard is known, and the signals on the switching channels are clean. Note, switching from snow and/or noisy channels to good channels will take longer. In fast lock mode video lock is achieved in 3 fields or less. Video characteristics including hue, contrast, brightness, saturation, and sharpness may be independently programmed for each channel using the industry standard I2C serial interface. The TVP5154 generates synchronization, blanking, lock, and clock signals in addition to digital video outputs for each channel. The TVP5154 includes methods for advanced vertical blanking interval (VBI) data retrieval. The VBI data processor slices, parses, and performs error checking on teletext, closed caption, and other data in several formats. I2C commands can be sent to one or more decoder cores simultaneously, reducing the amount of I2C activity necessary to configure each core. A register controls which decoder core receives I2C commands, and can be configured such that all 4 decoders receive commands at the same time. The main blocks for each of the channels of the TVP5154 decoder include: * Robust sync detector * ADC with analog processor * Y/C separation using 4-line adaptive comb filter * Independent, concurrent scaler outputs * Chrominance processor * Luminance processor * Video clock/timing processor and power-down control * I2C interface * VBI data processor
1.3.1
* * *
2
Related Products
TVP5150 TVP5150AM1 TVP5145
Introduction
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TVP5154 4 Channel Low Power PAL/NTSC/SECAM Video Decoder With Independent Scalers, Fast Lock
SLES163 - MARCH 2006
* * *
TVP5146 TVP5147 TVP5160
1.3.2
Ordering Information
TA 0C to 70C PACKAGED DEVICES 128-Pin TQFP-PowerPAD TVP5154PNP TVP5154PNPR Tray Tape and Reel PACKAGE OPTION
Introduction
3
TVP5154 4 Channel Low Power PAL/NTSC/SECAM Video Decoder With Independent Scalers, Fast Lock
SLES163 - MARCH 2006
www.ti.com
2
Functional Block Diagram
OUTPUT FORMATTER OUTPUT FORMATTER OUTPUT FORMATTER OUTPUT FORMATTER
VBI SLICER
Y/C SEPARATION
AIP1A AIP1B
M U X AGC
9-Bit A/D
LUMINANCE PROCESSING CHROMINANCE PROCESSING
SCALER
CH1_OUT [7:0] YCBCR 8-Bit 4:2:2
VBI SLICER
Y/C SEPARATION
AIP2A AIP2B
M U X
9-Bit A/D AGC
LUMINANCE PROCESSING CHROMINANCE PROCESSING
SCALER
CH2_OUT [7:0] YCBCR 8-Bit 4:2:2
VBI SLICER
Y/C SEPARATION
AIP3A AIP3B
M U X AGC
9-Bit A/D
LUMINANCE PROCESSING CHROMINANCE PROCESSING
SCALER
CH3_OUT [7:0] YCBCR 8-Bit 4:2:2
VBI SLICER
Y/C SEPARATION
AIP4A AIP4B
M U X AGC
9-Bit A/D
LUMINANCE PROCESSING CHROMINANCE PROCESSING
SCALER
CH4_OUT [7:0] YCBCR 8-Bit 4:2:2
SCL SDA
I2C INTERFACE SYNC PROCESSOR HOST PROCESSOR
FID/GLCO[1-4] VSYNC/PAL[1-4] INTERQ/GPCL/BLK[1-4] HSYNC[1-4] AVID[1-4] CLK[1-4] SCLK[1-4]
XIN/OSC XOUT
PLL
Figure 2-1. Functional Block Diagram
4
Functional Block Diagram
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TVP5154 4 Channel Low Power PAL/NTSC/SECAM Video Decoder With Independent Scalers, Fast Lock
SLES163 - MARCH 2006
3
3.1
Terminal Assignments
Pin Out
AGND AVDD REFP1 REFM1 XIN/OSC XOUT PDN RESETB SCL SDA I2CA0 I2CA1 DGND DVDD IOVDD IOGND CH1_OUT0 CH1_OUT1 CH1_OUT2 CH1_OUT3 CH1_OUT4 CH1_OUT5 CH1_OUT6 CH1_OUT7 SCLK1 CLK1 INT1/GPCL1/VBLK1 AVID1 HSYNC1 DGND DVDD IOVDD 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
AI1GND AIP1A AIP1B PLL_VDD PLL_GND REFM2 REFP2 AVDD AGND AI2GND AIP2A AIP2B PLL_VDD PLL_GND AVDD AGND REFM3 REFP3 AVDD AGND AI3GND AIP3A AIP3B PLL_VDD PLL_GND REFM4 REFP4 AVDD AGND AI4GND AIP4A AIP4B
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
TVP5154
128- TQFP Package Pin (Top View)
IOGND VSYNC1/PALI1 FID1/GLCO1 CH2_OUT0 CH2_OUT1 CH2_OUT2 CH2_OUT3 CH2_OUT4 CH2_OUT5 CH2_OUT6 CH2_OUT7 SCLK2 CLK2 INT2/GPCL2/VBLK2 DGND DVDD IOVDD IOGND AVID2 HSYNC2 VSYNC2/PALI2 FID2/GLCO2 CH3_OUT0 CH3_OUT1 CH3_OUT2 CH3_OUT3 CH3_OUT4 CH3_OUT5 CH3_OUT6 CH3_OUT7 DGND DVDD
PLL_VDD PLL_GND AGND TMS FID4/GLCO4 VSYNC4/PALI4 HSYNC4 AVID4 INT4/GPCL4/VBLK4 CLK4 SCLK4 IOGND IOVDD DVDD DGND CH4_OUT7 CH4_OUT6 CH4_OUT5 CH4_OUT4 CH4_OUT3 CH4_OUT2 CH4_OUT1 CH4_OUT0 FID3/GLCO3 VSYNC3/PALI3 HSYNC3 AVID3 INT3/GPCL3/VBLK3 CLK3 SCLK3 IOGND IOVDD
Terminal Assignments
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
5
TVP5154 4 Channel Low Power PAL/NTSC/SECAM Video Decoder With Independent Scalers, Fast Lock
SLES163 - MARCH 2006
www.ti.com
3.2
Terminal Functions
TERMINAL NAME NO. 2 3 I Analog inputs for Channel 1. Connect to the video analog input via 0.1F capacitor. The maximum input range is 0-0.75 VPP, and may require an attenuator to reduce the input amplitude to the desired level. If not used, connect to AGND via 0.1F capacitor. Refer to schematic in Section 12. Analog inputs for Channel 2. Connect to the video analog input via 0.1F capacitor. The maximum input range is 0-0.75 VPP, and may require an attenuator to reduce the input amplitude to the desired level. If not used, connect to AGND via 0.1F capacitor. Refer to schematic in Section 12. Analog inputs for Channel 3. Connect to the video analog input via 0.1F capacitor. The maximum input range is 0-0.75 VPP, and may require an attenuator to reduce the input amplitude to the desired level. If not used, connect to AGND via 0.1F capacitor. Refer to schematic in Section 12. Analog inputs for Channel 4. Connect to the video analog input via 0.1F capacitor. The maximum input range is 0-0.75 VPP, and may require an attenuator to reduce the input amplitude to the desired level. If not used, connect to AGND via 0.1F capacitor. Refer to schematic in Section 12. Analog power supply. Connect to 1.8-V analog supply. Analog power supply return. Connect to analog ground. I/O DESCRIPTION
ANALOG SECTION AIP1A AIP1B
AIP2A AIP2B
11 12
I
AIP3A AIP3B
22 23
I
AIP4A AIP4B
31 32
I
AVDD AGND
8, 15, 19, 28, 127 9, 16, 20, 29, 35, 128 1, 10, 21, 30 5, 14, 25, 34 4, 13, 24, 33 6, 17, 26, 125 7, 18, 27, 126 47, 66, 82, 99, 116 46, 65, 81, 98, 115 44, 63, 79, 96, 113 45, 64, 80, 97, 114 94 75 56 37 101 78 59 40 102 83 60 41
P P
AIxGND PLL_GND PLL_VDD REFMx REFPx DIGITAL SECTION DGND DVDD IOGND IOVDD FID1/GLCO1 FID2/GLCO2 FID3/GLCO3 FID4/GLCO4 AVID1 AVID2 AVID3 AVID4 INTREQ1/GPCL1/VBLK1 INTREQ2/GPCL2/VBLK2 INTREQ3/GPCL3/VBLK3 INTREQ4/GPCL4/VBLK4
P P P I I
Analog input signal return. Connect to analog ground. PLL power supply return. Connect to analog ground. PLL power supply. Connect to 1.8-V analog supply. Reference supply decoupling . Connect to analog ground through a 1F capacitor. Connect to REFPx through a 1F capacitor. Reference supply decoupling . Connect to analog ground through a 1F capacitor. Connect to REFMx through a 1F capacitor. Digital power supply return. Connect to digital ground Digital power supply. Connect to 1.8-V digital supply. IO power supply return. Connect to digital ground. IO power supply. Connect to 3.3-V digital supply 1. FID: Odd/even field indicator or vertical lock indicator. For the odd/even indicator, a 1 indicates the odd field. 2. GLCO: This serial output carries color PLL information. A slave device can decode the information to allow chroma frequency control from the TVP5154 decoder. Data is transmitted at the CLK rate in Genlock mode. Active video indicator. This signal is high during the horizontal active time of the video output.
P P P P O
O
I/O
1. Interrupt request : Open drain when active low. 2. GPCL: General-purpose output. In this mode the state of GPCL is directly programmed via I2C. 3. VBLK: Vertical blank output. In this mode the GPCL terminal is used to indicate the vertical blanking interval of the output video. The beginning and end times of this signal are programmable via I2C
6
Terminal Assignments
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TVP5154 4 Channel Low Power PAL/NTSC/SECAM Video Decoder With Independent Scalers, Fast Lock
SLES163 - MARCH 2006
TERMINAL NAME HSYNC1 HSYNC2 HSYNC3 HSYNC4 VSYNC1 VSYNC2 VSYNC3 VSYNC4 PDN RESETB SCL SDA I2CA0 /PALI1 /PALI2 /PALI3 /PALI4 NO. 100 77 58 39 95 76 57 38 122 121 120 119 118
I/O O Horizontal synchronization signal.
DESCRIPTION
O
1. VSYNC: Vertical synchronization signal 2. PALI: PAL line indicator or horizontal lock indicator. For the PAL line indicator, a 1 indicates a non-inverted line, and a 0 indicates an inverted line. Power-down terminal (active low). A 0 on this pin puts the decoder in standby mode. Preserves the value of the registers. Active-low reset. RESETB can be used only when PDN = 1. When RESETB is pulled low, it resets all the registers, restarts the internal microprocessor. I2C serial clock (open drain) I2C serial data (open drain) During power on reset this pin is sampled along with pin 117 (I2CA1) to determine the I2C address the device will be configured to. A 10-k resistor should pull this either high (to IOVDD) or low to select different I2C device addresses. During power on reset this pin is sampled along with pin 118 (I2CA0) to determine the I2C address the device will be configured to. A 10-k resistor should pull this either high (to IOVDD) or low to select different I2C device addresses. Un-scaled system data clock at either 27 MHz or 54 MHz.
I I I/O I/O I
I2CA1
117
I
CLK1 CLK2 CLK3 CLK4 SCLK1 SCLK2 SCLK3 SCLK4 XIN/OSC XOUT
103 84 61 42 104 85 62 43 124 123
O
O
Scaled system data clock at 27 MHz. This signal can be used to qualify scaled/unscaled data when the un-scaled system data clock is set to 54 MHz.
I O
External clock reference. The user may connect XIN to an oscillator or to one terminal of a crystal oscillator. The user may connect XOUT to the other terminal of the crystal oscillator or not connect XOUT at all. One single 14.31818-MHz crystal or oscillator is needed for ITU-R BT.601 sampling, for all supported standards. Decoded ITU-R BT.656 output/YCbCr 4:2:2 output with discrete sync for channel 1. Decoded ITU-R BT.656 output/YCbCr 4:2:2 output with discrete sync for channel 2. Decoded ITU-R BT.656 output/YCbCr 4:2:2 output with discrete sync for channel 3. Decoded ITU-R BT.656 output/YCbCr 4:2:2 output with discrete sync for channel 4. Test mode select. This pin should be connected to digital ground for correct device operation.
CH1_OUT[7:0] CH2_OUT[7:0] CH3_OUT[7:0] CH4_OUT[7:0] TMS
105-112 86-93 67-74 48-55 36
O O O O I
4
4.1
Functional Discription
Analog Front End
Each channel of the TVP5154 decoder has an analog input channel that accepts two video inputs, which should be ac-coupled through 0.1-F capacitors. The decoder supports a maximum input voltage range of 0.75 V; therefore, an attenuation of one-half is needed for standard input signals with a peak-to-peak variation of 1.5 V. The maximum parallel termination before the input to the device is 75 . Refer to schematic at the end of this document for recommended configuration. The two analog input ports can be connected as follows: * Two selectable composite video inputs or * One S-video input An internal clamping circuit restores the ac-coupled video signal to a fixed dc level. The programmable gain amplifier (PGA) and the AGC circuit work together to make sure that the input signal is amplified or attenuated correctly, ensuring the proper input range for the ADC.
Functional Discription
7
TVP5154 4 Channel Low Power PAL/NTSC/SECAM Video Decoder With Independent Scalers, Fast Lock
SLES163 - MARCH 2006
www.ti.com
When switching CVBS inputs from one input to the other the AGC settings are internally stored and the previous settings for the new input are restored. This eliminates flashes and dark frames associated with switching between inputs that have different signal amplitudes. The ADC has 9 bits of resolution and runs at a maximum speed of 27 MHz. The clock input for the ADC comes from the PLL.
4.2
Composite Processing Block Diagram
The composite processing block processes NTSC/PAL/SECAM signals into the YCbCr color space. Figure 2-1 explains the basic architecture of this processing block. Figure 2-1 illustrates the luminance/chrominance (Y/C) separation process in the TVP5154 decoders. The composite video is multiplied by sub-carrier signals in the quadrature modulator to generate the color difference signals Cb and Cr. Cb and Cr are then low-pass (LP) filtered to achieve the desired bandwidth and to reduce crosstalk. An adaptive 4-line comb filter separates CbCr from Y. Chroma is re-modulated through another quadrature modulator and subtracted from the line-delayed composite video to generate luma. Contrast, brightness, hue, saturation, and sharpness (using the peaking filter) are programmable via I2C. The Y/C separation is bypassed for S-video input. For S-video, the remodulation path is disabled.
4.3
Adaptive Comb Filtering
The 4-line comb filter can be selectively bypassed in the luma or chroma path. If the comb filter is bypassed in the luma path, then chroma notch filters are used. TI's patented adaptive 4-line comb filter algorithm reduces artifacts such as hanging dots at color boundaries and detects and properly handles false colors in high frequency luminance images such as a multiburst pattern or circle pattern.
4.4
Color Low-Pass Filter
In some applications, it is desirable to limit the Cb/Cr bandwidth to avoid crosstalk. This is especially true in case of video signals that have asymmetrical Cb/Cr sidebands. The color LP filters provided limit the bandwidth of the Cb/Cr signals. Color LP filters are needed when the comb filtering turns off, due to extreme color transitions in the input image. Refer to Chrominance Control #2 Register, for the response of these filters. The filters have three options that allow three different frequency responses based on the color frequency characteristics of the input video.
4.5
Luminance Processing
The luma component is derived from the composite signal by subtracting the remodulated chroma information. A line delay exists in this path to compensate for the line delay in the adaptive comb filter in the color processing chain. The luma information is then fed into the peaking circuit, which enhances the high frequency components of the signal, thus improving sharpness.
4.6
Chrominance Processing
For NTSC/PAL formats, the color processing begins with a quadrature demodulator. The Cb/Cr signals then pass through the gain control stage for chroma saturation adjustment. An adaptive comb filter is applied to the demodulated signals to separate chrominance and eliminate cross-chrominance artifacts. An automatic color killer circuit is also included in this block. The color killer suppresses the chroma processing when the color burst of the video signal is weak or not present. The SECAM standard is similar to PAL except for the modulation of color which is FM instead of QAM.
8
Functional Discription
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TVP5154 4 Channel Low Power PAL/NTSC/SECAM Video Decoder With Independent Scalers, Fast Lock
SLES163 - MARCH 2006
4.7
Timing Processor
The timing processor is a combination of hardware and software running in the internal microprocessor that serves to control horizontal lock to the input sync pulse edge, AGC and offset adjustment in the analog front end and vertical sync detection.
4.8
VBI Data Processor
The TVP5154 VBI data processor (VDP) slices various data services like teletext (WST, NABTS), closed caption (CC), wide screen signaling (WSS), etc. These services are acquired by programming the VDP to enable standards in the VBI. The results are stored in a FIFO and/or registers. The teletext results are stored in a FIFO only. Table 4-1 lists a summary of the types of VBI data supported according to the video standard. It supports ITU-R BT. 601 sampling for each. Table 4-1. Data Types Supported by the VDP
LINE MODE REGISTER (D0h-FCh) BITS [3:0] 0000b 0001b 0010b 0011b 0100b 0101b 0110b 0111b 1000b 1001b 1010b 1011b 1100b 1111b NAME WST SECAM WST PAL B WST PAL C WST, NTSC B NABTS, NTSC C NABTS, NTSC D CC, PAL CC, NTSC WSS, PAL WSS, NTSC VITC, PAL VITC, NTSC VPS, PAL Active Video DESCRIPTION Teletext, SECAM Teletext, PAL, System B Teletext, PAL, System C Teletext, NTSC, System B Teletext, NTSC, System C Teletext, NTSC, System D (Japan) Closed caption PAL Closed caption NTSC Wide-screen signal, PAL Wide-screen signal, NTSC Vertical interval timecode, PAL Vertical interval timecode, NTSC Video program system, PAL Active video/full field
At powerup the host interface is required to program the VDP-configuration RAM (VDP-CRAM) contents with the lookup table (see Section 9.2.63). This is done through port address C3h. Each read from or write to this address will auto increment an internal counter to the next RAM location. To access the VDP-CRAM, the line mode registers (D0h-FCh) must be programmed with FFh to avoid a conflict with the internal microprocessor and the VDP in both writing and reading. Full field mode must also be disabled. Available VBI lines are from line 6 to line 27 of both field 1 and field 2. Each line can be any VBI mode. Output data is available either through the VBI-FIFO (B0h) or through dedicated registers at 90h-AFh, both of which are available through the I2C port.
4.9
VBI FIFO and Ancillary Data in Video Stream
Sliced VBI data can be output as ancillary data in the video stream in the ITU-R BT.656 mode. VBI data is output during the horizontal blanking period following the line from which the data was retrieved. Table 4-2 shows the header format and sequence of the ancillary data inserted into the video stream. This format is also used to store any VBI data into the FIFO. The size of FIFO is 512 bytes. Therefore, the FIFO can store up to 11 lines of teletext data with the NTSC NABTS standard.
Functional Discription
9
TVP5154 4 Channel Low Power PAL/NTSC/SECAM Video Decoder With Independent Scalers, Fast Lock
SLES163 - MARCH 2006
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Table 4-2. Ancillary Data Format and Sequence
BYTE NO. 0 1 2 3 4 5 6 7 8 9 10 11 * * 0 0 0 D7 (MSB) 0 1 1 NEP NEP NEP D6 0 1 1 EP EP EP D5 0 1 1 0 F5 N5 D4 0 1 1 1 F4 N4 Data error D3 0 1 1 0 F3 N3 Video line # [7:0] Match #1 1. Data 2. Data 3. Data 4. Data * * m-1. Data m. Data NEP 4(N+2)-1 0 EP 0 0 0 0 CS[5:0] 0 0 0 Match #2 Video line # [9:8] D2 0 1 1 DID2 F2 N2 D1 0 1 1 DID1 F1 N1 D0 (LSB) 0 1 1 DID0 F0 N0 Data ID (DID) Secondary data ID (SDID) Number of 32 bit data (NN) Internal data ID0 (IDID0) Internal data ID1 (IDID1) Data byte Data byte Data byte Data byte * * Data byte Data byte Check sum Fill byte Nth word 1st word DESCRIPTION Ancillary data preamble
EP: NEP: DID:
Even parity for D0-D5 Negated even parity 91h: Sliced data of VBI lines of first field 53h: Sliced data of line 24 to end of first field 55h: Sliced data of VBI lines of second field 97h: Sliced data of line 24 to end of second field
SDID: This field holds the data format taken from the line mode register of the corresponding line. NN: Number of Dwords beginning with byte 8 through 4(N+2). This value is the number of Dwords where each Dword is 4 bytes
IDID0: Transaction video line number [7:0] IDID1: Bit 0/1 = Transaction video line number [9:8] Bit 2 = Match 2 flag Bit 3 = Match 1 flag Bit 4 = 1 if an error was detected in the EDC block. 0 if not. CS: Fill byte: Sum of D0-D7 of DID through last data byte. Fill bytes make a multiple of 4 bytes from byte 0 to last fill byte. For teletext modes, byte 8 is the sync pattern byte. Byte 9 is 1. Data (the first data byte).
4.10
Raw Video Data Output
The TVP5154 decoder can output raw A/D video data at 2x sampling rate for external VBI slicing. This is transmitted as an ancillary data block during the active horizontal portion of the line and during vertical blanking.
10
Functional Discription
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TVP5154 4 Channel Low Power PAL/NTSC/SECAM Video Decoder With Independent Scalers, Fast Lock
SLES163 - MARCH 2006
4.11
Output Formatter
The output formatter is responsible for generating the output digital video stream. The YCbCr digital output can be programmed as 8-bit 4:2:2 or 8-bit ITU-R BT.656 parallel interface standard. Depending on which output mode is selected the output for each channel can be un-scaled data, scaled data or both scaled and un-scaled data interleaved in various ways. Table 4-3. Summary of Line Frequencies, Data Rates, and Pixel Counts
STANDARDS HORIZONTAL LINE RATE (kHz) 15.73426 15.625 15.73426 15.625 15.625 PIXELS PER LINE 858 864 858 864 864 ACTIVE PIXELS PER LINE 720 720 720 720 720 CLK FREQUENCY (MHz) 27.00 27.00 27.00 27.00 27.00
NTSC (M, 4.43), ITU-R BT.601 PAL (B, D, G, H, I), ITU-R BT.601 PAL (M), ITU-R BT.601 PAL (N), ITU-R BT.601 SECAM, ITU-R BT.601
4.12
Synchronization Signals
External (discrete) syncs are provided via the following signals: * VSYNC (vertical sync) * FID/VLK (field indicator or vertical lock indicator) * GPCL/VBLK (general-purpose I/O or vertical blanking indicator) * PALI/HLK (PAL switch indicator or horizontal lock indicator) * HSYNC (horizontal sync) * AVID (active video indicator) VSYNC, FID, PALI, and VBLK are software-set and programmable to the CLK pixel count. This allows any possible alignment to the internal pixel count and line count. The default settings for a 525-/625-line video output are given as an example below.
Functional Discription
11
TVP5154 4 Channel Low Power PAL/NTSC/SECAM Video Decoder With Independent Scalers, Fast Lock
SLES163 - MARCH 2006
525-Line 525 Composite Video VSYNC FID GPCL/VBLK VBLK Start 262 Composite Video VSYNC FID GPCL/VBLK VBLK Start 625-Line 310 Composite Video VSYNC FID GPCL/VBLK VBLK Start 622 Composite Video VSYNC FID GPCL/VBLK VBLK Start Line numbering conforms to ITU-R BT.470. VBLK Stop 623 624 625 1 2 3 4 5 6 7 20 VBLK Stop 21 22 23 311 312 313 314 315 316 317 318 319 320 333 334 335 336 VBLK Stop 263 264 265 266 267 268 269 270 271 272 273 VBLK Stop 282 283 284 1 2 3 4 5 6 7 8 9 10 11 20 21 22
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Figure 4-1. 8-bit 4:2:2, Timing With 2x Pixel Clock (CLK) Reference
HSYN AVID AV ID STOP HSYN START AV ID STA RT
NOTE: AVID rising edge occurs 4 CLK cycles early when in ITU-R BT.656 output mode.
Figure 4-2. Horizontal Synchronization Signals
12
Functional Discription
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TVP5154 4 Channel Low Power PAL/NTSC/SECAM Video Decoder With Independent Scalers, Fast Lock
SLES163 - MARCH 2006
4.13
AVID Cropping
AVID or active video cropping provides a means to decrease the amount of video data output. This is accomplished by horizontally blanking a number of AVID pulses and by vertically blanking a number of lines per frame. The horizontal AVID cropping is controlled using registers 11h and 12h for start pixels MSB and LSB, respectively. Registers 13h and 14h provide access to stop pixels MSB and LSB, respectively. The vertical AVID cropping is controlled using the vertical blanking (VBLK) start and stop registers at addresses 18h and 19h. Figure 4-3 shows an AVID application. AVID cropping can be independently controlled for scaled (registers 25h, 26h, 29h, and 2Ah) and un-scaled (registers 11h thru 14h) data streams. AVID start and stop must be changed in multiples of 2 pixels to ensure correct UV alignment. Additionally, AVID start and stop can be configured to include the SAV and EAV embedded sync signals or to exclude them, and to either include or exclude ITU656 ancillary data.
VBLK Stop
Active Video Area
AVID Cropped Area
VBLK Start
VSYNC
AVID Start
AVID Stop
HSYNC
Figure 4-3. AVID Application
4.14
Embedded Syncs
Standards with embedded syncs insert SAV and EAV codes into the data stream at the beginning and end of horizontal blanking. These codes contain the V and F bits which also define vertical timing. F and V change on EAV. Table 4-4 gives the format of the SAV and EAV codes. H equals 1 always indicates EAV. H equals 0 always indicates SAV. The alignment of V and F to the line and field counter varies depending on the standard. Please refer to ITU-R BT.656 for more information on embedded syncs. The P bits are protection bits: P3 = V x or H P2 = F x or H P1 = F x or V P0 = F x or V x or H
Functional Discription 13
TVP5154 4 Channel Low Power PAL/NTSC/SECAM Video Decoder With Independent Scalers, Fast Lock
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Table 4-4. EAV and SAV Sequence
8-BIT DATA D7 (MSB) Preamble Preamble Preamble Status word 1 0 0 1 D6 1 0 0 F D5 1 0 0 V D4 1 0 0 H D3 1 0 0 P3 D2 1 0 0 P2 D1 1 0 0 P1 D0 1 0 0 P0
The status word may be modified in order to pass information about whether the current data corresponds to scaled or unscaled data. See register 1Fh for more information.
4.15
Clock and Data Control
Figure 4-4 shows a logical schematic of the data and clock control signals.
Blank Delay Decoder
Field mode(0) Field mode(1) Field mode(2) Field mode(3) Field mode(4) Field mode(5) Field mode(6) Field mode(7) Field mode(8) Field mode(9) Field mode(10) Field mode(11) Field mode(12) Field mode(13) Field mode(14) Field mode(15)
=01
=00
Data
Scaler
=11
=4
01
=1
00
=0
/2 = 27MHz
=2/3
Mode
SCLK
SCLK OE SCLK edge !=3
CLK 54MHz
=3 CLK OE Mode CLK edge
Figure 4-4. Clock and Data Control
14 Functional Discription
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TVP5154 4 Channel Low Power PAL/NTSC/SECAM Video Decoder With Independent Scalers, Fast Lock
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5
I2C Host Interface
The I2C standard consists of two signals, serial input/output data line (SDA) and input/output clock line (SCL), which carry information between the devices connected to the bus. The input pins I2CA0 and I2CA1 are used to select the slave address to which the device responds. Although the I2C system can be multi-mastered, the TVP5154 decoder functions as a slave device only. Both SDA and SCL must be connected to IOVDD via pull-up resistors. When the bus is free, both lines are high. The slave address select terminals (I2CA0 and I2CA1) enable the use of four TVP5154 decoders on the same I2C bus. At the trailing edge of reset the status of the I2CA0 and I2CA1 lines are sampled to determine the device address used. Table 5-1 summarizes the terminal functions of the I2C-mode host interface. Table 5-2 shows the device address selection options. Table 5-1. I2C Terminal Description
SIGNAL I2CA0 I2CA1 SCL SDA TYPE I I I/O (open drain) I/O (open drain) DESCRIPTION Slave address selection Slave address selection Input/output clock line Input/output data line
Table 5-2. I2C Host Interface Device Addresses
A6 1 1 1 1 A5 0 0 0 0 A4 1 1 1 1 A3 1 1 1 1 A2 1 1 1 1 A1(I2CA1) 0 0 1 1 A0 (I2CA0) 0 1 0 1 R/W 1/0 1/0 1/0 1/0 HEX B9/B8 BB/BA BD/BC BF/BE
Data transfer rate on the bus is up to 400 kbits/s. The number of interfaces connected to the bus is dependent on the bus capacitance limit of 400 pF. The data on the SDA line must be stable during the high period of the SCL except for start and stop conditions. The high or low state of the data line can only change with the clock signal on the SCL line being low. A high-to-low transition on the SDA line while the SCL is high indicates an I2C start condition. A low-to-high transition on the SDA line while the SCL is high indicates an I2C stop condition. Every byte placed on the SDA must be 8 bits long. The number of bytes which can be transferred is unrestricted. Each byte must be followed by an acknowledge bit. The acknowledge-related clock pulse is generated by the I2C master. To simplify programming of each of the 4 decoder channels a single I2C write transaction can be transmitted to any one or more of the 4 cores in parallel. This reduces the time required to download firmware or to configure the device when all channels are to be configured in the same manner. It also enables the addresses for all registers to be common across all decoders. I2C sub-address 0xFE contains 4 bits with each bit corresponding to one of the decoder cores. If this bit is set, then I2C write transactions will be sent to the corresponding decoder core. If the bit is 0 then the corresponding decoder will not receive the I2C write transactions. I2C sub-address 0xFF contains 4 bits with each bit corresponding to one of the decoder cores. If this bit is set, then I2C read transactions will be sent to the corresponding decoder core. Note, only one of the bits in this register should be set at a given time, ensuring that only one decoder core is accessed at a time for read operations. If more than one bit is set then the lowest set bit number will correspond to the core that will respond to the read transaction.
I2C Host Interface
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Note, when register 0xFE is written to with any value then register 0xFF will be set to 0x00. Likewise when register 0xFF is written to with any value then register 0xFE will be set to 0x00.
5.1
I2C Write Operation
Data transfers occur utilizing the following illustrated formats. An I2C master initiates a write operation to the TVP5154 decoder by generating a start condition (S) followed by the TVP5154 I2C address (as shown below), in MSB first bit order, followed by a 0 to indicate a write cycle. After receiving an acknowledge from the TVP5154 decoder, the master presents the sub-address of the register, or the first of a block of registers it wants to write, followed by one or more bytes of data, MSB first. The TVP5154 decoder acknowledges each byte after completion of each transfer. The I2C master terminates the write operation by generating a stop condition (P).
Step 1 I2C Start (master)
0 S 7 1 9 A 7 addr 9 A 7 Data 9 A 0 P 6 Data 5 Data 4 Data 3 Data 2 Data 1 Data 0 Data 6 addr 5 addr 4 addr 3 addr 2 addr 1 addr 0 addr 6 0 5 1 4 1 3 1 2 0 1 X 0 0
Step 2 I2C General address (master)
Step 3 I2C Acknowledge (slave)
Step 4 I2C Write register address (master) Step 5 I2C Acknowledge (slave) Step 6 I2C Write data (master) Step 7 (1) I2C Acknowledge (slave) Step 8 I2C Stop (master) (1)
Repeat steps 6 and 7 until all data have been written.
5.2
I2C Read Operation
The read operation consists of two phases. The first phase is the address phase. In this phase, an I2C master initiates a write operation to the TVP5154 decoder by generating a start condition (S) followed by the TVP5154 I2C address, in MSB first bit order, followed by a 0 to indicate a write cycle. After receiving acknowledges from the TVP5154 decoder, the master presents the sub-address of the register or the first of a block of registers it wants to read. After the cycle is acknowledged, the master terminates the cycle immediately by generating a stop condition (P). The second phase is the data phase. In this phase, an I2C master initiates a read operation to the TVP5154 decoder by generating a start condition followed by the TVP5154 I2C address (as shown below for a read operation), in MSB first bit order, followed by a 1 to indicate a read cycle. After an acknowledge from the TVP5154 decoder, the I2C master receives one or more bytes of data from the TVP5154 decoder. The I2C master acknowledges the transfer at the end of each byte. After the last data byte desired has been transferred from the TVP5154 decoder to the master, the master generates a not acknowledge followed by a stop.
16
I2C Host Interface
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Read Phase 1
Step 1 I2C Start (master) Step 2 I2C General address (master) Step 3 I2C Acknowledge (slave) Step 4 I2C Read register address (master) Step 5 I2C Acknowledge (slave) Step 6 I2C Stop (master) 0 S 7 1 9 A 7 addr 9 A 0 P 6 addr 5 addr 4 addr 3 addr 2 addr 1 addr 0 addr 6 0 5 1 4 1 3 1 2 0 1 X 0 0
Read Phase 2
Step 7 I2C Start (master) Step 8 I2C General address (master) 0 S 7 1 9 A 7 Data 9 A 0 P 6 Data 5 Data 4 Data 3 Data 2 Data 1 Data 0 Data 6 0 5 1 4 1 3 1 2 0 1 X 0 1
Step 9 I2C Acknowledge (slave)
Step 10 I2C Read data (slave)
Step 11 (1) I2C Not acknowledge (master) Step 12 I2C Stop (master) (1)
Repeat steps 10 and 11 for all bytes read. Master does not acknowledge the last read data received.
5.2.1
I2C Timing Requirements
The TVP5154 decoder requires delays in the I2C accesses to accommodate its internal processor's timing. In accordance with I2C specifications, the TVP5154 decoder holds the I2C clock line (SCL) low to indicate the wait period to the I2C master. If the I2C master is not designed to check for the I2C clock line held-low condition, then the maximum delays must always be inserted where required. These delays are of variable length; maximum delays are indicated in the following diagram: Table 5-3. I2C Timing
Start
Slave address (B8h)
Ack
Subaddress
Ack
Data (XXh)
Ack
Wait 128 s*
Stop
* If the SCL pin is not monitored by the master to enable pausing, then a delay of 128 S should be inserted between transactions for registers 00h through 8Fh.
I2C Host Interface
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6
Clock Circuits
An internal line-locked PLL generates the system and pixel clocks. A 14.31818-MHz clock is required to drive the PLL. This may be input to the TVP5154 decoder on terminal 124 (XIN), or a crystal of 14.31818-MHz fundamental resonant frequency may be connected across terminals 123 and 124 (XIN and XOUT). Figure 6-1 shows the reference clock configurations. For the example crystal circuit shown (a parallel-resonant crystal with 14.31818-MHz fundamental frequency), the external capacitors must have the following relationship: CL1 = CL2 = 2CL- CSTRAY, where CSTRAY is the terminal capacitance with respect to ground. Figure 6-1 shows the reference clock configurations.
124
14.31818 MHz 1.8V clock
14.31818 MHz CL1 crystal 124 R
123
123 CL2
Figure 6-1. Clock and Crystal Connectivity
7
Genlock Control and RTC
A Genlock control (GLCO) function is provided to support a standard video encoder to synchronize its internal color oscillator for properly reproduced color with unstable timebase sources like VCRs. The frequency control word of the internal color subcarrier digital control oscillator (DTO) and the subcarrier phase reset bit are transmitted via the GLCO terminal. The frequency control word is a 23-bit binary number. The frequency of the DTO can be calculated from the following equation: F F dto + ctrl F clk 223 where Fdto is the frequency of the DTO, Fctrl is the 23-bit DTO frequency control, and Fclk is the frequency of the CLK.
7.1
TVP5154 Genlock Control Interface
A write of 1 to bit 4 of the chrominance control register at I2C subaddress 1Ah causes the subcarrier DTO phase reset bit to be sent on the next scan line on GLCO. The active low reset bit occurs 7 CLKs after the transmission of the last bit of DCO frequency control. Upon the transmission of the reset bit, the phase of the TVP5154 internal subcarrier DCO is reset to zero. A Genlock slave device can be connected to the GLCO terminal and uses the information on GLCO to synchronize its internal color phase DCO to achieve clean line and color lock.
7.2
RTC Mode
Figure 7-1 shows the timing diagram of the RTC mode. Clock rate for the RTC mode is 4 times slower than the GLCO clock rate. For PLL frequency control, the upper 22 bits are used. Each frequency control bit is 2 clock cycles long. The active low reset bit occurs 6 CLKs after the transmission of the last bit of PLL frequency control.
18
Clock Circuits
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CLK
GLCO 22 >128 CLK
MSB
LSB
21 23 CLK 23-Bit Frequency Control
0 7 CLK 1 CLK DCO Reset Bit
1 CLK Start Bit
GLCO Timing
RTC
M S B
21
L S B 0
128 CLK
16 CLK
44 CLK 22-Bit Fsc Frequency Control
1 CLK
PAL
2 CLK Switch
2 CLK
Start Bit
3 CLK
1 CLK
Reset Bit
Figure 7-1. RTC Timing
8
Power Up, Reset, and Power Down Sequence (Required)
Terminals 121 (RESETB) and 122 (PDN) work together to put the TVP5154 decoder into one of the three modes. Table 8-1 shows the configuration. After power-up the device will be in an unknown state, with its outputs undefined, until it receives a resetb active low for at least 200 ns. The power supplies should be active and stable for 10 ms before resetb becomes inactive. There are no power sequencing requirements except that all power supplies should become active and stable within 500ms of each other. After each power-up and hardware reset, the following procedure must be followed: 1. Wait at least 1ms. Each decoder must be started by writing 0x00h to register 7Fh for all four decoders. 2. Wait at least 1ms. Check the status of the TVP5154 by doing an I2C read of the version number, register 81h, for all four decoders. 3. Verify that the value 0x54h is read. 4. If the value 0x54h is not read, toggle the TVP5154 reset pin (RESETB, pin number 121). This Procedure should be repeated if necessary until the value 0x54h is read from register 81h for all four decoders.
Power Up, Reset, and Power Down Sequence (Required)
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Table 8-1. Reset and Power Down Modes
PDN 0 0 1 1 RESETB 0 1 0 1 CONFIGURATION Reserved (undefined state) Powers down the decoder Resets the decoder Normal operation
9
9.1
Internal Control Registers
Overview
The TVP5154 decoder is initialized and controlled by sets of internal registers which set all device operating parameters. Communication between the external controller and the TVP5154 decoder is through I2C. Two sets of registers exist, direct and indirect. Table 9-1 shows the summary of the direct registers. Reserved registers must not be written. Reserved bits in the defined registers must be written with 0s, unless otherwise noted. The detailed programming information of each register is described in the following sections. I2C register 0xFE controls which of the four decoders will receive I2C commands. I2C register 0xFF controls which decoder core responds to I2C reads. Note, for a read operation it is necessary to perform a write first in order to set the desired sub-address for reading. After power up and the hardware reset, each decoder must be started by writing 0x00h to register 7Fh for all four decoders. Table 9-1. Direct Register Summary
REGISTER FUNCTION Video input source selection #1 Analog channel controls Operation mode controls Miscellaneous controls Autoswitch mask Clock control Color killer threshold control Luminance processing control #1 Luminance processing control #2 Brightness control Color saturation control Hue control Contrast control Outputs and data rates select Luminance processing control #3 Configuration shared pins Reserved Active video cropping start MSB for unscaled data Active video cropping start LSB for unscaled data Active video cropping stop MSB for unscaled data Active video cropping stop LSB for unscaled data Genlock/RTC Horizontal sync start (1) R = Read only; W = Write only; R/W = Read and write ADDRESS 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 00h 00h 00h 00h 01h 80h R/W R/W R/W R/W R/W R/W DEFAULT 00h 15h 00h 01h DCh 08h 10h 60h 00h 80h 80h 00h 80h 47h 00h 08h R/W (1) R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
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Internal Control Registers
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Table 9-1. Direct Register Summary (continued)
REGISTER FUNCTION Ancillary SAV/EAV control Vertical blanking start Vertical blanking stop Chrominance processing control #1 Chrominance processing control #2 Interrupt reset register B Interrupt enable register B Interrupt configuration register B Output control Reserved I2C indirect registers AVID start/control for scaled data Reserved Video standard AVID stop for scaled data Reserved Cb gain factor Cr gain factor Reserved 656 Revision Select Reserved MSB of device ID LSB of device ID ROM major version ROM minor version Vertical line count MSB Vertical line count LSB Interrupt status register B Interrupt active register B Status register #1 Status register #2 Status register #3 Status register #4 Status register #5 Reserved Closed caption data registers WSS data registers VPS data registers VITC data registers VBI FIFO read data Teletext filter 1 Teletext filter 2 Teletext filter enable Reserved Interrupt status register A Interrupt enable register A Interrupt configuration ADDRESS 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h-24h 25h-26h 27h 28h 29h-2Ah 2Bh 2Ch 2Dh 2Eh-2Fh 30 31h-7Fh 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh-8Fh 90h-93h 94h-99h 9Ah-A6h A7h-AFh B0h B1h-B5h B6h-BAh BBh BCh-BFh C0h C1h C2h 00h 00h 04h R/W R/W R/W Internal Control Registers 21 00h 00h 00h R R R R R R/W R/W R/W 51h 54h 02h 00h R R R R R R R R R R R R R 00h R/W R R 00h 00h R/W R/W 00h 00h R/W R/W DEFAULT 52h 00h 00h 0Ch 14h 00h 00h 00h 00h R/W (1) R/W R/W R/W R/W R/W R/W R/W R/W R/W
TVP5154 4 Channel Low Power PAL/NTSC/SECAM Video Decoder With Independent Scalers, Fast Lock
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Table 9-1. Direct Register Summary (continued)
REGISTER FUNCTION VDP configuration RAM data Configuration RAM address low byte Configuration RAM address high byte VDP status register FIFO word count FIFO interrupt threshold FIFO reset Line number interrupt Pixel alignment register low byte Pixel alignment register high byte FIFO output control Reserved Full field enable Line mode registers Full field mode register Reserved Decoder core write enables Decoder core read enables ADDRESS C3h C4h C5h C6h C7h C8h C9h CAh CBh CCh CDh CEh CFh D0h D1h-FBh FCh FDh FEh FFh 0Fh 00h R/W R/W 00h 00h FFh 7Fh R/W R/W R/W 80h 00h 00h 4Eh 00h 01h DEFAULT B8h 1Fh 00h R/W (1) R/W R/W R/W R R R/W W R/W R/W R/W R/W
9.2
Direct Register Definitions
Direct registers are written to by performing a 3 byte I2C transaction as shown below. START : DEVICE_ID : SUB_ADDRESS : DATA : STOP Each direct register is 8 bits wide.
9.2.1
Address Default 7
Video Input Source Selection #1 Register
00h 00h 6 5 4 3 Black output 2 Reserved 1 Channel n source selection 0 S-video selection
Reserved Channel n source selection: 0 = AIPnA selected (default) 1 = AIPnB selected
22
Internal Control Registers
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Table 9-2. Analog Channel and Video Mode Selection
INPUT(S) SELECTED Composite S-Video AIPnA (default) AIPnB AIPnA (luma), AIPnB (chroma) ADDRESS 00 BIT 1 0 1 x BIT 0 0 0 1
Where n = 1, 2, 3, 4 Black output: 0 = Normal operation (default) 1 = Force black screen output (outputs synchronized) a. Forced to 10h in normal mode b. Forced to 01h in extended mode
9.2.2
Address Default 7
Analog Channel Controls Register
01h 15h 6 Reserved 5 4 1 3 2 1 0
Automatic offset control
Automatic gain control
Automatic offset control: 00 = Disabled 01 = Automatic offset enabled (default) 10 = Reserved 11 = Offset level frozen to the previously set value Automatic gain control (AGC): 00 = Disabled (fixed gain value) 01 = AGC enabled (default) 10 = Reserved 11 = AGC frozen to the previously set value
Internal Control Registers
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9.2.3
Address Default
Operation Mode Controls Register
02h 00h 7 6 Color burst reference enable 5 4 3 White peak disable 2 Color subcarrier PLL frozen 1 Luma peak disable 0 Power down mode
Fast Lock Mode
TV/VCR mode
Fast lock mode: 0 = Normal operation (default) 1 = Fast lock mode. Locks within 3 fields if stable input signal and forced video standard. Color burst reference enable: 0 = Color burst reference for AGC disabled (default) 1 = Color burst reference for AGC enabled TV/VCR mode: 00 = Automatic mode determined by the internal detection circuit. (default) 01 = Reserved 10 = VCR (nonstandard video) mode 11 = TV (standard video) mode With automatic detection enabled, unstable or nonstandard syncs on the input video forces the detector into the VCR mode. This turns off the comb filters and turns on the chroma trap filter. White peak disable: 0 = White peak protection enabled (default) 1 = White peak protection disabled Color subcarrier PLL frozen: 0 = Color subcarrier PLL increments by the internally generated phase increment. (default) GLCO pin outputs the frequency increment 1 = Color subcarrier PLL stops operating. GLCO pin outputs the frozen frequency increment. Luma peak disable 0 = Luma peak processing enabled (default) 1 = Luma peak processing disabled Power down mode: 0 = Normal operation (default) 1 = Power down mode. A/Ds are turned off and internal clocks are reduced to minimum.
24
Internal Control Registers
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9.2.4
Address Default 7 VBKO
Miscellaneous Control Register
03h 01h 6 GPCL pin 5 GPCL output enable 4 Lock status (HVLK) 3 YCbCr output enable(TVPOE) 2 HSYNC, VSYNC/PALI, AVID, FID/GLCO output enable 1 Vertical blanking on/off 0 CLK output enable
VBKO (pins 41, 60, 83, 102) function select: 0 = GPCL (default) 1 = VBLK Note, if these pins are not configured as outputs then they must not be left floating. A 10-k pull-down resistor is recommended if not driven externally. GPCL (data is output based on state of bit 5): 0 = GPCL outputs 0 (default) 1 = GPCL outputs 1 GPCL output enable:(1) 0 = GPCL is inactive (default) 1 = GPCL is output Note, if these pins are not configured as outputs then they must not be left floating. A 10-k pull-down resistor is recommended if not driven externally. (1)GPCL should not be programmed to be 0, when register 0Fh bit 1 is`1, (programmed to be GPCL/VBLK). Lock status (HVLK) (configured along with register 0Fh, see Figure 9-1 for the relationship between the configuration shared pins): 0 = Terminal VSYNC/PALI outputs the PAL indicator (PALI) signal and terminal FID/GLCO outputs the field ID (FID) signal (default) (if terminals are configured to output PALI and FID in register 0Fh) 1 = Terminal VSYNC/PALI outputs the horizontal lock indicator (HLK) and terminal FID outputs the vertical lock indicator (VLK) (if terminals are configured to output PALI and FID in register 0Fh) These are additional functionalities that are provided for ease of use. YCbCr output enable: 0 = YOUT[7:0] high impedance (default) 1 = YOUT[7:0] active Note, if these pins are not configured as outputs then they must not be left floating. A 10-k pull-down resistor is recommended if not driven externally. HSYNC, VSYNC/PALI, active video indicator (AVID), and FID/GLCO output enables: 0 = HSYNC, VSYNC/PALI, AVID, and FID/GLCO are high-impedance (default). 1 = HSYNC, VSYNC/PALI, AVID, and FID/GLCO are active. Note, if these pins are not configured as outputs then they must not be left floating. A 10-k pull-down resistor is recommended if not driven externally. Vertical blanking on/off: 0 = Vertical blanking (VBLK) off (default) 1 = Vertical blanking (VBLK) on CLK output enable: 0 = CLK output is high impedance 1 = CLK output is enabled (default) Note: CLK edge and SCLK are configured through register 05h.
Table 9-3. Digital Output Control
Register 03h, Bit 3 (TVPOE) (1) 0 X 1 (1) Register C2h, Bit 2 (VDPOE) (1) X 0 1 YCbCr Output High impedance High impedance Active
VDPOE default is 1 and TVPOE default is 0
Internal Control Registers
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0F(Bit 2) VSYNC/PALI 0F(Bit 4) LOCK24B 0 1 M U X VSYNC/PALI/HLK/HVLK
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VSYNC PALI HLK HVLK 0 1 M U X HLK/HVLK 1 0 M U X PALI/HLK/HVLK
Pins 38, 57, 76, 95
HVLK VLK
1 0 M U X VLK/HVLK FID 1 0 M U X FID/VLK/HVLK GLCO 0 1 M U X FID/GLCO/VLK/HVLK Pins 37, 56, 75, 94
0F(BIT 6) LOCK23 03(Bit 4) HVLK 0F(BIT 3) FID/GLCO
VBLK GPCL
1 0 M U X VBLK/GPCL INTREQ 1 0 M U X INTREQ/GPCL//VBLK Pins 41, 60, 83, 102
CLK 03(BIT 7) VBKO PCLK 0F(BIT 1) INTREQ/GPCL/VBLK
0 1 M U X PCLK/CLK Pins 42, 61, 84, 103
0F(BIT 0) CLK/PCLK
NOTE: Also refer to the configuration shared pins register at subaddress 0Fh.
Figure 9-1. Configuration Shared Pins
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Internal Control Registers
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TVP5154 4 Channel Low Power PAL/NTSC/SECAM Video Decoder With Independent Scalers, Fast Lock
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9.2.5
Address Default 7
Autoswitch Mask Register
04h DCh 6 Reserved 5 SEC_OFF 4 N443_OFF 3 PALN_OFF 2 PALM_OFF 1 Reserved 0
N443_OFF: 0= 1= PALN_OFF: 0= 1= PALM_OFF: 0= 1= SEC_OFF: 0= 1=
NTSC443 is unmasked from the autoswitch process. Autoswitch does switch to NTSC443. NTSC443 is masked from the autoswitch process. Autoswitch does not switch to NTSC443. (default) PAL-N is unmasked from the autoswitch process. Autoswitch does switch to PAL-N. PAL-N is masked from the autoswitch process. Autoswitch does not switch to PAL-N. (default) PAL-M is unmasked from the autoswitch process. Autoswitch does switch to PAL-M. PAL-M is masked from the autoswitch process. Autoswitch does not switch to PAL-M. (default) SECAM is unmasked from the autoswitch process. Autoswitch does switch to SECAM. (default) SECAM is masked from the autoswitch process. Autoswitch does not switch to SECAM.
9.2.6
Address Default 7
Clock Control Register
05h 08h 6 Reserved 5 4 3 SCLK OE 2 Reserved 1 SCLK edge 0 CLK edge
CLK edge 0 = CLK data changes on falling edge of CLK 1 = CLK data changes on rising edge of CLK SCLK edge 0 = SCLK data changes on falling edge of SCLK 1 = SCLK data changes on rising edge of SCLK SCLK OE 0 = SCLK output disabled. Output is high impedance 1 = SCLK output enabled. NOTE: CLK OE is configured through register 0x03 to maintain compatibility with the TVP5150 family of devices.
9.2.7
Address Default 7
Color Killer Threshold Control Register
06h 10h 6 5 4 3 2 Color killer threshold 1 0
Reserved
Automatic color killer
Automatic color killer: 00 = Automatic mode (default) 01 = Reserved 10 = Color killer enabled, the CbCr terminals are forced to a zero color state. 11 = Color killer disabled Color killer threshold: 11111 = -30 dB (minimum) 10000 = - 24 dB (default) 00000 = - 18 dB (maximum)
Internal Control Registers
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TVP5154 4 Channel Low Power PAL/NTSC/SECAM Video Decoder With Independent Scalers, Fast Lock
SLES163 - MARCH 2006
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9.2.8
Address Default 7
Luminance Processing Control #1 Register
07h 60h 6 Pedestal not present 5 Disable raw header 4 Luma bypass enabled during vertical blanking 3 2 1 0
2x luma output enable
Luminance signal delay with respect to chrominance signal
2x luma output enable: 0 = Output depends on bit 4, luminance bypass enabled during vertical blanking (default). 1 = Outputs 2x luma samples during the entire frame. This bit takes precedence over bit 4. Pedestal not present: 0 = 7.5 IRE pedestal is present on the analog video input signal. 1 = Pedestal is not present on the analog video input signal (default). Disable raw header: 0 = Insert 656 ancillary headers for raw data 1 = Disable 656 ancillary headers and instead force dummy ones (0x40) (default) Luminance bypass enabled during vertical blanking: 0 = Disabled. If bit 7, 2x luma output enable, is 0, then normal luminance processing occurs and YCbCr samples are output during the entire frame (default). 1 = Enabled. If bit 7, 2x luma output enable, is 0, then normal luminance processing occurs and YCbCr samples are output during VACTIVE and 2x luma samples are output during VBLK. Luminance bypass occurs for the duration of the vertical blanking as defined by registers 18h and 19h. Luma signal delay with respect to chroma signal in pixel clock increments (range -8 to +7 pixel clocks): 1111 = - 8 pixel clocks delay 1011 = - 4 pixel clocks delay 1000 = - 1 pixel clocks delay 0000 = 0 pixel clocks delay (default) 0011 = 3 pixel clocks delay 0111 = 7 pixel clocks delay
9.2.9
Address Default 7
Luminance Processing Control #2 Register
08h 00h 6 Luminance filter select 5 Reserved 4 3 2 1 Reserved 0
Reserved
Peaking gain
Luminance filter select: 0 = Luminance comb filter enabled (default) 1 = Luminance chroma trap filter enabled Peaking gain (sharpness): 00 = 0 (default) 01 = 0.5 10 = 1 11 = 2 Information on peaking frequency: ITU-R BT.601 sampling rate: all standards -- peaking center frequency is 2.6 MHz
9.2.10
Address Default 7
Brightness Control Register
09h 80h 6 5 4 3 2 1 0
Brightness control Brightness control: 1111 1111 = 255 (bright) 1000 0000 = 128 (default) 0000 0000 = 0 (dark)
28
Internal Control Registers
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TVP5154 4 Channel Low Power PAL/NTSC/SECAM Video Decoder With Independent Scalers, Fast Lock
SLES163 - MARCH 2006
9.2.11
Address Default 7
Color Saturation Control Register
0Ah 80h 6 5 4 3 2 1 0
Saturation control Saturation control: 1111 1111 = 255 (maximum) 1000 0000 = 128 (default) 0000 0000 = 0 (no color)
9.2.12
Address Default 7
Hue Control Register (does not apply to SECAM)
0Bh 00h 6 5 4 Hue control 3 2 1 0
Hue control: 0111 1111 = +180 degrees 0000 0000 = 0 degrees (default) 1000 0000 = - 180 degrees
9.2.13
Address Default 7
Contrast Control Register
0Ch 80h 6 5 4 Contrast control 3 2 1 0
Contrast control: 1111 1111 = 255 (maximum contrast) 1000 0000 = 128 (default) 0000 0000 = 0 (minimum contrast)
Internal Control Registers
29
TVP5154 4 Channel Low Power PAL/NTSC/SECAM Video Decoder With Independent Scalers, Fast Lock
SLES163 - MARCH 2006
www.ti.com
9.2.14
Address Default 7
Outputs and Data Rates Select Register
0Dh 47h 6 YCbCr output code range 5 CbCr code format 4 3 2 1 0
Reserved
YCbCr data path bypass
YCbCr output format
YCbCr output code range: 0 = ITU-R BT.601 coding range (Y ranges from 16 to 235. U and V range from 16 to 240) 1 = Extended coding range (Y, U, and V range from 1 to 254) (default) CbCr code format: 0 = Offset binary code (2's complement + 128) (default) 1 = Straight binary code (2's complement) YCbCr data path bypass: 00 = Normal operation (default) 01 = Decimation filter output connects directly to the YCbCr output pins. This data is similar to the digitized composite data, but the HBLANK area is replaced with ITU-R BT.656 digital blanking. 10 = Digitized composite (or digitized S-video luma). A/D output connects directly to the YCbCr output pins. 11 = Reserved YCbCr output format: 000 = 8-bit 4:2:2 YCbCr with discrete sync output 001 = Reserved 010 = Reserved 011 = Reserved 100 = Reserved 101 = Reserved 110 = Reserved 111 = 8-bit ITU-R BT.656 interface with embedded sync output (default)
9.2.15
Address Default 7
Luminance Processing Control #3 Register
0Eh 00h 6 5 Reserved 4 3 2 1 0
Luminance trap filter select
Luminance filter stop band bandwidth (MHz): 00 = No notch (default) 01 = Notch 1 10 = Notch 2 11 = Notch
Luminance filter select [1:0] selects one of the four chroma trap (notch) filters to produce luminance signal by removing the chrominance signal from the composite video signal. The stopband of the chroma trap filter is centered at the chroma subcarrier frequency with stopband bandwidth controlled by the two control bits. Refer to Table 9-4 for the stopband bandwidths. The WCF bit is controlled in the chrominance control #2 register.
30
Internal Control Registers
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TVP5154 4 Channel Low Power PAL/NTSC/SECAM Video Decoder With Independent Scalers, Fast Lock
SLES163 - MARCH 2006
Table 9-4. Luma Filter Selection
WCF 0 FILTER SELECT 00 01 10 11 1 00 01 10 11 NTSC/PAL/SECAM ITU-R BT.601 1.2214 0.8782 0.7297 0.4986 1.4170 1.0303 0.8438 0.5537
9.2.16
Address Default 7 Reserved
Configuration Shared Pins Register
0Fh 08h 6 FID PIN 5 Reserved 4 PALI PIN 3 FID/GLCO 2 VSYNC/PALI 1 INTREQ/GPCL/VBLK 0 CLK/PCLK
FID PIN function select: 0 = FID (default, if bit 3 is selected to output FID) 1 = Lock indicator (indicates whether the device is locked vertically) PALI PIN function select: 0 = PALI (default, if bit 2 is selected to output PALI) 1 = Lock indicator (indicates whether the device is locked horizontally) FID/GLCO function select (also refer to register 03h for enhanced functionality): 0 = FID 1 = GLCO (default) VSYNC/PALI function select (also refer to register 03h for enhanced functionality): 0 = VSYNC (default) 1 = PALI INTREQ/GPCL/VBLK function select: 0 = INTREQ (default) 1 = GPCL or VBLK depending on bit 7 of register 03h CLK/PCLK (pins 42, 61, 84, 103) function select: 0 = CLK at 27 MHz (default) 1 = PCLK (1x pixel clock frequency at 13.5 MHz)
See Figure 9-1 for the relationship between the configuration shared pins.
9.2.17
Address Default 7
Active Video Cropping Start Pixel MSB for Unscaled Data Register
11h 00h 6 5 4 3 2 1 0
AVID start pixel MSB [9:2]
Active video cropping start pixel MSB [9:2], set this register first before setting register 12h. The TVP5154 decoder updates the AVID start values only when register 12h is written to. This start pixel value is relative to the default values of the AVID start pixel.
Internal Control Registers
31
TVP5154 4 Channel Low Power PAL/NTSC/SECAM Video Decoder With Independent Scalers, Fast Lock
SLES163 - MARCH 2006
www.ti.com
9.2.18
Address Default 7
Active Video Cropping Start Pixel LSB for Unscaled Data Register
12h 00h 6 5 Reserved 4 3 2 AVID active 1 0
AVID start pixel LSB [1:0]
AVID active: 0 = AVID out active in VBLK (default) 1 = AVID out inactive in VBLK AVID start [9:0] (combined registers 11h and 12h): 01 1111 1111 = 511 00 0000 0001 = 1 00 0000 0000 = 0 (default) 11 1111 1111 = - 1 10 0000 0000 = - 512 Active video cropping start pixel LSB [1:0]: The TVP5154 decoder updates the AVID start values only when this register is written to.
9.2.19
Address Default 7
Active Video Cropping Stop Pixel MSB LSB for Unscaled Data Register
13h 00h 6 5 4 3 2 1 0
AVID stop pixel MSB [9:2]
Active video cropping stop pixel MSB [9:2], set this register first before setting the register 14h. The TVP5154 decoder updates the AVID stop values only when register 14h is written to. This stop pixel value is relative to the default values of the AVID stop pixel.
9.2.20
Address Default 7
Active Video Cropping Stop Pixel LSB for Unscaled Data Register
14h 00h 6 5 Reserved 4 3 2 1 0
AVID stop pixel LSB [1:0]
Active video cropping stop pixel LSB [1:0]: The number of pixels of active video must be an even number. The TVP5154 decoder updates the AVID stop values only when this register is written to.
AVID stop [9:0] (combined registers 13h and 14h): 01 1111 1111 = 511 00 0000 0001 = 1 00 0000 0000 = 0 (default) (see Figure 4-2) and Figure 4-3) 11 1111 1111 = - 1 10 0000 0000 = - 512
32
Internal Control Registers
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TVP5154 4 Channel Low Power PAL/NTSC/SECAM Video Decoder With Independent Scalers, Fast Lock
SLES163 - MARCH 2006
9.2.21
Address Default 7
Genlock and RTC Register
15h 01h 6 Reserved 5 F/V bit control 4 3 Auto inc 2 1 GLCO/RTC 0
Stable syncs
Stable syncs 0 = Output F and V bits follow the input signal producing fixed vertical blanking periods by adapting the active video. 1 = Output F and V bits produce fixed active video periods by adapting the vertical blanking. F/V bit control
Table 9-5. F/V Bit Control
BIT 5 0 BIT 4 0 NUMBER OF LINES Standard Nonstandard even Nonstandard odd 0 1 1 1 0 1 Standard Nonstandard Standard Nonstandard Illegal F BIT ITU-R BT.656 Force to 1 Toggles ITU-R BT.656 Toggles ITU-R BT.656 Pulse mode V BIT ITU-R BT.656 Switch at field boundary Switch at field boundary ITU-R BT.656 Switch at field boundary ITU-R BT.656 Switch at field boundary
Auto inc. When this bit is set to 1 subsequent reading/writing from/to back door registers will automatically increment the address index. GLCO/RTC. Table 9-6 helps in understanding the different modes. Table 9-6. GLCO/RTC Control
BIT 2 0 0 1 1 BIT 1 x x x x BIT 0 0 1 0 1 GLCO RTC output mode 0 (default) GLCO RTC output mode 1 GENLOCK/RTC MODE
All other values are reserved. Figure 7-1shows the timing of GLCO and the timing of RTC.
Internal Control Registers
33
TVP5154 4 Channel Low Power PAL/NTSC/SECAM Video Decoder With Independent Scalers, Fast Lock
SLES163 - MARCH 2006
www.ti.com
9.2.22
Address Default 7
Horizontal Sync (HSYNC) Start Register
16h 80h 6 5 4 HSYNC start 3 2 1 0
HSYNC start 1111 1111 = 1111 1110 = 1000 0001 = 1000 0000 = 0111 1111 = 0111 1110 = 0000 0000 =
- 127 x 4 pixel clocks - 126 x 4 pixel clocks - 1 x 4 pixel clocks 0 pixel clocks (default) 1 x 4 pixel clocks 2 x 4 pixel clocks 128 x 4 pixel clocks
BT.656 EAV Code BT.656 SAV Code
YOUT[7:0]
U
Y
V
Y
F F
0 0
0 0
X Y
8 0
1 0
8 0
1 0
F F
0 0
0 0
X Y
U
Y
HSYNC
AVID
128 SCLK Nhbhs Nhb Start of Digital Active Line
Figure 9-2. Horizontal Sync Table 9-7. Clock Delays (CLKs)
STANDARD NTSC PAL SECAM Nhbhs 16 20 40 Nhb 272 284 280
Detailed timing information is also available in Section 4.12, Synchronization Signals.
34
Internal Control Registers
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TVP5154 4 Channel Low Power PAL/NTSC/SECAM Video Decoder With Independent Scalers, Fast Lock
SLES163 - MARCH 2006
9.2.23
Address Default 7 Reserved
Ancillary SAV/EAV Control
17h 52h 6 Scaler PD 5 Include scale ancillary 4 Include scale SAV 3 Include scale EAV 2 Include unscale ancillary 1 Include unscale SAV 0 Include unscale EAV
Include unscaled EAV: 0 = AVID period does not include the EAV sync codes (default) 1 = AVID period includes the EAV sync codes Include unscaled SAV: 0 = AVID period does not include the SAV sync codes 1 = AVID period includes the SAV sync codes (default) Include unscaled ancillary data: 0 = AVID period includes the ancillary data region (default) 1 = AVID period does not include the ancillary data region Include scaled EAV: 0 = AVID period does not include the EAV sync codes (default) 1 = AVID period includes the EAV sync codes Include scaled SAV: 0 = AVID period does not include the SAV sync codes 1 = AVID period includes the SAV sync codes (default) Include scaled ancillary data: 0 = AVID period includes the ancillary data region (default) 1 = AVID period does not include the ancillary data region Scaler PD. Scaler power down 0 = Scaler active 1 = Scaler powered down (default)
Data
SAV
Pixel Data
Un-scaled pixel data
EAV
ANC
AVID
Include SAV = 0, Include EAV = 0, Include ancillary = 1
AVID
Include SAV = 1, Include EAV = 0, Include ancillary = 0
AVID
Include SAV = 0, Include EAV = 1, Include ancillary = 1
Data
SAV
Pixel Data
EAV
ANC
Scaled pixel data, AVID start/stop reduced
AVID
Include SAV = 0, Include EAV = 0, Include ancillary = 1
AVID
Include SAV = 1, Include EAV = 0, Include ancillary = 0
AVID
Include SAV = 0, Include EAV = 1, Include ancillary = 1
Figure 9-3. AVID Behavior When Ancillary Data Present
Internal Control Registers 35
TVP5154 4 Channel Low Power PAL/NTSC/SECAM Video Decoder With Independent Scalers, Fast Lock
SLES163 - MARCH 2006
www.ti.com
Data
SAV
Pixel Data
Un-scaled pixel data
EAV
AVID
Include SAV = 0, Include EAV = 0
AVID
Include SAV = 1, Include EAV = 0
AVID
Include SAV = 0, Include EAV = 1
Data
SAV
Pixel Data
0 Data
EAV
Scaled pixel data, AVID start/stop same as for un-scaled data
AVID
Include SAV = 0, Include EAV = 0
AVID
Include SAV = 1, Include EAV = 0
AVID
Include SAV = 0, Include EAV = 1
Data
SAV
Pixel Data
EAV
Scaled pixel data, AVID start/stop reduced
AVID
Include SAV = 0, Include EAV = 0
AVID
Include SAV = 1, Include EAV = 0
AVID
Include SAV = 0, Include EAV = 1
Figure 9-4. AVID Behavior When No Ancillary Data Present
36
Internal Control Registers
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TVP5154 4 Channel Low Power PAL/NTSC/SECAM Video Decoder With Independent Scalers, Fast Lock
SLES163 - MARCH 2006
9.2.24
Address Default 7
Vertical Blanking Start Register
18h 00h 6 5 4 3 2 1 0
Vertical blanking start Vertical blanking (VBLK) start: 0111 1111 = 127 lines after start of vertical blanking interval 0000 0001 = 1 line after start of vertical blanking interval 0000 0000 = Same time as start of vertical blanking interval (default) (see Figure 4-1, Figure 4-2, and Figure 4-3) 1111 1111 = 1 line before start of vertical blanking interval 1000 0000 = 128 lines before start of vertical blanking interval
Vertical register register register
blanking is adjustable with respect to the standard vertical blanking intervals. The setting in this determines the timing of the GPCL/VBLK signal when it is configured to output vertical blank (see 03h). The setting in this register also determines the duration of the luma bypass function (see 07h).
9.2.25
Address Default 7
Vertical Blanking Stop Register
19h 00h 6 5 4 3 2 1 0
Vertical blanking stop Vertical blanking (VBLK) stop: 0111 1111 = 127 lines after stop of vertical blanking interval 0000 0001 = 1 line after stop of vertical blanking interval 0000 0000 = Same time as stop of vertical blanking interval (default) (see Figure 4-1, Figure 4-2, and Figure 4-3) 1111 1111 = 1 line before stop of vertical blanking interval 1000 0000 = 128 lines before stop of vertical blanking interval
Vertical register register register
blanking is adjustable with respect to the standard vertical blanking intervals. The setting in this determines the timing of the GPCL/VBLK signal when it is configured to output vertical blank (see 03h). The setting in this register also determines the duration of the luma bypass function (see 07h).
9.2.26
Address Default 7 6
Chrominance Control #1 Register
1Ah 0Ch 5 4 PLL reset 3 Chrominance adaptive comb filter enable (ACE) 2 Chrominance comb filter enable (CE) 1 0
Reserved Color
Automatic color gain control
Color PLL reset: 0 = Color PLL not reset (default) 1 = Color PLL reset Writing a 1 to this bit resets the color PLL and transmits a 1 in the reset bit of the GLCO output stream. Chrominance adaptive comb filter enable (ACE): 0 = Disable 1 = Enable (default) Chrominance comb filter enable (CE): 0 = Disable 1 = Enable (default) Automatic color gain control (ACGC): 00 = ACGC enabled (default) 01 = Reserved 10 = ACGC disabled 11 = ACGC frozen to the previously set value
Internal Control Registers
37
TVP5154 4 Channel Low Power PAL/NTSC/SECAM Video Decoder With Independent Scalers, Fast Lock
SLES163 - MARCH 2006
www.ti.com
9.2.27
Address Default 7
Chrominance Control #2 Register
1Bh 14h 6 Reserved 5 4 3 Reserved 2 WCF 1 0
Chrominance filter select
Wideband chroma filter (WCF): 0 = Disable 1 = Enable (default) Chrominance filter select: 00 = No notch (default) 01 = Notch 1 10 = Notch 2 11 = Notch 3 Chrominance output bandwidth (MHz):
Table 9-8. Chroma Output Bandwidth Select
WCF 0 FILTER SELECT 00 01 10 11 1 00 01 10 11 NTSC/PAL/SECAM ITU-R BT.601 1.2214 0.8782 0.7297 0.4986 1.4170 1.0303 0.8438 0.5537
38
Internal Control Registers
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TVP5154 4 Channel Low Power PAL/NTSC/SECAM Video Decoder With Independent Scalers, Fast Lock
SLES163 - MARCH 2006
9.2.28
Address Default 7
Interrupt Reset Register B
1Ch 00h 6 Reserved 5 Reserved 4 Field rate changed reset 3 Line alternation changed reset 2 Color lock changed reset 1 H/V lock changed reset 0 TV/VCR changed reset
Software initialization reset
Interrupt reset register B is used by the external processor to reset the interrupt status bits in interrupt status register B. Bits loaded with a 1 allow the corresponding interrupt status bit to reset to 0. Bits loaded with a 0 have no effect on the interrupt status bits.
Software initialization reset: 0 = No effect (default) 1 = Reset software initialization bit Field rate changed reset: 0 = No effect (default) 1 = Reset field rate changed bit Line alternation changed reset: 0 = No effect (default) 1 = Reset line alternation changed bit Color lock changed reset: 0 = No effect (default) 1 = Reset color lock changed bit H/V lock changed reset: 0 = No effect (default) 1 = Reset H/V lock changed bit TV/VCR changed reset [TV/VCR mode is determined by counting the total number of lines/frame. The mode switches to VCR for nonstandard number of lines]: 0 = No effect (default) 1 = Reset TV/VCR changed bit
9.2.29
Address Default
Interrupt Enable Register B
1Dh 00h 7 6 Reserved 5 Reserved 4 Field rate changed 3 Line alternation changed 2 Color lock changed 1 H/V lock changed 0 TV/VCR changed
Software initialization occurred enable
Interrupt enable register B is used by the external processor to mask unnecessary interrupt sources for interrupt B. Bits loaded with a 1 allow the corresponding interrupt condition to generate an interrupt on the external pin. Conversely, bits loaded with 0s mask the corresponding interrupt condition from generating an interrupt on the external pin. This register only affects the external pin, it does not affect the bits in the interrupt status register. A given condition can set the appropriate bit in the status register and not cause an interrupt on the external pin. To determine if this device is driving the interrupt pin either AND interrupt status register B with interrupt enable register B or check the state of interrupt B in the interrupt B active register.
Internal Control Registers
39
TVP5154 4 Channel Low Power PAL/NTSC/SECAM Video Decoder With Independent Scalers, Fast Lock
SLES163 - MARCH 2006
www.ti.com
Software initialization occurred enable: 0 = Disabled (default) 1 = Enabled Field rate changed: 0 = Disabled (default) 1 = Enabled Line alternation changed: 0 = Disabled (default) 1 = Enabled Color lock changed: 0 = Disabled (default) 1 = Enabled H/V lock changed: 0 = Disabled (default) 1 = Enabled TV/VCR changed: 0 = Disabled (default) 1 = Enabled
9.2.30
Address Default 7
Interrupt Configuration Register B
1Eh 00h 6 5 4 Reserved 3 2 1 0 Interrupt polarity B
Interrupt polarity B: 0 = Interrupt B is active low (default). 1 = Interrupt B is active high.
Interrupt polarity B must be same as interrupt polarity A bit at bit 0 of the interrupt configuration register A at address C2h. Interrupt configuration register B is used to configure the polarity of interrupt B on the external interrupt pin. When the interrupt B is configured for active low, the pin is driven low when active and high-impedance when inactive (open-drain). Conversely, when the interrupt B is configured for active high, it is driven high for active and driven low for inactive.
40
Internal Control Registers
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TVP5154 4 Channel Low Power PAL/NTSC/SECAM Video Decoder With Independent Scalers, Fast Lock
SLES163 - MARCH 2006
9.2.31
Address Default 7
Output Control
1Fh 00h 6 Bit swap 5 Ancillary Enable 4 Parity modifier 3 SAV/EAV modifier 2 1 Output mode 0
Output mode 000 = Mode 0 : Unscaled data clocked by clock 1 001 = Mode 1 : Scaled data clocked by clock 1 010 = Mode 2 : Multiplexed data with separate clocks 011 = Mode 3 : Multiplexed data with clock 1 at 54 MHz 100 = Mode 4 : Unscaled/Scaled field toggled data clocked by clock 1 SAV/EAV modifier 0 = SAV/EAV codes not modified 1 = SAV/EAV MSB modified. MSB = 1 indicates unscaled data, MSB = 0 indicates scaled data Parity modifier 0 = Parity calculation includes SAV/EAV MSB 1 = Parity calculation does not include SAV/EAV MSB Ancillary Enable 0 = Ancillary data not enabled 1 = Ancillary data packet added to indicate scaled or unscaled data Note : Scaled/unscaled ancillary data cannot be enabled at the same time as VBI ancillary data Bit swap 0 = chx_out(0) corresponds to data LSB, chx_out(7) corresponds to data MSB 1 = chx_out(0) corresponds to data MSB, chx_out(7) corresponds to data LSB
Table 9-9. Ancillary Data Format and Sequence
BYTE NO. 0 1 2 3 4 5 6 Z 8 9 10 11 1 1 0 0 0 0 0 0 0 0 D7 (MSB) 0 1 1 NEP 1 0 D6 0 1 1 EP 0 1 D5 0 1 1 0 0 0 D4 0 1 1 1 0 0 0 00h 00h 00h 0 0 0 D3 0 1 1 DID3 0 0 0 D2 0 1 1 DID2 0 0 0 D1 0 1 1 DID1 0 0 D0 (LSB) 0 1 1 DID0 0 1 Data ID (DID) Secondary data ID (SDID) Number of 32 bit data (NN) Internal data ID0 (IDID0) Video line # [9:8] Internal data ID1 (IDID1) Data byte Data byte Check sum Fill byte Data DESCRIPTION Ancillary data preamble
Video line # [7:0]
Internal Control Registers
41
TVP5154 4 Channel Low Power PAL/NTSC/SECAM Video Decoder With Independent Scalers, Fast Lock
SLES163 - MARCH 2006
www.ti.com
EP: NEP: DID:
Even parity for D0-D5 Negated even parity For un-scaled data D0 thru D3 taken from EAV DID value for un-scaled data stream register low nibble for field 0 and from high nibble for field 1 For scaled data D0 thru D3 taken from EAV DID value for scaled data stream register low nibble for field 0 and from high nibble for field 1
SDID: NN: IDID0: IDID1: CS: Fill byte:
Zero data. Indicates 1 D word of data Transaction video line number [7:0] Bit 0/1 = Transaction video line number [9:8] Sum of D0-D7 of DID through last data byte. Fill bytes make a multiple of 4 bytes from byte 0 to last fill byte. For teletext modes, byte 8 is the sync pattern byte. Byte 9 is 1. Data (the first data byte).
9.2.32
Address Default 7
Active Video Cropping Start Pixel MSB for Scaled Data Register
25h 00h 6 5 4 3 2 1 0
AVID start pixel MSB [9:2]
Active video cropping start pixel MSB [9:2], set this register first before setting register 26h. The TVP5154 decoder updates the AVID start values only when register 26h is written to. This start pixel value is relative to the default values of the AVID start pixel.
9.2.33
Address Default 7
Active Video Cropping Start Pixel LSB for Scaled Data Register
26h 00h 6 5 Reserved 4 3 2 Active 1 0
AVID start pixel LSB [1:0]
AVID active: 0 = AVID out active in VBLK (default) 1 = AVID out inactive in VBLK Active video cropping start pixel LSB [1:0]: The TVP5154 decoder updates the AVID start values only when this register is written to. AVID start [9:0]: 01 1111 1111 = 511 00 0000 0001 = 1 00 0000 0000 = 0 (default) 11 1111 1111 = - 1 10 0000 0000 = - 512
42
Internal Control Registers
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TVP5154 4 Channel Low Power PAL/NTSC/SECAM Video Decoder With Independent Scalers, Fast Lock
SLES163 - MARCH 2006
9.2.34
Address Default 7
Video Standard Register
28h 00h 6 Reserved 5 4 3 2 Video standard 1 0
Video standard: 0000 = 0001 = 0010 = 0011 = 0100 = 0101 = 0110 = 0111 = 1000 = 1001 = 1010 = 1011 = 1100 =
Autoswitch mode (default) Reserved (M) NTSC ITU-R BT.601 Reserved (B, G, H, I, N) PAL ITU-R BT.601 Reserved (M) PAL ITU-R BT.601 Reserved (Combination-N) PAL ITU-R BT.601 Reserved NTSC 4.43 ITU-R BT.601 Reserved SECAM ITU-R BT.601
With the autoswitch code running, the user can force the device to operate in a particular video standard mode and sample rate by writing the appropriate value into this register.
9.2.35
Address Default 7
Active Video Cropping Stop Pixel MSB for Scaled Data Register
29h 00h 6 5 4 3 2 1 0
AVID stop pixel MSB [9:2]
Active video cropping stop pixel MSB [9:2], set this register first before setting the register 2Ah. The TVP5154 decoder updates the AVID stop values only when register 2Ah is written to. This stop pixel value is relative to the default values of the AVID stop pixel.
9.2.36
Address Default 7
Active Video Cropping Stop Pixel LSB for Scaled Data Register
2Ah 00h 6 5 Reserved 4 3 2 1 0
AVID stop pixel LSB [1:0]
Active video cropping stop pixel LSB [1:0]: The number of pixels of active video must be an even number. The TVP5154 decoder updates the AVID stop values only when this register is written to. AVID stop [9:0] : 01 1111 1111 = 511 00 0000 0001 = 1 00 0000 0000 = 0 (default) (see Figure 4-1, Figure 4-2, and Figure 4-3) 11 1111 1111 = - 1 10 0000 0000 = - 512
Internal Control Registers
43
TVP5154 4 Channel Low Power PAL/NTSC/SECAM Video Decoder With Independent Scalers, Fast Lock
SLES163 - MARCH 2006
www.ti.com
9.2.37
Address 7
Cb Gain Factor Register
2Ch 6 5 4 Cb gain factor 3 2 1 0
This is a read-only register that provides the gain applied to the Cb in the YCbCr data stream.
9.2.38
Address 7
Cr Gain Factor Register
2Dh 6 5 4 Cr gain factor 3 2 1 0
This is a read-only register that provides the gain applied to the Cr in the YCbCr data stream.
9.2.39
Address Default 7
656 Revision Select Register
30h 00h 6 5 4 3 2 1 0 656 Rev
656 Revision Select 0 = Adheres to ITU-R BT656.4 timing. 1 = Adheres to ITU-R BT656.3 timing.
9.2.40
Address Default 7
MSB of Device ID Register
80h 51h 6 5 4 3 2 1 0
MSB of device ID
This register identifies the MSB of the device ID. Value = 0x51.
9.2.41
Address Default 7
LSB of Device ID Register
81h 54h 6 5 4 3 2 1 0
LSB of device ID
This register identifies the LSB of the device ID. Value = 0x54.
9.2.42
Address Default 7
ROM Major Version Register
82h 02h 6 5 4 3 2 1 0
ROM major version (1) (1) This register can contain a number from 0x01 to 0xFF.
44
Internal Control Registers
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TVP5154 4 Channel Low Power PAL/NTSC/SECAM Video Decoder With Independent Scalers, Fast Lock
SLES163 - MARCH 2006
9.2.43
Address Default 7
ROM Minor Version Register
83h 00h 6 5 4 ROM minor 3 version (1) 2 1 0
(1)
This register can contain a number from 0x01 to 0xFF.
9.2.44
Address 7
Vertical Line Count MSB Register
84h 6 5 Reserved 4 3 2 1 0
Vertical line count MSB
Vertical line count bits [9:8] .
9.2.45
Address 7
Vertical Line Count LSB Register
85h 6 5 4 3 2 1 0
Vertical line count LSB
Vertical line count bits [7:0] Registers 84h and 85h can be read and combined to extract the detected number of lines per frame. This can be used with nonstandard video signals such as a VCR in fast-forward or rewind modes to synchronize the downstream video circuitry.
9.2.46
Address 7
Interrupt Status Register B
86h 6 Reserved 5 Command ready 4 Field rate changed 3 Line alternation changed 2 Color lock changed 1 H/V lock changed 0 TV/VCR changed
Software initialization
Software initialization: 0 = Software initialization is not ready (default). 1 = Software initialization is ready. Command ready: 0 = TVP5154 is not ready to accept a new command (default). 1 = TVP5154 is ready to accept a new command. Field rate changed: 0 = Field rate has not changed (default). 1 = Field rate has changed. Line alternation changed: 0 = Line alteration has not changed (default). 1 = Line alternation has changed. Color lock changed: 0 = Color lock status has not changed (default). 1 = Color lock status has changed. H/V lock changed: 0 = H/V lock status has not changed (default). 1 = H/V lock status has changed. TV/VCR changed: 0 = TV/VCR status has not changed (default). 1 = TV/VCR status has changed.
Interrupt status register B is polled by the external processor to determine the interrupt source for interrupt B. After an interrupt condition is set, it can be reset by writing to the interrupt reset register B at subaddress 1Ch with a 1 in the appropriate bit.
Internal Control Registers
45
TVP5154 4 Channel Low Power PAL/NTSC/SECAM Video Decoder With Independent Scalers, Fast Lock
SLES163 - MARCH 2006
www.ti.com
9.2.47
Address 7
Interrupt Active Register B
87h 6 5 4 Reserved 3 2 1 0 Interrupt B
Interrupt B: 0 = Interrupt B is not active on the external terminal (default). 1 = Interrupt B is active on the external terminal.
The interrupt active register B is polled by the external processor to determine if interrupt B is active.
9.2.48
Address 7
Status Register #1
88h 6 Line-alternating status 5 Field rate status 4 Lost lock detect 3 Color subcarrier lock status 2 Vertical sync lock status 1 Horizontal sync lock status 0 TV/VCR status
Peak white detect status
Peak white detect status: 0 = Peak white is not detected. 1 = Peak white is detected. Line-alternating status: 0 = Nonline alternating 1 = Line alternating Field rate status: 0 = 60 Hz 1 = 50 Hz Lost lock detect: 0 = No lost lock since status register #1 was last read. 1 = Lost lock since status register #1 was last read. Color subcarrier lock status: 0 = Color subcarrier is not locked. 1 = Color subcarrier is locked. Vertical sync lock status: 0 = Vertical sync is not locked. 1 = Vertical sync is locked. Horizontal sync lock status: 0 = Horizontal sync is not locked. 1 = Horizontal sync is locked. TV/VCR status. TV mode is determined by detecting standard line-to-line variations and specific chroma SCH phases based on the standard input video format. VCR mode is determined by detecting variations in the chroma SCH phases compared to the chroma SCH phases of the standard input video format. 0 = TV 1 = VCR
9.2.49
Address 7 Reserved
Status Register #2
89h 6 Weak signal detection 5 PAL switch polarity 4 Field sequence status 3 AGC and offset frozen status 2 1 Reserved 0
Weak signal detection: 0 = No weak signal 1 = Weak signal mode PAL switch polarity of first line of odd field: 0 = PAL switch is 0 1 = PAL switch is 1 Field sequence status: 0 = Even field 1 = Odd field AGC and offset frozen status: 0 = AGC and offset are not frozen. 1 = AGC and offset are frozen. 46 Internal Control Registers
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TVP5154 4 Channel Low Power PAL/NTSC/SECAM Video Decoder With Independent Scalers, Fast Lock
SLES163 - MARCH 2006
9.2.50
Address 7
Status Register #3
8Ah 6 5 4 3 digital) (1) 2 1 0
Front-end AGC gain value (analog and (1)
Represents 8 bits (MSB) of a 10-bit value This register provides the front-end AGC gain value of both analog and digital gains.
9.2.51
Address 7
Status Register #4
8Bh 6 5 4 3 2 1 0
Subcarrier to horizontal (SCH) phase SCH (color PLL subcarrier phase at 50% of the falling edge of horizontal sync of line one of odd field; step size 360/256): 0000 0000 = 0.00o 0000 0001 = 1.41o 0000 0010 = 2.81o 1111 1110 = 357.2o 1111 1111 = 358.6o
9.2.52
Address
Status Register #5
8Ch 7 6 5 Reserved 4 3 2 Video standard 1 0 Sampling rate
Autoswitch mode
This register contains information about the detected video standard and the sampling rate at which the device is currently operating. When autoswitch code is running, this register must be tested to determine which video standard has been detected. Autoswitch mode: 0 = Stand-alone (forced video standard) mode 1 = Autoswitch mode Table 9-10. Auto Switch Video Standard
VIDEO STANDARD [3:1] BIT 3 0 0 0 0 0 0 0 0 1 1 1 1 (1) BIT 2 0 0 0 0 1 1 1 1 0 0 0 0 BIT 1 0 0 1 1 0 0 1 1 0 0 1 1 SR (1) BIT 0 0 1 0 1 0 1 0 1 0 1 0 1 Reserved (M) NTSC ITU-R BT.601 Reserved (B, G, H, I, N) PAL ITU-R BT.601 Reserved (M) PAL ITU-R BT.601 Reserved PAL-N ITU-R BT.601 Reserved NTSC 4.43 ITU-R BT.601 Reserved SECAM ITU-R BT.601 VIDEO STANDARD
Sampling rate (SR): 0 = Reserved, 1 = ITU-R BT.601
Internal Control Registers
47
TVP5154 4 Channel Low Power PAL/NTSC/SECAM Video Decoder With Independent Scalers, Fast Lock
SLES163 - MARCH 2006
www.ti.com
9.2.53
Address Address 90h 91h 92h 93h
Closed Caption Data Registers
90h-93h 7 6 5 4 3 2 1 0
Closed caption field 1 byte 1 Closed caption field 1 byte 2 Closed caption field 2 byte 1 Closed caption field 2 byte 2
These registers contain the closed caption data arranged in bytes per field.
9.2.54
Address
WSS Data Registers
94h-99h
NTSC
Address 94h 95h 96h 97h 98h 99h b13 b12 b13 b12 7 6 5 b5 b11 b19 b5 b11 b19 4 b4 b10 b18 b4 b10 b18 3 b3 b9 b17 b3 b9 b17 2 b2 b8 b16 b2 b8 b16 1 b1 b7 b15 b1 b7 b15 0 b0 b6 b14 b0 b6 b14 BYTE WSS field 1 byte 1 WSS field 1 byte 2 WSS field 1 byte 3 WSS field 2 byte 1 WSS field 2 byte 2 WSS field 2 byte 3
These registers contain the wide screen signaling (WSS) data for NTSC. Bits 0-1 represent word 0, aspect ratio Bits 2-5 represent word 1, header code for word 2 Bits 6-13 represent word 2, copy control Bits 14-19 represent word 3, CRC PAL/SECAM
Address 94h 95h 96h 97h 98h 99h b7 b6 b5 b13 7 b7 6 b6 5 b5 b13 4 b4 b12 b4 b12 3 b3 b11 b3 b11 2 b2 b10 b2 b10 1 b1 b9 b1 b9 0 b0 b8 b0 b8 BYTE WSS field 1 byte 1 WSS field 1 byte 2 WSS field 2 byte 1 WSS field 2 byte 2
Reserved
Reserved
PAL/SECAM: Bits 0-3 represent group 1, aspect ratio Bits 4-7 represent group 2, enhanced services Bits 8-10 represent group 3, subtitles Bits 11-13 represent group 4, others
48
Internal Control Registers
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TVP5154 4 Channel Low Power PAL/NTSC/SECAM Video Decoder With Independent Scalers, Fast Lock
SLES163 - MARCH 2006
9.2.55
Address
VPS Data Registers
9Ah-A6h 7 6 5 4 VPS byte 1 VPS byte 2 VPS byte 3 VPS byte 4 VPS byte 5 VPS byte 6 VPS byte 7 VPS byte 8 VPS byte 9 VPS byte 10 VPS byte 11 VPS byte 12 VPS byte 13 3 2 1 0
Address 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h A1h A2h A3h A4h A5h A6h
These registers contain the entire VPS data line except the clock run-in code or the start code
9.2.56
Address
VITC Data Registers
A7h-AFh 7 6 5 4 3 2 1 0
Address A7h A8h A9h AAh ABh ACh ADh AEh AFh
VITC byte 1, frame byte 1 VITC byte 2, frame byte 2 VITC byte 3, seconds byte 1 VITC byte 4, seconds byte 2 VITC byte 5, minutes byte 1 VITC byte 6, minutes byte 2 VITC byte 7, hour byte 1 VITC byte 8, hour byte 2 VITC byte 9, CRC
These registers contain the VITC data.
9.2.57
Address 7
VBI FIFO Read Data Register
B0h 6 5 4 FIFO read data 3 2 1 0
This address is provided to access VBI data in the FIFO through the host port. All forms of teletext data come directly from the FIFO, while all other forms of VBI data can be programmed to come from the registers or from the FIFO. Current status of the FIFO can be found at address C6h and the number of bytes in the FIFO is located at address C7h. If the host port is to be used to read data from the FIFO, then the output formatter must be disabled at address CDh bit 0. The format used for the VBI FIFO is shown in Section 4.9.
Internal Control Registers
49
TVP5154 4 Channel Low Power PAL/NTSC/SECAM Video Decoder With Independent Scalers, Fast Lock
SLES163 - MARCH 2006
www.ti.com
9.2.58
Address Default Address B1h B2h B3h B4h B5h B6h B7h B8h B9h BAh
Teletext Filter and Mask Registers
B1h-BAh 00h 7 6 5 4 3 2 1 0
Filter 1 mask 1 Filter 1 mask 2 Filter 1 mask 3 Filter 1 mask 4 Filter 1 mask 5 Filter 2 mask 1 Filter 2 mask 2 Filter 2 mask 3 Filter 2 mask 4 Filter 2 mask 5
Filter 1 pattern 1 Filter 1 pattern 2 Filter 1 pattern 3 Filter 1 pattern 4 Filter 1 pattern 5 Filter 2 pattern 1 Filter 2 pattern 2 Filter 2 pattern 3 Filter 2 pattern 4 Filter 2 pattern 5
For an NABTS system, the packet prefix consists of five bytes. Each byte contains four data bits (D[3:0]) interlaced with four Hamming protection bits (H[3:0]):
Bit 7 D[3] Bit 6 H[3] Bit 5 D[2] Bit 4 H[2] Bit 3 D[1] Bit 2 H[1] Bit 1 D[0] Bit 0 H[0]
Only the data portion D[3:0] from each byte is applied to a teletext filter function with the corresponding pattern bits P[3:0] and mask bits M[3:0]. Hamming protection bits are ignored by the filter. For a WST system (PAL or NTSC), the packet prefix consists of two bytes so that two patterns are used. Patterns 3, 4, and 5 are ignored. The mask bits enable filtering using the corresponding bit in the pattern register. For example, a 1 in the LSB of mask 1 means that the filter module must compare the LSB of nibble 1 in the pattern register to the first data bit on the transaction. If these match, then a true result is returned. A 0 in a bit of mask 1 means that the filter module must ignore that data bit of the transaction. If all 0s are programmed in the mask bits, then the filter matches all patterns returning a true result (default 00h). Pattern and mask for each byte and filter are referred as <1,2><1,2,3,4,5> where: <1,2> identifies the filter 1 or 2 identifies the pattern or mask <1,2,3,4,5> identifies the byte number
50
Internal Control Registers
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TVP5154 4 Channel Low Power PAL/NTSC/SECAM Video Decoder With Independent Scalers, Fast Lock
SLES163 - MARCH 2006
9.2.59
Address Default 7
Teletext Filter Control Register
BBh 00h 6 Reserved 5 4 Filter logic 3 2 Mode 1 TTX filter 2 enable 0 TTX filter 1 enable
Filter logic: allows different logic to be applied when combining the decision of filter 1 and filter 2 as follows: 00 = NOR (Default) 01 = NAND 10 = OR 11 = AND Mode: 0 = Teletext WST PAL mode B (2 header bytes) (default) 1 = Teletext NABTS NTSC mode C (5 header bytes) TTX filter 2 enable 0 = Disabled (default) 1 = Enabled TTX filter 1 enable: 0 = Disabled (default) 1 = Enabled
If the filter matches or if the filter mask is all 0s, then a true result is returned.
9.2.60
Address Default 7
Interrupt Status Register A
C0h 00h 6 Lock interrupt 5 4 Reserved 3 2 FIFO threshold interrupt 1 Line interrupt 0 Data interrupt
Lock state interrupt
The interrupt status register A can be polled by the host processor to determine the source of an interrupt. After an interrupt condition is set it can be reset by writing to this register with a 1 in the appropriate bit(s). Lock state interrupt: 0 = TVP5154 is not locked to the video signal (default) 1 = TVP5154 is locked to the video signal. Lock interrupt: 0 = A transition has not occurred on the lock signal (default). 1 = A transition has occurred on the lock signal. FIFO threshold interrupt: 0 = The amount of data in the FIFO has not yet crossed the threshold programmed at address C8h (default). 1 = The amount of data in the FIFO has crossed the threshold programmed at address C8h. Line interrupt: 0 = The video line number has not yet been reached (default). 1 = The video line number programmed in address CAh has occurred. Data interrupt: 0 = No data is available (default). 1 = VBI data is available either in the FIFO or in the VBI data registers.
Internal Control Registers
51
TVP5154 4 Channel Low Power PAL/NTSC/SECAM Video Decoder With Independent Scalers, Fast Lock
SLES163 - MARCH 2006
www.ti.com
9.2.61
Address Default 7
Interrupt Enable Register A
C1h 00h 6 Lock interrupt enable 5 Cycle complete interrupt enable 4 Bus error interrupt enable 3 Reserved 2 FIFO threshold interrupt enable 1 Line interrupt enable 0 Data interrupt enable
Reserved
The interrupt enable register A is used by the host processor to mask unnecessary interrupt sources. Bits loaded with a 1 allow the corresponding interrupt condition to generate an interrupt on the external pin. Conversely, bits loaded with a 0 mask the corresponding interrupt condition from generating an interrupt on the external pin. This register only affects the interrupt on the external terminal, it does not affect the bits in interrupt status register A. A given condition can set the appropriate bit in the status register and not cause an interrupt on the external terminal. To determine if this device is driving the interrupt terminal either perform a logical AND of interrupt status register A with interrupt enable register A, or check the state of the interrupt A bit in the interrupt configuration register at address C2h. Lock interrupt enable: 0 = Disabled (default) 1 = Enabled Cycle complete interrupt enable: 0 = Disabled (default) 1 = Enabled Bus error interrupt enable: 0 = Disabled (default) 1 = Enabled FIFO threshold interrupt enable: 0 = Disabled (default) 1 = Enabled Line interrupt enable: 0 = Disabled (default) 1 = Enabled Data interrupt enable: 0 = Disabled (default) 1 = Enabled
52
Internal Control Registers
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TVP5154 4 Channel Low Power PAL/NTSC/SECAM Video Decoder With Independent Scalers, Fast Lock
SLES163 - MARCH 2006
9.2.62
Address Default 7
Interrupt Configuration Register A
C2h 04h 6 5 Reserved 4 3 2 YCbCr enable (VDPOE) 1 Interrupt A 0 Interrupt polarity A
YCbCr enable (VDPOE): 0 = YCbCr pins are high impedance. 1 = YCbCr pins are active if other conditions are met (default). Interrupt A (read-only): 0 = Interrupt A is not active on the external pin (default). 1 = Interrupt A is active on the external pin. Interrupt polarity A: 0 = Interrupt A is active low (default). 1 = Interrupt A is active high.
Interrupt configuration register A is used to configure the polarity of the external interrupt terminal. When interrupt A is configured as active low, the terminal is driven low when active and high-impedance when inactive (open collector). Conversely, when the terminal is configured as active high, it is driven high when active and driven low when inactive.
9.2.63
Address Default
VDP Configuration RAM Register
C3h B8h 7 C4h 1Fh C5h 00h 6 5 4 3 2 1 0
Address C3h C4h C5h
Configuration data RAM address (7:0) Reserved RAM address 8
The configuration RAM data is provided to initialize the VDP with initial constants. The configuration RAM is 512 bytes organized as 32 different configurations of 16 bytes each. The first 12 configurations are defined for the current VBI standards. An additional 2 configurations can be used as a custom programmed mode for unique standards like Gemstar. Address C3h is used to read or write to the RAM. The RAM internal address counter is automatically incremented with each transaction. Addresses C5h and C4h make up a 9-bit address to load the internal address counter with a specific start address. This can be used to write a subset of the RAM for only those standards of interest. Registers D0h-FBh must all be programmed with FFh, before writing or reading the configuration RAM. Full field mode (CFh) must be disabled as well. The suggested RAM contents are shown below. All values are hexadecimal.
Internal Control Registers
53
TVP5154 4 Channel Low Power PAL/NTSC/SECAM Video Decoder With Independent Scalers, Fast Lock
SLES163 - MARCH 2006 Index Reserved WST SECAM Reserved WST PAL B Reserved WST PAL C Reserved WST NTSC Reserved NABTS, NTSC Reserved NABTS, NTSC-J Reserved CC, PAL/SECAM Reserved CC, NTSC Reserved WSS, PAL/SECAM Reserved WSS, NTSC C Reserved VITC, PAL/SECAM Reserved VITC, NTSC Reserved VPS, PAL Reserved Custom 1 Reserved Custom 2 Address 000 010 020 030 040 050 060 070 080 090 0A0 0B0 0C0 0D0 0E0 0F0 100 110 120 130 140 150 160 170 180 190 1A0 1B0 1C0 1D0 AA AA FF FF BA CE 2B 0 0 0 0 0 8F 6D 0 0 0 0 0 8F 6D 38 00 3F 00 0 71 6E 5B 55 C5 FF 0 71 6E AA 2A FF 3F 04 51 6E AA 2A FF 3F 04 51 6E AA AA FF FF A7 2E 20 AA AA FF FF E7 2E 20 AA AA FF FF 27 2E 20 AA AA FF FF E7 2E 20 AA AA FF FF 27 2E 20 AA AA FF FF E7 2E 20 0 1 2 3 4 5 6 7 8 9 A B C D Reserved 26 E6 B4 0E 0 0 0
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E F
10
0
Reserved 2B A6 72 10 0 0 0 10 0
Reserved 22 A6 98 0D 0 0 0 10 0
Reserved 23 69 93 0D 0 0 0 10 0
Reserved 22 69 93 0D 0 0 0 15 0
Reserved 23 69 93 0D 0 0 0 10 0
Reserved 02 A6 7B 09 0 0 0 27 0
Reserved 02 69 8C 09 0 0 0 27 0
Reserved 42 A6 CD 0F 0 0 0 3A 0
Reserved 43 69 7C 08 0 0 0 39 0
Reserved 49 A6 85 08 0 0 0 4C 0
Reserved 49 69 94 08 0 0 0 4C 0
Reserved 0D A6 DA 0B 0 0 0 60 0
Reserved Programmable Reserved Programmable
54
Internal Control Registers
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TVP5154 4 Channel Low Power PAL/NTSC/SECAM Video Decoder With Independent Scalers, Fast Lock
SLES163 - MARCH 2006
9.2.64
Address 7 FIFO full error
VDP Status Register
C6h 6 FIFO empty 5 TTX available 4 CC field 1 available 3 CC field 2 available 2 WSS available 1 VPS available 0 VITC available
The VDP status register indicates whether data is available in either the FIFO or data registers, and status information about the FIFO. Reading data from the corresponding register does not clear the status flags automatically. These flags are only reset by writing a 1 to the respective bit. However, bit 6 is updated automatically. FIFO full error: 0 = No FIFO full error 1 = FIFO was full during a write to FIFO. The FIFO full error flag is set when the current line of VBI data can not enter the FIFO. For example, if the FIFO has only 10 bytes left and teletext is the current VBI line, the FIFO full error flag is set, but no data is written because the entire teletext line will not fit. However, if the next VBI line is closed caption requiring only 2 bytes of data plus the header, this goes into the FIFO. Even if the full error flag is set. FIFO empty: 0 = FIFO is not empty 1 = FIFO is empty. TTX available: 0 = Teletext data is not available. 1 = Teletext data is available. CC field 1 available: 0 = Closed caption data from field 1 is not available. 1 = Closed caption data from field 1 is available. CC field 2 available: 0 = Closed caption data from field 2 is not available. 1 = Closed caption data from field 2 is available. WSS available: 0 = WSS data is not available. 1 = WSS data is available. VPS available 0 = VPS data is not available. 1 = VPS data is available. VITC available: 0 = VITC data is not available. 1 = VITC data is available.
9.2.65
Address 7
FIFO Word Count Register
C7h 6 5 4 3 2 1 0
Number of words
This register provides the number of words in the FIFO. 1 word equals 2 bytes.
9.2.66
Address Default 7
FIFO Interrupt Threshold Register
C8h 80h 6 5 4 3 2 1 0
Number of words
This register is programmed to trigger an interrupt when the number of words in the FIFO exceeds this value (default 80h). This interrupt must be enabled at address C1h. 1 word equals 2 bytes.
Internal Control Registers
55
TVP5154 4 Channel Low Power PAL/NTSC/SECAM Video Decoder With Independent Scalers, Fast Lock
SLES163 - MARCH 2006
www.ti.com
9.2.67
Address Default 7
FIFO Reset Register
C9h 00h 6 5 4 Any data 3 2 1 0
Writing any data to this register resets the FIFO and clears any data present in both the FIFO and the VDP registers.
9.2.68
Address Default 7
Line Number Interrupt Register
CAh 00h 6 Field 2 enable 5 4 3 2 Line number 1 0
Field 1 enable
This register is programmed to trigger an interrupt when the video line number matches this value in bits 5:0. This interrupt must be enabled at address C1h. The value of 0 or 1 does not generate an interrupt. Field 1 enable: 0 = Disabled (default) 1 = Enabled Field 2 enable: 0 = Disabled (default) 1 = Enabled Line number: (default 00h)
9.2.69
Address Default Address CBh CCh
Pixel Alignment Registers
CBh 4Eh 7 CCh 00h 6 5 Reserved 4 3 2 1 0
Switch pixel [7:0] Switch pixel [9:8]
These registers form a 10-bit horizontal pixel position from the falling edge of sync, where the VDP controller initiates the program from one line standard to the next line standard; for example, the previous line of teletext to the next line of closed caption. This value must be set so that the switch occurs after the previous transaction has cleared the delay in the VDP, but early enough to allow the new values to be programmed before the current settings are required.
9.2.70
Address Default 7
FIFO Output Control Register
CDh 01h 6 5 4 Reserved 3 2 1 0 Host access enable
This register is programmed to allow I2C access to the FIFO or allowing all VDP data to go out the video port. Host access enable: 0 = Output FIFO data to the video output Y[7:0] 1 = Allow I2C access to the FIFO data (default)
56
Internal Control Registers
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TVP5154 4 Channel Low Power PAL/NTSC/SECAM Video Decoder With Independent Scalers, Fast Lock
SLES163 - MARCH 2006
9.2.71
Address Default 7
Full Field Enable Register
CFh 00h 6 5 4 Reserved 3 2 1 0 Full field enable
This register enables the full field mode. In this mode, all lines outside the vertical blank area and all lines in the line mode registers programmed with FFh are sliced with the definition of register FCh. Values other than FFh in the line mode registers allow a different slice mode for that particular line. Full field enable: 0 = Disable full field mode (default) 1 = Enable full field mode
Internal Control Registers
57
TVP5154 4 Channel Low Power PAL/NTSC/SECAM Video Decoder With Independent Scalers, Fast Lock
SLES163 - MARCH 2006
www.ti.com
9.2.72
Address Default Address D0h D1h D2h D3h D4h D5h D6h D7h D8h D9h DAh DBh DCh DDh DEh DFh E0h E1h E2h E3h E4h E5h E6h E7h E8h E9h EAh EBh ECh EDh EEh EFh F0h F1h F2h F3h F4h F5h F6h F7h F8h F9h FAh FBh
Line Mode Registers
D0h 00h 7 D1h-FBh FFh 6 5 4 3 Line 6 Field 1 Line 6 Field 2 Line 7 Field 1 Line 7 Field 2 Line 8 Field 1 Line 8 Field 2 Line 9 Field 1 Line 9 Field 2 Line 10 Field 1 Line 10 Field 2 Line 11 Field 1 Line 11 Field 2 Line 12 Field 1 Line 12 Field 2 Line 13 Field 1 Line 13 Field 2 Line 14 Field 1 Line 14 Field 2 Line 15 Field 1 Line 15 Field 2 Line 16 Field 1 Line 16 Field 2 Line 17 Field 1 Line 17 Field 2 Line 18 Field 1 Line 18 Field 2 Line 19 Field 1 Line 19 Field 2 Line 20 Field 1 Line 20 Field 2 Line 21 Field 1 Line 21 Field 2 Line 22 Field 1 Line 22 Field 2 Line 23 Field 1 Line 23 Field 2 Line 24 Field 1 Line 24 Field 2 Line 25 Field 1 Line 25 Field 2 Line 26 Field 1 Line 26 Field 2 Line 27 Field 1 Line 27 Field 2 2 1 0
58
Internal Control Registers
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TVP5154 4 Channel Low Power PAL/NTSC/SECAM Video Decoder With Independent Scalers, Fast Lock
SLES163 - MARCH 2006
These registers program the specific VBI standard at a specific line in the video field Bit 7: 0 = Disable filtering of null bytes in closed caption modes 1 = Enable filtering of null bytes in closed caption modes (default) In teletext modes, bit 7 enables the data filter function for that particular line. If it is set to 0, then the data filter passes all data on that line. Bit 6: 0 = Send VBI data to registers only. 1 = Send VBI data to FIFO and the registers. Teletext data only goes to FIFO. (default) Bit 5: 0 = Allow VBI data with errors in the FIFO 1 = Do not allow VBI data with errors in the FIFO (default) Bit 4: 0 = Do not enable error detection and correction 1 = Enable error detection and correction (when bits [3:0] = 1 2, 3, and 4 only) (default) Bits [3:0]: 0000 = WST SECAM 0001 = WST PAL B 0010 = WST PAL C 0011 = WST NTSC 0100 = NABTS NTSC C 0101 = NABTS NTSC D 0110 = CC PAL 0111 = CC NTSC 1000 = WSS PAL 1001 = WSS NTSC 1010 = VITC PAL 1011 = VITC NTSC 1100 = VPS PAL 1101 = Custom 1 1110 = Custom 2 1111 = Active video (VDP off) (default) A value of FFh in the line mode registers is required for any line to be sliced as part of the full field mode.
Internal Control Registers
59
TVP5154 4 Channel Low Power PAL/NTSC/SECAM Video Decoder With Independent Scalers, Fast Lock
SLES163 - MARCH 2006
www.ti.com
9.2.73
Address Default 7
Full Field Mode Register
FCh 7Fh 6 5 4 3 Full field mode 2 1 0
This register programs the specific VBI standard for full field mode. It can be any VBI standard. Individual line settings take priority over the full field register. This allows each VBI line to be programmed independently but have the remaining lines in full field mode. The full field mode register has the same definitions as the line mode registers (default 7Fh).
9.2.74
Address Default 7
Decoder write enable
FEh 0Fh 6 Reserved 5 4 3 Decoder 4 2 Decoder 3 1 Decoder 2 0 Decoder 1
This register controls which of the four decoder cores receives I2C write transactions. A `1' in the corresponding bit position will enable the decoder to receive write commands. Any combination of decoders can be configured to receive write commands, allowing all four decoders to be programmed concurrently.
9.2.75
Address Default 7
Decoder read enable
FFh 00h 6 Reserved 5 4 3 Decoder 4 2 Decoder 3 1 Decoder 2 0 Decoder 1
This register controls which of the four decoder cores responds to I2C read transactions. A 1 in the corresponding bit position will enable the decoder to respond to read commands. If more than one decoder is enabled for reading then the lowest numbered decoder only will respond. Reads from multiple decoders at the same time is not possible. Note, when register 0xFE is written to with any value then register 0xFF will be set to 0x00. Likewise when register 0xFF is written to with any value then register 0xFE will be set to 0x00.
9.3
Indirect Register Definitions
To write to the TVP5154 indirect registers, it is required that the registers be unlocked using a password. The password prevents undesireable writes into the device at startup due to power surges for example. The following example demonstrates the method for unlocking the indirect registers. After writing to the desired indirect registers described below, it is recommended that the device be locked again. Unlock the device: 1. Write 0x51 to I2C_0x21. //MSB data 2. Write 0x54 to I2C_0x22. //LSB data 3. Write 0xFF to I2C_0x23. //Data address 4. Write 0x04 to I2C_0x24. //Write command Lock the device: 1. Write 0x00 to I2C_0x21. //MSB data
60
Internal Control Registers
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TVP5154 4 Channel Low Power PAL/NTSC/SECAM Video Decoder With Independent Scalers, Fast Lock
SLES163 - MARCH 2006
2. Write 0x00 to I2C_0x22. //LSB data 3. Write 0xFF to I2C_0x23. //Data address 4. Write 0x04 to I2C_0x24. //Write command Indirect registers are written to by performing the I2C transaction shown below. START : DEVICE_ID_w : 0x21 : DATA_HIGH : STOP START : DEVICE_ID_w : 0x22 : DATA_LOW : STOP START : DEVICE_ID_w : 0x23 : ADDRESS_LOW : STOP START : DEVICE_ID_w : 0x24 : WR_STROBE : STOP To read from an indirect register the following I2C transaction should be performed. START : DEVICE_ID_w : 0x23 : ADDRESS_LOW : STOP START : DEVICE_ID_w : 0x24 : RD_STROBE : STOP START : DEVICE_ID_r : 0x21 : data_msb : STOP START : DEVICE_ID_r : 0x22 : data_lsb : STOP Where: DEVICE_ID_w is the selected TVP5154 device ID with the read/write bit (LSB) set to write. DEVICE_ID_r is the selected TVP5154 device ID with the read/write bit (LSB) set to read. ADDRESS_LOW is the low byte of the register address. WR_STROBE is 0x06. RD_STROBE is 0x05. Note, the upper byte of the address is not directly used but is replaced by the corresponding STROBE signal. Each indirect register is 16 bits wide.
9.3.1
Address Default 7 15
DID Control
36Ah 000h 6 Unscaled field 1 DID 14 13 12 11 Scaled field 1 DID 5 4 3 2 10 1 9 0 8
Unscaled field 0 DID Scaled field 0 DID
This register controls the value of the EAV DID bytes for scaled and unscaled data. The value for each field can be independently set allowing identification of both which field is being processed, and whether the data comes from the scaled or unscaled channel.
Internal Control Registers
61
TVP5154 4 Channel Low Power PAL/NTSC/SECAM Video Decoder With Independent Scalers, Fast Lock
SLES163 - MARCH 2006
www.ti.com
9.3.2
Address Default 7 15
Misc Control
36Bh 0Ch 6 Clock rate 14 13 12 11 Scaled blank data 5 4 3 Clock OE 10 9 2 1 Clock edge 8 0
Scaled blank data : When no active scaled data is available this value is output during the active video region. Clock rate : This register controls various clock modes. Since this register is modified by the device during normal operation the clock rate bits should not be modified by the user. Clock OE : This register controls various clock modes. Since this register is modified by the device during normal operation the clock rate bits should not be modified by the user. Clock edge : This register controls various clock modes. Since this register is modified by the device during normal operation the clock rate bits should not be modified by the user.
9.3.3
Address Default 7 15
Interleave field control 1
36Dh 0h 6 14 Field count 5 13 4 12 3 11 Reserved 2 10 Blank timing 1 9 0 8
End pixel count[7:0] End pixel count[9:8]
End pixel count : Pixel count at which the frame status is updated. Do not change this value Blank timing : 0 : No timing signals are generated for blank fields 1 : H, V and F timing generated for blank fields based on unscaled video timing sequences. Field count : Number of output fields in field interleaved sequence.
9.3.4
Address Default 7
Interleave field control 2
36Eh 0h 6 Field mode(3) 15 Field mode(7) 14 13 Field mode(6) 5 Field mode(2) 12 11 Field mode(5) 4 3 Field mode(1) 10 9 Field mode(4) 2 1 Field mode(0) 8 0
9.3.5
Address Default 7
Interleave field control 3
36Fh 0h 6 Field mode(11) 15 Field mode(15) 14 13 Field mode(14) 5 Field mode(10) 12 11 Field mode(13) 4 3 Field mode(9) 10 9 Field mode(12) 2 1 Field mode(8) 8 0
62
Internal Control Registers
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TVP5154 4 Channel Low Power PAL/NTSC/SECAM Video Decoder With Independent Scalers, Fast Lock
SLES163 - MARCH 2006
These registers allow the output data stream to toggle between unscaled and scaled data on a field basis. By setting Field mode[n] appropriately it is possible to use the available output bandwidth to interleave unscaled and scaled frames to achieve reduced frame rates while still maintaining compatibility with legacy data receivers. These registers can also be used to reduce the frame rate of either unscaled data or scaled data by disabling fields within the sequence. A counter automatically moves from Field mode[0] to Field mode[n] where n can be 0 through 15, then returns back to Field mode[0]. Depending on the value of Field mode[n] either unscaled data, scaled data or no data is sent for the current frame. 00 = Unscaled data 01 = Null frame (no SAV/EAV sequence will be generated) 10 = Scaled data 11 = Reserved
9.3.6
Address Default 7 15
Vertical Scaling Field 1 Control
3A8h 0h 6 14 5 13 4 V_Field1[7:0] 12 Reserved 11 10 9 8 V_Field1[8] 3 2 1 0
Vertical scaling initial value in field 1 [8:0]: Initial value of vertical accumulator for field 1 V_Field 1 = (V desired/ V active) x 256
9.3.7
Address Default 7 15
Vertical Scaling Field 2 Control
3A9h 0h 6 14 5 13 4 V_Field2[7:0] 12 Reserved 11 10 9 8 V_Field2[8] 3 2 1 0
Vertical scaling initial value in field 2 [8:0]: Initial value of vertical accumulator for field 2 V_Field 2 = 1.5 x V_Field 1 - 128 If V_Field 2 is negative then add V_Field 1 to V_Field 2 and add V_Field 1 to V_Field 1 until V_Field 2 gets positive
9.3.8
Address Default 7 15
Scaler Output Active Pixels
3ABh 2D0h 6 14 5 13 Reserved 4 12 3 11 2 10 1 9 0 8
SCAL_PIXEL[7:0] SCAL_PIXEL[9:8]
SCAL_PIXEL [9:0]: Scaler active pixel outputs per line
Internal Control Registers
63
TVP5154 4 Channel Low Power PAL/NTSC/SECAM Video Decoder With Independent Scalers, Fast Lock
SLES163 - MARCH 2006
www.ti.com
9.3.9
Address Default 7 15
Vertical Scaling Control
3ACh 2100h 6 14 Reserved 5 13 1 4 12 Enable 3 11 2 10 Reserved 1 9 0 8 VERT_COEF[8]
VERT_COEF[7:0]
Enabled: Enable vertical and horizontal scaler 0 = Disable scaler (default) 1 = Enable scaler VERT_COEF [8:0]: Vertical scaling coefficient. VERT_COEF = (Vdesired/Vactive) x 256
9.3.10
Address Default 7 15
Horizontal Scaling Control
3ADh 400h 6 14 5 13 4 12 3 11 HORZ_COEF[14:8] Horizontal scaling coefficient, MSB 5 bits are integer values and LSB 10 bits are fraction numbers. HORZ_COEF = Hactive / Hdesired 2 10 1 9 0 8
HORZ_COEF[7:0] Reserved HORZ_COEF[14:0]:
10
10.1
Scaler Configuration
Overview
The TVP5154 contains 4 independent scalers, one for each video decoder channel. Each scaler is able to filter and scale both horizontally and vertically to different ratios. Horizontally a 7 tap poly phase filter is used to ensure optimal scaling performance, and can be configured to scale to any output size, below the input resolution, in decrements of 2 pixels. Vertically a running average filter is used to filter vertically and can be configured to scale to any output size below the input resolution. When scaling horizontally the output pixels are packed together to allow continuous reading of the pixels. AVID should be configured such that it qualifies the active pixels, allowing the receiving back end to ignore non active pixels. When scaling vertically, inactive lines are not removed from the output since there is no internal frame memory. The receiving back end must use AVID to qualify active lines/pixels. AVID can be configured to be either active or inactive during invalid output lines. Due to the fact that vertical scaling is performed on a field basis it is possible that the vertical resolution will be reduced due to filtering across lines within the field rather than adjacent lines in the frame. Aliasing will not occur, but the output image will appear soft vertically. If the desired scaling ration is 0.5, then this can be achieved by simply ignoring every other field. This will maintain sharpness, but may introduce aliasing artifacts.
64
Scaler Configuration
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TVP5154 4 Channel Low Power PAL/NTSC/SECAM Video Decoder With Independent Scalers, Fast Lock
SLES163 - MARCH 2006
10.2 10.2.1
Horizontal Scaling Registers
The horizontal scaler uses a 32 phase polymorphic filter. Excellent performance can be achieved by using the set of coefficients programmed into the 5154 for all scaling ratios. It is necessary to program the input and output scaling control registers (3AB and 3AD). Figure 10-1 shows how data is packed horizontally when scaled.
Un-scaled
SAV EAV
Scaled
SAV EAV
Figure 10-1. Unscaled and Scaled Pixel Data Alignment
10.3 10.3.1
Vertical scaling Registers
The vertical scaler implements a weighted running average filter which requires the initial weights and the ratio registers to be configured. Additionally, it is necessary to program the input and output scaling control registers (3A8, 3A9, and 3AC). Figure 10-2 shows the active and inactive data lines when scaled vertically.
Un-scaled Line n Line n+1 Line n+2 Line n+3 Line n+4 Line n+5 Line n+6 Line n+7 SAV SAV SAV SAV SAV SAV SAV SAV Scaled Line n Line n+1 Line n+2 Line n+3 Line n+4 Line n+5 Line n+6 Line n+7 SAV SAV EAV EAV SAV SAV EAV EAV SAV SAV EAV EAV EAV EAV EAV EAV EAV EAV EAV EAV
Figure 10-2. Unscaled and Scaled Vertical Data Formatting
Scaler Configuration 65
TVP5154 4 Channel Low Power PAL/NTSC/SECAM Video Decoder With Independent Scalers, Fast Lock
SLES163 - MARCH 2006
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10.4
Field Interleaving
In systems where either there are insufficient video ports on the back end processor to accommodate both scaled and unscaled video streams, or where the back end processor does not have sufficient processing power to perform compression on the unscaled image at the same time as other video processing such as composting of scaled images for display, it is possible to configure the TVP5154 to output different image types on consecutive fields. In this configuration the field rates for each of the scaled and unscaled images is reduced to accommodate the interleaving of fields, while maintaining a 27MHz pixel clock. This is usefull in video recording systems which require to display a scaled image, but still wish to compress and store full resolution images, albeit at reduced field rates. Field interleaving can generate a sequence of up to 16 fields, where each field can be either unscaled, scaled or blank.
10.4.1
Registers
The field loop count register controls how many fields are in the sequence. The field mode registers control the output field type for each field. The following example shows how to configure field interleaving for a sequence of 5 fields where the first field is unscaled, the second field is scaled, the third field is blank, the fourth field is scaled and the fifth field is blank.
Field 0 Field 1 Field 2 Field 3 Field 4 Field 0 Field 1
Figure 10-3. Field Interleaving Various additional registers exist to configure how the TVP5154 indicates to the back end processor the state of the current field. The Output Control Register 1Fh allows the scaled/unscaled status to be indicated by the upper bit of the SAV/EAV codes. The Output Control Register 1Fh also allows the scaled/unscaled status to be indicated by the DID codes of ancillary data.
66
Scaler Configuration
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TVP5154 4 Channel Low Power PAL/NTSC/SECAM Video Decoder With Independent Scalers, Fast Lock
SLES163 - MARCH 2006
11
11.1
Electrical Specifications
Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
IOVDD to DGND Supply voltage range DVDD to DGND PLL_AVDD to PLL_AGND AVDD to AGND Digital input voltage range, VI to DGND Input voltage range, XIN to PLL_GND Analog input voltage range AI to AGND Digital output voltage range, VO to DGND TA Tstg (1) Operating free-air temperature Storage temperature
VALUE -0.5 to 3.6 - 0.5 to 2.0 -0.5 to 2.0 -0.5 to 2.0 -0.5 to 3.6 -0.5 to 2.0 -0.2 to 2.0 -0.5 to 3.6 0 to 70 -65 to 150
UNIT V V V V V V V V C C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
11.2
IOVDD DVDD
Recommended Operating Conditions
MIN Digital I/O supply voltage Digital supply voltage Analog PLL supply voltage Analog core supply voltage Analog input voltage (ac-coupling necessary) Digital input voltage high Digital input voltage low XIN input voltage high XIN input voltage low High-level output current Low-level output current CLK high-level output current CLK low-level output current Operating free-air temperature 2 -2 4 -4 0 4 -4 8 -8 70 0.7 PLL_AVDD 0.3 PLL_AVDD 3.0 1.65 1.65 1.65 0 0.7 IOVDD 0.3 IOVDD NOM 3.3 1.8 1.8 1.8 MAX 3.6 1.95 1.95 1.95 0.75 UNIT V V V V V V V V V mA mA mA mA C
PLL_AVD D AVDD VI(P-P) VIH VIL VIH_XIN VIL_XIN IOH IOL IOH_CLK IOL_CLK TA
11.3
Crystal Specifications
MIN TYP 14.31818 50 MAX UNIT MHz ppm
Frequency Frequency tolerance
Electrical Specifications
67
TVP5154 4 Channel Low Power PAL/NTSC/SECAM Video Decoder With Independent Scalers, Fast Lock
SLES163 - MARCH 2006
www.ti.com
11.4
Electrical Characteristics
For typical values: Nominal conditions, TA = 25C For minimum/maximum values: Over recommended operating conditions (unless otherwise noted)
PARAMETER DC ELECTRICAL CHARACTERISTICS IDD(IO_D) IDD(D) IDD(A) PTOT Ci VOH VOL VOH_CLK VOL_CLK IIH IIL Zi Ci VI(pp) DG DG DNL INL Fr SNR NS DP DG (1) (2) (3) (4) IO digital supply current at 27 MHz IO digital supply current at 54 MHz Digital supply current Analog core supply current Total power dissipation, normal mode at 27 MHz Total power dissipation, normal mode at 54 MHz Input capacitance
(3)
TEST CONDITIONS (1) Color bar input Color bar input Color bar input Color bar input Color bar input Color bar input Color bar input
(2) (2) (2) (2) (2) (2) (2)
MIN
TYP 46 84 154 20 134 706 832
MAX 52 90 174 29 168 910 1050 10
UNIT mA mA mA mA mA mW mW pF V
IDD(PLL_A) Analog PLL supply current
Output voltage high Output voltage low CLK output voltage high CLK output voltage low High-level input current Low-level input current Input impedance, analog video inputs Input capacitance, analog video inputs Input voltage range (4) Gain control minimum Gain control maximum DC differential nonlinearity DC integral nonlinearity Frequency response Signal-to-noise ratio Noise spectrum (3) Differential phase (3) Differential gain (3)
IOH = 2 mA IOL = -2 mA IOH = 4 mA IOL = -4 mA VI = VIH VI = VIL By design By design Ccoupling = 0.1 F
0.8 IOVDD 0.22 IOVDD 0.8 IOVDD 0.22 IOVDD 22 22 200 0 0 12 500 10 0.75
V V V A A k pF V dB dB
ANALOG PROCESSING AND A/D CONVERTERS -- At FS = 30 MSPS
A/D only A/D only 6 MHz 1 MHz, 0.5 VP-P 50% flat field Modulated ramp Modulated ramp 48 48
0.5 1 -0.9 50 50 1.5 0.5
1 2.5 -3
LSB LSB dB dB dB deg %
Measured with a load of 15 pF. For typical measurements only. By design, not production tested The 0.75-V maximum applies to the sync-chroma amplitude, not sync-white. The recommended termination resistors are 37.4 .
68
Electrical Specifications
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TVP5154 4 Channel Low Power PAL/NTSC/SECAM Video Decoder With Independent Scalers, Fast Lock
SLES163 - MARCH 2006
11.5
Timing Requirements
PARAMETER TEST CONDITIONS (1) MIN TYP 50 13.5 13.5 90% to 10% 10% to 90% 10 25 4 16.5 18.5 4 16.5 18.5 3 3 90% to 10% 10% to 90% 6 6 5 5 MAX UNIT % ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
OUTPUT TIMING Duty cycle SCL t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 (1) CLK high time (at 27 MHz) CLK low time (at 27 MHz) CLK fall time (at 27 MHz) CLK rise time (at 27 MHz) Output hold time Output delay time Output hold time Output delay time Data period Output hold time Output delay time Data period CLK high time (at 54 MHz) CLK low time (at 54 MHz) CLK fall time (at 54 MHz) CLK rise time (at 54 MHz)
Measured with a load of 15 pF for 27MHz signals, 25 pF for 54 MHz signals. By design. Timing not production tested.
Electrical Specifications
69
TVP5154 4 Channel Low Power PAL/NTSC/SECAM Video Decoder With Independent Scalers, Fast Lock
SLES163 - MARCH 2006
t1 Negative edge clock Positive edge clock t3 t4 t2
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Y/C & Syncs
Data 1 t5 t6
Data 2
Figure 11-1. Output Modes 0 and 1. Clocks, Video Data, and Sync Timing
t1 SCLK CLK t3 t4 t2
Y/C & Syncs
Unscaled Data 1 t7 t8
Scaled Data 1
Unscaled Data 2
Scaled Data 2
t9
t9
Figure 11-2. Output Mode 2. Clocks, Video Data and Sync Timing
t13 t14
CLK t15 t16
Y/C & Syncs
Unscaled Data 1 t10 t11
Scaled Data 1
Unscaled Data 2
Scaled Data 2
t12
t12
Figure 11-3. Output Mode 3. Clock, Video and Sync Timing, Positive Edge Clock
70
Electrical Specifications
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TVP5154 4 Channel Low Power PAL/NTSC/SECAM Video Decoder With Independent Scalers, Fast Lock
SLES163 - MARCH 2006
11.6
t1 t2 t3 t4 t5 t6 t7 t8 Cb fI2C
I2C Host Port Timing
PARAMETER Bus free time between STOP and START Setup time for a (repeated) START condition Hold time (repeated) START condition Setup time for a STOP condition Data setup time Data hold time Rise time VC1(SDA) and VC0(SCL) signal Fall time VC1(SDA) and VC0(SCL) signal Capacitive load for each bus line I2C clock frequency Specified by design Specified by design Specified by design TEST CONDITIONS MIN 1.3 0.6 0.6 0.6 100 0 0.9 250 250 400 400 TYP MAX UNIT s s s ns ns s ns ns pF kHz
Electrical Specifications
71
TVP5154 4 Channel Low Power PAL/NTSC/SECAM Video Decoder With Independent Scalers, Fast Lock
SLES163 - MARCH 2006
www.ti.com
Stop Start
Stop
VC1 (SDA)
Data t1 t3 t7 t5 t8 t2 t3 t4
t6
VC0 (SCL)
Figure 11-4. I2C Host Port Timing
12
Schematic
72
Schematic
1
2
3
4
5
6
AVDD C 0.1uF
IOVDD XIN/OSC C 0.1uF C 0.1uF C 0.1uF C 0.1uF C 0.1uF XOUT R 100k Y4 14.31818MHz CL1 CL2 CH1_D0 CH1_D1 CH1_D2 CH1_D3 CH1_D4 CH1_D5 CH1_D6 CH1_D7 IOVDD AVDD REFP1 REFM1 XIN/OSC XOUT PDN /RESET SCL SDA I2CA0 I2CA1 DVDD SCLK1 CLK1 GPCL1/VBLK1 AVID1 HSYNC1 VSYNC1/PALI1 FID1/GLCO1
PLL_VDD C 0.1uF D
DVDD C 0.1uF C 0.1uF C 0.1uF C 0.1uF C 0.1uF RPACK8-33 CH1_OUT0 CH1_OUT1 CH1_OUT2 CH1_OUT3 CH1_OUT4 CH1_OUT5 CH1_OUT6 CH1_OUT7 CH1_OUT[7..0] CH1_OUT[7..0]
CH1_D0 CH1_D1 CH1_D2 CH1_D3 CH1_D4 CH1_D5 CH1_D6 CH1_D7
D
INPUT V DIVIDER NETWORK FOR 0-0.75V INPUT RANGE REMEMBER 75ohm TERMINATION
CL1 = CL2 = 2CL - CSTRAY
SCLK1 CLK1 GPCL1/VBLK1 AVID1 HSYNC1 VSYNC1/PALI1 FID1/GLCO1 RPACK8-33
SCK1 CK1 VB1 AV1 HS1 VS1 FID1
SCK1 CK1 VB1 AV1 HS1 VS1 FID1
PLL_VDD
CH1_A IN
R 37.4 R 37.4
CH1_A
CH1_B IN
R 37.4 R 37.4
CH1_B
U1 AGND AVDD REFP1 REFM1 XIN/OSC XOUT PDN RESETB SCL SDA I2CA0 I2CA1 DGND DVDD IOVDD IOGND CH1OUT0 CH1OUT1 CH1OUT2 CH1OUT3 CH1OUT4 CH1OUT5 CH1OUT6 CH1OUT7 SCLK1 CLK1 INT1/GPCL1/VBLK1 AVID1 HSYNC1 DGND DVDD IODVDD CH2_D0 CH2_D1 CH2_D2 CH2_D3 CH2_D4 CH2_D5 CH2_D6 CH2_D7
128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97
CH1_A CH1_B CH2_A IN R 37.4 C R 37.4 CH2_A CH2_B IN R 37.4 R 37.4 CH2_A CH2_B CH3_A IN R 37.4 R 37.4 CH3_A CH3_B IN R 37.4 R 37.4 CH3_A CH3_B CH4_A IN R 37.4 R 37.4 CH4_A CH4_B IN R 37.4 R 37.4 CH4_A CH4_B CH4_B CH3_B CH2_B
C C
0.1uF 0.1uF
REFM2 REFP2
C C
0.1uF 0.1uF
REFM3 REFP3 C C 0.1uF 0.1uF
REFM4 REFP4
C C
0.1uF 0.1uF
PLL_VDD PLL_GND AGND TMS FID4/GLCO4 VSYNC4/PALI4 HSYNC4 AVID4 INT4/GPCL4/VBLK4 CLK4 SCLK4 IOGND IOVDD DVDD DGND CH4OUT7 CH4OUT6 CH4OUT5 CH4OUT4 CH4OUT3 CH4OUT2 CH4OUT1 CH4OUT0 FID3/GLCO3 VSYNC3/PALI3 HSYNC3 AVID3 INT4/GPCL4/VBLK4 CLK3 SCLK3 IOGND IOVDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
AI1GND AI1A AI1B PLL_VDD PLL_GND REFM2 REFP2 AVDD AGND AI2GND AI2A AI2B PLL_VDD PLL_GND AVDD AGND REFM3 REFP3 AVDD AGND AI3GND AI3A AI3B PLL_VDD PLL_GND REFM4 REFP4 AVDD AGND AI4GND AI4A AI4B
IOGND VSYNC1/PALI1 FID1/GLCO1 CH2OUT0 CH2OUT1 CH2OUT2 CH2OUT3 CH2OUT4 CH2OUT5 CH2OUT6 CH2OUT7 SCLK2 CLK2 INT2/GPCL2/VBLK2 DGND DVDD IOVDD IOGND AVID2 HSYNC2 VSYNC2/PALI2 FID2/GLCO2 CH3OUT0 CH3OUT1 CH3OUT2 CH3OUT3 CH3OUT4 CH3OUT5 CH3OUT6 CH3OUT7 DGND DVDD
96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
CH2_D0 CH2_D1 CH2_D2 CH2_D3 CH2_D4 CH2_D5 CH2_D6 CH2_D7 SCLK2 CLK2 GPCL2/VBLK2
RPACK8-33 CH2_OUT0 CH2_OUT1 CH2_OUT2 CH2_OUT3 CH2_OUT4 CH2_OUT5 CH2_OUT6 CH2_OUT7 CH2_OUT[7..0] CH2_OUT[7..0]
SCLK2 CLK2 GPCL2/VBLK2 AVID2 HSYNC2 VSYNC2/PALI2 FID2/GLCO2 RPACK8-33
SCK2 CK2 VB2 AV2 HS2 VS2 FID2
SCK2 CK2 VB2 AV2 HS2 VS2 FID2
C
AVID2 HSYNC2 VSYNC2/PALI2 FID2/GLCO2 CH3_D0 CH3_D1 CH3_D2 CH3_D3 CH3_D4 CH3_D5 CH3_D6 CH3_D7 CH3_D0 CH3_D1 CH3_D2 CH3_D3 CH3_D4 CH3_D5 CH3_D6 CH3_D7
RPACK8-33 CH3_OUT0 CH3_OUT1 CH3_OUT2 CH3_OUT3 CH3_OUT4 CH3_OUT5 CH3_OUT6 CH3_OUT7 CH3_OUT[7..0] CH3_OUT[7..0]
TVP5154PNP 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
SCLK3 CLK3 GPCL3/VBLK3 AVID3 HSYNC3 VSYNC3/PALI3 FID3/GLCO3 SCLK3 CLK3 GPCL3/VBLK3 AVID3 HSYNC3 VSYNC3/PALI3 FID3/GLCO3 CH4_D0 CH4_D1 CH4_D2 CH4_D3 CH4_D4 CH4_D5 CH4_D6 CH4_D7 SCLK4 CLK4 GPCL4/VBLK4 AVID4 HSYNC4 VSYNC4/PALI4 FID4/GLCO4 RPACK8-33
SCK3 CK3 VB3 AV3 HS3 VS3 FID3
SCK3 CK3 VB3 AV3 HS3 VS3 FID3
B
TMS
B RPACK8-33 CH4_OUT0 CH4_OUT1 CH4_OUT2 CH4_OUT3 CH4_OUT4 CH4_OUT5 CH4_OUT6 CH4_OUT7 CH4_OUT[7..0] CH4_OUT[7..0]
I2C ADDRESS SELECTION
2-3 Base Addr 0xB8 - Default
CH4_D0 CH4_D1 CH4_D2 CH4_D3 CH4_D4 CH4_D5 CH4_D6 CH4_D7
IOVDD R 10k 1
IOVDD R 10k
IOVDD R 100 TMS R 10k
I2CA0
2
I2CA1
2
SCLK4 CLK4 GPCL4/VBLK4 AVID4 HSYNC4 VSYNC4/PALI4 FID4/GLCO4 RPACK8-33
SCK4 CK4 VB4 AV4 HS4 VS4 FID4
SCK4 CK4 VB4 AV4 HS4 VS4 FID4
3
R 10k
R 10k
3
1
SDA SCL C 1uF C REFM1 REFM2 A 1uF C 1uF C 1uF C REFM3 1uF C 1uF C 1uF C REFM4 1uF C 1uF C 1uF C 1uF TEXAS INSTRUMENTS, INC. 12500 TI BLVD DALLAS, TEXAS 75243 C 1uF /RESET
SDA SCL /RESET
REFP1
REFP2
REFP3
REFP4
A
TVP5154
Size C Scale
FCSM No.
DWG No.
Rev 1 Sheet 2 of 17
1
2
3
4
5
6
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