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TSC8x251G2D
Specification Update
1. Revision History
Date of revision August 23, 1999 Version Rev. A Creation Description
World Wide Web:http://www.temic-semi.de/ Product Hotline:C251@temic.fr Tools Hotline:x51_tools@temic.fr
2. Preface
This document is an update to the specifications contained in Table 1. Table 1. Affected Documents/Related Documents
Title TSC8x251G2D Datasheet TSC80251G1D Design Guide - October 1998 TSC80251 Programmer's Guide 1996 Reference Rev. A - May 7, 1999 Rev. C - October 8, 1998 Rev. B - October 23, 1996
3. Nomenclature
Errata are design defects or errors. These may cause the published (component, board, system) behavior to deviate from published specifications. Hardware and software designed to be used with any component, board, and system must consider all errata documented. Specification Changes are modifications to the current published specifications. These changes will be incorporated in any new release of the specification. Specification Clarifications describe a specification in greater detail or further highlight a specification's impact to a complex design situation. These clarifications will be incorporated in any new release of the specification. Documentation Changes include typos errors, or omissions from the current published specifications. These changes will be incorporated in any new release of the specifications (see Table 1).
Table 2. Codes Used in Summary Table
Page (Page) Page location of item in this document. Status Doc Fix No Fix Eval Document change or update will be implemented. This erratum is intended to be fixed in a future version of the component. There are no plans to fix this erratum. Plans to fix this erratum are under evaluation.
Rev. A - August 23, 1999
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TSC8x251G2D
4. Summary Tables of Changes
The following tables indicate the errata, specification changes, specification clarifications, or documentation changes which apply to TSC8x251G2D derivatives. TEMIC may fix some of the errata in a future version of the component, and account for the other outstanding issues through documentation or specification changes as noted.
Table 3. Errata List
TEMIC Reference C251G2D-01 C251G2D-02 C251G2D-03 Mask Number 5142A 5142A 5142A Page 3 3 4 Status Eval Eval Eval Errata Power Down Mode Current out of Specification in Romless Mode Power-Fail Threshold out of Specification I2C Data Transmission in Slave Transmitter Mode
Table 4. Specification Changes
TEMIC Reference Mask Number Page Status None
Specification Changes
Table 5. Specification Clarifications
TEMIC Reference Mask Number Page Status None Specification Clarifications
Table 6. Documentation Changes
TEMIC Reference Mask Number Page Status None Documentation Changes
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Rev. A - August 23, 1999
TSC8x251G2D
5. Errata
Reference C251G2D-01 Problem
IPD is out of specification when EA# pin is tied to a low level.
Erratum Power Down Mode Current out of Specification in Romless Mode
Implication
The ROMless products and EPROM and ROM products used as ROMless (EA#=0) are consuming extra current in Power Down mode. Table 7 shows the Power Down current maximum value and specification for High Speed and Low Voltage versions. Table 7. DC Characteristics; TA= -40 to +85C
Symbol
IPD IPD
Parameter
Power-Down Current Power-Down Current
Max Spec
20 10
Max Value
35 20
Units
A A
Test Conditions
VRET < VDD < 5.5 V VRET < VDD < 3.6 V
Workaround
No workaround is proposed.
Affected Products
All TSC8x251G2D are affected.
Reference C251G2D-02 Problem
Erratum Power-Fail Threshold out of Specification
The tolerance on the power fail reset voltage thresholds is out of specification.
Implication
The device may never exit reset at power-up when power fail reset is enabled.
Workaround
Some devices may need a higher voltage to exit reset. Then RSTD bit has to be set in POWM register to disable the Power-Fail Reset detector before the voltage is reduced.
Affected Products
This feature has been removed from ROMless, Mask ROM and OTP devices which are then not affected. All TSC87251G2D EPROM devices are affected.
Rev. A - August 23, 1999
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TSC8x251G2D
Reference C251G2D-03 Problem
When in slave transmitter mode, if the slave transmits a data starting with a low level on the bus (MSB is logic 0), data set-up time is not respected and leads to a bus error.
Erratum I2C Data Transmission in Slave Transmitter Mode
Implication
When this errata appears, a START condition is delivered on the bus during the transfer leading to a bus error (state 00). The transfer is then interrupted and slave does not continue to transmit the data to the master.
Workaround
The workaround proposed consist in removing the set-up violation by stretching the SDA line (P1.7) when the MSB of the data to transmit is logic 0. This workaround must be implemented in states A8h, B0h, and B8h when a data is written to the serial data register (SSDAT). In assembler the workaround is:
mov mov jb clr mov setb A,data SSDAT,A ACC.7,Msb_tst SDA SSCON,#40h SDA ; read data to transmit ; load transmit buffer ; test MSB ; stretch data line (P1.7) to low level ; or 44h: clear SSI flag ; data line is now driven by controller
Msb_tst:
In C language, the workaround becomes:
SSDAT = data; if (!(data & 0x80)) { SDA = 0; } SSCON = 0x40; SDA = 1; // load transmit buffer // test MSB // stretch data line (P1.7) to low level // or 0x44: clear SSI flag // data line is now driven by controller
Affected Products
All TSC8x251G2D are affected.
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Rev. A - August 23, 1999
TSC8x251G2D
6. Specification Changes
This section is intentionally left blank.
7. Specification Clarifications
This section is intentionally left blank.
8. Documentation Changes
This section is intentionally left blank.
Rev. A - August 23, 1999
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