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| TSB17BA1 IEEE STD 1394b SINGLE-PORT CABLE TRANSCEIVER SLLS568A - JUNE 2003 D Fully Supports Provisions of IEEE Std D 1394b-2002 at S100B Signaling Rates Provides One Transceiver to Drive IEEE Std 1394b Signaling Across Unshielded Twisted Pair Category 5 (UTP5 or CAT5) Cable or Better at 100 Megabits per Second (Mbits/s) Power-Down Features to Conserve Energy in Battery Powered Applications D Single 3.3-V Supply Operation or Optional Dual 3.3-V/1.8-V Supply Operation D Low-Cost High-Performance 24-Terminal D TSSOP Package Low-Power Modes to Put Device Into Low Power States When Data Is Not Being Driven D description The TSB17BA1 is a single-port 100-Mbps transceiver used in transporting IEEE Std 1394b (1394b) or other coded data across CAT5 or better cabling. It is attached to a 1394b-capable port on a 1394b physical layer (PHY) to enable 1394b 100-Mbps signals to be transmitted and received across up to 100 meters of unshielded twisted-pair category 5 (UTP5) cable. Equalization is applied to the signal received from the UTP5 cable to boost signal-to-noise ratio (SNR) to allow sensing of the data. A 1394b PHY device capable of transmitting at only 100 Mbits/s in 1394b-only mode is required for correct functionality. This PHY must be connected to the TSB17BA1 at one of the twisted-pair (TP) ports, with the 110- 1394b transmission line properly terminated. The TSB17BA1 must then be connected to a 100- transmission line properly terminated and connected to an isolating transformer. This transformer is then connected to an RJ45 connector. All of the parameters on the UTP5 side of the TSB17BA1 are set the same as 100baseT Ethernet. This allows the mechanical and magnetic infrastructure, which is used to design a 100baseT connection, to be used when designing a 100-Mbits/s UTP5 1394b connection. This device does not implement the autocrossover functionality described in chapter 12 of IEEE Std 1394b-2002. This means the required crossover of TPA to TPB and TPB to TPA must be done in the cable or connector or PWB; in other words, a mechanical crossover must be implemented (see the Application Information section). terminal assignments PW PACKAGE (TOP VIEW) E_OUT E_INN E_INP VSS33 BETA_OUTP BETA_OUTN VDD33 BETA_INP BETA_INN PD_SE TEST0 TEST1 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VREG_PD VCONTROL R1 R0 UTP5_INP UTP5_INN VDDCORE UTP5_OUTP UTP5_OUTN VSSCORE TEST3 TEST2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Implements technology covered by one or more patents of Apple Computer, Inc. and SGS Thompson, Limited. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 2003, Texas Instruments Incorporated POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 TSB17BA1 IEEE STD 1394b SINGLE-PORT CABLE TRANSCEIVER SLLS568A - JUNE 2003 functional block diagram 1394b Driver UTP5_INx Equalizer BETA_OUTx UTP5 Cable Side UTP5 Driver UTP5_OUTx Comparator AC Coupling 1394b PHY Side BETA_INx Power-Up Control Voltage Regulator equalizer The equalizer applies equalization to the signal received from the UTP5 cable to boost SNR to allow sensing of the data. 1394b driver This block drives the signal detected and enhanced by the equalizer from the UTP cable to a 1394b PHY port. ac coupling This block blocks direct current signals to the comparator. Only ac signals are propagated through this block. comparator This block converts 1394b signals from the 1394b PHY into levels capable of driving the UTP5 driver. UTP5 driver This block drives signals onto the UTP5 cable. power-up control This block provides a signal for the control of the device relative to the state of the supply voltage. voltage regulator This block regulates an externally provided 3-3.6 V down to an internally used 1.8 V. 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TSB17BA1 IEEE STD 1394b SINGLE-PORT CABLE TRANSCEIVER SLLS568A - JUNE 2003 Terminal Functions TERMINAL NAME Test Terminals E_INN E_INP E_OUT TEST0 TEST1 TEST2 TEST3 Test Test Test 2 3 1 11 12 13 14 I I O Input reserved for future enhancement. Must be grounded for normal operation. Input reserved for future enhancement. Must be grounded for normal operation. Output reserved for future enhancement. May be left unconnected for normal operation. Test control. These inputs are used in the manufacturing test of the TSB17BA1. For normal use, these terminals must be pulled low to GND. TYPE NO. I/O DESCRIPTION CMOS I IEEE Std 1394b PHY Terminals Input of ac-coupling block. These twisted-pair differential-signal terminals connect the TSB17BA1 BETA_INP to the 1394b PHY TPB+ and BETA_INN to the 1394b PHY TPB- terminals of the port on the 1394b PHY. Board traces from each pair of positive and negative differential signal terminals must be kept matched and as short as possible to the external load resistors and to the 1394b PHY. The transmission lines between the 1394b PHY and TSB17BA1 must be terminated properly. Output of 1394b driver block. These twisted-pair differential-signal terminals, connect the TSB17BA1 BETA_OUTP to the 1394b PHY TPA+ and BETA_OUTN to the 1394b PHY TPA- terminals of the port on the 1394b PHY. Board traces from each pair of positive and negative differential signal terminals must be kept matched and as short as possible to the external load resistors and to the 1394b PHY. The transmission lines between the 1394b PHY and TSB17BA1 must be terminated properly. BETA_INP BETA_INN Input from 1394b PHY 8 9 I BETA_OUTP BETA_OUTN Output to 1394b PHY 5 6 O RJ45 Terminals UTP5_INN Input from UTP5 Cable Input from UTP5 Cable Output to UTP5 Cable Output to UTP5 Cable CMOS Bias 19 I Negative differential side of input from the UTP5 cable to the TSB17BA1 termination network. Connect to network corresponding to RJ45 pin number 6 or RJ45 pin number 8. Positive differential side of input from the UTP5 cable to the TSB17BA1 termination network. Connect to network corresponding to RJ45 pin number 3 or RJ45 pin number 7. Negative differential side of output from TSB17BA1 to the UTP5 cable termination network. Connect to network corresponding to RJ45 pin number 2. Positive differential side of output from TSB17BA1 to the UTP5 cable termination network. Connect to network corresponding to RJ45 pin number 1. UTP5_INP 20 I UTP5_OUTN 16 O UTP5_OUTP 17 O Power and Ground Terminals PD_SE R0 10 21 I/O - Global power down. A high on this terminal turns off all internal circuitry. Current setting resistor. This terminal is connected to a precision external resistance to set the internal operating currents and the cable-driver output currents. This terminal has a very low impedance to ground. Current setting resistor (band-gap sense voltage). This terminal is connected to a precision external resistance to set the internal operating currents and the cable-driver output currents. A resistance of 6.04 k, 1% between R0 and R1, is required to meet the 1394b output-voltage limits. Voltage control (reserved). Nominally not connected. Power down for voltage regulator. When driven low, the device uses an internal regulator to generate the required 1.8 V. When driven high, the internal regulator is powered down and the 1.8 V must be supplied externally to power the 1.8-V circuitry of the device. Nominally tied low to enable the internal regulator. R1 Bias 22 I VCONTROL 23 I/O VREG_PD CMOS 24 I POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 TSB17BA1 IEEE STD 1394b SINGLE-PORT CABLE TRANSCEIVER SLLS568A - JUNE 2003 Terminal Functions (Continued) TERMINAL NAME TYPE NO. I/O DESCRIPTION Power and Ground Terminals (Continued) VDDCORE Supply 18 - Core power. Internal core circuit power terminal. Must be decoupled with a 1-F capacitor in parallel with other smaller capacitors, such as 0.001-F capacitors. 3.3-V power. I/O 3.3-V circuit power terminals. A combination of high-frequency decoupling capacitors near each terminal are suggested, such as paralleled 0.1 F and 0.001 F. Lower frequency 10-F filtering capacitors are also recommended. Core ground. Tie to the ground plane of the PWB as close as possible to the terminal. 3.3-V ground. Tie to the ground plane of the printed wiring board (PWB) as close as possible to the terminal. VDD33 VSSCORE VSS33 Supply Supply Supply 7 15 4 - - - 4 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TSB17BA1 IEEE STD 1394b SINGLE-PORT CABLE TRANSCEIVER SLLS568A - JUNE 2003 absolute maximum ratings over operating free-air temperature (unless otherwise noted) Supply voltage range, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 4 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VDD + 0.5 V Output voltage range at any output, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VDD + 0.5 V Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values, except differential I/O bus voltages, are with respect to network ground. DISSIPATION RATING TABLE PACKAGE TA 25C POWER RATING DERATING FACTOR ABOVE TA = 25C TA = 70C POWER RATING 0.44 W PW 0.93 W 10.9 mW/C This is the inverse of the traditional junction-to-ambient thermal resistance (RJA). 2-oz trace and copper pad with solder. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 TSB17BA1 IEEE STD 1394b SINGLE-PORT CABLE TRANSCEIVER SLLS568A - JUNE 2003 recommended operating conditions MIN Supply voltage, VDD33 Supply voltage, VDDCORE High-level input voltage, VIH Low-level input voltage, VIL Maximum junction temperature, TJ (see RJA values listed in thermal characteristics table) 1394b Differential input voltage, VID 1394b Common-mode input voltage, VIC Receive input jitter Receive input skew TEST[0:3], PD_SE, VREG_PD TEST[0:3], PD_SE, VREG_PD RJA = 91.47C/W, TA = 70C, high-K board RJA = 150.70_C/W, TA = 70C, low-K board BETA_INP-BETA_INN BETA_IN cable inputs, nonsource power node BETA_INP, BETA_INN cable inputs, S100 operation Between BETA_OUT and BETA_IN cable inputs, S100 operation 200 0.4706 3 1.65 0.7xVDD 0.3xVDD 86.5 97.1 800 2.015 1.08 0.8 TYP 3.3 1.8 MAX 3.6 1.95 UNIT V V V V C mV V ns ns All typical values are at VDD = 3.3 V and TA = 25C. 6 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TSB17BA1 IEEE STD 1394b SINGLE-PORT CABLE TRANSCEIVER SLLS568A - JUNE 2003 electrical characteristics over recommended ranges of operating conditions (unless otherwise noted) driver PARAMETER VOD VOD IBETA IUTP5 Differential output voltage (BETA) Differential output voltage (UTP5) Beta drive current, BETA_OUTP, BETA_OUTN UTP5 drive current, UTP5_OUTP, UTP5_OUTN Drivers enabled Drivers enabled TEST CONDITIONS TYP 705 500 12.5 10 UNIT mV mV mA mA receiver PARAMETER ZID ZIC VTH-R Differential impedance Common-mode Common mode impedance Receiver input threshold voltage TEST CONDITIONS Drivers disabled 20 Drivers disabled Drivers disabled -30 24 30 MIN 4 TYP 7 4 MAX UNIT k pF k pF mV device PARAMETER 3.3-V supply current IDDSTATIC VDDCORE supply current 3.3-V supply current 3.3-V supply current VDDCORE supply current 3.3-V supply current TEST CONDITIONS TYP 4 No signals to driver in uts inputs 4 7.5 6 Normal o eration operation 30 50 mA mA UNIT IDDDYN Measured with internal regulator off, 1.8-V supply current from external source Measured with internal regulator on thermal characteristics PARAMETER RJA RJC RJA RJC Junction-to-free-air thermal resistance Junction-to-case-thermal resistance Junction-to-free-air thermal resistance Junction-to-case-thermal resistance TEST CONDITIONS Board mounted, no air flow, high conductivity TI-recommended test board, board chip soldered or greased to thermal land with 2 oz copper (high K 2-oz (high-K board) Board mounted, no air flow, high conductivity JEDEC test board with 1 oz 1-oz copper (low-K board) TYP 91.5 41.2 150.7 41.2 UNIT C/W C/W C/W C/W POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 7 TSB17BA1 IEEE STD 1394b SINGLE-PORT CABLE TRANSCEIVER SLLS568A - JUNE 2003 electrical characteristics over recommended ranges of operating conditions (unless otherwise noted) (continued) switching characteristics PARAMETER Jitter, transmit Skew, Skew transmit tr tf tr tf TP differential rise time, transmit TP differential fall time, transmit UTP differential rise time, transmit UTP differential fall time, transmit TEST CONDITIONS Between BETA_OUT and BETA_IN Between BETA_OUT and BETA_IN Between UTP5_OUT and UTP5_IN 10% to 90% 90% to 10% 10% to 90%, at RJ45 connector 90% to 10%, at RJ45 connector 0.65 0.65 3.5 3.5 MIN TYP 2 0.10 0.20 ns ns ns ns ns MAX UNIT ns PARAMETER MEASUREMENT INFORMATION BETA_OUTP 56 BETA_OUTN Figure 1. Test Load for Beta Connection UTP5_OUTP 50 UTP5_OUTN Figure 2. Test Load for UTP5 Connection 8 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TSB17BA1 IEEE STD 1394b SINGLE-PORT CABLE TRANSCEIVER SLLS568A - JUNE 2003 APPLICATION INFORMATION Termination and Transformer RJ45 UTP Cable Termination 1394 Link 1394b PHY TSB17BA1 Figure 3. 1394b Cable Termination signal coding The signaling generated from a 1394b PHY is 8B/10B encoded. This means to send 8 bits of data requires the transmission of 10 bits across the cable. The maximum frequency that is required to send 100 Mbits/s is a fundamental frequency of 62.5 MHz (see the IEEE Std 1394b-2002 for more explanation). connector pins The current IEEE Std 1394b-2002 requires that the connection from 1394b PHY signal to the RJ45 connector pin be: D D D D TPB+ to RJ45 pin 1 TPB- to RJ45 pin 2 TPA+ to RJ45 pin 7 TPA- to RJ45 pin 8 There is a proposal to change the IEEE Std 1394b-2002 connection from 1394b PHY signal to the RJ45 connector pin to be the same as the 100baseT Ethernet. This allows use of more 100baseT Ethernet components for 1394b connections. This changes the connections to: D D D D TPB+ to RJ45 pin 1 TPB- to RJ45 pin 2 TPA+ to RJ45 pin 3 TPA- to RJ45 pin 6 It is anticipated that the change will be implemented into IEEE Std 1394b-2002, though it has not been ratified. Therefore, it is recommended that all implementations utilize the new pinout running TPA+ to pin 3 and TPA- to pin 6. If a closed system is created, meaning the designer controls the electronics at both ends of the UTP5 cable, then using pins 7 and 8 can give as much as a 12-dB reduction in crosstalk rather than using pins 3 and 6. Please contact Texas Instruments for further details. cable connection The IEEE Std 1394b-2002 requires the output of a TPB port to be connected to the input of a TPA port when connecting one device to a second device. In other words, it requires a crossover somewhere between the two PHY ports. The 1394b standard further states that a UTP5 device incorporates logic that can automatically implement this crossover in the logic. The TSB17BA1 does not contain this logic, therefore, the crossover must be implemented external to the TSB17BA1. It is recommended for users of the TSB17BA1 to: D Design the UTP5 connection to pins 1, 2 and 3, 6 as previously detailed. D Ship an Ethernet crossover cable with their devices. The crossover cable connects: D D D D Pin 1 on the near end of the cable to pin 3 on the far end of the cable Pin 2 on the near end of the cable to pin 6 on the far end of the cable Pin 3 on the near end of the cable to pin 1 on the far end of the cable Pin 6 on the near end of the cable to pin 2 on the far end of the cable, thereby implementing the crossover. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 9 TSB17BA1 IEEE STD 1394b SINGLE-PORT CABLE TRANSCEIVER SLLS568A - JUNE 2003 APPLICATION INFORMATION cable connection (continued) This also works for CAT5-structured wiring cable that is typically installed in a home or office. The CAT5 cables in these structured wiring installations are wired straight through and do not crossover. It is recommended that the structured wiring hub at the center of the star-type installation contain only straight-through wiring. If the RJ45 connector is brought outside the wall, then it also is connected straight through. If all networkable devices are also created as straight-through connections, then the required crossover is implemented when the networkable device is connected to the RJ45 wall-plate connection using a crossover cable. There is a special case for the structured wiring if the wall plate enables a 4-pin, 6-pin, or 9-pin 1394b connector. In this case, one port of the 1394b PHY is connected to the 1394b connector in the typical manner. However, the connection between the 1394b PHY and the UTP5 connection inside the wall must implement a crossover. This is true if the 1394b-structured wiring hub is wired straight through and the cable pulled is straight through. In this case, since all the electrical connections between the two 1394b ports are straight through, the crossover must be implemented on the wall-plate UTP5 connection. It is required that this crossover be completed between the RJ45 connector on the wall plate and the isolating transformer of the termination network. Please contact Texas Instruments for further detail. PCB layout considerations There are certain signals that require special care in the layout of the TSB17BA1. The UTP5_INP and UTP5_INN signals are the inputs from what might be a 100-m cable. After propagating through a cable this long the signal amplitudes could be small and more easily affected by board noise. The routing for these signals from the RJ45 connector through the termination network to the PHY must be short and, if possible, a ground guard etch must be implemented to protect them from board noise. This etch must extend the length of the traces, be far enough away from the signal traces not to significantly affect the trace impedance, and be connected to the ground plane every 2 cm or less. The precision resistor between the R1 and R0 terminals sets the internal currents and voltages of the TSB17BA1. Any noise that couples onto the R1 terminal can affect the entire device. Therefore, this connection must be kept short and as close to the TSB17BA1 as possible. This connection can also benefit from a ground guard etch around the R1 and R0 terminal connections. To keep the noise introduced to these signals to a minimum it is recommended that no digital signals or large amplitude analog signals (like switching regulators) be routed in the vicinity of terminals 19-22 on the TSB17BA1. The output signals of the TSB17BA1 (UTP5_OUTP, UTP5_OUTN, BETA_OUTP, and BETA_OUTN) must also be routed away from these sensitive input pins. 10 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1.3V Receive R40 49.9 C45 0.001 F HB726 8 7 1CT:1CT 9 10 6 11 TPB+ TPB- R31 1 M R36 1 M R39 49.9 T2 5 12 4 13 1 2 3 4 5 6 7 8 RJ45 C17 270 pF C20 270 pF Figure 4. Example Schematic Implementation L2 15 nH 1:1 UTPL_TPB2+ R38 49.9 C41 56 pF VCONTROL_U4 R86 6.04 k C46 0.001 F 3 2 1 T1 POST OFFICE BOX 655303 TSB17BA1 SSOP R59 56.2 R73 56.2 R74 56.2 R37 49.9 TPA2+ TPA2- VDD3.3V_U4 TPB2+ TPB2- UTP_TPA2+ UTP_TPA2- VDD1.8V_U4 UTP_TPB2+ UTP_TPB2- R28 1.2k C42 56 pF L1 15 nH UTPL_TPB2- R61 56.2 R87 56.2 R88 56.2 1 2 3 4 5 6 7 8 9 10 11 12 E_OUT VREG_PD E_INN VCONTROL E_INP R1 VSS33 R0 BETA_OUTP UTP5_INP BETA_OUTN UTP5_INN VDD33 VDD18 BETA_INP UTP5_OUTP BETA_INN UTP5_OUTN PD_SE VSS18 TEST0 TEST3 TEST1 TEST2 U4 24 23 22 21 20 19 18 17 16 15 14 13 R85 75 C107 0.001 F R57 1 M C126 270 pF R35 5.11 k 14 15 16 75 R58 56.2 Transformer Transmit 75 75 TSB17BA1 IEEE STD 1394b SINGLE-PORT CABLE TRANSCEIVER * DALLAS, TEXAS 75265 Receive 2/B2 2/B2 TPA2+ TPA2- Transmit 2/B2 2/B2 TPB2+ TPB2+ 75 R60 56.2 R53 75 C33 0.001 F R30 75 C127 0.001 F C68 0.01 F C16 270 pF VDD1.8V_U4 7/A3 SLLS568A - JUNE 2003 7/D3 VDD3.3V_U4 11 TSB17BA1 IEEE STD 1394b SINGLE-PORT CABLE TRANSCEIVER SLLS568A - JUNE 2003 MECHANICAL DATA PW (R-PDSO-G**) 14 PINS SHOWN PLASTIC SMALL-OUTLINE PACKAGE 0,65 14 8 0,30 0,19 0,10 M 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 A 7 0- 8 0,75 0,50 Seating Plane 1,20 MAX 0,15 0,05 0,10 PINS ** DIM A MAX 8 14 16 20 24 28 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 12 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MECHANICAL DATA MTSS001C - JANUARY 1995 - REVISED FEBRUARY 1999 PW (R-PDSO-G**) 14 PINS SHOWN PLASTIC SMALL-OUTLINE PACKAGE 0,65 14 8 0,30 0,19 0,10 M 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 A 7 0- 8 0,75 0,50 Seating Plane 1,20 MAX 0,15 0,05 0,10 PINS ** DIM A MAX 8 14 16 20 24 28 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. 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