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| TSB12LV26 EP OHCI Lynxt PCI Based IEEE 1394 Host Controller Data Manual JANUARY 2003 1394 Host Controller Solutions SGLS138A IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2003, Texas Instruments Incorporated Contents Section 1 Title Page 1-1 1-1 1-1 1-2 1-2 1-2 2-1 3-1 3-3 3-3 3-4 3-4 3-5 3-6 3-6 3-7 3-7 3-8 3-8 3-9 3-9 3-10 3-10 3-11 3-12 3-13 3-14 3-15 3-16 3-17 3-18 4-1 4-4 4-5 4-6 4-6 4-7 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Terminal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TSB12LV26 Controller Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 Class Code and Revision ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7 Latency Timer and Class Cache Line Size Register . . . . . . . . . . . . . . 3.8 Header Type and BIST Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9 OHCI Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.10 TI Extension Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.11 Subsystem Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.12 Power Management Capabilities Pointer Register . . . . . . . . . . . . . . . 3.13 Interrupt Line and Pin Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.14 MIN_GNT and MAX_LAT Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.15 OHCI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.16 Capability ID and Next Item Pointer Register . . . . . . . . . . . . . . . . . . . . 3.17 Power Management Capabilities Register . . . . . . . . . . . . . . . . . . . . . . 3.18 Power Management Control and Status Register . . . . . . . . . . . . . . . . 3.19 Power Management Extension Register . . . . . . . . . . . . . . . . . . . . . . . . 3.20 Miscellaneous Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . 3.21 Link Enhancement Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.22 Subsystem Access Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.23 GPIO Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OHCI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 OHCI Version Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 GUID ROM Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 Asynchronous Transmit Retries Register . . . . . . . . . . . . . . . . . . . . . . . 4.4 CSR Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5 CSR Compare Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 4 iii 5 6 7 4.6 CSR Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7 Configuration ROM Header Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.8 Bus Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.9 Bus Options Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.10 GUID High Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.11 GUID Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.12 Configuration ROM Mapping Register . . . . . . . . . . . . . . . . . . . . . . . . . . 4.13 Posted Write Address Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.14 Posted Write Address High Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.15 Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.16 Host Controller Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.17 Self-ID Buffer Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.18 Self-ID Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.19 Isochronous Receive Channel Mask High Register . . . . . . . . . . . . . . 4.20 Isochronous Receive Channel Mask Low Register . . . . . . . . . . . . . . . 4.21 Interrupt Event Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.22 Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.23 Isochronous Transmit Interrupt Event Register . . . . . . . . . . . . . . . . . . 4.24 Isochronous Transmit Interrupt Mask Register . . . . . . . . . . . . . . . . . . . 4.25 Isochronous Receive Interrupt Event Register . . . . . . . . . . . . . . . . . . . 4.26 Isochronous Receive Interrupt Mask Register . . . . . . . . . . . . . . . . . . . 4.27 Fairness Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.28 Link Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.29 Node Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.30 PHY Layer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.31 Isochronous Cycle Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.32 Asynchronous Request Filter High Register . . . . . . . . . . . . . . . . . . . . . 4.33 Asynchronous Request Filter Low Register . . . . . . . . . . . . . . . . . . . . . 4.34 Physical Request Filter High Register . . . . . . . . . . . . . . . . . . . . . . . . . . 4.35 Physical Request Filter Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . 4.36 Physical Upper Bound Register (Optional Register) . . . . . . . . . . . . . . 4.37 Asynchronous Context Control Register . . . . . . . . . . . . . . . . . . . . . . . . 4.38 Asynchronous Context Command Pointer Register . . . . . . . . . . . . . . 4.39 Isochronous Transmit Context Control Register . . . . . . . . . . . . . . . . . . 4.40 Isochronous Transmit Context Command Pointer Register . . . . . . . . 4.41 Isochronous Receive Context Control Register . . . . . . . . . . . . . . . . . . 4.42 Isochronous Receive Context Command Pointer Register . . . . . . . . 4.43 Isochronous Receive Context Match Register . . . . . . . . . . . . . . . . . . . GPIO Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial ROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1 Absolute Maximum Ratings Over Operating Temperature Ranges . 7.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3 Electrical Characteristics Over Recommended Operating Conditions 4-7 4-8 4-8 4-9 4-10 4-10 4-11 4-11 4-12 4-12 4-13 4-14 4-15 4-16 4-17 4-18 4-20 4-22 4-23 4-24 4-25 4-25 4-26 4-27 4-28 4-29 4-30 4-32 4-33 4-35 4-35 4-36 4-37 4-38 4-39 4-39 4-41 4-42 5-1 6-1 7-1 7-1 7-2 7-3 iv 8 7.4 Switching Characteristics for PCI Interface . . . . . . . . . . . . . . . . . . . . . . 7.5 Switching Characteristics for PHY-Link Interface . . . . . . . . . . . . . . . . . Mechanical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 7-3 8-1 List of Illustrations Figure Title Page 2-1 Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 3-1 TSB12LV26 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 5-1 GPIO2 and GPIO3 Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 List of Tables Table 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 3-11 3-12 3-13 3-14 3-15 3-16 3-17 3-18 3-19 3-20 Title Signals Sorted by Terminal Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Names Sorted Alphanumerically to Terminal Number . . . . . . . . . . Power Supply Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI System Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Address and Data Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Interface Control Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IEEE 1394 PHY/Link Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Miscellaneous Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bit Field Access Tag Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Configuration Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class Code and Revision ID Register Description . . . . . . . . . . . . . . . . . . . Latency Timer and Class Cache Line Size Register Description . . . . . . . Header Type and BIST Register Description . . . . . . . . . . . . . . . . . . . . . . . . OHCI Base Address Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . Subsystem Identification Register Description . . . . . . . . . . . . . . . . . . . . . . Interrupt Line and Pin Register Description . . . . . . . . . . . . . . . . . . . . . . . . . MIN_GNT and MAX_LAT Register Description . . . . . . . . . . . . . . . . . . . . . OHCI Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Capability ID and Next Item Pointer Register Description . . . . . . . . . . . . . Power Management Capabilities Register Description . . . . . . . . . . . . . . . Power Management Control and Status Register Description . . . . . . . . . Power Management Extension Register Description . . . . . . . . . . . . . . . . . Miscellaneous Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Link Enhancement Control Register Description . . . . . . . . . . . . . . . . . . . . Subsystem Access Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 2-2 2-3 2-3 2-4 2-4 2-5 2-6 2-6 3-1 3-3 3-4 3-5 3-6 3-6 3-7 3-7 3-8 3-9 3-10 3-10 3-11 3-12 3-13 3-14 3-15 3-16 3-17 3-18 v 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 4-11 4-12 4-13 4-14 4-15 4-16 4-17 4-18 4-19 4-20 4-21 4-22 4-23 4-24 4-25 4-26 4-27 4-28 4-29 4-30 4-31 4-32 6-1 6-2 OHCI Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OHCI Version Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GUID ROM Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous Transmit Retries Register Description . . . . . . . . . . . . . . . . CSR Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration ROM Header Register Description . . . . . . . . . . . . . . . . . . . . Bus Options Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration ROM Mapping Register Description . . . . . . . . . . . . . . . . . . . Posted Write Address Low Register Description . . . . . . . . . . . . . . . . . . . . Posted Write Address High Register Description . . . . . . . . . . . . . . . . . . . . Host Controller Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . Self-ID Count Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Isochronous Receive Channel Mask High Register Description . . . . . . . Isochronous Receive Channel Mask Low Register Description . . . . . . . . Interrupt Event Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Mask Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Isochronous Transmit Interrupt Event Register Description . . . . . . . . . . . Isochronous Receive Interrupt Event Register Description . . . . . . . . . . . Fairness Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Link Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Node Identification Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . PHY Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Isochronous Cycle Timer Register Description . . . . . . . . . . . . . . . . . . . . . . Asynchronous Request Filter High Register Description . . . . . . . . . . . . . Asynchronous Request Filter Low Register Description . . . . . . . . . . . . . . Physical Request Filter High Register Description . . . . . . . . . . . . . . . . . . . Physical Request Filter Low Register Description . . . . . . . . . . . . . . . . . . . Asynchronous Context Control Register Description . . . . . . . . . . . . . . . . . Asynchronous Context Command Pointer Register Description . . . . . . . Isochronous Transmit Context Control Register Description . . . . . . . . . . Isochronous Receive Context Control Register Description . . . . . . . . . . . Isochronous Receive Context Match Register Description . . . . . . . . . . . . Registers and Bits Loadable Through Serial ROM . . . . . . . . . . . . . . . . . . . Serial ROM Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4-4 4-5 4-6 4-7 4-8 4-9 4-11 4-11 4-12 4-13 4-15 4-16 4-17 4-18 4-20 4-22 4-24 4-25 4-26 4-27 4-28 4-29 4-30 4-32 4-33 4-35 4-36 4-37 4-38 4-39 4-42 6-1 6-2 vi 1 Introduction 1.1 Description The Texas Instruments TSB12LV26 device is a PCI-to-1394 host controller compliant with the PCI Local Bus Specification, PCI Bus Power Management Interface Specification, IEEE Std 1394-1995, and 1394 Open Host Controller Interface Specification. The chip provides the IEEE 1394 link function and is compatible with 100M bits/s, 200M bits/s, and 400M bits/s serial bus data rates. As required by the 1394 Open Host Controller Interface Specification (OHCI) and IEEE Std 1394a-2000, internal control registers are memory-mapped and nonprefetchable. The PCI configuration header is accessed through configuration cycles specified by PCI and provides plug-and-play (PnP) compatibility. Furthermore, the TSB12LV26 device is compliant with the PCI Bus Power Management Interface Specification, per the PC 99 Design Guide requirements. TSB12LV26 device supports the D0, D2, and D3 power states. The TSB12LV26 design provides PCI bus master bursting and is capable of transferring a cacheline of data at 132M bytes/s after connection to the memory controller. Since PCI latency can be large, deep FIFOs are provided to buffer 1394 data. The TSB12LV26 device provides physical write posting buffers and a highly-tuned physical data path for SBP-2 performance. The TSB12LV26 device also provides multiple isochronous contexts, multiple cacheline burst transfers, advanced internal arbitration, and bus-holding buffers on the PHY/link interface. An advanced CMOS process achieves low power consumption and allows the TSB12LV26 device to operate at PCI clock rates up to 33 MHz. 1.2 Features The TSB12LV26-EP device supports the following features: * * * * * * * * * * * * * * * * * Controlled Baseline One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of -40C to 110C Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product Change Notification Qualification Pedigree 3.3-V and 5-V PCI bus signaling 3.3-V supply (core voltage is internally regulated to 1.8 V) Serial bus data rates of 100M bits/s, 200M bits/s, and 400M bits/s Physical write posting of up to three outstanding transactions Serial ROM interface supports 2-wire devices External cycle timer control for customized synchronization PCI burst transfers and deep FIFOs to tolerate large host latency Two general-purpose I/Os Fabricated in advanced low-power CMOS process Packaged in 100-terminal LQFP (PZ) PCI_CLKRUN protocol Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. 1-1 1.3 Related Documents * * * * * * * 1394 Open Host Controller Interface Specification (Revision 1.0) IEEE Standard for a High Performance Serial Bus (IEEE Std 1394-1995) IEEE Standard for a High Performance Serial Bus--Amendment 1 (IEEE Std 1394a-2000) PC 99 Design Guide PCI Bus Power Management Interface Specification (Revision 1.0) PCI Local Bus Specification (Revision 2.2) Serial Bus Protocol 2 (SBP-2) 1.4 Trademarks OHCI-Lynx and TI are trademarks of Texas Instruments. Other trademarks are the property of their respective owners. 1.5 Ordering Information TOP-SIDE MARKING TSB12LV26TEP ORDERING NUMBER TSB12LV26TPZEP NAME OHCI-Lynxt PCI-Based IEEE 1394 Host Controller VOLTAGE 3.3V-, 5V-Tolerant I/Os PACKAGE 100-Terminal PQFP 1-2 2 Terminal Descriptions This section provides the terminal descriptions for the TSB12LV26 device. Figure 2-1 shows the signal assigned to each terminal in the package. Table 2-1 is a listing of signal names arranged in terminal number order, and Table 2-2 lists terminals in alphanumeric order by signal names. PZ PACKAGE (TOP VIEW) GND GPIO2 GPIO3 SCL SDA VCCP PCI_CLKRUN PCI_INTA 3.3 VCC G_RST GND PCI_CLK 3.3 VCC PCI_GNT PCI_REQ VCCP PCI_PME PCI_AD31 PCI_AD30 3.3 VCC PCI_AD29 PCI_AD28 PCI_AD27 GND PCI_AD26 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 REG18 PHY_LPS PHY_LINKON PHY_LREQ 3.3 VCC PHY_SCLK GND PHY_CTL0 PHY_CTL1 3.3 VCC PHY_DATA0 PHY_DATA1 PHY_DATA2 VCCP PHY_DATA3 PHY_DATA4 PHY_DATA5 GND PHY_DATA6 PHY_DATA7 3.3 VCC REG_EN CYCLEIN CYCLEOUT PCI_RST GND PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 3.3 VCC PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_C/BE0 PCI_AD8 VCCP PCI_AD9 PCI_AD10 GND PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 3.3 VCC PCI_AD15 PCI_C/BE1 PCI_PAR PCI_SERR PCI_AD25 PCI_AD24 PCI_C/BE3 PCI_IDSEL GND PCI_AD23 PCI_AD22 PCI_AD21 PCI_AD20 3.3 VCC PCI_AD19 PCI_AD18 PCI_AD17 VCCP PCI_AD16 PCI_C/BE2 REG18 PCI_FRAME PCI_IRDY PCI_TRDY 3.3 VCC PCI_DEVSEL PCI_STOP PCI_PERR GND Figure 2-1. Terminal Assignments 2-1 Table 2-1. Signals Sorted by Terminal Number NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 TERMINAL NAME GND GPIO2 GPIO3 SCL SDA VCCP PCI_CLKRUN PCI_INTA 3.3 VCC G_RST GND PCI_CLK 3.3 VCC PCI_GNT PCI_REQ VCCP PCI_PME PCI_AD31 PCI_AD30 3.3 VCC PCI_AD29 PCI_AD28 PCI_AD27 GND PCI_AD26 NO. 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 TERMINAL NAME PCI_AD25 PCI_AD24 PCI_C/BE3 PCI_IDSEL GND PCI_AD23 PCI_AD22 PCI_AD21 PCI_AD20 3.3 VCC PCI_AD19 PCI_AD18 PCI_AD17 VCCP PCI_AD16 PCI_C/BE2 REG18 PCI_FRAME PCI_IRDY PCI_TRDY 3.3 VCC PCI_DEVSEL PCI_STOP PCI_PERR GND NO. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 TERMINAL NAME PCI_SERR PCI_PAR PCI_C/BE1 PCI_AD15 3.3 VCC PCI_AD14 PCI_AD13 PCI_AD12 PCI_AD11 GND PCI_AD10 PCI_AD9 VCCP PCI_AD8 PCI_C/BE0 PCI_AD7 PCI_AD6 PCI_AD5 PCI_AD4 3.3 VCC PCI_AD3 PCI_AD2 PCI_AD1 PCI_AD0 GND NO. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 TERMINAL NAME PCI_RST CYCLEOUT CYCLEIN REG_EN 3.3 VCC PHY_DATA7 PHY_DATA6 GND PHY_DATA5 PHY_DATA4 PHY_DATA3 VCCP PHY_DATA2 PHY_DATA1 PHY_DATA0 3.3 VCC PHY_CTL1 PHY_CTL0 GND PHY_SCLK 3.3 VCC PHY_LREQ PHY_LINKON PHY_LPS REG18 2-2 Table 2-2. Signal Names Sorted Alphanumerically to Terminal Number TERMINAL NAME CYCLEIN CYCLEOUT GND GND GND GND GND GND GND GND GND GPIO2 GPIO3 G_RST PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 NO. 78 77 1 11 24 30 50 60 75 83 94 2 3 10 74 73 72 71 69 68 67 66 64 62 61 TERMINAL NAME PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31 PCI_C/BE0 PCI_C/BE1 PCI_C/BE2 PCI_C/BE3 NO. 59 58 57 56 54 40 38 37 36 34 33 32 31 27 26 25 23 22 21 19 18 65 53 41 28 TERMINAL NAME PCI_CLK PCI_CLKRUN PCI_DEVSEL PCI_FRAME PCI_GNT PCI_IDSEL PCI_INTA PCI_IRDY PCI_PAR PCI_PERR PCI_PME PCI_REQ PCI_RST PCI_SERR PCI_STOP PCI_TRDY PHY_CTL0 PHY_CTL1 PHY_DATA0 PHY_DATA1 PHY_DATA2 PHY_DATA3 PHY_DATA4 PHY_DATA5 PHY_DATA6 NO. 12 7 47 43 14 29 8 44 52 49 17 15 76 51 48 45 93 92 90 89 88 86 85 84 82 TERMINAL NAME PHY_DATA7 PHY_LINKON PHY_LPS PHY_LREQ PHY_SCLK REG_EN REG18 REG18 SCL SDA VCCP VCCP VCCP VCCP VCCP 3.3 VCC 3.3 VCC 3.3 VCC 3.3 VCC 3.3 VCC 3.3 VCC 3.3 VCC 3.3 VCC 3.3 VCC 3.3 VCC NO. 81 98 99 97 95 79 42 100 4 5 6 16 39 63 87 9 13 20 35 46 55 70 80 91 96 The terminals in Table 2-3 through Table 2-8 are grouped in tables by functionality, such as PCI system function and power supply function. The terminal numbers are also listed for convenient reference. Table 2-3. Power Supply Terminals TERMINAL NAME GND NO. 1, 11, 24, 30, 50, 60, 75, 83, 94 6, 16, 39, 63, 87 9, 13, 20, 35, 46, 55, 70, 80, 91, 96 I/O DESCRIPTION I Device ground terminals VCCP 3.3 VCC I PCI signaling clamp voltage power input. PCI signals are clamped per the PCI Local Bus Specification. I 3.3-V power supply terminals 2-3 Table 2-4. PCI System Terminals TERMINAL NAME NO. I/O DESCRIPTION Global power reset. This reset brings all of the TSB12LV26 internal registers to their default states, including those registers not reset by PCI_RST. When G_RST is asserted, the device is completely nonfunctional. G_RST 10 I When implementing wake capabilities from the 1394 host controller, it is necessary to implement two resets to the TSB12LV26 device. G_RST is designed to be a one-time power-on reset, and PCI_RST must be connected to the PCI bus RST. If wake capabilities are not required, G_RST can be connected to the PCI bus RST (see PCI_RST, terminal 76). PCI bus clock. Provides timing for all transactions on the PCI bus. All PCI signals are sampled at rising edge of PCI_CLK. Interrupt signal. This output indicates interrupts from the TSB12LV26 device to the host. This terminal is implemented as open-drain. PCI reset. When this bus reset is asserted, the TSB12LV26 device places all output buffers in a high-impedance state and resets all internal registers except device power management context- and vendor-specific bits initialized by host power-on software. When PCI_RST is asserted, the device is completely nonfunctional. If this terminal is implemented, it must be connected to the PCI bus RST signal. Otherwise, it must be pulled high to link VCC through a 4.7-k resistor, or strapped to the G_RST terminal (see G_RST, terminal 10). PCI_CLK PCI_INTA 12 8 I O PCI_RST 76 I Table 2-5. PCI Address and Data Terminals TERMINAL NAME PCI_AD31 PCI_AD30 PCI_AD29 PCI_AD28 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23 PCI_AD22 PCI_AD21 PCI_AD20 PCI_AD19 PCI_AD18 PCI_AD17 PCI_AD16 PCI_AD15 PCI_AD14 PCI_AD13 PCI_AD12 PCI_AD11 PCI_AD10 PCI_AD9 PCI_AD8 PCI_AD7 PCI_AD6 PCI_AD5 PCI_AD4 PCI_AD3 PCI_AD2 PCI_AD1 PCI_AD0 NO. 18 19 21 22 23 25 26 27 31 32 33 34 36 37 38 40 54 56 57 58 59 61 62 64 66 67 68 69 71 72 73 74 I/O DESCRIPTION I/O PCI address/data bus. These signals make up the multiplexed PCI address and data bus on the PCI interface. During the address phase of a PCI cycle, AD31-AD0 contain a 32-bit address or other destination information. During the data phase, AD31-AD0 contain data. 2-4 Table 2-6. PCI Interface Control Terminals TERMINAL NAME PCI_C/BE0 PCI_C/BE1 PCI_C/BE2 PCI_C/BE3 PCI_CLKRUN NO. 65 53 41 28 7 I/O DESCRIPTION PCI bus commands and byte enables. The command and byte enable signals are multiplexed on the same PCI terminals. During the address phase of a bus cycle PCI_C/BE3-PCI_C/BE0 define the bus command. During the data phase, this 4-bit bus is used as byte enables. Clock run. This terminal provides clock control through the PCI_CLKRUN protocol. An internal pulldown resistor is implemented on this terminal. This terminal is implemented as open-drain. PCI_DEVSEL 47 I/O PCI device select. The TSB12LV26 device asserts this signal to claim a PCI cycle as the target device. As a PCI initiator, the TSB12LV26 device monitors this signal until a target responds. If no target responds before time-out occurs, the TSB12LV26 device terminates the cycle with an initiator abort. PCI cycle frame. This signal is driven by the initiator of a PCI bus cycle. PCI_FRAME is asserted to indicate that a bus transaction is beginning, and data transfers continue while this signal is asserted. When PCI_FRAME is deasserted, the PCI bus transaction is in the final data phase. PCI bus grant. This signal is driven by the PCI bus arbiter to grant the TSB12LV26 device access to the PCI bus after the current data transaction has completed. This signal may or may not follow a PCI bus request, depending upon the PCI bus parking algorithm. Initialization device select. PCI_IDSEL selects the TSB12LV26 device during configuration space accesses. PCI_IDSEL can be connected to one of the upper 24 PCI address lines on the PCI bus. PCI initiator ready. PCI_IRDY indicates the ability of the PCI bus initiator to complete the current data phase of the transaction. A data phase is completed upon a rising edge of PCLK where both PCI_IRDY and PCI_TRDY are asserted. PCI parity. In all PCI bus read and write cycles, the TSB12LV26 device calculates even parity across the PCI_AD and PCI_C/BE buses. As an initiator during PCI cycles, the TSB12LV26 device outputs this parity indicator with a one PCI_CLK delay. As a target during PCI cycles, the calculated parity is compared to the initiator parity indicator; a miscompare can result in a parity error assertion (PCI_PERR). PCI parity error indicator. This signal is driven by a PCI device to indicate that calculated parity does not match PCI_PAR when PERR_ENB (bit 6) in the command register at offset 04h in the PCI configuration space (see Section 3.4, Command Register) is set to 1. Power management event. This terminal indicates wake events to the host. PCI bus request. Asserted by the TSB12LV26 device to request access to the bus as an initiator. The host arbiter asserts the PCI_GNT signal when the TSB12LV26 device has been granted access to the bus. PCI system error. When SERR_ENB (bit 8) in the command register at offset 04h in the PCI configuration space (see Section 3.4, Command Register) is set to 1, the output is pulsed, indicating an address parity error has occurred. The TSB12LV26 device need not be the target of the PCI cycle to assert this signal. This terminal is implemented as open-drain. PCI_STOP 48 I/O PCI cycle stop signal. This signal is driven by a PCI target to request the initiator to stop the current PCI bus transaction. This signal is used for target disconnects, and is commonly asserted by target devices which do not support burst data transfers. PCI target ready. PCI_TRDY indicates the ability of the PCI bus target to complete the current data phase of the transaction. A data phase is completed upon a rising edge of PCI_CLK where both PCI_IRDY and PCI_TRDY are asserted. I/O I/O PCI_FRAME 43 I/O PCI_GNT 14 I PCI_IDSEL 29 I PCI_IRDY 44 I/O PCI_PAR 52 I/O PCI_PERR PCI_PME PCI_REQ 49 17 15 I/O O O PCI_SERR 51 O PCI_TRDY 45 I/O 2-5 Table 2-7. IEEE 1394 PHY/Link Terminals TERMINAL NAME PHY_CTL1 PHY_CTL0 PHY_DATA7 PHY_DATA6 PHY_DATA5 PHY_DATA4 PHY_DATA3 PHY_DATA2 PHY_DATA1 PHY_DATA0 NO. 92 93 81 82 84 85 86 88 89 90 I/O DESCRIPTION PHY-link interface control. These bidirectional signals control passage of information between the two devices. The TSB12LV26 device can only drive these terminals after the PHY device has granted permission following a link request (PHY_LREQ). I/O I/O PHY-link interface data. These bidirectional signals pass data between the TSB12LV26 and the PHY devices. These terminals are driven by the TSB12LV26 device on transmissions and are driven by the PHY device on receptions. Only PHY_DATA1-PHY_DATA0 are valid for 100M-bit speeds, PHY_DATA3-PHY_DATA0 are valid for 200M-bit speeds, and PHY_DATA7-PHY_DATA0 are valid for 400M-bit speeds. PHY_LINKON 98 I/O LinkOn wake indication. The PHY_LINKON signal is pulsed by the PHY device to activate the link, and 3.3-V signaling is required. When connected to the TSB41LV0X C/LKON terminal, a 1-k series resistor is required between the link and PHY device. Link power status. The PHY_LPS signal is asserted when the link is powered on, and 3.3-V signaling is required. Link request. This signal is driven by the TSB12LV26 device to initiate a request for the PHY device to perform some service. System clock. This input from the PHY device provides a 49.152-MHz clock signal for data synchronization. PHY_LPS PHY_LREQ PHY_SCLK 99 97 95 I/O O I Table 2-8. Miscellaneous Terminals TERMINAL NAME CYCLEIN CYCLEOUT GPIO2 GPIO3 REG_EN REG18 NO. 78 77 2 3 79 42 100 I/O DESCRIPTION The CYCLEIN terminal allows an external 8-kHz clock to be used as a cycle timer for synchronization with other system devices. If this terminal is not implemented, it must be pulled high to the link VCC through a 4.7-k resistor. I/O I/O I/O I I This terminal provides an 8-kHz cycle timer synchronization signal. General-purpose I/O [2]. This terminal defaults as an input and if it is not implemented, it is recommended that it be pulled low to ground with a 220- resistor. General-purpose I/O [3]. This terminal defaults as an input and if it is not implemented, it is recommended that it be pulled low to ground with a 220- resistor. Regulator enable. This terminal is pulled low to ground through a 220- resistor. The REG18 terminals are connected to a 0.01 F capacitor which, in turn, is connected to ground. The capacitor provides a local bypass for the internal core voltage. Serial clock. The TSB12LV26 device determines whether a two-wire serial ROM or no serial ROM is implemented at reset. If a two-wire serial ROM is implemented, this terminal provides the SCL serial clock signaling. This terminal is implemented as open-drain, and for normal operation (a ROM is implemented in the design), this terminal must be pulled high to the ROM VCC with a 2.7-k resistor. Otherwise, it must be pulled low to ground with a 220- resistor. Serial data. The TSB12LV26 device determines whether a two-wire serial ROM or no serial ROM is implemented at reset. If a two-wire serial ROM is detected, this terminal provides the SDA serial data signaling. This terminal must be wired low to indicate no serial ROM is present. This terminal is implemented as open-drain, and for normal operation (a ROM is implemented in the design), this terminal must be pulled high to the ROM VCC with a 2.7-k resistor. Otherwise, it must be pulled low to ground with a 220- resistor. I/O SCL 4 I/O SDA 5 I/O 2-6 3 TSB12LV26 Controller Programming Model This section describes the internal registers used to program the TSB12LV26 device. All registers are detailed in the same format: a brief description for each register is followed by the register offset and a bit table describing the reset state for each register. A bit description table, typically included when the register contains bits of more than one type or purpose, indicates bit field names, field access tags which appear in the type column, and a detailed field description. Table 3-1 describes the field access tags. Table 3-1. Bit Field Access Tag Descriptions ACCESS TAG R W S C U NAME Read Write Set Clear Update MEANING Field can be read by software. Field can be written by software to any value. Field can be set by a write of 1. Writes of 0 have no effect. Field can be cleared by a write of 1. Writes of 0 have no effect. Field can be autonomously updated by the TSB12LV26 device. Figure 3-1 shows a simplified block diagram of the TSB12LV26 device. 3-1 PCI Target SM Internal Registers Serial EEPROM OHCI PCI Power Mgmt and CLKRUN GPIOs Misc. Interface ISO Transmit Contexts Async Transmit Contexts Transmit FIFO Physical DMA and Response Link Transmit Resp Timeout PCI Host Bus Interface Receive Acknowledge Central Arbiter and PCI Initiator SM PHY Register Access and Status Monitor Cycle Start Generator and Cycle Monitor CRC Request Filters Synthesized Bus Reset PHY / Link Interface General Request Receive Link Receive Async Response Receive Receive FIFO ISO Receive Contexts Figure 3-1. TSB12LV26 Block Diagram 3-2 3.1 PCI Configuration Registers The TSB12LV26 device is a single-function PCI device. The configuration header is compliant with the PCI Local Bus Specification as a standard header. Table 3-2 illustrates the PCI configuration header that includes both the predefined portion of the configuration space and the user-definable registers. Table 3-2. PCI Configuration Register Map REGISTER NAME Device ID Status Class code BIST Header type Latency timer OHCI registers base address TI extension registers base address Reserved Reserved Reserved Reserved Reserved Subsystem ID Reserved Reserved Reserved Maximum latency Minimum grant Interrupt pin Next item pointer Reserved Miscellaneous configuration register Link_Enhancements register Subsystem ID alias GPIO3 GPIO2 Subsystem vendor ID alias Reserved Interrupt line Capability ID OHCI control register Power management capabilities PM data PMCSR_BSE Power management CSR Power management capabilities pointer Subsystem vendor ID Vendor ID Command Revision ID Cache line size OFFSET 00h 04h 08h 0Ch 10h 14h 18h 1Ch 20h 24h 28h 2Ch 30h 34h 38h 3Ch 40h 44h 48h 4Ch-ECh F0h F4h F8h FCh 3.2 Vendor ID Register The vendor ID register contains a value allocated by the PCI SIG and identifies the manufacturer of the PCI device. The vendor ID assigned to Texas Instruments is 104Ch. Bit Name Type Default R 0 R 0 R 0 R 1 R 0 R 0 R 0 15 14 13 12 11 10 9 8 R 0 7 R 0 6 R 1 5 R 0 4 R 0 3 R 1 2 R 1 1 R 0 0 R 0 Vendor ID Register: Type: Offset: Default: Vendor ID Read-only 00h 104Ch 3-3 3.3 Device ID Register The device ID register contains a value assigned to the TSB12LV26 device by Texas Instruments. The device identification for the TSB12LV26 device is 8020h. Bit Name Type Default R 1 R 0 R 0 R 0 R 0 R 0 R 0 15 14 13 12 11 10 9 8 R 0 7 R 0 6 R 0 5 R 1 4 R 0 3 R 0 2 R 0 1 R 0 0 R 0 Device ID Register: Type: Offset: Default: Device ID Read-only 02h 8020h 3.4 Command Register The command register provides control over the TSB12LV26 interface to the PCI bus. All bit functions adhere to the definitions in the PCI Local Bus Specification, as seen in the following bit descriptions. See Table 3-3 for a complete description of the register contents. Bit Name Type Default R 0 R 0 R 0 R 0 R 0 R 0 R 0 15 14 13 12 11 10 9 8 R/W 0 7 R 0 6 R/W 0 5 R 0 4 R/W 0 3 R 0 2 R/W 0 1 R/W 0 0 R 0 Command Register: Type: Offset: Default: BIT 15-10 9 8 7 6 5 4 FIELD NAME RSVD FBB_ENB SERR_ENB STEP_ENB PERR_ENB VGA_ENB MWI_ENB Command Read/Write, Read-only 04h 0000h Table 3-3. Command Register Description TYPE R R R/W R R/W R R/W DESCRIPTION Reserved. Bits 15-10 return 0s when read. Fast back-to-back enable. The TSB12LV26 device does not generate fast back-to-back transactions; therefore, bit 9 returns 0 when read. PCI_SERR enable. When bit 8 is set to 1, the TSB12LV26 PCI_SERR driver is enabled. PCI_SERR can be asserted after detecting an address parity error on the PCI bus. Address/data stepping control. The TSB12LV26 device does not support address/data stepping; therefore, bit 7 is hardwired to 0. Parity error enable. When bit 6 is set to 1, the TSB12LV26 device is enabled to drive PCI_PERR response to parity errors through the PCI_PERR signal. VGA palette snoop enable. The TSB12LV26 device does not feature VGA palette snooping; therefore, bit 5 returns 0 when read. Memory write and invalidate enable. When bit 4 is set to 1, the TSB12LV26 device is enabled to generate MWI PCI bus commands. If this bit is cleared, the TSB12LV26 device generates memory write commands instead. Special cycle enable. The TSB12LV26 function does not respond to special cycle transactions; therefore, bit 3 returns 0 when read. Bus master enable. When bit 2 is set to 1, the TSB12LV26 device is enabled to initiate cycles on the PCI bus. Memory response enable. Setting bit 1 to 1 enables the TSB12LV26 device to respond to memory cycles on the PCI bus. This bit must be set to access OHCI registers. I/O space enable. The TSB12LV26 device does not implement any I/O-mapped functionality; therefore, bit 0 returns 0 when read. 3 2 1 0 SPECIAL MASTER_ENB MEMORY_ENB IO_ENB R R/W R/W R 3-4 3.5 Status Register The status register provides status over the TSB12LV26 interface to the PCI bus. All bit functions adhere to the definitions in the PCI Local Bus Specification, as seen in the following bit descriptions. See Table 3-4 for a complete description of the register contents. Bit Name Type Default RCU 0 RCU 0 RCU 0 RCU 0 RCU 0 R 0 R 1 0 15 14 13 12 11 10 9 8 Status RCU R 0 R 0 R 0 R 1 R 0 R 0 R 0 R 0 7 6 5 4 3 2 1 0 Register: Type: Offset: Default: Status Read/Clear/Update, Read-only 06h 0210h Table 3-4. Status Register Description BIT 15 14 13 12 11 10-9 8 FIELD NAME PAR_ERR SYS_ERR MABORT TABORT_REC TABORT_SIG PCI_SPEED DATAPAR TYPE RCU RCU RCU RCU RCU R RCU DESCRIPTION Detected parity error. Bit 15 is set to 1 when either an address parity or data parity error is detected. Signaled system error. Bit 14 is set to 1 when PCI_SERR is enabled and the TSB12LV26 device has signaled a system error to the host. Received master abort. Bit 13 is set to 1 when a cycle initiated by the TSB12LV26 device on the PCI bus has been terminated by a master abort. Received target abort. Bit 12 is set to 1 when a cycle initiated by the TSB12LV26 device on the PCI bus was terminated by a target abort. Signaled target abort. Bit 11 is set to 1 by the TSB12LV26 device when it terminates a transaction on the PCI bus with a target abort. DEVSEL timing. Bits 10 and 9 encode the timing of PCI_DEVSEL and are hardwired to 01b, indicating that the TSB12LV26 device asserts this signal at a medium speed on nonconfiguration cycle accesses. Data parity error detected. Bit 8 is set to 1 when the following conditions have been met: a. PCI_PERR was asserted by any PCI device including the TSB12LV26 device. b. The TSB12LV26 device was the bus master during the data parity error. c. Bit 6 (PERR_ENB) in the command register at offset 04h in the PCI configuration space (see Section 3.4, Command Register) is set to 1. 7 6 5 4 3-0 FBB_CAP UDF 66MHZ CAPLIST RSVD R R R R R Fast back-to-back capable. The TSB12LV26 device cannot accept fast back-to-back transactions; therefore, bit 7 is hardwired to 0. User-definable features (UDF) supported. The TSB12LV26 device does not support the UDF; therefore, bit 6 is hardwired to 0. 66-MHz capable. The TSB12LV26 device operates at a maximum PCI_CLK frequency of 33 MHz; therefore, bit 5 is hardwired to 0. Capabilities list. Bit 4 returns 1 when read, indicating that capabilities additional to standard PCI are implemented. The linked list of PCI power-management capabilities is implemented in this function. Reserved. Bits 3-0 return 0s when read. 3-5 3.6 Class Code and Revision ID Register The class code and revision ID register categorizes the TSB12LV26 device as a serial bus controller (0Ch), controlling an IEEE 1394 bus (00h), with an OHCI programming model (10h). Furthermore, the TI chip revision is indicated in the least significant byte. See Table 3-5 for a complete description of the register contents. Bit Name Type Default Bit Name Type Default R 0 R 0 R 0 R 1 R 0 R 0 R 0 15 R 0 14 R 0 13 R 0 12 R 1 11 R 1 10 31 30 29 28 27 26 25 R 0 9 R 0 24 R 0 8 R 0 23 R 0 7 R 0 22 R 0 6 R 0 21 R 0 5 R 0 20 R 0 4 R 0 19 R 0 3 R 0 18 R 0 2 R 0 17 R 0 1 R 0 16 R 0 0 R 0 Class code and revision ID Class code and revision ID Register: Type: Offset: Default: BIT 31-24 23-16 15-8 7-0 FIELD NAME BASECLASS SUBCLASS PGMIF CHIPREV Class code and revision ID Read-only 08h 0C00 1000h Table 3-5. Class Code and Revision ID Register Description TYPE R R R R DESCRIPTION Base class. This field returns 0Ch when read, which broadly classifies the function as a serial bus controller. Subclass. This field returns 00h when read, which specifically classifies the function as controlling an IEEE 1394 serial bus. Programming interface. This field returns 10h when read, indicating that the programming model is compliant with the 1394 Open Host Controller Interface Specification. Silicon revision. This field returns 00h when read, indicating the silicon revision of the TSB12LV26 device. 3.7 Latency Timer and Class Cache Line Size Register The latency timer and class cache line size register is programmed by host BIOS to indicate system cache line size and the latency timer associated with the TSB12LV26 device. See Table 3-6 for a complete description of the register contents. Bit Name Type Default R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 0 15 14 13 12 11 10 R/W 9 R/W 0 8 R/W 0 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 Latency timer and class cache line size Register: Type: Offset: Default: BIT 15-8 FIELD NAME Latency timer and class cache line size Read/Write 0Ch 0000h TYPE R/W DESCRIPTION PCI latency timer. The value in this register specifies the latency timer for the TSB12LV26 device, in units of PCI clock cycles. When the TSB12LV26 device is a PCI bus initiator and asserts PCI_FRAME, the latency timer begins counting from zero. If the latency timer expires before the TSB12LV26 transaction has terminated, the TSB12LV26 device terminates the transaction when its PCI_GNT is deasserted. Cache line size. This value is used by the TSB12LV26 device during memory write and invalidate, memory-read line, and memory-read multiple transactions. Table 3-6. Latency Timer and Class Cache Line Size Register Description LATENCY_TIMER 7-0 CACHELINE_SZ R/W 3-6 3.8 Header Type and BIST Register The header type and built-in self-test (BIST) register indicates the TSB12LV26 PCI header type and no built-in self-test. See Table 3-7 for a complete description of the register contents. Bit Name Type Default R 0 R 0 R 0 R 0 R 0 R 0 R 0 15 14 13 12 11 10 9 8 R 0 7 R 0 6 R 0 5 R 0 4 R 0 3 R 0 2 R 0 1 R 0 0 R 0 Header type and BIST Register: Type: Offset: Default: BIT 15-8 7-0 FIELD NAME BIST HEADER_TYPE Header type and BIST Read-only 0Eh 0000h Table 3-7. Header Type and BIST Register Description TYPE R R DESCRIPTION Built-in self-test. The TSB12LV26 device does not include a BIST; therefore, this field returns 00h when read. PCI header type. The TSB12LV26 device includes the standard PCI header, which is communicated by returning 00h when this field is read. 3.9 OHCI Base Address Register The OHCI base address register is programmed with a base address referencing the memory-mapped OHCI control. When BIOS writes all 1s to this register, the value read back is FFFF F800h, indicating that at least 2K bytes of memory address space are required for the OHCI registers. See Table 3-8 for a complete description of the register contents. Bit Name Type Default Bit Name Type Default R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R 0 R 0 R/W 0 15 R/W 0 14 R/W 0 13 R/W 0 12 R/W 0 11 R/W 0 10 R/W 0 9 31 30 29 28 27 26 25 24 R/W 0 8 R 0 23 R/W 0 7 R 0 22 R/W 0 6 R 0 21 R/W 0 5 R 0 20 R/W 0 4 R 0 19 R/W 0 3 R 0 18 R/W 0 2 R 0 17 R/W 0 1 R 0 16 R/W 0 0 R 0 OHCI base address OHCI address Register: Type: Offset: Default: BIT 31-11 10-4 3 2-1 0 FIELD NAME OHCI base address Read/Write, Read-only 10h 0000 0000h Table 3-8. OHCI Base Address Register Description TYPE R/W R R R R DESCRIPTION OHCI register pointer. Specifies the upper 21 bits of the 32-bit OHCI base address register. OHCI register size. This field returns 0s when read, indicating that the OHCI registers require a 2K-byte region of memory. OHCI register prefetch. This bit returns 0 when read, indicating that the OHCI registers are nonprefetchable. OHCI memory type. This field returns 0s when read, indicating that the OHCI base address register is 32 bits wide and mapping can be done anywhere in the 32-bit memory space. OHCI memory indicator. Bit 0 returns 0 when read, indicating that the OHCI registers are mapped into system memory space. OHCIREG_PTR OHCI_SZ OHCI_PF OHCI_MEMTYPE OHCI_MEM 3-7 3.10 TI Extension Base Address Register The TI extension base address register is programmed with a base address referencing the memory-mapped TI extension registers. See Section 3.9, OHCI Base Address Register for bit field details. Bit Name Type Default Bit Name Type Default R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 15 R/W 0 14 R/W 0 13 R/W 0 12 R/W 0 11 R/W 0 10 31 30 29 28 27 26 25 R/W 0 9 R 0 24 R/W 0 8 R 0 23 R/W 0 7 R 0 22 R/W 0 6 R 0 21 R/W 0 5 R 0 20 R/W 0 4 R 0 19 R/W 0 3 R 0 18 R/W 0 2 R 0 17 R/W 0 1 R 0 16 R/W 0 0 R 0 TI extension base address TI extension base address Register: Type: Offset: Default: TI extension base address Read/Write, Read-only 14h 0000 0000h 3.11 Subsystem Identification Register The subsystem identification register is used for system and option card identification purposes. This register can be initialized from the serial EEPROM or programmed via the subsystem access register at offset F8h in PCI configuration space (see Section 3.22, Subsystem Access Register). See Table 3-9 for a complete description of the register contents. Bit Name Type Default Bit Name Type Default RU 0 RU 0 RU 0 RU 0 RU 0 RU 0 RU 0 15 RU 0 14 RU 0 13 RU 0 12 RU 0 11 RU 0 10 31 30 29 28 27 26 25 RU 0 9 RU 0 24 RU 0 8 RU 0 23 RU 0 7 RU 0 22 RU 0 6 RU 0 21 RU 0 5 RU 0 20 RU 0 4 RU 0 19 RU 0 3 RU 0 18 RU 0 2 RU 0 17 RU 0 1 RU 0 16 RU 0 0 RU 0 Subsystem identification Subsystem identification Register: Type: Offset: Default: Subsystem identification Read/Update 2Ch 0000 0000h Table 3-9. Subsystem Identification Register Description BIT 31-16 15-0 FIELD NAME OHCI_SSID OHCI_SSVID TYPE RU RU DESCRIPTION Subsystem device ID. This field indicates the subsystem device ID. Subsystem vendor ID. This field indicates the subsystem vendor ID. 3-8 3.12 Power Management Capabilities Pointer Register The power management capabilities pointer register provides a pointer into the PCI configuration header where the PCI power-management register block resides. The TSB12LV26 configuration header doublewords at offsets 44h and 48h provide the power-management registers. This register is read-only and returns 44h when read. Bit Name Type Default R 0 R 1 R 0 7 6 5 4 R 0 3 R 0 2 R 1 1 R 0 0 R 0 Power management capabilities pointer Register: Type: Offset: Default: Power management capabilities pointer Read-only 34h 44h 3.13 Interrupt Line and Pin Register The interrupt line and pin register communicates interrupt line routing information. See Table 3-10 for a complete description of the register contents. Bit Name Type Default R 0 R 0 R 0 R 0 R 0 R 0 R 0 15 14 13 12 11 10 9 8 R 1 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 Interrupt line and pin Register: Type: Offset: Default: Interrupt line and pin Read/Write, Read-only 3Ch 0100h Table 3-10. Interrupt Line and Pin Register Description BIT 15-8 7-0 FIELD NAME INTR_PIN INTR_LINE TYPE R R/W DESCRIPTION Interrupt pin. This field returns 01h when read, indicating that the TSB12LV26 PCI function signals interrupts on the PCI_INTA terminal. Interrupt line. This field is programmed by the system and indicates to software which interrupt line the TSB12LV26 PCI_INTA is connected to. 3-9 3.14 MIN_GNT and MAX_LAT Register The MIN_GNT and MAX_LAT register communicates to the system the desired setting of bits 15-8 in the latency timer and class cache line size register at offset 0Ch in PCI configuration space (see Section 3.7, Latency Timer and Class Cache Line Size Register). If a serial EEPROM is detected, the contents of this register are loaded through the serial EEPROM interface after a PCI_RST. If no serial EEPROM is detected, this register returns a default value that corresponds to the MIN_GNT = 2, MAX_LAT = 4. See Table 3-11 for a complete description of the register contents. Bit Name Type Default RU 0 RU 0 RU 0 RU 0 RU 0 RU 1 15 14 13 12 11 10 9 RU 0 8 RU 0 7 RU 0 6 RU 0 5 RU 0 4 RU 0 3 RU 0 2 RU 0 1 RU 1 0 RU 0 MIN_GNT and MAX_LAT Register: Type: Offset: Default: BIT 15-8 FIELD NAME MAX_LAT MIN_GNT and MAX_LAT Read/Update 3Eh 0402h Table 3-11. MIN_GNT and MAX_LAT Register Description TYPE RU DESCRIPTION Maximum latency. The contents of this field may be used by host BIOS to assign an arbitration priority level to the TSB12LV26 device. The default for this register indicates that the TSB12LV26 device may need to access the PCI bus as often as every 0.25 s; thus, an extremely high priority level is requested. The contents of this field may also be loaded through the serial EEPROM. Minimum grant. The contents of this field may be used by host BIOS to assign a latency timer register value to the TSB12LV26 device. The default for this register indicates that the TSB12LV26 device may need to sustain burst transfers for nearly 64 s; thus, requesting a large value be programmed in bits 15-8 of the TSB12LV26 latency timer and class cache line size register at offset 0Ch in PCI configuration space (see Section 3.7, Latency Timer and Class Cache Line Size Register). 7-0 MIN_GNT RU 3.15 OHCI Control Register The OHCI control register is defined by the 1394 Open Host Controller Interface Specification and provides a bit for big endian PCI support. See Table 3-12 for a complete description of the register contents. Bit Name Type Default Bit Name Type Default R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 15 R 0 14 R 0 13 R 0 12 R 0 11 R 0 10 R 0 9 31 30 29 28 27 26 25 24 R 0 8 R 0 23 R 0 7 R 0 22 R 0 6 R 0 21 R 0 5 R 0 20 R 0 4 R 0 19 R 0 3 R 0 18 R 0 2 R 0 17 R 0 1 R 0 16 R 0 0 R/W 0 OHCI control OHCI control Register: Type: Offset: Default: BIT 31-1 0 FIELD NAME RSVD GLOBAL_SWAP OHCI control Read/Write, Read-only 40h 0000 0000h Table 3-12. OHCI Control Register Description TYPE R R/W Reserved. Bits 31-1 return 0s when read. When bit 0 is set to 1, all quadlets read from and written to the PCI interface are byte-swapped (big endian). This bit is loaded from serial EEPROM and must be cleared to 0 for normal IBM-compatible operation. DESCRIPTION 3-10 3.16 Capability ID and Next Item Pointer Register The capability ID and next item pointer register identifies the linked-list capability item and provides a pointer to the next capability item. See Table 3-13 for a complete description of the register contents. Bit Name Type Default R 0 R 0 R 0 R 0 R 0 R 0 15 14 13 12 11 10 9 R 0 8 R 0 7 R 0 6 R 0 5 R 0 4 R 0 3 R 0 2 R 0 1 R 0 0 R 1 Capability ID and next item pointer Register: Type: Offset: Default: Capability ID and next item pointer Read-only 44h 0001h Table 3-13. Capability ID and Next Item Pointer Register Description BIT 15-8 FIELD NAME NEXT_ITEM TYPE R DESCRIPTION Next item pointer. The TSB12LV26 device supports only one additional capability that is communicated to the system through the extended capabilities list; therefore, this field returns 00h when read. Capability identification. This field returns 01h when read, which is the unique ID assigned by the PCI SIG for PCI power-management capability. 7-0 CAPABILITY_ID R 3-11 3.17 Power Management Capabilities Register The power management capabilities register indicates the capabilities of the TSB12LV26 device related to PCI power management. See Table 3-14 for a complete description of the register contents. Bit Name Type Default RU 0 RU 1 RU 1 RU 0 RU 0 RU 1 15 14 13 12 11 10 9 R 0 8 R 0 7 R 0 6 R 0 5 R 0 4 R 0 3 R 0 2 R 0 1 R 0 0 R 1 Power management capabilities Register: Type: Offset: Default: Power management capabilities Read/Update, Read-only 46h 6401h Table 3-14. Power Management Capabilities Register Description BIT 15 FIELD NAME PME_D3COLD TYPE RU DESCRIPTION PCI_PME support from D3cold. This bit can be set to 1 or cleared to 0 via bit 15 (PME_D3COLD) in the miscellaneous configuration register at offset F0h in the PCI configuration space (see Section 3.20, Miscellaneous Configuration Register). The miscellaneous configuration register is loaded from ROM. When this bit is set to 1, it indicates that the TSB12LV26 device is capable of generating a PCI_PME wake event from D3cold. This bit state is dependent upon the TSB12LV26 VAUX implementation and may be configured by using bit 15 (PME_D3COLD) in the miscellaneous configuration register. PCI_PME support. This 4-bit field indicates the power states from which the TSB12LV26 device may assert PCI_PME. This field returns a value of 1100b by default, indicating that PCI_PME may be asserted from the D3hot and D2 power states. Bit 13 may be modified by host software using bit 13 (PME_SUPPORT_D2) in the miscellaneous configuration register at offset F0h in the PCI configuration space (see Section 3.20, Miscellaneous Configuration Register). D2 support. This bit can be set or cleared via bit 10 (D2_SUPPORT) in the miscellaneous configuration register at offset F0h in the PCI configuration space (see Section 3.20, Miscellaneous Configuration Register). The miscellaneous configuration register is loaded from serial EEPROM. When this bit is set to 1, it indicates that D2 support is present. When this bit is cleared, it indicates that D2 support is not present for backward compatibility with the TSB12LV22 device. For normal operation, this bit is set to 1. D1 support. Bit 9 returns a 0 when read, indicating that the TSB12LV26 device does not support the D1 power state. Dynamic data support. Bit 8 returns a 0 when read, indicating that the TSB12LV26 device does not report dynamic power-consumption data. Reserved. Bits 7 and 6 return 0s when read. Device-specific initialization. Bit 5 returns 0 when read, indicating that the TSB12LV26 device does not require special initialization beyond the standard PCI configuration header before a generic class driver is able to use it. Auxiliary power source. Since the TSB12LV26 device does not support PCI_PME generation in the D3cold device state, bit 4 returns 0 when read. PME clock. Bit 3 returns 0 when read, indicating that no host bus clock is required for the TSB12LV26 device to generate PCI_PME. Power-management version. This field returns 001b when read, indicating that the TSB12LV26 device is compatible with the registers described in the PCI Bus Power Management Interface Specification (Revision 1.0). 14-11 PME_SUPPORT RU 10 D2_SUPPORT RU 9 8 7-6 5 D1_SUPPORT DYN_DATA RSVD DSI R R R R 4 3 2-0 AUX_PWR PME_CLK PM_VERSION R R R 3-12 3.18 Power Management Control and Status Register The power management control and status register implements the control and status of the PCI power management function. This register is not affected by the internally generated reset caused by the transition from the D3hot to D0 state. See Table 3-15 for a complete description of the register contents. Bit Name Type Default RC 0 R 0 R 0 R 0 R 0 R 0 15 14 13 12 11 10 9 R 0 8 R/W 0 7 R 0 6 R 0 5 R 0 4 R 0 3 R 0 2 R 0 1 R/W 0 0 R/W 0 Power management control and status Register: Type: Offset: Default: Power management control and status Read/Clear, Read/Write, Read-only 48h 0000h Table 3-15. Power Management Control and Status Register Description BIT 15 FIELD NAME PME_STS TYPE RC DESCRIPTION Bit 15 is set to 1 when the TSB12LV26 device normally asserts the PCI_PME signal, independent of the state of bit 8 (PME_ENB). This bit is cleared by a writeback of 1, which also clears the PCI_PME signal driven by the TSB12LV26 device. Writing a 0 to this bit has no effect. Dynamic data control. This field returns 0s when read since the TSB12LV26 device does not report dynamic data. When bit 8 is set to 1, PCI_PME assertion is enabled. When bit 8 is cleared, PCI_PME assertion is disabled. This bit defaults to 0 if the function does not support PCI_PME generation from D3cold. If the function supports PCI_PME from D3cold, this bit is sticky and must be explicitly cleared by the operating system each time it is initially loaded. Functions that do not support PCI_PME generation from any D-state (that is, bits 15-11 in the power management capabilities register at offset 46h in PCI configuration space (see Section 3.17, Power Management Capabilities Register) equal 00000b), may hardwire this bit to be read-only, always returning a 0 when read by system software. Reserved. Bits 7-5 return 0s when read. Dynamic data. Bit 4 returns 0 when read since the TSB12LV26 device does not report dynamic data. Reserved. Bits 3 and 2 return 0s when read. Power state. This 2-bit field sets the TSB12LV26 device power state and is encoded as follows: 00 = Current power state is D0. 01 = Current power state is D1 (not supported by this device). 10 = Current power state is D2. 11 = Current power state is D3hot. 14-9 8 DYN_CTRL PME_ENB R R/W 7-5 4 3-2 1-0 RSVD DYN_DATA RSVD PWR_STATE R R R R/W 3-13 3.19 Power Management Extension Register The power management extension register provides extended power management features not applicable to the TSB12LV26 device; thus, it is read-only and returns 0s when read. See Table 3-16 for a complete description of the register contents. Bit Name Type Default R 0 R 0 R 0 R 0 R 0 R 0 15 14 13 12 11 10 9 R 0 8 R 0 7 R 0 6 R 0 5 R 0 4 R 0 3 R 0 2 R 0 1 R 0 0 R 0 Power management extension Register: Type: Offset: Default: Power management extension Read-only 4Ah 0000h Table 3-16. Power Management Extension Register Description BIT 15-8 7-0 FIELD NAME PM_DATA PMCSR_BSE TYPE R R DESCRIPTION Power management data. This field returns 00h when read since the TSB12LV26 device does not report dynamic data. Power management CSR - bridge support extensions. This field returns 00h when read since the TSB12LV26 device does not provide P2P bridging. 3-14 3.20 Miscellaneous Configuration Register The miscellaneous configuration register provides miscellaneous PCI-related configuration. See Table 3-17 for a complete description of the register contents. Bit Name Type Default Bit Name Type Default R/W 0 R 0 R/W 1 R 0 R 0 R/W 1 R 0 15 R 0 14 R 0 13 R 0 12 R 0 11 R 0 10 31 30 29 28 27 26 25 R 0 9 R 0 24 R 0 8 R 0 23 R 0 7 R 0 22 R 0 6 R 0 21 R 0 5 R 0 20 R 0 4 R/W 0 19 R 0 3 R/W 0 18 R 0 2 R/W 0 17 R 0 1 R/W 0 16 R 0 0 R/W 0 Miscellaneous configuration Miscellaneous configuration Register: Type: Offset: Default: Miscellaneous configuration Read/Write, Read-only F0h 0000 2400h Table 3-17. Miscellaneous Configuration Register BIT 31-16 15 FIELD NAME RSVD PME_D3COLD TYPE R R/W DESCRIPTION Reserved. Bits 31-16 return 0s when read. PCI_PME support from D3cold. This bit programs bit 15 (PME_D3COLD) in the power management capabilities register at offset 46h in PCI configuration space (see Section 3.17, Power Management Capabilities Register). Reserved. Bit 14 returns 0 when read. PCI_PME support. This bit programs bit 13 (PME_SUPPORT_D2) in the power management capabilities register at offset 46h in PCI configuration space (see Section 3.17, Power Management Capabilities Register). If wake up from the D2 power state implemented in the TSB12LV26 device is not desired, this bit is cleared to indicate to power-management software that wake-up from D2 is not supported. Reserved. Bits 12 and 11 return 0s when read. D2 support. This bit programs bit 10 (D2_SUPPORT) in the power management capabilities register at offset 46h in PCI configuration space (see Section 3.17, Power Management Capabilities Register). If the D2 power state in the TSB12LV26 device is not desired, this bit is cleared to indicate to power-management software that D2 is not supported. Reserved. Bits 9-5 return 0s when read. Bit 4 defaults to 0, which provides OHCI-Lynxt compatible target abort signaling. When this bit is set to 1, it enables the no-target-abort mode, in which the TSB12LV26 device returns indeterminate data instead of signaling target abort. The link is divided into the PCI_CLK and SCLK domains. If software tries to access registers in the link that are not active because the SCLK is disabled, a target abort is issued by the link. On some systems, this can cause a problem resulting in a fatal system error. Enabling this bit allows the link to respond to these types of requests by returning FFh. It is recommended that this bit be set to 1. 14 13 RSVD PME_SUPPORT_D2 R R/W 12-11 10 RSVD D2_SUPPORT R R/W 9-5 4 RSVD DIS_TGT_ABT R R/W 3 2 1 0 GP2IIC DISABLE_SCLKGATE DISABLE_PCIGATE KEEP_PCLK R/W R/W R/W R/W When bit 3 is set to 1, the GPIO3 and GPIO2 signals are internally routed to the SCL and SDA, respectively. The GPIO3 and GPIO2 terminals are also placed in a high-impedance state. When bit 2 is set to 1, the internal SCLK runs identically with the chip input. This is a test feature only and must be cleared to 0 (all applications). When bit 1 is set to 1, the internal PCI clock runs identically with the chip input. This is a test feature only and must be cleared to 0 (all applications). When bit 0 is set to 1, the PCI clock is always kept running through the PCI_CLKRUN protocol. When this bit is cleared, the PCI clock can be stopped using PCI_CLKRUN. 3-15 3.21 Link Enhancement Control Register The link enhancement control register implements TI proprietary bits that are initialized by software or by a serial EEPROM, if present. After these bits are set to 1, their functionality is enabled only if bit 22 (aPhyEnhanceEnable) in the host controller control register at OHCI offset 50h/54h (see Section 4.16, Host Controller Control Register) is set to 1. See Table 3-18 for a complete description of the register contents. Bit Name Type Default Bit Name Type Default R 0 R 0 R/W 0 R/W 1 R 0 R 0 R 0 15 R 0 14 R 0 13 R 0 12 R 0 11 R 0 10 31 30 29 28 27 26 25 R 0 9 R 0 24 R 0 8 R 0 23 R 0 7 R/W 0 22 R 0 6 R 0 21 R 0 5 R 0 20 R 0 4 R 0 19 R 0 3 R 0 18 R 0 2 R/W 0 17 R 0 1 R/W 0 16 R 0 0 R 0 Link enhancement control Link enhancement control Register: Type: Offset: Default: Link enhancement control Read/Write, Read-only F4h 0000 1000h Table 3-18. Link Enhancement Control Register Description BIT 31-14 13-12 FIELD NAME RSVD atx_thresh TYPE R R/W DESCRIPTION Reserved. Bits 31-14 return 0s when read. This field sets the initial AT threshold value, which is used until the AT FIFO is underrun. When the TSB12LV26 device retries the packet, it uses a 2K-byte threshold, resulting in a store-and-forward operation. 00 = Threshold ~ 2K bytes resulting in a store-and-forward operation 01 = Threshold ~ 1.7K bytes (default) 10 = Threshold ~ 1K bytes 11 = Threshold ~ 512 bytes These bits fine-tune the asynchronous transmit threshold. For most applications the 1.7-K threshold is optimal. Changing this value may increase or decrease the 1394 latency depending on the average PCI bus latency. Setting the AT threshold to 1.7K, 1K, or 512 bytes results in data being transmitted at these thresholds or when an entire packet has been checked into the FIFO. If the packet to be transmitted is larger than the AT threshold, the remaining data must be received before the AT FIFO is emptied; otherwise, an underrun condition will occur, resulting in a packet error at the receiving node. As a result, the link will then commence store-and-forward operation--that is, wait until it has the complete packet in the FIFO before retransmitting it on the second attempt, to ensure delivery. An AT threshold of 2K results in store-and-forward operation, which means that asynchronous data will not be transmitted until an end-of-packet token is received. Restated, setting the AT threshold to 2K results in only complete packets being transmitted. Note that this device always uses store-and-forward when the asynchronous transmit retries register at OHCI offset 08h (see Section 4.3, Asynchronous Transmit Retries Register) is cleared. 11-8 7 6 RSVD enab_unfair RSVD R R/W R Reserved. Bits 11-8 return 0s when read. Enable asynchronous priority requests. OHCI-Lynxt compatible. Setting bit 7 to 1 enables the link to respond to requests with priority arbitration. It is recommended that this bit be set to 1. This bit is not assigned in the TSB12LV26 follow-on products, since this bit location loaded by the serial EEPROM from the enhancements field corresponds to bit 23 (programPhyEnable) in the host controller control register at OHCI offset 50h/54h (see Section 4.16, Host Controller Control Register). Reserved. Bits 5-3 return 0s when read. 5-3 RSVD R 3-16 Table 3-18. Link Enhancement Control Register Description (Continued) BIT 2 FIELD NAME enab_insert_idle TYPE R/W DESCRIPTION Enable insert idle. OHCI-Lynxt compatible. When the PHY device has control of the PHY_CTL0 and PHY_CTL1 control lines and the PHY_DATA0-PHY_DATA7 data lines and the link requests control, the PHY device drives 11b on the PHY_CTL0 and PHY_CTL1 lines. The link can then start driving these lines immediately. Setting bit 2 to 1 inserts an idle state, so the link waits one clock cycle before it starts driving the lines (turnaround time). It is recommended that this bit be set to 1. Enable acceleration enhancements. OHCI-Lynxt compatible. When bit 1 is set to 1, the PHY device is notified that the link supports the IEEE 1394a-2000 acceleration enhancements, that is, ack-accelerated, fly-by concatenation, etc. It is recommended that this bit be set to 1. Reserved. Bit 0 returns 0 when read. 1 enab_accel R/W 0 RSVD R 3.22 Subsystem Access Register Write access to the subsystem access register updates the subsystem identification registers identically to OHCI-Lynxt. The system ID value written to this register may also be read back from this register. See Table 3-19 for a complete description of the register contents. Bit Name Type Default Bit Name Type Default R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 R/W 0 14 R/W 0 13 R/W 0 12 R/W 0 11 R/W 0 10 R/W 0 9 31 30 29 28 27 26 25 24 R/W 0 8 R/W 0 23 R/W 0 7 R/W 0 22 R/W 0 6 R/W 0 21 R/W 0 5 R/W 0 20 R/W 0 4 R/W 0 19 R/W 0 3 R/W 0 18 R/W 0 2 R/W 0 17 R/W 0 1 R/W 0 16 R/W 0 0 R/W 0 Subsystem access Subsystem access Register: Type: Offset: Default: Subsystem access Read/Write F8h 0000 0000h Table 3-19. Subsystem Access Register Description BIT 31-16 15-0 FIELD NAME SUBDEV_ID SUBVEN_ID TYPE R/W R/W DESCRIPTION Subsystem device ID alias. This field indicates the subsystem device ID. Subsystem vendor ID alias. This field indicates the subsystem vendor ID. 3-17 3.23 GPIO Control Register The GPIO control register has the control and status bits for the GPIO2 and GPIO3 ports. See Table 3-20 for a complete description of the register contents. Bit Name Type Default Bit Name Type Default R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 15 R 0 14 R/W 0 13 R/W 0 12 R 0 11 R 0 10 R 0 9 31 30 29 28 27 26 25 24 RWU 0 8 R 0 23 R/W 0 7 R 0 22 R 0 6 R 0 21 R/W 0 5 R 0 20 R/W 0 4 R 0 19 R 0 3 R 0 18 R 0 2 R 0 17 R 0 1 R 0 16 RWU 0 0 R 0 GPIO control GPIO control Register: Type: Offset: Default: GPIO control Read/Write/Update, Read/Write, Read-only FCh 0000 0000h Table 3-20. GPIO Control Register Description BIT 31 FIELD NAME INT_3EN TYPE R/W DESCRIPTION When bit 31 is set to 1, a TSB12LV26 general-purpose interrupt event occurs on a level change of the GPIO3 input. This event can generate an interrupt, with mask and event status reported through the interrupt mask register at OHCI offset 88h/8Ch (see Section 4.22, Interrupt Mask Register) and interrupt event register at OHCI offset 80h/84h (see Section 4.21, Interrupt Event Register). Reserved. Bit 30 returns 0 when read. GPIO3 polarity invert. When bit 29 is set to 1, the polarity of GPIO3 is inverted. GPIO3 enable control. When bit 28 is set to 1, the output is enabled. Otherwise, the output is high impedance. Reserved. Bits 27-25 return 0s when read. GPIO3 data. Reads from bit 24 return the logical value of the input to GPIO3. Writes to this bit update the value to drive to GPIO3 when output is enabled. When bit 23 is set to 1, a TSB12LV26 general-purpose interrupt event occurs on a level change of the GPIO2 input. This event may generate an interrupt, with mask and event status reported through the interrupt mask register at OHCI offset 88h/8Ch (see Section 4.22, Interrupt Mask Register) and interrupt event register at OHCI offset 80h/84h (see Section 4.21, Interrupt Event Register). Reserved. Bit 22 returns 0 when read. GPIO2 polarity invert. When bit 21 is set to 1, the polarity of GPIO2 is inverted. GPIO2 enable control. When bit 20 is set to 1, the output is enabled. Otherwise, the output is high impedance. Reserved. Bits 19-17 return 0s when read. GPIO2 data. Reads from bit 16 return the logical value of the input to GPIO2. Writes to this bit update the value to drive to GPIO2 when the output is enabled. Reserved. Bits 15-0 return 0s when read. 30 29 28 27-25 24 23 RSVD GPIO_INV3 GPIO_ENB3 RSVD GPIO_DATA3 INT_2EN R R/W R/W R RWU R/W 22 21 20 19-17 16 15-0 RSVD GPIO_INV2 GPIO_ENB2 RSVD GPIO_DATA2 RSVD R R/W R/W R RWU R 3-18 4 OHCI Registers The OHCI registers defined by the 1394 Open Host Controller Interface Specification are memory-mapped into a 2K-byte region of memory pointed to by the OHCI base address register at offset 10h in PCI configuration space (see Section 3.9, OHCI Base Address Register). These registers are the primary interface for controlling the TSB12LV26 IEEE 1394 link function. This section provides the register interface and bit descriptions. Several set/clear register pairs in this programming model are implemented to solve various issues with typical read-modify-write control registers. There are two addresses for a set/clear register: RegisterSet and RegisterClear. See Table 4-1 for a register listing. A 1 bit written to RegisterSet causes the corresponding bit in the set/clear register to be set to 1; a 0 bit leaves the corresponding bit unaffected. A 1 bit written to RegisterClear causes the corresponding bit in the set/clear register to be cleared; a 0 bit leaves the corresponding bit in the set/clear register unaffected. Typically, a read from either RegisterSet or RegisterClear returns the contents of the set or clear register, respectively. However, sometimes reading the RegisterClear provides a masked version of the set or clear register. The interrupt event register is an example of this behavior. Table 4-1. OHCI Register Map DMA CONTEXT -- REGISTER NAME OHCI version GUID ROM Asynchronous transmit retries CSR data CSR compare data CSR control Configuration ROM header Bus identification Bus options GUID high GUID low Reserved Configuration ROM map Posted write address low Posted write address high Vendor identification Host controller control Reserved ABBREVIATION Version GUID_ROM ATRetries CSRData CSRCompareData CSRControl ConfigROMhdr BusID BusOptions GUIDHi GUIDLo -- ConfigROMmap PostedWriteAddressLo PostedWriteAddressHi VendorID HCControlSet HCControlClr -- OFFSET 00h 04h 08h 0Ch 10h 14h 18h 1Ch 20h 24h 28h 2Ch-30h 34h 38h 3Ch 40h-4Ch 50h 54h 58h-5Ch 4-1 Table 4-1. OHCI Register Map (Continued) DMA CONTEXT Self ID Reserved Self ID buffer Self ID count Reserved -- Isochronous receive channel mask high Isochronous receive channel mask low Interrupt event Interrupt mask Isochronous transmit interrupt event Isochronous transmit interrupt mask -- Isochronous receive interrupt event Isochronous receive interrupt mask Reserved Fairness control Link control Node identification PHY layer control Isochronous cycle timer Reserved AsyncRequestFilterHiSet Asynchronous request filter high Asynchronous request filter low Physical request filter high Physical request filter low Physical upper bound Reserved AsyncRequestFilterHiClear AsyncRequestFilterLoSet AsyncRequestFilterloClear PhysicalRequestFilterHiSet PhysicalRequestFilterHiClear PhysicalRequestFilterLoSet PhysicalRequestFilterloClear PhysicalUpperBound -- FairnessControl LinkControlSet LinkControlClear NodeID PhyControl Isocyctimer REGISTER NAME -- SelfIDBuffer SelfIDCount -- IRChannelMaskHiSet IRChannelMaskHiClear IRChannelMaskLoSet IRChannelMaskLoClear IntEventSet IntEventClear IntMaskSet IntMaskClear IsoXmitIntEventSet IsoXmitIntEventClear IsoXmitIntMaskSet IsoXmitIntMaskClear IsoRecvIntEventSet IsoRecvIntEventClear IsoRecvIntMaskSet IsoRecvIntMaskClear ABBREVIATION OFFSET 60h 64h 68h 6Ch 70h 74h 78h 7Ch 80h 84h 88h 8Ch 90h 94h 98h 9Ch A0h A4h A8h ACh B0h-D8h DCh E0h E4h E8h ECh F0h F4h-FCh 100h 104h 108h 10Ch 110h 114h 118h 11Ch 120h 124h-17Ch 4-2 Table 4-1. OHCI Register Map (Continued) DMA CONTEXT REGISTER NAME Asynchronous context control Reserved Asynchronous context command pointer Reserved Asynchronous context control Reserved Asynchronous context command pointer Reserved Asynchronous context control Reserved Asynchronous context command pointer Reserved Asynchronous context control Reserved Asynchronous context command pointer Reserved Isochronous transmit context control Isochronous Transmit Context n n = 0, 1, 2, 3, ..., 7 Reserved Isochronous transmit context command pointer Reserved Isochronous receive context control Isochronous Receive Context n n = 0, 1, 2, 3 Reserved Isochronous receive context command pointer Context match ABBREVIATION ContextControlSet Asychronous Request Transmit [ ATRQ ] Q ContextControlClear -- CommandPtr -- ContextControlSet Asychronous Res onse Response Transmit [ ATRS ] ContextControlClear -- CommandPtr -- ContextControlSet Asychronous Request Receive [ ARRQ ] Q ContextControlClear -- CommandPtr -- ContextControlSet Asychronous Res onse Response Receive [ ARRS ] ContextControlClear -- CommandPtr -- ContextControlSet ContextControlClear -- CommandPtr -- ContextControlSet ContextControlClear -- CommandPtr ContextMatch OFFSET 180h 184h 188h 18Ch 190h-19Ch 1A0h 1A4h 1A8h 1ACh 1B0h-1BCh 1C0h 1C4h 1C8h 1CCh 1D0h-1DCh 1E0h 1E4h 1E8h 1ECh 1F0h-1FCh 200h + 16*n 204h + 16*n 208h + 16*n 20Ch + 16*n 280h-3FCh 400h + 32*n 404h + 32*n 408h + 32*n 40Ch + 32*n 410h + 32*n 4-3 4.1 OHCI Version Register The OHCI version register indicates the OHCI version support and whether or not the serial EEPROM is present. See Table 4-2 for a complete description of the register contents. Bit Name Type Default Bit Name Type Default R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 15 R 0 14 R 0 13 R 0 12 R 0 11 R 0 10 R 0 9 31 30 29 28 27 26 25 24 R X 8 R 0 23 R 0 7 R 0 22 R 0 6 R 0 21 R 0 5 R 0 20 R 0 4 R 0 19 R 0 3 R 0 18 R 0 2 R 0 17 R 0 1 R 0 16 R 1 0 R 0 OHCI version OHCI version Register: Type: Offset: Default: OHCI version Read-only 00h 0X01 0000h Table 4-2. OHCI Version Register Description BIT 31-25 24 23-16 15-8 7-0 FIELD NAME RSVD GUID_ROM version RSVD revision TYPE R R R R R DESCRIPTION Reserved. Bits 31-25 return 0s when read. The TSB12LV26 device sets bit 24 to 1 if the serial EEPROM is detected. If the serial EEPROM is present, the Bus_Info_Block is automatically loaded on system (hardware) reset. Major version of the OHCI. The TSB12LV26 device is compliant with the 1394 Open Host Controller Interface Specification; thus, this field reads 01h. Reserved. Bits 15-8 return 0s when read. Minor version of the OHCI. The TSB12LV26 device is compliant with the 1394 Open Host Controller Interface Specification; thus, this field reads 00h. 4-4 4.2 GUID ROM Register The GUID ROM register accesses the serial EEPROM and is applicable only if bit 24 (GUID_ROM) in the OHCI version register at OHCI offset 00h (see Section 4.1, OHCI Version Register) is set to 1. See Table 4-3 for a complete description of the register contents. Bit Name Type Default Bit Name Type Default R 0 R 0 R 0 R 0 R 0 R 0 R 0 RSU 0 15 R 0 14 R 0 13 R 0 12 R 0 11 R 0 10 RSU 0 9 31 30 29 28 27 26 25 24 R 0 8 R 0 23 RU X 7 R 0 22 RU X 6 R 0 21 RU X 5 R 0 20 RU X 4 R 0 19 RU X 3 R 0 18 RU X 2 R 0 17 RU X 1 R 0 16 RU X 0 R 0 GUID ROM GUID ROM Register: Type: Offset: Default: GUID ROM Read/Set/Update, Read/Update, Read-only 04h 00XX 0000h Table 4-3. GUID ROM Register Description BIT 31 FIELD NAME addrReset TYPE RSU DESCRIPTION Software sets bit 31 to 1 to reset the GUID ROM address to 0. When the TSB12LV26 device completes the reset, it clears this bit. The TSB12LV26 device does not automatically fill bits 23-16 (rdData field) with the 0th byte. Reserved. Bits 30-26 return 0s when read. A read of the currently addressed byte is started when bit 25 is set to 1. This bit is automatically cleared when the TSB12LV26 device completes the read of the currently addressed GUID ROM byte. Reserved. Bit 24 returns 0 when read. This field contains the data read from the GUID ROM. Reserved. Bits 15-0 return 0s when read. 30-26 25 24 23-16 15-0 RSVD rdStart RSVD rdData RSVD R RSU R RU R 4-5 4.3 Asynchronous Transmit Retries Register The asynchronous transmit retries register indicates the number of times the TSB12LV26 device attempts a retry for asynchronous DMA request transmit and for asynchronous physical and DMA response transmit. See Table 4-4 for a complete description of the register contents. Bit Name Type Default Bit Name Type Default R 0 R 0 R 0 R 0 R/W 0 R/W 0 R 0 15 R 0 14 R 0 13 R 0 12 R 0 11 R 0 10 31 30 29 28 27 26 25 R 0 9 R/W 0 24 R 0 8 R/W 0 23 R 0 7 R/W 0 22 R 0 6 R/W 0 21 R 0 5 R/W 0 20 R 0 4 R/W 0 19 R 0 3 R/W 0 18 R 0 2 R/W 0 17 R 0 1 R/W 0 16 R 0 0 R/W 0 Asynchronous transmit retries Asynchronous transmit retries Register: Type: Offset: Default: BIT 31-29 28-16 15-12 11-8 Asynchronous transmit retries Read/Write, Read-only 08h 0000 0000h Table 4-4. Asynchronous Transmit Retries Register Description TYPE R R R R/W DESCRIPTION The second limit field returns 0s when read, because outbound dual-phase retry is not implemented. The cycle limit field returns 0s when read, because outbound dual-phase retry is not implemented. Reserved. Bits 15-12 return 0s when read. The maxPhysRespRetries field tells the physical response unit how many times to attempt to retry the transmit operation for the response packet when a busy acknowledge or ack_data_error is received from the target node. The maxATRespRetries field tells the asynchronous transmit response unit how many times to attempt to retry the transmit operation for the response packet when a busy acknowledge or ack_data_error is received from the target node. The maxATReqRetries field tells the asynchronous transmit DMA request unit how many times to attempt to retry the transmit operation for the response packet when a busy acknowledge or ack_data_error is received from the target node. FIELD NAME secondLimit cycleLimit RSVD maxPhysRespRetries 7-4 maxATRespRetries R/W 3-0 maxATReqRetries R/W 4.4 CSR Data Register The CSR data register accesses the bus-management CSR registers from the host through compare-swap operations. This register contains the data to be stored in a CSR if the compare is successful. Bit Name Type Default Bit Name Type Default R X R X R X R X R X R X R X R X 15 R X 14 R X 13 R X 12 R X 11 R X 10 R X 9 31 30 29 28 27 26 25 24 R X 8 R X 23 R X 7 R X 22 R X 6 R X 21 R X 5 R X 20 R X 4 R X 19 R X 3 R X 18 R X 2 R X 17 R X 1 R X 16 R X 0 R X CSR data CSR data Register: Type: Offset: Default: CSR data Read-only 0Ch XXXX XXXXh 4-6 4.5 CSR Compare Register The CSR compare register accesses the bus-management CSR registers from the host through compare-swap operations. This register contains the data to be compared with the existing value of the CSR resource. Bit Name Type Default Bit Name Type Default R X R X R X R X R X R X R X R X 15 R X 14 R X 13 R X 12 R X 11 R X 10 R X 9 31 30 29 28 27 26 25 24 R X 8 R X 23 R X 7 R X 22 R X 6 R X 21 R X 5 R X 20 R X 4 R X 19 R X 3 R X 18 R X 2 R X 17 R X 1 R X 16 R X 0 R X CSR compare CSR compare Register: Type: Offset: Default: CSR compare Read-only 10h XXXX XXXXh 4.6 CSR Control Register The CSR control register accesses the bus-management CSR registers from the host through compare-swap operations. This register controls the compare-swap operation and selects the CSR resource. See Table 4-5 for a complete description of the register contents. Bit Name Type Default Bit Name Type Default R 0 R 0 R 0 R 0 R 0 R 0 R 0 RU 1 15 R 0 14 R 0 13 R 0 12 R 0 11 R 0 10 R 0 9 31 30 29 28 27 26 25 24 R 0 8 R 0 23 R 0 7 R 0 22 R 0 6 R 0 21 R 0 5 R 0 20 R 0 4 R 0 19 R 0 3 R 0 18 R 0 2 R 0 17 R 0 1 R/W X 16 R 0 0 R/W X CSR control CSR control Register: Type: Offset: Default: CSR control Read/Write, Read/Update, Read-only 14h 8000 000Xh Table 4-5. CSR Control Register Description BIT 31 30-2 1-0 FIELD NAME csrDone RSVD csrSel TYPE RU R R/W DESCRIPTION Bit 31 is set to 1 by the TSB12LV26 device when a compare-swap operation is complete. It is cleared whenever this register is written. Reserved. Bits 30-2 return 0s when read. This field selects the CSR resource as follows: 00 = BUS_MANAGER_ID 01 = BANDWIDTH_AVAILABLE 10 = CHANNELS_AVAILABLE_HI 11 = CHANNELS_AVAILABLE_LO 4-7 4.7 Configuration ROM Header Register The configuration ROM header register externally maps to the first quadlet of the 1394 configuration ROM, offset FFFF F000 0400h. See Table 4-6 for a complete description of the register contents. Bit Name Type Default Bit Name Type Default R/W X R/W X R/W X R/W X R/W X R/W X R/W 0 15 R/W 0 14 R/W 0 13 R/W 0 12 R/W 0 11 R/W 0 10 31 30 29 28 27 26 25 R/W 0 9 R/W X 24 R/W 0 8 R/W X 23 R/W 0 7 R/W X 22 R/W 0 6 R/W X 21 R/W 0 5 R/W X 20 R/W 0 4 R/W X 19 R/W 0 3 R/W X 18 R/W 0 2 R/W X 17 R/W 0 1 R/W X 16 R/W 0 0 R/W X Configuration ROM header Configuration ROM header Register: Type: Offset: Default: Configuration ROM header Read/Write 18h 0000 XXXXh Table 4-6. Configuration ROM Header Register Description BIT 31-24 23-16 15-0 FIELD NAME info_length crc_length rom_crc_value TYPE R/W R/W R/W DESCRIPTION IEEE 1394 bus-management field. Must be valid when bit 17 (linkEnable) in the host controller control register at OHCI offset 50h/54h (see Section 4.16, Host Controller Control Register) is set to 1. IEEE 1394 bus-management field. Must be valid when bit 17 (linkEnable) in the host controller control register at OHCI offset 50h/54h (see Section 4.16, Host Controller Control Register) is set to 1. IEEE 1394 bus-management field. Must be valid at any time bit 17 (linkEnable) in the host controller control register at OHCI offset 50h/54h (see Section 4.16, Host Controller Control Register) is set to 1. The reset value is undefined if no serial EEPROM is present. If a serial EEPROM is present, this field is loaded from the serial EEPROM. 4.8 Bus Identification Register The bus identification register externally maps to the first quadlet in the Bus_Info_Block and contains the constant 3133 3934h, which is the ASCII value of 1394. Bit Name Type Default Bit Name Type Default R 0 R 0 R 1 R 1 R 1 R 0 R 0 R 0 15 R 0 14 R 1 13 R 1 12 R 0 11 R 0 10 R 0 9 31 30 29 28 27 26 25 24 R 1 8 R 1 23 R 0 7 R 0 22 R 0 6 R 0 21 R 1 5 R 1 20 R 1 4 R 1 19 R 0 3 R 0 18 R 0 2 R 1 17 R 1 1 R 0 16 R 1 0 R 0 Bus identification Bus identification Register: Type: Offset: Default: Bus identification Read-only 1Ch 3133 3934h 4-8 4.9 Bus Options Register The bus options register externally maps to the second quadlet of the Bus_Info_Block. See Table 4-7 for a complete description of the register contents. Bit Name Type Default Bit Name Type Default R/W 1 R/W 0 R/W 1 R/W 0 R 0 R 0 R 0 R/W X 15 R/W X 14 R/W X 13 R/W X 12 R/W 0 11 R 0 10 R 0 9 31 30 29 28 27 26 25 24 R 0 8 R 0 23 R/W X 7 R/W X 22 R/W X 6 R/W X 21 R/W X 5 R 0 20 R/W X 4 R 0 19 R/W X 3 R 0 18 R/W X 2 R 0 17 R/W X 1 R 1 16 R/W X 0 R 0 Bus options Bus options Register: Type: Offset: Default: BIT 31 FIELD NAME irmc Bus options Read/Write, Read-only 20h X0XX A0X2h Table 4-7. Bus Options Register Description TYPE R/W DESCRIPTION Isochronous resource-manager capable. IEEE 1394 bus-management field. Must be valid when bit 17 (linkEnable) in the host controller control register at OHCI offset 50h/54h (see Section 4.16, Host Controller Control Register) is set to 1. Cycle master capable. IEEE 1394 bus-management field. Must be valid when bit 17 (linkEnable) in the host controller control register at OHCI offset 50h/54h (see Section 4.16, Host Controller Control Register) is set to 1. Isochronous support capable. IEEE 1394 bus-management field. Must be valid when bit 17 (linkEnable) in the host controller control register at OHCI offset 50h/54h (see Section 4.16, Host Controller Control Register) is set to 1. Bus manager capable. IEEE 1394 bus-management field. Must be valid when bit 17 (linkEnable) in the host controller control register at OHCI offset 50h/54h (see Section 4.16, Host Controller Control Register) is set to 1. Power-management capable. IEEE 1394 bus-management field. When bit 27 is set to 1, this indicates that the node is power-management capable. Must be valid when bit 17 (linkEnable) in the host controller control register at OHCI offset 50h/54h (see Section 4.16, Host Controller Control Register) is set to 1. Reserved. Bits 26-24 return 0s when read. Cycle master clock accuracy, in parts per million. IEEE 1394 bus-management field. Must be valid when bit 17 (linkEnable) in the host controller control register at OHCI offset 50h/54h (see Section 4.16, Host Controller Control Register) is set to 1. Maximum request. IEEE 1394 bus-management field. Hardware initializes this field to indicate the maximum number of bytes in a block request packet that is supported by the implementation. This value, max_rec_bytes, must be 512 or greater, and is calculated by 2^(max_rec + 1). Software may change this field; however, this field must be valid at any time bit 17 (linkEnable) in the host controller control register at OHCI offset 50h/54h (see Section 4.16, Host Controller Control Register) is set to 1. A received block write request packet with a length greater than max_rec_bytes may generate an ack_type_error. This field is not affected by a software reset, and defaults to a value indicating 2048 bytes on a system (hardware) reset. Reserved. Bits 11-8 return 0s when read. Generation counter. This field is incremented if any portion of the configuration ROM has been incremented since the prior bus reset. Reserved. Bits 5-3 return 0s when read. Link speed. This field returns 010, indicating that the link speeds of 100M bits/s, 200M bits/s, and 400M bits/s are supported. 30 cmc R/W 29 isc R/W 28 bmc R/W 27 pmc R/W 26-24 23-16 RSVD cyc_clk_acc R R/W 15-12 max_rec R/W 11-8 7-6 5-3 2-0 RSVD g RSVD Lnk_spd R R/W R R 4-9 4.10 GUID High Register The GUID high register represents the upper quadlet in a 64-bit global unique ID (GUID) which maps to the third quadlet in the Bus_Info_Block. This register contains node_vendor_ID and chip_ID_hi fields. This register initializes to 0s on a system (hardware) reset, which is an illegal GUID value. If a serial EEPROM is detected, the contents of this register are loaded through the serial EEPROM interface after a PCI_RST. At that point, the contents of this register cannot be changed. If no serial EEPROM is detected, the contents of this register are loaded by the BIOS after a PCI_RST. At that point, the contents of this register cannot be changed. Bit Name Type Default Bit Name Type Default R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 15 R 0 14 R 0 13 R 0 12 R 0 11 R 0 10 R 0 9 31 30 29 28 27 26 25 24 R 0 8 R 0 23 R 0 7 R 0 22 R 0 6 R 0 21 R 0 5 R 0 20 R 0 4 R 0 19 R 0 3 R 0 18 R 0 2 R 0 17 R 0 1 R 0 16 R 0 0 R 0 GUID high GUID high Register: Type: Offset: Default: GUID high Read-only 24h 0000 0000h 4.11 GUID Low Register The GUID low register represents the lower quadlet in a 64-bit global unique ID (GUID) which maps to chip_ID_lo in the Bus_Info_Block. This register initializes to 0s on a system (hardware) reset and behaves identically to the GUID high register at OHCI offset 24h (see Section 4.10, GUID High Register). Bit Name Type Default Bit Name Type Default R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 15 R 0 14 R 0 13 R 0 12 R 0 11 R 0 10 R 0 9 31 30 29 28 27 26 25 24 R 0 8 R 0 23 R 0 7 R 0 22 R 0 6 R 0 21 R 0 5 R 0 20 R 0 4 R 0 19 R 0 3 R 0 18 R 0 2 R 0 17 R 0 1 R 0 16 R 0 0 R 0 GUID low GUID low Register: Type: Offset: Default: GUID low Read-only 28h 0000 0000h 4-10 4.12 Configuration ROM Mapping Register The configuration ROM mapping register contains the start address within system memory that maps to the start address of 1394 configuration ROM for this node. See Table 4-8 for a complete description of the register contents. Bit Name Type Default Bit Name Type Default R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 R/W 0 14 R/W 0 13 R/W 0 12 R/W 0 11 R/W 0 10 31 30 29 28 27 26 25 R/W 0 9 R 0 24 R/W 0 8 R 0 23 R/W 0 7 R 0 22 R/W 0 6 R 0 21 R/W 0 5 R 0 20 R/W 0 4 R 0 19 R/W 0 3 R 0 18 R/W 0 2 R 0 17 R/W 0 1 R 0 16 R/W 0 0 R 0 Configuration ROM mapping Configuration ROM mapping Register: Type: Offset: Default: Configuration ROM mapping Read/Write, Read-only 34h 0000 0000h Table 4-8. Configuration ROM Mapping Register Description BIT 31-10 FIELD NAME configROMaddr TYPE R/W DESCRIPTION If a quadlet read request to 1394 offset FFFF F000 0400h through offset FFFF F000 07FFh is received, the low-order 10 bits of the offset are added to this register to determine the host memory address of the read request. Reserved. Bits 9-0 return 0s when read. 9-0 RSVD R 4.13 Posted Write Address Low Register The posted write address low register communicates error information if a write request is posted and an error occurs while writing the posted data packet. See Table 4-9 for a complete description of the register contents. Bit Name Type Default Bit Name Type Default RU X RU X RU X RU X RU X RU X RU X 15 RU X 14 RU X 13 RU X 12 RU X 11 RU X 10 31 30 29 28 27 26 25 RU X 9 RU X 24 RU X 8 RU X 23 RU X 7 RU X 22 RU X 6 RU X 21 RU X 5 RU X 20 RU X 4 RU X 19 RU X 3 RU X 18 RU X 2 RU X 17 RU X 1 RU X 16 RU X 0 RU X Posted write address low Posted write address low Register: Type: Offset: Default: Posted write address low Read/Update 38h XXXX XXXXh Table 4-9. Posted Write Address Low Register Description BIT 31-0 FIELD NAME offsetLo TYPE RU DESCRIPTION The lower 32 bits of the 1394 destination offset of the write request that failed. 4-11 4.14 Posted Write Address High Register The posted write address high register communicates error information if a write request is posted and an error occurs while writing the posted data packet. See Table 4-10 for a complete description of the register contents. Bit Name Type Default Bit Name Type Default RU X RU X RU X RU X RU X RU X RU X 15 RU X 14 RU X 13 RU X 12 RU X 11 RU X 10 31 30 29 28 27 26 25 RU X 9 RU X 24 RU X 8 RU X 23 RU X 7 RU X 22 RU X 6 RU X 21 RU X 5 RU X 20 RU X 4 RU X 19 RU X 3 RU X 18 RU X 2 RU X 17 RU X 1 RU X 16 RU X 0 RU X Posted write address high Posted write address high Register: Type: Offset: Default: Posted write address high Read/Update 3Ch XXXX XXXXh Table 4-10. Posted Write Address High Register Description BIT 31-16 15-0 FIELD NAME sourceID offsetHi TYPE RU RU DESCRIPTION This field is the 10-bit bus number (bits 31-22) and 6-bit node number (bits 21-16) of the node that issued the write request that failed. The upper 16 bits of the 1394 destination offset of the write request that failed. 4.15 Vendor ID Register The vendor ID register holds the company ID of an organization that specifies any vendor-unique registers. The TSB12LV26 device does not implement Texas Instruments unique behavior with regards to OHCI. Thus, this register is read-only and returns 0s when read. Bit Name Type Default Bit Name Type Default R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 15 R 0 14 R 0 13 R 0 12 R 0 11 R 0 10 R 0 9 31 30 29 28 27 26 25 24 R 0 8 R 0 23 R 0 7 R 0 22 R 0 6 R 0 21 R 0 5 R 0 20 R 0 4 R 0 19 R 0 3 R 0 18 R 0 2 R 0 17 R 0 1 R 0 16 R 0 0 R 0 Vendor ID Vendor ID Register: Type: Offset: Default: Vendor ID Read-only 40h 0000 0000h 4-12 4.16 Host Controller Control Register The host controller control set/clear register pair provides flags for controlling the TSB12LV26 device. See Table 4-11 for a complete description of the register contents. Bit Name Type Default Bit Name Type Default R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 15 RSC X 14 R 0 13 R 0 12 R 0 11 R 0 10 R 0 9 31 30 29 28 27 26 25 24 R 0 8 R 0 23 RC 0 7 R 0 22 RSC 0 6 R 0 21 R 0 5 R 0 20 R 0 4 R 0 19 RSC 0 3 R 0 18 RSC X 2 R 0 17 RSC 0 1 R 0 16 RSCU 0 0 R 0 Host controller control Host controller control Register: Type: Offset: Default: Host controller control Read/Set/Clear/Update, Read/Set/Clear, Read/Clear, Read-only 50h set register 54h clear register X00X 0000h Table 4-11. Host Controller Control Register Description BIT 31 30 29-24 23 FIELD NAME RSVD noByteSwapData RSVD programPhyEnable TYPE R RSC R RC Reserved. Bit 31 returns 0 when read. DESCRIPTION Bit 30 controls whether physical accesses to locations outside the TSB12LV26 device itself, as well as any other DMA data accesses, are swapped. Reserved. Bits 29-24 return 0s when read. Bit 23 informs upper-level software that lower-level software has consistently configured the IEEE 1394a-2000 enhancements in the link and PHY devices. When this bit is set to 1, generic software such as the OHCI driver is responsible for configuring IEEE 1394a-2000 enhancements in the PHY device and bit 22 (aPhyEnhanceEnable) in the TSB12LV26 device. When this bit is cleared to 0, the generic software may not modify the IEEE 1394a-2000 enhancements in the TSB12LV26 or PHY device and cannot interpret the setting of bit 22 (aPhyEnhanceEnable). This bit is initialized from serial EEPROM. When bits 23 (programPhyEnable) and 17 (linkEnable) are 1, the OHCI driver can set bit 22 to 1 to use all IEEE 1394a-2000 enhancements. When bit 23 (programPhyEnable) is cleared to 0, the software does not change PHY enhancements or this bit. Reserved. Bits 21 and 20 return 0s when read. Bit 19 controls the link power status. Software must set this bit to 1 to permit link-PHY communication. A 0 prevents link-PHY communication. The OHCI-link is divided into two clock domains (PCI_CLK and PHY_SCLK). If software tries to access any register in the PHY_SCLK domain while the PHY_SCLK is disabled, a target abort is issued by the link. This problem can be avoided by setting bit 4 (DIS_TGT_ABT) to 1 in the miscellaneous configuration register at offset F0h in the PCI configuration space (see Section 3.20, Miscellaneous Configuration Register). This allows the link to respond to these types of requests by returning all Fs (hex). It is recommended that this bit be set to 1 and is programmable via the ROM or BIOS. OHCI registers at offsets DCh-F0h and 100h-11Ch are in the PHY_SCLK domain. After setting LPS software must wait approximately 10 ms before attempting to access any of the OHCI registers. This gives the PHY_SCLK time to stabilize. 22 aPhyEnhanceEnable RSC 21-20 19 RSVD LPS R RSC 18 postedWriteEnable RSC Bit 18 enables (1) or disables (0) posted writes. Software must change this bit only when bit 17 (linkEnable) is 0. 4-13 Table 4-11. Host Controller Control Register Description (Continued) BIT 17 FIELD NAME linkEnable TYPE RSC DESCRIPTION Bit 17 is cleared to 0 by either a system (hardware) or software reset. Software must set this bit to 1 when the system is ready to begin operation and then force a bus reset. This bit is necessary to keep other nodes from sending transactions before the local system is ready. When this bit is cleared, the TSB12LV26 device is logically and immediately disconnected from the 1394 bus, no packets are received or processed, nor are packets transmitted. When bit 16 is set to 1, all TSB12LV26 device states are reset, all FIFOs are flushed, and all OHCI registers are set to their system (hardware) reset values, unless otherwise specified. PCI registers are not affected by this bit. This bit remains set to 1 while the software reset is in progress and reverts back to 0 when the reset has completed. Reserved. Bits 15-0 return 0s when read. 16 SoftReset RSCU 15-0 RSVD R 4.17 Self-ID Buffer Pointer Register The self-ID buffer pointer register points to the 2K-byte aligned base address of the buffer in host memory where the self-ID packets are stored during bus initialization. Bits 31-11 are read/write accessible. Bits 10-0 are reserved, and return 0s when read. Bit Name Type Default Bit Name Type Default R/W X R/W X R/W X R/W X R/W X R 0 R 0 R/W X 15 R/W X 14 R/W X 13 R/W X 12 R/W X 11 R/W X 10 X 9 31 30 29 28 27 26 25 R/W 24 R/W X 8 R 0 23 R/W X 7 R 0 22 R/W X 6 R 0 21 R/W X 5 R 0 20 R/W X 4 R 0 19 R/W X 3 R 0 18 R/W X 2 R 0 17 R/W X 1 R 0 16 R/W X 0 R 0 Self-ID buffer pointer Self-ID buffer pointer Register: Type: Offset: Default: Self ID-buffer pointer Read/Write, Read-only 64h XXXX XX00h 4-14 4.18 Self-ID Count Register The self-ID count register keeps a count of the number of times the bus self-ID process has occurred, flags self-ID packet errors, and keeps a count of the self-ID data in the self-ID buffer. See Table 4-12 for a complete description of the register contents. Bit Name Type Default Bit Name Type Default R 0 R 0 R 0 R 0 R 0 RU 0 RU 0 RU X 15 R 0 14 R 0 13 R 0 12 R 0 11 R 0 10 R 0 9 31 30 29 28 27 26 25 24 R 0 8 RU 0 23 RU X 7 RU 0 22 RU X 6 RU 0 21 RU X 5 RU 0 20 RU X 4 RU 0 19 RU X 3 RU 0 18 RU X 2 RU 0 17 RU X 1 R 0 16 RU X 0 R 0 Self-ID count Self-ID count Register: Type: Offset: Default: Self-ID count Read/Update, Read-only 68h X0XX 0000h Table 4-12. Self-ID Count Register Description BIT 31 FIELD NAME selfIDError TYPE RU DESCRIPTION When bit 31 is set to 1, an error was detected during the most recent self-ID packet reception. The contents of the self-ID buffer are undefined. This bit is cleared after a self-ID reception in which no errors are detected. Note that an error can be a hardware error or a host bus write error. Reserved. Bits 30-24 return 0s when read. The value in this field increments each time a bus reset is detected. This field rolls over to 0 after reaching 255. Reserved. Bits 15-11 return 0s when read. This field indicates the number of quadlets that have been written into the self-ID buffer for the current bits 23-16 (selfIDGeneration field). This includes the header quadlet and the self-ID data. This field is cleared to 0 when the self-ID reception begins. Reserved. Bits 1 and 0 return 0s when read. 30-24 23-16 15-11 10-2 RSVD selfIDGeneration RSVD selfIDSize R RU R RU 1-0 RSVD R 4-15 4.19 Isochronous Receive Channel Mask High Register The isochronous receive channel mask high set/clear register enables packet receives from the upper 32 isochronous data channels. A read from either the set register or clear register returns the content of the isochronous receive channel mask high register. See Table 4-13 for a complete description of the register contents. Bit Name Type Default Bit Name Type Default RSC X RSC X RSC X RSC X RSC X RSC X 15 RSC X 14 RSC X 13 RSC X 12 RSC X 11 31 30 29 28 27 26 RSC X 10 RSC X 25 RSC X 9 RSC X 24 RSC X 8 RSC X 23 RSC X 7 RSC X 22 RSC X 6 RSC X 21 RSC X 5 RSC X 20 RSC X 4 RSC X 19 RSC X 3 RSC X 18 RSC X 2 RSC X 17 RSC X 1 RSC X 16 RSC X 0 RSC X Isochronous receive channel mask high Isochronous receive channel mask high Register: Type: Offset: Default: Isochronous receive channel mask high Read/Set/Clear 70h set register 74h clear register XXXX XXXXh Table 4-13. Isochronous Receive Channel Mask High Register Description BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 FIELD NAME isoChannel63 isoChannel62 isoChannel61 isoChannel60 isoChannel59 isoChannel58 isoChannel57 isoChannel56 isoChannel55 isoChannel54 isoChannel53 isoChannel52 isoChannel51 isoChannel50 isoChannel49 isoChannel48 isoChannel47 isoChannel46 isoChannel45 isoChannel44 isoChannel43 isoChannel42 isoChannel41 isoChannel40 isoChannel39 TYPE RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC DESCRIPTION When bit 31 is set to 1, the TSB12LV26 device is enabled to receive from isochronous channel number 63. When bit 30 is set to 1, the TSB12LV26 device is enabled to receive from isochronous channel number 62. When bit 29 is set to 1, the TSB12LV26 device is enabled to receive from isochronous channel number 61. When bit 28 is set to 1, the TSB12LV26 device is enabled to receive from isochronous channel number 60. When bit 27 is set to 1, the TSB12LV26 device is enabled to receive from isochronous channel number 59. When bit 26 is set to 1, the TSB12LV26 device is enabled to receive from isochronous channel number 58. When bit 25 is set to 1, the TSB12LV26 device is enabled to receive from isochronous channel number 57. When bit 24 is set to 1, the TSB12LV26 device is enabled to receive from isochronous channel number 56. When bit 23 is set to 1, the TSB12LV26 device is enabled to receive from isochronous channel number 55. When bit 22 is set to 1, the TSB12LV26 device is enabled to receive from isochronous channel number 54. When bit 21 is set to 1, the TSB12LV26 device is enabled to receive from isochronous channel number 53. When bit 20 is set to 1, the TSB12LV26 device is enabled to receive from isochronous channel number 52. When bit 19 is set to 1, the TSB12LV26 device is enabled to receive from isochronous channel number 51. When bit 18 is set to 1, the TSB12LV26 device is enabled to receive from isochronous channel number 50. When bit 17 is set to 1, the TSB12LV26 device is enabled to receive from isochronous channel number 49. When bit 16 is set to 1, the TSB12LV26 device is enabled to receive from isochronous channel number 48. When bit 15 is set to 1, the TSB12LV26 device is enabled to receive from isochronous channel number 47. When bit 14 is set to 1, the TSB12LV26 device is enabled to receive from isochronous channel number 46. When bit 13 is set to 1, the TSB12LV26 device is enabled to receive from isochronous channel number 45. When bit 12 is set to 1, the TSB12LV26 device is enabled to receive from isochronous channel number 44. When bit 11 is set to 1, the TSB12LV26 device is enabled to receive from isochronous channel number 43. When bit 10 is set to 1, the TSB12LV26 device is enabled to receive from isochronous channel number 42. When bit 9 is set to 1, the TSB12LV26 device is enabled to receive from isochronous channel number 41. When bit 8 is set to 1, the TSB12LV26 device is enabled to receive from isochronous channel number 40. When bit 7 is set to 1, the TSB12LV26 device is enabled to receive from isochronous channel number 39. 4-16 Table 4-13. Isochronous Receive Channel Mask High Register Description (Continued) BIT 6 5 4 3 2 1 0 FIELD NAME isoChannel38 isoChannel37 isoChannel36 isoChannel35 isoChannel34 isoChannel33 isoChannel32 TYPE RSC RSC RSC RSC RSC RSC RSC DESCRIPTION When bit 6 is set to 1, the TSB12LV26 device is enabled to receive from isochronous channel number 38. When bit 5 is set to 1, the TSB12LV26 device is enabled to receive from isochronous channel number 37. When bit 4 is set to 1, the TSB12LV26 device is enabled to receive from isochronous channel number 36. When bit 3 is set to 1, the TSB12LV26 device is enabled to receive from isochronous channel number 35. When bit 2 is set to 1, the TSB12LV26 device is enabled to receive from isochronous channel number 34. When bit 1 is set to 1, the TSB12LV26 device is enabled to receive from isochronous channel number 33. When bit 0 is set to 1, the TSB12LV26 device is enabled to receive from isochronous channel number 32. 4.20 Isochronous Receive Channel Mask Low Register The isochronous receive channel mask low set/clear register enables packet receives from the lower 32 isochronous data channels. See Table 4-14 for a complete description of the register contents. Bit Name Type Default Bit Name Type Default RSC X RSC X RSC X RSC X RSC X X RSC X 15 RSC X 14 RSC X 13 RSC X 12 RSC X 11 X 10 RSC 31 30 29 28 27 26 RSC 25 RSC X 9 RSC X 24 RSC X 8 RSC X 23 RSC X 7 RSC X 22 RSC X 6 RSC X 21 RSC X 5 RSC X 20 RSC X 4 RSC X 19 RSC X 3 RSC X 18 RSC X 2 RSC X 17 RSC X 1 RSC X 16 RSC X 0 RSC X Isochronous receive channel mask low Isochronous receive channel mask low Register: Type: Offset: Default: Isochronous receive channel mask low Read/Set/Clear 78h set register 7Ch clear register XXXX XXXXh Table 4-14. Isochronous Receive Channel Mask Low Register Description BIT 31 30 29-2 1 0 FIELD NAME isoChannel31 isoChannel30 isoChanneln isoChannel1 isoChannel0 TYPE RSC RSC RSC RSC RSC DESCRIPTION When bit 31 is set to 1, the TSB12LV26 device is enabled to receive from isochronous channel number 31. When bit 30 is set to 1, the TSB12LV26 device is enabled to receive from isochronous channel number 30. Bits 29 through 2 (isoChanneln, where n = 29, 28, 27, ..., 2) follow the same pattern as bits 31 and 30. When bit 1 is set to 1, the TSB12LV26 device is enabled to receive from isochronous channel number 1. When bit 0 is set to 1, the TSB12LV26 device is enabled to receive from isochronous channel number 0. 4-17 4.21 Interrupt Event Register The interrupt event set/clear register reflects the state of the various TSB12LV26 interrupt sources. The interrupt bits are set to 1 by an asserting edge of the corresponding interrupt signal or by writing a 1 in the corresponding bit in the set register. The only mechanism to clear a bit in this register is to write a 1 to the corresponding bit in the clear register. This register is fully compliant with the 1394 Open Host Controller Interface Specification, and the TSB12LV26 device adds a vendor-specific interrupt function to bit 30. When the interrupt event register is read, the return value is the bit-wise AND function of the interrupt event and interrupt mask registers. See Table 4-15 for a complete description of the register contents. Bit Name Type Default Bit Name Type Default R 0 R 0 R 0 R 0 R 0 R 0 RSCU X X R 0 15 RSC X 14 R 0 13 R 0 12 R 0 11 RSCU X 10 RSCU X 9 X 8 RSCU 31 30 29 28 27 26 25 24 RSCU 23 RSCU X 7 Interrupt event RU X RU X RSCU X RSCU X RSCU X RSCU X RSCU X RSCU X 22 RSCU X 6 21 RSCU X 5 20 RSCU X 4 19 RSCU X 3 18 R 0 2 17 RSCU X 1 16 RSCU X 0 Interrupt event Register: Type: Offset: Default: Interrupt event Read/Set/Clear/Update, Read/Set/Clear, Read/Update, Read-only 80h set register 84h clear register [returns the contents of the interrupt event register bit-wise ANDed with the interrupt mask register when read] XXXX 0XXXh Table 4-15. Interrupt Event Register Description BIT 31 30 FIELD NAME RSVD vendorSpecific TYPE R RSC Reserved. Bit 31 returns 0 when read. DESCRIPTION This vendor-specific interrupt event is reported when either of the general-purpose interrupts are asserted. The general-purpose interrupts are enabled by setting the corresponding bits INT3_EN and INT_2EN (bits 31 and 23, respectively) to 1 in the GPIO control register at offset FCh in the PCI configuration space (see Section 3.23, GPIO Control Register). Reserved. Bits 29-27 return 0s when read. The TSB12LV26 device has received a PHY register data byte which can be read from bits 23-16 in the PHY layer control register at OHCI offset ECh (see Section 4.30, PHY Layer Control Register). If bit 21 (cycleMaster) in the link control register at OHCI offset E0h/E4h (see Section 4.28, Link Control Register) is set to 1, this indicates that over 125 s have elapsed between the start of sending a cycle start packet and the end of a subaction gap. Bit 21 (cycleMaster) in the link control register is cleared by this event. This event occurs when the TSB12LV26 device encounters any error that forces it to stop operations on any or all of its subunits, for example, when a DMA context sets its dead bit to 1. While bit 24 is set to 1, all normal interrupts for the context(s) that caused this interrupt are blocked from being set to 1. A cycle start was received that had values for the cycleSeconds and cycleCount fields that are different from the values in bits 31-25 (cycleSeconds field) and bits 24-12 (cycleCount field) in the isochronous cycle timer register at OHCI offset F0h (see Section 4.31, Isochronous Cycle Timer Register). A lost cycle is indicated when no cycle_start packet is sent or received between two successive cycleSynch events. A lost cycle can be predicted when a cycle_start packet does not immediately follow the first subaction gap after the cycleSynch event or if an arbitration reset gap is detected after a cycleSynch event without an intervening cycle start. Bit 22 may be set to 1 either when a lost cycle occurs or when logic predicts that one will occur. Indicates that the 7th bit of the cycle second counter has changed. 29-27 26 25 RSVD phyRegRcvd cycleTooLong R RSCU RSCU 24 unrecoverableError RSCU 23 cycleInconsistent RSCU 22 cycleLost RSCU 21 cycle64Seconds RSCU 4-18 Table 4-15. Interrupt Event Register Description (Continued) BIT 20 19 18 17 16 15-10 9 8 7 FIELD NAME cycleSynch phy RSVD busReset selfIDcomplete RSVD lockRespErr postedWriteErr isochRx TYPE RSCU RSCU R RSCU RSCU R RSCU RSCU RU DESCRIPTION Indicates that a new isochronous cycle has started. Bit 20 is set to 1 when the low-order bit of the cycle count toggles. Indicates that the PHY device requests an interrupt through a status transfer. Reserved. Bit 18 returns 0 when read. Indicates that the PHY device has entered bus reset mode. A self-ID packet stream has been received. It is generated at the end of the bus initialization process. Bit 16 is turned off simultaneously when bit 17 (busReset) is turned on. Reserved. Bits 15-10 return 0s when read. Indicates that the TSB12LV26 device sent a lock response for a lock request to a serial bus register, but did not receive an ack_complete. Indicates that a host bus error occurred while the TSB12LV26 device was trying to write a 1394 write request, which had already been given an ack_complete, into system memory. Isochronous receive DMA interrupt. Indicates that one or more isochronous receive contexts have generated an interrupt. This is not a latched event; it is the logical OR of all bits in the isochronous receive interrupt event register at OHCI offset A0h/A4h (see Section 4.25, Isochronous Receive Interrupt Event Register) and the isochronous receive interrupt mask register at OHCI offset A8h/ACh (see Section 4.26, Isochronous Receive Interrupt Mask Register). The isochronous receive interrupt event register indicates which contexts have been interrupted. Isochronous transmit DMA interrupt. Indicates that one or more isochronous transmit contexts have generated an interrupt. This is not a latched event; it is the logical OR of all bits in the isochronous transmit interrupt event register at OHCI offset 90h/94h (see Section 4.23, Isochronous Transmit Interrupt Event Register) and the isochronous transmit interrupt mask register at OHCI offset 98h/9Ch (see Section 4.24, Isochronous Transmit Interrupt Mask Register). The isochronous transmit interrupt event register indicates which contexts have been interrupted. Indicates that a packet was sent to an asynchronous receive response context buffer and the descriptor xferStatus and resCount fields have been updated. Indicates that a packet was sent to an asynchronous receive request context buffer and the descriptor xferStatus and resCount fields have been updated. Asynchronous receive response DMA interrupt. Bit 3 is conditionally set to 1 upon completion of an ARRS DMA context command descriptor. Asynchronous receive request DMA interrupt. Bit 2 is conditionally set to 1 upon completion of an ARRQ DMA context command descriptor. Asynchronous response transmit DMA interrupt. Bit 1 is conditionally set to 1 upon completion of an ATRS DMA command. Asynchronous request transmit DMA interrupt. Bit 0 is conditionally set to 1 upon completion of an ATRQ DMA command. 6 isochTx RU 5 4 3 2 1 0 RSPkt RQPkt ARRS ARRQ respTxComplete reqTxComplete RSCU RSCU RSCU RSCU RSCU RSCU 4-19 4.22 Interrupt Mask Register The interrupt mask set/clear register enables the various TSB12LV26 interrupt sources. Reads from either the set register or the clear register always return the contents of the interrupt mask register. In all cases except masterIntEnable (bit 31) and VendorSpecific (bit 30), the enables for each interrupt event align with the interrupt event register bits detailed in Table 4-15. See Table 4-16 for a description of bits 31 and 30. This register is fully compliant with the 1394 Open Host Controller Interface Specification, and the TSB12LV26 device adds a vendor-specific interrupt function to bit 30. Bit Name Type Default Bit Name Type Default R 0 R 0 R 0 R 0 R 0 R 0 RSC X RSCU X 15 RSC X 14 R 0 13 R 0 12 R 0 11 RSC X 10 RSC X 9 31 30 29 28 27 26 25 24 RSC X 8 RSC X 23 RSC X 7 RSC X 22 RSC X 6 RSC X 21 RSC X 5 RSC X 20 RSC X 4 RSC X 19 RSC X 3 RSC X 18 R 0 2 RSC X 17 RSC X 1 RSC X 16 RSC X 0 RSC X Interrupt mask Interrupt mask Register: Type: Offset: Default: Interrupt mask Read/Set/Clear/Update, Read/Set/Clear, Read/Update, Read-only 88h set register 8Ch clear register XXXX 0XXXh Table 4-16. Interrupt Mask Register Description BIT 31 FIELD NAME masterIntEnable TYPE RSCU DESCRIPTION Master interrupt enable. If bit 31 is set to 1, external interrupts are generated in accordance with the interrupt mask register. If this bit is cleared, external interrupts are not generated regardless of the interrupt mask register settings. When this bit and bit 30 (vendorSpecific) in the interrupt event register at OHCI offset 80h/84h (see Section 4.21, Interrupt Event Register) are set to 1, this vendor-specific interrupt mask enables interrupt generation. Reserved. Bits 29-27 return 0s when read. When this bit and bit 26 (phyRegRcvd) in the interrupt event register at OHCI offset 80h/84h (see Section 4.21, Interrupt Event Register) are set to 1, this PHY-register interrupt mask enables interrupt generation. When this bit and bit 25 (cycleTooLong) in the interrupt event register at OHCI offset 80h/84h (see Section 4.21, Interrupt Event Register) are set to 1, this cycle-too-long interrupt mask enables interrupt generation. When this bit and bit 24 (unrecoverableError) in the interrupt event register at OHCI offset 80h/84h (see Section 4.21, Interrupt Event Register) are set to 1, this unrecoverable-error interrupt mask enables interrupt generation. When this bit and bit 23 (cycleInconsistent) in the interrupt event register at OHCI offset 80h/84h (see Section 4.21, Interrupt Event Register) are set to 1, this inconsistent-cycle interrupt mask enables interrupt generation. When this bit and bit 22 (cycleLost) in the interrupt event register at OHCI offset 80h/84h (see Section 4.21, Interrupt Event Register) are set to 1, this lost-cycle interrupt mask enables interrupt generation. When this bit and bit 21 (cycle64Seconds) in the interrupt event register at OHCI offset 80h/84h (see Section 4.21, Interrupt Event Register) are set to 1, this 64-second-cycle interrupt mask enables interrupt generation. When this bit and bit 20 (cycleSynch) in the interrupt event register at OHCI offset 80h/84h (see Section 4.21, Interrupt Event Register) are set to 1, this isochronous-cycle interrupt mask enables interrupt generation. 30 vendorSpecific RSC 29-27 26 RSVD phyRegRcvd R RSC 25 cycleTooLong RSC 24 unrecoverableError RSC 23 cycleInconsistent RSC 22 cycleLost RSC 21 cycle64Seconds RSC 20 cycleSynch RSC 4-20 Table 4-16. Interrupt Mask Register Description (Continued) BIT 19 FIELD NAME phy TYPE RSC DESCRIPTION When this bit and bit 19 (phy) in the interrupt event register at OHCI offset 80h/84h (see Section 4.21, Interrupt Event Register) are set to 1, this PHY-status-transfer interrupt mask enables interrupt generation. Reserved. Bit 18 returns 0 when read. When this bit and bit 17 (busReset) in the interrupt event register at OHCI offset 80h/84h (see Section 4.21, Interrupt Event Register) are set to 1, this bus-reset interrupt mask enables interrupt generation. When this bit and bit 16 (selfIDcomplete) in the interrupt event register at OHCI offset 80h/84h (see Section 4.21, Interrupt Event Register) are set to 1, this self-ID-complete interrupt mask enables interrupt generation. Reserved. Bits 15-10 return 0s when read. When this bit and bit 9 (lockRespErr) in the interrupt event register at OHCI offset 80h/84h (see Section 4.21, Interrupt Event Register) are set to 1, this lock-response-error interrupt mask enables interrupt generation. When this bit and bit 8 (postedWriteErr) in the interrupt event register at OHCI offset 80h/84h (see Section 4.21, Interrupt Event Register) are set to 1, this posted-write-error interrupt mask enables interrupt generation. When this bit and bit 7 (isochRx) in the interrupt event register at OHCI offset 80h/84h (see Section 4.21, Interrupt Event Register) are set to 1, this isochronous-receive-DMA interrupt mask enables interrupt generation. When this bit and bit 6 (isochTx) in the interrupt event register at OHCI offset 80h/84h (see Section 4.21, Interrupt Event Register) are set to 1, this isochronous-transmit-DMA interrupt mask enables interrupt generation. When this bit and bit 5 (RSPkt) in the interrupt event register at OHCI offset 80h/84h (see Section 4.21, Interrupt Event Register) are set to 1, this receive-response-packet interrupt mask enables interrupt generation. When this bit and bit 4 (RQPkt) in the interrupt event register at OHCI offset 80h/84h (see Section 4.21, Interrupt Event Register) are set to 1, this receive-request-packet interrupt mask enables interrupt generation. When this bit and bit 3 (ARRS) in the interrupt event register at OHCI offset 80h/84h (see Section 4.21, Interrupt Event Register) are set to 1, this asynchronous-receive-response-DMA interrupt mask enables interrupt generation. When this bit and bit 2 (ARRQ) in the interrupt event register at OHCI offset 80h/84h (see Section 4.21, Interrupt Event Register) are set to 1, this asynchronous-receive-request-DMA interrupt mask enables interrupt generation. When this bit and bit 1 (respTxComplete) in the interrupt event register at OHCI offset 80h/84h (see Section 4.21, Interrupt Event Register) are set to 1, this response-transmit-complete interrupt mask enables interrupt generation. When this bit and bit 0 (reqTxComplete) in the interrupt event register at OHCI offset 80h/84h (see Section 4.21, Interrupt Event Register) are set to 1, this request-transmit-complete interrupt mask enables interrupt generation. 18 17 RSVD busReset R RSC 16 selfIDcomplete RSC 15-10 9 RSVD lockRespErr R RSC 8 postedWriteErr RSC 7 isochRx RSC 6 isochTx RSC 5 RSPkt RSC 4 RQPkt RSC 3 ARRS RSC 2 ARRQ RSC 1 respTxComplete RSC 0 reqTxComplete RSC 4-21 4.23 Isochronous Transmit Interrupt Event Register The isochronous transmit interrupt event set/clear register reflects the interrupt state of the isochronous transmit contexts. An interrupt is generated on behalf of an isochronous transmit context if an OUTPUT_LAST* command completes and its interrupt bits are set to 1. Upon determining that the isochTx (bit 6) interrupt in the interrupt event register at OHCI offset 80h/84h (see Section 4.21, Interrupt Event Register) has occurred, software can check this register to determine which context(s) caused the interrupt. The interrupt bits are set to 1 by an asserting edge of the corresponding interrupt signal, or by writing a 1 in the corresponding bit in the set register. The only mechanism to clear a bit in this register is to write a 1 to the corresponding bit in the clear register. See Table 4-17 for a complete description of the register contents. Bit Name Type Default Bit Name Type Default R 0 R 0 R 0 R 0 R 0 R 0 R 0 15 R 0 14 R 0 13 R 0 12 R 0 11 R 0 10 31 30 29 28 27 26 25 R 0 9 R 0 24 R 0 8 R 0 23 R 0 7 RSC X 22 R 0 6 RSC X 21 R 0 5 RSC X 20 R 0 4 RSC X 19 R 0 3 RSC X 18 R 0 2 RSC X 17 R 0 1 RSC X 16 R 0 0 RSC X Isochronous transmit interrupt event Isochronous transmit interrupt event Register: Type: Offset: Default: Isochronous transmit interrupt event Read/Set/Clear, Read-only 90h set register 94h clear register [returns the contents of the isochronous transmit interrupt event register bit-wise ANDed with the isochronous transmit interrupt mask register when read] 0000 00XXh Table 4-17. Isochronous Transmit Interrupt Event Register Description BIT 31-8 7 6 5 4 3 2 1 0 FIELD NAME RSVD isoXmit7 isoXmit6 isoXmit5 isoXmit4 isoXmit3 isoXmit2 isoXmit1 isoXmit0 TYPE R RSC RSC RSC RSC RSC RSC RSC RSC Reserved. Bits 31-8 return 0s when read. DESCRIPTION Isochronous transmit channel 7 caused the interrupt event register bit 6 (isochTx) interrupt. Isochronous transmit channel 6 caused the interrupt event register bit 6 (isochTx) interrupt. Isochronous transmit channel 5 caused the interrupt event register bit 6 (isochTx) interrupt. Isochronous transmit channel 4 caused the interrupt event register bit 6 (isochTx) interrupt. Isochronous transmit channel 3 caused the interrupt event register bit 6 (isochTx) interrupt. Isochronous transmit channel 2 caused the interrupt event register bit 6 (isochTx) interrupt. Isochronous transmit channel 1 caused the interrupt event register bit 6 (isochTx) interrupt. Isochronous transmit channel 0 caused the interrupt event register bit 6 (isochTx) interrupt. 4-22 4.24 Isochronous Transmit Interrupt Mask Register The isochronous transmit interrupt mask set/clear register enables the isochTx interrupt source on a per-channel basis. Reads from either the set register or the clear register always return the contents of the isochronous transmit interrupt mask register. In all cases, the enables for each interrupt event align with the isochronous transmit interrupt event register bits detailed in Table 4-17. Bit Name Type Default Bit Name Type Default R 0 R 0 R 0 R 0 R 0 R 0 R 0 15 R 0 14 R 0 13 R 0 12 R 0 11 R 0 10 31 30 29 28 27 26 25 R 0 9 R 0 24 R 0 8 R 0 23 R 0 7 RSC X 22 R 0 6 RSC X 21 R 0 5 RSC X 20 R 0 4 RSC X 19 R 0 3 RSC X 18 R 0 2 RSC X 17 R 0 1 RSC X 16 R 0 0 RSC X Isochronous transmit interrupt mask Isochronous transmit interrupt mask Register: Type: Offset: Default: Isochronous transmit interrupt mask Read/Set/Clear, Read-only 98h set register 9Ch clear register 0000 00XXh 4-23 4.25 Isochronous Receive Interrupt Event Register The isochronous receive interrupt event set/clear register reflects the interrupt state of the isochronous receive contexts. An interrupt is generated on behalf of an isochronous receive context if an INPUT_* command completes and its interrupt bits are set to 1. Upon determining that the isochRx (bit 7) interrupt in the interrupt event register at OHCI offset 80h/84h (see Section 4.21, Interrupt Event Register) has occurred, software can check this register to determine which context(s) caused the interrupt. The interrupt bits are set to 1 by the asserting edge of the corresponding interrupt signal, or by writing a 1 to the corresponding bit in the set register. The only mechanism to clear a bit in this register is to write a 1 to the corresponding bit in the clear register. See Table 4-18 for a complete description of the register contents. Bit Name Type Default Bit Name Type Default R 0 R 0 R 0 R 0 R 0 R 0 R 0 15 R 0 14 R 0 13 R 0 12 R 0 11 R 0 10 31 30 29 28 27 26 25 R 0 9 R 0 24 R 0 8 R 0 23 R 0 7 R 0 22 R 0 6 R 0 21 R 0 5 R 0 20 R 0 4 R 0 19 R 0 3 RSC X 18 R 0 2 RSC X 17 R 0 1 RSC X 16 R 0 0 RSC X Isochronous receive interrupt event Isochronous receive interrupt event Register: Type: Offset: Default: Isochronous receive interrupt event Read/Set/Clear, Read-only A0h set register A4h clear register [returns the contents of the isochronous receive interrupt event register bit-wise ANDed with the isochronous receive mask register when read] 0000 000Xh Table 4-18. Isochronous Receive Interrupt Event Register Description BIT 31-4 3 2 1 0 FIELD NAME RSVD isoRecv3 isoRecv2 isoRecv1 isoRecv0 TYPE R RSC RSC RSC RSC DESCRIPTION Reserved. Bits 31-4 return 0s when read. Isochronous receive channel 3 caused the interrupt event register bit 7 (isochRx) interrupt. Isochronous receive channel 2 caused the interrupt event register bit 7 (isochRx) interrupt. Isochronous receive channel 1 caused the interrupt event register bit 7 (isochRx) interrupt. Isochronous receive channel 0 caused the interrupt event register bit 7 (isochRx) interrupt. 4-24 4.26 Isochronous Receive Interrupt Mask Register The isochronous receive interrupt mask set/clear register enables the isochRx interrupt source on a per-channel basis. Reads from either the set register or the clear register always return the contents of the isochronous receive interrupt mask register. In all cases, the enables for each interrupt event align with the event register bits detailed in Table 4-18. Bit Name Type Default Bit Name Type Default R 0 R 0 R 0 R 0 R 0 R 0 R 0 15 R 0 14 R 0 13 R 0 12 R 0 11 R 0 10 31 30 29 28 27 26 25 R 0 9 R 0 24 R 0 8 R 0 23 R 0 7 R 0 22 R 0 6 R 0 21 R 0 5 R 0 20 R 0 4 R 0 19 R 0 3 RSC X 18 R 0 2 RSC X 17 R 0 1 RSC X 16 R 0 0 RSC X Isochronous receive interrupt mask Isochronous receive interrupt mask Register: Type: Offset: Default: Isochronous receive interrupt mask Read/Set/Clear, Read-only A8h set register ACh clear register 0000 000Xh 4.27 Fairness Control Register The fairness control register provides a mechanism by which software can direct the host controller to transmit multiple asynchronous requests during a fairness interval. See Table 4-19 for a complete description of the register contents. Bit Name Type Default Bit Name Type Default R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 15 R 0 14 R 0 13 R 0 12 R 0 11 R 0 10 R 0 9 31 30 29 28 27 26 25 24 R 0 8 R 0 23 R 0 7 R/W 0 22 R 0 6 R/W 0 21 R 0 5 R/W 0 20 R 0 4 R/W 0 19 R 0 3 R/W 0 18 R 0 2 R/W 0 17 R 0 1 R/W 0 16 R 0 0 R/W 0 Fairness control Fairness control Register: Type: Offset: Default: Fairness control Read-only, Read/Write DCh 0000 0000h Table 4-19. Fairness Control Register Description BIT 31-8 7-0 FIELD NAME RSVD pri_req TYPE R R/W DESCRIPTION Reserved. Bits 31-8 return 0s when read. This field specifies the maximum number of priority arbitration requests for asynchronous request packets that the link is permitted to make of the PHY device during a fairness interval. 4-25 4.28 Link Control Register The link control set/clear register provides the control flags that enable and configure the link core protocol portions of the TSB12LV26 device. It contains controls for the receiver and cycle timer. See Table 4-20 for a complete description of the register contents. Bit Name Type Default Bit Name Type Default R 0 R 0 R 0 R 0 R 0 RSC X RSC X R 0 15 R 0 14 R 0 13 R 0 12 R 0 11 R 0 10 R 0 9 31 30 29 28 27 26 25 24 R 0 8 R 0 23 R 0 7 R 0 22 RSC X 6 R 0 21 RSCU X 5 R 0 20 RSC X 4 R 0 19 R 0 3 R 0 18 R 0 2 R 0 17 R 0 1 R 0 16 R 0 0 R 0 Link control Link control Register: Type: Offset: Default: Link control Read/Set/Clear/Update, Read/Set/Clear, Read-only E0h set register E4h clear register 00X0 0X00h Table 4-20. Link Control Register Description BIT 31-23 22 FIELD NAME RSVD cycleSource TYPE R RSC DESCRIPTION Reserved. Bits 31-23 return 0s when read. When bit 22 is set to 1, the cycle timer uses an external source (CYCLEIN) to determine when to roll over the cycle timer. When this bit is cleared, the cycle timer rolls over when the timer reaches 3072 cycles of the 24.576-MHz clock (125 s). When bit 21 is set to 1 and the PHY device has notified the TSB12LV26 device that the PHY device is root, the TSB12LV26 device generates a cycle start packet every time the cycle timer rolls over, based on the setting of bit 22 (cycleSource). When bit 21 is cleared, the OHCI-Lynxt accepts received cycle start packets to maintain synchronization with the node that is sending them. Bit 21 is automatically cleared when bit 25 (cycleTooLong) in the interrupt event register at OHCI offset 80h/84h (see Section 4.21, Interrupt Event Register) is set to 1. Bit 21 cannot be set to 1 until bit 25 (cycleTooLong) is cleared. When bit 20 is set to 1, the cycle timer offset counts cycles of the 24.576-MHz clock and rolls over at the appropriate time, based on the settings of the above bits. When this bit is cleared, the cycle timer offset does not count. Reserved. Bits 19-11 return 0s when read. When bit 10 is set to 1, the receiver accepts incoming PHY packets into the AR request context if the AR request context is enabled. This bit does not control receipt of self-ID packets. When bit 9 is set to 1, the receiver accepts incoming self-ID packets. Before setting this bit to 1, software must ensure that the self-ID buffer pointer register contains a valid address. Reserved. Bits 8-0 return 0s when read. 21 cycleMaster RSCU 20 CycleTimerEnable RSC 19-11 10 9 8-0 RSVD RcvPhyPkt RcvSelfID RSVD R RSC RSC R 4-26 4.29 Node Identification Register The node identification register contains the address of the node on which the OHCI-Lynxt chip resides, and indicates the valid node number status. The 16-bit combination of the busNumber field (bits 15-6) and the NodeNumber field (bits 5-0) is referred to as the node ID. See Table 4-21 for a complete description of the register contents. Bit Name Type Default Bit Name Type Default RWU 1 RWU 1 RWU 1 RWU 1 RWU 1 RWU 1 RWU 1 RU 0 15 RU 0 14 R 0 13 R 0 12 RU 0 11 R 0 10 R 0 9 31 30 29 28 27 26 25 24 R 0 8 RWU 1 23 R 0 7 RWU 1 22 R 0 6 RWU 1 21 R 0 5 RU X 20 R 0 4 RU X 19 R 0 3 RU X 18 R 0 2 RU X 17 R 0 1 RU X 16 R 0 0 RU X Node identification Node identification Register: Type: Offset: Default: Node identification Read/Write/Update, Read/Update, Read-only E8h 0000 FFXXh Table 4-21. Node Identification Register Description BIT 31 FIELD NAME iDValid TYPE RU DESCRIPTION Bit 31 indicates whether or not the TSB12LV26 device has a valid node number. It is cleared when a 1394 bus reset is detected, and set to 1 when the TSB12LV26 device receives a new node number from the PHY device. Bit 30 is set to 1 during the bus reset process if the attached PHY device is root. Reserved. Bits 29 and 28 return 0s when read. Bit 27 is set to 1 if the PHY device is reporting that cable power status is OK. Reserved. Bits 26-16 return 0s when read. This field identifies the specific 1394 bus the TSB12LV26 device belongs to when multiple 1394-compatible buses are connected via a bridge. This field is the physical node number established by the PHY device during self-ID. It is automatically set to the value received from the PHY device after the self-ID phase. If the PHY device sets the NodeNumber to 63, software must not set bit 15 (run) in the asynchronous context control register (see Section 4.37, Asynchronous Context Control Register) for either of the AT DMA contexts. 30 29-28 27 26-16 15-6 5-0 root RSVD CPS RSVD BusNumber NodeNumber RU R RU R RWU RU 4-27 4.30 PHY Layer Control Register The PHY layer control register reads or writes a PHY register. See Table 4-22 for a complete description of the register contents. Bit Name Type Default Bit Name Type Default RWU 0 RWU 0 R 0 R 0 R/W 0 R/W 0 R/W 0 RU 0 15 R 0 14 R 0 13 R 0 12 RU 0 11 RU 0 10 RU 0 9 31 30 29 28 27 26 25 24 RU 0 8 R/W 0 23 RU 0 7 R/W 0 22 RU 0 6 R/W 0 21 RU 0 5 R/W 0 20 RU 0 4 R/W 0 19 RU 0 3 R/W 0 18 RU 0 2 R/W 0 17 RU 0 1 R/W 0 16 RU 0 0 R/W 0 PHY layer control PHY layer control Register: Type: Offset: Default: PHY layer control Read/Write/Update, Read/Write, Read/Update, Read-only ECh 0000 0000h Table 4-22. PHY Layer Control Register Description BIT 31 30-28 27-24 23-16 15 FIELD NAME rdDone RSVD rdAddr rdData rdReg TYPE RU R RU RU RWU DESCRIPTION Bit 31 is cleared to 0 by the TSB12LV26 device when either bit 15 (rdReg) or bit 14 (wrReg) is set to 1. This bit is set to 1 when a register transfer is received from the PHY device. Reserved. Bits 30-28 return 0s when read. This field is the address of the register most recently received from the PHY device. This field is the contents of a PHY register that has been read. Bit 15 is set to 1 by software to initiate a read request to a PHY register, and is cleared by hardware when the request has been sent. Bits 14 (wrReg) and 15 (rdReg) must not both be set to 1 simultaneously. Bit 14 is set to 1 by software to initiate a write request to a PHY register, and is cleared by hardware when the request has been sent. Bits 14 (wrReg) and 15 (rdReg) must not both be set to 1 simultaneously. Reserved. Bits 13 and 12 return 0s when read. This field is the address of the PHY register to be written or read. This field is the data to be written to a PHY register and is ignored for reads. 14 wrReg RWU 13-12 11-8 7-0 RSVD regAddr wrData R R/W R/W 4-28 4.31 Isochronous Cycle Timer Register The isochronous cycle timer register indicates the current cycle number and offset. When the TSB12LV26 device is cycle master, this register is transmitted with the cycle start message. When the TSB12LV26 device is not cycle master, this register is loaded with the data field in an incoming cycle start. In the event that the cycle start message is not received, the fields can continue incrementing on their own (if programmed) to maintain a local time reference. See Table 4-23 for a complete description of the register contents. Bit Name Type Default Bit Name Type Default RWU X RWU X RWU X RWU X RWU X RWU X RWU X 15 RWU X 14 RWU X 13 RWU X 12 RWU X 11 RWU X 10 31 30 29 28 27 26 25 RWU X 9 RWU X 24 RWU X 8 RWU X 23 RWU X 7 RWU X 22 RWU X 6 RWU X 21 RWU X 5 RWU X 20 RWU X 4 RWU X 19 RWU X 3 RWU X 18 RWU X 2 RWU X 17 RWU X 1 RWU X 16 RWU X 0 RWU X Isochronous cycle timer Isochronous cycle timer Register: Type: Offset: Default: Isochronous cycle timer Read/Write/Update F0h XXXX XXXXh Table 4-23. Isochronous Cycle Timer Register Description BIT 31-25 24-12 11-0 FIELD NAME cycleSeconds cycleCount cycleOffset TYPE RWU RWU RWU DESCRIPTION This field counts seconds [rollovers from bits 24-12 (cycleCount field)] modulo 128. This field counts cycles [rollovers from bits 11-0 (cycleOffset field)] modulo 8000. This field counts 24.576-MHz clocks modulo 3072, that is, 125 s. If an external 8-kHz clock configuration is being used, this field must be cleared to 0 at each tick of the external clock. 4-29 4.32 Asynchronous Request Filter High Register The asynchronous request filter high set/clear register enables asynchronous receive requests on a per-node basis, and handles the upper node IDs. When a packet is destined for either the physical request context or the ARRQ context, the source node ID is examined. If the bit corresponding to the node ID is not set to 1 in this register, the packet is not acknowledged and the request is not queued. The node ID comparison is done if the source node is on the same bus as the TSB12LV26 device. Nonlocal bus-sourced packets are not acknowledged unless bit 31 in this register is set to 1. See Table 4-24 for a complete description of the register contents. Bit Name Type Default Bit Name Type Default RSC 0 RSC 0 RSC 0 RSC 0 RSC 0 RSC 0 RSC 0 15 RSC 0 14 RSC 0 13 RSC 0 12 RSC 0 11 RSC 0 10 31 30 29 28 27 26 25 RSC 0 9 RSC 0 24 RSC 0 8 RSC 0 23 RSC 0 7 RSC 0 22 RSC 0 6 RSC 0 21 RSC 0 5 RSC 0 20 RSC 0 4 RSC 0 19 RSC 0 3 RSC 0 18 RSC 0 2 RSC 0 17 RSC 0 1 RSC 0 16 RSC 0 0 RSC 0 Asynchronous request filter high Asynchronous request filter high Register: Type: Offset: Default: Asynchronous request filter high Read/Set/Clear 100h set register 104h clear register 0000 0000h Table 4-24. Asynchronous Request Filter High Register Description BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 FIELD NAME asynReqAllBuses asynReqResource62 asynReqResource61 asynReqResource60 asynReqResource59 asynReqResource58 asynReqResource57 asynReqResource56 asynReqResource55 asynReqResource54 asynReqResource53 asynReqResource52 asynReqResource51 TYPE RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC DESCRIPTION If bit 31 is set to 1, all asynchronous requests received by the TSB12LV26 device from nonlocal bus nodes are accepted. If bit 30 is set to 1 for local bus node number 62, asynchronous requests received by the TSB12LV26 device from that node are accepted. If bit 29 is set to 1 for local bus node number 61, asynchronous requests received by the TSB12LV26 device from that node are accepted. If bit 28 is set to 1 for local bus node number 60, asynchronous requests received by the TSB12LV26 device from that node are accepted. If bit 27 is set to 1 for local bus node number 59, asynchronous requests received by the TSB12LV26 device from that node are accepted. If bit 26 is set to 1 for local bus node number 58, asynchronous requests received by the TSB12LV26 device from that node are accepted. If bit 25 is set to 1 for local bus node number 57, asynchronous requests received by the TSB12LV26 device from that node are accepted. If bit 24 is set to 1 for local bus node number 56, asynchronous requests received by the TSB12LV26 device from that node are accepted. If bit 23 is set to 1 for local bus node number 55, asynchronous requests received by the TSB12LV26 device from that node are accepted. If bit 22 is set to 1 for local bus node number 54, asynchronous requests received by the TSB12LV26 device from that node are accepted. If bit 21 is set to 1 for local bus node number 53, asynchronous requests received by the TSB12LV26 device from that node are accepted. If bit 20 is set to 1 for local bus node number 52, asynchronous requests received by the TSB12LV26 device from that node are accepted. If bit 19 is set to 1 for local bus node number 51, asynchronous requests received by the TSB12LV26 device from that node are accepted. 4-30 Table 4-24. Asynchronous Request Filter High Register Description (Continued) BIT 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD NAME asynReqResource50 asynReqResource49 asynReqResource48 asynReqResource47 asynReqResource46 asynReqResource45 asynReqResource44 asynReqResource43 asynReqResource42 asynReqResource41 asynReqResource40 asynReqResource39 asynReqResource38 asynReqResource37 asynReqResource36 asynReqResource35 asynReqResource34 asynReqResource33 asynReqResource32 TYPE RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC DESCRIPTION If bit 18 is set to 1 for local bus node number 50, asynchronous requests received by the TSB12LV26 device from that node are accepted. If bit 17 is set to 1 for local bus node number 49, asynchronous requests received by the TSB12LV26 device from that node are accepted. If bit 16 is set to 1 for local bus node number 48, asynchronous requests received by the TSB12LV26 device from that node are accepted. If bit 15 is set to 1 for local bus node number 47, asynchronous requests received by the TSB12LV26 device from that node are accepted. If bit 14 is set to 1 for local bus node number 46, asynchronous requests received by the TSB12LV26 device from that node are accepted. If bit 13 is set to 1 for local bus node number 45, asynchronous requests received by the TSB12LV26 device from that node are accepted. If bit 12 is set to 1 for local bus node number 44, asynchronous requests received by the TSB12LV26 device from that node are accepted. If bit 11 is set to 1 for local bus node number 43, asynchronous requests received by the TSB12LV26 device from that node are accepted. If bit 10 is set to 1 for local bus node number 42, asynchronous requests received by the TSB12LV26 device from that node are accepted. If bit 9 is set to 1 for local bus node number 41, asynchronous requests received by the TSB12LV26 device from that node are accepted. If bit 8 is set to 1 for local bus node number 40, asynchronous requests received by the TSB12LV26 device from that node are accepted. If bit 7 is set to 1 for local bus node number 39, asynchronous requests received by the TSB12LV26 device from that node are accepted. If bit 6 is set to 1 for local bus node number 38, asynchronous requests received by the TSB12LV26 device from that node are accepted. If bit 5 is set to 1 for local bus node number 37, asynchronous requests received by the TSB12LV26 device from that node are accepted. If bit 4 is set to 1 for local bus node number 36, asynchronous requests received by the TSB12LV26 device from that node are accepted. If bit 3 is set to 1 for local bus node number 35, asynchronous requests received by the TSB12LV26 device from that node are accepted. If bit 2 is set to 1 for local bus node number 34, asynchronous requests received by the TSB12LV26 device from that node are accepted. If bit 1 is set to 1 for local bus node number 33, asynchronous requests received by the TSB12LV26 device from that node are accepted. If bit 0 is set to 1 for local bus node number 32, asynchronous requests received by the TSB12LV26 device from that node are accepted. 4-31 4.33 Asynchronous Request Filter Low Register The asynchronous request filter low set/clear register enables asynchronous receive requests on a per-node basis and handles the lower node IDs. Other than filtering different node IDs, this register behaves identically to the asynchronous request filter high register. See Table 4-25 for a complete description of the register contents. Bit Name Type Default Bit Name Type Default RSC 0 RSC 0 RSC 0 RSC 0 RSC 0 RSC 0 RSC 0 15 RSC 0 14 RSC 0 13 RSC 0 12 RSC 0 11 RSC 0 10 31 30 29 28 27 26 25 RSC 0 9 RSC 0 24 RSC 0 8 RSC 0 23 RSC 0 7 RSC 0 22 RSC 0 6 RSC 0 21 RSC 0 5 RSC 0 20 RSC 0 4 RSC 0 19 RSC 0 3 RSC 0 18 RSC 0 2 RSC 0 17 RSC 0 1 RSC 0 16 RSC 0 0 RSC 0 Asynchronous request filter low Asynchronous request filter low Register: Type: Offset: Default: Asynchronous request filter low Read/Set/Clear 108h set register 10Ch clear register 0000 0000h Table 4-25. Asynchronous Request Filter Low Register Description BIT 31 30 29-2 1 0 FIELD NAME asynReqResource31 asynReqResource30 asynReqResourcen asynReqResource1 asynReqResource0 TYPE RSC RSC RSC RSC RSC DESCRIPTION If bit 31 is set to 1 for local bus node number 31, asynchronous requests received by the TSB12LV26 device from that node are accepted. If bit 30 is set to 1 for local bus node number 30, asynchronous requests received by the TSB12LV26 device from that node are accepted. Bits 29 through 2 (asynReqResourcen, where n = 29, 28, 27, ..., 2) follow the same pattern as bits 31 and 30. If bit 1 is set to 1 for local bus node number 1, asynchronous requests received by the TSB12LV26 device from that node are accepted. If bit 0 is set to 1 for local bus node number 0, asynchronous requests received by the TSB12LV26 device from that node are accepted. 4-32 4.34 Physical Request Filter High Register The physical request filter high set/clear register enables physical receive requests on a per-node basis, and handles the upper node IDs. When a packet is destined for the physical request context, and the node ID has been compared against the ARRQ registers, then the comparison is done again with this register. If the bit corresponding to the node ID is not set to 1 in this register, the request is handled by the ARRQ context instead of the physical request context. The node ID comparison is done if the source node is on the same bus as the TSB12LV26 device. Nonlocal bus-sourced packets are not acknowledged unless bit 31 in this register is set to 1. See Table 4-26 for a complete description of the register contents. Bit Name Type Default Bit Name Type Default RSC 0 RSC 0 RSC 0 RSC 0 RSC 0 RSC 0 RSC 0 15 RSC 0 14 RSC 0 13 RSC 0 12 RSC 0 11 RSC 0 10 31 30 29 28 27 26 25 RSC 0 9 RSC 0 24 RSC 0 8 RSC 0 23 RSC 0 7 RSC 0 22 RSC 0 6 RSC 0 21 RSC 0 5 RSC 0 20 RSC 0 4 RSC 0 19 RSC 0 3 RSC 0 18 RSC 0 2 RSC 0 17 RSC 0 1 RSC 0 16 RSC 0 0 RSC 0 Physical request filter high Physical request filter high Register: Type: Offset: Default: Physical request filter high Read/Set/Clear 110h set register 114h clear register 0000 0000h Table 4-26. Physical Request Filter High Register Description BIT 31 30 29 28 27 26 25 24 23 22 21 20 FIELD NAME physReqAllBusses physReqResource62 physReqResource61 physReqResource60 physReqResource59 physReqResource58 physReqResource57 physReqResource56 physReqResource55 physReqResource54 physReqResource53 physReqResource52 TYPE RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC DESCRIPTION If bit 31 is set to 1, all physical requests received by the TSB12LV26 device from nonlocal bus nodes are accepted. If bit 30 is set to 1 for local bus node number 62, physical requests received by the TSB12LV26 device from that node are handled through the physical request context. If bit 29 is set to 1 for local bus node number 61, physical requests received by the TSB12LV26 device from that node are handled through the physical request context. If bit 28 is set to 1 for local bus node number 60, physical requests received by the TSB12LV26 device from that node are handled through the physical request context. If bit 27 is set to 1 for local bus node number 59, physical requests received by the TSB12LV26 device from that node are handled through the physical request context. If bit 26 is set to 1 for local bus node number 58, physical requests received by the TSB12LV26 device from that node are handled through the physical request context. If bit 25 is set to 1 for local bus node number 57, physical requests received by the TSB12LV26 device from that node are handled through the physical request context. If bit 24 is set to 1 for local bus node number 56, physical requests received by the TSB12LV26 device from that node are handled through the physical request context. If bit 23 is set to 1 for local bus node number 55, physical requests received by the TSB12LV26 device from that node are handled through the physical request context. If bit 22 is set to 1 for local bus node number 54, physical requests received by the TSB12LV26 device from that node are handled through the physical request context. If bit 21 is set to 1 for local bus node number 53, physical requests received by the TSB12LV26 device from that node are handled through the physical request context. If bit 20 is set to 1 for local bus node number 52, physical requests received by the TSB12LV26 device from that node are handled through the physical request context. 4-33 Table 4-26. Physical Request Filter High Register Description (Continued) BIT 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIELD NAME physReqResource51 physReqResource50 physReqResource49 physReqResource48 physReqResource47 physReqResource46 physReqResource45 physReqResource44 physReqResource43 physReqResource42 physReqResource41 physReqResource40 physReqResource39 physReqResource38 physReqResource37 physReqResource36 physReqResource35 physReqResource34 physReqResource33 physReqResource32 TYPE RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC DESCRIPTION If bit 19 is set to 1 for local bus node number 51, physical requests received by the TSB12LV26 device from that node are handled through the physical request context. If bit 18 is set to 1 for local bus node number 50, physical requests received by the TSB12LV26 device from that node are handled through the physical request context. If bit 17 is set to 1 for local bus node number 49, physical requests received by the TSB12LV26 device from that node are handled through the physical request context. If bit 16 is set to 1 for local bus node number 48, physical requests received by the TSB12LV26 device from that node are handled through the physical request context. If bit 15 is set to 1 for local bus node number 47, physical requests received by the TSB12LV26 device from that node are handled through the physical request context. If bit 14 is set to 1 for local bus node number 46, physical requests received by the TSB12LV26 device from that node are handled through the physical request context. If bit 13 is set to 1 for local bus node number 45, physical requests received by the TSB12LV26 device from that node are handled through the physical request context. If bit 12 is set to 1 for local bus node number 44, physical requests received by the TSB12LV26 device from that node are handled through the physical request context. If bit 11 is set to 1 for local bus node number 43, physical requests received by the TSB12LV26 device from that node are handled through the physical request context. If bit 10 is set to 1 for local bus node number 42, physical requests received by the TSB12LV26 device from that node are handled through the physical request context. If bit 9 is set to 1 for local bus node number 41, physical requests received by the TSB12LV26 device from that node are handled through the physical request context. If bit 8 is set to 1 for local bus node number 40, physical requests received by the TSB12LV26 device from that node are handled through the physical request context. If bit 7 is set to 1 for local bus node number 39, physical requests received by the TSB12LV26 device from that node are handled through the physical request context. If bit 6 is set to 1 for local bus node number 38, physical requests received by the TSB12LV26 device from that node are handled through the physical request context. If bit 5 is set to 1 for local bus node number 37, physical requests received by the TSB12LV26 device from that node are handled through the physical request context. If bit 4 is set to 1 for local bus node number 36, physical requests received by the TSB12LV26 device from that node are handled through the physical request context. If bit 3 is set to 1 for local bus node number 35, physical requests received by the TSB12LV26 device from that node are handled through the physical request context. If bit 2 is set to 1 for local bus node number 34, physical requests received by the TSB12LV26 device from that node are handled through the physical request context. If bit 1 is set to 1 for local bus node number 33, physical requests received by the TSB12LV26 device from that node are handled through the physical request context. If bit 0 is set to 1 for local bus node number 32, physical requests received by the TSB12LV26 device from that node are handled through the physical request context. 4-34 4.35 Physical Request Filter Low Register The physical request filter low set/clear register enables physical receive requests on a per-node basis, and handles the lower node IDs. When a packet is destined for the physical request context, and the node ID has been compared against the asynchronous request filter registers, then the node ID comparison is done again with this register. If the bit corresponding to the node ID is not set to 1 in this register, the request is handled by the asynchronous request context instead of the physical request context. See Table 4-27 for a complete description of the register contents. Bit Name Type Default Bit Name Type Default RSC 0 RSC 0 RSC 0 RSC 0 RSC 0 RSC 0 RSC 0 15 RSC 0 14 RSC 0 13 RSC 0 12 RSC 0 11 RSC 0 10 31 30 29 28 27 26 25 RSC 0 9 RSC 0 24 RSC 0 8 RSC 0 23 RSC 0 7 RSC 0 22 RSC 0 6 RSC 0 21 RSC 0 5 RSC 0 20 RSC 0 4 RSC 0 19 RSC 0 3 RSC 0 18 RSC 0 2 RSC 0 17 RSC 0 1 RSC 0 16 RSC 0 0 RSC 0 Physical request filter low Physical request filter low Register: Type: Offset: Default: BIT 31 30 29-2 1 0 Physical request filter low Read/Set/Clear 118h set register 11Ch clear register 0000 0000h Table 4-27. Physical Request Filter Low Register Description TYPE RSC RSC RSC RSC RSC DESCRIPTION If bit 31 is set to 1 for local bus node number 31, physical requests received by the TSB12LV26 device from that node are handled through the physical request context. If bit 30 is set to 1 for local bus node number 30, physical requests received by the TSB12LV26 device from that node are handled through the physical request context. Bits 29 through 2 (physReqResourcen, where n = 29, 28, 27, ..., 2) follow the same pattern as bits 31 and 30. If bit 1 is set to 1 for local bus node number 1, physical requests received by the TSB12LV26 device from that node are handled through the physical request context. If bit 0 is set to 1 for local bus node number 0, physical requests received by the TSB12LV26 device from that node are handled through the physical request context. FIELD NAME physReqResource31 physReqResource30 physReqResourcen physReqResource1 physReqResource0 4.36 Physical Upper Bound Register (Optional Register) The physical upper bound register is an optional register and is not implemented. This register returns all 0s when read. Bit Name Type Default Bit Name Type Default R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 15 R 0 14 R 0 13 R 0 12 R 0 11 R 0 10 R 0 9 31 30 29 28 27 26 25 24 R 0 8 R 0 23 R 0 7 R 0 22 R 0 6 R 0 21 R 0 5 R 0 20 R 0 4 R 0 19 R 0 3 R 0 18 R 0 2 R 0 17 R 0 1 R 0 16 R 0 0 R 0 Physical upper bound Physical upper bound Register: Type: Offset: Default: Physical upper bound Read-only 120h 0000 0000h 4-35 4.37 Asynchronous Context Control Register The asynchronous context control set/clear register controls the state and indicates status of the DMA context. See Table 4-28 for a complete description of the register contents. Bit Name Type Default Bit Name Type Default RSCU 0 R 0 R 0 RSU X RU 0 RU 0 R 0 15 R 0 14 R 0 13 R 0 12 R 0 11 R 0 10 31 30 29 28 27 26 25 R 0 9 R 0 24 R 0 8 R 0 23 R 0 7 RU X 22 R 0 6 RU X 21 R 0 5 RU X 20 R 0 4 RU X 19 R 0 3 RU X 18 R 0 2 RU X 17 R 0 1 RU X 16 R 0 0 RU X Asynchronous context control Asynchronous context control Register: Type: Offset: Default: Asynchronous context control Read/Set/Clear/Update, Read/Set/Update, Read/Update, Read-only 180h set register [ATRQ] 184h clear register [ATRQ] 1A0h set register [ATRS] 1A4h clear register [ATRS] 1C0h set register [ARRQ] 1C4h clear register [ARRQ] 1E0h set register [ARRS] 1E4h clear register [ARRS] 0000 X0XXh Table 4-28. Asynchronous Context Control Register Description BIT 31-16 15 FIELD NAME RSVD run TYPE R RSCU DESCRIPTION Reserved. Bits 31-16 return 0s when read. Bit 15 is set to 1 by software to enable descriptor processing for the context and cleared by software to stop descriptor processing. The TSB12LV26 device changes this bit only on a system (hardware) or software reset. Reserved. Bits 14 and 13 return 0s when read. Software sets bit 12 to 1 to cause the TSB12LV26 device to continue or resume descriptor processing. The TSB12LV26 device clears this bit on every descriptor fetch. The TSB12LV26 device sets bit 11 to 1 when it encounters a fatal error, and clears the bit when software clears bit 15 (run). The TSB12LV26 device sets bit 10 to 1 when it is processing descriptors. Reserved. Bits 9 and 8 return 0s when read. This field indicates the speed at which a packet was received or transmitted and only contains meaningful information for receive contexts. This field is encoded as: 000 = 100M bits/sec 001 = 200M bits/sec 010 = 400M bits/sec All other values are reserved. 14-13 12 11 10 9-8 7-5 RSVD wake dead active RSVD spd R RSU RU RU R RU 4-0 eventcode RU This field holds the acknowledge sent by the link core for this packet or an internally generated error code if the packet was not transferred successfully. 4-36 4.38 Asynchronous Context Command Pointer Register The asynchronous context command pointer register contains a pointer to the address of the first descriptor block that the TSB12LV26 device accesses when software enables the context by setting bit 15 (run) in the asynchronous context control register (see Section 4.37) to 1. See Table 4-29 for a complete description of the register contents. Bit Name Type Default Bit Name Type Default RWU X RWU X RWU X RWU X RWU X RWU X 15 RWU X 14 RWU X 13 RWU X 12 RWU X 11 31 30 29 28 27 26 RWU X 10 RWU X 25 RWU X 9 RWU X 24 RWU X 8 RWU X 23 RWU X 7 RWU X 22 RWU X 6 RWU X 21 RWU X 5 RWU X 20 RWU X 4 RWU X 19 RWU X 3 RWU X 18 RWU X 2 RWU X 17 RWU X 1 RWU X 16 RWU X 0 RWU X Asynchronous context command pointer Asynchronous context command pointer Register: Type: Offset: Default: Asynchronous context command pointer Read/Write/Update 18Ch [ATRQ] 1ACh [ATRS] 1CCh [ARRQ] 1ECh [ARRS] XXXX XXXXh Table 4-29. Asynchronous Context Command Pointer Register Description BIT 31-4 3-0 FIELD NAME descriptorAddress Z TYPE RWU RWU DESCRIPTION Contains the upper 28 bits of the address of a 16-byte aligned descriptor block. Indicates the number of contiguous descriptors at the address pointed to by the descriptor address. If Z is 0, it indicates that the descriptorAddress field (bits 31-4) is not valid. 4-37 4.39 Isochronous Transmit Context Control Register The isochronous transmit context control set/clear register controls options, state, and status for the isochronous transmit DMA contexts. The n value in the following register addresses indicates the context number (n = 0, 1, 2, 3, ..., 7). See Table 4-30 for a complete description of the register contents. Bit Name Type Default Bit Name Type Default RSC 0 R 0 R 0 RSU X RU 0 RU 0 RSCU X 15 RSC X 14 RSC X 13 RSC X 12 RSC X 11 X 10 31 30 29 28 27 26 RSC 25 RSC X 9 R 0 24 RSC X 8 R 0 23 RSC X 7 RU X 22 RSC X 6 RU X 21 RSC X 5 RU X 20 RSC X 4 RU X 19 RSC X 3 RU X 18 RSC X 2 RU X 17 RSC X 1 RU X 16 RSC X 0 RU X Isochronous transmit context control Isochronous transmit context control Register: Type: Offset: Default: Isochronous transmit context control Read/Set/Clear/Update, Read/Set/Clear, Read/Set/Update, Read/Update, Read-only 200h + (16 * n) set register 204h + (16 * n) clear register XXXX X0XXh Table 4-30. Isochronous Transmit Context Control Register Description BIT 31 FIELD NAME cycleMatchEnable TYPE RSCU DESCRIPTION When bit 31 is set to 1, processing occurs such that the packet described by the context first descriptor block is transmitted in the cycle whose number is specified in the cycleMatch field (bits 30-16). The cycleMatch field (bits 30-16) must match the low-order two bits of cycleSeconds and the 13-bit cycleCount field in the cycle start packet that is sent or received immediately before isochronous transmission begins. Since the isochronous transmit DMA controller may work ahead, the processing of the first descriptor block may begin slightly in advance of the actual cycle in which the first packet is transmitted. The effects of this bit, however, are impacted by the values of other bits in this register and are explained in the 1394 Open Host Controller Interface Specification. Once the context has become active, hardware clears this bit. 30-16 cycleMatch RSC This field contains a 15-bit value, corresponding to the low-order two bits in the bus isochronous cycle timer register at OHCI offset F0h (see Section 4.31, Isochronous Cycle Timer Register) cycleSeconds field (bits 31-25) and the cycleCount field (bits 24-12). If bit 31 (cycleMatchEnable) is set to 1, this isochronous transmit DMA context becomes enabled for transmits when the low-order two bits of the bus isochronous cycle timer register cycleSeconds field (bits 31-25) and the cycleCount field (bits 24-12) value equal this field (cycleMatch) value. Bit 15 is set to 1 by software to enable descriptor processing for the context and cleared by software to stop descriptor processing. The TSB12LV26 device changes this bit only on a system (hardware) or software reset. Reserved. Bits 14 and 13 return 0s when read. Software sets bit 12 to 1 to cause the TSB12LV26 device to continue or resume descriptor processing. The TSB12LV26 device clears this bit on every descriptor fetch. The TSB12LV26 device sets bit 11 to 1 when it encounters a fatal error, and clears the bit when software clears bit 15 (run). The TSB12LV26 device sets bit 10 to 1 when it is processing descriptors. Reserved. Bits 9 and 8 return 0s when read. This field is not meaningful for isochronous transmit contexts. Following an OUTPUT_LAST* command, the error code is indicated in this field. Possible values are: ack_complete, evt_descriptor_read, evt_data_read, and evt_unknown. 15 run RSC 14-13 12 11 10 9-8 7-5 4-0 RSVD wake dead active RSVD spd event code R RSU RU RU R RU RU 4-38 4.40 Isochronous Transmit Context Command Pointer Register The isochronous transmit context command pointer register contains a pointer to the address of the first descriptor block that the TSB12LV26 device accesses when software enables an isochronous transmit context by setting bit 15 (run) in the isochronous transmit context control register (see Section 4.39, Isochronous Transmit Context Control Register) to 1. The n value in the following register addresses indicates the context number (n = 0, 1, 2, 3, ..., 7). Bit Name Type Default Bit Name Type Default R X R X R X R X R X R X 15 R X 14 R X 13 R X 12 R X 11 31 30 29 28 27 26 R X 10 R X 25 R X 9 R X 24 R X 8 R X 23 R X 7 R X 22 R X 6 R X 21 R X 5 R X 20 R X 4 R X 19 R X 3 R X 18 R X 2 R X 17 R X 1 R X 16 R X 0 R X Isochronous transmit context command pointer Isochronous transmit context command pointer Register: Type: Offset: Default: Isochronous transmit context command pointer Read-only 20Ch + (16 * n) XXXX XXXXh 4.41 Isochronous Receive Context Control Register The isochronous receive context control set/clear register controls options, state, and status for the isochronous receive DMA contexts. The n value in the following register addresses indicates the context number (n = 0, 1, 2, 3). See Table 4-31 for a complete description of the register contents. Bit Name Type Default Bit Name Type Default RSCU 0 R 0 R 0 RSU X RU 0 0 RSC X 15 RSC X 14 RSCU X 13 RSC X 12 R 0 11 0 10 RU 31 30 29 28 27 26 R 25 R 0 9 R 0 24 R 0 8 R 0 23 R 0 7 RU X 22 R 0 6 RU X 21 R 0 5 RU X 20 R 0 4 RU X 19 R 0 3 RU X 18 R 0 2 RU X 17 R 0 1 RU X 16 R 0 0 RU X Isochronous receive context control Isochronous receive context control Register: Type: Offset: Default: BIT 31 FIELD NAME bufferFill Isochronous receive context control Read/Set/Clear/Update, Read/Set/Clear, Read/Update, Read-only 400h + (32 * n) set register 404h + (32 * n) clear register X000 X0XXh Table 4-31. Isochronous Receive Context Control Register Description TYPE RSC DESCRIPTION When bit 31 is set to 1, received packets are placed back-to-back to completely fill each receive buffer. When this bit is cleared, each received packet is placed in a single buffer. If bit 28 (multiChanMode) is set to 1, this bit must also be set to 1. The value of this bit must not be changed while bit 10 (active) or bit 15 (run) is set to 1. When bit 30 is set to 1, received isochronous packets include the complete 4-byte isochronous packet header seen by the link layer. The end of the packet is marked with xferStatus in the first doublet, and a 16-bit timeStamp indicating the time of the most recently received (or sent) cycleStart packet. When this bit is cleared, the packet header is stripped from received isochronous packets. The packet header, if received, immediately precedes the packet payload. The value of this bit must not be changed while bit 10 (active) or bit 15 (run) is set to 1. 30 isochHeader RSC 4-39 Table 4-31. Isochronous Receive Context Control Register Description (Continued) BIT 29 FIELD NAME cycleMatchEnable TYPE RSCU DESCRIPTION When bit 29 is set to 1 and the 13-bit cycleMatch field (bits 24-12) in the isochronous receive context match register (see Section 4.43, Isochronous Receive Context Match Register) matches the 13-bit cycleCount field in the cycleStart packet, the context begins running. The effects of this bit, however, are impacted by the values of other bits in this register. Once the context has become active, hardware clears this bit. The value of this bit must not be changed while bit 10 (active) or bit 15 (run) is set to 1. When bit 28 is set to 1, the corresponding isochronous receive DMA context receives packets for all isochronous channels enabled in the isochronous receive channel mask high register at OHCI offset 70h/74h (see Section 4.19, Isochronous Receive Channel Mask High Register) and isochronous receive channel mask low register at OHCI offset 78h/7Ch (see Section 4.20, Isochronous Receive Channel Mask Low Register). The isochronous channel number specified in the isochronous receive context match register (see Section 4.43, Isochronous Receive Context Match Register) is ignored. When this bit is cleared, the isochronous receive DMA context receives packets for that single channel specified in the isochronous receive context match register (see Section 4.43). Only one isochronous receive DMA context may use the isochronous receive channel mask registers (see Sections 4.19 and 4.20). If more than one isochronous receive context control register has this bit set to 1, results are undefined. The value of this bit must not be changed while bit 10 (active) or bit 15 (run) is set to 1. 27-16 15 RSVD run R RSCU Reserved. Bits 27-16 return 0s when read. Bit 15 is set to 1 by software to enable descriptor processing for the context and cleared by software to stop descriptor processing. The TSB12LV26 device changes this bit only on a system (hardware) or software reset. Reserved. Bits 14 and 13 return 0s when read. Software sets bit 12 to 1 to cause the TSB12LV26 device to continue or resume descriptor processing. The TSB12LV26 device clears this bit on every descriptor fetch. The TSB12LV26 device sets bit 11 to 1 when it encounters a fatal error, and clears the bit when software clears bit 15 (run). The TSB12LV26 device sets bit 10 to 1 when it is processing descriptors. Reserved. Bits 9 and 8 return 0s when read. This field indicates the speed at which the packet was received. 000 = 100M bits/sec 001 = 200M bits/sec 010 = 400M bits/sec All other values are reserved. 4-0 event code RU For bufferFill mode, possible values are: ack_complete, evt_descriptor_read, evt_data_write, and evt_unknown. Packets with data errors (either dataLength mismatches or dataCRC errors) and packets for which a FIFO overrun occurred are backed out. For packet-per-buffer mode, possible values are: ack_complete, ack_data_error, evt_long_packet, evt_overrun, evt_descriptor_read, evt_data_write, and evt_unknown. 28 multiChanMode RSC 14-13 12 11 10 9-8 7-5 RSVD wake dead active RSVD spd R RSU RU RU R RU 4-40 4.42 Isochronous Receive Context Command Pointer Register The isochronous receive context command pointer register contains a pointer to the address of the first descriptor block that the TSB12LV26 device accesses when software enables an isochronous receive context by setting bit 15 (run) in the isochronous receive context control register (see Section 4.41, Isochronous Receive Context Control Register) to 1. The n value in the following register addresses indicates the context number (n = 0, 1, 2, 3). Bit Name Type Default Bit Name Type Default R X R X R X R X R X R X 15 R X 14 R X 13 R X 12 R X 11 31 30 29 28 27 26 R X 10 R X 25 R X 9 R X 24 R X 8 R X 23 R X 7 R X 22 R X 6 R X 21 R X 5 R X 20 R X 4 R X 19 R X 3 R X 18 R X 2 R X 17 R X 1 R X 16 R X 0 R X Isochronous receive context command pointer Isochronous receive context command pointer Register: Type: Offset: Default: Isochronous receive context command pointer Read-only 40Ch + (32 * n) XXXX XXXXh 4-41 4.43 Isochronous Receive Context Match Register The isochronous receive context match register starts an isochronous receive context running on a specified cycle number, filters incoming isochronous packets based on tag values, and waits for packets with a specified sync value. The n value in the following register addresses indicates the context number (n = 0, 1, 2, 3). See Table 4-32 for a complete description of the register contents. Bit Name Type Default Bit Name Type Default R/W X R/W X R/W X R/W X R/W X R/W X R/W X 15 R/W X 14 R/W X 13 R/W X 12 R 0 11 R 0 10 31 30 29 28 27 26 25 R 0 9 R/W X 24 R/W X 8 R/W X 23 R/W X 7 R 0 22 R/W X 6 R/W X 21 R/W X 5 R/W X 20 R/W X 4 R/W X 19 R/W X 3 R/W X 18 R/W X 2 R/W X 17 R/W X 1 R/W X 16 R/W X 0 R/W X Isochronous receive context match Isochronous receive context match Register: Type: Offset: Default: Isochronous receive context match Read/Write, Read-only 410Ch + (32 * n) XXXX XXXXh Table 4-32. Isochronous Receive Context Match Register Description BIT 31 30 29 28 27 26-12 FIELD NAME tag3 tag2 tag1 tag0 RSVD cycleMatch TYPE R/W R/W R/W R/W R R/W DESCRIPTION If bit 31 is set to 1, this context matches on isochronous receive packets with a tag field of 11b. If bit 30 is set to 1, this context matches on isochronous receive packets with a tag field of 10b. If bit 29 is set to 1, this context matches on isochronous receive packets with a tag field of 01b. If bit 28 is set to 1, this context matches on isochronous receive packets with a tag field of 00b. Reserved. Bit 27 returns 0 when read. This field contains a 15-bit value corresponding to the low-order two bits of cycleSeconds and the 13-bit cycleCount field in the cycleStart packet. If bit 29 (cycleMatchEnable) in the isochronous receive context control register (see Section 4.41, Isochronous Receive Context Control Register) is set to 1, this context is enabled for receives when the two low-order bits in the isochronous cycle timer register at OHCI offset F0h (see Section 4.31, Isochronous Cycle Timer Register) cycleSeconds field (bits 31-25) and cycleCount field (bits 24-12) value equal this field (cycleMatch) value. This 4-bit field is compared to the sync field of each isochronous packet for this channel when the command descriptor w field is set to 11b. Reserved. Bit 7 returns 0 when read. If bit 6 and bit 29 (tag1) are set to 1, packets with tag 01b are accepted into the context if the two most significant bits of the packets sync field are 00b. Packets with tag values other than 01b are filtered according to bit 28 (tag0), bit 30 (tag2), and bit 31 (tag3) without any additional restrictions. If this bit is cleared, this context matches on isochronous receive packets as specified in bits 28-31 (tag0-tag3) with no additional restrictions. 11-8 7 6 sync RSVD tag1SyncFilter R/W R R/W 5-0 channelNumber R/W This 6-bit field indicates the isochronous channel number for which this isochronous receive DMA context accepts packets. 4-42 5 GPIO Interface The general-purpose input/output (GPIO) interface consists of two GPIO ports. GPIO2 and GPIO3 power up as general-purpose inputs and are programmable via the GPIO control register. Figure 5-1 shows the logic diagram for GPIO2 and GPIO3 implementation. GPIO Read Data GPIO Port GPIO Write Data D Q GPIO_Invert GPIO Enable Figure 5-1. GPIO2 and GPIO3 Logic Diagram 5-1 6 Serial EEPROM Interface The TSB12LV26 device provides a serial bus interface to initialize the 1394 global unique ID register and a few PCI configuration registers through a serial EEPROM. The TSB12LV26 device communicates with the serial EEPROM via the 2-wire serial interface. After power up the serial interface initializes the locations listed in Table 6-1. While the TSB12LV26 device is accessing the serial EEPROM, all incoming PCI slave accesses are terminated with retry status. Table 6-2 shows the serial EEPROM memory map required for initializing the TSB12LV26 registers. NOTE: If a ROM is implemented in the design, it must be programmed. An unprogrammed ROM defaults to all 1s, which adversely impacts device operation. Table 6-1. Registers and Bits Loadable Through Serial EEPROM EEPROM OFFSET 00h 01h 03h 05h (bit 6) 05h 06h-0Ah 0Bh-0Eh 10h 11h-12h 13h OHCI/PCI CONFIGURATION OFFSET PCI register (3Eh) PCI register (2Dh) PCI register (2Ch) OHCI register (50h) PCI register (F4h) OHCI register (24h) OHCI register(28h) PCI register (F4h) PCI register (F0h) PCI register (40h) REGISTER PCI maximum latency, PCI minimum grant PCI vendor ID PCI subsystem ID Host controller control Link enhancements control GUID high GUID low Link enhancements control PCI miscellaneous PCI OHCI BITS LOADED FROM EEPROM 15-0 15-0 15-0 23 7, 2, 1 31-0 31-0 13, 12 15, 13, 10, 4-0 0 6-1 Table 6-2. Serial EEPROM Map BYTE ADDRESS 00 01 02 03 04 [7] Link_enhancementControl.enab_unfair [6] HCControl. ProgramPhy Enable PCI maximum latency (0h) PCI vendor ID PCI vendor ID (msbyte) PCI subsystem ID (lsbyte) PCI subsystem ID [5-3] RSVD [2] Link_enhancementControl.enab_ insert_idle [1] Link_enhancementControl.enab_accel [0] RSVD BYTE DESCRIPTION PCI minimum grant (0h) 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 [15-14] RSVD [7-5] RSVD Mini ROM address GUID high (lsbyte 0) GUID high (byte 1) GUID high (byte 2) GUID high (msbyte 3) GUID low (lsbyte 0) GUID low (byte 1) GUID low (byte 2) GUID low (msbyte 3) Checksum [13-12] AT threshold [4] Disable Target Abort [13] PME Support D2 [3] GP2IIC [2] Disable SCLK gate [11-8] RSVD [1] Disable PCI gate [0] Keep PCI 11 12 [15] PME D3 Cold [14] RSVD [12-11] RSVD [10] D2 support [9-8] RSVD 13 14 15-1E 1F [7-1] RSVD RSVD RSVD RSVD [0] Global swap 6-2 7 Electrical Characteristics 7.1 Absolute Maximum Ratings Over Operating Temperature Ranges Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 3.6 V Supply voltage range, VCCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 5.5 V Input voltage range for PCI, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to VCCP + 0.5 V Input voltage range for miscellaneous and PHY interface, VI . . . . . . . . . . . . . . . . . . . . . . . -0.5 to VCCI + 0.5 V Output voltage range for PCI, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to VCCP + 0.5 V Input voltage range for miscellaneous and PHY interface, VO . . . . . . . . . . . . . . . . . . . . . -0.5 to VCCP + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to 110C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. Applies to external input and bidirectional buffers. VI > VCCP. 2. Applies to external output and bidirectional buffers. VO > VCCP. 7-1 7.2 Recommended Operating Conditions OPERATION VCC VCCP Core voltage PCI I/O clamping voltage 3.3 V 3.3 V 5V 3.3 V PCI VIH High-level High level input voltage PHY interface Miscellaneous 3.3 V PCI VIL Low level input voltage Low-level PHY interface Miscellaneous PCI VI Input voltage g PHY interface Miscellaneous PCI VO tt Output voltage g PHY interface Miscellaneous Input transition time (tr and tf) PCI 3.3 V 3.3 V 5V 5V MIN 3 3 4.5 0.475 VCCP 2 2 2 0 0 0 0 0 0 0 0 0 0 0 -40 25 NOM 3.3 3.3 5 MAX 3.6 3.6 5.5 VCCP 3.6 3.6 VCCP 0.325 VCCP 0.8 0.8 0.8 VCCP 3.6 VCCP VCCP 3.6 VCCP 6 110 ns C V V V V V UNIT V TA Operating ambient temperature Applies for external inputs and bidirectional buffers without hysteresis. Miscellaneous terminals are: GPIO2 (2), GPIO3 (3), SDA (5), SCL (4), CYCLEOUT (77). Applies to external output buffers. 7-2 7.3 Electrical Characteristics Over Recommended Operating Conditions (unless otherwise noted) OPERATION PCI VOH High level output High-level out ut voltage PHY interface Miscellaneous PCI VOL Low level output Low-level out ut voltage PHY interface Miscellaneous IOZ IIL IIH 3-state output high-impedance Low-level Low level input current High-level High level input current Output pins Input pins I/O pins PCI Others 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V TEST CONDITIONS IOH = - 0.5 mA IOH = - 2 mA IOH = - 4 A IOH = - 8 mA IOH = - 4 mA IOL = 1.5 mA IOL = 6 mA IOL = 4 mA IOL = 8 mA IOL = 4 mA VO = VCC or GND VI = GND VI = GND VI = VCC VI = VCC MIN 0.9 VCC 2.4 2.8 VCC - 0.6 VCC - 0.6 0.1 VCC 0 0.55 0.4 0.5 20 20 20 20 20 A A A A V V MAX UNIT For I/O terminals, input leakage (IIL and IIH) includes IOZ of the disabled output. Miscellaneous terminals are: GPIO2 (2), GPIO3 (3), SDA (5), SCL (4), CYCLEOUT (77). 7.4 Switching Characteristics for PCI Interface PARAMETER tsu th Setup time before PCLK Hold time before PCLK MEASURED -50% to 50% -50% to 50% -50% to 50% MIN 7 0 2 11 MAX UNIT ns ns ns tval Delay time, PHY_CLK to data valid These parameters are ensured by design. 7.5 Switching Characteristics for PHY-Link Interface PARAMETER tsu th Setup time, Dn, CTLn, LREQ to PHY_CLK Hold time, Dn, CTLn, LREQ before PHY_CLK MEASURED -50% to 50% -50% to 50% -50% to 50% MIN 6 0 2 11 MAX UNIT ns ns ns td Delay time, PHY_CLK to Dn, CTLn These parameters are ensured by design. 7-3 8 Mechanical Information The TSB12LV26 device is packaged in a 100-terminal PZ package. The following shows the mechanical dimensions for the PZ package. PZ (S-PQFP-G100) PLASTIC QUAD FLATPACK 0,50 75 51 0,27 0,17 0,08 M 76 50 100 26 0,13 NOM 1 12,00 TYP 14,20 SQ 13,80 16,20 SQ 15,80 1,45 1,35 25 Gage Plane 0,05 MIN 0,25 0- 7 0,75 0,45 Seating Plane 1,60 MAX 0,08 4040149 /B 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026 8-1 |
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