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TPA3002D2
SLOS402A - DECEMBER 2002 - REVISED APRIL 2003
9-W STEREO CLASS-D AUDIO POWER AMPLIFIER WITH DC VOLUME CONTROL
FEATURES D 9-W/Ch Into an 8- Load From 12-V Supply D Efficient, Class-D Operation Eliminates D D D D
Heatsinks and Reduces Power Supply Requirements 32-Step DC Volume Control From -40 dB to 36 dB Line Outputs For External Headphone Amplifier With Volume Control Regulated 5-V Supply Output for Powering TPA6110A2 Space-Saving, Thermally-Enhanced PowerPAD Packaging Thermal and Short-Circuit Protection
DESCRIPTION
The TPA3002D2 is a 9-W (per channel) efficient, Class-D audio amplifier for driving bridged-tied stereo speakers. The TPA3002D2 can drive stereo speakers as low as 8 . The high efficiency of the TPA3002D2 eliminates the need for external heatsinks when playing music. Stereo speaker volume is controlled with a dc voltage applied to the volume control terminal offering a range of gain from -40 dB to 36 dB. Line outputs, for driving external headphone amplifier inputs, are also dc voltage controlled with a range of gain from -56 dB to 20 dB. An integrated 5-V regulated supply is provided for powering an external headphone amplifier.
D APPLICATIONS D LCD Monitors and TVs D Powered Speakers
PVCC 10 nF Cbs
10 F Cs 0.1 F Cs
10 F Cs 0.1 F Cs
PVCC 10 nF Cbs
ROUTN
ROUTN
PVCCR
PVCCR
PVCCR
PGNDR
PGNDR
ROUTP
ROUTP
PVCCR
BSRN
BSRP
Ccpr 1 F
SDZ RINN RINP
Crinn Crinp 1 F 1 F C2p5
SD RINN RINP V2P5 LINP LINN AVDDREF VREF
VCLAMPR MODE_OUT MODE AVCC VAROUTR VAROUTL RLINE_OUT LLINE_OUT AVDD Cosc 220 pF Cvdd 100 nF Rosc 120 k Ccpl 1 F 10 k 10 k MODE_OUT MODE AVCC Cs 0.1 F Cvcc 10 F
LINP LINN
Clinp 1 F 1 F Clinn 1 F
TPA3002D2
AGND AVDD COSC ROSC AGND VCLAMPL
VREF VARDIFF VARMAX VOL REFGND
VARDIFF VARMAX VOLUME REFGND PGNDL PGNDL LOUTN LOUTN LOUTP LOUTP PVCCL PVCCL PVCCL PVCCL Cbs 10 nF PVCC BSLN
Cs Cbs 10 nF PVCC 0.1 F Cs 10 F
Cs 0.1 F Cs 10 F
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
BSLP
Copyright 2002-2003, Texas Instruments Incorporated
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1
TPA3002D2
SLOS402A - DECEMBER 2002 - REVISED APRIL 2003
AVAILABLE OPTIONS PACKAGED DEVICE TA 48-PIN HTQFP (PHP) - 40C to 85C TPA3002D2PHP The PHP package is available taped and reeled. To order a taped and reeled part, add the suffix R to the part number (e.g., TPA3002D2PHPR). PHP PACKAGE (TOP VIEW)
PGNDR
PGNDR
ROUTN
ROUTN
PVCCR
PVCCR
PVCCR
PVCCR
ROUTP
ROUTP
BSRN
48 47
46 45 44
43 42
41 40 39 38
37 36 35 34 33 32
BSRP
SD RINN RINP V2P5 LINP LINN AVDDREF VREF VARDIFF VARMAX VOLUME REFGND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 BSLN PVCCL 15 16 17 PVCCL LOUTN LOUTN 18 19 PGNDL PGNDL 20 21 22 23 PVCCL PVCCL LOUTP LOUTP 24 BSLP
VCLAMPR MODE_OUT MODE AVCC VAROUTR VAROUTL AGND AVDD COSC ROSC AGND VCLAMPL
TPA3002D2
31 30 29 28 27 26 25
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TPA3002D2
SLOS402A - DECEMBER 2002 - REVISED APRIL 2003
functional block diagram
V2P5
V2P5
VAROUTR
V2P5 Gain Adj.
PVCC VClamp Gen
VCLAMPR
BSRN
PVCCR(2)
Cint2
Gate Drive
ROUTN(2)
PGNDR
RINN RINP
V2P5
Gain Adj.
Deglitch &
Rfdbk2
Modulation Logic
BSRP PVCCR(2)
Gate Drive
Rfdbk2
VREF
VOLUME
Gain Control
Cint2
ROUTP(2)
PGNDR
VARDIFF VARMAX
REFGND
To Gain Adj.
Blocks
V2P5
OC Detect Startup Protection Logic Thermal VDD VDDok AVCC VCCok
ROSC COSC
Ramp Generator
Biases
&
References
AVDDREF
AVDD
AVDD
5V LDO
AVCC AGND
PVCC
SD
TTL Input Buffer
VClamp Gen
VCLAMPL
BSLN
MODE MODE_OUT
Mode Control
PVCCL(2)
Cint2
V2P5
Gate Drive
LOUTN(2) PGNDL
BSLP
LINN LINP
Gain Adj.
Deglitch &
Rfdbk2
Modulation Logic
PVCCL(2)
Gate Drive
Rfdbk2 V2P5 Gain Adj.
Cint2
LOUTP(2) PGNDL
VAROUTL
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3
TPA3002D2
SLOS402A - DECEMBER 2002 - REVISED APRIL 2003
Terminal Functions
TERMINAL NO. AGND AVCC AVDD AVDDREF BSLN BSLP BSRN BSRP COSC LINN LINP LOUTN LOUTP MODE NAME 26, 30 33 29 7 13 24 48 37 28 6 5 16, 17 20, 21 34 I/O - - O O I/O I/O I/O I/O I/O I I O O I DESCRIPTION Analog ground for digital/analog cells in core High-voltage analog power supply (8.5 V to 14 V) 5-V Regulated output capable of 100-mA output 5-V Reference output--provided for connection to adjacent VREF terminal. Bootstrap I/O for left channel, negative high-side FET Bootstrap I/O for left channel, positive high-side FET Bootstrap I/O for right channel, negative high-side FET Bootstrap I/O for right channel, positive high-side FET I/O for charge/discharging currents onto capacitor for ramp generator triangle wave biased at V2P5 Negative differential audio input for left channel Positive differential audio input for left channel Class-D 1/2-H-bridge negative output for left channel Class-D 1/2-H-bridge positive output for left channel Input for MODE control. A logic high on this pin places the amplifier in the variable output mode and the Class-D outputs are disabled. A logic low on this pin places the amplifier in the Class-D mode and Class-D stereo outputs are enabled. Variable outputs (VAROUTL and VAROUTR) are still enabled in Class-D mode to be used as line-level outputs for external amplifiers. Output for control of the variable output amplifiers. When the MODE pin (34) is a logic high, the MODE_OUT pin is driven low. When the MODE pin (34) is a logic low, the MODE_OUT pin is driven high. This pin is intended for MUTE control of an external headphone amplifier. Leave unconnected when not used for headphone amplifier control. Power ground for left channel H-bridge Power ground for right channel H-bridge Power supply for left channel H-bridge (tied to pins 22 and 23 internally), not connected to PVCCR or AVCC. Power supply for left channel H-bridge (tied to pins 14 and 15 internally), not connected to PVCCR or AVCC. Power supply for right channel H-bridge (tied to pins 46 and 47 internally), not connected to PVCCL or AVCC. Power supply for right channel H-bridge (tied to pins 38 and 39 internally), not connected to PVCCL or AVCC. Ground for gain control circuitry. Connect to AGND. If using a DAC to control the volume, connect the DAC ground to this terminal. Positive differential audio input for right channel Negative differential audio input for right channel Current setting resistor for ramp generator. Nominally equal to 1/8*VCC Class-D 1/2-H-bridge negative output for right channel Class-D 1/2-H-bridge positive output for right channel Shutdown signal for IC (low = shutdown, high = operational). TTL logic levels with compliance to VCC. DC voltage to set the difference in gain between the Class-D and VAROUT outputs. Connect to GND or AVDDREF if VAROUT outputs are unconnected. DC voltage that sets the maximum gain for the VAROUT outputs. Connect to GND or AVDDREF if VAROUT outputs are unconnected. Variable output for left channel audio. Line level output for driving external HP amplifier. Variable output for right channel audio. Line level output for driving external HP amplifier. Internally generated voltage supply for left channel bootstrap capacitors.
MODE_OUT
35
O
PGNDL PGNDR PVCCL PVCCL PVCCR PVCCR REFGND RINP RINN ROSC ROUTN ROUTP SD VARDIFF VARMAX VAROUTL VAROUTR VCLAMPL
18, 19 42, 43 14, 15 22, 23 38,39 46, 47 12 3 2 27 44, 45 40, 41 1 9 10 31 32 25
- - - - - - - I I I/O O O I I I O O -
4
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TPA3002D2
SLOS402A - DECEMBER 2002 - REVISED APRIL 2003
Terminal Functions (Continued)
TERMINAL NO. VCLAMPR VOLUME VREF V2P5 -- NAME 36 11 8 4 Thermal Pad I/O - I I O - DESCRIPTION Internally generated voltage supply for right channel bootstrap capacitors. DC voltage that sets the gain of the Class-D and VAROUT outputs. Analog reference for gain control section. 2.5-V Reference for analog cells, as well as reference for unused audio input when using single-ended inputs. Connect to AGND and PGND--should be center point for both grounds.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range: AVCC, PVCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 15 V Input voltage range, VI: MODE, VREF, VARDIFF, VARMAX, VOLUME . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to 5.5 V SD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to VCC + 0.3 V RINN, RINP, LINN, LINP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 7 V Supply current, AVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 mA AVDDREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA Output current, VAROUTL, VAROUTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40C to 85C Operating junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40C to 150C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. DISSIPATION RATING TABLE PACKAGE PHP TA 25C 4.3 W DERATING FACTOR 34.7 mW/C TA = 70C 2.7 W TA = 85C 2.2 W
The PowerPAD must be soldered to a thermal land on the printed circuit board. Please refer to the PowerPAD Thermally Enhanced Package application note (SLMA002).
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5
TPA3002D2
SLOS402A - DECEMBER 2002 - REVISED APRIL 2003
recommended operating conditions
MIN Supply voltage, VCC Volume reference voltage Volume control pins, input voltage High-level High level input voltage VIH voltage, Low-level Low level input voltage VIL voltage, High-level output voltage, VOH Low-level output voltage, VOL High-level High level input current IIH current, Low-level Low level input current IIL current, Oscillator frequency, fOSC Operating free-air temperature, TA PVCC, AVCC VREF VARDIFF, VARMAX, VOLUME SD MODE SD MODE MODE_OUT, IOH = 1 mA MODE_OUT, IOL = -1 mA MODE, VI= 5 V, VCC = 14 V SD, VI= 14 V, VCC = 14 V MODE, VI= 0 V, VCC = 14 V SD, VI= 0 V, VCC = 14 V 225 -40 AVDD-100mV AGND+100mV 1 10 1 1 275 85 2 3.5 0.8 2 V V V uA uA uA uA kHz C V 8.5 3.0 MAX 14 5.5 5.5 UNIT V V V
dc characteristics, TA = 25C, VCC = 12 V, RL = 8 (unless otherwise noted)
PARAMETER | VOS | V2P5 (terminal 4) AVDD PSRR ICC(class-D) ICC(varout) ICC(class-D - max power) ICC(SD) rds(on) Class-D Output offset voltage (measured differentially) 2.5-V Bias voltage 5-V Regulated output Class-D power supply rejection ratio Class-D mode quiescent current Variable output mode quiescent current Class-D mode RMS current at max power Supply current in shutdown mode TEST CONDITIONS INN and INP connected together, Gain = 36 dB No load IO = 0 to 100 mA, SD = 2 V, VCC = 8 V to 14 V VCC = 11.5 V to 12.5 V MODE = 2 V, SD = 2 V MODE = 3.5 V, SD = 2 V RL = 8 , PO = 9 W SD = 0.8 V 0.45x AVDD 4.5 MIN TYP 10 0.5x AVDD 5.0 -80 16 7 2 1 10 28.5 9 MAX 65 0.55x AVDD 5.5 UNIT mV V V dB mA mA A uA
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Drain-source on-state resistance VCC = 12 V, IO = 1 A, TJ = 2 C 25C High side Low side Total 300 250 550 m 590 6 www.ti.com
TPA3002D2
SLOS402A - DECEMBER 2002 - REVISED APRIL 2003
ac characteristics for Class-D outputs, TA = 25C, VCC = 12 V, RL = 8 (unless otherwise noted)
PARAMETER kSVR PO Supply ripple rejection ratio Continuous output power TEST CONDITIONS VCC = 11.5 V to 12.5 V from 10 Hz to 1 kHz, Gain = 36 dB THD+N = 1%, f = 1 kHz, RL = 8 THD+N = 10%, f = 1 kHz, RL = 8 20 Hz to 22 kHz, No filter, Gain = 0.5 dB Vn Output integrated noise floor 20 Hz to 22 kHz, A-weighted filter, A weighted Gain = 13.2 dB Crosstalk, Class-D-Left Class-D-Right Crosstalk, Class-D VAROUT SNR Signal-to-noise ratio Thermal trip point Thermal hystersis Gain = 13.2 dB, PO = 1 W, RL = 8 Maximum output at THD < 0.5%, Gain = 36 dB Maximum output at THD+N < 0.5%, f= 1 kHz, Gain = 36 dB MIN TYP -67 7.5 9 79 -82 100 -80 -77 -63 96 150 20 MAX UNITS dB W W V dBV V dBV dB dB dB C C
characteristics for VAROUT outputs
PARAMETER |VOS| Output offset voltage TEST CONDITIONS Measured between V2P5 and VAROUT, Gain = 20 dB, RL = 10 k AV = 7.3 dB, f = 1 kHz, PO = 6 mW, RL = 32 AV = 7.3 dB, f = 1 kHz, RL = 2 k, VO = 1 Vrms Gain = 20 dB Gain = 20 dB, f = 1 kHz Maximum output at THD < 0.5%, Gain = 20 dB Maximum output at THD < 0.5%, Gain = 20 dB 20 Hz to 22 kHz, Gain = 20 dB Vn Output integrated noise floor 20 Hz to 22 kHz, Gain = -0.3 dB MIN TYP 10 0.025% 0.002% -74 -95 -60 -74 75 15 dB dB dB dB V V MAX UNITS mV
THD+N
Total harmonic distortion + noise
PSRR kSVR
DC power supply rejection ratio Supply ripple rejection ratio Crosstalk, VAROUTL VAROUTR Crosstalk, VAROUT Class-D
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7
TPA3002D2
SLOS402A - DECEMBER 2002 - REVISED APRIL 2003
Table 1. DC Volume Control for Class-D Outputs
VOLTAGE ON THE VOLUME PIN AS A PERCENTAGE OF VREF (INCREASING VOLUME OR FIXED GAIN) % 0 - 4.5 4.5 - 6.7 6.7 - 8.91 8.9 - 11.1 11.1 - 13.3 13.3 - 15.5 15.5 - 17.7 17.7 - 19.9 19.9 - 22.1 22.1 - 24.3 24.3 - 26.5 26.5 - 28.7 28.7 - 30.9 30.9 - 33.1 33.1 - 35.3 35.3 - 37.5 37.5 - 39.7 39.7 - 41.9 41.9 - 44.1 44.1 - 46.4 46.4 - 48.6 48.6 - 50.8 50.8 - 53.0 53.0 - 55.2 55.2 - 57.4 57.4 - 59.6 59.6 - 61.8 61.8 - 64.0 64.0 - 66.2 66.2 - 68.4 68.4 - 70.6 VOLTAGE ON THE VOLUME PIN AS A PERCENTAGE OF VREF (DECREASING VOLUME) % 0 - 2.9 2.9 - 5.1 5.1 - 7.2 7.2 - 9.4 9.4 - 11.6 11.6 - 13.8 13.8 - 16.0 16.0 - 18.2 18.2 - 20.4 20.4 - 22.6 22.6 - 24.8 24.8 - 27.0 27.0 - 29.1 29.1 - 31.3 31.3 - 33.5 33.5 - 35.7 35.7 - 37.9 37.9 - 40.1 40.1 - 42.3 42.3 - 44.5 44.5 - 46.7 46.7 - 48.9 48.9 - 51.0 51.0 - 53.2 53.2 - 55.4 55.4 - 57.6 57.6 - 59.8 59.8 - 62.0 62.0 - 64.2 64.2 - 66.4 66.4 - 68.6 GAIN OF CLASS-D AMPLIFIER
dB -75 -40.0 -37.5 -35.0 -32.4 -29.9 -27.4 -24.8 -22.3 -19.8 -17.2 -14.7 -12.2 -9.6 -7.1 -4.6 -2.0 0.5 3.1 5.6 8.1 10.7 13.2 15.7 18.3 20.8 23.3 25.9 28.4 30.9 33.5 36.0
> 70.6 >68.6 Tested in production. Remaining steps are specified by design.
8
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TPA3002D2
SLOS402A - DECEMBER 2002 - REVISED APRIL 2003
Table 2. DC Volume Control for VAROUT Outputs
VAROUT_VOLUME (V) - FROM FIGURE 35 - AS A PERCENTAGE OF VREF (INCREASING VOLUME OR FIXED GAIN) % 0 - 4.5 4.5 - 6.7 6.7 - 8.91 8.9 - 11.1 11.1 - 13.3 13.3 - 15.5 15.5 - 17.7 17.7 - 19.9 19.9 - 22.1 22.1 - 24.3 24.3 - 26.5 26.5 - 28.7 28.7 - 30.9 30.9 - 33.1 33.1 - 35.3 35.3 - 37.5 37.5 - 39.7 39.7 - 41.9 41.9 - 44.1 44.1 - 46.4 46.4 - 48.6 48.6 - 50.8 50.8 - 53.0 53.0 - 55.2 55.2 - 57.4 57.4 - 59.6 59.6 - 61.8 61.8 - 64.0 64.0 - 66.2 66.2 - 68.4 68.4 - 70.6 VAROUT_VOLUME (V) - FROM FIGURE 35 - AS A PERCENTAGE OF VREF (DECREASING VOLUME) % 0 - 2.9 2.9 - 5.1 5.1 - 7.2 7.2 - 9.4 9.4 - 11.6 11.6 - 13.8 13.8 - 16.0 16.0 - 18.2 18.2 - 20.4 20.4 - 22.6 22.6 - 24.8 24.8 - 27.0 27.0 - 29.1 29.1 - 31.3 31.3 - 33.5 33.5 - 35.7 35.7 - 37.9 37.9 - 40.1 40.1 - 42.3 42.3 - 44.5 44.5 - 46.7 46.7 - 48.9 48.9 - 51.0 51.0 - 53.2 53.2 - 55.4 55.4 - 57.6 57.6 - 59.8 59.8 - 62.0 62.0 - 64.2 64.2 - 66.4 66.4 - 68.6 GAIN OF VAROUT AMPLIFIER
dB -66 -56.0 -53.5 -50.9 -48.4 -45.9 -43.3 -40.8 -38.3 -35.7 -33.2 -30.7 -28.1 -25.6 -23.1 -20.5 -18.0 -15.5 -13.0 -10.4 -7.9 -5.3 -2.8 -0.3 2.3 4.8 7.3 9.9 12.4 14.9 17.5 20.0
> 70.6 >68.6 Tested in production. Remaining steps are specified by design.
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9
TPA3002D2
SLOS402A - DECEMBER 2002 - REVISED APRIL 2003
TYPICAL CHARACTERISTICS Table of Graphs
FIGURE Class-D Efficiency PO ICC IO(sd) Class-D Output power Class-D Supply current y Shutdown supply current Class-D Input resistance THD+N kSVR Class D Total harmonic distortion + noise Class-D Class-D Supply ripple rejection ratio Class-D Closed loop response Class-D Intermodulation performance Class-D Input offset voltage Class-D Crosstalk Class-D Mute attenuation Class-D Shutdown attenuation Class-D Common-mode rejection ratio VAROUT Input resistance VAROUT Noise VAROUT Closed Loop Response VAROUT Common-mode rejection ratio VAROUT Crosstalk vs Frequency vs Frequency vs Output power THD+N kSVR VAROUT Total harmonic distortion + noise VAROUT Supply ripple rejection ratio vs Output voltage vs Frequency vs Frequency vs Frequency vs Frequency vs Gain vs Frequency vs Common-mode input voltage vs Frequency vs Output power vs Load resistance vs Supply voltage vs Supply voltage vs Output Power vs Supply voltage vs Gain vs Frequency vs Output power vs Frequency 1 2 3 4 5 6 7 8, 9 10, 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
10
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TPA3002D2
SLOS402A - DECEMBER 2002 - REVISED APRIL 2003
TYPICAL CHARACTERISTICS
EFFICIENCY vs OUTPUT POWER
100 90 80 PO - Output Power - W 70 Efficiency - % 60 50 40 30 20 10 0 0 2 4 6 PO - Output Power - W 8 10 VCC = 12 V, Class-D, LC Filter, Resistive Load 12 10 8 6 4 2 0 8 RL = 8 16 14
OUTPUT POWER vs LOAD RESISTANCE
f = 1 kHz, LC Filter, Class-D, Resistive Load, TA = 25C VCC = 12 V, THD = 1%
VCC = 12 V, THD = 10%
VCC = 8.5 V, THD = 10%
VCC = 8.5 V, THD = 1% 16
10 12 14 RL - Load Resistance -
Figure 1
Figure 2
OUTPUT POWER vs SUPPLY VOLTAGE
14 17 16 I CC- Supply Current - mA
SUPPLY CURRENT vs SUPPLY VOLTAGE
SD = 2 V, MODE = 2 V, Class-D, No Load
12 P - Output Power - W O
15 14
10 8 Speaker 10% THD+N 8
13
6
8 Speaker 1% THD+N
12 11
4 TA = 25C 2 8.5 9 12 10 11 VCC - Supply Voltage - V 13 14
10 8.5
9
10 11 12 VCC - Supply Voltage - V
13
14
Figure 3
Figure 4
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TPA3002D2
SLOS402A - DECEMBER 2002 - REVISED APRIL 2003
TYPICAL CHARACTERISTICS
SUPPLY CURRENT vs OUTPUT POWER
2.5 I CC(sd)- Shutdown Supply Current - A VCC = 12 V, MODE = 2 V, Class-D, Stereo, TA = 25C 2.2 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 8.5 9
SHUTDOWN SUPPLY CURRENT vs SUPPLY VOLTAGE
SD = 0 V No Load
2.0 I CC - Supply Current - A
1.5 8 1.0 16 0.5
0 0 5 10 15 PO - Output Power - W 20
12 10 11 VCC - Supply Voltage - V
13
14
Figure 5
INPUT RESISTANCE vs GAIN
120 Class-D 100 RL - Input Resistance - k THD+N - Total Harmonic Distortion + Noise - % 1
Figure 6
TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY
VCC = 8 V RL = 8 Gain = +36 dB Class-D PO = 3 W
80
60
0.1
PO = 0.25 W
40
PO = 1.5 W
20
0 -50
0.01 20 100 1k 10k f - Frequency - Hz
-30
-10 10 Gain - dB
30
50
Figure 7
Figure 8
12
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TPA3002D2
SLOS402A - DECEMBER 2002 - REVISED APRIL 2003
TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY
THD+N - Total Harmonic Distortion + Noise - % 1 THD+N - Total Harmonic Distortion + Noise - % VCC = 12 V RL = 8 Gain = +36 dB Class-D 10
TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER
VCC = 8 V RL = 8 Gain = +13.2 dB Class-D 1
0.1
PO = 5 W
PO = 0.5 W
f = 1 kHz
0.1
f = 20 Hz
PO = 2.5 W
0.01 10 100 1k 10k f - Frequency - Hz
0.01 10 m
100 m
1
10
PO - Output Power - W
Figure 9
TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER
10 THD+N - Total Harmonic Distortion + Noise - % k SVR - Supply Ripple Rejection Ratio - dB VCC = 12 V RL = 8 Gain = +13.2 dB Class-D 1 f = 20 Hz -40 -45 -50 -55
Figure 10
SUPPLY RIPPLE REJECTION RATIO vs FREQUENCY
RL = 8 , C2p5 = 1 F, Class-D
VCC = 8 V -60 -65 VCC = 12 V -70 -75 -80 20
f = 1 kHz 0.1
0.01 10 m
100 m
1
10
100
PO - Output Power - W
1k f - Frequency - Hz
10 k 20 k
Figure 11
Figure 12
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13
TPA3002D2
SLOS402A - DECEMBER 2002 - REVISED APRIL 2003
TYPICAL CHARACTERISTICS
CLOSED LOOP RESPONSE
100 50 0 Phase Gain - dB -50 -100 -150 -200 -250 10 VCC = 12 V, Gain= +36 dB, RL = 8 Class-D 100 1k 10 k f - Frequency - Hz 100 k -50 -100 -150 -200 -250 1M Gain 100 50 0 Phase - Deg FFT - dBr 0 -20
INTERMODULATION PERFORMANCE
VCC = 12 V, 19 kHz, 20 kHz, 1:1, PO = 1 W, RL = 8 Gain= +13.2 dB, BW =20 Hz to 22 kHz, Class-D No Filter
-40 -60 -80 -100
-120
-140 50
100
1k f - Frequency - Hz
10 k
Figure 13
Figure 14
INPUT OFFSET VOLTAGE vs COMMON-MODE INPUT VOLTAGE
6 VCC = 12 V Class-D 0 -10 -20 4 3 Crosstalk - dB -30 -40 -50 -60 1 -70 0 -1 0 4 1 2 3 VICM - Common-Mode Input Voltage - V 5 -80 -90 20
CROSSTALK vs FREQUENCY
VCC = 12 V, C2p5 = 1 F, PO = 1 W, Gain = +13.2 dB, Class-D, RL = 8
5 VIO - Input Offset Voltage - mV
2
100
1k f - Frequency - Hz
10 k 20 k
Figure 15
Figure 16
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TPA3002D2
SLOS402A - DECEMBER 2002 - REVISED APRIL 2003
TYPICAL CHARACTERISTICS
MUTE ATTENUATION vs FREQUENCY
-30 -40 -50 Mute Attenuation - dB -60 -70 -80 -90 -100 -110 -120 -130 10 100 1k 10 k f - Frequency - Hz VCC = 12 V, RL = 8 , VI = 1 Vrms Class-D, VOLUME = 0 V -80 -85 Shutdown Attenuation - dB -90 -95 -100 -105 -110 -115 -120 -125 -130 10
SHUTDOWN ATTENUATION vs FREQUENCY
VCC = 12 V, RL = 8 , VI = 1 Vrms Gain = +13.2 dB, Class-D
100
1k
10 k
f - Frequency - Hz
Figure 17
COMMON-MODE REJECTION RATIO vs FREQUENCY
-40 CMRR - Common-Mode Rejection Ratio - dB VCC = 12 V, RL = 8 , C2p5 = 1 F, Class-D 160
Figure 18
INPUT RESISTANCE vs GAIN
VAROUT 140 RL - Input Resistance - k 120 100 80 60 40 20 0 -50
-50
-60
-70
-80
-90
-100 10 100 10 k 1k f - Frequency - Hz 100 k
-30
-10 Gain - dB
10
30
Figure 19
Figure 20
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TPA3002D2
SLOS402A - DECEMBER 2002 - REVISED APRIL 2003
TYPICAL CHARACTERISTICS
NOISE vs FREQUENCY
0 -20 -40 -60 Noise FFT - dBV -80 -100 -120 -140 -160 -180 -200 20 100 1k f - Frequency - Hz 10 k VCC = 12 V, Gain= +20 dB, RL = 8 Inputs AC Coupled to GND, VAROUT, No Filter Gain - dB 12.9 9.3 5.8 2.2 -1.3
CLOSED LOOP RESPONSE
175 Gain 150 125 100 50 Phase -4.8 -8.4 -11.9 -15.4 -19.0 -22.5 10 VCC = 12 V, Gain= +7.9 dB, RL = 8 VAROUT 100 1k 10 k 25 0 -25 -50 -75 -100 -125 -150 -175 f - Frequency - Hz Phase - Deg 75
Figure 21
Figure 22
COMMON-MODE REJECTION RATIO vs FREQUENCY
-40 CMRR - Common-Mode Rejection Ratio - dBv -42 -44 -46 -48 -50 -52 -54 -56 -58 -60 20 100 1k f- Frequency - Hz 10 k Crosstalk - dB VCC = 12 V, RL = 8 , C2P5 = 1 F, VAROUT 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 20
CROSSTALK (VAROUTL-TO-VAROUTR) vs FREQUENCY
VO = 1 Vrms, RL = 10 k, VAROUT G = 20 dB G = 10 dB G = 0 dB G = -10 dB
100
1k f - Frequency - Hz
10 k
Figure 23
Figure 24
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TPA3002D2
SLOS402A - DECEMBER 2002 - REVISED APRIL 2003
TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER
THD+N -Total Harmonic Distortion + Noise - % 20 THD+N -Total Harmonic Distortion + Noise - % 10 VCC = 12 V RL = 32 , Gain = +6 dB, VAROUT
TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT VOLTAGE
20 10 VCC = 12 V RL = 10 k, Gain = +6 dB VAROUT
2 1
2 1
0.2 0.1
f = 1 kHz f = 20 kHz
0.2 0.1 f = 1 kHz
0.02 0.01 f = 20 Hz
0.02 0.01
0.001
20
100 200
1m 2m
10 m 20 m
0.001 20 m
100 m
100 m
1
2
PO - Output Power - W
VO - Output Voltage - VRMS
Figure 25
Figure 26
TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY
THD+N -Total Harmonic Distortion + Noise - % 10 k SVR - Supply Ripple Rejection Ratio - dB VCC = 12 V RL = 32 , PO = 5 mW, Gain = +7.9 dB, VAROUT -40 -50 -60 -70
SUPPLY RIPPLE REJECTION RATIO vs FREQUENCY
2 1
VCC = 12 V VAROUT
0.2 0.1
-80 -90
0.02 0.01 0.005 20 100 1k f - Frequency - Hz 10 k
-100 -110 20
100
1k f - frequency - Hz
10 k
Figure 27
Figure 28
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17
TPA3002D2
SLOS402A - DECEMBER 2002 - REVISED APRIL 2003
APPLICATION INFORMATION
ROUT- ROUT+ C23 1 nF L2 (Bead) PGND 10 nF C18 C9 C10 C15 0.1uF 10 nF 0.1uF C19 GND VCC VCC PVCCR PVCCR
C22 1 nF
L1 (Bead) 10 F
BSRN
PVCCR
PGNDR
PVCCR
PGNDR
ROUTN
ROUTN
ROUTP
ROUTP
BSRP
C7 1 F GND PGND MODEB MODE C13 0.1 F C16 10 F VCC VAROUTR VAROUTL C14 C6 220pF 100 nF R1 120 k C8 AGND GND 1 F PGND AVDD
SHUTDOWN RIN- C2
C1 1 F
SD RINN RINP V2P5 LINP LINN AVDDREF VREF
VCLAMPR MODE_OUT MODE AVCC VAROUTR
AGND
1 F C5 C3 LIN- 1 F
1 F C4 1 F
TPA3002D2
VAROUTL AGND AVDD COSC ROSC AGND VCLAMPL
P3 50k
T7 VARDIFF P2 50 k T6 VARMAX P1 50 k T5 VOLUME REFGND PGNDL PGNDL LOUTN LOUTN PVCCL PVCCL PVCCL PVCCL C21 10 nF PGND L4 (Bead) LOUTP LOUTP BSLN
GND
AGND
C11 C20 10 nF 0.1 F C17 10 F L3 (Bead)
C12 0.1 F
C24 1nF
C25 1nF
LOUT-
LOUT+
VCC
Figure 29. Stereo Class-D With Single-Ended Inputs
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GND
VCC
BSLP
VCC
GND
ROUT+
ROUT- C22 1 nF C23 1 nF L1 (Bead) 10 F PGND 10 nF 0.1 F C19 C9 C10 AVDD R3 120 k L2 (Bead) C15 0.1 F
10 nF C18
VCC BSRP Rout2 1 k Cout2 Rout1 1 k Cin1 AVCC C13 0.1 F C16 10 F (T1) LINN VAROUTL AVDDREF T7 P3 50 k VARDIFF T6 VARMAX T5 VOLUME REFGND AGND VCLAMPL BSLP LOUTN LOUTN LOUTP PGNDL PVCCL PVCCL LOUTP PVCCL PVCCL PGNDL C8 1 F PGND P1 50 k GND BSLN P2 50 k VREF Cout1 Rhps1 10 k Cvcc Cin2 0.47 F (T2) 1 F Rin2 10 k AVDD AVDD COSC ROSC 220 pF C6 C14 100 nF R1 120 k 10 k Rhps2 10 k (T3) Rhpf2 TPA6110A2
BYP IN1
BSRN C7 VCLAMPR MODE_OUT MODE AVCC VAROUTR 1 F
PVCCR
PVCCR
ROUTP
ROUTP
PVCCR
PVCCR
ROUTN
ROUTN
PGNDR
PGNDR
220 F 220 F Rhpf1 10 k
SHUTDOWN RIN- RINN RINP 1 F V2P5 LINP 1 F C2 C5 AGND C3 LIN- C4 1 F 1 F C1 1 F
SD
1 F Rin1 10 k
(T4)
GND Vo1 SD VDD IN2 Vo2
AVDD
APPLICATION INFORMATION
Figure 30. Stereo Class-D With Single-Ended Inputs and Stereo Headphone Amplifier Interface
TPA3002D2
AGND
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AGND C11 C20 10 nF 0.1 F C17 10 F L3 (Bead) C12 C21 0.1 F 10 nF PGND L4 (Bead) C24 1 nF C25 1 nF VCC VCC GND LOUT- LOUT+
SLOS402A - DECEMBER 2002 - REVISED APRIL 2003
TPA3002D2
19
TPA3002D2
SLOS402A - DECEMBER 2002 - REVISED APRIL 2003
APPLICATION INFORMATION class-D operation
This section focuses on the class-D operation of the TPA3002D2. traditional class-D modulation scheme The traditional class-D modulation scheme, which is used in the TPA032D0x family, has a differential output where each output is 180 degrees out of phase and changes from ground to the supply voltage, VCC. Therefore, the differential prefiltered output varies between positive and negative VCC, where filtered 50% duty cycle yields 0 V across the load. The traditional class-D modulation scheme with voltage and current waveforms is shown in Figure 31. Note that even at an average of 0 V across the load (50% duty cycle), the current to the load is high, causing high loss, thus causing a high supply current.
OUTP
OUTN +12 V Differential Voltage Across Load 0V -12 V
Current
Figure 31. Traditional Class-D Modulation Scheme's Output Voltage and Current Waveforms Into an Inductive Load With No Input TPA3002D2 modulation scheme The TPA3002D2 uses a modulation scheme that still has each output switching from 0 to the supply voltage. However, OUTP and OUTN are now in phase with each other with no input. The duty cycle of OUTP is greater than 50% and OUTN is less than 50% for positive output voltages. The duty cycle of OUTP is less than 50% and OUTN is greater than 50% for negative output voltages. The voltage across the load sits at 0 V throughout most of the switching period, greatly reducing the switching current, which reduces any I2R losses in the load.
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TPA3002D2
SLOS402A - DECEMBER 2002 - REVISED APRIL 2003
APPLICATION INFORMATION
TPA3002D2 modulation scheme (continued)
OUTP
OUTN Differential Voltage Across Load Output = 0 V +12 V 0V -12 V
Current
OUTP
OUTN Differential Voltage Across Load -12 V +12 V 0V
Output > 0 V
Current
Figure 32. The TPA3002D2 Output Voltage and Current Waveforms Into an Inductive Load efficiency: LC filter required with the traditional class-D modulation scheme The main reason that the traditional class-D amplifier needs an output filter is that the switching waveform results in maximum current flow. This causes more loss in the load, which causes lower efficiency. The ripple current is large for the traditional modulation scheme, because the ripple current is proportional to voltage multiplied by the time at that voltage. The differential voltage swing is 2 x VCC, and the time at each voltage is half the period for the traditional modulation scheme. An ideal LC filter is needed to store the ripple current from each half cycle for the next half cycle, while any resistance causes power dissipation. The speaker is both resistive and reactive, whereas an LC filter is almost purely reactive. The TPA3002D2 modulation scheme has very little loss in the load without a filter because the pulses are very short and the change in voltage is VCC instead of 2 x VCC. As the output power increases, the pulses widen, making the ripple current larger. Ripple current could be filtered with an LC filter for increased efficiency, but for most applications the filter is not needed. An LC filter with a cutoff frequency less than the class-D switching frequency allows the switching current to flow through the filter instead of the load. The filter has less resistance than the speaker, which results in less power dissipation, therefore increasing efficiency.
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TPA3002D2
SLOS402A - DECEMBER 2002 - REVISED APRIL 2003
APPLICATION INFORMATION
effects of applying a square wave into a speaker Audio specialists have advised for years not to apply a square wave to speakers. If the amplitude of the waveform is high enough and the frequency of the square wave is within the bandwidth of the speaker, the square wave could cause the voice coil to jump out of the air gap and/or scar the voice coil. A 250-kHz switching frequency, however, does not significantly move the voice coil, as the cone movement is proportional to 1/f2 for frequencies beyond the audio band. Damage may occur if the voice coil cannot handle the additional heat generated from the high-frequency switching current. The amount of power dissipated in the speaker may be estimated by first considering the overall efficiency of the system. If the on-resistance (rds(on)) of the output transistors is considered to cause the dominant loss in the system, then the maximum theoretical efficiency for the TPA3002D2 with an 8- load is as follows: Efficiency (theoretical, %) + R L R )r L ds(on) 100% + 8 (8 ) 0.58) 100% + 93.24% (1)
The maximum measured output power is approximately 7.5 W with an 12-V power supply. The total theoretical power supplied (P(total)) for this worst-case condition would therefore be as follows: P (total) +P O Efficiency + 7.5 W 0.9324 + 8.04 W (2)
The efficiency measured in the lab using an 8- speaker was 89%. The power not accounted for as dissipated across the rds(on) may be calculated by simply subtracting the theoretical power from the measured power: Other losses + P (total) (measured) * P (total) (theoretical) + 8.43 * 8.04 + 0.387 W (3)
The quiescent supply current at 14 V is measured to be 14.3 mA. It can be assumed that the quiescent current encapsulates all remaining losses in the device, i.e., biasing and switching losses. It may be assumed that any remaining power is dissipated in the speaker and is calculated as follows: P (dis) + 0.387 W * (14 V 14.3 mA) + 0.19 W (4)
Note that these calculations are for the worst-case condition of 7.5 W delivered to the speaker. Since the 0.19 W is only 2.5% of the power delivered to the speaker, it may be concluded that the amount of power actually dissipated in the speaker is relatively insignificant. Furthermore, this power dissipated is well within the specifications of most loudspeaker drivers in a system, as the power rating is typically selected to handle the power generated from a clipping waveform. when to use an output filter Design the TPA3002D2 without the filter if the traces from amplifier to speaker are short (< 1 inch). Powered speakers, where the speaker is in the same enclosure as the amplifier, is a typical application for class-D without a filter. Most applications require a ferrite bead filter. The ferrite filter reduces EMI around 1 MHz and higher (FCC and CE only test radiated emissions greater than 30 MHz). When selecting a ferrite bead, choose one with high impedance at high frequencies, but very low impedance at low frequencies. Use a LC output filter if there are low frequency (<1 MHz) EMI sensitive circuits and/or there are long wires from the amplifier to the speaker.
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TPA3002D2
SLOS402A - DECEMBER 2002 - REVISED APRIL 2003
APPLICATION INFORMATION
when to use an output filter (continued)
33 H OUTP L1 33 H OUTN L2 C1 0.47 F C3 0.1 F C2 0.1 F
Figure 33. Typical LC Output Filter, Cutoff Frequency of 41 kHz, Speaker Impedance = 8
Ferrite Chip Bead OUTP 1 nF Ferrite Chip Bead OUTN 1 nF
Figure 34. Typical Ferrite Chip Bead Filter (Chip bead example: Fair-Rite 2512067007Y3)
volume control operation
Three pins labeled VOLUME, VARDIFF, and VARMAX control the class-D volume when driving speakers and the VAROUT volume. All of these pins are controlled with a dc voltage, which should not exceed VREF. When driving speakers in class-D mode, the VOLUME pin is the only pin that controls the gain. Table 1 lists the gain in class-D mode as determined by the voltage on the VOLUME pin in reference to the voltage on VREF. If using a resistor divider to fix the gain of the amplifier, the VREF terminal can be directly connected to AVDDREF and a resistor divider can be connected across VREF and REFGND. (See Figure 29 in the Applications Section). For fixed gain, calculate the resistor divider values necessary to center the voltage between the two percentage points given in the first column of Table 1. For example, if a gain of 10.7 dB is desired, the resistors in the divider network can both be 10 k. With these resistor values, a voltage of 50%*VREF will be present at the VOLUME pin and result in a class-D gain of 10.7 dB. If using a DAC to control the class-D gain, VREF and REFGND should be connected to the reference voltage for the DAC and the GND terminal of the DAC, respectively. For the DAC application, AVDDREF would be left unconnected. The reference voltage of the DAC provides the reference to the internal gain circuitry through the VREF input and any fluctuations in the DAC output voltage will not affect the TPA3002D2 gain. The percentages in the first column of Table 1 should be used for setting the voltages of the DAC when the voltage on the VOLUME terminal is increased. The percentages in the second column should be used for the DAC voltages when decreasing the voltage on the VOLUME terminal. Two lookup tables should be used in software to control the gain based on an increase or decrease in the desired system volume. This is explained further in a section below.
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TPA3002D2
SLOS402A - DECEMBER 2002 - REVISED APRIL 2003
APPLICATION INFORMATION volume control operation (continued)
If using an analog potentiometer to control the gain, it should be connected between VREF and REFGND. VREF can be connected to AVDDREF or an external voltage source, if desired. The first and second column in Table 1 should be used to determine the point at which the gain changes depending on the direction that the potentiometer is turned. If the voltage on the center tap of the potentiometer is increasing, the first column in Table 1 should be referenced to determine the trip points. If the voltage is decreasing, the trip points in the second column should be referenced. The trip point, where the gain actually changes, is different depending on whether the voltage on the VOLUME terminal is increasing or decreasing as a result of hysteresis about each trip point. The hysteresis ensures that the gain control is monotonic and does not oscillate from one gain step to another. A pictorial representation of the volume control can be found in Figure 36. The graph focuses on three gain steps with the trip points defined in the first and second columns of Table 1 for class-D gain. The dotted lines represent the hysteresis about each gain step.
VARDIFF and VARMAX operation
The TPA3002D2 allows the user to specify a difference between the class-D gain and VAROUT gain. This is desirable to avoid any listening discomfort when plugging in headphones. When interfacing with the variable outputs, the VARDIFF and VARMAX pins control the VAROUT channel gain proportional to the gain set by the voltage on the VOLUME pin. When VARDIFF=0 V, the difference between the class-D gain and the VAROUT gain is 16 dB. As the voltage on the VARDIFF terminal is increased, the VAROUT channel gain decreases. Internal to the TPA3002D2 device, the voltage on the VARDIFF terminal is subtracted from the voltage on the VOLUME terminal and this value is used to determine the VAROUT gain. Some audio systems require that the gain be limited in the VAROUT mode to a level that is comfortable for headphone listening. The VARMAX terminal controls the maximum gain for the VAROUT channels. The functionality of the VARDIFF and VARMAX pin are combined to fix the VAROUT channel gain. A block diagram of the combined functionality is shown in Figure 35. The value obtained from the block diagram for VAROUT_VOLUME is a DC voltage that can be used in conjunction with Table 2 to determine the VAROUT channel gain. Table 2 lists the gain in VAROUT mode as determined by the VAROUT_VOLUME voltage in reference to the voltage on VREF. The timing of the volume control circuitry is controlled by an internal 30Hz clock. This clock determines the rate at which the gain changes when adjusting the voltage on the external volume control pins. The gain updates every 4 clock cycles (nominally 133ms based on a 30Hz clock) to the next step until the final desired gain is reached. For example, if the TPA3002D2 is currently in the +0.53 db class-D gain step and the VOLUME pin is adjusted for maximum gain at +36 dB, the time required for the gain to reach 36dB is 14 steps x 133ms/step = 1.862 seconds. Referencing table 1, there are 14 steps between the +0.53 dB gain step and the maximum gain step of +36 dB.
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TPA3002D2
SLOS402A - DECEMBER 2002 - REVISED APRIL 2003
APPLICATION INFORMATION VARDIFF and VARMAX operation (continued)
VARDIFF (V) VARMAX (V)
- + VOLUME (V) VOLUME-VARDIFF
Is VARMAX> YES (VOLUME-VARDIFF) VAROUT_VOLUME (V) = VOLUME (V) - VARDIFF (V) ?
NO VAROUT_VOLUME (V) = VARMAX (V)
Figure 35. Block Diagram of VAROUT Volume Control
Decreasing Voltage on VOLUME Terminal 5.6
Class-D Gain - dB
3.1 Increasing Voltage on VOLUME Terminal
0.5
2.00 (40.1%*VREF)
2.21 2.10 2.11 (44.1%*VREF) (41.9%*VREF) (42.3%*VREF) Voltage on VOLUME Pin - V
Figure 36. DC Volume Control Operation, VREF = 5 V
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25
TPA3002D2
SLOS402A - DECEMBER 2002 - REVISED APRIL 2003
APPLICATION INFORMATION MODE operation
The MODE pin is an input for controlling the output mode of the TPA3002D2. A logic HIGH on this pin disables the Class-D outputs. A logic LOW on this pin enables the class-D outputs. The VAROUT outputs are active in both modes and can be used as line level inputs to an external powered subwoofer while driving internal stereo speakers with the class-D outputs. The trip levels are defined in the specifications table. For interfacing with an external headphone amplifier like the TPA6110A2, the MODE pin can be connected to the switch on a headphone jack. When configured like Figure 30, the class-D outputs will be disabled when a headphone plug is inserted into the headphone jack.
MODE_OUT operation
The MODE_OUT pin is an output for controlling the SHUTDOWN pin on an external headphone amplifier like the TPA6110A2 or for interfacing with other logic. The output voltages for a given load condition are given in the specifications table. This output is controlled by the MODE pin logic. When the MODE input is driven to a logic low, the MODE_OUT output drives to a logic high. Conversely, when the MODE pin is driven to a logic high, the MODE_OUT output drives LOW. The MODE_OUT output is simply the inverted state of the MODE input. It is designed in this manner because the TPA6110A2 SHUTDOWN input is active high. This allows the TPA3002D2 to place the TPA6110A2 into the shutdown state when driving internal speakers in the Class-D mode. Conversely, the MODE_OUT pin drives low to enable the TPA6110A2 headphone amplifier when headphones are plugged into the headphone jack and the MODE input is driven high.
selection of COSC and ROSC
The switching frequency is determined using the values of the components connected to ROSC (pin 20) and COSC (pin 21) and may be calculated with the following equation: fOSC = 6.6 / (ROSC * COSC) The frequency may be varied from 225 kHz to 275 kHz by adjusting the values chosen for ROSC and COSC. The recommended values are COSC = 220 pF, ROSC=120 k for a switching frequency of 250 kHz.
internal 2.5-V bias generator capacitor selection
The internal 2.5-V bias generator (V2P5) provides the internal bias for the preamplifier stages on both the class-D amplifiers and the variable amplifiers. The external input capacitors and this internal reference allow the inputs to be biased within the optimal common-mode range of the input preamplifiers. The selection of the capacitor value on the V2P5 terminal is critical for achieving the best device performance. During startup or recovery from the shutdown state, the V2P5 capacitor determines the rate at which the amplifier starts up. When the voltage on the V2P5 capacitor equals 0.75xV2P5, or 75% of its final value, the device turns on and the class-D outputs start switching. The startup time is not critical for the best depop performance since any pop sound that is heard is the result of the class-D outputs switching on and not the startup time. However, at least a 0.47-F capacitor is recommended for the V2P5 capacitor. A secondary function of the V2P5 capacitor is to filter high frequency noise on the internal 2.5-V bias generator.
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TPA3002D2
SLOS402A - DECEMBER 2002 - REVISED APRIL 2003
APPLICATION INFORMATION input resistance
Each gain setting is achieved by varying the input resistance of the amplifier, which can range from its smallest value to over six times that value. As a result, if a single capacitor is used in the input high-pass filter, the -3 dB or cutoff frequency also changes by over six times.
Zf Ci Input Signal IN Zi
The -3-dB frequency can be calculated using equation 5. Input impedance (Zi) vs Gain can be found in Figure 7. f *3dB + 1 2p Z iC i (5)
input capacitor, Ci
In the typical application an input capacitor (Ci) is required to allow the amplifier to bias the input signal to the proper dc level (V2P5)for optimum operation. In this case, Ci and the input impedance of the amplifier (Zi) form a high-pass filter with the corner frequency determined in equation 6.
-3 dB
(6)
1 fc + 2 p Zi Ci
fc
The value of Ci is important, as it directly affects the bass (low frequency) performance of the circuit. Consider the example where Zi is 20 k and the specification calls for a flat bass response down to 20 Hz. Equation 6 is reconfigured as equation 7. Ci + 1 2p Z i f c (7)
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27
TPA3002D2
SLOS402A - DECEMBER 2002 - REVISED APRIL 2003
APPLICATION INFORMATION
In this example, Ci is 0.4 F, so one would likely choose a value in the range of 0.47 F to 1 F. If the gain is known and will be constant, use Zi from Figure 7 (Input Impedance vs Gain) to calculate Ci. Calculations for Ci should be based off the impedance at the lowest gain step intended for use in the system. A further consideration for this capacitor is the leakage path from the input source through the input network (Ci) and the feedback network to the load. This leakage current creates a dc offset voltage at the input to the amplifier that reduces useful headroom, especially in high gain applications. For this reason a low-leakage tantalum or ceramic capacitor is the best choice. When polarized capacitors are used, the positive side of the capacitor should face the amplifier input in most applications as the dc level there is held at 2.5 V, which is likely higher than the source dc level. Note that it is important to confirm the capacitor polarity in the application. power supply decoupling, CS The TPA3002D2 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to ensure the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also prevents oscillations for long lead lengths between the amplifier and the speaker. The optimum decoupling is achieved by using two capacitors of different types that target different types of noise on the power supply leads. For higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR) ceramic capacitor, typically 0.1 F placed as close as possible to the device VCC lead works best. For filtering lower-frequency noise signals, a larger aluminum electrolytic capacitor of 10 F or greater placed near the audio power amplifier is recommended. The 10-F capacitor also serves as local storage capacitor for supplying current during large signal transients on the amplifier outputs. BSN and BSP capacitors The full H-bridge output stages use only NMOS transistors. They therefore require bootstrap capacitors for the high side of each output to turn on correctly. A 10-nF ceramic capacitor, rated for at least 25 V, must be connected from each output to its corresponding bootstrap input. Specifically, one 10-nF capacitor must be connected from xOUTP to xBSP, and one 10-nF capacitor must be connected from xOUTN to xBSN. (See the application circuit diagram in Figure 29.) VCLAMP capacitors To ensure that the maximum gate-to-source voltage for the NMOS output transistors is not exceeded, two internal regulators clamp the gate voltage. Two 1-F capacitors must be connected from VCLAMPL (pin 25) and VCLAMPR (pin 36) to ground and must be rated for at least 25 V. The voltages at the VCLAMP terminals vary with VCC and may not be used for powering any other circuitry. internal regulated 5-V supply (AVDD) The AVDD terminal (pin 29) is the output of an internally-generated 5-V supply, used for the oscillator, preamplifier, and volume control circuitry. It requires a 0.1-F to 1-F capacitor, placed very close to the pin, to ground to keep the regulator stable. The regulator may be used to power an external headphone amplifier or other circuitry, up to a current limit specified in the specification table.
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TPA3002D2
SLOS402A - DECEMBER 2002 - REVISED APRIL 2003
APPLICATION INFORMATION
AVDD - POWER-UP RESPONSE
Power-Up
Ch1 (AVDD)
AVDD (pin 29)
Ch2 (AVCC)
AVCC (pin 33)
Ch1 5.00 V/div
Ch2 2.00 V/div
M 10.0 s
Figure 37. Power-Up Response differential input The differential input stage of the amplifier cancels any noise that appears on both input lines of the channel. To use the TPA3002D2 EVM with a differential source, connect the positive lead of the audio source to the INP input and the negative lead from the audio source to the INN input. To use the TPA3002D2 with a single-ended source, ac ground the INP input through a capacitor equal in value to the input capacitor on INN and apply the audio source to the INN input. In a single-ended input application, the INP input should be ac-grounded at the audio source instead of at the device input for best noise performance.
SD operation
The TPA3002D2 employs a shutdown mode of operation designed to reduce supply current (ICC) to the absolute minimum level during periods of nonuse for power conservation. The SD input terminal should be held high (see specification table for trip point)during normal operation when the amplifier is in use. Pulling SD low causes the outputs to mute and the amplifier to enter a low-current state, ICC(SD) = 10 A. SD should never be left unconnected, because amplifier operation would be unpredictable. For the best power-off pop performance, the amplifier should be placed in the shutdown mode prior to removing the power supply voltage.
using low-ESR capacitors
Low-ESR capacitors are recommended throughout this application section. A real (as opposed to ideal) capacitor can be modeled simply as a resistor in series with an ideal capacitor. The voltage drop across this resistor minimizes the beneficial effects of the capacitor in the circuit. The lower the equivalent value of this resistance the more the real capacitor behaves like an ideal capacitor.
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TPA3002D2
SLOS402A - DECEMBER 2002 - REVISED APRIL 2003
APPLICATION INFORMATION short-circuit protection
The TPA3002D2 has short circuit protection circuitry on the outputs that prevents damage to the device during output-to-output shorts, output-to-GND shorts, and output-to-VCC shorts. When a short-circuit is detected on the outputs, the part immediately disables the output drive. This is a latched fault and must be reset by cycling the voltage on the SD pin to a logic low and back to the logic high state for normal operation. This will clear the short-circuit flag and allow for normal operation if the short was removed. If the short was not removed, the protection circuitry will again activate. The trip-point for the short-circuit protection is nominally set at 8 A. However, this trip point can vary with PCB layout and the separation of AVCC and PVCC. It is important to connect the AVCC pin as close as possible to all of the PVCC pins with a wide (>20 mils) trace. This minimizes the inductance between the two pins and allows the short-circuit protection to trip at the nominal current. If the inductance between these two pins is large, the short-circuit protection may inadvertently trip when drive low impedance loads into heavy clipping.
thermal protection
Thermal protection on the TPA3002D2 prevents damage to the device when the internal die temperature exceeds 150C. There is a 15 degree tolerance on this trip point from device to device. Once the die temperature exceeds the thermal set point, the device enters into the shutdown state and the outputs are disabled. This is not a latched fault. The thermal fault is cleared once the temperature of the die is reduced by 20C. The device begins normal operation at this point with no external system interaction.
thermal considerations: output power and maximum ambient temperature
To calculate the maximum ambient temperature, the following equation may be used: TAmax = TJmax - JAPDissipated where: TJmax = 150C JA = 19C/W (2-Layer PCB, 5 sq. in. copper, see Figure 38) (8)
To estimate the power dissipation, the following equation may be used: PDissipated = PO(average) x ((1 / Efficiency) - 1) Efficiency = ~85% for an 8- load = ~75% for a 4- load (9)
Example. What is the maximum ambient temperature for an application that requires the TPA3002D2 to drive 7.5 W into an 8- speaker? (stereo?) PDissipated = 15 W x ((1 / 0.85) - 1) = 2.65 W TAmax = 150C - (19C/W x 2.65 W) = 99.65C This calculation shows that the TPA3002D2 can drive 7.5 W into an 8- speaker up to the absolute maximum ambient temperature rating of 85C, which must never be exceeded. Figures 39 and 40 show the results of several thermal experiments conducted with the TPA3002D2. Both figures show that the best thermal performance can be achieved with more copper area for heat dissipation and an adequate number of thermal vias. (PO = 7.5 W * 2)
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TPA3002D2
SLOS402A - DECEMBER 2002 - REVISED APRIL 2003
APPLICATION INFORMATION thermal considerations: output power and maximum ambient temperature (continued)
Figure 38 shows two curves for a 2-layer and 4-layer PCB. The 2-layer PCB layout was tightly controlled with a fixed amount of 2 oz. copper on the bottom layer of the PCB. The amount of copper is shown on the x-axis. Nine thermal vias of 13 mil (0.33mm) diameter were drilled under the PowerPad and connected to the bottom layer. The top layer only consisted of traces for signal routing. The 4-layer PCB layout was also tightly controlled with a fixed amount of 2 oz. copper in middle GND layer. The top layer only consisted of traces for signal routing. The bottom and other middle layer were left blank. Nine thermal vias of 0.33mm diameter were drilled under the PowerPad and connected to the middle layer. Figure 39 shows the effect of the number of thermal vias drilled under the PowerPad on the thermal performance of the PCB. The experiment was conducted with a 2-layer PCB and 3 square inches of copper on the bottom layer. For the best thermal performance, at least 16 vias in a 4x4 pattern should be used under the PowerPad. Refer to the TPA3002D2 EVM User's Manual, SLOU151, for an example layout with a 4x4 via pattern. PCB gerber files are available at request.
printed circuit board (PCB) layout
Because the TPA3002D2 is a class-D amplifier that switches at a high frequency, the layout of the printed circuit board (PCB) should be optimized according to the following guidelines for the best possible performance.
D Decoupling capacitors -- As described on page 28, the high-frequency 0.1-uF decoupling capacitors
should be placed as close to the PVCC (pin 14, 15, 22, 23, 38, 39, 46, 47) and AVCC (pin 33) terminals as possible. The V2P5 (pin 4) capacitor, AVDD (pin 29) capacitor, and VCLAMP (pins 25, 36) capacitor should also be placed as close to the device as possible. Large (10 uF or greater) bulk power supply decoupling capacitors should be placed near the TPA3002D2 on the PVCCL, PVCCR, and AVCC terminals.
D Grounding -- The AVCC (pin 33) decoupling capacitor, AVDD (pin 29) capacitor, V2P5 (pin 4) capacitor,
COSC (pin 28) capacitor, and ROSC (pin 27) resistor should each be grounded to analog ground (AGND, pin 26 and pin 30). The PVCC (pin 9 and pin 16) decoupling capacitors should each be grounded to power ground (PGND, pins 18, 19, 42, 43). Analog ground and power ground may be connected at the PowerPAD, which should be used as a central ground connection or star ground for the TPA3002D2. Basically, an island should be created with a single connection to PGND at the PowerPAD.
D Output filter -- The ferrite EMI filter (Figure 34, page 23) should be placed as close to the output terminals
as possible for the best EMI performance. The LC filter (Figure 33, page 23 should be placed close to the outputs. The capacitors used in both the ferrite and LC filters should be grounded to power ground.
D PowerPAD -- The PowerPAD must be soldered to the PCB for proper thermal performance and optimal
reliability. The dimensions of the PowerPAD thermal land should be 5 mm by 5 mm (197 mils by 197 mils). The PowerPAD size measures 4.55 x 4.55 mm. Four rows of solid vias (four vias per row, 0.3302 mm or 13 mils diameter) should be equally spaced underneath the thermal land. The vias should connect to a solid copper plane, either on an internal layer or on the bottom layer of the PCB. The vias must be solid vias, not thermal relief or webbed vias. For additional information, please refer to the PowerPAD Thermally Enhanced Package application note, TI literature number SLMA002. For an example layout, please refer to the TPA3002D2 Evaluation Module (TPA3002D2EVM) User Manual, TI literature number SLOU151. Both the EVM user manual and the PowerPAD application note are available on the TI web site at http://www.ti.com.
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TPA3002D2
SLOS402A - DECEMBER 2002 - REVISED APRIL 2003
APPLICATION INFORMATION
THERMAL RESISTANCE vs COPPER AREA 2-LAYER PCB
35 JA - Thermal Resistance - C/W 35
THERMAL RESISTANCE vs COPPER AREA 4-LAYER PCB
30
JA - Thermal Resistance - C/W 1 1.5 2 2.5 3 3.5 4 Copper Area - sq. Inches 4.5 5
30
25
25
20
20
15
15 1 2 3 4 Copper Area - sq. Inches 5
Figure 38. Thermal Resistance
THERMAL RESISTANCE vs THERMAL VIA QUANTITY 2-LAYER PCB
25 JA - Thermal Resistance - C/W
24
23
22
21
20 4
6 8 10 12 14 Thermal Via Quantity (13 Mil Diameter)
16
Figure 39. Thermal Resistance
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TPA3002D2
SLOS402A - DECEMBER 2002 - REVISED APRIL 2003
APPLICATION INFORMATION basic measurement system
This application note focuses on methods that use the basic equipment listed below:
D D D D D D D D D
Audio analyzer or spectrum analyzer Digital multimeter (DMM) Oscilloscope Twisted pair wires Signal generator Power resistor(s) Linear regulated power supply Filter components EVM or other complete audio circuit
Figure 40 shows the block diagrams of basic measurement systems for class-AB and class-D amplifiers. A sine wave is normally used as the input signal since it consists of the fundamental frequency only (no other harmonics are present). An analyzer is then connected to the APA output to measure the voltage output. The analyzer must be capable of measuring the entire audio bandwidth. A regulated dc power supply is used to reduce the noise and distortion injected into the APA through the power pins. A System Two audio measurement system (AP-II) (Reference 1) by Audio Precision includes the signal generator and analyzer in one package. The generator output and amplifier input must be ac-coupled. However, the EVMs already have the ac-coupling capacitors, (CIN), so no additional coupling is required. The generator output impedance should be low to avoid attenuating the test signal, and is important since the input resistance of APAs is not very high (about 10 k). Conversely the analyzer-input impedance should be high. The output impedance, ROUT, of the APA is normally in the hundreds of milliohms and can be ignored for all but the power-related calculations. Figure 40(a) shows a class-AB amplifier system, which is relatively simple because these amplifiers are linear their output signal is a linear representation of the input signal. They take analog signal input and produce analog signal output. These amplifier circuits can be directly connected to the AP-II or other analyzer input. This is not true of the class-D amplifier system shown in Figure 40(b), which requires low pass filters in most cases in order to measure the audio output waveforms. This is because it takes an analog input signal and converts it into a pulse-width modulated (PWM) output signal that is not accurately processed by some analyzers.
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33
TPA3002D2
SLOS402A - DECEMBER 2002 - REVISED APRIL 2003
APPLICATION INFORMATION
Power Supply
Signal Generator
APA
RL
Analyzer 20 Hz - 20 kHz
(a) Basic Class-AB
Power Supply
Low-Pass RC Filter Signal Generator Class-D APA RL Low-Pass RC Filter Analyzer 20 Hz - 20 kHz
(b) Filter-Free and Traditional Class-D
Figure 40. Audio Measurement Systems The TPA3002D2 uses a modulation scheme that does not require an output filter for operation, but they do sometimes require an RC low-pass filter when making measurements. This is because some analyzer inputs cannot accurately process the rapidly changing square-wave output and therefore record an extremely high level of distortion. The RC low-pass measurement filter is used to remove the modulated waveforms so the analyzer can measure the output sine wave.
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TPA3002D2
SLOS402A - DECEMBER 2002 - REVISED APRIL 2003
APPLICATION INFORMATION differential input and BTL output
All of the class-D APAs and many class-AB APAs have differential inputs and bridge-tied load (BTL) outputs. Differential inputs have two input pins per channel and amplify the difference in voltage between the pins. Differential inputs reduce the common-mode noise and distortion of the input circuit. BTL is a term commonly used in audio to describe differential outputs. BTL outputs have two output pins providing voltages that are 180 degrees out of phase. The load is connected between these pins. This has the added benefits of quadrupling the output power to the load and eliminating a dc blocking capacitor. A block diagram of the measurement circuit is shown in Figure 41. The differential input is a balanced input, meaning the positive (+) and negative (-) pins will have the same impedance to ground. Similarly, the BTL output equates to a balanced output.
Evaluation Module Generator CIN VGEN RGEN CIN RGEN RIN RIN ROUT ROUT RL Low-Pass RC Filter Audio Power Amplifier Low-Pass RC Filter RANA RANA CANA CANA Analyzer
Twisted-Pair Wire
Twisted-Pair Wire
Figure 41. Differential Input--BTL output Measurement Circuit The generator should have balanced outputs and the signal should be balanced for best results. An unbalanced output can be used, but it may create a ground loop that will affect the measurement accuracy. The analyzer must also have balanced inputs for the system to be fully balanced, thereby cancelling out any common mode noise in the circuit and providing the most accurate measurement. The following general rules should be followed when connecting to APAs with differential inputs and BTL outputs:
D D D D D
Use a balanced source to supply the input signal. Use an analyzer with balanced inputs. Use twisted-pair wire for all connections. Use shielding when the system environment is noisy. Ensure the cables from the power supply to the APA, and from the APA to the load, can handle the large currents (see Table 3).
Table 3 shows the recommended wire size for the power supply and load cables of the APA system. The real concern is the dc or ac power loss that occurs as the current flows through the cable. These recommendations are based on 12-inch long wire with a 20-kHz sine-wave signal at 25C.
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35
TPA3002D2
SLOS402A - DECEMBER 2002 - REVISED APRIL 2003
APPLICATION INFORMATION
Table 3. Recommended Minimum Wire Size for Power Cables
POUT (W) 10 2 1 < 0.75 RL () 4 4 8 8 AWG SIZE 18 18 22 22 22 22 28 28 DC POWER LOSS (MW) 16 3.2 2.0 1.5 40 8.0 8.0 6.1 AC POWER LOSS (MW) 18 3.7 2.1 1.6 42 8.5 8.1 6.2
Class-D RC low-pass filter
An RC filter is used to reduce the square-wave output when the analyzer inputs cannot process the pulse-width modulated class-D output waveform. This filter has little effect on the measurement accuracy because the cutoff frequency is set above the audio band. The high frequency of the square wave has negligible impact on measurement accuracy because it is well above the audible frequency range and the speaker cone cannot respond at such a fast rate. The RC filter is not required when an LC low-pass filter is used, such as with the class-D APAs that employ the traditional modulation scheme (TPA032D0x, TPA005Dxx). The component values of the RC filter are selected using the equivalent output circuit as shown in Figure 42. RL is the load impedance that the APA is driving for the test. The analyzer input impedance specifications should be available and substituted for RANA and CANA. The filter components, RFILT and CFILT, can then be derived for the system. The filter should be grounded to the APA near the output ground pins or at the power supply ground pin to minimize ground loops.
Load RC Low-Pass Filters RFILT CFILT RL VL= VIN RFILT CFILT To APA GND CANA RANA VOUT CANA AP Analyzer Input
RANA
Figure 42. Measurement Low-Pass Filter Derivation Circuit--Class-D APAs
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TPA3002D2
SLOS402A - DECEMBER 2002 - REVISED APRIL 2003
APPLICATION INFORMATION
The transfer function for this circuit is shown in equation (10) where O = REQCEQ, REQ = RFILTRANA and CEQ = (CFILT + CANA). The filter frequency should be set above fMAX, the highest frequency of the measurement bandwidth, to avoid attenuating the audio signal. Equation (11) provides this cutoff frequency, fC. The value of RFILT must be chosen large enough to minimize current that is shunted from the load, yet small enough to minimize the attenuation of the analyzer-input voltage through the voltage divider formed by RFILT and RANA. A rule of thumb is that RFILT should be small (~100 ) for most measurements. This reduces the measurement error to less than 1% for RANA 10 k. R + ANA )R ANA FILT w 1)j w O (10) (11) R
V
OUT V IN
f
C
+2
f
MAX
An exception occurs with the efficiency measurements, where RFILT must be increased by a factor of ten to reduce the current shunted through the filter. CFILT must be decreased by a factor of ten to maintain the same cutoff frequency. See Table 2 for the recommended filter component values. Once fC is determined and RFILT is selected, the filter capacitance is calculated using equation (12). When the calculated value is not available, it is better to choose a smaller capacitance value to keep fC above the minimum desired value calculated in equation (11). C FILT + 1 2p f C R FILT (12)
Table 2 shows recommended values of RFILT and CFILT based on common component values. The value of fC was originally calculated to be 28 kHz for an fMAX of 20 kHz. CFILT, however, was calculated to be 57000 pF, but the nearest values of 56000 pF and 51000 pF were not available. A 47000 pF capacitor was used instead, and fC is 34 kHz, which is above the desired value of 28 kHz. Table 4. Typical RC Measurement Filter Values
MEASUREMENT Efficiency All other measurements RFILT 1 000 100 CFILT 5 600 pF 56 000 pF
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37
TPA3002D2
SLOS402A - DECEMBER 2002 - REVISED APRIL 2003
MECHANICAL DATA
PHP (S-PQFP-G48)
0,50 36 25 0,27 0,17
PowerPAD PLASTIC QUAD FLATPACK
0,08 M
37
24 Thermal Pad (see Note D)
48
13 0,13 NOM 1 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 1,05 0,95 Seating Plane 12 Gage Plane 0,25 0,15 0,05 0- 7
0,75 0,45
1,20 MAX
0,08
4146927/A 01/98 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane. This pad is electrically and thermally connected to the backside of the die and possibly selected leads. E. Falls within JEDEC MS-026
PowerPAD is a trademark of Texas Instruments.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
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Copyright 2003, Texas Instruments Incorporated

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