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| TMS320VC5502 Fixed-Point Digital Signal Processor Data Manual Literature Number: SPRS208 December 2002 PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2002, Texas Instruments Incorporated REVISION HISTORY REVISION DATE PRODUCT STATUS HIGHLIGHTS These changes are made to SPRS166A (TMS320VC5502-200 Data Manual) to create SPRS208 (TMS320VC5502-300 Data Manual): Changed Instruction Cycle Time to 3.33 ns for 300-MHz Clock Rate. Updated Table 2-3, Signal Descriptions. Updated Figure 3-1, Block Diagram of the TMS320VC5502. Added Table 3-3, Boot Configuration Selection Via the BOOTM[2:0] Pins, which describes the different boot modes that are available for the 5502. Updated Section 3.1.1, On-Chip ROM. Updated Section 3.1.4, Boot Configuration. Updated Section 3.2, Peripherals. Restructured and added information to Section 3.3, Configurable External Ports and Signals. Updated Section 3.3.1, Parallel Port Mux. Updated Section 3.3.2, Host Port Mux. * December 2002 Product Preview Updated Section 3.3.3, Serial Port Mux. Updated Section 3.3.4, External Bus Selection Register (XBSR). Updated Table 3-7, External Bus Selection Register Bit Field Description. Updated Section 3.4, Timers. Updated Section 3.5, Universal Asynchronous Receiver/Transmitter (UART). Updated Figure 3-6, UART Functional Block Diagram. Updated Figure 3-7, I2C Module Block Diagram. Updated Section 3.7, Host-Port Interface (HPI). Updated Section 3.8, Direct Memory Access (DMA) Controller. Updated Figure 3-8, DMA Channel 0 Control Register Layout (0x0C01). Updated Table 3-9, Synchronization Control Function. Updated Section 3.9, System Clock Generator. (Continued on next page) iii REVISION HISTORY (CONTINUED) REVISION DATE PRODUCT STATUS HIGHLIGHTS Updated Figure 3-9, PLL and Clock Generator Logic. Updated Section 3.9.1.1, Internal System Oscillator With External Crystal. Updated Section 3.9.3, EMIF Input Clock Selection. Updated Section 3.9.4.2, Fast Peripherals Clock Group. Updated Section 3.9.4.3, Slow Peripherals Clock Group. Updated Section 3.9.4.4, External Memory Interface Clock Group. Updated description of STABLE bit in Table 3-11, PLL Control/Status Register Bit Field Description. Updated Table 3-12, PLL Multiplier Control Register Bit Field Description. Updated Table 3-13, PLL Divider 0 Register Bit Field Description. Updated Section 3.9.5.10, CLKOUT Selection Register (CLKOUTSR). Updated Section 3.9.6, Reset Sequence. * (Continued) December 2002 Product Preview Updated Section 3.10, Idle Control. Updated Section 3.10.1, Clock Domains. Updated Table 3-23, Peripheral Behavior at Entering IDLE State. Updated Section 3.10.4.7, IDLE3 Mode With Internal Oscillator Disabled Wake-up Procedure. Updated Section 3.10.6, Clock State of Multiplexed Modules. Updated Table 3-26, IDLE Configuration Register Bit Field Description. Updated Section 3.11, General-Purpose I/O (GPIO). Renamed Section 3.13 from "System Configuration and Status Registers" to "Internal Ports and System Registers". Updated Section 3.13, Internal Ports and System Registers. Updated Section 3.13.4, System Configuration Register (CONFIG). Updated Figure 3-46, System Configuration Register Layout (0x07FD). (Continued on next page) iv REVISION HISTORY (CONTINUED) REVISION DATE PRODUCT STATUS HIGHLIGHTS Updated Table 3-51, System Configuration Register Bit Field Description. Updated Section 3.13.5, Time-Out Control Register (TOCR). Updated Table 3-53, CPU Memory-Mapped Registers. Updated Table 3-54, Peripheral Bus Controller Configuration Registers. Added DMA_GTCR to Table 3-56, DMA Configuration Registers. Updated Table 3-57, Instruction Cache Registers. Updated Table 3-60, Timers. Updated Table 3-61, Multichannel Serial Port #0. Updated Table 3-64, HPI. (Continued on next page) Updated Table 3-66, Device Revision ID. Updated Table 3-67, I2C. * (Continued) December 2002 Product Preview Updated Table 3-68, UART. Updated Table 3-71, CLKOUT Selector Register. Updated Table 3-72, Clock Controller Registers. Updated Table 3-74, Interrupt Table. Updated Section 3.16.1, IFR and IER Registers. Updated Figure 3-48, IFR0, IER0, DBIFR0, and DBIER0 Registers Layout. Added Section 5, Device and Development-Support Tool Nomenclature. Updated Table 6-1, Thermal Resistance Characteristics. Updated MIN value of Parameter E1 in Table 6-6, EMIF Timing Requirements for ECLKIN. Updated description of td(EKO1H-CEV) in Table 6-14, EMIF Synchronous DRAM Cycle Switching Characteristics. Updated Section 6.12, Reset Timings. Updated Table 6-18, Reset Switching Characteristics . (Continued on next page) v REVISION HISTORY (CONTINUED) REVISION DATE PRODUCT STATUS HIGHLIGHTS Updated Section 6.15.1, TIM0/TIM1/WDTOUT Timings: - Added Table 6-24, TIM0/TIM1/WDTOUT Pins Configured as Inputs Timing Requirements. - Updated Table 6-25, TIM0/TIM1/WDTOUT Pins Configured as Outputs Switching Characteristics. - Added Figure 6-26, TIM0/TIM1/WDTOUT Timings When Configured as Inputs. - Updated Figure 6-27, TIM0/TIM1/WDTOUT Timings When Configured as Outputs. December 2002 Product Preview Updated Section 6.16.3, McBSP as SPI Master or Slave Timing. Updated Table 6-34, McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1). Updated Section 6.17, HPI Timings. Updated Section 6.18, I2C Timing. * (Continued) vi Contents Contents Section 1 2 TMS320VC5502 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.1 Ball Grid Array (GGW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.2 Low-Profile Quad Flatpack (PGF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.1 On-Chip ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.2 On-Chip Dual-Access RAM (DARAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.3 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.4 Boot Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 Configurable External Ports and Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.1 Parallel Port Mux . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.2 Host Port Mux . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.3 Serial Port Mux . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.4 External Bus Selection Register (XBSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.1 Timer Signal Selection Register (TSSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 Universal Asynchronous Receiver/Transmitter (UART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 Inter-Integrated Circuit (I2C) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7 Host-Port Interface (HPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8 Direct Memory Access (DMA) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.1 DMA Channel 0 Control Register (DMA_CCR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9 System Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9.1 Input Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9.2 Clock Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9.3 EMIF Input Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9.4 Changing the Clock Group Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9.5 PLL Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9.6 Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.10 Idle Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.10.1 Clock Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.10.2 IDLE Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.10.3 Module Behavior at Entering IDLE State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.10.4 Wake-Up Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.10.5 Auto-Wakeup/Idle Function for McBSP and DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.10.6 Clock State of Multiplexed Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.10.7 IDLE Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 1 2 2 3 3 5 7 17 18 18 19 20 21 21 22 22 23 24 25 26 27 29 31 32 33 33 35 35 37 37 38 40 49 50 50 50 53 54 57 57 57 3 December 2002 SPRS208 vii Contents Section 3.11 General-Purpose I/O (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.11.1 General-Purpose I/O Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.11.2 Parallel Port General-Purpose I/O (PGPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Bus Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.12.1 External Bus Control Register (XBCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Ports and System Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13.1 XPORT Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13.2 DPORT Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13.3 IPORT Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13.4 System Configuration Register (CONFIG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13.5 Time-Out Control Register (TOCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CPU Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peripheral Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.16.1 IFR and IER Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.16.2 Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 64 64 66 73 73 74 74 77 79 80 81 82 84 98 99 100 101 102 103 103 103 103 104 105 105 106 106 107 108 110 113 117 122 123 124 125 126 127 128 128 131 132 3.12 3.13 3.14 3.15 3.16 4 5 6 Documentation Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device and Development-Support Tool Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4 Electrical Characteristics Over Recommended Operating Case Temperature Range (Unless Otherwise Noted) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 Package Thermal Resistance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6 Timing Parameter Symbology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.7 Clock Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.7.1 Clock Generation in Bypass Mode (APLL Disabled) . . . . . . . . . . . . . . . . . . . . . . . . . . 6.7.2 Clock Generation in PLL Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.7.3 EMIF Clock Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.8 EMIF Asynchronous Memory Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.9 Programmable Synchronous Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.10 Synchronous DRAM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.11 HOLD/HOLDA Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.12 Reset Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.13 External Interrupt and Interrupt Acknowledge (IACK) Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.14 XF Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.15 General-Purpose Input/Output (GPIOx)Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.15.1 TIM0/TIM1/WDTOUT Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.16 Multichannel Buffered Serial Port (McBSP) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.16.1 McBSP Transmit and Receive Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.16.2 McBSP General-Purpose I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.16.3 McBSP as SPI Master or Slave Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viii SPRS208 December 2002 Contents Section 6.17 6.18 6.19 7 HPI Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 137 143 144 145 145 146 Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1 Ball Grid Array Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 Low-Profile Quad Flatpack Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . December 2002 SPRS208 ix Figures List of Figures Figure 2-1 2-2 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 3-11 3-12 3-13 3-14 3-15 3-16 3-17 3-18 3-19 3-20 3-21 3-22 3-23 3-24 3-25 3-26 3-27 3-28 3-29 3-30 3-31 3-32 3-33 3-34 3-35 3-36 3-37 176-Terminal GGW Ball Grid Array (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176-Pin PGF Low-Profile Quad Flatpack (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram of the TMS320VC5502 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TMS320VC5502 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Bus Selection Register Layout (0x6C00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Signal Selection Register Layout (0x8000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watchdog Timer Hook-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DMA Channel 0 Control Register Layout (0x0C01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL and Clock Generator Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal System Oscillator External Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Generator (PLL) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Control/Status Register Layout (0x1C80) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Multiplier Control Register Layout (0x1C88) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Divider 0 Register Layout (0x1C8A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Divider 1 Register Layout (0x1C8C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Divider 2 Register Layout (0x1C8E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Divider 3 Register Layout (0x1C90) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator Divider1 Register Layout (0x1C92) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator Wakeup Control Register Layout (0x1C98) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLKOUT3 Select Register Layout (0x1C82) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLKOUT Selection Register Layout (0x8400) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Mode Control Register Layout (0x8C00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDLE Configuration Register Layout (0x0001) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDLE Status Register Layout (0x0002) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peripheral IDLE Control Register Layout (0x9400) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peripheral IDLE Status Register Layout (0x9401) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master IDLE Control Register Layout (0x9402) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master IDLE Status Register Layout (0x9403) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Direction Register Layout (0x3400) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Data Register Layout (0x3401) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel GPIO Enable Register 0 Layout (0x4400) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel GPIO Direction Register 0 Layout (0x4401) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel GPIO Data Register 0 Layout (0x4402) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel GPIO Enable Register 1 Layout (0x4403) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel GPIO Direction Register 1 Layout (0x4404) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel GPIO Data Register 1 Layout (0x4405) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel GPIO Enable Register 2 Layout (0x4406) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 3 5 17 20 25 27 28 30 31 33 35 36 38 40 42 43 44 44 45 46 47 48 48 49 57 59 60 62 63 64 65 65 67 67 68 69 69 70 71 x SPRS208 December 2002 Figures Figure 3-38 3-39 3-40 3-41 3-42 3-43 3-44 3-45 3-46 3-47 3-48 3-49 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 6-10 6-11 6-12 6-13 6-14 6-15 6-16 6-17 6-18 6-19 6-20 6-21 6-22 6-23 6-24 6-25 6-26 6-27 6-28 6-29 Parallel GPIO Direction Register 2 Layout (0x4407) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel GPIO Data Register 2 Layout (0x4408) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Bus Control Register Layout (0x6C01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XPORT Configuration Register Layout (0x0100) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XPORT Bus Error Register Layout (0x0102) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DPORT Configuration Register Layout (0x0200) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DPORT Bus Error Register Layout (0x0202) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IPORT Bus Error Register Layout (0x0302) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Configuration Register Layout (0x07FD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Time-Out Control Register Layout (0x9000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IFR0, IER0, DBIFR0, and DBIER0 Registers Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IFR1, IER1, DBIFR1, and DBIER1 Registers Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3-V Test Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bypass Mode Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Multiply-by-N Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ECLKIN Timing for EMIF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ECLKOUT1 Timing for EMIF Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ECLKOUT2 Timing for the EMIF Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous Memory Read Timing for EMIF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous Memory Write Timing for EMIF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmable Synchronous Interface Read Timing for EMIF (With Read Latency = 2) . . . . . . . . Programmable Synchronous Interface Write Timing for EMIF (With Write Latency = 0) . . . . . . . . Programmable Synchronous Interface Write Timing for EMIF (With Write Latency = 1) . . . . . . . . SDRAM Read Command (CAS Latency 3) for EMIF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SDRAM Write Command for EMIF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SDRAM ACTV Command for EMIF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SDRAM DCAB Command for EMIF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SDRAM DEAC Command for EMIF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SDRAM REFR Command for EMIF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SDRAM MRS Command for EMIF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SDRAM Self-Refresh Timing for EMIF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HOLD/HOLDA Timing for EMIF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Interrupt Acknowledge Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XF Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General-Purpose Input/Output (GPIOx) Signal Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TIM0/TIM1/WDTOUT Timings When Configured as Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TIM0/TIM1/WDTOUT Timings When Configured as Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . McBSP Receive Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . McBSP Transmit Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 71 72 73 75 76 77 78 79 80 81 99 99 105 106 107 108 108 109 111 112 114 115 116 117 118 118 119 119 120 120 121 122 123 124 124 125 126 127 127 130 130 December 2002 SPRS208 xi Figures Figure 6-30 6-31 6-32 6-33 6-34 6-35 6-36 6-37 6-38 6-39 6-40 6-41 6-42 7-1 7-2 McBSP General-Purpose I/O Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . . . McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . . . McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . . . McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . . . Non-Multiplexed Read/Write Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multiplexed Read Timings Using HAS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multiplexed Read Timings With HAS Held High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multiplexed Write Timings Using HAS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multiplexed Write Timings With HAS Held High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HINT Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TMS320VC5502 176-Ball MicroStar BGA Plastic Ball Grid Array Package . . . . . . . . . . . . . . . . . . . TMS320VC5502 176-Pin Low-Profile Quad Flatpack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 131 133 134 135 136 138 139 140 141 142 142 143 144 145 146 xii SPRS208 December 2002 Tables List of Tables Table 2-1 2-2 2-3 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 3-11 3-12 3-13 3-14 3-15 3-16 3-17 3-18 3-19 3-20 3-21 3-22 3-23 3-24 3-25 3-26 3-27 3-28 3-29 3-30 3-31 3-32 3-33 3-34 3-35 3-36 3-37 3-38 3-39 3-40 3-41 3-42 176-Terminal GGW Ball Grid Array Ball Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176-Pin PGF Low-Profile Quad Flatpack Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-Chip ROM Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DARAM Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Boot Configuration Selection Via the BOOTM[2:0] Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TMS320VC5502 Routing of Parallel Port Mux Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TMS320VC5502 Routing of Host Port Mux Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TMS320VC5502 Routing of Serial Port Mux Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Bus Selection Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Signal Selection Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronization Control Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Control/Status Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Multiplier Control Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Divider 0 Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Divider 1 Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Divider 2 Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Divider3 Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator Divider1 Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator Wakeup Control Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLKOUT3 Select Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLKOUT Selection Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Mode Control Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Number of Reference Clock Cycles Needed Until Program Flow Begins . . . . . . . . . . . . . . . . . . . . . Peripheral Behavior at Entering IDLE State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wake-Up Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Domain Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDLE Configuration Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDLE Status Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peripheral IDLE Control Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peripheral IDLE Status Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master IDLE Control Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master IDLE Status Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Direction Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Data Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TMS320VC5502 PGPIO Cross-Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel GPIO Enable Register 0 Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel GPIO Direction Register 0 Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel GPIO Data Register 0 Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel GPIO Enable Register 1 Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel GPIO Direction Register 1 Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel GPIO Data Register 1 Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel GPIO Enable Register 2 Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel GPIO Direction Register 2 Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 4 6 7 18 19 21 23 24 24 26 27 34 40 41 42 43 44 45 45 46 47 48 49 49 50 53 56 57 58 59 60 62 63 64 65 65 66 67 67 68 69 69 70 71 72 December 2002 SPRS208 xiii Tables Table 3-43 3-44 3-45 3-46 3-47 3-48 3-49 3-50 3-51 3-52 3-53 3-54 3-55 3-56 3-57 3-58 3-59 3-60 3-61 3-62 3-63 3-64 3-65 3-66 3-67 3-68 3-69 3-70 3-71 3-72 3-73 3-74 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 6-10 6-11 6-12 6-13 6-14 Parallel GPIO Data Register 2 Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Bus Control Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Addresses Under Scope of XPORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XPORT Configuration Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XPORT Bus Error Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DPORT Configuration Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DPORT Bus Error Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IPORT Bus Error Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Configuration Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Time-Out Control Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CPU Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peripheral Bus Controller Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Memory Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DMA Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Instruction Cache Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Trace FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Signal Selection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multichannel Serial Port #0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multichannel Serial Port #1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multichannel Serial Port #2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device Revision ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I 2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Bus Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLKOUT Selector Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDLE Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Resistance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLKIN in Bypass Mode Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLKOUT in Bypass Mode Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLKIN in Lock Mode Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLKOUT in Lock Mode Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMIF Timing Requirements for ECLKIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMIF Switching Characteristics for ECLKOUT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMIF Switching Characteristics for ECLKOUT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMIF Asynchronous Memory Cycle Timing Requirements for ECLKIN . . . . . . . . . . . . . . . . . . . . . . EMIF Asynchronous Memory Cycle Switching Characteristics for ECLKOUT1 . . . . . . . . . . . . . . . EMIF Programmable Synchronous Interface Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . EMIF Programmable Synchronous Interface Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . EMIF Synchronous DRAM Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMIF Synchronous DRAM Cycle Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 72 73 74 75 76 77 78 79 80 81 82 84 85 86 89 89 89 89 91 92 93 94 94 94 95 96 96 96 96 97 97 98 105 106 106 107 107 108 108 109 110 110 113 113 117 117 xiv SPRS208 December 2002 Tables Table 6-15 6-16 6-17 6-18 6-19 6-20 6-21 6-22 6-23 6-24 6-25 6-26 6-27 6-28 6-29 6-30 6-31 6-32 6-33 6-34 6-35 6-36 6-37 6-38 6-39 6-40 6-41 6-42 EMIF HOLD/HOLDA Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMIF HOLD/HOLDA Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Interrupt and Interrupt Acknowledge Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . External Interrupt and Interrupt Acknowledge Switching Characteristics . . . . . . . . . . . . . . . . . . . . . XF Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Pins Configured as Inputs Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Pins Configured as Inputs Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TIM0/TIM1/WDTOUT Pins Configured as Inputs Timing Requirements . . . . . . . . . . . . . . . . . . . . . . TIM0/TIM1/WDTOUT Pins Configured as Outputs Switching Characteristics . . . . . . . . . . . . . . . . . McBSP Transmit and Receive Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . McBSP Transmit and Receive Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . McBSP General-Purpose I/O Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . McBSP General-Purpose I/O Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) . . . . . . . . . . McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0) . . . . . . McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0) . . . . . . . . . . McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0) . . . . . . . McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1) . . . . . . . . . . McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1) . . . . . . McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1) . . . . . . . . . . McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1) . . . . . . . HPI Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HPI Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Signals (SDA and SCL) Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 122 122 123 123 124 124 125 126 126 127 127 128 129 131 131 132 132 134 134 135 135 136 136 137 137 143 144 144 December 2002 SPRS208 xv Features 1 TMS320VC5502 Features D High-Performance, Low-Power, Fixed-Point TMS320C55x Digital Signal Processor (DSP) - 3.33-ns Instruction Cycle Time for 300-MHz Clock Rate - 16K-Byte Instruction Cache (I-Cache) - One/Two Instructions Executed per Cycle - Dual Multipliers [Up to 600 Million Multiply-Accumulates Per Second (MMACS)] - Two Arithmetic/Logic Units (ALUs) - One Program Bus, Three Internal Data/Operand Read Buses, and Two Internal Data/Operand Write Buses 32K x 16-Bit On-Chip RAM That is Composed of Eight Blocks of 4K x 16-Bit Dual-Access RAM (DARAM) (64K Bytes) 16K x 16-Bit One-Wait-State On-Chip ROM (32K Bytes) 8M x 16-Bit Maximum Addressable External Memory Space 32-Bit External Parallel Bus Memory Supporting External Memory Interface (EMIF) With General-Purpose Input/Output (GPIO) Capabilities and Glueless Interface to: - Asynchronous Static RAM (SRAM) - Asynchronous EPROM - Synchronous DRAM (SDRAM) - Synchronous Burst RAM (SBRAM) Emulation/Debug Trace Capability Saves Last 16 Program Counter (PC) Discontinuities and Last 32 PC Values D Programmable Low-Power Control of Six D Device Functional Domains On-Chip Peripherals - Six-Channel Direct Memory Access (DMA) Controller - Three Multichannel Buffered Serial Ports (McBSPs) - Programmable Analog Phase-Locked Loop (APLL) Clock Generator - General-Purpose I/O (GPIO) Pins and a Dedicated Output Pin (XF) - 8-Bit/16-Bit Parallel Host-Port Interface (HPI) - Four Timers - Two 64-Bit General-Purpose Timers - 64-Bit Programmable Watchdog Timer - 64-Bit DSP/BIOS Counter - Inter-Integrated Circuit (I2C) Interface - Universal Asynchronous Receiver/ Transmitter (UART) On-Chip Scan-Based Emulation Logic IEEE Std 1149.1 (JTAG) Boundary Scan Logic Packages: - 176-Terminal LQFP (Low-Profile Quad Flatpack) (PGF Suffix) - 176-Terminal MicroStar BGA (Ball Grid Array) (GGW Suffix) 3.3-V I/O Supply Voltage 1.26-V Core Supply Voltage D D D D D D D D D D TMS320C55x, DSP/BIOS, and MicroStar BGA are trademarks of Texas Instruments. Other trademarks are the property of their respective owners. IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture. 1 December 2002 SPRS208 PRODUCT PREVIEW Introduction 2 Introduction This section describes the main features of the TMS320VC5502 and gives a brief description of the device. NOTE: This document is designed to be used in conjunction with the TMS320C55x DSP Functional Overview (literature number SPRU312) and the TMS320C55x DSP CPU Reference Guide (literature number SPRU371). 2.1 Description The TMS320VC5502 (5502) fixed-point digital signal processor (DSP) is based on the TMS320C55x DSP generation CPU processor core. The C55x DSP architecture achieves high performance and low power through increased parallelism and total focus on reduction in power dissipation. The CPU supports an internal bus structure that is composed of one program bus, three data read buses, two data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to three data reads and two data writes in a single cycle. In parallel, the DMA controller can perform data transfers independent of the CPU activity. The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit x 17-bit multiplication in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by an additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel activity and power consumption. These resources are managed in the Address Unit (AU) and Data Unit (DU) of the C55x CPU. The C55x DSP generation supports a variable byte width instruction set for improved code density. The Instruction Unit (IU) performs 32-bit program fetches from internal or external memory and queues instructions for the Program Unit (PU). The Program Unit decodes the instructions, directs tasks to AU and DU resources, and manages the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution of conditional instructions. The 5502 peripheral set includes an external memory interface (EMIF) that provides glueless access to asynchronous memories like EPROM and SRAM, as well as to high-speed, high-density memories such as synchronous DRAM and synchronous burst RAM. Additional peripherals include UART, watchdog timer, and an I-Cache. Three full-duplex multichannel buffered serial ports (McBSPs) provide glueless interface to a variety of industry-standard serial devices, and multichannel communication with up to 128 separately enabled channels. The host-port interface (HPI) is a 8-/16-bit parallel interface used to provide host processor access to 32K words of internal memory on the 5502. The HPI can be configured in either multiplexed or non-multiplexed mode to provide glueless interface to a wide variety of host processors. The DMA controller provides data movement for six independent channel contexts without CPU intervention. Two general-purpose timers, eight dedicated general-purpose I/O (GPIO) pins, and analog phase-locked loop (APLL) clock generation are also included. The 5502 is supported by the industry's award-winning eXpressDSP, Code Composer Studio Integrated Development Environment (IDE), DSP/BIOS, Texas Instruments' algorithm standard, and the industry's largest third-party network. The Code Composer Studio IDE features code generation tools that include a C Compiler, Visual Linker, simulator, RTDX, XDS510 emulation device drivers, and evaluation modules. The 5502 is also supported by the C55x DSP Library, which features more than 50 foundational software kernels (FIR filters, IIR filters, FFTs, and various math functions) as well as chip and board support libraries. PRODUCT PREVIEW 2 C55x, eXpressDSP, Code Composer Studio, RTDX, and XDS510 are trademarks of Texas Instruments. SPRS208 December 2002 Introduction 2.2 Pin Assignments 2.2.1 Ball Grid Array (GGW) Figure 2-1 illustrates the ball locations for the 176-pin ball grid array (BGA) package and Table 2-1 lists the signal names and terminal numbers. U T R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Figure 2-1. 176-Terminal GGW Ball Grid Array (Bottom View) December 2002 SPRS208 3 PRODUCT PREVIEW Introduction Table 2-1. 176-Terminal GGW Ball Grid Array Ball Assignments BALL NO. B1 C2 C1 D3 D2 D1 E3 E2 E1 F3 F2 F1 G4 G3 SIGNAL NAME GPIO6 GPIO4 GPIO2 GPIO1 GPIO0 TIM1 TIM0 INT0 CVDD INT1 INT2 DVDD INT3 NMI/WDTOUT IACK VSS CLKR0 DR0 FSR0 CLKX0 CVDD DX0 FSX0 CLKR1 DR1 FSR1 DX1 CLKX1 VSS FSX1 DR2 DX2 CVDD SP3 SP2 DVDD SP1 SP0 VSS SCL SDA HC1 HC0 HCS BALL NO. U2 T3 U3 R4 T4 U4 R5 T5 U5 R6 T6 U6 P7 R7 T7 U7 U8 P8 R8 T8 U9 P9 R9 T9 U10 T10 P10 R10 U11 T11 R11 P11 U12 T12 R12 U13 T13 R13 U14 T14 R14 U15 T15 U16 SIGNAL NAME HCNTL1 HCNTL0 VSS HR/W HDS2 CVDD HDS1 HRDY DVDD CLKOUT XF VSS C15 C14 HINT PVDD PSENSE X1 X2/CLKIN EMIFCLKS VSS C13 C12 C11 C10 C9 C8 C7 VSS ECLKIN ECLKOUT2 ECLKOUT1 CVDD C6 C5 DVDD C4 C3 VSS C2 C1 C0 A21 A20 BALL NO. T17 R16 R17 P15 P16 P17 N15 N16 N17 M15 M16 M17 L14 L15 L16 L17 K17 K14 K15 K16 J17 J14 J15 J16 H17 H16 H14 H15 G17 G16 G15 G14 F17 F16 F15 E17 E16 E15 D17 D16 D15 C17 C16 B17 SIGNAL NAME A19 A18 VSS A17 A16 DVDD A15 A14 VSS A13 A12 CVDD A11 A10 A9 A8 DVDD A7 A6 A5 VSS A4 A3 A2 CVDD D31 D30 D29 VSS D28 D27 D26 CVDD D25 D24 DVDD D23 D22 D21 D20 D19 VSS D18 D17 BALL NO. A16 B15 A15 C14 B14 A14 C13 B13 A13 C12 B12 A12 D11 C11 B11 A11 A10 D10 C10 B10 A9 D9 C9 B9 A8 B8 D8 C8 A7 B7 C7 D7 A6 B6 C6 A5 B5 C5 A4 B4 C4 A3 B3 A2 SIGNAL NAME D16 D15 D14 D13 D12 D11 D10 D9 DVDD D8 D7 VSS D6 D5 D4 CVDD D3 D2 D1 D0 VSS EMU1/OFF EMU0 TDO VSS TDI TRST TCK TMS RESET HPIENA HD7 CVDD HD6 HD5 DVDD HD4 HD3 CVDD HD2 HD1 VSS HD0 GPIO7 PRODUCT PREVIEW 4 G2 G1 H1 H4 H3 H2 J1 J4 J3 J2 K1 K2 K4 K3 L1 L2 L3 L4 M1 M2 M3 N1 N2 N3 P1 P2 P3 R1 R2 T1 NOTE: CVDD is core VDD , DVDD is I/O VDD , and PVDD is PLL VDD . PSENSE must be left unconnected. SPRS208 December 2002 Introduction 2.2.2 Low-Profile Quad Flatpack (PGF) Figure 2-2 illustrates the pin locations for the 176-pin low-profile quad flatpack (LQFP) and Table 2-2 provides a numerical list (by pin number) of the pin assignments. 132 133 89 88 176 1 44 45 Figure 2-2. 176-Pin PGF Low-Profile Quad Flatpack (Top View) December 2002 SPRS208 5 PRODUCT PREVIEW Introduction Table 2-2. 176-Pin PGF Low-Profile Quad Flatpack Pin Assignments PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SIGNAL NAME GPIO6 GPIO4 GPIO2 GPIO1 GPIO0 TIM1 TIM0 INT0 CVDD INT1 INT2 DVDD INT3 NMI/WDTOUT IACK VSS CLKR0 DR0 FSR0 CLKX0 CVDD DX0 FSX0 CLKR1 DR1 FSR1 DX1 CLKX1 VSS FSX1 DR2 DX2 CVDD SP3 SP2 DVDD SP1 SP0 VSS SCL SDA HC1 HC0 HCS PIN NO. 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 SIGNAL NAME HCNTL1 HCNTL0 VSS HR/W HDS2 CVDD HDS1 HRDY DVDD CLKOUT XF VSS C15 C14 HINT PVDD PSENSE X1 X2/CLKIN EMIFCLKS VSS C13 C12 C11 C10 C9 C8 C7 VSS ECLKIN ECLKOUT2 ECLKOUT1 CVDD C6 C5 DVDD C4 C3 VSS C2 C1 C0 A21 A20 PIN NO. 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 SIGNAL NAME A19 A18 VSS A17 A16 DVDD A15 A14 VSS A13 A12 CVDD A11 A10 A9 A8 DVDD A7 A6 A5 VSS A4 A3 A2 CVDD D31 D30 D29 VSS D28 D27 D26 CVDD D25 D24 DVDD D23 D22 D21 D20 D19 VSS D18 D17 PIN NO. 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 SIGNAL NAME D16 D15 D14 D13 D12 D11 D10 D9 DVDD D8 D7 VSS D6 D5 D4 CVDD D3 D2 D1 D0 VSS EMU1/OFF EMU0 TDO VSS TDI TRST TCK TMS RESET HPIENA HD7 CVDD HD6 HD5 DVDD HD4 HD3 CVDD HD2 HD1 VSS HD0 GPIO7 PRODUCT PREVIEW 6 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 NOTE: CVDD is core VDD , DVDD is I/O VDD , and PVDD is PLL VDD . PSENSE must be left unconnected. SPRS208 December 2002 Introduction 2.3 Signal Descriptions Table 2-3 lists each signal, function, and operating mode(s) grouped by function. See Section 2.2, Pin Assignments, for exact pin locations based on package type. Table 2-3. Signal Descriptions Pin Name Multiplexed Signal Name Pin Type Other Parallel Bus Function A[21:18] I/O/Z C, D, F, G, H, M PGPIO[3:0] I/O/Z These pins serve one of two functions: EMIF address bus EMIF.A[21:18] or PGPIO[3:0]. At reset, GPIO6 is sampled. If GPIO6 is low, the HPI non-multiplexed mode is enabled, the address bus A[21:18] is set to GPIO with all pins set as inputs. If GPIO6 is high, the EMIF mode is enabled and all address pins are set as outputs. The address bus includes a bus holder feature that eliminates passive components and the power dissipation associated with them. The bus holder keeps the address bus at the previous logic level when the bus went into a high-impedance state. These pins also include Schmitt-trigger inputs. Parallel general-purpose I/O. PGPIO[3:0] is selected when GPIO6 is low at reset, enabling the HPI non-multiplexed mode with the Parallel GPIO register driving the Parallel Port Mux address bus EMIF.A[21:18]. EMIF.A[21:18] O/Z A[17:2] I/O/Z C, D, F, M HPI.A[15:0] I These pins serve one of two functions: EMIF address bus EMIF.A[17:2] or HPI address bus HPI.A[15:0]. At reset, GPIO6 is sampled. If GPIO6 is low, the HPI non-multiplexed mode is enabled, A[17:2] is set to HPI.A[15:0]. If GPIO6 is high, the EMIF mode is enabled and all address pins are set as outputs. The address bus includes a bus holder feature that eliminates passive components and the power dissipation associated with them. The bus holder keeps the address bus at the previous logic level when the bus went into a high-impedance state. These pins also include Schmitt trigger inputs. HPI address bus. HPI.A[15:0] is selected when GPIO6 is low at reset. This setting enables the HPI non-multiplexed mode and HPI address bus drives the Parallel Port Mux address bus. HPI.A[15:0] provides internal memory access to the HPI in non-multiplexed mode. In non-multiplexed mode, these signals are driven by an external host as address lines. EMIF address bus. EMIF.A[17:2] is selected when GPIO6 is high at reset, enabling EMIF mode and the EMIF address bus drives the Parallel Port Mux address bus. EMIF.A[17:2] O/Z I = Input, O = Output, S = Supply, Z = High impedance Other Pin Characteristics: A - Internal pullup (always enabled) E - Pin is high impedance in HOLD mode (due to HOLD pin). B - Internal pulldown (always enabled) F - Pin is high impedance in OFF mode (due to EMU1/OFF pin). C - Hysteresis input G - Pin can be configured as a general-purpose input. D - Pin has bus holder H - PIn can be configured as a general-purpose output. J - Internal pullup enabled through the External Bus Control Register (XBCR) K - Internal pulldown enabled through the External Bus Control Register (XBCR) L - Fail-safe pin M - Pin is in high-impedance during reset (RESET pin is low) December 2002 SPRS208 7 PRODUCT PREVIEW EMIF address bus. EMIF.A[21:18] is selected when GPIO6 is high at reset, enabling EMIF mode and the EMIF address bus drives the Parallel Port Mux address bus. Introduction Table 2-3. Signal Descriptions (Continued) Pin Name Multiplexed Signal Name Pin Type Other Parallel Bus (Continued) The 32 data pins, D[31:0], are multiplexed to transfer data between the core CPU and external data/program memory or I/O devices. At reset, GPIO6 is sampled. If GPIO6 is low, then the HPI non-multiplexed mode is enabled and D[31:16] is set as PGPIO[19:4] inputs. If GPIO6 is high, the EMIF mode is enabled and all data pins are set as data inputs/outputs. The data bus includes bus holders to reduce the static power dissipation caused by floating, unused pins. The bus holders also eliminate the need for external bias resistors on unused pins. When the data bus is not being driven by the CPU, the bus holders keep the pins at the logic level that were most recently driven. The data bus holders are disabled at reset, and can be enabled/disabled under software control. At reset, the bus is in a high-impedance state. Parallel general-purpose I/O. PGPIO[19:4] is selected when GPIO6 is low at reset, enabling the HPI non-multiplexed mode with the Parallel GPIO register driving the Parallel Port Mux data bus D[31:16]. EMIF data bus. EMIF.D[31:16] is selected when GPIO6 is high. This setting enables the EMIF mode and the EMIF data bus drives the Parallel Port Mux data bus. The 32 data pins, D[31:0], are multiplexed to transfer data between the core CPU and external data/program memory or I/O devices. At reset, GPIO6 is sampled. If GPIO6 is low, then the HPI non-multiplexed mode is enabled and D[15:0] is set to HPI.D[15:0]. If GPIO6 is high, the EMIF mode is enabled and all data pins are set as data inputs. The data bus includes bus holders to reduce the static power dissipation caused by floating, unused pins. The bus holders also eliminate the need for external bias resistors on unused pins. When the data bus is not being driven by the CPU, the bus holders keep the pins at the logic level that were most recently driven. The data bus holders are disabled at reset, and can be enabled/disabled under software control. At reset, the bus is in a high-impedance state. HPI data bus. HPI.D[15:0] is selected when GPIO6 is low at reset. This setting enables the HPI non-multiplexed mode and the HPI bidirectional data bus drives the Parallel Port Mux data bus. EMIF data bus. EMIF.D[15:0] is selected when GPIO6 is high. This setting enables the EMIF mode and the EMIF data bus drives the Parallel Port Mux data bus. EMIF control function [asynchronous memory read-enable (ARE) multiplexed with synchronous memory address strobe (SADS), SDRAM column-address strobe (SDCAS), and synchronous read enable (SRE) (selected when by RENEN in CE Secondary Control Register 1)] or PGPIO20. At reset, GPIO6 is sampled. If GPIO6 is low, the HPI non-multiplexed mode is enabled and C0 is set to PGPIO20 input. If GPIO6 is high, the full EMIF mode is enabled and C0 is set to EMIF control I/O. EMIF control pin. Asynchronous memory read-enable (EMIF.ARE) / synchronous memory address strobe (EMIF.SADS) / SDRAM column-address strobe (EMIF.SDCAS) / synchronous read enable (EMIF.SRE) selected when GPIO6 is high at reset. Function D[31:16] I/O/Z C, D, F, G, H, M PGPIO[19:4] I/O/Z EMIF.D[31:16] I/O/Z PRODUCT PREVIEW D[15:0] I/O/Z C, D, F, M HPI.D[15:0] I/O/Z EMIF.D[15:0] I/O/Z C0 I/O/Z C, D, F, G, H, GHM EMIF.ARE/SADS/ SDCAS/SRE O/Z PGPIO20 I/O/Z Parallel general-purpose I/O 20. PGPIO20 is selected when GPIO6 is low at reset. I = Input, O = Output, S = Supply, Z = High impedance Other Pin Characteristics: A - Internal pullup (always enabled) E - Pin is high impedance in HOLD mode (due to HOLD pin). B - Internal pulldown (always enabled) F - Pin is high impedance in OFF mode (due to EMU1/OFF pin). C - Hysteresis input G - Pin can be configured as a general-purpose input. D - Pin has bus holder H - PIn can be configured as a general-purpose output. J - Internal pullup enabled through the External Bus Control Register (XBCR) K - Internal pulldown enabled through the External Bus Control Register (XBCR) L - Fail-safe pin M - Pin is in high-impedance during reset (RESET pin is low) 8 SPRS208 December 2002 Introduction Table 2-3. Signal Descriptions (Continued) Pin Name Multiplexed Signal Name Pin Type Other Parallel Bus (Continued) EMIF control function [asynchronous memory output-enable (AOE) multiplexed with synchronous memory output-enable (SOE) and SDRAM row address strobe (SDRAS)] or PGPIO21. At reset, GPIO6 is sampled. If GPIO6 is low, the HPI non-multiplexed mode is enabled and C1 is set to PGPIO21 input. If GPIO6 is high, the full EMIF mode is enabled and C1 is set to EMIF control output in high-impedance mode. EMIF control pin. Asynchronous memory output-enable (EMIF.AOE)/ synchronous memory output-enable (EMIF.SOE)/SDRAM row address strobe (EMIF.SDRAS) selected when GPIO6 is high at reset. Parallel general-purpose I/O21. PGPIO21 is selected when GPIO6 is low at reset. EMIF control function [Asynchronous memory write-enable (AWE) multiplexed with synchronous memory write-enable (SWE) and SDRAM write-enable (SDWE)] or PGPIO22. At reset, GPIO6 is sampled. If GPIO6 is low, the HPI non-multiplexed mode is enabled and C2 is set to PGPIO22 input. If GPIO6 is high, the full EMIF mode is enabled and C2 is set to EMIF control output in high-impedance mode. EMIF control pin. Asynchronous memory write-enable (EMIF.AWE)/ synchronous memory write-enable (EMIF.SWE)/SDRAM write-enable (EMIF.SDWE) selected when GPIO6 is high at reset. Parallel general-purpose I/O22. PGPIO22 is selected when GPIO6 is low at reset. EMIF data ready input or PGPIO23. At reset, GPIO6 is sampled. If GPIO6 is low, the HPI non-multiplexed mode is enabled and C3 is set to PGPIO23 input. If GPIO6 is high, the full EMIF mode is enabled and C3 is set to EMIF.ARDY input. EMIF data ready. Input used to insert wait states for slow memories. EMIF.ARDY is selected when GPIO6 is high at reset. Parallel general-purpose I/O23. PGPIO23 is selected when GPIO6 is low at reset. EMIF chip-select for memory space CE0 or PGPIO24. At reset, GPIO6 is sampled. If GPIO6 is low, the HPI non-multiplexed mode is enabled and C4 is set to PGPIO24 input. If GPIO6 is high, the full EMIF mode is enabled and C4 is set to EMIF.CE0 input. EMIF chip-select for memory space CE0. EMIF.CE0 is selected when GPIO6 is high at reset. Parallel general-purpose I/O24. PGPIO24 is selected when GPIO6 is low at reset. EMIF chip-select for memory space CE1 or PGPIO25. At reset, GPIO6 is sampled. If GPIO6 is low, the HPI non-multiplexed mode is enabled and C5 is set to PGPIO25 input. If GPIO6 is high, the full EMIF mode is enabled and C5 is set to EMIF.CE1 input. EMIF chip-select for memory space CE1. EMIF.CE1 is selected when GPIO6 is high at reset. Function C1 I/O/Z C, D, F, G, H, M EMIF.AOE/SOE/ SDRAS PGPIO21 O/Z I/O/Z C2 I/O/Z C, D, F, G, H, M EMIF.AWE/ SWE/SDWE PGPIO22 O/Z I/O/Z I/O/Z F, G, H, J, M C3 EMIF.ARDY PGPIO23 C4 I I/O/Z I/O/Z EMIF.CE0 PGPIO24 C5 O/Z I/O/Z I/O/Z C, D, F, G, H, M EMIF.CE1 O/Z C, D, F, G, H, M PGPIO25 I/O/Z Parallel general-purpose I/O 25. PGPIO25 is selected when GPIO6 is low at reset. I = Input, O = Output, S = Supply, Z = High impedance Other Pin Characteristics: A - Internal pullup (always enabled) E - Pin is high impedance in HOLD mode (due to HOLD pin). B - Internal pulldown (always enabled) F - Pin is high impedance in OFF mode (due to EMU1/OFF pin). C - Hysteresis input G - Pin can be configured as a general-purpose input. D - Pin has bus holder H - PIn can be configured as a general-purpose output. J - Internal pullup enabled through the External Bus Control Register (XBCR) K - Internal pulldown enabled through the External Bus Control Register (XBCR) L - Fail-safe pin M - Pin is in high-impedance during reset (RESET pin is low) December 2002 SPRS208 9 PRODUCT PREVIEW Introduction Table 2-3. Signal Descriptions (Continued) Pin Name Multiplexed Signal Name Pin Type Other Parallel Bus (Continued) C6 I/O/Z C, D, F, G, H, M EMIF chip-select for memory space CE2 or PGPIO26. At reset, GPIO6 is sampled. If GPIO6 is low, the HPI non-multiplexed mode is enabled and C6 is set to PGPIO26 input. If GPIO6 is high, the full EMIF mode is enabled and C6 is set to EMIF.CE2 input. EMIF chip-select for memory space CE2. EMIF.CE2 is selected when GPIO6 is high at reset. Parallel general-purpose I/O 26. PGPIO26 is selected when GPIO6 is low at reset. EMIF chip-select for memory space CE3 or PGPIO27. At reset, GPIO6 is sampled. If GPIO6 is low, the HPI non-multiplexed mode is enabled and C7 is set to PGPIO27 input. If GPIO6 is high, the full EMIF mode is enabled and C7 is set to EMIF.CE3 input. EMIF chip-select for memory space CE3. EMIF.CE3 is selected when If GPIO6 is high at reset. Parallel general-purpose I/O 27. PGPIO27 is selected when GPIO6 is low at reset. EMIF byte-enable 0 or PGPIO28. At reset, GPIO6 is sampled. If GPIO6 is low, the HPI non-multiplexed mode is enabled and C8 is set to PGPIO28 input. If GPIO6 is high, the full EMIF mode is enabled and C8 is set to EMIF.BE0 output. EMIF byte-enable 0 control. EMIF.BE0 is selected when GPIO6 is high at reset. Parallel general-purpose I/O 28. PGPIO28 is selected when GPIO6 is low at reset. EMIF byte-enable 1 or PGPIO29. At reset, GPIO6 is sampled. If GPIO6 is low, the HPI non-multiplexed mode is enabled and C9 is set to PGPIO29 input. If GPIO6 is high, the full EMIF mode is enabled and C9 is set to EMIF.BE1 output. EMIF byte-enable 1 control. EMIF.BE1 is selected when GPIO6 is high at reset. Parallel general-purpose I/O 29. PGPIO29 is selected when GPIO6 is low at reset. EMIF byte-enable 2 or PGPIO30. At reset, GPIO6 is sampled. If GPIO6 is low, the HPI non-multiplexed mode is enabled and C10 is set to PGPIO30 input. If GPIO6 is high, the full EMIF mode is enabled and C10 is set to EMIF.BE2 output. EMIF byte-enable 2 control. EMIF.BE2 is selected when GPIO6 is high at reset. Parallel general-purpose I/O 30. PGPIO30 is selected when GPIO6 is low at reset. EMIF byte-enable 3 or PGPIO31. At reset, GPIO6 is sampled. If GPIO6 is low, the HPI non-multiplexed mode is enabled and C11 is set to PGPIO31 input. If GPIO6 is high, the full EMIF mode is enabled and C11 is set to EMIF.BE3 output. EMIF byte-enable 3 control. EMIF.BE3 is selected when GPIO6 is high at reset. Function EMIF.CE2 PGPIO26 C7 O/Z I/O/Z I/O/Z EMIF.CE3 PGPIO27 C8 O/Z I/O/Z I/O/Z C, D, F, G, H, M PRODUCT PREVIEW EMIF.BE0 PGPIO28 C9 EMIF.BE1 PGPIO29 C10 EMIF.BE2 PGPIO30 C11 EMIF.BE3 O/Z I/O/Z I/O/Z O/Z I/O/Z I/O/Z O/Z I/O/Z I/O/Z O/Z C, D, F, G, H, M C, D, F, G, H, M C, D, F, G, H, M C, D, F, G, H, M PGPIO31 I/O/Z Parallel general-purpose I/O 31. PGPIO31 is selected when GPIO6 is low at reset. I = Input, O = Output, S = Supply, Z = High impedance Other Pin Characteristics: A - Internal pullup (always enabled) E - Pin is high impedance in HOLD mode (due to HOLD pin). B - Internal pulldown (always enabled) F - Pin is high impedance in OFF mode (due to EMU1/OFF pin). C - Hysteresis input G - Pin can be configured as a general-purpose input. D - Pin has bus holder H - PIn can be configured as a general-purpose output. J - Internal pullup enabled through the External Bus Control Register (XBCR) K - Internal pulldown enabled through the External Bus Control Register (XBCR) L - Fail-safe pin M - Pin is in high-impedance during reset (RESET pin is low) 10 SPRS208 December 2002 Introduction Table 2-3. Signal Descriptions (Continued) Pin Name Multiplexed Signal Name Pin Type Other Parallel Bus (Continued) C12 EMIF.SDCKE PGPIO32 I/O/Z O/Z I/O/Z C, D, F, G, H, M EMIF SDRAM clock-enable or PGPIO32. At reset, GPIO6 is sampled. If GPIO6 is low, the HPI non-multiplexed mode is enabled and C12 is set to PGPIO32 input. If GPIO6 is high, the full EMIF mode is enabled and C12 is set to EMIF.SDCKE output. EMIF SDRAM clock-enable. EMIF.SDCKE is selected when GPIO6 is high at reset. Parallel general-purpose I/O32. PGPIO32 is selected when GPIO6 is low at reset. EMIF synchronous memory output-enable for CE3 or PGPIO33. At reset, GPIO6 is sampled. If GPIO6 is low, the HPI non-multiplexed mode is enabled and C13 is set to PGPIO33 input. If GPIO6 is high, the full EMIF mode is enabled and C13 is set to EMIF.SOE3 output. EMIF synchronous memory output-enable for CE3 (intended for glueless FIFO interface). EMIF.SOE3 is selected when GPIO6 is high at reset. Parallel general-purpose I/O 33. PGPIO33 is selected when GPIO6 is low at reset. EMIF memory interface Hold request from a host or PGPIO34. At reset, GPIO6 is sampled. If GPIO6 is low, the HPI non-multiplexed mode is enabled and C14 is set to PGPIO34 input. If GPIO6 is high, the full EMIF mode is enabled and C14 is set to EMIF.HOLD input. Memory interface Hold request. EMIF.HOLD is selected when GPIO6 is high at reset. Parallel general-purpose I/O 34. PGPIO34 is selected when GPIO6 is low at reset. EMIF memory interface Hold Acknowledge from the C55x to a Host or PGPIO35. At reset, GPIO6 is sampled. If GPIO6 is low, the HPI non-multiplexed mode is enabled and C15 is set to PGPIO35 input. If GPIO6 is high, the full EMIF mode is enabled and C15 is set to EMIF.HOLDA output. Memory interface Hold Acknowledge. EMIF.HOLDA is selected when GPIO6 is high at reset. Parallel general-purpose I/O 35. PGPIO35 is selected when GPIO6 is low at reset. C, L F, M F C, L External EMIF input clock. When EMIFCLKS = 1 during reset, this pin is configured as the input clock to the EMIF. EMIF output clock. Drives EMIF input clock by default. Can be held low or set to high-impedance through the EMIF Global Control Register. EMIF output clock. Set to high-impedance by default. Can be enabled to drive EMIF input clock divided by a factor of 1, 2, or 4 through the EMIF Global Control Register. EMIF input clock source select. If EMIFCLKS = 0 during reset, the internal clock is used by EMIF. If EMIFCLKS = 1 during reset, ECLKIN is used by EMIF. HPI Data Pins HD[7:0] HPI.HD[7:0] PGPIO[43:36] I/O/Z O/Z I/O/Z C, D, F, G, H, M HPI data pins HPI.HD[7:0] or PGPIO[43:36]. At reset, GPIO6 is sampled. If GPIO6 is low, the HPI non-multiplexed mode is enabled and HD[7:0] are set to PGPIO[43:36]. If GPIO6 is high, the full EMIF mode is enabled and HD[7:0] are set to HPI.HD[7:0]. Data pins for HPI. HPI.HD[7:0] are selected when GPIO6 is high at reset. Parallel general-purpose I/O [43:36]. PGPIO[43:36] are selected when GPIO6 is low at reset. Function C13 I/O/Z C, D, F, G, H, M EMIF.SOE3 PGPIO33 O/Z I/O/Z C14 EMIF.HOLD PGPIO34 I/O/Z F, G, H, J, JM O/Z I/O/Z C15 I/O/Z C, D, F, G, H, M EMIF.HOLDA PGPIO35 O/Z I/O/Z I O/Z O/Z I ECLKIN ECLKOUT1 ECLKOUT2 EMIFCLKS I = Input, O = Output, S = Supply, Z = High impedance Other Pin Characteristics: A - Internal pullup (always enabled) E - Pin is high impedance in HOLD mode (due to HOLD pin). B - Internal pulldown (always enabled) F - Pin is high impedance in OFF mode (due to EMU1/OFF pin). C - Hysteresis input G - Pin can be configured as a general-purpose input. D - Pin has bus holder H - PIn can be configured as a general-purpose output. J - Internal pullup enabled through the External Bus Control Register (XBCR) K - Internal pulldown enabled through the External Bus Control Register (XBCR) L - Fail-safe pin M - Pin is in high-impedance during reset (RESET pin is low) December 2002 SPRS208 11 PRODUCT PREVIEW Introduction Table 2-3. Signal Descriptions (Continued) Pin Name Multiplexed Signal Name Pin Type Other HPI Control Pins HC0 HPI.HAS PGPIO44 HC1 HPI.HBIL PGPIO45 HCNTL0 HCNTL1 HCS I/O/Z I I/O/Z I/O/Z I I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I I O/Z O/Z I F, J, M F, J, M C, F, J, M F, J, M C, J C, J F, J, M F, J, M C, K F, G, H, K, M C, F, G, H, J, M Host address strobe or PGPIO44. At reset, GPIO6 is sampled. If GPIO6 is low, the HPI non-multiplexed mode is enabled and HC0 is set to PGPIO44 input. If GPIO6 is high, the full EMIF mode is enabled and HC0 is set to HPI.HAS input. Host address strobe. HPI.HAS is selected when GPIO6 is high at reset. Parallel general-purpose I/O 44. PGPIO44 is selected when GPIO6 is low at reset. HPI host byte identification or PGPIO45. At reset, GPIO6 is sampled. If GPIO6 is low, the HPI non-multiplexed mode is enabled and HC1 is set to PGPIO45 input. If GPIO6 is high, the full EMIF mode is enabled and HC1 is set to HPI.HBIL input. Host byte identification. HPI.HBIL is selected when GPIO6 is high at reset. Parallel general-purpose I/O 45. PGPIO45 is selected when GPIO6 is low at reset. HPI host control 0 HPI host control 1 HPI host chip-select HPI host read- or write-select Host data strobe 1 Host data strobe 2 Host ready Host interrupt HPI enable. HPIENA must be pulled high and kept high in systems that use the HPI. If the HPI is not needed, HPIENA can be pulled low. An internal pulldown resistor is active on this pin. Initialization, Interrupt, and Reset Pins INT[3:0] I C, L C, F, J, M F, M External user interrupt. INT0-INT3 are maskable interrupts. They are prioritized by the Interrupt Enable Register (IER) and the interrupt mode bit. INT[3:0] can be polled and reset by way of the interrupt flag register. Non-maskable interrupt input and/or Watchdog Timer output. The function of this pin is controlled by the Timer Selection Register. Interrupt acknowledge Reset. RESET causes the digital signal processor (DSP) to terminate current program execution. When RESET is brought to a high level, program execution begins by fetching the reset interrupt service routine vector at the reset vector address FFFF00h (IVPD:FFFFh). RESET affects various registers and status bits. Function PRODUCT PREVIEW HR/W HDS1 HDS2 HRDY HINT HPIENA NMI/WDTOUT IACK I/O/Z O/Z RESET I C, L I = Input, O = Output, S = Supply, Z = High impedance Other Pin Characteristics: A - Internal pullup (always enabled) E - Pin is high impedance in HOLD mode (due to HOLD pin). B - Internal pulldown (always enabled) F - Pin is high impedance in OFF mode (due to EMU1/OFF pin). C - Hysteresis input G - Pin can be configured as a general-purpose input. D - Pin has bus holder H - PIn can be configured as a general-purpose output. J - Internal pullup enabled through the External Bus Control Register (XBCR) K - Internal pulldown enabled through the External Bus Control Register (XBCR) L - Fail-safe pin M - Pin is in high-impedance during reset (RESET pin is low) 12 SPRS208 December 2002 Introduction Table 2-3. Signal Descriptions (Continued) Pin Name Multiplexed Signal Name Pin Type Other Bit I/O Signals General-purpose I/O. Eight input/output lines that can be individually configured as inputs or outputs, and can also be individually set or reset when configured as outputs. At reset, the eight pins (GPIO[7:0]) are configured as inputs. These pins are latched with the rising edge of RESET and their state is used to determine the HPI16 non-multiplexed mode, boot mode of the bootloader, and the serial-port mode. GPIO[0-2] are used for boot-mode selection of the bootloader. The GPIO[2:0] pins are sampled at reset and are stored in the BOOT_MOD (0x000F) register. GPIO3 is multiplexed with the CLKX pin of McBSP2. At reset, if GPIO7 is low, the McBSP2 pins are disabled and this pin has the function of GPIO3. If GPIO7 is high, the McBSP2 pins are enabled and this pin has the function of the CLKX2. GPIO4 is used as a function of the clock mode pin. At reset, if GPIO4 is low, the PLL is bypassed with clock running at input clock rate and the oscillator disabled. If GPIO4 is high, the PLL is bypassed with clock rate running at input clock rate and the oscillator enabled. GPIO4 is also used as an output for handshaking purposes on some of the boot modes. Although this pin is not involved in boot mode selection, users should be aware that this pin will become active as an output during the bootload process and should design accordingly. After the bootload is complete, the loaded application may change the function of the GPIO4 pin. GPIO5 is multiplexed with the FSX pin of McBSP2. At reset, if the GPIO7 is low, the McBSP2 pins are disabled and this pin has the function of GPIO5. If GPIO7 is high, the McBSP2 pins are enabled and this pin has the function of the FSX2. GPIO6 is used as HPI16. At reset, if GPIO6 is low, the parallel bus is used as the HPI16 non-multiplexed mode. GPIO7 is used as the McBSP2 mode. At reset, if GPIO7 is low, the McBSP2 pins are disabled. External output (latched software-programmable signal). XF is set high by the BSET XF instruction, set low by BCLR XF instruction, or by loading ST1. XF is used for signaling other processors in multiprocessor configurations or used as a general-purpose output pin. Oscillator/Clock Signals CLKOUT X2/CLKIN X1 O/Z I O F Master clock output signal. CLKOUT can be set to reflect the clock of fast peripherals (DMA, HPI, ...), slow peripherals (I2C, UART, ...0), or EMIF clock. Clock/oscillator input. If the internal oscillator is not being used, X2/CLKIN functions as the clock input. Output pin from the internal oscillator for the crystal. If the internal oscillator is not used, X1 should be left unconnected. Function GPIO[7:0] I/O/Z F, G, H, M XF O/Z F I = Input, O = Output, S = Supply, Z = High impedance Other Pin Characteristics: A - Internal pullup (always enabled) E - Pin is high impedance in HOLD mode (due to HOLD pin). B - Internal pulldown (always enabled) F - Pin is high impedance in OFF mode (due to EMU1/OFF pin). C - Hysteresis input G - Pin can be configured as a general-purpose input. D - Pin has bus holder H - PIn can be configured as a general-purpose output. J - Internal pullup enabled through the External Bus Control Register (XBCR) K - Internal pulldown enabled through the External Bus Control Register (XBCR) L - Fail-safe pin M - Pin is in high-impedance during reset (RESET pin is low) December 2002 SPRS208 13 PRODUCT PREVIEW Introduction Table 2-3. Signal Descriptions (Continued) Pin Name Multiplexed Signal Name Pin Type Other Timer Signals F, G, H, M Input/Output terminal from Timer 0. When configured as an output, TIM0 signals a pulse or a change of state when the on-chip timer count matches its period. When configured as an input, TIM0 provides the clock source for the internal timer module. At reset, this pin is configured as input. This pin can also be used as general-purpose I/O. Input/Output terminal from Timer 1. When configured as an output, TIM1 signals a pulse or a change of state when the on-chip timer count matches its period. When configured as an input, TIM1 provides the clock source for the internal timer module. At reset, this pin is configured as input. This pin can also be used as general-purpose I/O. Function TIM0 I/O/Z TIM1 I/O/Z F, G, H, M Multichannel Buffered Serial Port Signals CLKR0 DR0 FSR0 I/O/Z I I/O/Z I/O/Z O/Z I/O/Z I/O/Z I I/O/Z O/Z I/O/Z I/O/Z C, F, G, H, M L, G F, G, H, M C, F, G, H, M F, H, M F, G, H, M C, G, H, M L, G F, G, H, M F, H, M C, F, G, H, M F, G, H, M Receive clock input of McBSP0 Serial data receive input of McBSP0 Frame synchronization pulse for receive input of McBSP0 Transmit clock of McBSP0 Serial data transmit output of McBSP0 Frame synchronization pulse for transmit output of McBSP0 Receive clock input of McBSP1 Serial data receive input of McBSP1 Frame synchronization pulse for receive input of McBSP1 Serial data transmit output of McBSP1 Transmit clock of McBSP1 Frame synchronization pulse for transmit output of McBSP1 PRODUCT PREVIEW CLKX0 DX0 FSX0 CLKR1 DR1 FSR1 DX1 CLKX1 FSX1 I = Input, O = Output, S = Supply, Z = High impedance Other Pin Characteristics: A - Internal pullup (always enabled) E - Pin is high impedance in HOLD mode (due to HOLD pin). B - Internal pulldown (always enabled) F - Pin is high impedance in OFF mode (due to EMU1/OFF pin). C - Hysteresis input G - Pin can be configured as a general-purpose input. D - Pin has bus holder H - PIn can be configured as a general-purpose output. J - Internal pullup enabled through the External Bus Control Register (XBCR) K - Internal pulldown enabled through the External Bus Control Register (XBCR) L - Fail-safe pin M - Pin is in high-impedance during reset (RESET pin is low) 14 SPRS208 December 2002 Introduction Table 2-3. Signal Descriptions (Continued) Pin Name Multiplexed Signal Name Pin Type Other McBSP2/UART DR2 DX2 SP0 I O/Z I/O/Z L, G F, H, M C, F, M McBSP2 data receive input McBSP2 data transmit output McBSP2 transmit clock or GPIO3. At reset, if GPIO7 is low, the McBSP2 pins are disabled and this pin has the function of GPIO3. If GPIO7 is high, the McBSP2 pins are enabled and this pin has the function of the CLKX2. McBSP2 transmit clock. CLKX2 is selected when GPIO7 is high at reset or the External Bus Selection Register has a 1 in the Serial Port2 Mode bit field. GPIO3. Selected when GPIO7 is low at reset or the External Bus Selection Register has a 0 in the Serial Port2 Mode bit field. McBSP2 receive clock or UART transmit data output. At reset, GPIO7 is sampled. If GPIO7 is low, the McBSP2 pins are disabled and SP1 is set to UART.TX output. If GPIO7 is high, the McBSP2 pins are enabled and SP1 is set to CLKR2 input. McBSP2 receive clock. CLKR2 is selected when GPIO7 is high at reset or the External Bus Selection Register has a 1 in the Serial Port2 Mode bit field. UART transmit data output. UART.TX is selected when GPIO7 is low at reset or the External Bus Selection Register has a 0 in the Serial Port2 Mode bit field. F, M Frame synchronization pulse for transmit or GPIO5. At reset, if GPIO7 is low, the McBSP2 pins are disabled and this pin has the function of GPIO5. If GPIO7 is high, the McBSP2 pins are enabled and this pin has the function of the FSX2. Frame synchronization pulse for transmit output of McBSP2. FSX2 is selected when GPIO7 is high at reset or the External Bus Selection Register has a 1 in the Serial Port2 Mode bit field. GPIO5. Selected when GPIO7 is low at reset or the External Bus Selection Register has a 0 in the Serial Port2 Mode bit field. Frame synchronization pulse for receive input of McBSP2 or UART receive data input. At reset, GPIO7 is sampled. If GPIO7 is low, the McBSP2 pins are disabled and SP3 is set to UART receive data input. If GPIO7 is high, the McBSP2 pins are enabled and SP3 is set to FSR2 input. Frame synchronization pulse for receive input of McBSP2. FSR2 is selected when GPIO7 is high at reset or the External Bus Selection Register has a 1 in the Serial Port2 Mode bit field. UART receive data input. UART.RX is selected when GPIO7 is low at reset or the External Bus Selection Register has a 0 in the Serial Port2 Mode bit field. I2C Pins C, F, M I2C clock bidirectional port. (Open collector I/O) I2C data bidirectional port. (Open collector I/O) Function CLKX2 GPIO3 I/O O G, H G, H SP1 I/O/Z C, F, M CLKR2 UART.TX I/O O G, H SP2 I/O/Z FSX2 I/O/Z G, H GPIO5 I/O/Z G, H SP3 I/O/Z F, M FSR2 I/O/Z G, H UART.RX I SCL I/O/Z SDA I/O/Z C, F, M I = Input, O = Output, S = Supply, Z = High impedance Other Pin Characteristics: A - Internal pullup (always enabled) E - Pin is high impedance in HOLD mode (due to HOLD pin). B - Internal pulldown (always enabled) F - Pin is high impedance in OFF mode (due to EMU1/OFF pin). C - Hysteresis input G - Pin can be configured as a general-purpose input. D - Pin has bus holder H - PIn can be configured as a general-purpose output. J - Internal pullup enabled through the External Bus Control Register (XBCR) K - Internal pulldown enabled through the External Bus Control Register (XBCR) L - Fail-safe pin M - Pin is in high-impedance during reset (RESET pin is low) December 2002 SPRS208 15 PRODUCT PREVIEW Introduction Table 2-3. Signal Descriptions (Continued) Pin Name Multiplexed Signal Name Pin Type Other Supply Pins VSS CVDD PVDD PSENSE DVDD S S S S Digital Ground. Dedicated ground for the device. Digital Power, + VDD. Dedicated power supply for the core CPU. Digital Power, + VDD. Dedicated power supply for the PLL module. For test purposes only. Must be left unconnected. Digital Power, + VDD. Dedicated power supply for the I/O pins. Test Pins IEEE standard 1149.1 test clock. TCK is normally a free-running clock signal with a 50% duty cycle. The changes on test access port (TAP) of input signals TMS and TDI are clocked into the TAP controller, instruction register, or selected test data register on the rising edge of TCK. Changes at the TAP output signal (TDO) occur on the falling edge of TCK. IEEE standard 1149.1 test data input. Pin with internal pullup device. TDI is clocked into the selected register (instruction or data) on a rising edge of TCK. IEEE standard 1149.1 test data output. The contents of the selected register (instruction or data) are shifted out of TDO on the falling edge of TCK. TDO is in the high-impedance state except when the scanning of data is in progress. J IEEE standard 1149.1 test mode select. Pin with internal pullup device. This serial control input is clocked into the TAP controller on the rising edge of TCK. IEEE standard 1149.1 test reset. TRST, when high, gives the IEEE standard 1149.1 scan system control of the operations of the device. If TRST is not connected or driven low, the device operates in its functional mode, and the IEEE standard 1149.1 signals are ignored. Pin with internal pulldown device. Emulator 0 pin. When TRST is driven low, EMU0 must be high for activation of the OFF condition. When TRST is driven high, EMU0 is used as an interrupt to or from the emulator system and is defined as I/O by way of the IEEE standard 1149.1 scan system. Emulator 1 pin/disable all outputs. When TRST is driven high, EMU1/OFF is used as an interrupt to or from the emulator system and is defined as I/O by way of IEEE standard 1149.1 scan system. When TRST is driven low, EMU1/OFF is configured as OFF. The EMU1/OFF signal, when active (low), puts all output drivers into the high-impedance state. Note that OFF is used exclusively for testing and emulation purposes (not for multiprocessing applications). Therefore, for the OFF condition, the following apply: TRST = low, EMU0 = high, EMU1/OFF = low Function TCK I C, J TDI I J PRODUCT PREVIEW TDO O/Z TMS I TRST I C, L, K EMU0 I/O/Z J EMU1/OFF I/O/Z J I = Input, O = Output, S = Supply, Z = High impedance Other Pin Characteristics: A - Internal pullup (always enabled) E - Pin is high impedance in HOLD mode (due to HOLD pin). B - Internal pulldown (always enabled) F - Pin is high impedance in OFF mode (due to EMU1/OFF pin). C - Hysteresis input G - Pin can be configured as a general-purpose input. D - Pin has bus holder H - PIn can be configured as a general-purpose output. J - Internal pullup enabled through the External Bus Control Register (XBCR) K - Internal pulldown enabled through the External Bus Control Register (XBCR) L - Fail-safe pin M - Pin is in high-impedance during reset (RESET pin is low) 16 SPRS208 December 2002 Functional Overview 3 Functional Overview The following functional overview is based on the block diagram in Figure 3-1. P, B, C, D, E, and F Buses and Control Signals Cbus Dbus Cbus Dbus Cbus Bbus Bbus Pbus Ebus Pbus Ebus Pbus Fbus Fbus Dbus 55x Core 32K Dual-Access RAM Program/Data 16K ROM Program/Data TCK TMS TDI TDO TRST EMU0 EMU1/OFF ECLKIN ECLKOUT1 ECLKOUT2 EMIFCLKS Peripheral Bus Emulation Control DMA Bus [2:0] 4 [7:6] GPIO 3 5 GPIO[2:0] GPIO4 GPIO[7:6] External Memory Interface McBSP0 Receive Parallel Port MUX A[21:18] D[31:16] C0-C15 A[17:2] D[15:0] A[21:18] D[31:16] C0-C15 A[17:2] D[15:0] [3:0] [19:4] [35:20] [43:36] 44 PGPIO 45 A[15:0] D[15:0] HD[7:0] HAS HBIL HPI Module McBSP1 FSX1 DX1 CLKX1 FSR1 DR1 CLKR1 Transmit Receive DX2 McBSP2 DR2 Rx Tx Serial Port MUX SP0 SP1 SP2 SP3 UART HD[7:0] HC0 HC1 Host Port MUX HCNTL0 HCNTL1 HCS HR/W HDS1 HDS2 HRDY HINT HPIENA Muxing Logic DMA Controller 6 Channels I2C SDL SDA TIM0 Timer 0 Timer 1 Interrupt Logic NMI INT3 RESET INT[2:0] TIM1 WDTimer WDTOUT X1 CLKIN CLKOUT NMI/WDTOUT INT3 RESET INT[2:0] APLL Figure 3-1. Block Diagram of the TMS320VC5502 December 2002 SPRS208 17 PRODUCT PREVIEW FSX0 DX0 CLKX0 FSR0 DR0 CLKR0 Transmit Functional Overview 3.1 Memory The 5502 supports a unified memory map (program and data accesses are made to the same physical space). The total on-chip memory is 48K words (32K 16-bit words of RAM and 16K 16-bit words of ROM). 3.1.1 On-Chip ROM TMS320VC5502 incorporates 16K x16-bit of on-chip, one-wait-state maskable ROM that can be mapped into program memory space. The ROM contains a bootloader program to facilitate system initialization. This bootloader can be used to automatically transfer user code from an external source to anywhere in the program memory at power up. The ROM can be masked. The on-chip ROM is located at the byte address range FF8000h-FFFFFFh when bit MP/MC = 0. It can be accessed by the program bus and the three read data buses P, C, and D. The on-chip ROM is a one-cycle-per-word memory access, except for the first word access, which requires two cycles. When MP/MC = 1 at reset, the on-chip ROM is disabled and not present in the memory map, and byte address range FF8000h-FFFFFFh is directed to external memory space. The status of the MP/MC bit (located in the ST3_55 status register) is determined by the logic level on the BOOTM[2:0] pins when sampled at reset. If BOOTM[2:0] is set to 00h or 04h at reset, the MP/MC bit is set to 1 and the on-chip ROM is disabled. Otherwise, the MP/MC bit is cleared to 0 and the on-chip ROM is enabled. These pins are not sampled again until the next hardware reset. The software reset instruction does not affect the MP/MC bit. Software can also be used to set or clear the MP/MC bit. The Bootloader mode selection is determined by the logic level on the GPIO[2:0] pins when sampled at reset. A branch instruction to the start of the Bootloader program is contained at FF8000h. TMS320VC5502 provides different ways to download the code to accommodate various system requirements: * * * * * * Parallel boot from 16-bit asynchronous memory connected to the EMIF at 200000h Serial boot from McBSP0 (McBSP0 in SPI mode or standard mode) Host-port interface boot load in non-multiplexed mode Host-port interface boot load in multiplexed mode I2C boot load UART boot load PRODUCT PREVIEW The standard on-chip ROM layout is shown in Table 3-1. Table 3-1. On-Chip ROM Layout STARTING BYTE ADDRESS FF_8000h FF_ECB0h FF_ED00h FF_EF00h FF_FF00h FF_FFFCh CONTENTS Bootloader program Boot Mode Branch Table Sine Table Factory Test Code Interrupt Vector Table ID Code 18 SPRS208 December 2002 Functional Overview 3.1.2 On-Chip Dual-Access RAM (DARAM) TMS320VC5502 features 32K x 16-bit (64K bytes) of on-chip dual-access RAM. This memory enhances system performance, since the C55x CPU can access a DARAM block twice per machine cycle. The DARAM is composed of 8 blocks of 4K x 16-bit each (see Table 3-2). Each block in the DARAM can support two reads in one cycle, a read and a write in one cycle, or two writes in one cycle. The dual-access RAM is located in the (byte) address range 000000h-00FFFFh, it can be accessed by the program, data and DMA buses. The HPI has NO access to the DARAM block when device is in reset. Table 3-2. DARAM Blocks BYTE ADDRESS RANGE 000000h - 001FFFh 002000h - 003FFFh 004000h - 005FFFh 006000h - 007FFFh 008000h - 009FFFh 00A000h - 00BFFFh 00C000h - 00DFFFh 00E000h - 00FFFFh MEMORY BLOCK DARAM 0 DARAM 1 DARAM 2 DARAM 3 DARAM 4 DARAM 5 DARAM 7 DARAM 6 December 2002 SPRS208 19 PRODUCT PREVIEW Functional Overview 3.1.3 Memory Map 000000h DARAM0 (8K Bytes) 002000h DARAM1 (8K Bytes) 004000h DARAM2 (8K Bytes) 006000h DARAM3 (8K Bytes) 008000h DARAM4 (8K Bytes) 002000h DARAM1 (8K Bytes) 004000h DARAM2 (8K Bytes) 006000h DARAM3 (8K Bytes) 008000h DARAM4 (8K Bytes) 00A000h DARAM5 (8K Bytes) DARAM6 (8K Bytes) 00E000h DARAM7 (8K Bytes) 010000h External CE0 Space (4M minus 64K Bytes) 400000h External CE1 Space (4M Bytes) 800000h External CE2 Space (4M Bytes) C00000h External CE3 Space (4M Bytes) FF8000h ROM (32K Bytes) MP/MC = 0 The 64K bytes are the on-chip DARAM block. MP/MC = 1 External CE3 Space (4M Bytes) C00000h 800000h External CE2 Space (4M Bytes) 400000h External CE1 Space (4M Bytes) External CE0 Space (4M minus 64K Bytes) 000000h DARAM0 (8K Bytes) PRODUCT PREVIEW 00A000h DARAM5 (8K Bytes) 00C000h DARAM6 (8K Bytes) 00E000h DARAM7 (8K Bytes) 010000h 00C000h Figure 3-2. TMS320VC5502 Memory Map 20 SPRS208 December 2002 Functional Overview 3.1.4 Boot Configuration The on-chip bootloader provides a way to transfer application code and tables from an external source to the on-chip RAM at power up. The 5502 provides several options to download the code to accommodate varying system requirements. These options include: * * * * * * * Host-port interface (HPI) boot, both in multiplexed and non-multiplexed modes External memory boot (via EMIF) from 16-bit asynchronous memory Serial port boot (from McBSP0) with 16-bit element length SPI EPROM boot (from McBSP0) supporting EPROMs with 24-bit addresses I2C EPROM boot (from I2C) supporting EPROMs larger than 512K bits UART boot Direct execution (no boot) from 16- or 32-bit external asynchronous memory The external pins BOOTM2, BOOTM1, and BOOTM0 select the boot configuration. The values of BOOTM[2:0] are latched with the rising edge of the RESET input. BOOTM2 is shared with GPIO2, BOOTM1 is shared with GPIO1, and BOOTM0 is shared with GPIO0. The boot configurations available are summarized in Table 3-3. BOOTM[2:0] 000 001 010 011 100 101 110 111 SPI EPROM boot Serial port boot (from McBSP0) BOOT PROCESS Direct execution from 16-bit external asynchronous memory External memory boot (via EMIF) from 16-bit asynchronous memory Direct execution from 32-bit external asyncrhonous memory HPI boot I2C EPROM boot UART boot 3.2 Peripherals The 5502 supports the following on-chip peripherals: * * * * * * An external memory interface (EMIF) - Supporting a 32-bit interface to asynchronous memory, SDRAM, and SBSRAM A host-port interface (HPI) - Configurable to 8 bits (multiplexed mode) or 16 bits (non-multiplexed mode) A six-channel direct memory access (DMA) controller Three multichannel buffered serial ports (McBSPs) A programmable analog phase-locked loop (APLL) clock generator General-purpose I/O (GPIO) pins and a dedicated output pin (XF) The 5502 can be configured as follows: * 32-bit external memory interface with 8-bit (multiplexed) host-port interface * no external memory interface with 16-bit (non-multiplexed) host-post interface December 2002 SPRS208 21 PRODUCT PREVIEW Table 3-3. Boot Configuration Selection Via the BOOTM[2:0] Pins Functional Overview * Four timers - - - Two 64-bit general-purpose timers A programmable watchdog timer A DSP/BIOS timer * * An Inter-integrated Circuit (I2C) multi-master and slave interface A Universal Asynchronous Receiver/Transmitter (UART) For detailed information on the C55x DSP peripherals, see the following documents: * * TMS320C55x DSP Functional Overview (literature number SPRU312) TMS320C55x DSP Peripherals Reference Guide (literature number SPRU317) 3.3 Configurable External Ports and Signals A number of pins on the 5502 have two functions, a feature that allows system designers to choose an appropriate media interface for his/her application without the need for a large pin-count package. Three muxes are included in the 5502 to control the configuration of these dual-function pins: the Parallel Port Mux, the Host Port Mux, and the Serial Port Mux. The state of these muxes is set at reset based on the state of the GPIO6 and GPIO7 pins. The External Bus Selection Register (XBSR) shows the configuration of these muxes after the 5502 comes out of reset. PRODUCT PREVIEW 3.3.1 Parallel Port Mux The Parallel Port Mux of the 5502 controls the function of 20 address signals (pins A[21:2]), 32 data signals (pins D[31:0]), and 16 control signals (pins C0 through C15). The Parallel Port Mux supports two different modes: * * Full EMIF mode: The EMIF is enabled and its 20 address, 32 data, and 16 control signals are routed to their corresponding pins on the Parallel Port Mux. Non-multiplexed HPI mode: The HPI is enabled with its 16 address, 16 data, and 9 control signals routed to their corresponding pins on the Parallel Port Mux. Moreover, 16 control signals, 4 address signals, and 16 data signals of the Parallel Port Mux that are not needed for HPI operation are set to general-purpose I/O (PGPIO). The mode of the Parallel Port Mux is determined by the state of the GPIO6 pin at reset. If GPIO6 is low, the EMIF will be disabled and the HPI will be enabled in non-multiplexed mode: pins A[17:2] are set to HPI.A[15:0] and pins D[15:0] are set to HPI.D[15:0]. All address, data, and control signals in the Parallel Port Mux not needed by the HPI are set to parallel general-purpose I/O. The Parallel/Host Port Mux Mode bit field in the External Bus Selection Register (XBSR) will also be set to 0 to reflect the non-multiplexed HPI mode of the Parallel Port Mux. If GPIO6 is high at reset, the HPI will be enabled in multiplexed mode and the EMIF will be fully enabled: pins A[21:2] are set to EMIF.A[21:2], pins D[31:0] are set to EMIF[31:0], and pins C[15:0] are set to their corresponding EMIF operation. The Parallel/Host Port Mux Mode bit field in the XBSR will be set to 1 to reflect the full EMIF mode of the Parallel Port Mux. Note that in multiplexed mode, the HPI will use the HD[7:0] pins to strobe in address and data information (see Section 3.7, Host-Port Interface (HPI), for more information on the operation of the HPI in multiplexed and non-multiplexed modes). 22 SPRS208 December 2002 Functional Overview Table 3-4 lists the individual routing of the EMIF, PGPIO, and HPI signals to the external parallel address, data, and control buses. Table 3-4. TMS320VC5502 Routing of Parallel Port Mux Signals PARALLEL PORT MUX MODE = 0 (HPI NON-MULTIPLEX) Address Bus A[17:2] A[21:18] D[15:0] D[31:16] C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 HPI.A[15:0] PGPIO[3:0] Data Bus HPI.D[15:0] PGPIO[19:4] Control Bus PGPIO20 PGPIO21 PGPIO22 PGPIO23 PGPIO24 PGPIO25 PGPIO26 PGPIO27 PGPIO28 PGPIO29 PGPIO30 PGPIO31 PGPIO32 PGPIO33 PGPIO34 PGPIO35 EMIF.ARE/SADS/SDCAS/SRE EMIF.AOE/SOE/SDRAS EMIF.AWE/SWE/SDWE EMIF.ARDY EMIF.CE1 EMIF.CE2 EMIF.CE3 EMIF.BE0 EMIF.BE1 EMIF.BE2 EMIF.BE3 EMIF.SDCKE EMIF.SOE3 EMIF.HOLD EMIF.HOLDA EMIF.CE0 EMIF.D[15:0] EMIF.D[31:16] EMIF.A[17:2] EMIF.A[21:18] PARALLEL PORT MUX MODE = 1 (FULL EMIF) PIN 3.3.2 Host Port Mux The 5502 Host Port Mux controls the function of 8 data signals (pins HD[7:0]) and 2 control signals (pins HC0 and HC1). The Host Port Mux supports two different modes: * * 8-bit multiplexed mode: The HPI's 8 data and 2 control signals are routed to their corresponding pins on the Host Port Mux. Parallel general-purpose I/O mode: All pins on the Host Port Mux are routed to PGPIO. The HPI is enabled to 16-bit (non-multiplexed) mode, but communicates through the Parallel Port Mux. The mode of the Host Port Mux is determined by the state of the GPIO6 pin at reset. If GPIO6 is low, the pins of the Host Port Mux will be set to PGPIO. The HPI will still be enabled, but it will communicate through the Parallel Port Mux. The Parallel/Host Port Mux Mode bit of the External Bus Control Register will be set to 0 to reflect the PGPIO mode of the Host Port Mux. If GPIO6 is high, the HPI will be enabled in 8-bit (multiplexed) mode: pins HD[7:0] are set to HPI.HD[7:0], and HC0 and HC1 are set to HPI.HAS and HPI.HBIL, respectively. The Parallel/Host Port Mux Mode bit field in the XBSR will be set to 1 to reflect the HPI multiplexed mode of the Host Port Mux. See Section 3.7, Host-Port Interface (HPI), for more information on the operation of the HPI in multiplexed and non-multiplexed modes. December 2002 SPRS208 23 PRODUCT PREVIEW Functional Overview Table 3-5 lists the individual routing of the HPI and PGPIO signals to the Host Port Mux pins. Table 3-5. TMS320VC5502 Routing of Host Port Mux Signals PIN HOST PORT MUX MODE = 0 (PGPIO) Data Bus HD[7:0] HC0 HC1 PGPIO[43:36] Control Bus PGPIO44 PGPIO45 HPI.HAS HPI.HBIL HPI.HD[7:0] HOST PORT MUX MODE = 1 (8-BIT HPI MULTIPLEXED) 3.3.3 Serial Port Mux The 5502 has three serial ports: McBSP0, McBSP1, and McBSP2, each of which has six signals. The signals for McBSP0 and McBSP1 are directly routed to pins on the 5502. Four of the pins for McBSP2 are multiplexed with two pins of the on-chip UART and two pins of the GPIO, the mode of the Serial Port Mux determines which signals are routed to the 5502 pins. The mode of the Serial Port Mux is determined by the state of the GPIO7 pin at reset. If GPIO7 is low, the UART is enabled and its RX and TX pins are routed to the SP1 and SP3 pins, respectively. The GPIO3 and GPIO5 pins are routed to the SP0 and SP2 pins, respectively. In this mode, McBSP2 will be disabled and any writes or reads to/from its registers will result in a bus error if the PERITOEN bit of the Time-Out Control Register is set to 1. If GPIO7 is high, McBSP2 will be enabled and its CLKX2, CLKR2, FSX2, and FSR2 signals will be routed to the SP0, SP1, SP2, and SP3 pins, respectively. In this mode, the UART will be disabled and any writes or reads to/from its registers will result in a bus error if the PERITOEN bit of the Time-Out Control Register is set to 1. GPIO3 and GPIO5 will not be available during this mode of the Serial Port Mux. Table 3-6 lists the individual routing of the McBSP2, UART, and GPIO signals to the Serial Port Mux pins. Table 3-6. TMS320VC5502 Routing of Serial Port Mux Signals PIN SP0 SP1 SP2 SP3 SERIAL PORT MUX MODE = 0 GPIO3 UART.TX GPIO5 UART.RX SERIAL PORT MUX MODE = 1 CLKX2 CLKR2 FSX2 FSR2 PRODUCT PREVIEW 24 SPRS208 December 2002 Functional Overview 3.3.4 External Bus Selection Register (XBSR) The External Bus Selection Register controls the mode of the Parallel Port Mux, Host Port Mux, and the Serial Port Mux. The Parallel Port Mux can be configured to support the 32-bit EMIF or to support the HPI in 16-bit (non-multiplexed) mode and parallel general-purpose I/O. The Host Port Mux can be configured to support the HPI in 8-bit (multiplexed) mode or parallel general-purpose I/O (PGPIO). The Serial Port Mux can be configured to support either the McBSP2 or the UART and general-purpose I/O. The XBSR configures the Parallel Port Mux and the Host Port Mux at reset based on the state of the GPIO6 pin. When GPIO6 is high at reset, the Parallel Port Mux will be configured to support the 32-bit EMIF and the Host Port Mux will be configured to support the HPI in 8-bit (multiplexed) mode. When GPIO6 is low at reset, the Parallel Port Mux will be configured to support the HPI in 16-bit (non-multiplexed) mode and parallel general-purpose I/O (PGPIO) and the Host Port Mux will be configured to support parallel general-purpose I/O. The Paralle/Host Port Mux Mode bit of the XBSR will reflect the mode selected for the Parallel and Host Port Muxes. The XBSR configures the Serial Port Mux based on the state of the GPIO7 pin at reset. When GPIO7 is high at reset, the Serial Port Mux will be configured to support the McBSP2. When GPIO7 is low at reset, the Serial Port Mux will be configured to support the UART and general-purpose I/O (PGPIO). The Serial Port Mux Mode bit of the XBSR will reflect the mode selected for the Serial Port Mux. The clock to the McBSP2, UART, and EMIF modules is disabled automatically when these modules are not selected through the External Bus Selection Register. Note that any accesses to disabled modules will result in a bus error if the PERITOEN bit of the Time-Out Control Register is set to 1. 15 Reserved R, 00000000 8 7 4 3 Reserved R/W, 0 2 Serial Port Mux Mode R/W, GPIO7 1 0 Parallel /Host Port Mux Mode R/W, GPIO6 Reserved R, 0000 LEGEND: R = Read, W = Write, n = value at reset This reserved bit must be kept as zero during any writes to XBSR. Reserved R, 0 Figure 3-3. External Bus Selection Register Layout (0x6C00) Modifying the XBSR to change the mode of the Parallel Port Mux, Host Port Mux, and Serial Port Mux after the 5502 has been brought out of reset is not recommended. December 2002 SPRS208 25 PRODUCT PREVIEW Functional Overview Table 3-7. External Bus Selection Register Bit Field Description BIT NAME Reserved Reserved Serial Port Mux Mode BIT NO. 15-4 3 2 ACCESS R R/W R/W RESET VALUE 000000000000 0 GPIO7 Reserved Reserved. This reserved bit must be kept as zero during any writes to XBSR. Serial Port Mux Mode bit. Determines the mode of the third serial port. Serial Port Mux Mode = 0: The Serial Port Mux is configured to support the McBSP2. In this mode, the McBSP2 is enabled and its six signals are routed to their corresponding pins on the Serial Port Mux. The Serial Port Mux is configured to support the UART and PGPIO. In this mode, the UART is enabled and its two signals are routed to the corresponding pins on the Serial Port Mux. GPIO3 and GPIO5 are also routed to their corresponding pins on the Serial Port Mux. DESCRIPTION Serial Port Mux Mode = 1: Reserved 1 0 R R/W 0 GPIO6 Reserved Parllel/Host Port Mux Mode bit. Determines the mode of the Parallel Port Mux and the Host Port Mux. * Parallel/Host Port Mux Mode = 0: The Parallel Port Mux is configured to support the HPI in 16-bit (non-multiplexed) mode and PGPIO. In this mode, the HPI is enabled and its 16 address, 16 data, and 9 control signals are routed to their corresponding pins on the Parallel Port Mux. The rest of the pins are routed to PGPIO. The EMIF cannot be used in this mode. The Host Port Mux is configured to support PGPIO. In this mode, the Host Port Mux pins will be routed to PGPIO. Parallel/Host Port Mux Mode = 1: The Parallel Port Mux is configured to support the 32-bit EMIF. In this mode, the EMIF is enabled and its 20 address, 32 data, and 16 control signals are routed to their corresponding pins on the Parallel Port Mux. The Host Port Mux is configured to support the HPI in 8-bit (multiplexed) mode. In this mode, the HPI is enabled and its eight data/address and two control signals are routed to their corresponding pins on the Host Port Mux. PRODUCT PREVIEW Parallel/Host Port Mux Mode * 3.4 Timers The 5502 has four 64-bit timers: Timer 0, Timer 1, Watchdog Timer (WDT), and Timer 3. The input/output pin of Timer 0, Timer 1, and the Watchdog Timer can be configured as an input or an output via the Timer Signal Selection Register (TSSR). Furthermore, the TSSR can be used to connect the Watchdog Timer output to NMI, RESET, or INT3. * * The first two timers, Timer 0 and Timer 1, are mainly used as general-purpose timers. The third timer, the Watchdog Timer, can be used as either a general-purpose timer or a watchdog timer. The output pin of the Watchdog Timer, WDTOUT, is multiplexed with the NMI input pin; its function can be controlled via the NMI/WDTOUT_CFG bit of the TSSR. If the NMI/WDTOUT pin is configured as the Watchdog Timer pin, it can be configured as an input or an output via the WDT_MODE bit of the TSSR. The Watchdog Timer output can also be internally connected to the NMI, RESET, and INT3 signals of the 5502 via the IWCON bits of the TSSR. The fourth timer is reserved as a DSP/BIOS counter. This timer has no input or output pin. No interrupts are needed from this timer; therefore, the timer output is not internally connected to the CPU interrupt logic. * 26 SPRS208 December 2002 Functional Overview 3.4.1 Timer Signal Selection Register (TSSR) The Timer Signal Selection Register (TSSR) controls several pin characteristics for Timer 0, Timer 1, and the Watchdog Timer. The TSSR can be used to specify whether the pins of Timer 0, Timer 1, and the Watchdog Timer are input or output. The TSSR also determines how the output signal of the Watchdog Timer is connected internally and sets the function for the NMI/WDTOUT pin of the 5502. By default, all the timer pins (TIM0, TIM1, and NMI/WDTOUT) are set as inputs, the output of the Watchdog Timer is not internally connected to anything, and the NMI/WDTOUT pin has the function of the NMI signal. 15 Reserved R, 00000000 8 7 6 5 4 3 2 1 0 NMI/WDTOUT _CFG R/W, 1 Reserved R, 00 WDT_MODE R/W, 0 TIM1_MODE R/W, 0 TIM0_MODE R/W, 0 IWCON R/W, 00 LEGEND: R = Read, W = Write, n = value at reset Figure 3-4. Timer Signal Selection Register Layout (0x8000) Table 3-8. Timer Signal Selection Register Bit Field Description BIT NAME Reserved WDT_MODE BIT NO. 15-6 5 ACCESS R R/W RESET VALUE 0000000000 0 Reserved WDT pin mode WDT_MODE = 0: WDT_MODE = 1: TIM1_MODE 4 R/W 0 TIM1 pin mode TIM1_MODE = 0: TIM1_MODE = 1: TIM0_MODE 3 R/W 0 TIM0 pin mode TIM0_MODE = 0: TIM0_MODE = 1: TIM0 pin is used as the timer input pin. TIM0 pin is used as the timer output pin. TIM1 pin is used as the timer input pin. TIM1 pin is used as the timer output pin. WDTOUT pin is used as the timer input pin. WDTOUT pin is used as the timer output pin. DESCRIPTION If NMI/WDTOUT_CFG = 1 and IWCON = 10, only the WDTOUT signal will drive the NMI signal; the external source driving the NMI/WDTOUT pin will be ignored (see Figure 3-5). December 2002 SPRS208 27 PRODUCT PREVIEW Functional Overview Table 3-8. Timer Signal Selection Register Bit Field Description (Continued) BIT NAME IWCON BIT NO. 2:1 ACCESS R/W RESET VALUE 00 DESCRIPTION Internal WDT output signal connection IWCON = 00: IWCON = 01: IWCON = 10: IWCON = 11: NMI/WDTOUT_CFG 0 R/W 1 Internal watchdog timer output signal has no internal connection. Internal watchdog timer output signal has an internal connection to RESET pin. Internal watchdog timer output signal has an internal connection to NMI pin. Internal watchdog timer output signal has an internal connection to INT3 pin. NMI/WDTOUT configuration NMI/WDTOUT_CFG = 0: NMI/WDTOUT pin is used as the WDTOUT pin. NMI/WDTOUT_CFG = 1: NMI/WDTOUT pin is used as the NMI input pin. If NMI/WDTOUT_CFG = 1 and IWCON = 10, only the WDTOUT signal will drive the NMI signal; the external source driving the NMI/WDTOUT pin will be ignored (see Figure 3-5). PRODUCT PREVIEW RESET INT3 NMI TINT TOUTP TINP 10 Others 01 11 10 IWCON WDT_MODE NMI/WDTOUT_CFG RESET INT3 NMI/WDTOUT Figure 3-5. Watchdog Timer Hook-Up 28 SPRS208 December 2002 Functional Overview 3.5 Universal Asynchronous Receiver/Transmitter (UART) The UART peripheral is based on the industry-standard TL16C550B asynchronous communications element, which in turn, is a functional upgrade of the TL16C450. Functionally similar to the TL16C450 on power up (character or TL16C450 mode), the UART can be placed in an alternate FIFO (TL16C550) mode. This relieves the CPU of excessive software overhead by buffering received and transmitted characters. The receiver and transmitter FIFOs store up to 16 bytes, including three additional bits of error status per byte for the receiver FIFO. The UART performs serial-to-parallel conversions on data received from a peripheral device or modem and parallel-to-serial conversion on data received from the CPU. The CPU can read the UART status at any time. The UART includes control capability and a processor interrupt system that can be configured to minimize software management of the communications link. The UART includes a programmable baud rate generator capable of dividing the CPU clock by divisors from 1 to 65535 and producing a 16 x reference clock for the internal transmitter and receiver logic. The UART pins are multiplexed with the pins of the McBSP2. The Serial Port Mux determines which pins are connected to the SP0, SP1, SP2, and SP3. If GPIO7 is high at reset, the Serial Port Mux Mode bit in the External Bus Selection Register (XBSR) will be set to 1 to indicate that the UART module is enabled. In this mode, the TX and RX signals of the UART will be routed to the SP1 and SP3 pins, respectively. If GPIO7 is low at reset, the Serial Port Mux Mode bit will be set to 0 to indicate that the UART module is disabled. In this mode, any reads or writes to the UART registers will result in bus errors if the PERITOEN bit of the Time-Out Control Register is set to 1. December 2002 SPRS208 29 PRODUCT PREVIEW Functional Overview S e l e c t Data Bus Buffer 16 Line Control Register Receiver Timing and Control 8 8 Receiver FIFO 8 Peripheral Bus Receiver Buffer Register 8 Receiver Shift Register RX signal Divisor Latch (LS) Divisor Latch (MS) 16 Baud Generator PRODUCT PREVIEW Line Status Register 8 Transmitter FIFO 8 8 S e l e c t Transmitter Timing and Control Transmitter Holding Register Modem Control Register Interrupt Enable Register Interrupt Identification Register FIFO Control Register 8 8 Transmitter Shift Register TX signal 8 Control Logic Interrupt/ Event Control Logic 8 Interrupt to CPU Event to DMA controller Power and Emulation Control Register Figure 3-6. UART Functional Block Diagram 30 SPRS208 December 2002 Functional Overview 3.6 Inter-Integrated Circuit (I2C) Module The TMS320VC5502 also includes an I2C serial port for control purposes. Features of the I2C port include: * * * * * * * Compatibility with Philips I2C-Bus Specification, Version 2.1 (January 2000) Fast mode up to 400 Kbps (no fail-safe I/O buffers) Noise filters (on the SDA and SCL pins) to suppress noise of 50 ns or less (I2C module clock must be in the range of 7 MHz to 12 MHz) 7-bit and 10-bit device addressing modes Master (transmit/receive) and slave (transmit/receive) functionality Events: DMA, interrupt, or polling Slew-rate limited open-drain output buffers The I2C module clock must be in the range of 7 MHz to 12 MHz. This is necessary for the proper operation of the I2C module. NOTE: For additional information, see TMS320C55x DSP Peripherals Reference Guide (literature number SPRU317). Figure 3-7 is a block diagram of the I2C module. Clock Prescale I2CPSC SYSCLK2 From PLL Clock Generator SCL I2C Clock Noise Filter Bit Clock Generator I2CCLKH I2CCLKL Control I2COAR I2CSAR I2CMDR Own Address Slave Address Mode Data Count Transmit I2CXSR Transmit Shift Transmit Buffer Interrupt/DMA Noise Filter Receive I2CDRR Receive Buffer Receive Shift I2CIER I2CSTR I2CISRC Interrupt Enable Status Interrupt Source I2CCNT I2CDXR SDA I2C Data I2CRSR NOTE A: Shading denotes control/status registers. Figure 3-7. I2C Module Block Diagram Philips and I2C Bus are trademarks of Koninklijke Philips Electronics N.V. December 2002 SPRS208 31 PRODUCT PREVIEW I2C Module Functional Overview 3.7 Host-Port Interface (HPI) The 5502 HPI provides a 16-bit parallel interface to a host with the following features: * * * * * * 16-bit host address bus and 16-bit host data bus (non-multiplexed mode only) Multiplexed and non-multiplexed modes Host access to on-chip DARAM (excluding CPU memory-mapped registers) 16-bit address register with autoincrement capability for faster transfers Multiple address/data strobes provide a glueless interface to a variety of hosts HRDY signal for handshaking with host The 5502 HPI can access all of internal DARAM space (including memory-mapped CPU registers), but it cannot access peripheral registers or external memory. Note that all memory accesses made through the HPI are word-addressed. The 5502 HPI supports both multiplexed 8-bit and non-multiplexed 16-bit modes. One of these two modes can be selected via the GPIO6 pin. At reset, if GPIO6 is low, the HPI non-multiplexed 16-bit mode is enabled and some of the HPI signals can be used as GPIOs. If GPIO6 is high, the HPI can be used in multiplexed 8-bit mode. Similarly, some of the HPI signals can be used as GPIOs. (See Section 3.3.2, Host Port Mux, for more information on pin multiplexing for both modes of the HPI.) PRODUCT PREVIEW NOTE: No host access should occur when the HPI is placed in IDLE. The host cannot wake up the DSP through the DSP_INT bit of the HPIC1 register when the DSP is in IDLE mode. When GPIO6 is low at reset, the 5502 HPI will be configured in non-multiplexed mode. In this mode, pins A[17:2] and pins D[15:0] of the Parallel Port Mux will be set to HPI.A[15:0] and HPI.D[15:0], respectively. In non-multiplexed mode, the host can read/write 16-bit data from the 5502's internal memory by using the 16-bit address and data bus and the HPI control signals [see the TMS320C55x DSP Peripherals Reference Guide (literature number SPRU317) for more information on the 5502 HPI]. Note that in this mode, the 5502 EMIF wil be disabled. When GPIO6 is high at reset, the 5502 HPI will be configured in multiplexed mode. In this mode, pins HD[7:0], HC0, and HC1 of the Host Port Mux will be set to HPI.HD[7:0], HPI.HAS, and HPI.HBIL, respectively. In multiplexed mode, the host can only send 8 bits of data at a time through the HPI.HD[7:0] bus; therefore, some extra steps have to be taken to read/write from the 5502's internal memory [see the TMS320C55x DSP Peripherals Reference Guide (literature number SPRU317) for more information on the 5502 HPI]. Note that in this mode, the EMIF is fully enabled. The 5502 HPI has its own register set, therefore the HINT bit of CPU register ST3_55 is not used for DSP-to-host interrrupts. The HINT bit in the Host Port Control Register (HPIC) should be used for DSP-to-host interrupts. The HPI can access the entire DARAM space of the 5502; however, it does not have access to external memory of the peripheral I/O space. The HPI cannot access internal DARAM space when the device is in reset. 32 SPRS208 December 2002 Functional Overview 3.8 Direct Memory Access (DMA) Controller The 5502 DMA provides the following features: * * * * * * * Four standard ports for the following data resources: two for DARAM, one for Peripherals, and one for External Memory Six channels, which allow the DMA controller to track the context of six independent DMA channels Programmable low/high priority for each DMA channel One interrupt for each DMA channel Event synchronization. DMA transfers in each channel can be dependent on the occurrence of selected events. Programmable address modification for source and destination addresses Idle mode that allows the DMA controller to be placed in a low-power (idle) state under software control The 5502 has an Auto-wakeup/Idle function for McBSP to DMA to on-chip memory data transfers when the DMA and the McBSP are both set to IDLE. In the case that the McBSP is set to external clock mode and the McBSP and the DMA are set to idle, the McBSP and the DMA can wake up from IDLE state automatically if the McBSP gets a new data transfer. The McBSP and the DMA enter the idle state automatically after data transfer is complete. [The clock generator (PLL) should be active and the PLL core should not be in power-down mode for the Auto-wakeup/Idle function to work.] The 5502 DMA controller allows transfers to be synchronized to selected events. The 5502 supports 16 separate synchronization events and each channel can be tied to separate synchronization event independent of the other channels. Synchronization events are selected by programming the SYNC field in the channel-specific DMA Channel Control Register (DMA_CCR). The 5502 DMA can access all the internal DARAM space as well as all external memory space. The 5502 DMA also has access to the registers for the following peripheral modules: McBSP, UART, GPIO, PGPIO, and I2C. 3.8.1 DMA Channel 0 Control Register (DMA_CCR0) The DMA Channel 0 Control Register (DMA_CCR0) bit layouts are shown in Figure 3-8. DMA_CCR1 to DMA_CCR5 have similar bit layouts. See the TMS320C55x DSP Peripherals Reference Guide (literature number SPRU317) for more information on the DMA Channel n Control Register (n = 0, 1, 2, 3, 4, or 5). 15 DSTAMODE R/W, 00 14 13 SRCAMODE R/W, 00 12 11 ENDPROG R/W, 0 10 WP R/W, 0 9 REPEAT R/W, 0 8 AUTOINIT R/W, 0 7 EN R/W, 0 6 PRIO R/W, 0 5 FS R/W, 0 4 SYNC R/W, 00000 0 LEGEND: R = Read, W = Write, n = value at reset Figure 3-8. DMA Channel 0 Control Register Layout (0x0C01) The SYNC field (bits[4:0]) of the DMA_CCR register specifies the event that can initiate the DMA transfer for the corresponding DMA channel. The five bits allow several configurations as listed in Table 3-9. The bits are set to zero upon reset. For those synchronization modes with more than one peripheral listed, the Serial Port Mux Mode bit field of the External Bus Selection Register (XBSR) dictates which peripheral event is actually connected to the DMA input. December 2002 SPRS208 33 PRODUCT PREVIEW Functional Overview Table 3-9. Synchronization Control Function SYNC FIELD IN DMA_CCR 00000b 00001b 00010b 00011b 00100b 00101b 00110b 00111b 01000b 01001b No event synchronized McBSP 0 Receive Event (REVT0) McBSP 0 Transmit Event (XEVT0) Reserved (Do not use this value) Reserved (Do not use this value) McBSP1 Receive Event (REVT1) McBSP1 Transmit Event (XEVT1) Reserved (Do not use this value) Reserved (Do not use this value) Reserved/McBSP Event Serial Port Mux Mode = 0: Reserved Serial Port Mux Mode = 1: McBSP2 Receive Event (REVT2) Reserved/McBSP Event Serial Port Mux Mode = 0: Reserved Serial Port Mux Mode = 1: McBSP2 Transmit Event (XEVT2) Reserved/UART Event Serial Port Mux Mode = 0: UART Receive Event (UARTREVT) Serial Port Mux Mode = 1: Reserved Reserved/UART Event Serial Port Mux Mode = 0: UART Transmit Event (UARTXEVT) Serial Port Mux Mode = 1: Reserved Timer 0 Interrupt Event Timer 1 Interrupt Event External Interrupt 0 External Interrupt 1 External Interrupt 2 External Interrupt 3 I2C Receive Event I2C Transmit Event Reserved (Do not use these values) SYNCHRONIZATION MODE 01010b PRODUCT PREVIEW 34 01011b 01100b 01101b 01110b 01111b 10000b 10001b 10010b 10011b 10100b Other values SPRS208 December 2002 Functional Overview 3.9 System Clock Generator The TMS320VC5502 includes a flexible clock generator module consisting of a PLL and oscillator, with several dividers so that different clocks may be generated for different parts of the system (i.e., DSP core, Internal Peripheral Bus, External Memory Interface). GPIO4 at Reset = 0 -> CLKMD0 = 0 GPIO4 at Reset = 1 -> CLKMD0 = 1 GPIO4 at Reset 55x Core CLKMD CLKMD[0] PVDD CLKMD Port Power Down PLLEN (PLLCSR[0]) CKOSEL (CLKOSR[2:1]) CKODIS (CLKOSR[0]) CLKOUT OSCPWRDN Bit 1 X2/CLKIN OSC X1 PSENSE CK3SEL OD1 /1,/2.../32 D2 /1,/2,/4 D3 /1,/2,/4 SYSCLK2 (Slow Peripherals) SYSCLK3 (EMIF INT CLK) D1 /1,/2,/4 SYSCLK1 (Fast Peripherals) 1 OSCIN 0 D0 /1,/2.../32 M1 x1,x2...x16 0 PLL ECLKIN EMIFCLKS EMIF 1 0 CLKOUT3 (DSP Core Clock) ECLKOUT1 /1,/2,/4 ECLKOUT2 Figure 3-9. PLL and Clock Generator Logic 3.9.1 Input Clock Source The clock input to the 5502 can be sourced from either an externally generated 3.3-V clock input on the X2/CLKIN pin, or from the on-chip oscillator if an external crystal circuit is attached to the device as shown in Figure 3-10. At reset, if GPIO4 is low, the internal oscillator will be enabled and the internal oscillator and an external crystal will generate the input clock. If GPIO4 is high, the internal oscillator will be set to power-down mode and the input clock will be taken from the X2/CLKIN pin. The CLKMD0 bit of the Clock Mode Control Register (CLKMD) will reflect the state of GPIO4 after reset. Please note that after reset, the GPIO4 pin may become active depending on the boot mode selected through the GPIO[2:0] pins. December 2002 SPRS208 35 PRODUCT PREVIEW Functional Overview 3.9.1.1 Internal System Oscillator With External Crystal The oscillator requires an external crystal or ceramic resonator connected across the X1 and X2/CLKIN pins. If the internal oscillator is not used, an external clock source must be applied to the X2/CLKIN pin and the X1 pin should be left unconnected. Since the internal oscillator can be used as a clock source to the PLL, the crystal oscillation frequency can be multiplied to generate the input clock to the different clock groups. The crystal should be in fundamental-mode operation, and parallel resonant, with a maximum effective series resistance of 30 and a power dissipation of 1 mW. The internal oscillator supports fundamental-mode crystals up to 25 MHz. The connection of the required circuit, consisting of the crystal and two load capacitors, is shown in Figure 3-10. The load capacitors, C1 and C2, should be chosen such that the equation below is satisfied. CL in the equation is the load specified for the crystal, which must be 10 pF. CL + C 1C 2 (C 1 ) C 2) PRODUCT PREVIEW X2/CLKIN X1 RS Crystal C1 C2 Figure 3-10. Internal System Oscillator External Crystal The 5502 has internal circuitry that will count down a predetermined number of clock cycles (41,032 reference clock cycles) to allow the oscillator input to become stable after waking up from power-down state or after reset. If a reset is asserted, program flow will start after all stabilization periods have expired; this includes the oscillator stabilization period only if GPIO4 is low at reset. If the oscillator is coming out of power-down mode, program flow will start immediately after the oscillator stabilization period has completed. See Section 3.9.6, Reset Sequence, for more details on program flow after reset or after oscillator power-down. See Section 3.10, Idle Control, for more information on the oscillator power-down mode. 3.9.1.2 Clock Generation With PLL Disabled (Bypass Mode, Default) After reset, the PLL multiplier (M1) and its divider (D0) will be bypassed by default and the input clock to point C in Figure 3-11 will be taken from, depending on the state of the GPIO4 pin after reset, either the internal oscillator or the X2/CLKIN pin. The PLL can be taken out of bypassed mode as described in Section 3.9.4.1, C55x Subsystem Clock Group. 36 SPRS208 December 2002 Functional Overview 3.9.1.3 Clock Generation With PLL Enabled (PLL Mode) When not in bypass mode, the frequency of the input clock can be divided down by a programmable divider (D0) by any factor from 1 to 32. The output clock of the divider can be multiplied by any factor from 1 to 16 through a programmable multiplier (M1). The divider factor can be set through the PLLDIV0 bit of the PLL Divider 0 Register. The multiplier factor can be set through the PLLM bits of the PLL Multiplier Control Register. By default, the divider and multiplier factors are set to 1 after reset. NOTE: There is a specific minimum and maximum input clock for the block labeled PLL in Figure 3-9, as well as for the DSP subsystem, peripherals, and EMIF. In addition, there is a maximum output frequency for the PLL. The clock generator must not be configured to exceed any of these constraints (certain combinations of external clock input, internal dividers, and PLL multiply ratios might not be supported). 3.9.2 Clock Groups The TMS320VC5502 has four clock groups: the C55x Subsystem Clock Group, the Fast Peripherals Clock Group, the Slow Peripherals Clock Group, and the External Memory Interface Clock Group. Clock groups allow for lower power and performance optimization since the frequency of groups with no high-speed requirements can be set to 1/4 or 1/2 the frequency of other groups. The C55x Subsystem Clock Group includes the C55x CPU core, internal memory (DARAM and ROM), the ICACHE, and all CPU-related modules. The input clock to this clock group is taken from the CLKOUT3 signal (as shown in Figure 3-9), the source of which can be controlled through the CLKOUT3 Select Register (CK3SEL). The frequency of CLKOUT3 can be set by adjusting the divider and multiplier values of D0 and M1 through the PLLDIV0 and PLLM registers, respectively. 3.9.2.2 Fast Peripherals Clock Group The Fast Peripherals Clock Group includes the DMA, HPI, and the timers. The input clock to this clock group is taken from the output of divider 1 (D1) (as shown in Figure 3-9). By default, the divider is set to divide its input clock by four, but the divide value can be changed to divide-by-1 or divide-by-2 by modifying the PLLDIV1 bits of the PLL Divider1 Register (PLLDIV1) through software. 3.9.2.3 Slow Peripherals Clock Group The Slow Peripherals Clock Group includes the McBSPs, I2C, and the UART. The input clock to this clock group is taken from the output of divider 2 (D2). by default, the divider is set to divide its input clock by four, but the divide value can be changed to divide-by-1 or divide-by-2 by modifying the PLLDIV2 bits of the PLL Divider2 Register (PLLDIV2) through software. The clock frequency of the Slow Peripherals Clock Group must be equal to or less than that of the Fast Peripherals Clock Group. 3.9.2.4 External Memory Interface Clock Group The External Memory Interface Clock Group includes the External Memory Interface (EMIF) module and the external data bridge modules. The input clock to this clock group is taken from the output of divider 3 (D3). By default, the divider is set to divide its input clock by four, but the divide value can be changed to divide-by-1 or divide-by-2 by modifying the PLLDIV3 bits of the PLL Divider3 Register (PLLDIV3) through software. The clock frequency of the External Memory Interface Clock Group must be equal to or less than that of the Fast Peripherals Clock Group. 3.9.3 EMIF Input Clock Selection The EMIF may be clocked from an external asynchronous clock source through the ECLKIN pin if a specific EMIF frequency is needed. The source for the EMIF clock can be specified at reset through the EMIFCLKS pin. If EMIFCLKS is low at reset, then the EMIF will be clocked via the same internal clock that feeds the data bridge module and performance will be optimal. If EMIFCLKS is high at reset, then an external asynchronous clock, which can be taken up to 100 MHz (TBD), will clock the EMIF. The data throughput performance may be degraded due to synchronization issues when an external clock source is used for the EMIF. December 2002 SPRS208 37 PRODUCT PREVIEW 3.9.2.1 C55x Subsystem Clock Group Functional Overview 3.9.4 Changing the Clock Group Frequencies DSP software can be used to change the clock frequency of each clock group by setting adequate values in the PLL control registers. Figure 3-11 shows which PLL control registers affect the different portions of the clock generator. The following sections describe the procedures for changing the frequencies of each clock group. OSCIN X2/CLKIN CLKMD0 0 Point A 1 Divider D0 Point B PLL Core Multiplier M1 1 Point C 0 Divider D1 Divider D2 Divider D3 SYSCLK1 SYSCLK2 SYSCLK3 PLLEN PRODUCT PREVIEW CLKOUT3 Divider OD1 PLLCSR PLLM PLLDIV0 PLLDIV1 PLLDIV2 PLLDIV3 OSCDIV1 CK3SEL WKEN Oscillator Power-Down Control Figure 3-11. Clock Generator (PLL) Registers 38 SPRS208 December 2002 Functional Overview 3.9.4.1 C55x Subsystem Clock Group Changes to the PLL Control Register (PLLCSR), the PLL Divider0 Register (PLLDIV0), and the PLL Multiplier Register (PLLM) affect the clock of this clock group. The following procedure must be followed to change or to set the PLL to a specific value: 1. Switch to bypass mode by setting the PLLEN bit to 0. 2. Set the PLL to its reset state by setting the PLLRST bit to 1. 3. Change the PLL setting through the PLLM and PLLDIV0 bits. 4. Wait for 1 s. 5. Release the PLL from its reset state by setting PLLRST to 0. 6. Wait for the PLL to relock by polling the LOCK bit or by setting up a LOCK interrupt. 7. Switch back to PLL mode by setting the PLLEN bit to 1. The frequency of the C55x Subsystem Clock Group can be up to 300 MHz. 3.9.4.2 Fast Peripherals Clock Group Changes to the clock of the C55x Subsystem Clock Group affect the clock of the Fast Peripherals Clock Group. The PLLDIV1 value of the PLL Divider1 Register (PLLDIV1) should not be set in a manner that makes the frequency for this clock group greater than 150 MHz. There must be no activity in the modules included in the Fast Peripherals Clock Group when the value of PLLDIV1 is being changed. It is recommended that the fast peripheral modules be put in IDLE mode before changing the PLLDIV1 value. 3.9.4.3 Slow Peripherals Clock Group Changes to the clock of the C55x Subsystem Clock Group affect the clock of the Slow Peripherals Clock Group. The PLLDIV2 value of the PLL Divider2 Register (PLLDIV2) should not be set in a manner that makes the frequency for this clock group greater than 150 MHz or greater than the frequency of the Fast Peripherals Clock Group. There must be no activity in the modules included in the Slow Peripherals Clock Group when the value of PLLDIV2 is being changed. It is recommended that the slow peripheral modules be put in IDLE mode before changing the PLLDIV2 value. 3.9.4.4 External Memory Interface Clock Group Changes to the clock of the C55x Subsystem Clock Group affect the clock of the External Memory Interface Clock Group. The PLLDIV3 value of the PLL Divider3 Register (PLLDIV3) should not be set in a manner that makes the frequency for this clock group greater than 100 MHz or greater than the frequency of the Fast Peripherals Clock Group, whichever is smaller. If an external clock is used, the EMIF can operate up to 100 MHz as long as the external clock frequency does not exceed the frequency of the internal clock to the data bridge modules or the frequency of the Fast Peripherals Clock Group, whichever is smaller. There must be no external memory accesses when the value of PLLDIV3 is being changed, this means that the value of PLLDIV3 cannot be changed by a program that is being executed from external memory. It is recommended that the EMIF be put in IDLE mode before changing the PLLDIV3 value. December 2002 SPRS208 39 PRODUCT PREVIEW Functional Overview 3.9.5 PLL Control Registers The 5502 PLL control registers are accessible via the I/O memory map. Table 3-10. PLL Control Registers ADDRESS 1C80h 1C82h 1C88h 1C8Ah 1C8Ch 1C8Eh 1C90h 1C92h 1C98h REGISTER PLLCSR CK3SEL PLLM PLLDIV0 PLLDIV1 PLLDIV2 PLLDIV3 OSCDIV1 WKEN PRODUCT PREVIEW 3.9.5.1 15 PLL Control / Status Register (PLLCSR) 8 Reserved R, 00000000 7 Reserved R, 0 6 STABLE R, 1 5 LOCK R, 0 4 Reserved R, 0 3 PLLRST R/W, 1 2 OSCPWRDN R/W, 0 1 PLLPWRDN R/W, 0 0 PLLEN R/W, 0 LEGEND: R = Read, W = Write, n = value at reset Figure 3-12. PLL Control/Status Register Layout (0x1C80) 40 SPRS208 December 2002 Functional Overview Table 3-11. PLL Control/Status Register Bit Field Description BIT NAME Reserved STABLE BIT NO. 15:7 6 ACCESS R R RESET VALUE 000000000 1 DESCRIPTION Reserved. Reads return 0. Writes have no effect. Oscillator input stable. This bit indicates if the OSCIN/CLKIN input has stabilized. STABLE = 0: OSCIN/CLKIN input is not yet stable. Oscillator counter is not done counting 41,032 reference clock cycles. OSCIN/CLKIN input is stable. This is true if any one of the three cases is true: a) Oscillator counter has finished counting. b) Oscillator counter is disabled. c) Test mode. STABLE = 1: LOCK 5 R 0 Lock mode indicator. This bit indicates whether the clock generator is in its lock mode. LOCK = 0: LOCK = 1: The PLL is in the process of getting a phase lock. The clock generator is in the lock mode. The PLL has a phase lock and the output clock of the PLL has the frequency determined by the PLLM register and PLLDIV0 register. Reserved PLLRST 4 3 R R/W 0 1 Reserved. Reads return 0. Writes have no effect. Asserts RESET to PLL PLLRST = 0: PLLRST = 1: PLL reset released PLL reset asserted OSCPWRDN 2 R/W 0 Selects oscillator power down OSCPWRDN = 0: OSCPWRDN = 1: Oscillator operational Oscillator placed in power-down state PLLPWRDN 1 R/W 0 Selects PLL power down PLLPWRDN = 0: PLLPWRDN = 1: PLL operational PLL placed in power-down state PLLEN 0 R/W 0 PLL mode enable. This bit controls the multiplexer before dividers D1, D2, and D3. PLLEN = 0: Bypass mode. Divider D1 and PLL are bypassed. SYSCLK1 to 3 divided down directly from input reference clock. PLL mode. Divider D1 and PLL are not bypassed. SYSCLK1 to 3 divided down from PLL output. PLLEN = 1: December 2002 SPRS208 41 PRODUCT PREVIEW Functional Overview 3.9.5.2 15 PLL Multiplier Control Register (PLLM) 8 Reserved R, 00000000 7 Reserved R, 000 5 4 PLLM R/W, 00000 0 LEGEND: R = Read, W = Write, n = value at reset Figure 3-13. PLL Multiplier Control Register Layout (0x1C88) Table 3-12. PLL Multiplier Control Register Bit Field Description BIT NAME Reserved PLLM BIT NO. 15:5 4:0 ACCESS R R/W RESET VALUE 00000000000 00000 PLL multiplier-select PLLM = 00000-00001: PLLM = 00010: PLLM = 00011: PLLM = 00100: PLLM = 00101: PLLM = 00110: PLLM = 00111: PLLM = 01000: PLLM = 01001: PLLM = 01010: PLLM = 01011: PLLM = 01100: PLLM = 01101: PLLM = 01110: PLLM = 01111: PLLM = 10000-11111: Reserved Times 2 Times 3 Times 4 Times 5 Times 6 Times 7 Times 8 Times 9 Times 10 Times 11 Times 12 Times 13 Times 14 Times 15 Reserved DESCRIPTION Reserved. Reads return 0. Writes have no effect. PRODUCT PREVIEW 42 SPRS208 December 2002 Functional Overview 3.9.5.3 PLL Divider 0 Register (PLLDIV0) (Prescaler) This register controls the value of the PLL prescaler (Divider D0). 15 D0EN R/W, 1 7 Reserved R, 000 LEGEND: R = Read, W = Write, n = value at reset 5 4 PLLDIV0 R/W, 00000 14 Reserved R, 0000000 0 8 Figure 3-14. PLL Divider 0 Register Layout (0x1C8A) Table 3-13. PLL Divider 0 Register Bit Field Description BIT NAME D0EN BIT NO. 15 ACCESS R/W RESET VALUE 1 Divider D0 enable D0EN = 0: D0EN = 1: Reserved PLLDIV0 14:5 4:0 R R/W 0000000000 00000 Divider D0 ratio PLLDIV0 PLLDIV0 PLLDIV0 PLLDIV0 PLLDIV0 PLLDIV0 PLLDIV0 PLLDIV0 PLLDIV0 PLLDIV0 PLLDIV0 PLLDIV0 PLLDIV0 PLLDIV0 PLLDIV0 PLLDIV0 PLLDIV0 PLLDIV0 PLLDIV0 PLLDIV0 PLLDIV0 PLLDIV0 PLLDIV0 PLLDIV0 PLLDIV0 PLLDIV0 PLLDIV0 PLLDIV0 PLLDIV0 PLLDIV0 PLLDIV0 PLLDIV0 = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 00000: 00001: 00010: 00011: 00100: 00101: 00110: 00111: 01000: 01001: 01010: 01011: 01100: 01101: 01110: 01111: 10000: 10001: 10010: 10011: 10100: 10101: 10110: 10111: 11000: 11001: 11010: 11011: 11100: 11101: 11110: 11111: Divide by 1 Divide by 2 Divide by 3 Divide by 4 Divide by 5 Divide by 6 Divide by 7 Divide by 8 Divide by 9 Divide by 10 Divide by 11 Divide by 12 Divide by 13 Divide by 14 Divide by 15 Divide by 16 Divide by 17 Divide by 18 Divide by 19 Divide by 20 Divide by 21 Divide by 22 Divide by 23 Divide by 24 Divide by 25 Divide by 26 Divide by 27 Divide by 28 Divide by 29 Divide by 30 Divide by 31 Divide by 32 Divider 0 disabled Divider 0 enabled DESCRIPTION Reserved. Reads return 0. Writes have no effect. December 2002 SPRS208 43 PRODUCT PREVIEW Functional Overview 3.9.5.4 PLL Divider1 Register (PLLDIV1) for SYSCLK1 This register controls the value of the divider D1 for SYSCLK1. It is in both the BYPASS and PLL paths. 15 D1EN R/W, 1 14 Reserved R, 0000000 8 7 Reserved R, 000 5 4 PLLDIV1 R/W, 00011 0 LEGEND: R = Read, W = Write, n = value at reset Figure 3-15. PLL Divider 1 Register Layout (0x1C8C) PRODUCT PREVIEW Table 3-14. PLL Divider 1 Register Bit Field Description BIT NAME D1EN BIT NO. 15 ACCESS R/W RESET VALUE 1 Divider D1 enable D1EN = 0: D1EN = 1: Reserved PLLDIV1 14:5 4:0 R R/W 0000000000 00011 Divider 1 disabled Divider 1 enabled DESCRIPTION Reserved. Reads return 0. Writes have no effect. Divider D1 ratio (SYSCLK1 divider) PLLDIV1 = 00000: PLLDIV1 = 00001: PLLDIV1 = 00010: PLLDIV1 = 00011: PLLDIV1 = 00100-11111: Divide by 1 Divide by 2 Reserved Divide by 4 Reserved 3.9.5.5 PLL Divider2 Register (PLLDIV2) for SYSCLK2 This register controls the value of the divider D2 for SYSCLK2. It is in both the BYPASS and PLL paths. 15 D2EN R/W, 1 14 Reserved R, 0000000 8 7 Reserved R, 000 5 4 PLLDIV2 R/W, 00011 0 LEGEND: R = Read, W = Write, n = value at reset Figure 3-16. PLL Divider 2 Register Layout (0x1C8E) 44 SPRS208 December 2002 Functional Overview Table 3-15. PLL Divider 2 Register Bit Field Description BIT NAME D2EN BIT NO. 15 ACCESS R/W RESET VALUE 1 Divider D2 enable D2EN = 0: D2EN = 1: Reserved PLLDIV2 14:5 4:0 R R/W 0000000000 00011 Divider 2 disabled Divider 2 enabled DESCRIPTION Reserved. Reads return 0. Writes have no effect. Divider D2 ratio (SYSCLK2 divider) PLLDIV2 = 00000: PLLDIV2 = 00001: PLLDIV2 = 00010: PLLDIV2 = 00011: PLLDIV2 = 00100-11111: Divide by 1 Divide by 2 Reserved Divide by 4 Reserved 3.9.5.6 PLL Divider3 Register (PLLDIV3) for SYSCLK3 15 D3EN R/W, 1 14 Reserved R, 0000000 8 7 Reserved R, 000 5 4 PLLDIV3 R/W, 00011 0 LEGEND: R = Read, W = Write, n = value at reset Figure 3-17. PLL Divider 3 Register Layout (0x1C90) Table 3-16. PLL Divider3 Register Bit Field Description BIT NAME D3EN BIT NO. 15 ACCESS R/W RESET VALUE 1 Divider D3 enable D3EN = 0: D3EN = 1: Reserved PLLDIV3 14:5 4:0 R R/W 0000000000 00011 Divider 3 disabled Divider 3 enabled DESCRIPTION Reserved. Reads return 0. Writes have no effect. Divider D3 ratio (SYSCLK3 divider) PLLDIV3 = 00000: PLLDIV3 = 00001: PLLDIV3 = 00010: PLLDIV3 = 00011: PLLDIV3 = 00100-11111: Divide by 1 Divide by 2 Reserved Divide by 4 Reserved December 2002 SPRS208 45 PRODUCT PREVIEW This register controls the value of the divider D3 for SYSCLK3. It is in both the BYPASS and PLL paths. Functional Overview 3.9.5.7 Oscillator Divider1 Register (OSCDIV1) for CLKOUT3 This register controls the value of the divider OD1 for CLKOUT3. It does not go through the PLL path. 15 OD1EN R/W, 0 7 Reserved R, 000 LEGEND: R = Read, W = Write, n = value at reset 5 4 OSCDIV1 R/W, 00000 14 Reserved R, 0000000 0 8 Figure 3-18. Oscillator Divider1 Register Layout (0x1C92) Table 3-17. Oscillator Divider1 Register Bit Field Description PRODUCT PREVIEW BIT NAME OD1EN BIT NO. 15 ACCESS R/W RESET VALUE 0 DESCRIPTION Oscillator divider OD1 enable OD1EN = 0: OD1EN = 1: Oscillator divider 1 disabled Oscillator divider 1 enabled Reserved OSCDIV1 14:5 4:0 R R/W 0000000000 00000 Reserved. Reads return 0. Writes have no effect. Divider OD1 ratio (CLKOUT3 divider) OSCDIV1 = 00000: OSCDIV1 = 00001: OSCDIV1 = 00010: OSCDIV1 = 00011: OSCDIV1 = 00100: OSCDIV1 = 00101: OSCDIV1 = 00110: OSCDIV1 = 00111: OSCDIV1 = 01000: OSCDIV1 = 01001: OSCDIV1 = 01010: OSCDIV1 = 01011: OSCDIV1 = 01100: OSCDIV1 = 01101: OSCDIV1 = 01110: OSCDIV1 = 01111: OSCDIV1 = 10000: OSCDIV1 = 10001: OSCDIV1 = 10010: OSCDIV1 = 10011: OSCDIV1 = 10100: OSCDIV1 = 10101: OSCDIV1 = 10110: OSCDIV1 = 10111: OSCDIV1 = 11000: OSCDIV1 = 11001: OSCDIV1 = 11010: OSCDIV1 = 11011: OSCDIV1 = 11100: OSCDIV1 = 11101: OSCDIV1 = 11110: OSCDIV1 = 11111: Divide by 1 Divide by 2 Divide by 3 Divide by 4 Divide by 5 Divide by 6 Divide by 7 Divide by 8 Divide by 9 Divide by 10 Divide by 11 Divide by 12 Divide by 13 Divide by 14 Divide by 15 Divide by 16 Divide by 17 Divide by 18 Divide by 19 Divide by 20 Divide by 21 Divide by 22 Divide by 23 Divide by 24 Divide by 25 Divide by 26 Divide by 27 Divide by 28 Divide by 29 Divide by 30 Divide by 31 Divide by 32 46 SPRS208 December 2002 Functional Overview 3.9.5.8 Oscillator Wakeup Control Register (WKEN) This register controls whether different events in the system are enabled to wake up the device after entering OSCPWRDN. 15 Reserved R, 00000000 7 Reserved R, 000 LEGEND: R = Read, W = Write, n = value at reset 5 4 WKEN4 R/W, 1 3 WKEN3 R/W, 1 2 WKEN2 R/W, 1 1 WKEN1 R/W, 1 0 WKEN0 R/W, 1 8 Figure 3-19. Oscillator Wakeup Control Register Layout (0x1C98) Table 3-18. Oscillator Wakeup Control Register Bit Field Description BIT NAME Reserved WKEN4 BIT NO. 15:5 4 ACCESS R R/W RESET VALUE 00000000000 1 DESCRIPTION Reserved. Reads return 0. Writes have no effect. Input INT3 can wake up the oscillator when the OSCPWRDN bit in PLLCSR is asserted to logic 1. WKEN4 = 0: Wake-up enabled. A low-to-high transition on INT3 wakes up the oscillator and clears the OSCPWRDN bit. WKEN4 = 1: Wake-up disabled. A low-to-high transition on INT3 does not wake up the oscillator. WKEN3 3 R/W 1 Input INT2 can wake up the oscillator when the OSCPWRDN bit in PLLCSR is asserted to logic 1. WKEN3 = 0: Wake-up enabled. A low-to-high transition on INT2 wakes up the oscillator and clears the OSCPWRDN bit. WKEN3 = 1: Wake-up disabled. A low-to-high transition on INT2 does not wake up the oscillator. WKEN2 2 R/W 1 Input INT1 can wake up the oscillator when the OSCPWRDN bit in PLLCSR is asserted to logic 1. WKEN2 = 0: Wake-up enabled. A low-to-high transition on INT1 wakes up the oscillator and clears the OSCPWRDN bit. WKEN2 = 1: Wake-up disabled. A low-to-high transition on INT1 does not wake up the oscillator. WKEN1 1 R/W 1 Input INT0 can wake up the oscillator when the OSCPWRDN bit in PLLCSR is asserted to logic 1. WKEN1 = 0: Wake-up enabled. A low-to-high transition on INT0 wakes up the oscillator and clears the OSCPWRDN bit. WKEN1 = 1: Wake-up disabled. A low-to-high transition on INT0 does not wake up the oscillator. WKEN0 0 R/W 1 Input NMI can wake up the oscillator when the OSCPWRDN bit in PLLCSR is asserted to logic 1. WKEN0 = 0: Wake-up enabled. A low-to-high transition on NMI wakes up the oscillator and clears the OSCPWRDN bit. WKEN0 = 1: Wake-up disabled. A low-to-high transition on NMI does not wake up the oscillator. December 2002 SPRS208 47 PRODUCT PREVIEW Functional Overview 3.9.5.9 CLKOUT3 Select Register (CK3SEL) This register controls which clock is output onto the CLKOUT3 so that it may be used to test and debug the PLL (in addition to its normal function of being a direct input clock divider). Modes other than CK3SEL = 1011 are intended for debug use only and should not be used during normal operation. 15 Reserved R, 00000000 7 Reserved R, 0000 LEGEND: R = Read, W = Write, n = value at reset 4 3 CK3SEL R/W, 1011 0 8 PRODUCT PREVIEW Figure 3-20. CLKOUT3 Select Register Layout (0x1C82) Table 3-19. CLKOUT3 Select Register Bit Field Description BIT NAME Reserved CK3SEL BIT NO. 15:4 3:0 ACCESS R R/W RESET VALUE 000000000000 1011 Output on CLK3SEL pin CK3SEL = 1001 CK3SEL = 1010 CK3SEL = 0000-0111 CK3SEL = 1011 CK3SEL = Other CLKOUT3 becomes point A in Figure 3-11 CLKOUT3 becomes point B in Figure 3-11 CLKOUT3 becomes oscillator divider output in Figure 3-11 CLKOUT3 becomes point C in Figure 3-11 Not supported DESCRIPTION Reserved. Reads return 0. Writes have no effect. 3.9.5.10 CLKOUT Selection Register (CLKOUTSR) As described in Section 3.9.2, Clock Groups, the 5502 has different clock groups, each of which can be driven by a clock that is different from the CPU clock. The CLKOUT Selection Register determines which clock signal is reflected on the CLKOUT pin. 15 Reserved R, 00000000 7 Reserved R, 00000 LEGEND: R = Read, W = Write, n = value at reset 3 2 CLKOSEL R/W, 01 1 0 CLKOUTDIS R/W, 0 8 Figure 3-21. CLKOUT Selection Register Layout (0x8400) 48 SPRS208 December 2002 Functional Overview Table 3-20. CLKOUT Selection Register Bit Field Description BIT NAME Reserved CLKOSEL BIT NO. 15-3 2:1 ACCESS R R/W RESET VALUE 0000000000000 01 Reserved CLKOUT source-select CLKOSEL = 00: CLKOSEL = 01: CLKOSEL = 10: CLKOSEL = 11: CLKOUTDIS 0 R/W 0 Disable CLKOUT CLKOUTDIS = 0: CLKOUTDIS = 1: CLKOUT enabled CLKOUT disabled (driving 0) Reserved CLKOUT source is SYSCLK1 CLKOUT source is SYSCLK2 CLKOUT source is SYSCLK3 DESCRIPTION 3.9.5.11 Clock Mode Control Register (CLKMD) 15 Reserved R, 00000000 8 7 Reserved R, 0000000 LEGEND: R = Read, W = Write, n = value at reset 1 0 CLKMD0 R/W, GPIO4 state at reset Figure 3-22. Clock Mode Control Register Layout (0x8C00) Table 3-21. Clock Mode Control Register Bit Field Description BIT NAME Reserved CLKMD0 BIT NO. 15-1 0 ACCESS R R/W RESET VALUE 000000000000000 GPIO4 state at reset Reserved Clock output source-select CLKMD0 = 0: CLKMD0 = 1: OSCIN is selected as clock input source X2/CLKIN is selected as clock input source DESCRIPTION 3.9.6 Reset Sequence When reset is low, the clock generator is in bypass mode with the input clock set to OSCIN or X2/CLKIN, dependent upon the state of the GPIO4. After reset, the following conditions occur: * * GPIO6 and GPIO7 are sampled on the rising edge of the reset signal. If GPIO6 is set high, the External Bus Selection Register is configured with the Parallel Bus in EMIF mode. If GPIO6 is set low, the External Bus Selection Register is configured with the Parallel Bus in non-multiplexed mode. If GPIO7 is set high, the Serial Port Mux is configured in McBSP mode. If GPIO7 is set low, the Serial Port Mux is configured in UART mode. * December 2002 SPRS208 49 PRODUCT PREVIEW Functional Overview The 5502 has internal circuitry that will count down 70 reference clock cycles to allow reset signals to propagate correctly to all parts of the device after reset (RESET pin goes high). Furthermore, the 5502 also has internal circuitry that will count down 41,032 reference clock cycles to allow the oscillator input to become stable after waking up from power-down state or reset. If a reset is asserted, program flow will start after all stabilization periods have expired; this includes the oscillator stabilization period only if GPIO4 is low at reset. If the oscillator is coming out of power-down mode, program flow will start immediately after the oscillator stabilization period has completed. Table 3-22 summarizes the number of reference clock cycles needed before program flow begins. Table 3-22. Number of Reference Clock Cycles Needed Until Program Flow Begins CONDITION Oscillator Not Used After Reset After Oscillator Power-Down Oscillator Used REFERENCE CLOCK CYCLES 70 41,102 41,032 PRODUCT PREVIEW All output (O/Z) and input/output (I/O/Z) pins (except for CLKOUT, ECLKOUT2, and XF) will go into high-impedance mode during reset and will come out of high-impedance mode when the stabilization periods have expired. All output (O/Z) and input/output (I/O/Z) pins will retain their value when the device enters a power-down mode such as IDLE3 mode. At power up, the reset pin must be kept at a low state until the 5502 has been completely powered up to prevent any unexpected behavior. 3.10 Idle Control The Idle function is implemented for low power consumption. The Idle function achieves low power consumption by gating the clock to unused parts of the chip, and/or setting the clock generator (PLL) and the internal oscillator to a power-down mode. 3.10.1 Clock Domains The 5502 provides six clock domains to power-off the main clock to the portions of the device that are not being used. The six domains are: * * * * * * CPU Domain Master Port Domain (includes DMA and HPI modules) ICACHE Peripherals Domain Clock Generator Domain EMIF Domain 3.10.2 IDLE Procedures Before entering idle mode (executing the IDLE instruction), the user has first to determine which part of the system needs to be disabled and then program the Idle Control Register (ICR) accordingly. When the IDLE instruction is executed, the ICR will be copied into the Idle Status Register (ISTR). The different bits of the ISTR register will be propagated to disable the chosen domains. Special care has to be taken in programming the ICR as some IDLE domain combinations are not valid (for example: CPU on and clock generator off). 50 SPRS208 December 2002 Functional Overview 3.10.2.1 CPU Domain Idle Procedure The 5502 CPU can be idled by executing the following procedure. 1. Write `1' to the CPUI bit (bit 0 of ICR). 2. Execute the IDLE instruction. 3. CPU will go to idle state 3.10.2.2 Master Port Domain (DMA/HPI) Idle Procedure The clock to the DMA module and/or the HPI module will be stopped when the DMA and/or the HPI bit in the MICR is set to 1 and the MPIS bit in the ISTR becomes 1. The DMA will go into idle immediately if there is no data transfer taking place. If there is a data transfer taking place, then it will finish the current transfer and then go into idle. The HPI will go into idle regardless of whether or not there is a data transfer taking place. Software must confirm that the HPI has no activity before setting it to idle. The 5502 DMA module and the HPI module can be disabled by executing the following procedure. 1. Write `1' to the DMA bit and/or the HPI bit in MICR. 3. Execute the IDLE instruction. 4. DMA and/or HPI go/goes to idle. 3.10.2.3 Peripheral Modules Idle Procedure The clock to the modules included in the Peripherals Domain will be stopped when their corresponding bit in the PICR is set to 1 and the PERIS bit in the ISTR becomes 1. Each module in this domain will go into idle immediately if it has no activity. If the module being set to idle has activity, it will wait until the activity completes before going into idle. Each peripheral module can be idled by executing the following procedure. 1. Write `1' to the corresponding bit in PICR for each peripheral to be idled. 2. Write `1' to the PERI bit in ICR. 3. Execute the IDLE instruction. 4. Every peripheral with its corresponding PICR bit set will go to idle. 3.10.2.4 EMIF Module Idle Procedure The 5502 EMIF can be idled in one of two ways: through the ICR and through the PICR. The EMIF will go into idle immediately if there is no data transfer taking place within the DMA. If there is a data transfer taking place, then the EMIF will wait until the DMA finishes the current transfer and goes into idle before going into idle itself. Please note that while the EMIF is in idle, the SDRAM refresh function of the EMIF will not be available. The 5502 EMIF can be idled through the ICR only when the following modules are set to idle: CPU, I-Port, ICACHE, DMA, and HPI. To place the EMIF in idle using the ICR, execute the following procedure: 1. Write `1' to the DMA and HPI bits in MICR. 2. Write `1' to the CPUI, MPI, ICACHEI, EMIFI, and IPORTI bits in ICR. 3. Execute the IDLE instruction. 4. EMIF and all modules listed in Step 2 will go to idle. December 2002 SPRS208 51 PRODUCT PREVIEW 2. Write `1' to the MPI bit in ICR. Functional Overview The 5502 EMIF can also be idled through the PICR. To place the EMIF in idle using the PICR, execute the following procedure: 1. Write a `1' to the EMIF bit in PICR. 2. Write a `1' to the PERI bit in ICR. 3. Execute IDLE instruction. 4. EMIF will go to IDLE. 3.10.2.5 IDLE2 Mode In IDLE2 mode, all modules except the CLOCK module are set to idle state. To place the 5502 in IDLE2 mode, perform the following steps. 1. Write a `1' to all peripheral module bits in the PICR. 2. Write a `1' to the HPI and DMA bits in MICR. 3. Write a `1' to all domain bits in the ICR except the CLOCK domain bit (CLKI). PRODUCT PREVIEW 4. Execute the IDLE instruction. 5. All internal clocks will be disabled, the CLOCK module will remain active. 3.10.2.6 IDLE3 Mode In IDLE3 mode, all modules (including the CLOCK module) are set to idle state. To place the 5502 in IDLE3 mode, perform the following steps. 1. Clear (i.e., set to `0') the PLLEN bit in PLLCSR to place the PLL in bypass mode. 2. Set the PLLPWRDN and PLLRST bits in PLLCSR to `1'. 3. Write a `1' to all peripheral module bits in PICR. 4. Write a `1' to the HPI and DMA bits in MICR. 5. Write a `1' to all domain bits in ICR. 6. Execute the IDLE instruction. 7. PLL core is set to power-down mode and all internal clocks are disabled. 3.10.2.7 IDLE3 Mode With Internal Oscillator Disabled In this state, all modules (including the CLOCK module) are set to the idle state and the internal oscillator is set to the power-down mode. This is the lowest power-consuming state that 5502 can be placed under. 1. Clear (i.e., set to `0') the PLLEN bit in PLLCSR to place the PLL in bypass mode. 2. Set the PLLPWRDN, PLLRST, and OSCPWRDN bits in PLLCSR to `1'. 3. Set the WKEN register to specify which event will wake up internal oscillator [e.g., set bit 1 to have interrupt 0 (INT0) wake up the oscillator]. 4. Write a `1' to all peripheral module bits in the PICR. 5. Write a `1' to the HPI and DMA bits in MICR. 6. Write a `1' to all domain bits in the ICR. External interrupt being used must be enabled through IER prior to setting the 5502 to IDLE. 52 SPRS208 December 2002 Functional Overview 7. Execute the IDLE instruction. 8. Internal oscillator is set to power-down mode, PLL core is set to power-down mode, and all internal clocks are disabled. 3.10.3 Module Behavior at Entering IDLE State All transactions must be completed before entering the IDLE state. Table 3-23 lists the behavior of each module before entering the IDLE state. Table 3-23. Peripheral Behavior at Entering IDLE State 5502 IDLE DOMAIN MODULES CPU Interrupt Controller IDLE Controller PLL Controller CPU Bus Selection Register Timer Signal Selection Register CLKOUT Selection Register External Bus Control Register Clock Mode Control Register MODULE BEHAVIOR AT ENTERING IDLE STATE (ASSUMING THE IDLE CONTROL IS SET) Enter IDLE after CPU stops pipeline. Enter IDLE after CPU stops. Enter IDLE after CPU stops. Enter IDLE after CPU stops. Enter IDLE after CPU stops. Enter IDLE after CPU stops. Enter IDLE after CPU stops. Enter IDLE after CPU stops. Enter IDLE state after current DMA transfer to internal memory, EMIF, or peripheral, or enter IDLE state immediately if no transfer exists. Master Port DMA DMA has function of Auto-wakeup/Idle with McBSP data transfer during IDLE. HPI ICACHE ICACHE Timer0/1 and WDT DSP/BIOS Timer MCBSP0/1/2 GPIO Peripheral DIEID I2C UART Parallel GPIO PLL divider CLKGEN (PLL) PLL core Oscillator EMIF EMIF Enter IDLE state immediately. Software has to take care of HPI activity. Enter IDLE state after current data transfer from EMIF or program fetch from CPU finishes, or enter IDLE state immediately if no transfer and no access exist. Enter IDLE state immediately Enter IDLE state immediately Enter IDLE state after current McBSP activity is finished or enter IDLE state immediately if no activity exists. McBSP has function of Auto-wakeup/Idle with DMA data transfer during IDLE. Enter IDLE state immediately. Enter IDLE state immediately. Enter IDLE state after current I2C activity is finished or enter IDLE state immediately if no activity exists. Enter IDLE state after current UART activity is finished or enter IDLE state immediately if no activity exists. Enter IDLE state immediately. Enter IDLE state immediately. Power-down state if set by software before IDLE Power-down state if set by software before IDLE Enter IDLE mode after current DMA transfer or enter IDLE mode immediately if no activity exists. Enter IDLE after CPU stops. December 2002 SPRS208 53 PRODUCT PREVIEW Functional Overview 3.10.4 Wake-Up Procedure It is the user's responsibility to ensure that there exists a valid wake-up procedure before entering idle mode. Keep in mind that a hardware reset will restore all modules to their active state. All wake-up procedures are described in the next sections. 3.10.4.1 CPU Domain Wake-up Procedure The CPU domain can be taken out of idle though an enabled external interrupt or an NMI signal. External interrupts can be enabled through the use of the IER0 and IER1 registers. Other modules, such as the EMIF module, will be taken out of idle automatically when the CPU wakes up. Please see the wake-up procedures for other modules for more information. 3.10.4.2 Master Port Domain (DMA/HPI) Wake-up Procedure The 5502 DMA module and the HPI module can be taken out of idle simultaneously by executing the following procedure. 1. Write `0' to the MPI bit in ICR. 2. Execute the IDLE instruction. PRODUCT PREVIEW 3. DMA and HPI wake up. It is also possible to wake up the DMA and HPI modules individually through the use of the Master Idle Control Register. To wake up only the DMA or the HPI module, perform the following steps: 1. Write `0' to the DMA bit or the HPI bit in MICR. 2. Selected module wakes up. 3.10.4.3 Peripheral Modules Wake-up Procedure All 5502 peripherals can be taken out of idle simultaneously by executing the following procedure. 1. Write `0' to the PERI bit in ICR. 2. Execute the IDLE instruction. 3. All idled peripherals wake up. It is also possible to wake up individual peripherals through the use of the Peripheral Idle Control Register by executing the following procedure. 1. Write `0' to the idle control bit of peripheral(s) in PICR. 2. Idled peripherals with `0' in PICR wake up. 54 SPRS208 December 2002 Functional Overview 3.10.4.4 EMIF Module Wake-up Procedure If both the CPU and the EMIF are in idle, then the EMIF will come out of idle when the CPU is taken out of idle. The CPU can be taken out of idle through the use of an NMI or an enabled external interrupt. External interrupts can be enabled through the IER0 and IER1 registers. If the CPU is not in idle, then the EMIF can be taken out of idle through either of the following two procedures: 1. Write `0' to the PERI bit in ICR. 2. Execute the IDLE instruction. 3. All idled peripherals, including the EMIF, wake up. Or: 1. Write `0' to the EMIF bit in PICR. 2. The EMIF module will wake up. 3.10.4.5 IDLE2 Mode Wake-up Procedure 1. CPU wakes up from idle through NMI or enabled external interrupt. 2. Write `0' to all bits in the ICR. 3. Execute the IDLE instruction. 4. All internal clocks are enabled and all modules come out of idle. 3.10.4.6 IDLE3 Mode Wake-up Procedure The 5502 can be taken completely out of IDLE3 mode by executing the following procedure. 1. CPU wakes up from idle through NMI or enabled external interrupt. 2. Write `0' to all bits in the ICR. 3. Execute the IDLE instruction. 4. All internal clocks are enabled and all modules come out of idle. 5. Write `0' to the PLLPWRDN and PLLRST bits in PLLCSR. 6. Wait for the PLL to relock by polling the LOCK bit or by setting up a LOCK interrupt. 7. Set the PLLEN bit in PLLCSR to `1'. 8. All internal clocks will now come from the PLL core. NOTE: Step 3 can be modified to only wake up certain modules, see previous sections for more information on the wake-up procedures for the 5502 modules. December 2002 SPRS208 55 PRODUCT PREVIEW The 5502 can be taken completely out of IDLE2 mode by executing the following procedure. Functional Overview 3.10.4.7 IDLE3 Mode With Internal Oscillator Disabled Wake-up Procedure The internal oscillator of the 5502 will be woken up along with the CLOCK module through an NMI or an enabled external interrupt. The source (INT0, INT1, INT2, INT3, or NMI) for the wake-up signal can be selected through the use of the WKEN register. The maskable external interrupts must be enabled through IER0 and IER1 prior to setting the 5502 to Idle 3 mode. The 5502 has internal circuitry that will count down a predetermined number of clock cycles (41,032 reference clock cycles) to allow the oscillator input to become stable after waking up from power-down state or reset. When waking up from idle mode, program flow will start after the stabilization period of the oscillator has expired. To take the 5502 (including the internal oscillator) out of the idle 3 state, execute the following procedure: 1. External interrupt or NMI occurs (as specified in the WKEN register) and program flow begins after 41,032 reference clock cycles. 2. CPU wakes up. PRODUCT PREVIEW 3. Write `0' to all bits in the ICR. 4. Execute the IDLE instruction. 5. All internal clocks are enabled and all modules come out of idle. 6. Write `0' to the PLLPWRDN, PLLRST, and OSCPWRDN bits in PLLCSR. 7. Wait for the PLL to relock by polling the LOCK bit or by setting up a LOCK interrupt. 8. Set the PLLEN bit in PLLCSR to `1'. 9. All internal clocks will now come from the PLL core. NOTE: Step 2 can be modified to only wake up certain modules, see previous sections for more information on the wake-up procedures for the 5502 modules. 3.10.4.8 Summary of Wake-up Procedures Table 3-24 summarizes the wake-up procedures. Table 3-24. Wake-Up Procedures ISTR VALUE xxx0xxx0 CLOCK DOMAIN STATUS CPU - ON Clock Generator - ON Other - ON/OFF CPU - OFF Clock Generator - ON Other - ON/OFF CPU - OFF Clock Generator - OFF Other - OFF EXIT FROM IDLE 1. DSP software modifies ICR and executes "IDLE" instruction 2. Reset 1. Unmasked interrupt from external or on-chip module 2. Reset xxx11111 1. Unmasked interrupt from external 2. Reset ICR AFTER WAKE-UP 1. Modified value ISTR AFTER WAKE-UP 1. Updated to ICR modified value after "IDLE" instruction 2. All "0" 1. CPUIS, CLKIS, and EMIFIS/XPORTIS/IPORTIS are set to "0" 2. All "0" 1. CPUIS, CLKIS, and EMIFIS/XPORTIS/IPORTIS are set to "0" 2. All "0" 2. All "0" 1. Not modified xxx0xxx1 2. All "0" 1. Not modified 2. All "0" 56 SPRS208 December 2002 Functional Overview 3.10.5 Auto-Wakeup/Idle Function for McBSP and DMA The 5502 has an Auto-wakeup/Idle function for McBSP to DMA to on-chip memory data transfers when the DMA and the McBSP are both set to IDLE. In the case that the McBSP is set to external clock mode and the McBSP and the DMA are set to idle, the McBSP and the DMA can wake up from IDLE state automatically if the McBSP gets a new data transfer. The McBSP and the DMA enter the idle state automatically after data transfer is complete. [The clock generator (PLL) should be active and the PLL core should not be in power-down mode for the Auto-wakeup/Idle function to work.] 3.10.6 Clock State of Multiplexed Modules The clock to the McBSP2, UART, and EMIF modules is disabled automatically when these modules are not selected through the External Bus Selection Register (XBSR). Note that any accesses to disabled modules will result in a bus error. 3.10.7 IDLE Control and Status Registers Table 3-25. Clock Domain Memory-Mapped Registers ADDRESS 0x0001 0x0002 0x9400 0x9401 0x9402 0x9403 REGISTER NAME IDLE Configuration Register (ICR) IDLE Status Register (ISTR) Peripheral IDLE Control Register (PICR) Peripheral IDLE Status Register (PISTR) Master IDLE Control Register (MICR) Master IDLE Status Register (MISR) 3.10.7.1 IDLE Configuration Register (ICR) 15 Reserved R, 0000000 9 8 IPORTI R/W, 0 7 MPORTI R/W, 0 6 XPORTI R/W, 0 5 EMIFI R/W, 0 4 CLKI R/W, 0 3 PERI R/W, 0 2 ICACHEI R/W, 0 1 MPI R/W, 0 0 CPUI R/W, 0 LEGEND: R = Read, W = Write, n = value at reset Figure 3-23. IDLE Configuration Register Layout (0x0001) December 2002 SPRS208 57 PRODUCT PREVIEW The clock domains are controlled by the IDLE Configuration Register (ICR) that allows the user to place different parts of the device in Idle mode. The IDLE Status Register (ISTR) reflects the portion of the device that remains active. The peripheral domain is controlled by the Peripheral IDLE Control Register (PICR). The Peripheral IDLE Status Register (PISTR) reflects the portion of the peripherals that are in the IDLE state. The PLL Control/Status Register (PLLCSR) is used to power down the PLL core when the IDLE instruction is executed. Functional Overview Table 3-26. IDLE Configuration Register Bit Field Description BIT NAME Reserved IPORTI BIT NO. 15-9 8 ACCESS R R/W RESET VALUE 0000000 0 Reserved IPORT idle control bit. The IPORT is used for all ICACHE transactions. IPORTI = 0: IPORTI = 1: MPORTI 7 R/W 0 IPORT remains active after execution of an IDLE instruction IPORT is disabled after execution of an IDLE instruction DESCRIPTION MPORT idle control bit. The MPORT is used for all DMA transactions. MPORTI = 0: MPORTI = 1: MPORT remains active after execution of an IDLE instruction MPORT is disabled after execution of an IDLE instruction XPORTI 6 R/W 0 XPORT idle control bit. The XPORT is used for all I/O memory transactions. XPORTI = 0: XPORTI = 1: XPORT remains active after execution of an IDLE instruction XPORT is disabled after execution of an IDLE instruction EMIFI 5 R/W 0 External Memory Interface (EMIF) idle control bit EMIFI = 0: EMIFI = 1: EMIF module remains active after execution of an IDLE instruction EMIF module is disabled after execution of an IDLE instruction PRODUCT PREVIEW CLKI 4 R/W 0 Device clock generator idle control bit CLKI = 0: CLKI = 1: Device clock generator module remains active after execution of an IDLE instruction. Device clock generator is disabled after execution of an IDLE instruction. Disabling the clock generator provides the lowest level of power reduction by stopping the system clock. When CLKI is set to 1, the CPUI and DPI bits will be set to 1 in order to ensure a proper power-down mode. PERI 3 R/W 0 Peripheral Idle control bit PERI = 0: PERI = 1: All peripheral modules become/remain active after execution of an IDLE instruction All peripheral modules with 1 in PICR are disabled after execution of an IDLE instruction ICACHEI 2 R/W 0 ICACHE idle control bit ICACHEI = 0: ICACHEI = 1: ICACHE module remains active after execution of an IDLE instruction ICACHE module is disabled after execution of an IDLE instruction MPI 1 R/W 0 Master peripheral (DMA and HPI) idle control bit MPI = 0: MPI = 1: DMA and HPI modules remain active after execution of an IDLE instruction DMA and HPI modules are disabled after execution of an IDLE instruction CPUI 0 R/W 0 CPU idle control bit CPUI = 0: CPUI = 1: CPU module remains active after execution of an IDLE instruction CPU module is disabled after execution of an IDLE instruction NOTE: For example, writing xxx000001b into the ICR does not indicate that the CPU domain is in IDLE mode; rather, it indicates that after the IDLE instruction, the CPU domain will be in IDLE mode. 58 SPRS208 December 2002 Functional Overview 3.10.7.2 IDLE Status Register (ISTR) 15 Reserved R, 0000000 9 8 IPORTIS R, 0 7 MPORTIS R, 0 6 XPORTIS R, 0 5 EMIFIS R, 0 4 CLKIS R, 0 3 PERIS R, 0 2 ICACHEIS R, 0 1 MPIS R, 0 0 CPUIS R, 0 LEGEND: R = Read, W = Write, n = value at reset Figure 3-24. IDLE Status Register Layout (0x0002) Table 3-27. IDLE Status Register Bit Field Description BIT NAME Reserved IPORTIS BIT NO. 15-9 8 ACCESS R R RESET VALUE 0000000 0 Reserved IPORT idle status bit. The IPORT is used for all ICACHE transactions. IPORTIS = 0: IPORTIS = 1: MPORTIS 7 R 0 IPORT is active IPORT is disabled DESCRIPTION MPORT idle status bit. The MPORT is used for all DMA transactions. MPORTIS = 0: MPORTIS = 1: MPORT is active MPORT is disabled XPORTIS 6 R 0 XPORT idle status bit. The XPORT is used for all I/O memory transactions. XPORTIS = 0: XPORTIS = 1: XPORT is active XPORT is disabled EMIFIS 5 R 0 External Memory Interface (EMIF) idle status bit EMIFIS = 0: EMIFIS = 1: EMIF module is active EMIF module is disabled CLKIS 4 R 0 Device clock generator idle status bit CLKIS = 0: CLKIS = 1: Device clock generator module is active Device clock generator is disabled PERIS 3 R 0 Peripheral idle status bit PERIS = 0: PERIS = 1: All peripheral modules are active All peripheral modules are disabled ICACHEIS 2 R 0 ICACHE idle status bit ICACHEIS = 0: ICACHE module is active ICACHEIS = 1: ICACHE module is disabled MPIS 1 R 0 DMA and HPI idle status bit MPIS = 0: MPIS = 1: DMA and HPI modules are active DMA and HPI modules are disabled CPUIS 0 R 0 CPU idle status bit CPUIS = 0: CPUIS = 1: CPU module is active CPU module is disabled December 2002 SPRS208 59 PRODUCT PREVIEW Functional Overview 3.10.7.3 Peripheral IDLE Control Register (PICR) 15 Reserved R, 00 14 13 MISC R/W, 0 12 EMIF R/W, 0 11 BIOST R/W, 0 10 WDT R/W, 0 9 PIO R/W, 0 8 URT R/W, 0 7 I2C R/W, 0 6 ID R/W, 0 5 IO R/W, 0 4 SP2 R/W, 0 3 SP1 R/W, 0 2 SP0 R/W, 0 1 TIM1 R/W, 0 0 TIM0 R/W, 0 LEGEND: R = Read, W = Write, n = value at reset Figure 3-25. Peripheral IDLE Control Register Layout (0x9400) PRODUCT PREVIEW Table 3-28. Peripheral IDLE Control Register Bit Field Description BIT NAME Reserved MISC BIT NO. 15-14 13 ACCESS R R/W RESET VALUE 00 0 Reserved MISC bit MISC = 0: MISC = 1: Miscellaneous modules remain active when ISTR.PERIS = 1 and IDLE instruction is executed. MIscellaneous module is disabled when ISTR.PERIS = 1 and IDLE instruction is executed. DESCRIPTION Miscellaneous modules include the XBSR, TIMEOUT Error Register, XBCR, Timer Signal Selection Register, CLKOUT Select Register, and Clock Mode Control Register. EMIF 12 R/W 0 EMIF bit EMIF = 0: EMIF = 1: BIOST 11 R/W 0 EMIF module remains active when ISTR.PERIS = 1 and IDLE instruction is executed. EMIF module is disabled when ISTR.PERIS = 1 and IDLE instruction is executed. BIOS timer bit BIOST = 0: BIOST = 1: DSP/BIOS timer remains active when ISTR.PERIS = 1 and the IDLE instruction is executed. DSP/BIOS timer is disabled when ISTR.PERIS = 1 and the IDLE instruction is executed. WDT 10 R/W 0 Watchdog timer bit WDT = 0: WDT = 1: WDT remains active when ISTR.PERIS = 1 and the IDLE instruction is executed. WDT is disabled when ISTR.PERIS = 1 and the IDLE instruction is executed. PIO 9 R/W 0 Parallel GPIO timer bit PIO = 0: PIO = 1: Parallel GPIO remains active when ISTR.PERIS = 1 (ISTR.[3]) and the IDLE instruction is executed. Parallel GPIO is disabled when ISTR.PERIS = 1 and the IDLE instruction is executed. If the peripheral is already in IDLE, setting PERIS (bit 3 of ISTR) to 0 and executing the IDLE instruction will wake up all peripherals, and PICR bit settings will be ignored. If PERIS = 1, executing the IDLE instruction will wake up the peripheral if the PICR bit is 0. 60 SPRS208 December 2002 Functional Overview Table 3-28. Peripheral IDLE Control Register Bit Field Description (Continued) BIT NAME URT BIT NO. 8 ACCESS R/W RESET VALUE 0 UART timer bit URT = 0: URT = 1: I2C 7 R/W 0 I2C timer bit I2C = 0: I2C = 1: ID 6 R/W 0 ID timer bit ID = 0: ID = 1: IO 5 R/W 0 IO timer bit ID remains active when ISTR.PERIS = 1 and the IDLE instruction is executed. ID is disabled when ISTR.PERIS = 1 and the IDLE instruction is executed. I2C remains active when ISTR.PERIS = 1 and the IDLE instruction is executed. I2C is disabled when ISTR.PERIS = 1 and the IDLE instruction is executed. UART remains active when ISTR.PERIS = 1 and the IDLE instruction is executed. UART is disabled when ISTR.PERIS = 1 and the IDLE instruction is executed. DESCRIPTION IO = 1: SP2 4 R/W 0 McBSP2 timer bit SP2 = 0: SP2 = 1: McBSP2 remains active when ISTR.PERIS = 1 and the IDLE instruction is executed. McBSP2 is disabled when ISTR.PERIS = 1 and the IDLE instruction is executed. SP1 3 R/W 0 McBSP1 timer bit SP1 = 0: SP1 = 1: McBSP1 remains active when ISTR.PERIS = 1 and the IDLE instruction is executed. McBSP1 is disabled when ISTR.PERIS = 1 and the IDLE instruction is executed. SP0 2 R/W 0 McBSP0 timer bit SP0 = 0: SP0 = 1: McBSP0 remains active when ISTR.PERIS = 1 and the IDLE instruction is executed. McBSP0 is disabled when ISTR.PERIS = 1 and the IDLE instruction is executed. TIM1 1 R/W 0 TIMER1 timer bit TIM1 = 0: TIM1 = 1: TIMER1 remains active when ISTR.PERIS = 1 and the IDLE instruction is executed. TIMER1 is disabled when ISTR.PERIS = 1 and the IDLE instruction is executed. TIM0 0 R/W 0 TIMER0 timer bit TIM0 = 0: TIM0 = 1: TIMER0 remains active when ISTR.PERIS = 1 and the IDLE instruction is executed. TIMER0 is disabled when ISTR.PERIS = 1 and the IDLE instruction is executed. If the peripheral is already in IDLE, setting PERIS (bit 3 of ISTR) to 0 and executing the IDLE instruction will wake up all peripherals, and PICR bit settings will be ignored. If PERIS = 1, executing the IDLE instruction will wake up the peripheral if the PICR bit is 0. December 2002 SPRS208 61 PRODUCT PREVIEW IO = 0: GPIO remains active when ISTR.PERIS = 1 and the IDLE instruction is executed. GPIO is disabled when ISTR.PERIS = 1 and the IDLE instruction is executed. Functional Overview 3.10.7.4 Peripheral IDLE Status Register (PISTR) 15 Reserved R, 00 7 I2C R, 0 6 ID R, 0 14 13 MISC R, 0 5 IO R, 0 12 EMIF R, 0 4 SP2 R, 0 11 BIOST R, 0 3 SP1 R, 0 10 WDT R, 0 2 SP0 R, 0 9 PIO R, 0 1 TIM1 R, 0 8 URT R, 0 0 TIM0 R, 0 LEGEND: R = Read, W = Write, n = value at reset Figure 3-26. Peripheral IDLE Status Register Layout (0x9401) Table 3-29. Peripheral IDLE Status Register Bit Field Description BIT NAME BIT NO. 15-14 13 ACCESS R R RESET VALUE 00 0 Reserved MISC bit MISC = 0: MISC = 1: Miscellaneous modules are active Miscellaneous modules are disabled DESCRIPTION PRODUCT PREVIEW Reserved MISC Miscellaneous modules include the XBSR, TIMEOUT Error Register, XBCR, Timer Signal Selection Register, CLKOUT Select Register, and Clock Mode Control Register. EMIF 12 R 0 EMIF bit EMIF = 0: EMIF = 1: BIOST 11 R 0 EMIF module is active EMIF module is disabled BIOS timer bit BIOST = 0: BIOST = 1: DSP/BIOS timer is active DSP/BIOS timer is disabled WDT 10 R 0 Watchdog timer bit WDT = 0: WDT = 1: WDT is active WDT is disabled PIO 9 R 0 Parallel GPIO timer bit PIO = 0: PIO = 1: Parallel GPIO is active Parallel GPIO is disabled URT 8 R 0 UART timer bit URT = 0: URT = 1: UART is active UART is disabled I2C 7 R 0 I2C timer bit I2C = 0: I2C = 1: I2C is active I2C is disabled ID 6 R 0 ID timer bit ID = 0: ID = 1: ID is active ID is disabled IO 5 R 0 IO timer bit IO = 0: IO = 1: GPIO is active GPIO is disabled 62 SPRS208 December 2002 Functional Overview Table 3-29. Peripheral IDLE Status Register Bit Field Description (Continued) BIT NAME SP2 BIT NO. 4 ACCESS R RESET VALUE 0 McBSP2 timer bit SP2 = 0: SP2 = 1: SP1 3 R 0 McBSP2 is active McBSP2 is disabled DESCRIPTION McBSP1 timer bit SP1 = 0: SP1 = 1: McBSP1 is active McBSP1 is disabled SP0 2 R 0 McBSP0 timer bit SP0 = 0: SP0 = 1: McBSP0 is active McBSP0 is disabled TIM1 1 R 0 TIMER1 timer bit TIM1 = 0: TIM1 = 1: TIMER1 is active TIMER1 is disabled TIM0 0 R 0 TIMER0 timer bit TIM0 = 0: TIM0 = 1: TIMER0 is active TIMER0 is disabled 3.10.7.5 Master IDLE Control Register (MICR) 15 Reserved R, 00000000 8 7 Reserved R, 000000 LEGEND: R = Read, W = Write, n = value at reset 2 1 HPI R/W, 0 0 DMA R/W, 0 Figure 3-27. Master IDLE Control Register Layout (0x9402) Table 3-30. Master IDLE Control Register Bit Field Description BIT NAME Reserved HPI BIT NO. 15-2 1 ACCESS R R/W RESET VALUE 00000000000000 0 Reserved HPI bit HPI = 0: HPI = 1: DMA 0 R/W 0 DMA bit DMA = 0: DMA = 1: DMA remains active when ISTR.MPIS becomes 1 DMA is disabled when ISTR.MPIS becomes 1 HPI remains active when ISTR.MPIS becomes 1 HPI is disabled when ISTR.MPIS becomes 1 DESCRIPTION December 2002 SPRS208 63 PRODUCT PREVIEW Functional Overview 3.10.7.6 Master IDLE Status Register (MISR) 15 Reserved R, 00000000 8 7 Reserved R, 000000 LEGEND: R = Read, W = Write, n = value at reset 2 1 HPI R, 0 0 DMA R, 0 Figure 3-28. Master IDLE Status Register Layout (0x9403) Table 3-31. Master IDLE Status Register Bit Field Description BIT NAME Reserved HPI BIT NO. 15-2 1 ACCESS R R RESET VALUE 00000000000000 0 Reserved HPI bit HPI = 0: HPI = 1: DMA 0 R 0 DMA bit DMA = 0: DMA = 1: DMA is active DMA is in IDLE status HPI is active HPI is in IDLE status DESCRIPTION PRODUCT PREVIEW 3.11 General-Purpose I/O (GPIO) The 5502 includes an 8-bit I/O port solely for general-purpose inputs and outputs. Several dual-purpose (multiplexed) pins complement the dedicated GPIO pins. The following sections describe the 8-bit GPIO port as well as the dual GPIO functions of the Parallel Port Mux and Host Port Mux pins. 3.11.1 General-Purpose I/O Port The general-purpose I/O port consists of eight individually bit-selectable I/O pins GPIO0 (LSB) through GPIO7 (MSB). The I/O port is controlled using two registers--IODIR and IODATA--that can be accessed by the CPU or by the DMA, via the peripheral bus controller. The General-Purpose I/O Direction Register (IODIR) is mapped at address 0x3400, and the General-Purpose I/O Data Register (IODATA) is mapped at address 0x3401. Figure 3-29 and Figure 3-30 show the bit layout of IODIR and IODATA, respectively. Table 3-32 and Table 3-33 describe the bit fields of these registers. 64 SPRS208 December 2002 Functional Overview 3.11.1.1 General-Purpose I/O Direction Register (IODIR) 15 Reserved R, 00000000 7 IO7DIR R/W, 0 6 IO6DIR R/W, 0 5 IO5DIR R/W, 0 4 IO4DIR R/W, 0 3 IO3DIR R/W, 0 2 IO2DIR R/W, 0 1 IO1DIR R/W, 0 0 IO0DIR R/W, 0 8 LEGEND: R = Read, W = Write, n = value at reset Figure 3-29. GPIO Direction Register Layout (0x3400) Table 3-32. GPIO Direction Register Bit Field Description BIT NAME Reserved IOxDIR BIT NO. 15-8 7-0 ACCESS R R/W RESET VALUE 00000000 00000000 Reserved Data direction bits that configure the GPIO pins as inputs or outputs. IOxDIR = 0: IOxDIR = 1: x = value from 0 to 7 Configure corresponding GPIO pin as an input Configure corresponding GPIO pin as an output DESCRIPTION 3.11.1.2 General-Purpose I/O Data Register (IODATA) 15 Reserved R, 00000000 7 IO7D R/W, pin 6 IO6D R/W, pin 5 IO5D R/W, pin 4 IO4D R/W, pin 3 IO3D R/W, pin 2 IO2D R/W, pin 1 IO1D R/W, pin 0 IO0D R/W, pin 8 LEGEND: R = Read, W = Write, n = value at reset, pin = the reset value depends on the signal level on the corresponding I/O pin. Figure 3-30. GPIO Data Register Layout (0x3401) Table 3-33. GPIO Data Register Bit Field Description BIT NAME Reserved IOxD BIT NO. 15-8 7-0 ACCESS R R/W RESET VALUE 00000000 Depends on the signal level on the corresponding I/O pin Reserved Data bits that are used to control the level of the I/O pins configured as outputs and to monitor the level of the I/O pins configured as inputs. If IOxDIR = 0, then: IOxD = 0: Corresponding GPIO pin is read as a low IOxD = 1: Corresponding GPIO pin is read as a high If IOxDIR = 1, then: IOxD = 0: Set corresponding GPIO pin to low IOxD = 1: Set corresponding GPIO pin to high x = value from 0 to 7 DESCRIPTION December 2002 SPRS208 65 PRODUCT PREVIEW Functional Overview 3.11.2 Parallel Port General-Purpose I/O (PGPIO) The 4 address signals (EMIF.A[21:18]), 16 data signals (EMIF.D[31:16]), 8 host data signals (HD[7:0]), 2 HPI control signals (HC1-HC0), and 16 control signals (C[15:0]) can be individually enabled as PGPIO when the Parallel Port Mux Mode bit field of the External Bus Selection Register (XBSR) is cleared for non-multiplexed HPI mode. (See Table 3-34.) These pins are controlled by three set of registers: the PGPIO enable registers, the PGPIO direction registers, and the PGPIO data registers. * * * The PGPIO enable registers PGPIOEN0-PGPIOEN2 (see Figure 3-31, Figure 3-34, and Figure 3-37) determine if the pin serves as PGPIO or if it is placed in high-impedance state. The PGPIO direction registers PGPIODIR0-PGPIODIR2 (see Figure 3-32, Figure 3-35, and Figure 3-38) determine if the pin is an input or output. The PGPIO data registers PGPIODAT0-PGPIODAT2 (see Figure 3-33, Figure 3-36, and Figure 3-39) store the value read or written externally. NOTE: The enable registers PGPIOENn cannot override the External Bus Selection Register (XBSR) setting. Table 3-34. TMS320VC5502 PGPIO Cross-Reference PRODUCT PREVIEW PIN PARALLEL PORT MUX MODE = 0 (HPI NON-MULTIPLEX) EMIF Address Bus PGPIO[3:0] EMIF Data Bus PGPIO[19:4] EMIF Control Bus PGPIO20 PGPIO21 PGPIO22 PGPIO23 PGPIO24 PGPIO25 PGPIO26 PGPIO27 PGPIO28 PGPIO29 PGPIO30 PGPIO31 PGPIO32 PGPIO33 PGPIO34 PGPIO35 HPI Data Bus PGPIO[43:36] HPI Control Bus PGPIO44 PGPIO45 PARALLEL PORT MUX MODE = 1 (FULL EMIF) EMIF.A[21:18] EMIF.D[31:16] EMIF.ARE/SADS/SDCAS/SRE EMIF.AOE/SOE/SDRAS EMIF.AWE/SWE/SDWE EMIF.ARDY EMIF.CE0 EMIF.CE1 EMIF.CE2 EMIF.CE3 EMIF.BE0 EMIF.BE1 EMIF.BE2 EMIF.BE3 EMIF.SDCKE EMIF.SOE3 EMIF.HOLD EMIF.HOLDA HPI.HD[7:0] HPI.HAS HPI.HBIL A[21:18] D[31:16] C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 HD[7:0] HC0 HC1 66 SPRS208 December 2002 Functional Overview 3.11.2.1 Parallel GPIO Enable Register 0 (PGPIOEN0) 15 IO15EN R/W, 0 7 IO7EN R/W, 0 14 IO14EN R/W, 0 6 IO6EN R/W, 0 13 IO13EN R/W, 0 5 IO5EN R/W, 0 12 IO12EN R/W, 0 4 IO4EN R/W, 0 11 IO11EN R/W, 0 3 IO3EN R/W, 0 10 IO10EN R/W, 0 2 IO2EN R/W, 0 9 IO9EN R/W, 0 1 IO1EN R/W, 0 8 IO8EN R/W, 0 0 IO0EN R/W, 0 LEGEND: R = Read, W = Write, n = value at reset Figure 3-31. Parallel GPIO Enable Register 0 Layout (0x4400) Table 3-35. Parallel GPIO Enable Register 0 Bit Field Description BIT NAME IOxEN BIT NO. 15-0 ACCESS R/W RESET VALUE 0000000000000000 DESCRIPTION Enable or disable GPIO function of the EMIF address bus EMIF.A[21:18] and the EMIF data bus EMIF.D[27:16]. See Table 3-4. IOxEN = 0: IOxEN = 1: GPIO function of corresponding signal is disabled, i.e., the pin goes into a high-impedance state. GPIO function of corresponding signal is enabled, i.e., the signal supports its GPIO function. Bits [15:4] correspond to EMIF.D[27:16] Bits [3:0] correspond to EMIF.A[21:18] x = value from 0 to 15 3.11.2.2 Parallel GPIO Direction Register 0 (PGPIODIR0) 15 IO15DIR R/W, 0 7 IO7DIR R/W, 0 14 IO14DIR R/W, 0 6 IO6DIR R/W, 0 13 IO13DIR R/W, 0 5 IO5DIR R/W, 0 12 IO12DIR R/W, 0 4 IO4DIR R/W, 0 11 IO11DIR R/W, 0 3 IO3DIR R/W, 0 10 IO10DIR R/W, 0 2 IO2DIR R/W, 0 9 IO9DIR R/W, 0 1 IO1DIR R/W, 0 8 IO8DIR R/W, 0 0 IO0DIR R/W, 0 LEGEND: R = Read, W = Write, n = value at reset Figure 3-32. Parallel GPIO Direction Register 0 Layout (0x4401) Table 3-36. Parallel GPIO Direction Register 0 Bit Field Description BIT NAME IOxDIR BIT NO. 15-0 ACCESS R/W RESET VALUE 0000000000000000 DESCRIPTION Data direction bits that configure corresponding I/O pins either as inputs or outputs. See Table 3-4. IOxDIR = 0: IOxDIR = 1: Configure corresponding pin as an input. Configure corresponding pin as an output. Bits [15:4] correspond to EMIF.D[27:16] Bits [3:0] correspond to EMIF.A[21:18] x = value from 0 to 15 December 2002 SPRS208 67 PRODUCT PREVIEW Functional Overview 3.11.2.3 Parallel GPIO Data Register 0 (PGPIODAT0) 15 IO15DAT R/W, pin 7 IO7DAT R/W, pin 14 IO14DAT R/W, pin 6 IO6DAT R/W, pin 13 IO13DAT R/W, pin 5 IO5DAT R/W, pin 12 IO12DAT R/W, pin 4 IO4DAT R/W, pin 11 IO11DAT R/W, pin 3 IO3DAT R/W, pin 10 IO10DAT R/W, pin 2 IO2DAT R/W, pin 9 IO9DAT R/W, pin 1 IO1DAT R/W, pin 8 IO8DAT R/W, pin 0 IO0DAT R/W, pin LEGEND: R = Read, W = Write, n = value at reset, pin = the reset value depends on the signal level on the corresponding I/O pin. Figure 3-33. Parallel GPIO Data Register 0 Layout (0x4402) Table 3-37. Parallel GPIO Data Register 0 Bit Field Description BIT NAME BIT NO. 15-0 ACCESS R/W RESET VALUE Depends on the signal level on the corresponding I/O pin DESCRIPTION Data bits that are used to control the level of the corresponding signals configured as I/O output pins and to monitor the level of the corresponding signals configured as I/O input pins. See Table 3-4. If IOxDIR = 0, then: IOxDAT = 0: IOxDAT = 1: Corresponding I/O pin is read as a low Corresponding I/O pin is read as a high PRODUCT PREVIEW IOxDAT If IOxDIR = 1, then: IOxDAT = 0: IOxDAT = 1: Set corresponding I/O pin to low Set corresponding I/O pin to high Bits [15:4] correspond to EMIF.D[27:16] Bits [3:0] correspond to EMIF.A[21:18] x = value from 0 to 15 68 SPRS208 December 2002 Functional Overview 3.11.2.4 Parallel GPIO Enable Register 1 (PGPIOEN1) 15 IO31EN R/W, 0 7 IO23EN R/W, 0 14 IO30EN R/W, 0 6 IO22EN R/W, 0 13 IO29EN R/W, 0 5 IO21EN R/W, 0 12 IO28EN R/W, 0 4 IO20EN R/W, 0 11 IO27EN R/W, 0 3 IO19EN R/W, 0 10 IO26EN R/W, 0 2 IO18EN R/W, 0 9 IO25EN R/W, 0 1 IO17EN R/W, 0 8 IO24EN R/W, 0 0 IO16EN R/W, 0 LEGEND: R = Read, W = Write, n = value at reset Figure 3-34. Parallel GPIO Enable Register 1 Layout (0x4403) Table 3-38. Parallel GPIO Enable Register 1 Bit Field Description BIT NAME IOxEN BIT NO. 15-0 ACCESS R/W RESET VALUE 0000000000000000 DESCRIPTION Enable or disable GPIO function of the EMIF data bus EMIF.D[31:28] and the EMIF control signals C[11:0]. See Table 3-4. IOxEN = 0: IOxEN = 1: GPIO function of corresponding signal is disabled, i.e., the pin goes into a high-impedance state. GPIO function of corresponding signal is enabled, i.e., the signal supports its GPIO function. Bits [15:4] correspond to C[11:0] Bits [3:0] correspond to EMIF.D[31:28] x = value from 16 to 31 3.11.2.5 Parallel GPIO Direction Register 1 (PGPIODIR1) 15 IO31DIR R/W, 0 7 IO23DIR R/W, 0 14 IO30DIR R/W, 0 6 IO22DIR R/W, 0 13 IO29DIR R/W, 0 5 IO21DIR R/W, 0 12 IO28DIR R/W, 0 4 IO20DIR R/W, 0 11 IO27DIR R/W, 0 3 IO19DIR R/W, 0 10 IO26DIR R/W, 0 2 IO18DIR R/W, 0 9 IO25DIR R/W, 0 1 IO17DIR R/W, 0 8 IO24DIR R/W, 0 0 IO16DIR R/W, 0 LEGEND: R = Read, W = Write, n = value at reset Figure 3-35. Parallel GPIO Direction Register 1 Layout (0x4404) Table 3-39. Parallel GPIO Direction Register 1 Bit Field Description BIT NAME IOxDIR BIT NO. 15-0 ACCESS R/W RESET VALUE 0000000000000000 DESCRIPTION Data direction bits that configure corresponding I/O pins either as inputs or outputs. See Table 3-4. IOxDIR = 0: IOxDIR = 1: Configure corresponding pin as an input. Configure corresponding pin as an output. Bits [15:4] correspond to C[11:0] Bits [3:0] correspond to EMIF.D[31:28] x = value from 16 to 31 December 2002 SPRS208 69 PRODUCT PREVIEW Functional Overview 3.11.2.6 Parallel GPIO Data Register 1 (PGPIODAT1) 15 IO31DAT R/W, pin 7 IO23DAT R/W, pin 14 IO30DAT R/W, pin 6 IO22DAT R/W, pin 13 IO29DAT R/W, pin 5 IO21DAT R/W, pin 12 IO28DAT R/W, pin 4 IO20DAT R/W, pin 11 IO27DAT R/W, pin 3 IO19DAT R/W, pin 10 IO26DAT R/W, pin 2 IO18DAT R/W, pin 9 IO25DAT R/W, pin 1 IO17DAT R/W, pin 8 IO24DAT R/W, pin 0 IO16DAT R/W, pin LEGEND: R = Read, W = Write, n = value at reset, pin = the reset value depends on the signal level on the corresponding I/O pin. Figure 3-36. Parallel GPIO Data Register 1 Layout (0x4405) Table 3-40. Parallel GPIO Data Register 1 Bit Field Description BIT NAME BIT NO. 15-0 ACCESS R/W RESET VALUE Depends on the signal level on the corresponding I/O pin DESCRIPTION Data bits used to control the level of the corresponding signals configured as output pins and to monitor the level of the corresponding signals configured as input pins. See Table 3-4. If IOxDIR = 0, then: IOxDAT = 0: IOxDAT = 1: Corresponding I/O pin is read as a low Corresponding I/O pin is read as a high IOxDAT PRODUCT PREVIEW If IOxDIR = 1, then: IOxDAT = 0: IOxDAT = 1: Set corresponding I/O pin to low Set corresponding I/O pin to high Bits [15:4] correspond to C[11:0] Bits [3:0] correspond to EMIF.D[31:28] x = value from 16 to 31 70 SPRS208 December 2002 Functional Overview 3.11.2.7 Parallel GPIO Enable Register 2 (PGPIOEN2) 15 Reserved R/W, 00 7 IO39EN R/W, 0 6 IO38EN R/W, 0 14 13 IO45EN R/W, 0 5 IO37EN R/W, 0 12 IO44EN R/W, 0 4 IO36EN R/W, 0 11 IO43EN R/W, 0 3 IO35EN R/W, 0 10 IO42EN R/W, 0 2 IO34EN R/W, 0 9 IO41EN R/W, 0 1 IO33EN R/W, 0 8 IO40EN R/W, 0 0 IO32EN R/W, 0 LEGEND: R = Read, W = Write, n = value at reset Figure 3-37. Parallel GPIO Enable Register 2 Layout (0x4406) Table 3-41. Parallel GPIO Enable Register 2 Bit Field Description BIT NAME Reserved IOxEN BIT NO. 15-14 13-0 ACCESS R/W R/W RESET VALUE 00 00000000000000 Reserved Enable or disable GPIO function of the EMIF control signals C[15:12], the HPI data pins HD[7:0], and the HPI control signals HC[1:0]. See Table 3-4 and Table 3-5. IOxEN = 0: IOxEN = 1: GPIO function of corresponding signal is disabled, i.e., the pin goes into a high-impedance state. GPIO function of corresponding signal is enabled, i.e., the signal supports its GPIO function. DESCRIPTION Bits [13:12] correspond to HC[1:0] Bits [11:4] correspond to HD[7:0] Bits [3:0] correspond to C[15:12] x = value from 32 to 45 3.11.2.8 Parallel GPIO Direction Register 2 (PGPIODIR2) 15 Reserved R/W, 00 7 IO39DIR R/W, 0 6 IO38DIR R/W, 0 14 13 IO45DIR R/W, 0 5 IO37DIR R/W, 0 12 IO44DIR R/W, 0 4 IO36DIR R/W, 0 11 IO43DIR R/W, 0 3 IO35DIR R/W, 0 10 IO42DIR R/W, 0 2 IO34DIR R/W, 0 9 IO41DIR R/W, 0 1 IO33DIR R/W, 0 8 IO40DIR R/W, 0 0 IO32DIR R/W, 0 LEGEND: R = Read, W = Write, n = value at reset Figure 3-38. Parallel GPIO Direction Register 2 Layout (0x4407) December 2002 SPRS208 71 PRODUCT PREVIEW Functional Overview Table 3-42. Parallel GPIO Direction Register 2 Bit Field Description BIT NAME Reserved IOxDIR BIT NO. 15-14 13-0 ACCESS R/W R/W RESET VALUE 00 00000000000000 Reserved Data direction bits that configure corresponding I/O pins either as inputs or outputs. See Table 3-4 and Table 3-5. IOxDIR = 0: IOxDIR = 1: Configure corresponding pin as an input. Configure corresponding pin as an output. DESCRIPTION Bits [13:12] correspond to HC[1:0] Bits [11:4] correspond to HD[7:0] Bits [3:0] correspond to C[15:12] x = value from 32 to 45 3.11.2.9 Parallel GPIO Data Register 2 (PGPIODAT2) 15 14 Reserved R/W, 00 7 IO39DAT R/W, pin 6 IO38DAT R/W, pin 13 IO45DAT R/W, pin 5 IO37DAT R/W, pin 12 IO44DAT R/W, pin 4 IO36DAT R/W, pin 11 IO43DAT R/W, pin 3 IO35DAT R/W, pin 10 IO42DAT R/W, pin 2 IO34DAT R/W, pin 9 IO41DAT R/W, pin 1 IO33DAT R/W, pin 8 IO40DAT R/W, pin 0 IO32DAT R/W, pin PRODUCT PREVIEW LEGEND: R = Read, W = Write, n = value at reset, pin = the reset value depends on the signal level on the corresponding I/O pin. Figure 3-39. Parallel GPIO Data Register 2 Layout (0x4408) Table 3-43. Parallel GPIO Data Register 2 Bit Field Description BIT NAME Reserved IOxDAT BIT NO. 15-14 13-0 ACCESS R/W R/W RESET VALUE 00 Depends on the signal level on the corresponding I/O pin Reserved Data bits used to control the level of the EMIF control signals C[15:12], the HPI data pins HD[7:0], and the HPI control signals HC[1:0] configured as I/O output pins, and to monitor the level of the corresponding signals configured as I/O input signals. See Table 3-4 and Table 3-5. If IOxDIR = 0, then: IOxDAT = 0: IOxDAT = 1: Corresponding I/O pin is read as a low Corresponding I/O pin is read as a high DESCRIPTION If IOxDIR = 1, then: IOxDAT = 0: IOxDAT = 1: Set corresponding I/O pin to low Set corresponding I/O pin to high Bits [13:12] correspond to HC[1:0] Bits [11:4] correspond to HD[7:0] Bits [3:0] correspond to C[15:12] x = value from 32 to 45 72 SPRS208 December 2002 Functional Overview 3.12 External Bus Control Register The I/O macro control register is used to control I/O macro function (bus holder, pullup, pulldown) of the device I/O pins. 3.12.1 External Bus Control Register (XBCR) 15 Reserved R, 00000000 8 7 EMU R/W, 0 6 TEST R/W, 0 5 WDT R/W, 0 4 HC R/W, 0 3 HD R/W, 0 2 PC R/W, 0 1 PD R/W, 0 0 PA R/W, 0 LEGEND: R = Read, W = Write, n = value at reset Figure 3-40. External Bus Control Register Layout (0x6C01) Table 3-44. External Bus Control Register Bit Field Description BIT NAME Reserved EMU BIT NO. 15-8 7 ACCESS R R/W RESET VALUE 00000000 0 Reserved EMU bit EMU = 0: EMU = 1: TEST 6 R/W 0 TEST bit TEST = 0: Pullups/pulldowns on test pins are enabled (does not include EMU1 and EMU0 pins) TEST = 1: Pullups/pulldowns on test pins are disabled (does not include EMU1 and EMU0 pins) WDT 5 R/W 0 WDT bit WDT = 0: Pullup on NMI/WDTOUT pin is enabled WDT = 1: Pullup on NMI/WDTOUT pin is disabled HC 4 R/W 0 HPI control signal bit HC = 0: HC = 1: HD 3 R/W 0 Pullups/pulldowns on HPI control signals (HC bus) pins are enabled Pullups/pulldowns on HPI control signals (HC bus) pins are disabled Pullups on EMU1 and EMU0 pins are enabled. Pullups on EMU1 and EMU0 pins are disabled. DESCRIPTION HPI data bus bit HD = 0: HD = 1: Bus holders on HPI data bus (HD bus) are enabled Bus holders on HPI data bus (HD bus) are disabled PC 2 R/W 0 EMIF control signals PC = 0: PC = 1: Bus holders on EMIF control signals (C bus) are enabled Bus holders on EMIF control signals (C bus) are disabled December 2002 SPRS208 73 PRODUCT PREVIEW Functional Overview Table 3-44. External Bus Control Register Bit Field Description (Continued) BIT NAME PD BIT NO. 1 ACCESS R/W RESET VALUE 0 EMIF data bus signals PD = 0: PD = 1: PA 0 R/W 0 Bus holders on EMIF data bus signals (D bus) are enabled Bus holders on EMIF data bus signals (D bus) are disabled DESCRIPTION EMIF address bus signals PA = 0: PA = 1: Bus holders on EMIF address bus signals (A bus) are enabled Bus holders on EMIF address bus signals (A bus) are disabled 3.13 Internal Ports and System Registers The 5502 includes three internal ports that interface the CPU core with the peripheral modules. Although these ports cannot be directly controlled by user code, the registers associated with each port can be used to monitor a number of error conditions that could be generated through illegal operation of the 5502. The port registers are described in the following sections. PRODUCT PREVIEW The 5502 also includes two registers that can be used to monitor and control several aspects of the interface between the CPU and the system-level peripherals, these registers are also described in the following sections. 3.13.1 XPORT Interface The XPORT interfaces the CPU core to all peripheral modules. The XPORT will generate bus errors for invalid accesses to any registers that fall under the ranges shown in Table 3-45. The INTERREN bit of the XPORT Configuration Register (XCR) controls the bus error feature of the XPORT. The INTERR bit of the XPORT Bus Error Register (XERR) is set to "1" when an error occurs during an access to a register listed in Table 3-45. The EBUS and DBUS bits can be used to distinguish whether the error occurred during a write or read access. Table 3-45. I/O Addresses Under Scope of XPORT I/O ADDRESS RANGE 0x0000-0x03FF 0x1400-0x17FF 0x2000-0x23FF The PERITO bit of the XERR is used to indicate that a CPU, DMA, or HPI access to a disabled/idled peripheral module has generated a time-out error. The time-out error feature is enabled through the PERITOEN bit of the Time-Out Control Register (TOCR). A time-out error is generated when 512 clock cycles pass without a response from the peripheral register. The XPORT can be placed into idle by setting the XPORTI bit of the Idle Control Register (ICR) and executing the IDLE instruction. When the XPORT is in idle, it will stop accepting new peripheral module requests and it will also not check for internal I/O bus errors. If there is a request from the CPU core or a peripheral module, the XPORT will not respond and hang. The ICR register will generate a bus error if the XPORT is idled without the CPU or Master Port domains being in idle mode. 74 SPRS208 December 2002 Functional Overview 3.13.1.1 XPORT Configuration Register (XCR) The XPORT Configuration Register bit layout is shown in Figure 3-41 and the bits are described in Table 3-46. 15 INTERREN R/W, 1 14 Reserved R, 0000000 8 7 Reserved R, 00000000 LEGEND: R = Read, W = Write, n = value at reset 0 Table 3-46. XPORT Configuration Register Bit Field Description BIT NAME INTERREN BIT NO. 15 ACCESS R/W RESET VALUE 1 INTERREN bit INTERREN = 0: The XPORT will not generate a bus error for invalid accesses to registers listed in Table 3-45. Note that any invalid accesses to these registers will hang the pipeline. The XPORT will generate a bus error for invalid accesses to registers listed in Table 3-45. Note that when a bus error occurs, any data returned by the read instruction will not be valid. DESCRIPTION INTERREN = 1: Reserved 14-0 R 000000000000000 Reserved This feature will not work if the XPORT is placed in idle through the ICR. However, a bus error will be generated if the XPORT is placed in idle without the CPU being in idle. December 2002 SPRS208 75 PRODUCT PREVIEW Figure 3-41. XPORT Configuration Register Layout (0x0100) Functional Overview 3.13.1.2 XPORT Bus Error Register (XERR) The XPORT Bus Error Register bit layout is shown in Figure 3-42 and the bits are described in Table 3-47. 15 INTERR R, 1 14 Reserved R, 00 13 12 PERITO R, 0 11 Reserved R, 0000 8 7 Reserved R, 000 5 4 EBUS R, 0 3 DBUS R, 0 2 Reserved R, 000 0 LEGEND: R = Read, W = Write, n = value at reset Figure 3-42. XPORT Bus Error Register Layout (0x0102) PRODUCT PREVIEW Table 3-47. XPORT Bus Error Register Bit Field Description BIT NAME INTERR BIT NO. 15 ACCESS R RESET VALUE 1 INTERR bit INTERR = 0: INTERR = 1: Reserved PERITO 14-13 12 R R 00 0 Reserved PERITO bit PERITO = 0: PERITO = 1: Reserved EBUS 11-5 4 R R 0000000 0 Reserved EBUS error bit EBUS = 0: EBUS = 1: DBUS 3 R 0 DBUS error bit DBUS = 0: DBUS = 1: No error An error occurred during a DBUS access (read) to one of the registers listed in Table 3-45. No error An error occurred during an EBUS access (write) to one of the registers listed in Table 3-45. No error A time-out error occurred during an access to a peripheral register. No error An error occurred during an access to one of the registers listed in Table 3-45. DESCRIPTION Reserved 2-0 R 000 Reserved See the TMS320C55x DSP CPU Reference Guide (literature number SPRU371) for more information on the D-bus and E-bus. 76 SPRS208 December 2002 Functional Overview 3.13.2 DPORT Interface The DPORT interfaces the CPU to the EMIF module. The DPORT is capable of enabling write posting on the EMIF module. Write posting prevents stalls to the CPU during external memory writes. Two write posting registers, which are freely associated with E and F bus writes, exist within the DPORT and are used to store the write address and data so that writes can be zero wait state for the CPU. External memory writes will not generate stalls to the CPU unless the two write posting registers are filled. Write posting is enabled by setting the WPE bit of the DCR to 1. The EMIFTO bit of the DERR is used to indicate that a CPU, DMA, HPI, or IPORT access to external memory has generated a time-out error. The time-out error feature is enabled through the EMIFTOEN bit of the Time-Out Control Register (TOCR). This function is not recommended during normal operation of the 5502. The DPORT can be placed into idle through the EMIFI bit of the Idle Control Register (ICR) and executing the IDLE instruction. When the DPORT is in idle, it will stop accepting new EMIF requests. If there is a request from the CPU or the EMIF, the DPORT will not respond and hang. The ICR register will generate a bus error if the DPORT is idled without the CPU or Master Port domains being in idle. 3.13.2.1 DPORT Configuration Register (DCR) 15 Reserved R, 00000000 8 7 WPE R/W, 0 6 Reserved R, 0000000 0 LEGEND: R = Read, W = Write, n = value at reset Figure 3-43. DPORT Configuration Register Layout (0x0200) Table 3-48. DPORT Configuration Register Bit Field Description BIT NAME Reserved WPE BIT NO. 15-8 7 ACCESS R R/W RESET VALUE 00000000 0 Reserved Write Posting Enable bit WPE = 0: WPE = 1: Write posting disabled Write posting enabled DESCRIPTION Reserved 6-0 R 0000000 Reserved Write posting should not be enabled or disabled while the EMIF is conducting a transaction with external memory. December 2002 SPRS208 77 PRODUCT PREVIEW The DPORT Configuration Register bit layout is shown in Figure 3-43 and the bits are described in Table 3-48. Functional Overview 3.13.2.2 DPORT Bus Error Register (DERR) The DPORT Bus Error Register bit layout is shown in Figure 3-44 and the bits are described in Table 3-49. 15 Reserved R, 000 13 12 EMIFTO R, 0 11 Reserved R, 0000 8 7 Reserved R, 00000000 LEGEND: R = Read, W = Write, n = value at reset 0 Figure 3-44. DPORT Bus Error Register Layout (0x0202) PRODUCT PREVIEW Table 3-49. DPORT Bus Error Register Bit Field Description BIT NAME Reserved EMIFTO BIT NO. 15-13 12 ACCESS R R RESET VALUE 000 0 Reserved EMIFTO bit EMIFTO = 0: EMIFTO = 1: Reserved 11-0 R 000000000000 Reserved No error Error 1 error DESCRIPTION 78 SPRS208 December 2002 Functional Overview 3.13.3 IPORT Interface The IPORT interfaces the I-Cache to the EMIF module. The ICACHETO bit of the IPORT Bus Error Register (IERR) can be used to determine if a time-out error has occurred during an ICACHE access to external memory. The time-out feature is enabled through the EMIFTOEN bit of the Time-Out Control Register (TOCR). The IPORT can be placed into idle through the IPORTI bit of the Idle Control Register (ICR) and executing the IDLE instruction. The IPORT will go into idle when there are no new requests from the ICACHE. When the IPORT is in idle, it will stop accepting new requests from the CPU, it is important that the program flow not use external memory in this case. If there are requests from the CPU, the IPORT will not respond and hang. The ICR register will generate a bus error if the IPORT is idled without the CPU domain being in idle. 3.13.3.1 IPORT Bus Error Register (IERR) The IPORT Bus Error Register bit layout is shown in Figure 3-45 and the bits are described in Table 3-50. 15 Reserved R, 000 13 12 ICACHETO R, 0 11 Reserved R, 0000 8 7 Reserved R, 00000000 LEGEND: R = Read, W = Write, n = value at reset 0 Figure 3-45. IPORT Bus Error Register Layout (0x0302) Table 3-50. IPORT Bus Error Register Bit Field Description BIT NAME Reserved ICACHETO BIT NO. 15-13 12 ACCESS R R RESET VALUE 000 0 Reserved ICACHETO bit ICACHETO = 0: ICACHETO = 1: No error A time-out error occurred during an ICACHE access to external memory. DESCRIPTION Reserved 11-0 R 000000000000 Reserved See the TMS320C55x DSP CPU Reference Guide (literature number SPRU371) for more information on the P-bus. December 2002 SPRS208 79 PRODUCT PREVIEW Functional Overview 3.13.4 System Configuration Register (CONFIG) The System Configuration Register can be used to determine the operational state of the ICACHE. If the ICACHE is not functioning, the CACHEPRES bit of the CONFIG register will be cleared. If the ICACHE is functioning normally, this bit will be set. The System Configuration Register bit layout is shown in Figure 3-46 and the bits are described in Table 3-51. 15 Reserved R, 00000010 8 7 Reserved R, 00 6 5 CACHEPRES R, 0 4 Reserved RW, 0 3 Reserved R, 0000 0 PRODUCT PREVIEW LEGEND: R = Read, W = Write, n = value at reset This Reserved bit must be kept as zero during any writes to CONFIG. Figure 3-46. System Configuration Register Layout (0x07FD) Table 3-51. System Configuration Register Bit Field Description BIT NAME Reserved CACHEPRES BIT NO. 15-6 5 ACCESS R R RESET VALUE 0000001000 0 Reserved ICACHE present CACHEPRES = 0: ICACHE is not functioning CACHEPRES = 1: ICACHE is enabled and working Reserved 4 R/W 0 Reserved Reserved 3-0 R 0000 Reserved This Reserved bit must be kept as zero during any writes to CONFIG. DESCRIPTION 80 SPRS208 December 2002 Functional Overview 3.13.5 Time-Out Control Register (TOCR) The Time-Out Control Register can be used to select whether or not a time-out error is generated when an access to a disabled/idled peripheral module occurs. If the CPU or DMA access a disabled/idle peripheral module and 512 CPU clock cycles pass without an acknowledgement from the peripheral module, then a time-out error will be sent to the corresponding module if bit 1 in the Time-Out Control Register is set. A time-out error will generate a CPU bus error that can be serviced through software by using the bus error interrupt (BERR) (see Section 3.16, Interrupts, for more information on interrupts). If the DMA gets a time-out error, it will set the TIMEOUT bit in the DMA Status Register (DMACSR) and generate a time-out error that can be serviced through software by the CPU [see the TMS320C55x DSP Peripherals Reference Guide (literature number SPRU317) for more information on using this feature of the DMA]. The Time-Out Control Register can also be used to select whether or not a time-out error is generated when a memory access through the EMIF module stalls for more than 512 CPU clock cycles. It is recommended that this feature not be used for it can cause unexpected results. 15 Reserved R, 00000000 7 Reserved R, 000000 LEGEND: R = Read, W = Write, n = value at reset 2 1 EMIFTOEN R/W, 0 0 PERITOEN R/W, 1 8 Figure 3-47. Time-Out Control Register Layout (0x9000) Table 3-52. Time-Out Control Register Bit Field Description BIT NAME Reserved EMIFTOEN BIT NO. 15-2 1 ACCESS R R/W RESET VALUE 00000000000000 0 Reserved EMIF time-out control bit EMIFTOEN = 0: EMIFTOEN = 1: A time-out error is not generated when an EMIF access stalls for more than 512 CPU clock cycles. A time-out error is generated when an EMIF access stalls for more than 512 CPU clock cycles. DESCRIPTION PERITOEN 0 R/W 1 Peripheral module time-out control bit PERITOEN = 0: PERITOEN = 1: A time-out error is not generated when a CPU access to a disabled/idle peripheral module stalls for more than 512 CPU clock cycles. A time-out error is generated when a CPU access to a disabled/idle peripheral module stalls for more than 512 CPU clock cycles. December 2002 SPRS208 81 PRODUCT PREVIEW Functional Overview 3.14 CPU Memory-Mapped Registers The 5502 has 78 memory-mapped CPU registers that are mapped in data memory space address 0h to 4Fh. Table 3-53 provides a list of the CPU memory-mapped registers (MMRs) available. The corresponding TMS320C54x (C54x) CPU registers are also indicated where applicable. Table 3-53. CPU Memory-Mapped Registers C54X REGISTER IER IFR - - - - ST0 ST1 AL C55X REGISTER IER0 IFR0 ST0_55 ST1_55 ST3_55 - ST0 ST1 AC0L AC0H AC0G AC1L AC1H AC1G T3 TRN0 AR0 AR1 AR2 AR3 AR4 AR5 AR6 AR7 SP BK03 BRC0 RSA0L REA0L PMST XPC - T0 T1 T2 T3 AC2L AC2H AC2G WORD ADDRESS (HEX) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 Temporary Register 3 Transition Register 0 Auxiliary Register 0 Auxiliary Register 1 Auxiliary Register 2 Auxiliary Register 3 Auxiliary Register 4 Auxiliary Register 5 Auxiliary Register 6 Auxiliary Register 7 Data Stack Pointer Circular Buffer Size Register for AR[0-3] Block Repeat Counter 0 Low Part of Block Repeat Start Address Register 0 Low Part of Block Repeat End Address Register 0 Status Register 3 (protected address for C54x code) Program Counter Extension Register for C54x code Reserved Temporary Register 0 Temporary Register 1 Temporary Register 2 Temporary Register 3 Accumulator 2 Accumulator 1 Accumulator 0 C55X REGISTER DESCRIPTION Interrupt Enable Register 0 Interrupt Flag Register 0 Status Register 0 Status Register 1 Status Register 3 Reserved Status Register 0 (protected address for C54x code) Status Register 1 (protected address for C54x code) BIT FIELD [15-0] [15-0] [15-0] [15-0] [15-0] [15-0] [15-0] [15-0] [15-0] [31-16] [39-32] [15-0] [31-16] [39-32] [15-0] [15-0] [15-0] [15-0] [15-0] [15-0] [15-0] [15-0] [15-0] [15-0] [15-0] [15-0] [15-0] [15-0] [15-0] [15-0] [7-0] [15-0] [15-0] [15-0] [15-0] [15-0] [15-0] [31-16] [39-32] PRODUCT PREVIEW 82 AH AG BL BH BG TREG TRN AR0 AR1 AR2 AR3 AR4 AR5 AR6 AR7 SP BK BRC RSA REA PMST XPC - - - - - - - - TMS320C54x and C54x are trademarks of Texas Instruments. SPRS208 December 2002 Functional Overview Table 3-53. CPU Memory-Mapped Registers (Continued) C54X REGISTER - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - C55X REGISTER CDP AC3L AC3H AC3G DPH - - DP PDP BK47 BKC BSA01 BSA23 BSA45 BSA67 BSAC BIOS TRN1 BRC1 BRS1 CSR RSA0H RSA0L REA0H REA0L RSA1H RSA1L REA1H REA1L RPTC IER1 IFR1 DBIER0 DBIER1 IVPD IVPH ST2_55 SSP SP SPH CDPH WORD ADDRESS (HEX) 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F Single Repeat Counter Interrupt Enable Register 1 Interrupt Flag Register 1 Debug Interrupt Enable Register 0 Debug Interrupt Enable Register 0 Interrupt Vector Pointer Interrupt Vector Pointer Status Register 2 System Stack Pointer Data Stack Pointer High Part of the Extended Stack Pointers (XSP = SPH:SP, XSSP = SPH:SSP) High Part of the Extended Coefficient Data Pointer (XCDP = CDPH:CDP) Block Repeat End Address Register 1 Block Repeat Start Address Register 1 Block Repeat End Address Register 0 High Part of the Extended Data Page Register (XDP = DPH:DP) Reserved Reserved Data Page Register Peripheral Data Page Register Circular Buffer Size Register for AR[4-7] Circular Buffer Size Register for CDP Circular Buffer Start Address Register for AR[0-1] Circular Buffer Start Address Register for AR[2-3] Circular Buffer Start Address Register for AR[4-5] Circular Buffer Start Address Register for AR[6-7] Circular Buffer Start Address Register for CDP Data Page Pointer Storage Location for 128-word Data Table Transition Register 1 Block Repeat Counter 1 BRC1 Save Register Computed Single Repeat Register Block Repeat Start Address Register 0 C55X REGISTER DESCRIPTION Coefficient Data Pointer Accumulator 3 BIT FIELD [15-0] [15-0] [31-16] [39-32] [6-0] [6-0] [6-0] [15-0] [8-0] [15-0] [15-0] [15-0] [15-0] [15-0] [15-0] [15-0] [15-0] [15-0] [15-0] [15-0] [23-16] [15-0] [23-16] [15-0] [23-16] [15-0] [23-16] [15-0] [15-0] [15-0] [15-0] [15-0] [15-0] [15-0] [15-0] [15-0] [15-0] [15-0] [6-0] [6-0] [15-0] December 2002 SPRS208 83 PRODUCT PREVIEW Functional Overview 3.15 Peripheral Registers Each 5502 device has a set of memory-mapped registers associated with peripherals as listed in Table 3-54 through Table 3-73. Some registers use less than 16 bits. When reading these registers, unused bits are always read as 0. Table 3-54. Peripheral Bus Controller Configuration Registers WORD ADDRESS 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 ICR ISTR PER1 PER2 PER3 PER4 PER5 PER6 PER7 PER8 PER9 PER10 PER11 Reserved BOOT_MOD Reserved Reserved XCR XERR DCR DERR IERR XPORT Configuration Register XPORT Bus Error Register DPORT Configuration Register DPORT Bus Error Register IPORT Bus Error Register System Configuration Register 1000 0000 0000 0000 1000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 0000 0000 Boot Mode Register (read only) Value of GPIO[2:0] at reset REGISTER NAME CMR DESCRIPTION Control Mode Register Idle Configuration Register Idle Status Register Priority Encoder Register 1 Priority Encoder Register 2 Priority Encoder Register 3 Priority Encoder Register 4 Priority Encoder Register 5 Priority Encoder Register 6 Priority Encoder Register 7 Priority Encoder Register 8 Priority Encoder Register 9 Priority Encoder Register 10 Priority Encoder Register 11 RESET VALUE 1111 1110 1001 0011 0000 0000 0000 0000 0000 0000 0000 0000 00001-00000000 01100-00000010 00111-00000110 01001-00001000 01111-00001110 10101-00010000 00100-00000011 01011-00001000 10010-00010001 10100-00010011 00101-00011101 PRODUCT PREVIEW 0x0009 0x000A 0x000B 0x000C 0x000D 0x000E 0x000F 0x0010 0x0011 0x0100 0x0102 0x0200 0x0202 0x0302 0x07FD CONFIG x denotes a "don't care." 84 SPRS208 December 2002 Functional Overview Table 3-55. External Memory Interface Registers WORD ADDRESS 0x0800 0x0801 0x0802 0x0803 0x0804 0x0805 0x0806 0x0807 0x0808 0x0809 0x080A 0x080B 0x080C 0x080D 0x080E 0x080F 0x0810 0x0811 0x0812 : 0x0821 0x0822 0x0823 0x0824 0x0825 0x0826 0x0827 0x0828 0x0829 0x082A 0x082B 0x082C : REGISTER NAME EGCR1 EGCR2 CE1_1 CE1_2 CE0_1 CE0_2 - - CE2_1 CE2_2 CE3_1 CE3_2 SDC1 SDC2 SDRC1 SDRC2 SDX1 SDX2 - - - CE1_SC1 CE1_SC2 CE0_SC1 CE0_SC2 - - CE2_SC1 CE2_SC2 CE3_SC1 CE3_SC2 - - DESCRIPTION EMIF Global Control Register 1 EMIF Global Control Register 2 EMIF CE1 Space Control Register 1 EMIF CE1 Space Control Register 2 EMIF CE0 Space Control Register 1 EMIF CE0 Space Control Register 2 Reserved Reserved EMIF CE2 Space Control Register 1 EMIF CE2 Space Control Register 2 EMIF CE3 Space Control Register 1 EMIF CE3 Space Control Register 2 EMIF SDRAM Control Register 1 EMIF SDRAM Control Register 2 EMIF SDRAM Refresh Control Register 1 EMIF SDRAM Refresh Control Register 2 EMIF SDRAM Extension Register 1 EMIF SDRAM Extension Register 2 Reserved : Reserved EMIF CE1 Secondary Control Register 1 EMIF CE1 Secondary Control Register 2 EMIF CE0 Secondary Control Register 1 EMIF CE0 Secondary Control Register 2 Reserved Reserved EMIF CE2 Secondary Control Register 1 EMIF CE2 Secondary Control Register 2 EMIF CE3 Secondary Control Register 1 EMIF CE3 Secondary Control Register 2 Reserved : Reserved 0000 0000 0000 0010 0000 0000 0000 0000 0000 0000 0000 0010 0000 0000 0000 0000 0000 0000 0000 0010 0000 0000 0000 0000 0000 0000 0000 0010 0000 0000 0000 0000 1111 1111 1111 0011 1111 1111 1111 1111 1111 1111 1111 0011 1111 1111 1111 1111 1111 0000 0000 0000 0000 0011 0100 1000 1100 0101 1101 1100 0000 0000 0101 1101 1111 1001 0100 1000 1111 1001 0100 1000 RESET VALUE 0000 0000 0110 0000 0000 0000 0000 1001 1111 1111 1111 0011 1111 1111 1111 1111 0000 0000 0000 0010 0000 0000 0000 0000 0x0839 - x denotes a "don't care." December 2002 SPRS208 85 PRODUCT PREVIEW Functional Overview Table 3-56. DMA Configuration Registers WORD ADDRESS REGISTER NAME DESCRIPTION GLOBAL REGISTER 0x0E00 0x0E01 DMA_GCR(2:0) DMA_GTCR(3:0) DMA Global Control Register DMA Global Timeout Control Register CHANNEL #0 REGISTERS 0x0C00 0x0C01 0x0C02 0x0C03 0x0C04 0x0C05 0x0C06 0x0C07 0x0C08 0x0C09 0x0C0A 0x0C0B 0x0C0C 0x0C0D 0x0C0E 0x0C0F DMA_CSDP0 DMA_CCR0(15:0) DMA_CICR0(5:0) DMA_CSR0(6:0) DMA_CSSA_L0 DMA_CSSA_U0 DMA_CDSA_L0 DMA_CDSA_U0 DMA_CEN0 DMA_CFN0 DMA_CSFI0 DMA_CSEI0 DMA_CSAC0 DMA_CDAC0 DMA_CDEI0 DMA_CDFI0 DMA Channel 0 Source Destination Parameters Register DMA Channel 0 Control Register DMA Channel 0 Interrupt Control register DMA Channel 0 Status register DMA Channel 0 Source Start Address, lower bits, register DMA Channel 0 Source Start Address, upper bits, register DMA Channel 0 Source Destination Address, lower bits, register DMA Channel 0 Source Destination Address, upper bits, register DMA Channel 0 Element Number register DMA Channel 0 Frame Number register DMA Channel 0 Source Frame Index register DMA Channel 0 Source Element Index register DMA Channel 0 Source Address Counter register DMA Channel 0 Destination Address Counter register DMA Channel 0 Destination Element Index register DMA Channel 0 Destination Frame Index register CHANNEL #1 REGISTERS 0x0C20 0x0C21 0x0C22 0x0C23 0x0C24 0x0C25 0x0C26 0x0C27 0x0C28 0x0C29 0x0C2A 0x0C2B 0x0C2C 0x0C2D 0x0C2E 0x0C2F DMA_CSDP1 DMA_CCR1(15:0) DMA_CICR1(5:0) DMA_CSR1(6:0) DMA_CSSA_L1 DMA_CSSA_U1 DMA_CDSA_L1 DMA_CDSA_U1 DMA_CEN1 DMA_CFN1 DMA_CSFI1 DMA_CSEI1 DMA_CSAC1 DMA_CDAC1 DMA_CDEI1 DMA_CDFI1 DMA Channel 1 Source Destination Parameters Register DMA Channel 1 Control Register DMA Channel 1 Interrupt Control register DMA Channel 1 Status register DMA Channel 1 Source Start Address, lower bits, register DMA Channel 1 Source Start Address, upper bits, register DMA Channel 1 Source Destination Address, lower bits, register DMA Channel 1 Source Destination Address, upper bits, register DMA Channel 1 Element Number register DMA Channel 1 Frame Number register DMA Channel 1 Source Frame Index register DMA Channel 1 Source Element Index register DMA Channel 1 Source Address Counter register DMA Channel 1 Destination Address Counter register DMA Channel 1 Destination Element Index register DMA Channel 1 Destination Frame Index register 0000 0000 0000 0000 0000 0000 0000 0000 00 0011 00 0000 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 0000 0000 0000 0000 0000 0000 0000 0000 00 0011 00 0000 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 000 0000 RESET VALUE PRODUCT PREVIEW 86 SPRS208 December 2002 Functional Overview Table 3-56. DMA Configuration Registers (Continued) WORD ADDRESS 0x0C40 0x0C41 0x0C42 0x0C43 0x0C44 0x0C45 0x0C46 0x0C47 0x0C48 0x0C49 0x0C4A 0x0C4B 0x0C4C 0x0C4D 0x0C4E 0x0C4F 0x0C60 0x0C61 0x0C62 0x0C63 0x0C64 0x0C65 0x0C66 0x0C67 0x0C68 0x0C69 0x0C6A 0x0C6B 0x0C6C 0x0C6D 0x0C6E 0x0C6F REGISTER NAME DMA_CSDP2 DMA_CCR2(15:0) DMA_CICR2(5:0) DMA_CSR2(6:0) DMA_CSSA_L2 DMA_CSSA_U2 DMA_CDSA_L2 DMA_CDSA_U2 DMA_CEN2 DMA_CFN2 DMA_CSFI2 DMA_CSEI2 DMA_CSAC2 DMA_CDAC2 DMA_CDEI2 DMA_CDFI2 DMA_CSDP3 DMA_CCR3(15:0) DMA_CICR3(5:0) DMA_CSR3(6:0) DMA_CSSA_L3 DMA_CSSA_U3 DMA_CDSA_L3 DMA_CDSA_U3 DMA_CEN3 DMA_CFN3 DMA_CSFI3 DMA_CSEI3 DMA_CSAC3 DMA_CDAC3 DMA_CDEI3 DMA_CDFI3 DESCRIPTION CHANNEL #2 REGISTERS DMA Channel 2 Source Destination Parameters Register DMA Channel 2 Control Register DMA Channel 2 Interrupt Control register DMA Channel 2 Status register DMA Channel 2 Source Start Address, lower bits, register DMA Channel 2 Source Start Address, upper bits, register DMA Channel 2 Source Destination Address, lower bits, register DMA Channel 2 Source Destination Address, upper bits, register DMA Channel 2 Element Number register DMA Channel 2 Frame Number register DMA Channel 2 Source Frame Index register DMA Channel 2 Source Element Index register DMA Channel 2 Source Address Counter register DMA Channel 2 Destination Address Counter register DMA Channel 2 Destination Element Index register DMA Channel 2 Destination Frame Index register CHANNEL #3 REGISTERS DMA Channel 3 Source Destination Parameters Register DMA Channel 3 Control Register DMA Channel 3 Interrupt Control register DMA Channel 3 Status register DMA Channel 3 Source Start Address, lower bits, register DMA Channel 3 Source Start Address, upper bits, register DMA Channel 3 Source Destination Address, lower bits, register DMA Channel 3 Source Destination Address, upper bits, register DMA Channel 3 Element Number register DMA Channel 3 Frame Number register DMA Channel 3 Source Frame Index register DMA Channel 3 Source Element Index register DMA Channel 3 Source Address Counter register DMA Channel 3 Destination Address Counter register DMA Channel 3 Destination Element Index register DMA Channel 3 Destination Frame Index register 0000 0000 0000 0000 0000 0000 0000 0000 00 0011 00 0000 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 0000 0000 0000 0000 0000 0000 0000 0000 00 0011 00 0000 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined RESET VALUE December 2002 SPRS208 87 PRODUCT PREVIEW Functional Overview Table 3-56. DMA Configuration Registers (Continued) WORD ADDRESS REGISTER NAME DESCRIPTION CHANNEL #4 REGISTERS 0x0C80 0x0C81 0x0C82 0x0C83 0x0C84 0x0C85 0x0C86 0x0C87 0x0C88 DMA_CSDP4 DMA_CCR4(15:0) DMA_CICR4(5:0) DMA_CSR4(6:0) DMA_CSSA_L4 DMA_CSSA_U4 DMA_CDSA_L4 DMA_CDSA_U4 DMA_CEN4 DMA_CFN4 DMA_CSFI4 DMA_CSEI4 DMA_CSAC4 DMA_CDAC4 DMA_CDEI4 DMA_CDFI4 DMA Channel 4 Source Destination Parameters Register DMA Channel 4 Control Register DMA Channel 4 Interrupt Control register DMA Channel 4 Status register DMA Channel 4 Source Start Address, lower bits, register DMA Channel 4 Source Start Address, upper bits, register DMA Channel 4 Source Destination Address, lower bits, register DMA Channel 4 Source Destination Address, upper bits, register DMA Channel 4 Element Number register DMA Channel 4 Frame Number register DMA Channel 4 Source Frame Index register DMA Channel 4 Source Element Index register DMA Channel 4 Source Address Counter register DMA Channel 4 destination Address Counter register DMA Channel 4 Destination Element Index register DMA Channel 4 Destination Frame Index register CHANNEL #5 REGISTERS 0x0CA0 0x0CA1 0x0CA2 0x0CA3 0x0CA4 0x0CA5 0x0CA6 0x0CA7 0x0CA8 0x0CA9 0x0CAA 0x0CAB 0x0CAC 0x0CAD 0x0CAE 0x0CAF DMA_CSDP5 DMA_CCR5(15:0) DMA_CICR5(5:0) DMA_CSR5(6:0) DMA_CSSA_L5 DMA_CSSA_U5 DMA_CDSA_L5 DMA_CDSA_U5 DMA_CEN5 DMA_CFN5 DMA_CSFI5 DMA_CSEI5 DMA_CSAC5 DMA_CDAC5 DMA_CDEI5 DMA_CDFI5 DMA Channel 5 Source Destination Parameters Register DMA Channel 5 Control Register DMA Channel 5 Interrupt Control register DMA Channel 5 Status register DMA Channel 5 Source Start Address, lower bits, register DMA Channel 5 Source Start Address, upper bits, register DMA Channel 5 Source Destination Address, lower bits, register DMA Channel 5 Source Destination Address, upper bits, register DMA Channel 5 Element Number register DMA Channel 5 Frame Number register DMA Channel 5 Source Frame Index register DMA Channel 5 Source Element Index register DMA Channel 5 Source Address Counter register DMA Channel 5 Destination Address Counter register DMA Channel 5 Destination Element Index register DMA Channel 5 Destination Frame Index register 0000 0000 0000 0000 0000 0000 0000 0000 00 0011 00 0000 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 0000 0000 0000 0000 0000 0000 0000 0000 00 0011 00 0000 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined RESET VALUE PRODUCT PREVIEW 0x0C89 0x0C8A 0x0C8B 0x0C8C 0x0C8D 0x0C8E 0x0C8F 88 SPRS208 December 2002 Functional Overview Table 3-57. Instruction Cache Registers WORD ADDRESS 0x1400 0x1401 0x1402 0x1403 ICGC ICFLARL ICFLARH ICWMC REGISTER NAME DESCRIPTION ICache Global Control Register ICache Flush Line Address Register Low Part ICache Flush Line Address Register High Part ICache N-Way Control Register Table 3-58. Trace FIFO WORD ADDRESS 0x2000 - 0x203F 0x2040 - 0x204F 0x2050 0x2051 0x2052 0x2053 REGISTER NAME TRC00 - TRC63 TRC64 - TRC79 TRC_LPCOFFSET1 TRC_LPCOFFSET2 TRC_PTR TRC_CNTL DESCRIPTION Trace Register Discontinuity Section Trace Register Last PC Section Trace LPC Offset Register 1 Trace LPC Offset Register 2 Trace Pointer Register Trace Control Register 0x2054 TRC_ID Trace ID Register The Trace FIFO registers are used by the emulator only and do not require any intervention from the user. Table 3-59. Timer Signal Selection Register WORD ADDRESS 0x8000 REGISTER NAME TSSR DESCRIPTION Timer Signal Selection Register RESET VALUE 0000 0000 0000 0000 Table 3-60. Timers WORD ADDRESS 0x1000 0x1001 0x1002 0x1003 0x1004 0x1005 0x1006 0x1007 0x1008 0x1009 0x100A 0x100B 0x100C 0x100D 0x100E 0x100F 0x1010 0x1011 0x1012 0x2400 0x2401 0x2402 0x2403 0x2404 0x2405 REGISTER NAME GPTPID1_0 GPTPID2_0 GPTEMU_0 GPTCLK_0 GPTGPINT_0 GPTGPEN_0 GPTGPDAT_0 GPTGPDIR_0 GPTCNT1_0 GPTCNT2_0 GPTCNT3_0 GPTCNT4_0 GPTPRD1_0 GPTPRD2_0 GPTPRD3_0 GPTPRD4_0 GPTCTL1_0 GPTCTL2_0 GPTGCTL1_0 GPTPID1_1 GPTPID2_1 GPTEMU_1 GPTCLK_1 GPTGPINT_1 GPTGPEN_1 DESCRIPTION Peripheral ID register 1, Timer #0 Peripheral ID register 2, Timer #0 Emulation Management Register, Timer #0 Timer Clock Speed Register, Timer #0 GPIO Interrupt Control Register, Timer #0 GPIO Enable Register, Timer #0 GPIO Data Register, Timer #0 GPIO Direction Register, Timer #0 Timer Counter 1 Register, Timer #0 Timer Counter 2 Register, Timer #0 Timer Counter 3 Register, Timer #0 Timer Counter 4 Register, Timer #0 Period Register 1, Timer #0 Period Register 2, Timer #0 Period Register 3, Timer #0 Period Register 4, Timer #0 Timer Control Register 1, Timer #0 Timer Control Register 2, Timer #0 Global Timer Control Register 1, Timer #0 Peripheral ID register 1, Timer #1 Peripheral ID register 2, Timer #1 Emulation Management Register, Timer #1 Timer Clock Speed Register, Timer #1 GPIO Interrupt Control Register, Timer #1 GPIO Enable Register, Timer #1 RESET VALUE 0000 0111 0000 0001 0000 0000 0000 0001 0000 0000 0000 0000 0000 0001 0000 1000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1111 1111 0000 0000 0000 0000 0000 0000 0000 0111 0000 0001 0000 0000 0000 0001 0000 0000 0000 0000 0000 0001 0000 1000 0000 0000 0000 0000 0000 0000 0000 0000 December 2002 SPRS208 89 PRODUCT PREVIEW Functional Overview Table 3-60. Timers (Continued) WORD ADDRESS 0x2406 0x2407 0x2408 0x2409 0x240A 0x240B 0x240C 0x240D 0x240E 0x240F 0x2410 0x2411 0x2412 0x4000 0x4001 0x4002 REGISTER NAME GPTGPDAT_1 GPTGPDIR_1 GPTCNT1_1 GPTCNT2_1 GPTCNT3_1 GPTCNT4_1 GPTPRD1_1 GPTPRD2_1 GPTPRD3_1 GPTPRD4_1 GPTCTL1_1 GPTCTL2_1 GPTGCTL1_1 WDTPID1 WDTPID2 WDTEMU WDTCLK WDTGPINT WDTGPEN WDTGPDAT WDTGPDIR WDTCNT1 WDTCNT2 WDTCNT3 WDTCNT4 WDTPRD1 WDTPRD2 WDTPRD3 WDTPRD4 WDTCTL1 WDTCTL2 WDTGCTL1 WDTWCTL1 WDTWCTL2 DESCRIPTION GPIO Data Register, Timer #1 GPIO Direction Register, Timer #1 Timer Counter 1 Register, Timer #1 Timer Counter 2 Register, Timer #1 Timer Counter 3 Register, Timer #1 Timer Counter 4 Register, Timer #1 Period Register 1, Timer #1 Period Register 2, Timer #1 Period Register 3, Timer #1 Period Register 4, Timer #1 Timer Control Register 1, Timer #1 Timer Control Register 2, Timer #1 Global Timer Control Register 1, Timer #1 Peripheral ID register 1, Watchdog Timer Peripheral ID register 2, Watchdog Timer Emulation Management Register, Watchdog Timer Timer Clock Speed Register, Watchdog Timer GPIO Interrupt Control Register, Watchdog Timer GPIO Enable Register, Watchdog Timer GPIO Data Register, Watchdog Timer GPIO Direction Register, Watchdog Timer Timer Counter 1 Register, Watchdog Timer Timer Counter 2 Register, Watchdog Timer Timer Counter 3 Register, Watchdog Timer Timer Counter 4 Register, Watchdog Timer Period Register 1, Watchdog Timer Period Register 2, Watchdog Timer Period Register 3, Watchdog Timer Period Register 4, Watchdog Timer Timer Control Register 1, Watchdog Timer Timer Control Register 2, Watchdog Timer Global Timer Control Register 1, Watchdog Timer WD Timer Control Register 1, Watchdog Timer WD Timer Control Register 2, Watchdog Timer RESET VALUE 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1111 1111 0000 0000 0000 0000 0000 0000 0000 0111 0000 0001 0000 0000 0000 0001 0000 0000 0000 0000 0000 0001 0000 1000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 PRODUCT PREVIEW 0x4003 0x4004 0x4005 0x4006 0x4007 0x4008 0x4009 0x400A 0x400B 0x400C 0x400D 0x400E 0x400F 0x4010 0x4011 0x4012 0x4014 0x4015 90 SPRS208 December 2002 Functional Overview Table 3-61. Multichannel Serial Port #0 WORD ADDRESS 0x2800 0x2801 0x2802 0x2803 0x2804 0x2805 0x2806 0x2807 0x2808 0x2809 0x280A 0x280B 0x280C 0x280D 0x280E 0x280F 0x2810 0x2811 0x2812 0x2813 0x2814 0x2815 0x2816 0x2817 0x2818 0x2819 0x281A 0x281B 0x281C 0x281D 0x281E 0x281F RCERC_0 RCERD_0 XCERC_0 XCERD_0 RCERE_0 RCERF_0 XCERE_0 XCERF_0 RCERG_0 RCERH_0 XCERG_0 XCERH_0 REGISTER NAME DRR1_0 DRR2_0 DXR1_0 DXR2_0 SPCR1_0 SPCR2_0 RCR1_0 RCR2_0 XCR1_0 XCR2_0 SRGR1_0 SRGR2_0 MCR1_0 MCR2_0 RCERA_0 RCERB_0 XCERA_0 XCERB_0 PCR0 DESCRIPTION Data Receive Register 1, McBSP #0 Data Receive Register 2, McBSP #0 Data Transmit Register 1, McBSP #0 Data Transmit Register 2, McBSP #0 Serial Port Control Register 1, McBSP #0 Serial Port Control Register 2, McBSP #0 Receive Control Register 1, McBSP #0 Receive Control Register 2, McBSP #0 Transmit Control Register 1, McBSP #0 Transmit Control Register 2, McBSP #0 Sample Rate Generator Register 1, McBSP #0 Sample Rate Generator Register 2, McBSP #0 Multichannel Control Register 1, McBSP #0 Multichannel Control Register 2, McBSP #0 Receive Channel Enable Register Partition A, McBSP #0 Receive Channel Enable Register Partition B, McBSP #0 Transmit Channel Enable Register Partition A, McBSP #0 Transmit Channel Enable Register Partition B, McBSP #0 Pin Control Register, McBSP #0 Reserved Receive Channel Enable Register Partition C, McBSP #0 Receive Channel Enable Register Partition D, McBSP #0 Transmit Channel Enable Register Partition C, McBSP #0 Transmit Channel Enable Register Partition D, McBSP #0 Receive Channel Enable Register Partition E, McBSP #0 Receive Channel Enable Register Partition F, McBSP #0 Transmit Channel Enable Register Partition E, McBSP #0 Transmit Channel Enable Register Partition F, McBSP #0 Receive Channel Enable Register Partition G, McBSP #0 Receive Channel Enable Register Partition H, McBSP #0 Transmit Channel Enable Register Partition G, McBSP #0 Transmit Channel Enable Register Partition H, McBSP #0 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 RESET VALUE 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0020 0000 0000 0000 0000 0000 0000 0001 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 December 2002 SPRS208 91 PRODUCT PREVIEW 0000 0000 0000 0000 Functional Overview Table 3-62. Multichannel Serial Port #1 WORD ADDRESS 0x2C00 0x2C01 0x2C02 0x2C03 0x2C04 0x2C05 0x2C06 0x2C07 0x2C08 0x2C09 0x2C0A 0x2C0B 0x2C0C 0x2C0D 0x2C0E 0x2C0F 0x2C10 0x2C11 0x2C12 0x2C13 0x2C14 0x2C15 0x2C16 0x2C17 0x2C18 0x2C19 0x2C1A 0x2C1B 0x2C1C 0x2C1D 0x2C1E 0x2C1F RCERC_1 RCERD_1 XCERC_1 XCERD_1 RCERE_1 RCERF_1 XCERE_1 XCERF_1 RCERG_1 RCERH_1 XCERG_1 XCERH_1 REGISTER NAME DRR1_1 DRR2_1 DXR1_1 DXR2_1 SPCR1_1 SPCR2_1 RCR1_1 RCR2_1 XCR1_1 XCR2_1 SRGR1_1 SRGR2_1 MCR1_1 MCR2_1 RCERA_1 RCERB_1 XCERA_1 XCERB_1 PCR1 DESCRIPTION Data Receive Register 1, McBSP #1 Data Receive Register 2, McBSP #1 Data Transmit Register 1, McBSP #1 Data Transmit Register 2, McBSP #1 Serial Port Control Register 1, McBSP #1 Serial Port Control Register 2, McBSP #1 Receive Control Register 1, McBSP #1 Receive Control Register 2, McBSP #1 Transmit Control Register 1, McBSP #1 Transmit Control Register 2, McBSP #1 Sample Rate Generator Register 1, McBSP #1 Sample Rate Generator Register 2, McBSP #1 Multichannel Register 1, McBSP #1 Multichannel Register 2, McBSP #1 Receive Channel Enable Register Partition A, McBSP #1 Receive Channel Enable Register Partition B, McBSP #1 Transmit Channel Enable Register Partition A, McBSP #1 Transmit Channel Enable Register Partition B, McBSP #1 Pin Control Register, McBSP #1 Reserved Receive Channel Enable Register Partition C, McBSP #1 Receive Channel Enable Register Partition D, McBSP #1 Transmit Channel Enable Register Partition C, McBSP #1 Transmit Channel Enable Register Partition D, McBSP #1 Receive Channel Enable Register Partition E, McBSP #1 Receive Channel Enable Register Partition F, McBSP #1 Transmit Channel Enable Register Partition E, McBSP #1 Transmit Channel Enable Register Partition F, McBSP #1 Receive Channel Enable Register Partition G, McBSP #1 Receive Channel Enable Register Partition H, McBSP #1 Transmit Channel Enable Register Partition G, McBSP #1 Transmit Channel Enable Register Partition H, McBSP #1 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 RESET VALUE 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0020 0000 0000 0000 0000 0000 0000 0001 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 PRODUCT PREVIEW 92 SPRS208 December 2002 Functional Overview Table 3-63. Multichannel Serial Port #2 WORD ADDRESS 0x3000 0x3001 0x3002 0x3003 0x3004 0x3005 0x3006 0x3007 0x3008 0x3009 0x300A 0x300B 0x300C 0x300D 0x300E 0x300F 0x3010 0x3011 0x3012 0x3013 0x3014 0x3015 0x3016 0x3017 0x3018 0x3019 0x301A 0x301B 0x301C 0x301D 0x301E 0x301F RCERC_2 RCERD_2 XCERC_2 XCERD_2 RCERE_2 RCERF_2 XCERE_2 XCERF_2 RCERG_2 RCERH_2 XCERG_2 XCERH_2 REGISTER NAME DRR1_2 DRR2_2 DXR1_2 DXR2_2 SPCR1_2 SPCR2_2 RCR1_2 RCR2_2 XCR1_2 XCR2_2 SRGR1_2 SRGR2_2 MCR1_2 MCR2_2 RCERA_2 RCERB_2 XCERA_2 XCERB_2 PCR2 DESCRIPTION Data Receive Register 1, McBSP #2 Data Receive Register 2, McBSP #2 Data Transmit Register 1, McBSP #2 Data Transmit Register 2, McBSP #2 Serial Port Control Register 1, McBSP #2 Serial Port Control Register 2, McBSP #2 Receive Control Register 1, McBSP #2 Receive Control Register 2, McBSP #2 Transmit Control Register 1, McBSP #2 Transmit Control Register 2, McBSP #2 Sample Rate Generator Register 1, McBSP #2 Sample Rate Generator Register 2, McBSP #2 Multichannel Register 1, McBSP #2 Multichannel Register 2, McBSP #2 Receive Channel Enable Register Partition A, McBSP #2 Receive Channel Enable Register Partition B, McBSP #2 Transmit Channel Enable Register Partition A, McBSP #2 Transmit Channel Enable Register Partition B, McBSP #2 Pin Control Register, McBSP #2 Reserved Receive Channel Enable Register Partition C, McBSP #2 Receive Channel Enable Register Partition D, McBSP #2 Transmit Channel Enable Register Partition C, McBSP #2 Transmit Channel Enable Register Partition D, McBSP #2 Receive Channel Enable Register Partition E, McBSP #2 Receive Channel Enable Register Partition F, McBSP #2 Transmit Channel Enable Register Partition E, McBSP #2 Transmit Channel Enable Register Partition F, McBSP #2 Receive Channel Enable Register Partition G, McBSP #2 Receive Channel Enable Register Partition H, McBSP #2 Transmit Channel Enable Register Partition G, McBSP #2 Transmit Channel Enable Register Partition H, McBSP #2 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 RESET VALUE 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0020 0000 0000 0000 0000 0000 0000 0001 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 December 2002 SPRS208 93 PRODUCT PREVIEW Functional Overview Table 3-64. HPI WORD ADDRESS 0xA000 0xA001 0xA002 0xA003 - 0xA005 0xA006 0xA007 0xA008 0xA009 0xA00A 0xA00B - 0xA017 0xA018 0xA019 0xA01A 0xA01B 0xA01C 0xA01D - 0xA020 x denotes a "don't care." HPIAW HPIAR HPIC GPIODAT HGPIODIR HGPIOEN REGISTER NAME PID LSW PID MSW PWREMU_MGMT1 PID [15:0] PID [31:16] Power and Management Register 1 Reserved HPI GPIO enable register Reserved HPI GPIO direction register Reserved GPIO data register Reserved Host Port Control Register Reserved Host Port Write Address Register Reserved Host Port Read Address Register Reserved xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 1000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 DESCRIPTION RESET VALUE 0000 0010 0000 0000 0000 0001 0000 0000 0000 0000 PRODUCT PREVIEW Table 3-65. GPIO WORD ADDRESS 0x3400 0x3401 0x4400 0x4401 0x4402 0x4403 0x4404 0x4405 0x4406 0x4407 0x4408 REGISTER NAME IODIR IODATA PGPIOEN0 PGPIODIR0 PGPIODAT0 PGPIOEN1 PGPIODIR1 PGPIODAT1 PGPIOEN2 PGPIODIR2 PGPIODAT2 DESCRIPTION General-purpose I/O Direction Register General-purpose I/O Data Register Parallel GPIO Enable Register 0 Parallel GPIO Direction Register 0 Parallel GPIO Data Register 0 Parallel GPIO Enable Register 1 Parallel GPIO Direction Register 1 Parallel GPIO Data Register 1 Parallel GPIO Enable Register 2 Parallel GPIO Direction Register 2 Parallel GPIO Data Register 2 RESET VALUE 0000 0000 0000 0000 0000 0000 xxxx xxxx 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 x denotes a "don't care." Table 3-66. Device Revision ID WORD ADDRESS 0x3800 - 0x3803 0x3804 0x3805 0x3806 0x3807 REGISTER NAME Die ID Chip ID (LSW) Chip ID (MSW) Sub ID Cat ID Die ID Defines F# 3LS digits and PG rev Defines F# 3MS digits Defines subsytem ID Defines catalog device xxxx xxxx xxxx 0001 0000 xxxx xxxx xxxx 0000 0000 0000 0000 0101 0101 0000 0010 (5502h) DESCRIPTION RESET VALUE x denotes a "don't care." Denotes single core 94 SPRS208 December 2002 Functional Overview Table 3-67. I2C WORD ADDRESS 0x3C00 0x3C01 0x3C02 0x3C03 0x3C04 0x3C05 0x3C06 0x3C07 0x3C08 0x3C09 0x3C0A 0x3C0B 0x3C0C 0x3C0D 0x3C0E - REGISTER NAME I2COAR I2CIER I2CSTR I2CCLKL I2CCLKH I2CCNT I2CDRR I2CSAR I2CDXR I2CMDR I2CISRC I2CGPIO I2CPSC PID1 PID2 I2CXSR DESCRIPTION I2C Own Address Register I2C Interrupt Enable Register I2C Status Register I2C Clock Low-Time Divider Register I2C Clock High-Time Divider Register I2C Data Count I2C Data Receive Register I2C Slave Address Register I2C Data Transmit Register I2C Mode Register I2C Interrupt Source Register I2C General-Purpose Register (Not supported) I2C Prescaler Register I2C Peripheral ID Register 1 I2C Peripheral ID Register 2 I2C Transmit Shift Register I2C Receive Shift Register RESET VALUE 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0011 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 xxxx xxxx xxxx xxxx 0000 0000 0000 0000 - - - - I2CRSR x denotes a "don't care." December 2002 SPRS208 95 PRODUCT PREVIEW - Functional Overview Table 3-68. UART WORD ADDRESS 0x9C00 REGISTER NAME URRBR/ URTHR/ URDLL URIER/ URDLM URIIR/ URFCR URLCR URMCR URLSR URSCR URDLL URDLM URPID1 URPID2 URPECR DESCRIPTION Receive Buffer Register Transmit Holding Register Divisor Latch LSB Register Interrupt Enable Register Divisor Latch MSB Register Interrupt Identification Register FIFO Control Register Line Control Register Modem Control Register Line Status Register Scratch Register Divisor Latch LSB Register Divisor Latch MSB Register Peripheral ID Register (LSW) Peripheral ID Register (MSW) Power and Emulation Control Register RESET VALUE xxxx xxxx 0x9C01 0x9C02 0x9C03 0x9C04 0x9C05 0x9C07 0x9C08 0x9C09 0x9C0A 0x9C0B 0x9C0C 0000 0000 0000 0001 0000 0000 0000 0000 0000 0000 0110 0000 xxxx xxxx - - - - 0000 0000 0000 0000 PRODUCT PREVIEW x denotes a "don't care." The registers URRBR, URTHR, and URDLL share one address. URDLL also has a dedicated address. When using the dedicated address, the DLAB bit can be kept cleared, so that URRBR and URTHR are always selected at the shared address. If DLAB = 0 : Read Only: URRBR Write Only: URTHR If DLAB = 1: Read/Write: URDLL The registers URIER and URDLM share one address. URDLM also has a dedicated address. When using the dedicated address, the DLAB bit can be kept cleared, so that URIER is always selected at the shared address. If DLAB = 0: Read/WRite: URIER If DLAB = 1: Read/Write: URDLM The registers URIIR and URFCR share one address. Read Only: URIIR Write Only: URFCR Table 3-69. External Bus Selection WORD ADDRESS 0x6C00 0x6C01 REGISTER NAME XBSR XBCR DESCRIPTION External Bus Selection Register External Bus Control Register RESET VALUE 0000 0000 0000 0000 0000 0000 0000 0000 Table 3-70. Clock Mode Register WORD ADDRESS 0x8C00 REGISTER NAME CLKMD DESCRIPTION Clock Mode Control Register RESET VALUE 0000 0000 0000 0000 Table 3-71. CLKOUT Selector Register WORD ADDRESS 0x8400 REGISTER NAME CLKOUTSR DESCRIPTION CLKOUT Selection Register RESET VALUE 0000 0000 0000 0010 96 SPRS208 December 2002 Functional Overview Table 3-72. Clock Controller Registers WORD ADDRESS 0x1C80 0x1C82 0x1C88 0x1C8A 0x1C8C 0x1C8E 0x1C90 0x1C92 0x1C98 REGISTER NAME PLLCSR CK3SEL PLLM PLLDIV0 PLLDIV1 PLLDIV2 PLLDIV3 OSCDIV1 WKEN DESCRIPTION PLL Control Status Register CLKOUT3 Select Register PLL Multiplier Control Register PLL Divider 0 Register PLL Divider 1 Register PLL Divider 2 Register PLL Divider 3 Register Oscillator Divider 1 Register Oscillator Wakeup Control Register RESET VALUE 0000 0000 0000 0000 0000 0000 0000 1011 0000 0000 0000 0000 1000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 Table 3-73. IDLE Control Registers WORD ADDRESS 0x9400 0x9401 0x9402 0x9403 REGISTER NAME PICR PISTR MICR MISR DESCRIPTION Peripheral IDLE Control Register Peripheral IDLE Status Register Master IDLE Control Register Master IDLE Status Register RESET VALUE 0000 0000 0000 0000 0000 0000 0000 0010 0000 0000 0000 0000 0000 0000 0000 0010 December 2002 SPRS208 97 PRODUCT PREVIEW Functional Overview 3.16 Interrupts Vector-relative locations and priorities for all internal and external interrupts are shown in Table 3-74. For more information on setting up and using interrupts, please refer to the TMS320C55x DSP CPU Reference Guide (literature number SPRU371). Table 3-74. Interrupt Table NAME RESET NMI INT0 INT2 TINT0 RINT0 RINT1 XINT1 LCKINT DMAC1 DSPINT INT3/WDTINT RINT2 XINT2 DMAC4 DMAC5 INT1 XINT0 DMAC0 - DMAC2 DMAC3 TINT1 IIC BERR DLOG RTOS - - - - SOFTWARE (TRAP) EQUIVALENT SINT0 SINT1 SINT2 SINT3 SINT4 SINT5 SINT6 SINT7 SINT8 SINT9 SINT10 SINT11 SINT12 SINT13 SINT14 SINT15 SINT16 SINT17 SINT18 SINT19 SINT20 SINT21 SINT22 SINT23 SINT24 SINT25 SINT26 SINT27 SINT28 SINT29 SINT30 LOCATION (HEX BYTES) 0 8 10 18 20 28 30 38 40 48 50 58 60 68 70 78 80 88 90 98 A0 A8 B0 B8 C0 C8 D0 D8 E0 E8 F0 PRIORITY 0 1 3 5 6 7 9 10 11 13 14 15 17 18 21 22 4 8 12 16 19 20 23 24 2 25 26 27 28 29 30 FUNCTION Reset (hardware and software) Nonmaskable interrupt External interrupt #0 External interrupt #2 Timer #0 interrupt McBSP #0 receive interrupt McBSP #1 receive interrupt McBSP #1 transmit interrupt PLL lock interrupt DMA Channel #1 interrupt Interrupt from host External interrupt #3 or Watchdog timer interrupt McBSP #2 receive interrupt McBSP #2 transmit interrupt DMA Channel #4 interrupt DMA Channel #5 interrupt External interrupt #1 McBSP #0 transmit interrupt DMA Channel #0 interrupt Software interrupt #19 DMA Channel #2 interrupt DMA Channel #3 interrupt Timer #1 interrupt I2C interrupt Bus Error interrupt Data Log interrupt Real-time Operating System interrupt Software interrupt #27 Software interrupt #28 Software interrupt #29 Software interrupt #30 PRODUCT PREVIEW SINT31 F8 31 Software interrupt #31 WDTINT is only available when the Watchdog Timer is used as a general-purpose timer. 98 SPRS208 December 2002 Functional Overview 3.16.1 IFR and IER Registers The Interrupt Enable Registers (IER0 and IER1) control which interrupts will be masked or enabled during normal operation. The Interrupt Flag Registers (IFR0 and IFR1) contain flags that indicate interrupts that are currently pending. The Debug Interrupt Enable Registers (DBIER0 and DBIER1) are used only when the CPU is halted in the real-time emulation mode. If the CPU is running in real-time mode, the standard interrupt processing (IER0/1) is used and DBIER0/1 are ignored. A maskable interrupt enabled in DBIER0/1 is defined as a time-critical interrupt. When the CPU is halted in the real-time mode, the only interrupts that are serviced are time-critical interrupts that are also enabled in an interrupt enable register (IER0 or IER1). Write the DBIER0/1 to enable or disable time-critical interrupts. To enable an interrupt, set its corresponding bit. To disable an interrupt, clear its corresponding bit. Initialize these registers before using the real-time emulation mode. A DSP hardware reset clears IFR0/1, IER0/1, and DBIER0/1 to 0. A software reset instruction clears IFR0/1 to 0 but does not affect IER0/1 and DBIER0/1. The bit layouts of these registers for each interrupt are shown in Figure 3-48 and Figure 3-49. For more information on the IER, IFR, and DBIER registers, refer to the TMS320C55x DSP CPU Reference Guide (literature number SPRU371). 15 DMAC5 R/W, 0 14 DMAC4 R/W, 0 13 XINT2 R/W, 0 12 RINT2/ UART R/W, 0 11 INT3/ WDTINT R/W, 0 10 DSPINT R/W, 0 9 DMAC1 R/W, 0 8 Reserved R/W, 0 7 XINT1 R/W, 0 6 RINT1 R/W, 0 5 RINT0 R/W, 0 4 TINT0 R/W, 0 3 INT2 R/W, 0 2 INT0 R/W, 0 1 Reserved R, 0 0 LEGEND: R = Read, W = Write, n = value at reset Figure 3-48. IFR0, IER0, DBIFR0, and DBIER0 Registers Layout 15 Reserved R, 0 11 10 RTOS R/W, 0 9 DLOG R/W, 0 8 BERR R/W, 0 7 I2C R/W, 0 6 TINT1 R/W, 0 5 DMAC3 R/W, 0 4 DMAC2 R/W, 0 3 INT4 R/W, 0 2 DMAC0 R/W, 0 1 XINT0 R/W, 0 0 INT1 R/W, 0 LEGEND: R = Read, W = Write, n = value at reset Figure 3-49. IFR1, IER1, DBIFR1, and DBIER1 Registers Layout December 2002 SPRS208 99 PRODUCT PREVIEW Functional Overview 3.16.2 Interrupt Timing The external interrupts (NMI and INT) are synchronized to the CPU by way of a two-flip-flop synchronizer. The interrupt inputs are sampled on falling edges of the CPU clock. A sequence on the interrupt pin of 1-0-0-0 on consecutive cycles is required for an interrupt to be detected. Therefore, the minimum low pulse duration on the external interrupts on the 5502 is three CPU clock periods. PRODUCT PREVIEW 100 SPRS208 December 2002 Documentation Support 4 Documentation Support Extensive documentation supports all TMS320 DSP family of devices from product announcement through applications development. The following types of documentation are available to support the design and use of the TMS320C5000 platform of DSPs: * * * * * TMS320C55x DSP Functional Overview (literature number SPRU312) Device-specific data sheets Complete user's guides Development support tools Hardware and software application reports TMS320C55x reference documentation that includes, but is not limited to, the following: * * * * * TMS320C55x DSP CPU Reference Guide (literature number SPRU371) TMS320C55x DSP Mnemonic Instruction Set Reference Guide (literature number SPRU374) TMS320C55x DSP Algebraic Instruction Set Reference Guide (literature number SPRU375) TMS320C55x DSP Programmer's Guide (literature number SPRU376) TMS320C55x DSP Peripherals Reference Guide (literature number SPRU317) A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support digital signal processing research and education. The TMS320 DSP newsletter, Details on Signal Processing, is published quarterly and distributed to update TMS320 DSP customers on product information. Information regarding TI DSP products is also available on the Worldwide Web at http://www.ti.com uniform resource locator (URL). TMS320 and TMS320C5000 are trademarks of Texas Instruments. 101 December 2002 SPRS208 PRODUCT PREVIEW The reference guides describe in detail the TMS320C55x DSP products currently available and the hardware and software applications, including algorithms, for fixed-point TMS320 DSP family of devices. Device and Development-Support Tool Nomenclature 5 Device and Development-Support Tool Nomenclature To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all TMS320 DSP devices and support tools. Each TMS320 DSP commercial family member has one of three prefixes: TMX, TMP, or TMS. Texas Instruments recommends two of three possible prefix designators for support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMX / TMDX) through fully qualified production devices/tools (TMS / TMDS). Device development evolutionary flow: TMX TMP TMS Experimental device that is not necessarily representative of the final device's electrical specifications Final silicon die that conforms to the device's electrical specifications but has not completed quality and reliability verification Fully qualified production device Support tool development evolutionary flow: PRODUCT PREVIEW TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing. TMDS Fully qualified development-support product TMX and TMP devices and TMDX development-support tools are shipped with appropriate disclaimers describing their limitations and intended uses. Experimental devices (TMX) may not be representative of a final product and Texas Instruments reserves the right to change or discontinue these products without notice. TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies. Predictions show that prototype devices ( TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used. 102 SPRS208 December 2002 Electrical Specifications 6 Electrical Specifications This section provides the absolute maximum ratings and the recommended operating conditions for the TMS320VC5502 DSP. All electrical and switching characteristics in this data manual are valid over the recommended operating conditions unless otherwise specified. 6.1 Absolute Maximum Ratings The list of absolute maximum ratings are specified over operating case temperature. Stresses beyond those listed under Section 6.2, Electrical Specifications, may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Section 6.3, Recommended Operating Conditions, is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All supply voltage values (core and I/O) are with respect to VSS. Figure 6-1 provides the test load circuit values for a 3.3-V device. Measured timing information contained in this data manual is based on the test load setup and conditions shown in Figure 6-1. This section provides the absolute maximum ratings for the TMS320VC5502 DSP. Supply voltage I/O range, DVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 4.0 V Supply voltage core range, CVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 2.0 V Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 4.5 V Output voltage range, Vo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 4.5 V Operating case temperature range, TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to 85C Storage temperature range Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 55_C to 150_C 6.3 Recommended Operating Conditions This section provides the recommended operating conditions for the TMS320VC5502 DSP. MIN NOM 3.3 1.26 3.3 0 Hysteresis inputs DVDD = 2.7 - 3.6 V All other inputs Hysteresis inputs DVDD = 2.7 - 3.6 V All other inputs All outputs All outputs -40 2.2 2 -0.3 -0.3 DVDD + 0.3 DVDD + 0.3 0.8 V 0.8 - 300 1.5 85 A mA C MAX 3.6 1.32 3.6 UNIT V V V V DVDD CVDD PVDD VSS VIH Device supply voltage, I/O Device supply voltage, core Device supply voltage, PLL Supply voltage, GND 2.7 1.20 2.7 High level input High-level in ut voltage, I/O V VIL IOH IOL TC Low-level in ut voltage, I/O Low level input High-level output current Low-level output current Operating case temperature December 2002 SPRS208 103 PRODUCT PREVIEW 6.2 Electrical Specifications Electrical Specifications 6.4 Electrical Characteristics Over Recommended Operating Case Temperature Range (Unless Otherwise Noted) PARAMETER TEST CONDITIONS DVDD = 2.7 - 3.0 V, IOH = MAX DVDD = 3.3 0.3 V, IOH = MAX IOL = MAX Bus holders enabled DVDD = MAX, VO = VSS to DVDD DVDD = MAX, -0.3 V < VI < 4.5 V DVDD = MAX, -0.3 V < VI < 4.5 V DVDD = MAX, -0.3 V < VI < 4.5 V DVDD = MAX, -0.3 V < VI < 4.5 V Pullup enabled DVDD = MAX, -0.3 V < VI < 4.5 V DVDD = MAX, -0.3 V < VI < 4.5 V CVDD = Nominal CPU clock = 300 MHz TC = 25C DVDD = Nominal CPU clock = 300 MHz TC = 25C PVDD = Nominal 30-MHz clock input, APLL mode = x10 TC = 25C CVDD = Nominal input clock stopped DVDD = Nominal no pin activity TC = 25C 25C 85C MIN 2.2 V 2.4 0.4 - 300 300 A -5 -5 TBD TBD 5 300 TBD TBD A V TYP MAX UNIT VOH High level output voltage High-level VOL Low-level output voltage Output-only or input/output pins with bus holders All other output-only or input/output pins Input pins with internal pulldown X2/CLKIN with oscillator on X2/CLKIN with oscillator off IIZ Input current for outputs in high impedance PRODUCT PREVIEW II Input current Input pins with internal pullup - 300 5 All other input-only pins CVDD supply current, CPU + internal memory access -5 5 IDDC TBD mA IDDD DVDD supply current, pins active TBD mA IDDP PVDD supply current, standby Only CLKGEN domain enabled, PLL enabled CVDD supply current, standby su ly All domains idled DVDD supply current, standby All domains idled Input capacitance TBD mA TBD TBD TBD 3 mA A pF IDDC IDDD Ci Co Output capacitance 3 pF Test Condition: CPU executing 75% Dual-MAC / 25% ADD with moderate data bus activity (table of sine values). CPU and CLKGEN domains are active. All other domains are idled. The APLL is enabled. Test Condition: One word of a table of 16-bit sine values is written to the EMIF each microsecond (16 Mbps). Each EMIF output pin is connected to a 10-pF load capacitance. 104 SPRS208 December 2002 Electrical Specifications IOL-test 50 Tester Pin Electronics VLoad CT Output Under Test IOH-test Where: IOL-test IOH-test VLoad CT = = = = 1.5 mA (all outputs) 300 A (all outputs) 1.8 V 15 pF typical load circuit capacitance Figure 6-1. 3.3-V Test Load Circuit 6.5 Package Thermal Resistance Characteristics Table 6-1 provide the thermal resistance characteristics for the recommended package types used on the TMS320VC5502 DSP. Table 6-1. Thermal Resistance Characteristics PARAMETER RJC GGW PACKAGE TBD PGF PACKAGE TBD UNIT C/W BOARD TYPE 2s JEDEC Test Card Board types are as defined by JEDEC. Reference JEDEC Standard JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements. 6.6 Timing Parameter Symbology Timing parameter symbols used in the timing requirements and switching characteristics tables are created in accordance with JEDEC Standard 100. To shorten the symbols, some of the pin names and other related terminology have been abbreviated as follows: Lowercase subscripts and their meanings: a c d dis en f h r su t v w X access time cycle time (period) delay time disable time enable time fall time hold time rise time setup time transition time valid time pulse duration (width) Unknown, changing, or don't care level Letters and symbols and their meanings: H L V Z High Low Valid High impedance December 2002 SPRS208 105 PRODUCT PREVIEW Electrical Specifications 6.7 Clock Options This section provides the timing requirements and switching characteristics for the various clock options available on the 5502. 6.7.1 Clock Generation in Bypass Mode (APLL Disabled) Table 6-2 and Table 6-3 assume testing over recommended operating conditions and H = 0.5tc(CO) (see Figure 6-2). Table 6-2. CLKIN in Bypass Mode Timing Requirements NO. C7 C8 C9 tc(CI) tf(CI) Cycle time, CLKIN Fall time, CLKIN MIN 3.33 MAX 6 UNIT ns ns tr(CI) Rise time, CLKIN 6 ns This device utilizes a fully static design and therefore can operate with tc(CI) approaching . The device is characterized at frequencies approaching 0 Hz. Table 6-3. CLKOUT in Bypass Mode Switching Characteristics PRODUCT PREVIEW NO. C1 C2 C3 C4 C5 C6 tc(CO) td(CIH-CO) tf(CO) tr(CO) tw(COL) tw(COH) Cycle time, CLKOUT PARAMETER MIN 3.33 1 TYP tc(CI) 2 1 1 MAX 4 UNIT ns ns ns ns Delay time, CLKIN high to CLKOUT high/low Fall time, CLKOUT Rise time, CLKOUT Pulse duration, CLKOUT low Pulse duration, CLKOUT high H-1 H-1 H H H+1 H+1 ns ns This device utilizes a fully static design and therefore can operate with tc(CI) approaching . The device is characterized at frequencies approaching 0 Hz. It is recommended that the lock mode (APLL synthesis enabled) clocking option be used for maximum frequency operation. C9 C7 CLKIN C8 C1 C2 CLKOUT C3 C4 C6 C5 NOTE: The relationship of CLKIN to CLKOUT depends on the divide factor chosen. The waveform relationship shown in Figure 6-2 is intended to illustrate the timing parameters only and may differ based on configuration. Figure 6-2. Bypass Mode Clock Timing 106 SPRS208 December 2002 Electrical Specifications 6.7.2 Clock Generation in PLL Mode The frequency of the reference clock provided at the CLKIN pin can be multiplied by a synthesis factor of N to generate the internal CPU clock cycle. The synthesis factor is determined by: N+ M D0 where: M = D0 = the multiply factor set in the PLLM field of the PLL Multiplier Control Register (PLLM) the divide factor set in the PLLDIV0 field of the PLL Divider 0 Register (PLLDIV0) Valid values for M are (multiply by) 1 to 16. Valid values for D0 are (divide by) 1 - 32. For detailed information on clock generation configuration, see the TMS320C55x DSP Peripherals Reference Guide (literature number SPRU317). Table 6-4 and Table 6-5 assume testing over recommended operating conditions and H = 0.5tc(CO) (see Figure 6-3). Table 6-4. CLKIN in Lock Mode Timing Requirements NO. Oscillator disabled C7 C8 C9 tc(CI) tf(CI) tr(CI) Cycle time, CLKIN time Fall time, CLKIN Rise time, CLKIN APLL synthesis enabled Oscillator enabled MIN 40 50 MAX 400 200 6 6 UNIT ns ns ns ns The clock frequency synthesis factor and minimum CLKIN cycle time should be chosen such that the resulting CLKOUT cycle time is within the specified range [tc(CO)]. Table 6-5. CLKOUT in Lock Mode Switching Characteristics NO. C1 C2 C3 C4 C5 C6 tc(CO) td(CI-CO) tf(CO) tr(CO) tw(COL) tw(COH) PARAMETER Cycle time, CLKOUT Delay time, CLKIN high/low to CLKOUT high/low Fall time, CLKOUT Rise time, CLKOUT Pulse duration, CLKOUT low Pulse duration, CLKOUT high H-1 H-1 MIN 3.33 1 TYP tc(CI)/N 2 1 1 H H H+1 H+1 MAX 4 UNIT ns ns ns ns ns ns N = Clock frequency synthesis factor C8 C9 C7 CLKIN C2 C1 CLKOUT C6 C3 C5 C4 Bypass Mode NOTE: The waveform relationship of CLKIN to CLKOUT depends on the multiply and divide factors chosen. The waveform relationship shown in Figure 6-3 is intended to illustrate the timing parameters only and may differ based on configuration. Figure 6-3. External Multiply-by-N Clock Timing December 2002 SPRS208 107 PRODUCT PREVIEW Electrical Specifications 6.7.3 EMIF Clock Options Table 6-6 through Table 6-8 assume testing over recommended operating conditions (see Figure 6-4 through Figure 6-6). Table 6-6. EMIF Timing Requirements for ECLKIN NO. E1 E2 E3 tc(EKI) tw(EKIH) tw(EKIL) tt(EKI) Cycle time, ECLKIN Pulse duration, ECLKIN high Pulse duration, ECLKIN low MIN 10 3.38 3.38 2 MAX 16P UNIT ns ns ns ns E4 Transition time, ECLKIN P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns. The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN. Table 6-7. EMIF Switching Characteristics for ECLKOUT1# NO. E11 E22 E33 tc(EKO1) tw(EKO1H) tw(EKO1L) tt(EKO1) PARAMETER Cycle time, ECLKOUT1 Pulse duration, ECLKOUT1 high Pulse duration, ECLKOUT1 low Transition time, ECLKOUT1 MIN E - 0.7 EH - 0.7 EL - 0.7 MAX E + 0.7 EH + 0.7 EL + 0.7 1 UNIT ns ns ns ns ns ns PRODUCT PREVIEW E44 E55 td(EKIH-EKO1H) Delay time, ECLKIN high to ECLKOUT1 high 3 8 E66 td(EKIL-EKO1L) Delay time, ECLKIN low to ECLKOUT1 low 3 8 The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN. E = the EMIF input clock (CPU clock, CPU/2 clock, or CPU/4 clock) period in ns for EMIF. # EH is the high period of E (EMIF input clock period) in ns and EL is the low period of E (EMIF input clock period) in ns for EMIF. E1 E2 ECLKIN E3 E4 E4 Figure 6-4. ECLKIN Timing for EMIF ECLKIN E66 E55 ECLKOUT1 E11 E22 E33 E44 E44 Figure 6-5. ECLKOUT1 Timing for EMIF Module 108 SPRS208 December 2002 Electrical Specifications Table 6-8. EMIF Switching Characteristics for ECLKOUT2 NO. E1 E2 E3 E4 E5 tc(EKO2) tw(EKO2H) tw(EKO2L) tt(EKO2) td(EKIH-EKO2H) td(EKIH-EKO2L) PARAMETER Cycle time, ECLKOUT2 Pulse duration, ECLKOUT2 high Pulse duration, ECLKOUT2 low Transition time, ECLKOUT2 Delay time, ECLKIN high to ECLKOUT2 high 3 3 MIN NE - 0.7 0.5NE - 0.7 0.5NE - 0.7 MAX NE + 0.7 0.5NE + 0.7 0.5NE + 0.7 1 8 8 UNIT ns ns ns ns ns ns E6 Delay time, ECLKIN high to ECLKOUT2 low The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN. E = the EMIF input clock (CPU clock, CPU/2 clock, or CPU/4 clock) period in ns for EMIF. N = the EMIF input clock divider; N = 1, 2, or 4. E5 E6 ECLKIN E1 E2 E3 ECLKOUT2 E4 E4 Figure 6-6. ECLKOUT2 Timing for the EMIF Module December 2002 SPRS208 109 PRODUCT PREVIEW Electrical Specifications 6.8 EMIF Asynchronous Memory Timing Table 6-9 and Table 6-10 assume testing over recommended operating conditions (see Figure 6-7 and Figure 6-8). Table 6-9. EMIF Asynchronous Memory Cycle Timing Requirements for ECLKIN NO. E3 E4 E6 tsu(EDV-AREH) th(AREH-EDV) tsu(ARDY-EKO1H) th(EKO1H-ARDY) Setup time, Dx valid before ARE high Hold time, Dx valid after ARE high Setup time, ARDY valid before ECLKOUT1 high MIN 6 1 3 MAX UNIT ns ns ns E7 Hold time, ARDY valid after ECLKOUT1 high 1 ns To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. The ARDY signal is recognized in the cycle for which the setup and hold time is met. To use ARDY as an asynchronous input, the pulse width of the ARDY signal should be wide enough (e.g., pulse width = 2E) to ensure setup and hold time is met. RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are programmed via the EMIF CE space control registers. Table 6-10. EMIF Asynchronous Memory Cycle Switching Characteristics for ECLKOUT1 NO. PARAMETER tosu(SELV-AREL) toh(AREH-SELIV) td(EKO1H-AREV) tosu(SELV-AWEL) toh(AWEH-SELIV) td(EKO1H-AWEV) Output setup time, select signals valid to ARE low Output hold time, ARE high to select signals invalid Delay time, ECLKOUT1 high to ARE valid Output setup time, select signals valid to AWE low Output hold time, AWE high to select signals invalid MIN RS * E - 1.5 RH * E - 1.5 1.5 WS * E - 1.5 WH * E - 1.5 5 MAX UNIT ns ns ns ns ns E1 E2 E5 E8 E9 PRODUCT PREVIEW E10 Delay time, ECLKOUT1 high to AWE valid 1.5 5 ns RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are programmed via the EMIF CE space control registers. E = ECLKOUT1 period in ns for EMIF. Select signals for EMIF include: CEx, BE[3:0], A[21:2], and AOE; and for EMIF writes, include D[31:0]. 110 SPRS208 December 2002 Electrical Specifications Setup = 2 ECLKOUT1 E1 CEx E1 BE[3:0] E1 A[21:2] Address E3 E4 D[31:0] E1 AOE/SOE/SDRAS E5 ARE/SADS/SDCAS/SRE AWE/SWE/SDWE E6 ARDY AOE/SOE/SDRAS, ARE/SADS/SDCAS/SRE, and AWE/SWE/SDWE operate as AOE (identified under select signals), ARE, and AWE, respectively, during asynchronous memory accesses. E5 Read Data E2 BE E2 E2 E2 Strobe = 3 Not Ready Hold = 2 E7 E6 E7 Figure 6-7. Asynchronous Memory Read Timing for EMIF December 2002 SPRS208 111 PRODUCT PREVIEW Electrical Specifications Setup = 2 ECLKOUT1 E8 CEx E8 BE[3:0] E8 A[21:2] E8 D[31:0] AOE/SOE/SDRAS ARE/SADS/SDCAS/SRE E10 E10 Write Data Address E9 BE E9 E9 E9 Hold = 2 Strobe = 3 Not Ready PRODUCT PREVIEW AWE/SWE/SDWE E7 E6 ARDY AOE/SOE/SDRAS, ARE/SADS/SDCAS/SRE, and AWE/SWE/SDWE operate as AOE (identified under select signals), ARE, and AWE, respectively, during asynchronous memory accesses. E6 E7 Figure 6-8. Asynchronous Memory Write Timing for EMIF 112 SPRS208 December 2002 Electrical Specifications 6.9 Programmable Synchronous Interface Timing Table 6-11 and Table 6-12 assume testing over recommended operating conditions (see Figure 6-9 through Figure 6-11). Table 6-11. EMIF Programmable Synchronous Interface Timing Requirements NO. E6 E7 tsu(EDV-EKOxH) th(EKOxH-EDV) Setup time, read Dx valid before ECLKOUTx high Hold time, read Dx valid after ECLKOUTx high MIN 2 1.5 MAX UNIT ns ns Table 6-12. EMIF Programmable Synchronous Interface Switching Characteristics NO. E1 E2 E3 E4 E5 E8 E9 E10 E11 td(EKOxH-CEV) td(EKOxH-BEV) td(EKOxH-BEIV) td(EKOxH-EAV) td(EKOxH-EAIV) td(EKOxH-ADSV) td(EKOxH-OEV) td(EKOxH-EDV) td(EKOxH-EDIV) td(EKOxH-WEV) PARAMETER Delay time, ECLKOUTx high to CEx valid Delay time, ECLKOUTx high to BEx valid Delay time, ECLKOUTx high to BEx invalid Delay time, ECLKOUTx high to Ax valid Delay time, ECLKOUTx high to Ax invalid Delay time, ECLKOUTx high to SADS/SRE valid Delay time, ECLKOUTx high to, SOE valid Delay time, ECLKOUTx high to Dx valid Delay time, ECLKOUTx high to Dx invalid 1 1 1 1 5 5 5 1 5 MIN 1 MAX 5 5 UNIT ns ns ns ns ns ns ns ns ns E12 Delay time, ECLKOUTx high to SWE valid 1 5 ns The following parameters are programmable via the EMIF CE Secondary Control Registers (CEx_SC1, CEx_SC2): - Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency - Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency - CEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, CEx goes inactive after the final command has been issued (CEEXT = 0). For synchronous FIFO interface with glue, CEx is active when SOE is active (CEEXT = 1). - Function of SADS/SRE (RENEN): For standard SBSRAM or ZBT SRAM interface, SADS/SRE acts as SADS with deselect cycles (RENEN = 0). For FIFO interface, SADS/SRE acts as SRE with NO deselect cycles (RENEN = 1). - Synchronization clock (SNCCLK): Synchronized to ECLKOUT1 or ECLKOUT2 December 2002 SPRS208 113 PRODUCT PREVIEW Electrical Specifications READ latency = 2 ECLKOUTx E1 CEx BE[3:0] A[21:2] E2 BE1 E4 A1 A2 E6 D[31:0] E8 ARE/SADS/SDCAS/SRE E9 AOE/SOE/SDRAS AWE/SWE/SDWE E9 Q1 A3 EA3 E7 Q2 E3 BE2 BE3 BE4 E5 A4 E1 Q3 Q4 E8 PRODUCT PREVIEW The read latency and the length of CEx assertion are programmable via the SYNCRL and CEEXT fields, respectively, in the EMIF CE Secondary Control Registers (CEx_SC1, CEx_SC2). In the figure, SYNCRL = 2 and CEEXT = 0. The following parameters are programmable via the EMIF CE Secondary Control Registers (CEx_SC1, CEx_SC2): - Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency - Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency - CEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, CEx goes inactive after the final command has been issued (CEEXT = 0). For synchronous FIFO interface with glue, CEx is active when SOE is active (CEEXT = 1). - Function of SADS/SRE (RENEN): For standard SBSRAM or ZBT SRAM interface, SADS/SRE acts as SADS with deselect cycles (RENEN = 0). For FIFO interface, SADS/SRE acts as SRE with NO deselect cycles (RENEN = 1). - Synchronization clock (SNCCLK): Synchronized to ECLKOUT1 or ECLKOUT2 ARE/SADS/SDCAS/SRE, AOE/SOE/SDRAS, and AWE/SWE/SDWE operate as SADS/SRE, SOE, and SWE, respectively, during programmable synchronous interface accesses. Figure 6-9. Programmable Synchronous Interface Read Timing for EMIF (With Read Latency = 2) 114 SPRS208 December 2002 Electrical Specifications ECLKOUTx CEx E1 E2 BE1 E4 A1 E10 D[31:0] ARE/SADS/SDCAS/SRE AOE/SOE/SDRAS E12 AWE/SWE/SDWE The write latency and the length of CEx assertion are programmable via the SYNCWL and CEEXT fields, respectively, in the EMIF CE Secondary Control Registers (CEx_SC1, CEx_SC2). In this figure, SYNCWL = 0 and CEEXT = 0. ARE/SADS/SDCAS/SRE, AOE/SOE/SDRAS, and AWE/SWE/SDWE operate as SADS/SRE, SOE, and SWE, respectively, during programmable synchronous interface accesses. E12 E10 Q1 E8 E1 E3 BE2 BE3 BE4 E5 A2 A3 A4 E11 Q2 Q3 Q4 E8 BE[3:0] A[21:2] Figure 6-10. Programmable Synchronous Interface Write Timing for EMIF (With Write Latency = 0) December 2002 SPRS208 115 PRODUCT PREVIEW Electrical Specifications Write Latency = 1 ECLKOUTx E1 CEx BE[3:0] A[21:2] D[31:0] E8 ARE/SADS/SDCAS/SRE AOE/SOE/SDRAS E12 AWE/SWE/SDWE E12 E2 BE1 E4 A1 E10 A2 E10 Q1 A3 Q2 A4 E11 Q3 Q4 E8 E3 BE2 BE3 BE4 E5 E1 PRODUCT PREVIEW The write latency and the length of CEx assertion are programmable via the SYNCWL and CEEXT fields, respectively, in the EMIF CE Secondary Control Registers (CEx_SC1, CEx_SC2). In this figure, SYNCWL = 1 and CEEXT = 0. The following parameters are programmable via the EMIF CE Secondary Control Registers (CEx_SC1, CEx_SC2): - Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency - Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency - CEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, CEx goes inactive after the final command has been issued (CEEXT = 0). For synchronous FIFO interface with glue, CEx is active when SOE is active (CEEXT = 1). - Function of SADS/SRE (RENEN): For standard SBSRAM or ZBT SRAM interface, SADS/SRE acts as SADS with deselect cycles (RENEN = 0). For FIFO interface, SADS/SRE acts as SRE with NO deselect cycles (RENEN = 1). - Synchronization clock (SNCCLK): Synchronized to ECLKOUT1 or ECLKOUT2 ARE/SADS/SDCAS/SRE, AOE/SOE/SDRAS, and AWE/SWE/SDWE operate as SADS/SRE, SOE, and SWE, respectively, during programmable synchronous interface accesses. Figure 6-11. Programmable Synchronous Interface Write Timing for EMIF (With Write Latency = 1) 116 SPRS208 December 2002 Electrical Specifications 6.10 Synchronous DRAM Timing Table 6-13 and Table 6-14 assume testing over recommended operating conditions (see Figure 6-12 through Figure 6-19). Table 6-13. EMIF Synchronous DRAM Cycle Timing Requirements NO. E6 E7 tsu(EDV-EKO1H) th(EKO1H-EDV) Setup time, read Dx valid before ECLKOUT1 high Hold time, read Dx valid after ECLKOUT1 high MIN 0.5 2 MAX UNIT ns ns Table 6-14. EMIF Synchronous DRAM Cycle Switching Characteristics NO. E1 E2 E3 E4 E5 E8 E9 E10 E11 E12 E13 td(EKO1H-CEV) td(EKO1H-BEV) td(EKO1H-BEIV) td(EKO1H-EAV) td(EKO1H-EAIV) td(EKO1H-CASV) td(EKO1H-EDV) td(EKO1H-EDIV) td(EKO1H-WEV) td(EKO1H-RAS) td(EKO1H-ACKEV) PARAMETER Delay time, ECLKOUT1 high to CEx valid/invalid Delay time, ECLKOUT1 high to BEx valid Delay time, ECLKOUT1 high to BEx invalid Delay time, ECLKOUT1 high to Ax valid Delay time, ECLKOUT1 high to Ax invalid Delay time, ECLKOUT1 high to SDCAS valid Delay time, ECLKOUT1 high to Dx valid Delay time, ECLKOUT1 high to Dx invalid Delay time, ECLKOUT1 high to SDWE valid Delay time, ECLKOUT1 high to SDRAS valid Delay time, ECLKOUT1 high to SDCKE valid 1 1 1 1 5 5 5 1 1 5 5 1 5 MIN 1 MAX 5 5 UNIT ns ns ns ns ns ns ns ns ns ns ns READ ECLKOUT1 E1 CEx BE[3:0] E4 Bank E4 Column E4 A12 E6 D[31:0] AOE/SOE/SDRAS E8 ARE/SADS/SDCAS/SRE AWE/SWE/SDWE ARE/SADS/SDCAS/SRE, AWE/SWE/SDWE, and AOE/SOE/SDRAS operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses. E8 D1 E7 D2 D3 D4 E2 BE1 E5 E3 BE2 BE3 BE4 E1 A[21:13] A[11:2] E5 E5 Figure 6-12. SDRAM Read Command (CAS Latency 3) for EMIF December 2002 SPRS208 117 PRODUCT PREVIEW Electrical Specifications WRITE ECLKOUT1 E1 CEx E2 BE[3:0] E4 A[21:13] E4 A[11:2] A12 E9 D[31:0] AOE/SOE/SDRAS D1 E9 D2 D3 D4 E10 Column E4 E5 Bank E5 BE1 E5 E2 BE2 BE3 BE4 E3 E1 PRODUCT PREVIEW E8 ARE/SADS/SDCAS/SRE E11 AWE/SWE/SDWE E8 E11 ARE/SADS/SDCAS/SRE, AWE/SWE/SDWE, and AOE/SOE/SDRAS operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses. Figure 6-13. SDRAM Write Command for EMIF ACTV ECLKOUT1 E1 CEx BE[3:0] E4 Bank Activate E4 Row Address E4 Row Address E5 E1 A[21:13] A[11:2] E5 E5 A12 D[31:0] E12 AOE/SOE/SDRAS ARE/SADS/SDCAS/SRE AWE/SWE/SDWE E12 ARE/SADS/SDCAS/SRE, AWE/SWE/SDWE, and AOE/SOE/SDRAS operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses. Figure 6-14. SDRAM ACTV Command for EMIF 118 SPRS208 December 2002 Electrical Specifications DCAB ECLKOUT1 E1 CEx BE[3:0] A[21:13, 11:2] E4 A12 D[31:0] E12 AOE/SOE/SDRAS ARE/SADS/SDCAS/SRE E11 AWE/SWE/SDWE E11 E12 E5 E1 Figure 6-15. SDRAM DCAB Command for EMIF DEAC ECLKOUT1 E1 CEx BE[3:0] E4 A[21:13] A[11:2] E4 A12 D[31:0] E12 AOE/SOE/SDRAS ARE/SADS/SDCAS/SRE E11 AWE/SWE/SDWE ARE/SADS/SDCAS/SRE, AWE/SWE/SDWE, and AOE/SOE/SDRAS operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses. E11 E12 E5 Bank E5 E1 Figure 6-16. SDRAM DEAC Command for EMIF December 2002 SPRS208 119 PRODUCT PREVIEW ARE/SADS/SDCAS/SRE, AWE/SWE/SDWE, and AOE/SOE/SDRAS operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses. Electrical Specifications REFR ECLKOUT1 E1 CEx BE[3:0] A[21:13, 11:2] E1 A12 D[31:0] E12 AOE/SOE/SDRAS E8 ARE/SADS/SDCAS/SRE AWE/SWE/SDWE ARE/SADS/SDCAS/SRE, AWE/SWE/SDWE, and AOE/SOE/SDRAS operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses. E8 E12 PRODUCT PREVIEW Figure 6-17. SDRAM REFR Command for EMIF MRS ECLKOUT1 E1 CEx BE[3:0] E4 MRS value E5 E1 A[21:2] D[31:0] E12 AOE/SOE/SDRAS E8 ARE/SADS/SDCAS/SRE E11 AWE/SWE/SDWE E12 E8 E11 ARE/SADS/SDCAS/SRE, AWE/SWE/SDWE, and AOE/SOE/SDRAS operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses. Figure 6-18. SDRAM MRS Command for EMIF 120 SPRS208 December 2002 Electrical Specifications TRAS cycles Self Refresh ECLKOUT1 CEx BE[3:0] A[21:13, 11:2] A12 D[31:0] AOE/SOE/SDRAS ARE/SADS/SDCAS/SRE End Self-Refresh AWE/SWE/SDWE E13 SDCKE ARE/SADS/SDCAS/SRE, AWE/SWE/SDWE, and AOE/SOE/SDRAS operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses. E13 Figure 6-19. SDRAM Self-Refresh Timing for EMIF December 2002 SPRS208 121 PRODUCT PREVIEW Electrical Specifications 6.11 HOLD/HOLDA Timing Table 6-15 and Table 6-16 assume testing over recommended operating conditions (see Figure 6-20). Table 6-15. EMIF HOLD/HOLDA Timing Requirements NO. H3 toh(HOLDAL-HOLDL) Hold time, HOLD low after HOLDA low E = the EMIF input clock (ECLKIN, CPU/1 clock, CPU1/2 clock, or CPU1/4 clock) period in ns for EMIF. MIN E MAX UNIT ns Table 6-16. EMIF HOLD/HOLDA Switching Characteristics NO. H1 H2 H4 H5 H6 H7 td(HOLDL-EMHZ) td(EMHZ-HOLDAL) td(HOLDH-EMLZ) td(EMLZ-HOLDAH) td(HOLDL-EKOHZ) td(HOLDH-EKOLZ) PARAMETER Delay time, HOLD low to EMIF Bus high impedance Delay time, EMIF Bus high impedance to HOLDA low Delay time, HOLD high to EMIF Bus low impedance Delay time, EMIF Bus low impedance to HOLDA high Delay time, HOLD low to ECLKOUTx high impedance Delay time, HOLD high to ECLKOUTx low impedance MIN 2E 0 2E 0 2E 2E MAX 2E 7E 2E 7E UNIT ns ns ns ns ns PRODUCT PREVIEW ns E = the EMIF input clock (ECLKIN, CPU/1 clock, CPU1/2 clock, or CPU1/4 clock) period in ns for EMIF. EMIF Bus consists of: CE[3:0], BE[3:0], D[31:0], A[21:2], ARE/SADS/SDCAS/SRE, AOE/SOE/SDRAS, and AWE/SWE/SDWE, SDCKE, and SOE3. The EKxHZ bits in the EMIF Global Control Registers (EGCR1, EGCR2) determine the state of the ECLKOUTx signals during HOLDA. If EKxHZ = 0, ECLKOUTx continues clocking during Hold mode. If EKxHZ = 1, ECLKOUTx goes to high impedance during Hold mode, as shown in Figure 6-20. All pending EMIF transactions are allowed to complete before HOLDA is asserted. If no bus transactions are occurring, then the minimum delay time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1. DSP Owns Bus External Requestor Owns Bus H3 HOLD H2 HOLDA EMIF Bus H1 5502 H4 H5 DSP Owns Bus ECLKOUTx H6 ECLKOUTx EMIF Bus consists of: CE[3:0], BE[3:0], D[31:0], A[21:2], ARE/SADS/SDCAS/SRE, AOE/SOE/SDRAS, and AWE/SWE/SDWE, SDCKE, and SOE3. H7 Figure 6-20. HOLD/HOLDA Timing for EMIF 122 SPRS208 December 2002 Electrical Specifications 6.12 Reset Timings Table 6-17 and Table 6-18 assume testing over recommended operating conditions (see Figure 6-21). Table 6-17. Reset Timing Requirements NO. R1 MIN MAX UNIT ns tw(RSL) Pulse width, RESET low 2P + 5 P = the period of the clock on the X2/CLKIN pin in ns. For example, when using 20 MHz as the input clock, use P = 50 ns. Table 6-18. Reset Switching Characteristics NO. R3 R4 R5 R6 R7 R8 R9 R10 td(RSL-EMIFHZ) td(RSH-EMIFV) td(RSL-LOWIV) td(RSH LOWV) d(RSH-LOWV) td(RSL-HIGHIV) td(RSH HIGHV) d(RSH-HIGHV) td(RSL-ZHZ) td(RSH ZV) d(RSH-ZV) PARAMETER Delay time, RESET low to EMIF group high impedance Delay time RESET high to EMIF group valid time, Delay time, RESET low to low group invalid Delay time RESET high to low group valid time, Delay time, RESET low to high group invalid Delay time RESET high to high group valid time, Delay time, RESET low to Z group high impedance Delay time RESET high to Z group invalid time, GPIO4 = 0 (CLKMOD = 0) GPIO4 = 1 (CLKMOD = 1) GPIO4 = 0 (CLKMOD = 0) GPIO4 = 1 (CLKMOD = 1) GPIO4 = 0 (CLKMOD = 0) GPIO4 = 1 (CLKMOD = 1) GPIO4 = 0 (CLKMOD = 0) GPIO4 = 1 (CLKMOD = 1) MIN MAX 6 41102P + 6 70P + 6 6 41102P + 6 70P + 6 6 41102P + 6 70P + 6 6 41102P + 6 70P + 6 ns ns ns ns ns UNIT ns ns P = the period of the clock on the X2/CLKIN pin in ns. For example, when using 20 MHz as the input clock, use P = 50 ns. EMIF group: CE[3:0], BE[3:0], ECLKOUTx, ARE, AOE, AWE, SADS, SOE, SWE, SDRAS, SDCAS, SDWE High group: HINT, IACK Low group: HOLDA Z group: A[21:2], D[31:0], CLKR[2:0], CLKX[2:0], FSR[2:0], FSX[2:0], DX[2:0], GPIO[7:0], XF, TIM1, and TIM0. R1 RESET R3 EMIF Group R5 Low Group R7 High Group R9 Z Group R10 R8 R6 R4 Figure 6-21. Reset Timing December 2002 SPRS208 123 PRODUCT PREVIEW ns Electrical Specifications 6.13 External Interrupt and Interrupt Acknowledge (IACK) Timings Table 6-19 and Table 6-20 assume testing over recommended operating conditions (see Figure 6-22 and Figure 6-23). Table 6-19. External Interrupt and Interrupt Acknowledge Timing Requirements NO. I1 tw(INTL)A Pulse width, interrupt low, CPU active MIN 3P 2P MAX UNIT ns ns I2 tw(INTH)A Pulse width, interrupt high, CPU active P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns. Table 6-20. External Interrupt and Interrupt Acknowledge Switching Characteristics NO. I3 PARAMETER td(COH-IACKV) Delay time, CLKOUT high to IACK valid MIN 0 MAX 3 UNIT ns I1 PRODUCT PREVIEW INTx, NMI I2 Figure 6-22. External Interrupt Timing CLKOUT I3 I3 IACK Figure 6-23. External Interrupt Acknowledge Timing 124 SPRS208 December 2002 Electrical Specifications 6.14 XF Timing Table 6-21 assumes testing over recommended operating conditions (see Figure 6-24). Table 6-21. XF Switching Characteristics NO. X1 td(XF) PARAMETER Delay time, CLKOUT high to XF high Delay time, CLKOUT high to XF low MIN 0 0 MAX 3 3 ns UNIT CLKOUT X1 XF Figure 6-24. XF Timing December 2002 SPRS208 125 PRODUCT PREVIEW Electrical Specifications 6.15 General-Purpose Input/Output (GPIOx)Timing Table 6-22 and Table 6-23 assume testing over recommended operating conditions (see Figure 6-25). Table 6-22. GPIO Pins Configured as Inputs Timing Requirements NO. G2 G3 tsu(GPIO-COH) th(COH-GPIO) Setup time, GPIOx input valid before CLKOUT high Hold time, GPIOx input valid after CLKOUT high MIN 4 0 MAX UNIT ns ns Table 6-23. GPIO Pins Configured as Inputs Switching Characteristics NO. G1 td(COH-GPIO) CLKOUT PARAMETER Delay time, CLKOUT high to GPIOx output change MIN 0 MAX 3 UNIT ns G2 PRODUCT PREVIEW G3 GPIOx Input Mode G1 GPIOx Output Mode Figure 6-25. General-Purpose Input/Output (GPIOx) Signal Timings 126 SPRS208 December 2002 Electrical Specifications 6.15.1 TIM0/TIM1/WDTOUT Timings Table 6-24 and Table 6-25 assume testing over recommended operating conditions (see Figure 6-26 and Figure 6-27). Table 6-24. TIM0/TIM1/WDTOUT Pins Configured as Inputs Timing Requirements NO. T4 T5 tw(TIML) tw(TIMH) Pulse width, TIM0/TIM1/WDTOUT low Pulse width, TIM0/TIM1/WDTOUT high MIN P/4 P/4 MAX UNIT ns ns P = (Divider1 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the fast peripheral domain at 1/2 the CPU clock frequency, use P = 2/300 MHz = 6.66 ns. Table 6-25. TIM0/TIM1/WDTOUT Pins Configured as Outputs Switching Characteristics NO. T1 T2 td(COH-TIMH) td(COH-TIML) PARAMETER Delay time, CLKOUT high to TIM0/TIM1/WDTOUT high Delay time, CLKOUT high to TIM0/TIM1/WDTOUT low MIN 0 0 P MAX 3 3 UNIT ns ns T4 T5 TIM0/TIM1/WDTOUT as Input Figure 6-26. TIM0/TIM1/WDTOUT Timings When Configured as Inputs CLKOUT T2 T1 TIM0/TIM1/WDTOUT as Output T3 Figure 6-27. TIM0/TIM1/WDTOUT Timings When Configured as Outputs December 2002 SPRS208 127 PRODUCT PREVIEW T3 tw(TIM) Pulse duration, TIM0/TIM1/WDTOUT ns P = (Divider1 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the fast peripheral domain at 1/2 the CPU clock frequency, use P = 2/300 MHz = 6.66 ns. Electrical Specifications 6.16 Multichannel Buffered Serial Port (McBSP) Timing 6.16.1 McBSP Transmit and Receive Timings Table 6-26 and Table 6-27 assume testing over recommended operating conditions (see Figure 6-28 and Figure 6-29). Table 6-26. McBSP Transmit and Receive Timing Requirements NO. M11 M12 M13 M14 M15 M16 tc(CKRX) tw(CKRX) tr(CKRX) tf(CKRX) tsu(FRH-CKRL) th(CKRL-FRH) tsu(DRV-CKRL) th(CKRL-DRV) tsu(FXH-CKXL) th(CKXL-FXH) Cycle time, CLKR/X Pulse duration, CLKR/X high or CLKR/X low Rise time, CLKR/X Fall time, CLKR/X Setup time external FSR high before CLKR low time, Hold time external FSR high after CLKR low time, Setup time DR valid before CLKR low time, Hold time DR valid after CLKR low time, Setup time external FSX high before CLKX low time, Hold time external FSX high after CLKX low time, CLKR/X ext CLKR/X ext CLKR/X ext CLKR/X ext CLKR int CLKR ext CLKR int CLKR ext CLKR int M17 M18 M19 M20 CLKR ext CLKR int CLKR ext CLKX int CLKX ext CLKX int CLKX ext 5 1 0 2 3 1 0 2 5 1 0 2 ns ns ns ns ns ns MIN 2P P-1 5 5 MAX UNIT ns ns ns ns PRODUCT PREVIEW Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted. P = (Divider2 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the slow peripheral domain at 1/2 the CPU clock frequency, use P = 2/300 MHz = 6.66 ns. 128 SPRS208 December 2002 Electrical Specifications Table 6-27. McBSP Transmit and Receive Switching Characteristics NO. M1 M2 M3 M4 M5 M6 tc(CKRX) tw(CKRXH) tw(CKRXL) td(CKRH-FRV) td(CKXH-FXV) Cycle time, CLKR/X Pulse duration, CLKR/X high Pulse duration, CLKR/X low Delay time CLKR high to internal FSR valid time, Delay time CLKX high to internal FSX valid time, PARAMETER CLKR/X int CLKR/X int CLKR/X int CLKR int CLKR ext CLKX int CLKX ext CLKX int CLKX ext CLKX int DXENA = 0 CLKX ext CLKX int DXENA = 0 Only applies to first bit transmitted when in Data Delay 1 or 2 (XDATDLY=01b or 10b) modes Enable time, CLKX high to DX driven , g DXENA = 0 M8 ten(CKXH-DX) Only applies to first bit transmitted when in Data Delay 1 or 2 (XDATDLY=01b or 10b) modes Delay time, FSX high to DX valid y , g DXENA = 0 M9 td(FXH-DXV) Only applies to first bit transmitted when in Data Delay 0 (XDATDLY=00b) mode. Enable time, FSX high to DX driven , g DXENA = 0 M10 ten(FXH-DX) Only applies to first bit transmitted when in Data Delay 0 (XDATDLY=00b) mode CLKX ext CLKX int DXENA = 1 CLKX ext CLKX int CLKX ext CLKX int DXENA = 1 CLKX ext FSX int FSX ext FSX int DXENA = 1 FSX ext FSX int FSX ext FSX int DXENA = 1 FSX ext 0 6 2P P+6 ns 0 6 2P 2P+6 1 7 2P+1 2P+7 ns ns 8 2 8 ns MIN 2P D-1 C-1 -2 4 -2 4 -5 1 MAX D+1 C+1 2 8 2 8 5 11 2 ns ns ns UNIT ns ns ns Disable time, CLKX high to DX high im edance impedance tdis(CKXH-DXHZ) following last data bit Delay time, CLKX high to DX valid. This applies to all bits except the first bit transmitted. M7 td(CKXH DXV) d(CKXH-DXV) Delay time, CLKX high to DX valid y , g 2P+8 Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted. P = (Divider2 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the slow peripheral domain at 1/2 the CPU clock frequency, use P = 2/300 MHz = 6.66 ns. T=CLKRX period = (1 + CLKGDV) * P C=CLKRX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * P when CLKGDV is even D=CLKRX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * P when CLKGDV is even See the TMS320C55x DSP Peripherals Reference Guide (literature number SPRU317) for a description of the DX enable (DXENA) and data delay features of the McBSP. December 2002 SPRS208 129 PRODUCT PREVIEW 2P+2 Electrical Specifications M1, M11 M2, M12 M13 M3, M12 CLKR M4 FSR (Int) M15 FSR (Ext) M17 DR (RDATDLY=00b) M18 Bit (n-1) M17 (n-2) M18 Bit (n-1) M17 DR (RDATDLY=10b) Bit (n-1) (n-2) M18 (n-2) (n-3) (n-3) (n-4) M16 M4 M14 PRODUCT PREVIEW DR (RDATDLY=01b) Figure 6-28. McBSP Receive Timings M1, M11 M2, M12 M3, M12 CLKX M5 FSX (Int) M19 FSX (Ext) M9 M10 DX (XDATDLY=00b) DX (XDATDLY=01b) Bit 0 Bit (n-1) M8 Bit 1 M6 DX (XDATDLY=10b) NOTE A: Bit 2 Bit 1 Bit 0 Bit (n-1) (n-2) M7 (n-2) M7 M8 Bit 0 Bit (n-1) (n-2) (n-3) M7 (n-3) (n-4) M20 M5 M13 M14 This figure does not include first or last frames. For first frame, no data will be present before frame synchronization. For last frame, no data will be present after frame synchronization. Figure 6-29. McBSP Transmit Timings 130 SPRS208 December 2002 Electrical Specifications 6.16.2 McBSP General-Purpose I/O Timing Table 6-28 and Table 6-29 assume testing over recommended operating conditions (see Figure 6-30). Table 6-28. McBSP General-Purpose I/O Timing Requirements NO. M22 M23 MGPIOx refers to CLKRx, FSRx, DRx, CLKXx, or FSXx when configured as a general-purpose input. tsu(MGPIO-COH) th(COH-MGPIO) Setup time, MGPIOx input mode before CLKOUT high Hold time, MGPIOx input mode after CLKOUT high MIN 4 0 MAX UNIT ns ns Table 6-29. McBSP General-Purpose I/O Switching Characteristics NO. PARAMETER Delay time, CLKOUT high to MGPIOx output mode MIN 0 MAX 4 UNIT ns M21 td(COH-MGPIO) MGPIOx refers to CLKRx, FSRx, CLKXx, FSXx, or DXx when configured as a general-purpose output. M22 CLKOUT M21 M23 MGPIO Input Mode MGPIO Output Mode MGPIOx refers to CLKRx, FSRx, DRx, CLKXx, or FSXx when configured as a general-purpose input. MGPIOx refers to CLKRx, FSRx, CLKXx, FSXx, or DXx when configured as a general-purpose output. Figure 6-30. McBSP General-Purpose I/O Timings December 2002 SPRS208 131 PRODUCT PREVIEW Electrical Specifications 6.16.3 McBSP as SPI Master or Slave Timing Table 6-30 to Table 6-37 assume testing over recommended operating conditions (see Figure 6-31 through Figure 6-34). Table 6-30. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) MASTER NO. NO M30 M31 M32 M33 tsu(DRV-CKXL) th(CKXL-DRV) tsu(BFXL-CKXH) tc(CKX) Setup time, DR valid before CLKX low Hold time, DR valid after CLKX low Setup time, FSX low before CLKX high Cycle time, CLKX 2P MIN 3 1 MAX SLAVE MIN 2 - 6P 6 + 6P 10 16P MAX UNIT ns ns ns ns For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. P = (Divider2 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the slow peripheral domain at 1/2 the CPU clock frequency, use P = 2/300 MHz = 6.66 ns. Table 6-31. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0) PRODUCT PREVIEW MASTER NO. NO M24 M25 M26 M27 M28 td(CKXL-FXL) td(FXL-CKXH) td(CKXH-DXV) tdis(CKXL-DXHZ) tdis(FXH-DXHZ) PARAMETER Delay time, CLKX low to FSX low Delay time, FSX low to CLKX high# Delay time, CLKX high to DX valid Disable time, DX high impedance following last data bit from CLKX low Disable time, DX high impedance following last data bit from FSX high MIN T-1 C-1 -2 C-2 MAX T+1 C+1 2 C +10 SLAVE MIN MAX UNIT ns ns 3P + 4 5P+ 10 ns ns 2P+ 4 4P + 10 ns M29 td(FXL-DXV) Delay time, FSX low to DX valid 2P + 4 4P + 10 ns For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. P = (Divider2 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the slow peripheral domain at 1/2 the CPU clock frequency, use P = 2/300 MHz = 6.66 ns. T = BCLKX period = (1 + CLKGDV) * 2P C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2P when CLKGDV is even FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP # FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX). 132 SPRS208 December 2002 Electrical Specifications LSB CLKX M25 M24 FSX M28 M27 DX Bit 0 M30 M31 DR Bit 0 Bit (n-1) (n-2) (n-3) (n-4) M29 Bit (n-1) (n-2) (n-3) (n-4) M26 M32 MSB M33 Figure 6-31. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 December 2002 SPRS208 133 PRODUCT PREVIEW Electrical Specifications Table 6-32. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0) MASTER NO. NO M39 M40 M41 M42 tsu(DRV-CKXH) th(CKXH-DRV) tsu(FXL-CKXH) tc(CKX) Setup time, DR valid before CLKX high Hold time, DR valid after CLKX high Setup time, FSX low before CLKX high Cycle time, CLKX 2P MIN 3 1 MAX SLAVE MIN 2 - 6P 6 +6P 10 16P MAX UNIT ns ns ns ns For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. P = (Divider2 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the slow peripheral domain at 1/2 the CPU clock frequency, use P = 2/300 MHz = 6.66 ns. Table 6-33. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0) MASTER NO. NO PARAMETER td(CKXL-FXL) td(FXL-CKXH) td(CKXH-DXV) tdis(CKXL-DXHZ) Delay time, CLKX low to FSX low Delay time, FSX low to CLKX high# Delay time, CLKX high to DX valid Disable time, DX high impedance following last data bit from CLKX low MIN C-1 T-1 -2 -2 MAX C+1 T+1 2 10 3P + 4 3P + 4 5P + 10 5P + 10 MIN M34 M35 M36 M37 SLAVE MAX UNIT ns ns ns ns PRODUCT PREVIEW M38 td(FXL-DXV) Delay time, FSX low to DX valid D-2 D +10 2P - 4 4P + 10 ns For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. P = (Divider2 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the slow peripheral domain at 1/2 the CPU clock frequency, use P = 2/300 MHz = 6.66 ns. T = CLKX period = (1 + CLKGDV) * P C = CLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * P when CLKGDV is even D = CLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * P when CLKGDV is even FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP # FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX). LSB CLKX M41 MSB M42 M35 M34 FSX M38 Bit (n-1) M39 M40 DR Bit 0 Bit (n-1) (n-2) (n-3) (n-4) (n-2) (n-3) (n-4) M36 M37 DX Bit 0 Figure 6-32. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 134 SPRS208 December 2002 Electrical Specifications Table 6-34. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1) MASTER NO. NO M49 M50 M51 M52 tsu(DRV-CKXH) th(CKXH-DRV) tsu(FXL-CKXL) tc(CKX) Setup time, DR valid before CLKX high Hold time, DR valid after CLKX high Setup time, FSX low before CLKX low Cycle time, CLKX 2P MIN 3 1 MAX SLAVE MIN 2 - 6P 6 + 6P 10 16P MAX UNIT ns ns ns ns For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. P = (Divider2 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the slow peripheral domain at 1/2 the CPU clock frequency, use P = 2/300 MHz = 6.66 ns. Table 6-35. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1) MASTER NO. NO M43 M44 M45 M46 M47 td(CKXH-FXL) td(FXL-CKXL) td(CKXL-DXV) tdis(CKXH-DXHZ) tdis(FXH-DXHZ) PARAMETER Delay time, CLKX high to FSX low Delay time, FSX low to CLKX low# Delay time, CLKX low to DX valid Disable time, DX high impedance following last data bit from CLKX high Disable time, DX high impedance following last data bit from FSX high MIN T-1 D-1 -2 D-2 MAX T+1 D+1 2 D +10 2P + 4 4P + 10 3P + 4 5P + 10 MIN SLAVE MAX UNIT ns ns ns ns M48 td(FXL-DXV) Delay time, FSX low to DX valid 2P - 4 4P + 10 ns For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. P = (Divider2 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the slow peripheral domain at 1/2 the CPU clock frequency, use P = 2/300 MHz = 6.66 ns. T = CLKX period = (1 + CLKGDV) * P D = CLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * P when CLKGDV is even FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP # FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX). LSB CLKX M44 M43 FSX M47 M46 DX Bit 0 M49 M50 DR Bit 0 Bit (n-1) (n-2) (n-3) (n-4) M48 Bit (n-1) (n-2) (n-3) (n-4) M45 M51 MSB M52 Figure 6-33. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 December 2002 SPRS208 135 PRODUCT PREVIEW ns Electrical Specifications Table 6-36. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1) MASTER NO. NO M58 M59 M60 M61 tsu(DRV-CKXL) th(CKXL-DRV) tsu(FXL-CKXL) tc(CKX) Setup time, DR valid before CLKX low Hold time, DR valid after CLKX low Setup time, FSX low before CLKX low Cycle time, CLKX 2P MIN 3 1 MAX MIN 2 - 6P 6 + 6P 10 16P SLAVE MAX UNIT ns ns ns ns For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. P = (Divider2 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the slow peripheral domain at 1/2 the CPU clock frequency, use P = 2/300 MHz = 6.66 ns. Table 6-37. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1) MASTER NO. NO M53 td(CKXH-FXL) td(FXL-CKXL) td(CKXH-DXV) tdis(CKXH-DXHZ) PARAMETER Delay time, CLKX high to FSX low Delay time, FSX low to CLKX low# Delay time, CLKX high to DX valid Disable time, DX high impedance following last data bit from CLKX high MIN D-1 T-1 -2 -2 MAX D+1 T+1 2 10 3P + 4 3P + 4 5P + 10 5P + 10 MIN SLAVE MAX UNIT ns ns ns ns PRODUCT PREVIEW M54 M55 M56 M57 td(FXL-DXV) Delay time, FSX low to DX valid C-2 C +10 2P - 4 4P + 10 ns For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. P = (Divider2 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the slow peripheral domain at 1/2 the CPU clock frequency, use P = 2/300 MHz = 6.66 ns. T = CLKX period = (1 + CLKGDV) * P C = CLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * P when CLKGDV is even D = CLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * P when CLKGDV is even FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP # FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX). M60 LSB CLKX MSB M61 M54 M53 FSX M57 Bit (n-1) M58 M59 DR Bit 0 Bit (n-1) (n-2) (n-3) (n-4) (n-2) (n-3) (n-4) M55 M56 DX Bit 0 Figure 6-34. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 136 SPRS208 December 2002 Electrical Specifications 6.17 HPI Timings Table 6-38 and Table 6-39 assume testing over recommended operating conditions (see Figure 6-35 through Figure 6-40). Table 6-38. HPI Timing Requirements NO. H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 tsu(HASL-HDSL) th(HDSL-HASL) tsu(HBV-HASL) th(HASL-HBV) tw(HDSL) tw(HDSH) tsu(HBV-HDSL) th(HDSL-HBV) tsu(HDV-HDSH)W th(HDSH-HDV)W Setup time, HAS low before DS falling edge Hold time, HAS low after DS falling edge Setup time, HAD valid before HAS falling edge Hold time, HAD valid after HAS falling edge Pulse duration, DS low Pulse duration, DS high Setup time, HAD valid before DS falling edge Hold time, HAD valid after DS falling edge Setup time, HD valid before DS rising edge Hold time, HD valid after DS rising edge MIN 5 2 5 5 10 2P 5 5 10 0 MAX UNIT ns ns ns ns ns ns ns ns ns ns Table 6-39. HPI Switching Characteristics NO. PARAMETER Case 1. Read Data present in FIFO. H1 td(HDSL-HDV) Delay time, DS low to HD valid Case 2. FIFO is Empty; No other DMA/MEM activity is present. Case 3. HPIC or Unobstructed HPIA Read. H2 H3 H4 H5 td(HDSH-HDV)R td(HDSL-HDD) td(HDSL-HRDYL) td(HDSH-HRDYL) Delay time, DS rising edge to HD valid, read Delay time, DS low to HD driven Delay time, DS low to HRDY low Delay time, DS high to HRDY low Delay time, DS high to HRDY high Case 1. FIFO is Empty; No other DMA/MEM activity present. Case 2. FIFO is Full; No other DMA/MEM activity is present. 3 0 3 MIN 3 MAX 20 n*2H+20 UNIT ns ns 20 10 20 12 12 n*2H+20 n*2H+20 7 3 ns ns ns ns ns ns ns ns ns H6 td(HDSH-HRDYH) tv(HRDYH-HDV) td(COH-HINT) H7 H8 Valid time, HD valid after HRDY high Delay time, CLKOUT rising edge to HINT change DS refers to logical OR of HCS, HDS1, and HDS2. HD refers to HPI Data Bus. HDS refers to HDS1 or HDS2. HAD refers to HCNTL0, HCNTL1, and HR/W. H is half the CPU clock cycle. December 2002 SPRS208 137 PRODUCT PREVIEW P = (Divider1 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the fast peripheral domain at 1/2 the CPU clock frequency, use P = 2/300 MHz = 6.66 ns. DS refers to logical OR of HCS, HDS1, and HDS2. HD refers to HPI Data Bus. HDS refers to HDS1 or HDS2. HAD refers to HCNTL0, HCNTL1, and HR/W. Electrical Specifications Read HCS H14 H13 HDSx H15 H16 HR/W H15 H16 H13 Write HPI.A[15:0] Valid H1 H3 H2 Read data Valid HPI.D[15:0] (Read) PRODUCT PREVIEW H17 HPI.D[15:0] (Write) H4 HRDY H7 H5 Write data H6 H18 Figure 6-35. Non-Multiplexed Read/Write Timings 138 SPRS208 December 2002 Electrical Specifications HCS H9 H10 HAS H11 HDSx H12 H14 HR/W H13 HCNTL[1:0] H1 HPI.HD[7:0] H3 HRDY Data 1 H5 H2 H4 H7 HPI.HBIL H6 Figure 6-36. Multiplexed Read Timings Using HAS December 2002 SPRS208 139 PRODUCT PREVIEW Data 2 Electrical Specifications HCS HDSx H15 H16 HR/W H2 HCNTL[1:0] H1 HPI.HD[7:0] H3 H4 HRDY H5 Data 1 Data 2 H14 H13 PRODUCT PREVIEW H7 HPI.HBIL H6 Figure 6-37. Multiplexed Read Timings With HAS Held High 140 SPRS208 December 2002 Electrical Specifications HCS H11 H10 HAS H9 HR/W H12 HCNTL[1:0] H14 HDSx H17 HPI.HD[7:0] Data 1 H18 HRDY H5 H6 HPI.HBIL H13 Figure 6-38. Multiplexed Write Timings Using HAS December 2002 SPRS208 141 PRODUCT PREVIEW Data 2 Electrical Specifications HCS H14 HDSx H15 HR/W H16 HCNTL[1:0] H17 HPI.HD[7:0] Data 1 H18 Data 2 H13 PRODUCT PREVIEW HRDY H5 H6 HPI.HBIL Figure 6-39. Multiplexed Write Timings With HAS Held High CLKOUT H8 HINT Figure 6-40. HINT Timing 142 SPRS208 December 2002 Electrical Specifications 6.18 I2C Timing Table 6-40 assumes testing over recommended operating conditions (see Figure 6-41). Table 6-40. I2C Signals (SDA and SCL) Switching Characteristics NO. IC1 IC2 IC3 IC4 IC5 IC6 IC7 IC8 IC9 IC10 IC11 IC12 IC13 IC14 IC15 tc(SCL) tsu(SCLH-SDAL) th(SCLL-SDAL) tw(SCLL) tw(SCLH) tsu(SDA-SCLH) th(SDA SCLL) h(SDA-SCLL) tw(SDAH) tr(SDA) tr(SCL) tf(SDA) tf(SCL) tsu(SCLH-SDAH) tw(SP) Cb PARAMETER Cycle time, SCL Setup time, SCL high before SDA low for a START and a repeated START condition Hold time, SCL low after SDA low for a START and a repeated START condition Pulse duration, SCL low Pulse duration, SCL high Setup time, SDA valid before SCL high Hold time, SDA valid after SCL For CBUS compatible masters low For I2C bus devices Pulse duration, SDA high between STOP and START conditions Rise time, SDA Rise time, SCL Fall time, SDA Fall time, SCL Setup time, SCL high before SDA high (for STOP condition) Pulse duration, spike (must be suppressed) Capacitive load for each bus line 400 4.0 STANDARD MODE MIN 10 4.7 4 4.7 4 250 5 0 4.7 1000 1000 300 300 0.6 0 50 400 0 1.3 300 300 300 300 ns s s pF ns 0.9 MAX FAST MODE MIN 2.5 0.6 0.6 1.3 0.6 100 MAX s s s s s ns s s UNIT The maximum th(SCLL-SDAL) has only to be met if the device does not stretch the low period (tw(SCLL)) of the SCL signal. Cb = The total capacitance of one bus line in pF. SDA IC8 IC4 IC10 SCL IC1 IC7 IC3 Stop Start Repeated Start IC12 IC3 IC2 IC5 IC6 IC14 IC13 Stop NOTES: A. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL. B. The maximum th(SCLL-SDAL) has only to be met if the device does not stretch the LOW period [tw(SCLL)] of the SCL signal. C. A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tsu(SDA-SCLH) * 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA-SCLH) = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the SCL line is released. D. Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed. Figure 6-41. I2C Timings December 2002 SPRS208 143 PRODUCT PREVIEW Electrical Specifications 6.19 UART Timing Table 6-41 to Table 6-42 assume testing over recommended operating conditions (see Figure 6-42). Table 6-41. UART Timing Requirements NO. U1 U2 tw(UDB)R tw(USB)R Pulse width, receive data bit Pulse width, receive start bit MIN 0.99U 0.99U MAX 1.01U 1.01U UNIT ns ns U = UART baud time = 1/programmed baud rate Table 6-42. UART Switching Characteristics NO. U3 U4 U5 fbaud tw(UDB)X PARAMETER Maximum programmable baud rate Pulse width, transmit data bit U - 2 U - 2 MIN MAX 5 U + 2 U + 2 UNIT MHz ns ns tw(USB)X Pulse width, transmit start bit U = UART baud time = 1/programmed baud rate PRODUCT PREVIEW U5 Data Bits TX Start Bit U4 Data Bits RX Start Bit U1 U2 Figure 6-42. UART Timings 144 SPRS208 December 2002 Mechanical Data 7 7.1 Mechanical Data Ball Grid Array Mechanical Data PLASTIC BALL GRID ARRAY GGW (S-PBGA-N176) 15,10 SQ 14,90 0,80 U T R P N M L K J H G F E D C B A A1 Corner 0,95 0,85 1 3 5 12,80 TYP 0.80 2 4 6 7 8 9 10 11 12 13 14 15 16 17 Bottom View 1,40 MAX Seating Plane 0,55 0,45 0,08 0,45 0,35 0,12 4145255-2/D 08/02 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice C. MicroStar BGAt configuration. Figure 7-1. TMS320VC5502 176-Ball MicroStar BGA Plastic Ball Grid Array Package MicroStar BGA is a trademark of Texas Instruments. 145 December 2002 SPRS208 PRODUCT PREVIEW Mechanical Data 7.2 Low-Profile Quad Flatpack Mechanical Data PLASTIC QUAD FLATPACK 89 PGF (S-PQFP-G176) 132 133 88 0,27 0,17 0,08 M 0,50 PRODUCT PREVIEW 0,13 NOM 176 45 1 21,50 SQ 24,20 SQ 23,80 26,20 SQ 25,80 1,45 1,35 44 Gage Plane 0,05 MIN 0,25 0- 7 0,75 0,45 Seating Plane 1,60 MAX 0,08 4040134 / B 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026 Figure 7-2. TMS320VC5502 176-Pin Low-Profile Quad Flatpack 146 SPRS208 December 2002 |
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