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| 5-V Voltage Regulator TLE 4287 G Preliminary Data Features * * * * * * * * * * * * Output voltage tolerance 2% Very low standby current consumption Input voltage up to 42 V Reset function down to 1 V output voltage ESD protection up to 2000 V Adjustable reset time On/Off logic Overtemperature protection Reverse polarity protection Short-circuit proof Very wide temperature range Very small output capacitor Ordering Code Q67006-A9286 P-DSO-14-4 Type w TLE 4287 G w New type Package P-DSO-14-4 (SMD) Functional Description The TLE 4287 G is a monolithic integrated 5-V voltage regulator in P-DSO-14-4 package. It supplies an output current IQ > 250 mA. The IC is short circuit proof and incorporates temperature protection that disables it at overtemperature. The input voltage VI is regulated in the range of 7.5 V < VI < 40 V to VQrated = 5 V. Therefore a reference voltage, which is kept highly accurate by resistance adjustment, is compared via a control amplifier to a voltage that is proportional to the output voltage. The control amplifier drives the base of the series transistor by a buffer. A comparator in the reset-generator block compares a reference voltage that is independent of the input voltage to the scaled-down output voltage. In the case of an output voltage VQ < 4.5 V the reset delay capacitor is discharged and a reset signal is generated by setting the reset output LOW. The reset delay time can be set by an external capacitor within a wide range. When the output voltage rises above VQ 4.5 V the reset delay capacitor is charged again. As soon as the delay capacitor voltage reaches the upper switching threshold the reset output pin is set HIGH again. Semiconductor Group 1 1998-11-01 TLE 4287 G The device has two logic inputs, EN and H. It is turned ON by a voltage > 4 V at EN, for example by the ignition and remains active in case H is set LOW, even if the voltage at EN goes LOW. This makes it possible to implement a self-holding circuit without external components. When the device is turned OFF, the output voltage drops to 0 V and current consumption tends towards 0 A. (Please see following truth table). Design Notes for External Components The input capacitor CI is necessary for compensation line influences. The resonant circuit consisting of lead inductance and input capacitance can be damped by a resistor of approx. 1 in series with CI. The output capacitor is necessary for the stability of the regulating circuit. Stability is guaranteed for CQ 100 nF within the operating temperature range. Table 1 Truth Table for Turn-On/Turn-Off Logic Enable EN Hold H L H H X L L X X L L L H VQ 0V 5V 5V 5V 5V 0V Remarks Initial state, pin 9 internally pulled up Regulator switched on via pin 6, by ignition for example Pin 9 clamped active to GND by controller while pin 6 is still HIGH Previous state remains, even ignition is shut off: self-holding state Ignition shut off while regulator is in self-holding state Regulator shut down by releasing of pin 9 while pin 6 remains LOW, final state. No active clamping required by external self-holding circuit (C) to keep regulator shut off Semiconductor Group 2 1998-11-01 TLE 4287 G Pin Configuration (top view) N.C. GND GND GND EN R 1 2 3 4 5 6 7 14 13 12 11 10 9 8 GND Q GND GND GND H RD AEP02240 Pin Definitions and Functions Pin No. 1 2 3, 4, 5, 10, 11, 12, 14 9 7 8 6 Symbol I N.C. GND H R RD EN Function Input; block to ground directly at the IC by a ceramic capacitor Not connected Ground Hold and release; active low, see truth table above for function, connected to Q via a pull-up resistor of 50 k Reset Output; open-collector output, internally connected to Q via a pull-up resistor of 30 k Reset Delay; connect to GND via external delay capacitor for setting delay time Enable; active high, device is turned ON by HIGH signal at this pin, internally connected to GND via pull-down resistor of 100 k Output; block to GND with a capacitor CQ 100 nF 13 Q Semiconductor Group 3 1998-11-01 TLE 4287 G Temperature Sensor Saturation Control and Protection Circuit 13 5V Output Input 1 Control Amplifier Adjustment Bandgap Reference Buffer Reset Generator 7 Reset Output 8 Reset Delay Turn-ON / Turn-OFF Logic 6 Enable 9 Hold 3,4,5,10,11,12,14 GND AEB02241 Figure 1 Block Diagram Semiconductor Group 4 1998-11-01 TLE 4287 G Absolute Maximum Ratings Tj = - 40 to 165 C Parameter Symbol Limit Values min. Input I Voltage Current Output Q Voltage Current Reset Output R Voltage Current Reset Delay Voltage Current Enable Voltage Current Hold Voltage Current max. Unit Remarks VI II - 0.5 - 42 - V mA - internally limited VQ IQ - 0.3 - 7 - V - - internally limited VR IR - 0.3 - 7 - V - - internally limited Vd Id - 0.3 - 42 - V - - - VEN IEN - 42 -5 42 5 V mA - t 400 ms VH IH -2 - 7 - V - - internally limited Semiconductor Group 5 1998-11-01 TLE 4287 G Absolute Maximum Ratings (cont'd) Tj = - 40 to 165 C Parameter Symbol Limit Values min. Ground GND Current Temperatures Junction temperature Junction temperature Storage temperature max. Unit Remarks IGND - 0.5 - A - Tj Tj Tstg - 40 - 40 - 50 165 175 150 C C C - max. 15 min - Note: Maximum ratings are absolute ratings; exceeding any one of these values may cause irreversible damage to the integrated circuit. Operating Range Parameter Input voltage Junction temperature Thermal Resistances Junction pin Junction ambient Symbol Limit Values min. max. 42 165 V C - - 7.5 - 40 Unit Remarks VI Tj Rthjc Rthja - - 30 70 K/W K/W - - Note: ESD-Protection according to MIL Std. 883: 2 kV. Semiconductor Group 6 1998-11-01 TLE 4287 G Electrical Characteristics 7.5 V VI 40 V; - 40 C < Tj < 150 C; VEN > 4 V (unless otherwise specified) Parameter Output voltage Output voltage Output current limitation Drop voltage Current consumption Iq = II - IQ Current consumption Iq = II - IQ Current consumption Iq = II - IQ Load regulation Line regulation Power-Supply-RippleRejection Temperature output voltage drift Output capacitance Reset Generator Reset switching threshold Vrt 4.50 - 4.5 20 10 2.2 0.1 7 Symbol Limit Values min. typ. 5.0 5.0 - 1.8 - 1.0 2.3 - - 55 0.5 - max. 5.10 5.10 - 2.5 50 10 5 + 25 + 25 - - - 4.90 4.90 250 - - - - - 25 - 25 - Unit V V mA V A A mA mV V dB mV/K nF Test Condition 5 mA < IQ < 200 mA 7.5 V < VI < 22 V 5 mA < IQ < 80 mA 7.5 V < VI < 36 V VQ VQ IQ VDR Iq Iq Iq VQ VQ PSRR VI < 22 V IQ = 200 mA1) Regulator OFF: VEN = 0 V, H = open Tj = 25 C, VEN = 0 V, H = open 5 mA < IQ < 200 mA 5 mA < IQ < 200 mA 7.5 V < VI < 22 V IQ = 20 mA fr = 100 Hz; Vr = 0.5 VSS - - VQ /T - CQ 100 4.65 0.1 - 30 15 3 0.43 4.80 0.4 5.05 40 38 3.6 0.8 V V V k A V V - VR,low Reset output high voltage VR,high RR Reset pull up resistor Reset output low voltage RR = 4.7 k to VQ2) RR = internally connected to Q Id Delay switching threshold Vdt Delay switching threshold Vst Reset charging current Semiconductor Group VD = 1.5 V - - 1998-11-01 TLE 4287 G Electrical Characteristics (cont'd) 7.5 V VI 40 V; - 40 C < Tj < 150 C; VEN > 4 V (unless otherwise specified) Parameter Delay saturation voltage Reset delay time, low ' high Reset delay time, high ' low Enable EN, Hold H Symbol Limit Values min. typ. 50 20 2.0 max. - 30 4.0 mV ms s - 7.5 0.5 Unit Test Condition Vd,sat td tt VQ < Vrt CD = 100 nF CD = 100 nF VEN Enable turn-OFF voltage VEN Enable pull-down resistor REN Enable turn-ON voltage Enable hysteresis Enable input current Hold keep on voltage Hold release voltage Hold pull-up resistor 1) 2) 2.3 2.0 50 0.2 - 30 60 20 3.0 2.5 100 0.4 35 35 70 50 4.0 3.5 200 0.8 100 50 80 100 V V k V A % % k IC turned-ON IC turned-OFF internally connected to GND - VEN IEN VH VH RH VEN = 4 V referred to VQ; VQ > 4.5 V referred to VQ; VQ > 4.5 V internally connected to Q Measured when the output voltage VQ has dropped 100 mV from the nominal value The reset output is LOW between VQ = 1 V and Vrt Semiconductor Group 8 1998-11-01 TLE 4287 G Input 1 13 Enable e.g. from Terminal 15 Reset to MC C 100 nF 5V Output 6 7 TLE 4287 3,4,5, 10,11, 12,14 9 8 CQ 100 nF CD 100 nF AES02243 Hold from MC Figure 2 Application Circuit Semiconductor Group 9 1998-11-01 TLE 4287 G V V EN V EN, ON V EN, OFF VQ V rt tt V d, sat V R, sat Power on Reset Thermal Voltage Drop Shutdown at Input Undervoltage at Output Secondary Load Spike Bounce Shutdown AES02244 Figure 3 Time Response Semiconductor Group 10 1998-11-01 TLE 4287 G V V EN V EN, ON V EN, OFF VH V H, rel V H, hold VQ V Q, nom V rt Vd V dT V st V d, sat VR 8) 4) 1) 5) <1 s <10 s 2) 6) 7) 10) td tt 9) 3) V R, sat 1) Enable active 2) Hold inactive, pulled up by VQ 3) Power-ON reset 4) Hold active, clamped to GND by external MC 5) Enable inactive, clamped by int. pull-down resistor 6) Pulse width smaller than 1 s 7) Hold inactive, released by MC 8) Voltage controller shutdown 9) Output-low reset 10) No switch on via V E6 possible after E6 was released to V E6 > V E6, rel for more than 4 s AES02245 Figure 4 Enable and Hold Behavior Semiconductor Group 11 1998-11-01 TLE 4287 G Package Outlines P-DSO-14-4 (Plastic Dual Small Outline) 0.35 x 45 1.75 max 1.45 -0.2 0.19 +0.06 0.2 -0.1 4 -0.2 1) 1.27 0.35 +0.15 2) 14 0.1 0.2 14x 6 0.2 8 0.4 +0.8 1 7 8.75 -0.21) Index Marking 1) Does not include plastic or metal protrusion of 0.15 max. per side 2) Does not include dambar protrusion of 0.05 max. per side GPS05093 Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device Semiconductor Group 12 8 max. Dimensions in mm 1998-11-01 |
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