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| Features * Initialization of the Program Memory by DMA via the User Extension Interface (8-bit or * * * * * * * * * * * * * * 16-bit data format possible) or via the Synchronous Serial Input Link 1 (16-bit data format), SRAM and DRAM support Write access protection 40-bit User Extension interface Automatic conversion to and from a 32-bit data User Extension Interface Powerful 16-bit programmable versatile IO port featuring 2 input/output serial ports, up to 16-bit input/output parallel port, 4 pulse generators, 2 full duplex UART Four External interrupts Two 32-bit timers Watch Dog Two CRC accelerators (one for the input data stream, one for the output data stream) JTAG Maximum Operating frequency: 40MHz for ClkIn Power Consumption: 350 mA at 40MHz for ClkIn Latch Up immunity better than 100 MeV Designed on Atmel M62265E matrix sea of gates, into an MQFPF256 Radiation Tolerant DSP Peripheral Controller T7904E Introduction After Atmel successfully released the TSC21020F DSP, a code and pin compatible radiation hard version (including SEU hardening) of the ADI ADSP-21020, ASTRIUM have, under an ESA contract, developed a TSC21020F companion chip called DSP Peripheral Controller (DPC). This DSP Peripheral Controller is a generic support device suitable for on-board applications using the TSC21020F processor. The device implements those support functions which are required for the integration of the processor with other devices in a board design. It has been designed on the Atmel MG2RT Sea of Gates series, allowing to have a DPC chip hardened almost at the same level as the TSC21020F is, latch up and total dose wise. The T7904E is now available from Atmel as a standard ASIC. It is available in a 256pin MQFPF ceramic package. Rev. C-24-Aug-01 1 T7904E Figure 1. Functional block diagram of the T7904E Flexible IO port including: - serial links coupled to FIFO and / or CRC - parallel ports - UARTs - pulse genrators 16-bit flexible IO port WatchDog 4 * FIFO 256 x 32 2 32-bit Timers Interrupt Request to DSP Interrupt Controller External Interrupt Interface DPC internal registers User Extension Interface Control User Extension Interface Control Signal Internal Data Bus DSP Data Memory Interface Data Memory Sequencer DRAM Control Signal Register Selection Data Memory + control signal Address Decoder and Controls Data Memory Data Parity Generation Parity bit for Data Memory Internal Data Bus DSP Program Memory Interface Program Memory Address Decoder and Controls Program Memory Data Parity Generation Parity and Check bits for Program Memory Program Memory Sequencer Control Signal for Programs Memory Clock, Reset Clock + Reset JTAG Interface JTAG 2 Rev. C-24-Aug-01 Typical DSP core architecture based on the T7904E This section presents 2 typical DSP core architectures implementing the T7904E. DSP Processor Core Architecture: SRAM implementation This architecture is based on a parallel data bus approach. The DSP Processor core implements the following discrete circuits on a PCB: - - - - the TSC21020 DSP, the T7904E, SRAMs for both the Program Memory and the Data Memory (optional parity protection), transceivers on the address and data bus of the User Extension Interface (the control signal of this interface are directly generated by the T7904E). Figure 2. DSP Processor Core Architecture: SRAM implementation Address bus Control bus 48-bit data bus Parity bit Program Memory (SRAM implementation) JTAG Interface Program Memory Interface 21020 DSP Data Memory Interface Interrupt Request T7904E 16 bits Flexible IO Port FIFO Interface External Interrupts 16 bits Chip Select + Ctrl Parity bit 40-bit data bus Address bus Parity bit Buffer Data Address User Extension Interface Parity bit 40-bit data bus Control bus Address bus Data Memory (SRAM implementation) DSP Processor Core Architecture: DRAM implementation 3 This architecture is quite similar to the previous one, except that the Data Memory (DMBANK0) is made up of DRAMs. T7904E Rev. C-24-Aug-01 T7904E Figure 3. DSP Processor Core Architecture: DRAM implementation Address bus Control bus 48-bit data bus Parity bit Program Memory (SRAM implementation) JTAG Interface Program Memory Interface 21020 DSP Data Memory Interface Interrupt Request T7904E 16 bits Flexible IO Port FIFO Interface External Interrupts 20 bits Chip Select + Ctrl Parity bit 40-bit data bus Address bus Buffer Parity bit Data Address User Extension Interface Parity bit RAS*/CAS* 40-bit data bus Control bus Address bus Data Memory (DRAM implementation) 4 Rev. C-24-Aug-01 Functional description Program Memory initialization * The T7904E can initialize the program memory according to a predefined configuration. The configuration is selected by reading the PMD(1-0) data bus in the last cycle of the reset phase: 1. PMD(1-0) = 00: No Program Memory Initialization is performed by the T7904E, 2. PMD(1-0) = 01: The Program Memory Initialization is done via the data bus DMD(15-8) of IO Area 0 for the flat package T7904E: 8-bit width, 3. PMD(1-0) = 10: The Program Memory Initialization is done via the data bus DMD(23-8) of IO Area 0 for the flat package T7904E: 16-bit width, 4. PMD(1-0) = 11: The Program Memory Initialization is done via the Synchronous Serial Input Link 1: 16-bit width. * When the Program Memory Initialization is done via the IO Area 0 or via the Synchronous Serial Input Link 1, the 20 lsb of the first 6 x 8 bytes that are fetched, indicate the number of 48-bit words to be loaded in the Program Memory RAM. The least significant byte of the 48-bit words are fetched first. Each time a new byte is fetched, it is stored in the Program Register named PrgReg(47-0), the first byte in PrgReg(7-0), the second byte in PrgReg(15-8), the third byte in PrgReg(23-16), the fourth byte in PrgReg(31-24), the fifth byte in PrgReg(39-32) and the sixth byte in PrgReg(47-40). When 6 bytes are available in PrgReg, the T7904E performs a DMA access to write the content of PrgReg(47-0) into the Program Memory RAM. During the Program Memory initialization, the T7904E generates the parity bit PMPar over PMD(47-0) if required. As soon as the Program Memory initialization is completed, the DSP can set the bit SysAv in the General Configuration Register (GConfReg). The value of SysAv in GConfReg is reflected on the output signal SysAv to indicate the system is available. The Data Memory interface is organized into 4 identical banks DMBANK0, DMBANK1, DMBANK2, DMBANK3 corresponding to the Data Memory banks defined in the TSC21020 User's manual: 1. DMBANK0 is dedicated to the Data Memory RAM. The T7904E supports to implement DRAM devices or SRAM devices in the DMBANK0. DMBANK0 is a 40-bit data bus area, 2. DMBANK1 provides 4 identical areas which size is 4Mwords for User Extensions. Each area is decoded by a specific selection signal IOSel*(3-0). The T7904E implements its internal registers in DMBANK1. DMBANK1 is a 40bit data bus area except the T7904E internal register area which is a 32-bit data bus area, 3. DMBANK2 and DMBANK3 are 40-bit data bus areas. * The T7904E supports to perform a 32-bit data bus automatic conversion to and from 8-bit/16-bit data bus on the sub-areas IOArea0, IOArea1, IOArea2 and IOArea3 of DMANK1. The automatic conversion is enable by programming the General Configuration Register. The T7904E generates the DMAC(1-0) address bits during the automatic conversion. Only DMAC(1) is relevant in 16-bit mode. The 8-bit data bus device must be connected on DMD(15-8). The 16-bit data bus device must be connected on DMD(23-8). * * Memory Organization * 5 T7904E Rev. C-24-Aug-01 T7904E Table 1. T7904E Program Memory mapping Bank Designation Address (hex) 0 00000 Content Features * * * 48-bit data bus SRAM devices supported Parity protection option Write access protection if PMRAM1 not used Failing address support if PMRAM1 not used Accesses are performed in 1 clock cycle (+ 1 clock cycle for the write access if parity protection enable or write access protection is selected) 48-bit data bus SRAM devices supported Parity protection option Accesses are performed in 1 clock cycle (+ 1 clock cycle for the write access if parity protection) PMBANK0 Program Memory RAM (PMRAM0) * * * 0 FFFFF 1 00000 Program Memory RAM (PMRAM1) 7 FFFFF 8 00000 PMBANK1 Program Memory RAM 8 FFFFF 9 00000 Program Memory RAM F FFFFF * * * * Same as PMRAM0 Same as PMRAM1 6 Rev. C-24-Aug-01 Table 2. T7904E Data Memory mapping Bank Designation Address (hex) 00 000000 Content * * * DMBANK0 Data Memory RAM (DMRAM0) * * * 0 FFFFFF 01 000000 Data Memory RAM (DMRAM1) 1F FFFFFF 20 000000 * * * * * * * * DMBANK1 IO Area 0 * * * 20 3FFFFF 20 400000 20 7FFFFF 20 800000 20 BFFFFF 20 C00000 20 FFFFFF 21 000000 T7904E Internal Registers 3F FFFFFF 40 000000 IO Area 1 40-bit data bus SRAM and DRAM devices supported Parity protection option Write access protection if DMRAM1 not used Failing address support if DMRAM1 not used Accesses are performed in 1 clock cycle (+ 1 clock cycle for the write access if parity protection enable or write access protection is selected or DRAM implemented) 40-bit data bus SRAM devices supported Parity protection option Accesses are performed in 1 clock cycle (+ 1 clock cycle for the write access if parity protection enable) 40-bit data bus 4Mwords supported Parity protection option Programmable wait-state Programmable automatic conversion to and from 32-bit data bus width Failing address support Accesses are performed in 2 clock cycles + number of wait-states (+ 1 clock cycle for the write access if parity protection enable) Features Same as IO Area 0 IO Area 2 Same as IO Area 0 + Bus Ready Controlled IO Area 3 Same as IO Area 0 + Bus Ready Controlled * * * * * * 32-bit data bus Accesses are performed in 1 clock cycle Internal Parity Protection 40-bit data bus Programmable wait-state Parity protection option Failing address support Accesses are performed in 2 clock cycles + number of wait-states (+ 1 clock cycle for the write access if parity protection enable) DMBANK2 41 FFFFFF 42 000000 7F FFFFFF 80 000000 DMBANK3 81 FFFFFF 82 000000 FF FFFFFF Extended Area (EA20) * * Extended Area (EA21) Same as EA20 except no failing address support Extended Area (EA30) Same as EA20 Extended Area (EA31) Same as EA21 7 T7904E Rev. C-24-Aug-01 T7904E Dynamic memory access * The T7904E supports the DSP21020 to access DRAM devices in DMBANK0. The T7904E selects the DRAM or SRAM configuration by reading the PMD(2) data bus during the last cycle of the reset phase: 1. PMD(2) = 0: SRAM implementation 2. PMD(2) = 1: DRAM implementation. * The page size of the DRAM devices is done by reading the PMD(5-4) data bus in the last cycle of the reset phase: 1. PMD(5-4) = 00: 512 words, 2. PMD(5-4) = 01: 1024 words, 3. PMD(5-4) = 10: 2048 words, 4. PMD(5-4) = 11: 4096 words. * * When the reset phase is completed, the T7904E generates 8 DMRAS* before proper DRAM operation is achieved. DMRAS* is generated for Data Memory page mode initialization when DMPAGE input signal is asserted. During a page mode initialization, the T7904E generates DMTS* in order to three state Data Memory Bus of the DSP21020 and also DMACK to hold on the DSP21020. The T7904E generates the DRAM address bus according to the page size selection: 1. PMD(5-4) = 00: DRAM row addresses are on DMA(8-0), 2. PMD(5-4) = 01: DRAM row addresses are on DMA(9-0), 3. PMD(5-4) = 10: DRAM row addresses are on DMA(10-0), 4. PMD(5-4) = 11: DRAM row addresses are on DMA(11-0) * * DMCAS* is generated during a fast page mode access for the Data Memory Data DRAMs. The T7904E generates DMDWr* to manage a delayed write cycle on the DRAM devices that store the Data and the check bits or the parity bit of the Data Memory Interface. The T7904E provides automatic DRAM refresh according to a CAS* before RAS* refresh cycle. The refresh cycle period is set by programming the General Configuration Register One implicit extra wait-state is inserted during a DRAM write access. * * Memory protection * The Program Memory RAMs (PMBANK0 and PMBANK1) and the Data Memory RAMs (DMBANK0) can be protected with a parity bit. The protection is selected by reading the PMD(7-6) data bus in the last cycle of the reset phase: 1. PMD(7-6) = 00: No Parity protection, 2. PMD(7-6) = 01: Parity protection, 3. PMD(7-6) = 10: No Parity protection, 4. PMD(7-6) = 11: No Parity protection. * * The Data Memory RAM (DMBANK1, DMBANK2, DMANK3) can be protected with a parity bit. The protection is enable by programming UEConfReg. Parity: The T7904E implements: 8 Rev. C-24-Aug-01 1. a 48-bit even parity generator/checker for PMBANK0, PMBANK1. PMPar is the parity bit over the Program Memory data bus, 2. a 40-bit even parity generator/checker for DMBANK0. DMPar is the parity bit over the Data Memory data bus, 3. a 40-bit even parity generator/checker for DMBANK 1, 2 and 3. DMPar is the parity bit over the Data Memory data bus. In case of parity protection, the T7904E generates DMDWr* and PMDWr* during write accesses. In addition to that, the T7904E inserts one implicit wait state during the write accesses. In case of a parity error in PMBANK0 or PMBANK1, the T7904E sets the PMDataError flag (IPReg(1)) if GConfReg(0) is 0 or resets the system if GConfReg(0) is 1. The T7904E stores the failing Program Memory address and bank in FPMAReg. In case of a parity error in DMBANK0, DMBANK1, DMBANK2 or DMBANK3, the T7904E sets the DMDataError flag (IPReg(2)) if GConfReg(1) is 0 or reset the system if GConfReg(1) is 1. The T7904E stores the failing Program Memory address and bank in FDMAReg. The error detection mechanism do not overwrite FDMAReg and FDMAReg registers until they have been read. FPMAReg and FDMAReg are reset only by SysReset* assertion. Write access protection * The Program Memory RAMs (PMBANK0 and PMBANK1) and the Data Memory RAMs (DMBANK0) can be protected against write accesses. The write protection is selected by reading the PMD(8) data bit in the last cycle of the reset phase: 1. PMD(8) = 0: No write protection selected, 2. PMD(8) = 1: Write protection selected. * The T7904E can protect up to 4 zones in the Program Memory and/or in the Data Memory against write accesses. The area to protect against write access is defined on a 512 word basis area. Each zone is defined by 2 registers: the Access Protection Segment Base Register and the Access Protection Segment End Register that defines the beginning and the end of the area that must be protected When write access protection is selected, the T7904E generates DMDWr* and PMDWr* during the write accesses. In addition to that, the T7904E inserts one implicit wait state during write accesses. In case of a write access protection error in the Program Memory, the T7904E: 1. stores the failing address in FPMAReg, 2. sets the flag PMProtAreaError of the IPReg(3), 3. do not generate PMDWr*. * * * In case of a write access protection error in the Data Memory, the T7904E: 1. stores the failing address in FDMAReg, 2. sets the flag DMProtAreaError of the IPReg(4), 3. do not generate DMDWr*. 9 T7904E Rev. C-24-Aug-01 T7904E User Extension Interface The User Extension Interface is a 40-bit data interface which consists in: 1. The pre-decoded IO Area in DMBANK1: IO Area 0 selected by IOSel0*, IO Area 1 selected by IOSel1*, IO Area2 selected by IOSel2* and IO Area 3 selected by IOSel3*, 2. DMBANK2, 3. DMBANK3. * The T7904E provides: 1. a write signal UEWr* and a read signal UERd* to allow connection of user extensions on the User Extension Interface without any glue logic, 2. a Ready signal UERdy2 (resp. UERdy3*) dedicated to IO Area2 (resp. IO Area3) for the users that require extended time in addition to the wait-states programmed in UEConfReg to complete an access, 3. a user extension enable signal UEEn* to enable the external user extension buffers. UEEn* is generated when accessing IO Area0, IO Area 1, IO Area2, IO Area 3, DMBANK2 or DMBANK3. * The T7904E provides UEConfReg register to program the number of wait states required for the IO Area 0 access, the IO Area 1 access, the IO Area 2 access, the IO Area 3 access, the DMBANK2 and the DMBANK3. A bus time out function of 256 system clocks is provided by the T7904E. The bus time out counter starts when the access is initiated in IOArea2 or IOArea3 (falling edge of DMRd* or DMWr*). If UERdy2 or UERdy3* are not asserted before 256 system clock cycles, the T7904E rises the flag BusTimeOut of the IPReg(9). The T7904E stores the failing Data Memory address in FDMAReg. The Watchdog function consists of a Watchdog Timer. It is possible to program the timer by setting a specific value in the Watchdog Program Register. The register consists of one scaler field (bit(23-16)) and one counter field (bit(15-0)) corresponding directly to the scaler field and to the counter field of the watchdog timer. Reading the Watchdog Program Register returns the current value of the counters. As soon as the Program Memory Initialization is completed, the timer is enabled and starts running with the default value of the scaler and of the counter. A 6-bit implicit pre-scaler is performed on the scaler. By writing the Trap Door Set Register after reset, the timer is disabled. After the disabling of the watchdog timer, a write operation in the Watchdog Program Register starts the counter counting with the value of the specified field. The Watchdog cannot be disabled when the Watchdog Program Register has been written. If the timer is refreshed by writing the Watchdog Program Register before the counter reaches zero, the timer restarts counting with the new delay value. If the timer is not refreshed before the counter reaches zero, then the flag WatchdogTimeOut is set in IPReg(0) and the timer restarts counting a time out period programmed in the field (31-24) of the Watchdog Program Register. Then if the timer is reprogrammed before the time out period elapses again, the timer restarts counting with the new delay value. But if the timer is not reprogrammed before the time-out period elapses, then reset is asserted. * Watchdog * * * 10 Rev. C-24-Aug-01 Timer * The T7904E provides 2 programmable timers. When enable, the timer decrements a 32-bit counter which starting value n is programmed in the Timer Program Register (TPReg). Once n ClkOut clock cycles are elapsed, the flag TimerExp1 (resp. TimerExp2) is set in IPReg(8) (resp. IPReg(12)). Each timer is controlled separately by programming the Timer Control Register (TCReg) : 4. TCiEn of TCReg enables the counter to start counting. 5. ReloadTCiEn selects the mode of the counter: Once n clock cycles are elapsed, either the timer is reloaded with the programmed value n in TPReg and then it restarts or the timer stops. 6. LoadTCi restarts the timer with the programmed value in TPReg if the timer is enable. * * It is possible to cascade timer1 and timer2 if CascadeEnable is set in TCReg. In this configuration, timer1 is not set TimerExp1. The 64-bit timer sets TimerExp2 when the timer reaches zero. When the timer1 and timer2 are cascaded, the 64-bit timer is fully controlled by TC2En, ReloadTC2En and LoadTC2 of TCReg. The T7904E provides a versatile IO port on the VIOP(15-0) bus. It is possible to define VIOP(15-0) as: Versatile IO port * 1. 2 synchronous serial links (input and output), 2. 2 asynchronous serial links (input and output), 3. Up to 16-bit input port, 4. Up to 4-bit dynamic output port + 12-bit static output port. * The configuration of the VIOP(15-0) is performed by programming the following internal registers: 1. the serial link configuration register (SLConfReg), 2. the parallel input port configuration register (PIPConfReg), 3. the parallel output port configuration register (POPConfReg). * For the configuration of VIOP(15-0), SLConfReg has the highest priority, then PIPConfReg, and last POPConfReg has the lowest priority. The SOL configuration bits in SLConfReg have a highest priority than the UART configuration bits. The T7904E provides 2 synchronous serial input links (SIL0 and SIL1) featuring an input data valid strobe (DVALI), an input clock (CKI) and an input data (DI) that are defined by SLConfReg. As soon as DVALI is de-asserted, the SIL is reset. The MSB is received first. 8, 16 and 32-bit data format are possible for the serial input links by programming SLConfReg. Depending on the programation of SLConfReg (16 bit or 32 bit serial link), when DVALI is de-asserted, the being received byte(s) are filled with zeros to get a 16 or 32-bit word. The T7904E provides the data register of the 2 input serial links named Serial Link Input Register 0 and Serial Link Input Register 1. It is possible to clear the Input serial link including the associated FIFO flag by programming the Serial Link Status Register (SLStatusReg). SIL0 is coupled to a 258 x 32 words FIFO named FIFO00. The flag Empty FIFO is set when FIFO00 is empty (no word has been received). The flag Full FIFO is set when FIFO00 is full. SIL1 can be coupled to a 258 x 32 word FIFO named FIFO10. Synchronous input serial * link * * * * * 11 T7904E Rev. C-24-Aug-01 T7904E * An interrupt is generated when a word has been received on SIL1 and the flag Data Ready 1 in SLStatusReg is set. The T7904E provides 2 synchronous serial output links (SOL0 and SOL1) featuring an output data valid strobe (DVALO), an input data ready signal (DR), an output clock (CKO), an output data (DO) and an output abort data transfer signal (AT) that is defined by SLConfReg. The MSB is transmitted first. 8, 16 and 32-bit data format is possible for the serial output links by programming SLConfReg. The clock rate of the 2 synchronous serial output links is defined by the Serial Link Clock Configuration Register (SLCConfReg). It is possible to abort a data transfer of the output serial link by programming the Serial Link Status Register (SLStatusReg), then the output abort data transfer signal (AT) is asserted until a next transfer is initialized and the output serial link including the associated FIFO flag are reset. SOL0 is coupled with a 256 x 32 words FIFO named FIFO01. The flag Full FIFO is set when FIFO01 is full. The flag Empty FIFO is set when SOL0 has no word to send. SOL1 can be coupled to a 256 x 32 word FIFO named FIFO11. An interrupt is generated when a word has been sent by SOL1 and the flag Transmit Register Empty (TRE1) in SLStatusReg is set. The T7904E provides up to 16 bit input port that are enabled by programming the Parallel Input Port Configuration Register (PIPConfReg). The T7904E provides the data register of the Parallel Input Port named Parallel Input Port Register. The input data must be asserted at least 2 ClkOut periods to be taken into account. An interrupt is generated when a change is detected on the parallel input port. The T7904E provides up to 16-bit output port which consists in 4 independent pulse generators + 12 discret outputs. The output port is enabled by programming the Parallel Output Port Configuration Register (POPConfReg). It is possible to define each pulse generator as a one shot pulse generator or as a cyclic pulse generator by programming POPConfReg. It is possible to define the polarity of the pulse by programming the Parallel Output Port Polarity Register (POPPReg). The delay and the length of each pulse are programmable in the Pulse Delay Control Register and in the Pulse Length Control Register. The T7904E provides the Parallel Output Register that allows to start or restart each pulse generator. It is possible to read the value of the discrete output port through the Parallel Output Register. The pulse generator on VIOP(15) can count even if disable in the POPConfReg. The pulse generator on VIOP(15) set the flag IPReg(31) in the Interrupt Pending Register when the pulse is elapsed The T7904E provides two full duplex Universal Asynchronous Receiver Transmitter (UART). The data format of the UARTs is 8-bit word. It is possible to choose between even or odd parity or no parity, and between one or two stop bits by programming the SLConfReg. Synchronous output serial link * * * * * * Parallel input port * * * Parallel output port * * * * * * * UART * 12 Rev. C-24-Aug-01 * * * * It is possible to interface the UART through an 8-bit data register or 32-bit data by programming the SLConfReg. The baud rate of the UART is set by programming the SLConfReg. The T7904E provides a dedicated UART register for each UART (UARTReg1 associated to UART1, UARTReg2 associated to UART2). To output a byte on the serial output (LSB first), the following procedure must be followed. First, the UART Status Register (UARTStatusReg) must be read to check that the transmitter register is empty. Then the word (8-bit or 32-bit) to be output is written in the right UART Register (UARTReg1 or 2). The word will be then automatically converted in a serial form also adding start bit, parity bit and stop bit if required. When the word has been sent on the serial interface a flag UARTRxTx is set in IPReg(11). ClockFrequency Scaler (LSB first), parity and stop bitThe receiver converts serial start bit, data word = ----------------------------------------------------------------------- into Baudrate ( 2 - UBR ) ) ( 16 parallel form and loads the data (8-bit or 32-bit) in the right UARTReg. Framing error (FE), parity error (PE) and overrun error (OE) are indicated in the UART Status Register (UARTStatusReg) and rise the UARTError flag in IPReg(10). A correct received word is indicated by Data Ready bit in the UARTStatusReg. When a word is received on the serial interface, a flag UARTRxTx (IPReg(11)) is issued. When the UARTReg is read, the corresponding FE, PE, OE and DataReady flag in the UARTStatusReg are cleared. It is possible to clear an UART by writing the Clear UART bit in UARTStatusReg. The formula to calculate the value of the scaler is: ClockFrequency Scaler = ----------------------------------------------------------------------( 16 Baudrate ( 2 - UBR ) ) * * * FIFO * * * The T7904E provides 4 FIFOs named FIFO00, FIFO01, FIFO10 and FIFO11. FIFO00 is permanently coupled to SIL0, FIFO01 is permanently coupled to SOL0. Each FIFO provides an empty, half full and full flag. Each FIFO flag can rise a flag in the Interrupt Pending Register when set. The mode of the FIFO10 and FIFO11 is defined by the FIFO Configuration Register (FIFOConfReg). Bit 0 of FIFOConfReg has the highest priority in the configuration of FIFO10. Bit 3 of FIFOConfReg has the lowest priority in the configuration of FIFO10. Bit 4 of FIFOConfReg has the highest priority in the configuration of FIFO11. Bit 7 of FIFOConfReg has the lowest priority in the configuration of FIFO11. Bit 2 and 3 have a highest priority than bit 4 and 5. Table 3. FIFO mode description FIFO 10 Mode Description FIFO10 (258 words of 32bit) coupled to Synchronous Serial Input Link 1: * * As soon as a word is received in SSIL 1, then the received word is written in FIFO10 if the FIFO is not full, The FIFO is read by the DSP thanks to FIFOOutReg10. FIFO 11 Mode Description FIFO11 (256 words of 32bit) coupled to Synchronous Serial Output Link 1: * * FIFO11 is written by the DSP thanks to FIFOInReg11, As long as the FIFO is not empty, the words are sent by SOL1. FIFO10 (258 words of 32bit) in Stand alone Mode (Read and write operations performed by DSP): * * FIFOInReg10 is controlled by DSP, FIFOOutReg10 is controlled by DSP. FIFO11 (258 words of 32bit) in Stand alone Mode (Read and write operations performed by DSP): * * FIFOInReg11 is controlled by DSP, FIFOOutReg11 is controlled by DSP. 13 T7904E Rev. C-24-Aug-01 T7904E CRC accelerator * The T7904E provides 2 16-bit field cyclic redundant code (CRC) accelerators generated with the polynom X16 + X12 + X5 + 1 with the shift register being initialized to all ones before processing each frame. The CRC accelerators are enabled when they are written (CRC0 register, CRC1 register). The CRC accelerators are initialized when they are read (CRC0 register, CRC1 register). * Table 4. CRC mode description CRC 0 Mode Description CRC0 linked to Synchronous Serial Input Link 0: As long as DVALI is asserted, the received bits plus the 16 check bits at SIL0 input are clocked into the input of the CRC accelerator. For an error-free block, the CRC contents must be zero. As soon as DVALI is de-asserted, the content of the CRC is stored in the CRC register and the CRC accelerator is initialized. CRC 1 Mode Description CRC1 linked to Synchronous Serial Output Link 0: As long as SOL0 input buffer is not empty, the CRC accelerator is fed by the SOL0 output. As soon as SOL0 input buffer is empty, the input of the CRC accelerator is clamped to zero and the 16 check bits are emitted without any gap. Reset * Reset* is generated on SysReset* assertion, on WatchDogReset, on Error Reset or by writing the Software Reset Register (SRReg). The reset cause is memorized in GConfReg(24-23). The Reset* signal is asserted at least 32 system clock cycles. The System Clock ClkOut is provided during reset phase. The SysAv bit GConfReg(22) is reset: 1. When Reset* is asserted by the T7904E, 2. When a non correctable error is detected in the Program Memory Bank or in the Data Memory Bank, 3. When a write protection access is done in a write protected area, 4. When an internal hardware error in detected in the T7904E. * * Interrupts * The T7904E provides: 1. an Interrupt Pending Register (IPReg) that memorizes all the interrupt sources, 2. an Interrupt Vector Register (IVReg) identifying among all the interrupts that are memorized in IPReg, the interrupt that has the highest priority (lsb). When IVReg is read, the corresponding interrupt is cleared in IPReg. As soon as a bit in IPReg is set high, the T7904E asserts IRQ* if the interrupt is not masked 3. an Interrupt Mask Register (IMReg) that allows to mask each interrupt individually. A masked interrupt is set in IPReg but is not be prioritized in IVReg and do not assert IRQ*. When writing IPReg, the bit in IPReg that are equal to one resets the corresponding interrupt in IPReg 4. an Interrupt Force Register (IFReg) that allows to force each interrupt individually. * The T7904E provides 4 External Interrupts input signals that are monitored by IPReg. The external interrupts are edge or level sensitive programmable. It is possible to set the polarity of the external interrupts by programming GConfReg. 14 Rev. C-24-Aug-01 Table 5. Priority level of all the interrupt sources Interrupt source Watch Dog Time Out Parity Error in PMBANK0. Parity Error in DMBANK0, 1, 2 or 3. Write Access Protection Error in PMBANK0. Write Access Protection Error in DMBANK0. Internal Hardware Error External Interrupt 0 External Interrupt 1 Timer1 has expired Bus Time Out Error on the User Extension Interface UART Error UARTRXTX : A data word has been correctly received by the UART or a word has been sent. Timer2 has expired External Interrupt 2 External Interrupt 3 Not defined Not defined A word has been correctly received or a word has been sent (Synchronous Serial Link 1) A change has been detected on Parallel Input Port EF00 Empty Flag of FIFO 00 (SSIL link0) HF00 Half Full Flag of FIFO 00 (SSIL link0) FF00 Full Flag of FIFO 00 (SSIL link0) EF01 Empty Flag of FIFO 01 (SSOL link0) HF01 Half Full Flag of FIFO 01 (SSOL link0) FF01 Full Flag of FIFO 01 (SSOL link0) EF10 Empty Flag of FIFO 10 HF10 Half Full Flag of FIFO 10 FF10 Full Flag of FIFO 10 Priority level 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Interrupt vector value 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 0x80 0x88 0x90 0x98 0xA0 0xA8 0xB0 0xB8 0xC0 0xC8 0xD0 0xD8 15 T7904E Rev. C-24-Aug-01 T7904E Interrupt source EF11 Empty Flag of FIFO 11 HF11 Half Full Flag of FIFO 11 FF11 Full Flag of FIFO 11 Pulse Generator 15 elapsed Priority level 28 29 30 31 Interrupt vector value 0xE0 0xE8 0xF0 0xF8 Clock JTAG * * * The External Input clock ClkIn is divided by 2 to get ClkOut. The T7904E implements the boundary scan circuitry in compliance with IEEE Standard Test Access Port and Boundary-Scan Architecture. The boundary register is 629 bits long. The function of each position in the scan path is given in annex 1. All T7904E internal registers are parity protected. If an internal parity error is detected, then the T7904E sets the flag HWError (IPReg(5)) if GConfReg(2) is 0 or reset the system if GConfReg(2) is 1. It is possible to lock all the configuration registers of the T7904E by writing the lock register with all ones, and to unlock all the configuration registers of the T7904E by writing the lock register with all zero. The T7904E register address map is given in the following table. Register description * * * Table 6. Register Description T7904E Register Access Protection Segment 0 Base Register (APS0Breg) Access Protection Segment 1 Base Register (APS1Breg) Access Protection Segment 2 Base Register (APS2Breg) Access Protection Segment 3 Base Register (APS3Breg) Access Protection Segment 0 End Register (APS0EReg) Access Protection Segment 1 End Register (APS1EReg) Access Protection Segment 2 End Register (APS2EReg) Access Protection Segment 3 End Register (APS3EReg) General Configuration Register (GConfReg) UE Configuration Register (UEConfReg) Failing Data Memory Address Register (FDMAReg) Failing Program Memory Address Register (FPMAReg) Interruption Vector Register (IVReg) Interruption Pending Register (IPReg) Interruption Mask Register (IMReg) Interruption Force Register (IFReg) Address (hex) 21 000000 21 000001 21 000002 21 000003 21 000004 21 000005 21 000006 21 000007 21 000008 21 000009 21 00000A 21 00000B 21 00000C 21 00000D 21 00000E 21 00000F Lock Possible Possible Possible Possible Possible Possible Possible Possible Possible Possible Possible Possible Not Applicable Possible Possible Possible 16 Rev. C-24-Aug-01 T7904E Register Software Reset Register (SSReg) Timer 1 Program Register (T1Preg) Timer 2 Program Register (T2Preg) Timer Control Register (TCReg) Watchdog Program Register (WPReg) Watchdog Trap Door Set Register (WTDSReg) Serial Link Configuration Register (SLConfReg) Serial Link Clock Configuration Register (SLCConfReg) Parallel Input Port Configuration Register (PIPConfReg) Parallel Output Port Configuration Register (POPConfReg) Parallel Output Port Polarity Register (POPPReg) Serial Link Input Register 0 (SLIReg0) Serial Link Input Register 1 (SLIReg1) Serial Link Output Register 0 (SLOReg0) Serial Link Output Register 1 (SLOReg1) Serial Link Status Register (SLStatusReg) Parallel Input Port Register (PIPReg) Parallel Output Port Register (POPReg) Lock Register Not defined Pulse Delay Control Register 12 (PDCReg 12) Pulse Delay Control Register 13 (PDCReg 13) Pulse Delay Control Register 14 (PDCReg 14) Pulse Delay Control Register 15 (PDCReg 15) Not defined Pulse Length Control Register 12 (PLCReg 12) Pulse Length Control Register 13 (PLCReg 13) Pulse Length Control Register 14 (PLCReg 14) Pulse Length Control Register 15 (PLCReg 15) UART Receive Transmit Register 1 (UARTReg1) UART Receive Transmit Register 2 (UARTReg2) UART Status Register (UARTStatusReg) Not defined CRC0 Register (CRCReg0) CRC1 Register (CRCReg1) Address (hex) 21 000010 21 000011 21 000012 21 000013 21 000014 21 000015 21 000016 21 000017 21 000018 21 000019 21 00001A 21 00001B 21 00001C 21 00001D 21 00001E 21 00001F 21 000020 21 000021 21 000022 21 000023- 21 00002E 21 00002F 21 000030 21 000031 21 000032 21 000033-21 00003E 21 00003F 21 000040 21 000041 21 000042 21 000043 21 000044 21 000045 21 000046 21 000047 21 000048 Lock Not Possible Possible Possible Not Possible Not Possible Not Possible Possible Possible Possible Possible Possible Not Applicable Not Applicable Not Possible Not Possible Not Possible Not Applicable Not Possible Not Possible Possible Possible Possible Possible Possible Possible Possible Possible Not Possible Not Possible Not Possible Not Possible Not Possible 17 T7904E Rev. C-24-Aug-01 T7904E T7904E Register FIFO Configuration Register (FIFOConfReg) FIFO 10 Input Register (FIFOInReg10) FIFO 10 Output Register (FIFOOutReg10) FIFO 11 Input Register (FIFOInReg11) FIFO 11 Output Register (FIFOOutReg11) Address (hex) 21 000049 21 00004A 21 00004B 21 00004C 21 00004D Lock Possible Not Possible Not Applicable Not Possible Not Applicable Table 7. Access Protection Segment 0 Base Register (APS0Breg) Bits 15-0 Name SegBase 0 Reset Value 0000 Function Start Address of the Access Protection Segment 0. Only the 11 lsb are relevant for the Program Memory Interface, SegBase0(15-12) must be set to " 0000 ". Selection of the Memory BANK to protect : 16 Bank 0 Program Bank when 0 Data Bank when 1 17 APE 0 Access Protection Enable when 1 r/w r/w r/w r/w Table 8. Access Protection Segment 1 Base Register (APS1Breg) Bits 15-0 Name SegBase 1 Reset Value 0000 Function Start Address of the Access Protection Segment 1. Only the 11 lsb are relevant for the Program Memory Interface, SegBase1(15-12) must be set to " 0000 ". Selection of the Memory BANK to protect : 16 Bank 0 Program Bank when 0 Data Bank when 1 17 APE 0 Access Protection Enable when 1 r/w r/w r/w r/w Table 9. Access Protection Segment 2 Base Register (APS2Breg) Bits 15-0 Name SegBase 2 Reset Value 0000 Function Start Address of the Access Protection Segment 2. Only the 11 lsb are relevant for the Program Memory Interface, SegBase2(15-12) must be set to " 0000 ". Selection of the Memory BANK to protect : 16 Bank 0 Program Bank when 0 Data Bank when 1 17 APE 0 Access Protection Enable when 1 r/w r/w r/w r/w 18 Rev. C-24-Aug-01 Table 10. Access Protection Segment 3 Base Register (APS3Breg) Bits 15-0 Name SegBase 3 Reset Value 0000 Function Start Address of the Access Protection Segment 3. Only the 11 lsb are relevant for the Program Memory Interface, SegBase3(15-12) must be set to " 0000 ". Selection of the Memory BANK to protect : 16 Bank 0 Program Bank when 0 Data Bank when 1 17 APE 0 Access Protection Enable when 1 r/w r/w r/w r/w Table 11. Access Protection Segment 0 End Register (APS0EReg) Bits 15-0 Name SegEnd 0 Reset Value 0000 Function End Address of the Access Protection Segment 0. Only the 11 lsb are relevant for the Program Memory Interface. r/w r/w Table 12. Access Protection Segment 1 End Register (APS1EReg) Bits 15-0 Name SegEnd 1 Reset Value 0000 Function End Address of the Access Protection Segment 1. Only the 11 lsb are relevant for the Program Memory Interface. r/w r/w Table 13. Access Protection Segment 2 End Register (APS2EReg) Bits 15-0 Name SegEnd 2 Reset Value 0000 Function End Address of the Access Protection Segment 2. Only the 11 lsb are relevant for the Program Memory Interface. r/w r/w Table 14. Access Protection Segment 3 End Register (APS3EReg) Bits 15-0 Name SegEnd 3 Reset Value 0000 Function End Address of the Access Protection Segment 3. Only the 11 lsb are relevant for the Program Memory Interface. r/w r/w 19 T7904E Rev. C-24-Aug-01 T7904E Table 15. General Configuration Register (GConfReg) Bits Name Reset Value Function Interrupt or reset in case of Parity Error in PMBANK0: 0 IntOrRst0 0 0 : Reset 1 : Interrupt Interrupt or reset in case of Parity Error in DMBANK0, 1, 2 or 3 : 1 IntOrRst1 0 0 : Reset 1 : Interrupt Interrupt or reset in case of Internal Parity Error: 2 IntOrRst2 0 0 : Reset 1 : Interrupt 32-bit Automatic Conversion on IO Area0 : 00 : No conversion 4-3 ACIO0 00 01 : 8-bit conversion 10 : 16-bit conversion 11 : No conversion 32-bit Automatic Conversion on IO Area1 : 00 : No conversion 6-5 ACIO1 00 01 : 8-bit conversion 10 : 16-bit conversion 11 : No conversion 32-bit Automatic Conversion on IO Area2 : 00 : No conversion 8-7 ACIO2 00 01 : 8-bit conversion 10 : 16-bit conversion 11 : No conversion 32-bit Automatic Conversion on IO Area3 : 00 : No conversion 10-9 ACIO3 00 01 : 8-bit conversion 10 : 16-bit conversion 11 : No conversion External Interrupt 0 sensitivity mode 11 EISM0 0 0 : level sensitive 1 : edge sensitive External Interrupt 1 sensitivity mode 12 EISM1 0 0 : level sensitive 1 : edge sensitive External Interrupt 2 sensitivity mode 13 EISM2 0 0 : level sensitive 1 : edge sensitive External Interrupt 3 sensitivity mode 14 EISM3 0 0 : level sensitive 1 : edge sensitive r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 20 Rev. C-24-Aug-01 Bits Name Reset Value Function External Interrupt 0 polarity mode r/w 15 EIPM0 0 0 : Falling edge or low level active 1 : Rising edge or high level active External Interrupt 1 polarity mode r/w 16 EIPM1 0 0 : Falling edge or low level active 1 : Rising edge or high level active External Interrupt 2 polarity mode r/w 17 EIPM2 0 0 : Falling edge or low level active 1 : Rising edge or high level active External Interrupt 3 polarity mode r/w 18 EIPM3 0 0 : Falling edge or low level active 1 : Rising edge or high level active Memory Protection Enable for the Program Memory and DMBANK0 : 0 : the memory protection is done according to PMD(7-6) 1 : disable the memory protection. DRAM refresh period : 00 : Refresh is performed every 160 clock periods r/w 19 MPE 0 r/w 21-20 DRP 11 01 : Refresh is performed every 128 clock periods 10 : Refresh is performed every 96 clock periods 11 : Refresh is performed every 64 clock periods r/w 22 SysAv 0 System available when high Reset Cause : 00 : System Reset r/w 24-23 Reset Cause 01 : Error Reset 10 : Watch Dog Reset 11 : Software Reset r 21 T7904E Rev. C-24-Aug-01 T7904E Table 16. UE Configuration Register (UEConfReg) Bits Name Reset Value Function Protection Option for the IO Area 0 : 00 : No Parity protection 1-0 POIO0 00 01 : Parity protection 10 : No Parity protection 11 : No Parity protection Protection Option for the IO Area 1 : 00 : No Parity protection 3-2 POIO1 00 01 : Parity protection 10 : No Parity protection 11 : No Parity protection Protection Option for the IO Area 2 : 00 : No Parity protection 5-4 POIO2 00 01 : Parity protection 10 : No Parity protection 11 : No Parity protection Protection Option for the IO Area 3 : 00 : No Parity protection 7-6 POIO3 00 01 : Parity protection 10 : No Parity protection 11 : No Parity protection Protection Option for the DMBank2 : 00 : No Parity protection 9-8 PODMB2 00 01 : Parity protection 10 : No Parity protection 11 : No Parity protection Protection Option for the DMBank3 : 00 : No Parity protection 11-10 PODMB3 00 01 : Parity protection 10 : No Parity protection 11 : No Parity protection 14-12 17-15 20-18 23-21 26-24 29-27 WSIO0 WSIO1 WSIO2 WSIO3 WSB2 WSB3 111 000 000 000 000 000 Wait State Number for the IO Area 0 Wait State Number for the IO Area 1 Wait State Number for the IO Area 2 Wait State Number for the IO Area 3 Wait State Number for the DMBANK 2 Wait State Number for the DMBANK 3 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 22 Rev. C-24-Aug-01 Table 17. Failing Data Memory Address Register (FDMAReg) Bits 24-0 Name FDMA Reset Value 0000000 Function Failing Data Memory Address Failing Data Memory Bank : 00 : Bank 0 26-25 FDMBK 00 01 : Bank 1 10 : Bank 2 11 : Bank 3 r/w r/w r/w Table 18. Failing Program Memory Address Register (FPMAReg) Bits 19-0 Name FPMA Reset Value 00000 Function Failing Program Memory Address Failing Program Memory Bank : 20 FDMBK 0 0 : Bank 0 1 : Bank 1 r/w r/w r/w 23 T7904E Rev. C-24-Aug-01 T7904E Table 19. Interruption Pending Register (IPReg) Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Name WatchDogTimeOut PMDataError DMDataError PMProtAreaError DMProtAreaError HWError ExtIt0 ExtIt1 Timer 1 BusTimeOutError UARTError UARTRxTx Timer 2 ExtIt2 ExtIt3 Not defined Not defined SSLRxTx PIC EF00 HF00 FF00 EF01 HF01 FF01 EF10 HF10 Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 Generated by the synchronous serial link 1 when a word has been correctly received or sent. Parallel Input Port Change. Empty Flag FIFO 00 (SSIL link0). Half Full Flag FIFO 00 (SSIL link0). Full Flag FIFO 00 (SSIL link0). Empty Flag FIFO 01 (SSOL link0). Half Full Flag FIFO 01 (SSOL link0). Full Flag FIFO 01 (SSOL link0). Empty Flag of FIFO 10. Half Full Flag of FIFO 10. Function Generated by the WatchDog when the counter has elapsed. Parity Error in Program Memory. Parity Error in Data Memory. Access Protection Error in Program Memory. Access Protection Error in Data Memory. Internal Hardware Error. External interrupt 0. External interrupt 1. Generated by the Timer 1 when it reaches zero. Bus Time Out Error. No Ready has been received. Generated by the UARTs if an error is detected. Generated by the UARTs each time a word has been correctly received or sent. Interrupt generated by the Timer 2 when it reaches zero. External interrupt 2. External interrupt 3. r/w r r r r r r r r r r r r r r r r r r r r r r r r r r r 24 Rev. C-24-Aug-01 Bits 27 28 29 30 31 Name FF10 EF11 HF11 FF11 GP15 Reset Value 0 1 0 0 0 Full Flag of FIFO 10. Empty Flag of FIFO 11. Half Full Flag of FIFO 11. Full Flag of FIFO 11. Pulse Generator 15 interrupt. Function r/w r r r r r Table 20. Interruption Mask Register (IMReg) Bits Name Reset Value Masked interrupts : bit 0 = 0 : IPReg(0) is not masked 31-0 IM FFFF bit 0 = 1 : IPReg(0) is masked ...... bit 31 = 0 : IPReg(31) is not masked bit 31 = 1 : IPReg(31) is masked r/w Function r/w Table 21. Interruption Force Register (IFReg) Bits Name Reset Value Function Forced interrupts : bit 0 = 0 : no action 31-0 IF 0000 bit 0 = 1 : IPReg(0) is set ...... bit 31= 0 : no action bit 31 = 1 : IPReg(31) is set w r/w Software Reset Register (SSReg) Write only register. Writing this register asserts Reset* Table 22. Timer 1 Program Register (T1PReg) Bits 31-0 Name TC1 Reset Value 0xFFFFFFFF Function Programmed value of the down counting 32-bit counter 1 r/w w Reading T1PReg returns the current value of the counter. Table 23. Timer 2 Program Register (T2PReg) Bits 31-0 Name TC2 Reset Value 0xFFFFFFFF Function Programmed Value of the down counting 32-bit counter 2 r/w w Reading T2PReg returns the current value of the counter. 25 T7904E Rev. C-24-Aug-01 T7904E Table 24. Timer Control Register (TCReg) Bits Name Reset Value Timer Counter 1 Enable : 0 TC1En 0 1 : Enable counting 0 : Hold Timer Counter Value Timer Counter 1 Reload Enable : 1 ReloadTC1En 0 1 : Reload Counter when zero and restart 0 : Stop Counter when zero Timer Counter 1 Load : 2 LoadTC1 0 1 : Load Counter with programmed value and restart if enable 0 : No function Timer Counter 2 Enable : 3 TC2En 0 1 : Enable counting 0 : Hold Timer Counter Value Timer Counter 2 Reload Enable : 4 ReloadTC2En 0 1 : Reload Counter when zero and restart 0 : Stop Counter when zero Timer Counter 2 Load : 5 LoadTC2 0 1 : Load Counter with programmed value and restart if enable 0 : No function 6 Cascade 0 Cascade Timer 1 and Timer 2 to made a 64-bits timer when 1 (Timer 1 LSB, Timer 2 MSB) r/w w r/w r/w w r/w r/w Function r/w Table 25. Watchdog Program Register (WPReg) Bits 15-0 23-16 31-24 Name WDC WDS WDR Reset Value FFFF FF FF Preset 16-bit counter value Preset 8-bit scaler value Preset 8-bit reset counter value Function r/w r/w r/w r/w Reading WPReg returns the current value of the counter. Watchdog Trap Door Set Register (WTDSReg) Write only register with any data. Writing this register after reset but before the watchdog has elapsed will disable the watchdog. The watchdog will stay disabled until it is reprogrammed by writing WPReg 26 Rev. C-24-Aug-01 Table 26. Serial Link Configuration Register (SLConfReg) Bits Name Reset Value Function Protocol selection of Serial Link 0 : 0 PROTO0 0 0 : not TTC-B01 1 : Slave TTC-B01 Synchronous Serial Input Link 0 Definition : 00 : Serial Input Link 0 disable 01 : 8-bit Serial Input Link 0 enable 10 : 16-bit Serial Input Link 0 enable 2-1 SSIL0 00 11 : 32-bit Serial Input Link 0 enable VIOP(0) : DVALI0 (input data valid strobe) VIOP(1) : CKI0 (input clock) VIOP(2) : DI0 (input data) 3 Not defined 0 Synchronous Serial Input Link 1 Definition : 00 : Serial Input Link 1 disable 01 : 8-bit Serial Input Link 1 enable 10 : 16-bit Serial Input Link 1 enable 5-4 SSIL1 10 11 : 32-bit Serial Input Link 1 enable VIOP(3) : DVALI1 (input data valid strobe) VIOP(4) : CKI1 (input clock) VIOP(5) : DI1 (input data) Synchronous Serial Output Link 0 Definition : 00 : Serial Output Link 0 disable 01 : 8-bit Serial Output Link 0 enable 10 : 16-bit Serial Output Link 0 enable 11 : 32-bit Serial Output Link 0 enable 7-6 SSOL0 00 VIOP(6) : DVALO0 (output data valid strobe) VIOP(7) : DR0 (input data ready strobe) VIOP(8) : CKO0 (output clock) VIOP(9) : DO0 (output data) VIOP(10) : AT0 (output abort data transfer) Synchronous Serial Output Link 1 Definition : 00 : Serial Output Link 1 disable 01 : 8-bit Serial Output Link 1 enable 10 : 16-bit Serial Output Link 1 enable 11 : 32-bit Serial Output Link 1 enable 9-8 SSOL1 00 VIOP(11) : DVALO1 (output data valid strobe) VIOP(12) : DR1 (input data ready strobe) VIOP(13) : CKO1 (output clock) VIOP(14) : DO1 (output data) VIOP(15) : AT1 (output abort data transfer) r/w r/w r/w r/w r/w r/w r/w 27 T7904E Rev. C-24-Aug-01 T7904E Bits Name Reset Value UART Mode : 10 UARTMODE 0 0 : 8-bit data interface 1 : 32-bit data interface Asynchronous Serial Link 1 Enable 0 : disable 11 UART 1 0 1 : enable VIOP(11) : Receive Data Channel VIOP(12) : Transmit Data Channel Asynchronous Serial Link 2 Enable 0 : disable 12 UART 2 0 1 : enable VIOP(13) : Receive Data Channel VIOP(14) : Transmit Data Channel UART baud rate. 13 UBR 0 0 : divide UART scaler baud rate by 2 1 : No change of UART scaler baud rate UART parity enable. 14 UPE 1 0 : no parity 1 : parity enable UART parity. 15 UP 1 0 : even parity 1 : odd parity UART stop bit. 16 USB 0 0 : one stop bit 1 : two stop bits 24-17 Scaler 00000001 UART scaler r/w r/w r/w r/w r/w r/w r/w r/w Function r/w 28 Rev. C-24-Aug-01 Table 27. Serial Link Clock Configuration Register (SLCConfReg) Bits 3-0 11-4 15-12 23-16 SSLPS0 SSLS0 SSLPS1 SSLS1 Name Reset Value 0001 00000001 0001 00000001 Function Synchronous Serial Link Prescaler 0 Synchronous Serial Output Link Scaler 0 Synchronous Serial Link Prescaler 1 Synchronous Serial Output Link Scaler 1 r/w r/w r/w r/w r/w Table 28. Parallel Input Port Configuration Register (PIPConfReg) Bits Name Reset Value Parallel Input Bit Enable * 15-0 PIBE 0x0000 * 0 VIOP corresponding bit disable 1 VIOP corresponding bit enable r/w Function r/w Parallel port can be defined on VIOP(15-0) Table 29. Parallel Output Port Configuration Register (POPConfReg) Bits Name Reset Value Parallel Output Bit Enable 0 VIOP corresponding bit disable 15-0 POBE 0x0000 1 VIOP corresponding bit enable Parallel port can be defined on VIOP(15-0) 27-16 Not defined 0x000 Parallel Output Bit Mode 31-28 POBM 0x0 0 One shot pulse 1 Cyclic pulse generator r/w r r/w Function r/w Table 30. Parallel Output Port Polarity Register (POPPReg) Bits 11-0 Name Not defined Reset Value 0x000 Parallel Output Port Polarity 15-12 POPP 0x0 0 Pulse not inverted 1 Pulse inverted r/w Function r/w r 29 T7904E Rev. C-24-Aug-01 T7904E Table 31. Serial Link Input Register 0 (SLIReg0) Bits 31-0 Name SLIReg0 Reset Value 0x00000000 Function Data Register of Serial Input Link 0 r/w r Table 32. Serial Link Input Register 1 (SLIReg1) Bits 31-0 Name SLIReg1 Reset Value 0x00000000 Function Data Register of Serial Input Link 1 r/w r Table 33. Serial Link Output Register 0 (SLOReg0) Bits 31-0 Name SLOReg0 Reset Value 0x00000000 Function Data Register of Serial Output Link 0 r/w w Table 34. Serial Link Output Register 1 (SLOReg1) Bits 31-0 Name SLOReg1 Reset Value 0x00000000 Function Data Register of Serial Output Link 1 r/w w Table 35. Serial Link Status Register (SLStatusReg) Bits 0 1 2 3 4 5 Name CSIL0 CSOL0 DR1 TRE1 CSIL1 CSOL1 Reset Value 0 0 0 1 0 0 Clear the Serial input link 0 Clear the Serial output link 0 Data Ready in the serial input link 1 Transmitter Register Empty in the serial output link 1 Clear the Serial input link 1 Clear the Serial output link 1 Function r/w w w r r w w Table 36. Parallel Input Port Register (PIPReg) Bits 15-0 Name PIPReg Reset Value 0x0000 Parallel Input Port Data Function r/w r 30 Rev. C-24-Aug-01 Table 37. Parallel Output Port Register (POPReg) Bits Name Reset Value Discrete Parallel Output Port 11-0 POPReg 0x000 0 output 0 on corresponding VIOP bit if enable 1 output 1 on corresponding VIOP bit if enable Parallel Output Port Control 15-12 POPReg 0x0 0 No action 1 Restart associated pulse generator w r/w Function r/w Table 38. Pulse Delay Control Register n (PDCReg n) n can vary from 12 to 15 depending on the value of POPConfReg Bits 31-0 Name PDCn Reset Value 0x00000000 Function Value of the Pulse Delay for bit n of VIOP port if defined as a pulse generator r/w r/w Table 39. Pulse Length Control Register n (PLCReg n) n can vary from 12 to 15 depending on the value of POPConfReg Bits 31-0 Name PLCn Reset Value 0x00000000 Function Value of the Pulse Length for bit n of VIOP port if defined as a pulse generator r/w r/w Table 40. UART Receive Transmit Register 1 (UARTReg1) Bits 31-0 Name RTD1 Reset Value 0x00000000 Function Rx/Tx Data of UART1 (8-bit or 32-bit data register depending on SLConfReg) r/w r/w Table 41. UART Receive Transmit Register 2 (UARTReg2) Bits 31-0 Name RTD2 Reset Value 0x00000000 Function Rx/Tx Data of UART2 (8-bit or 32-bit data register depending on SLConfReg) r/w r/w 31 T7904E Rev. C-24-Aug-01 T7904E Table 42. UART Status Register (UARTStatusReg) Bits 0 1 2 3 4 5 6 7 8 9 10 11 Name DR1 TRE1 FE1 PE1 OE1 CU1 DR2 TRE2 FE2 PE2 OE2 CU2 Reset Value 0 1 0 0 0 0 0 1 0 0 0 0 Data Ready in channel 1 Transmitter Register Empty in channel 1 Framing Error in receiver 1 Parity Error in receiver 1 Overrun Error in receiver 1 Clear UART1 Data Ready in channel 2 Transmitter Register Empty in channel 2 Framing Error in receiver 2 Parity Error in receiver 2 Overrun Error in receiver 2 Clear UART2 Function r/w r r r r r w r r r r r w Table 43. CRC0 Register (CRCReg0) Bits 15-0 Name CRC0 Reset Value 0x1111 Function CRC0 register (Reading this register resets it) r/w r Table 44. CRC1 Register (CRCReg1) Bits 15-0 Name CRC1 Reset Value 0x1111 Function CRC1 register (Reading this register resets it) r/w r 32 Rev. C-24-Aug-01 Table 45. FIFO Configuration Register (FIFOConfReg) Bits 0 1 2 3 4 5 6 7 Name FSI0 FSA0 F20SAEXT0 Not defined FSO1 FSAO1 F20SAEXT1 Not defined Reset Value 0 0 0 0 0 0 0 0 FIFO10 coupled to SIL1 when 1 FIFO10 in Stand Alone mode when 1 FIFO10 in Stand Alone mode. The FIFO10 20-bit input data bus is connected to DFIFO(19-0) T7904E external port. Must be written to zero. FIFO11 coupled to SOL1 when 1 FIFO11 in Stand Alone mode when 1 FIFO11 in Stand Alone mode. The FIFO11 20-bit output data bus is connected to DFIFO(19-0) T7904E external port. Must be written to zero. Function r/w r/w r/w r/w r/w r/w r/w r/w r/w Table 46. FIFO Input Register (FIFOInReg) Bits 31-0 Name FIFOIn Reset Value Input Data of FIFO Function r/w w Table 47. FIFO Output Register (FIFOOutReg) Bits 31-0 Name FIFOOut Reset Value Output Data of FIFO Function r/w r 33 T7904E Rev. C-24-Aug-01 T7904E Signal description Name Type Definition DATA MEMORY Interface Data Memory Address. The Data Memory Address bus is generated by the DSP21020 during a data memory access except DMA(24-0) I/O During the Program Memory Initialization if performed by the T7904E through the User Extension Interface. On page boundary crossings, this address bus is the DRAM row address bus latched by the DMRAS* signal. It is then generated by the T7904E and the DSP21020 address bus is three stated thanks to DMTS* assertion. DMAC(1-0) DMD(39-0) DMRD* O I/O I/O Data Memory LSB Address. These address bits are generated by the T7904E during an access to an automatic 32-bit conversion area. Data Memory Data bus. Data Memory Read strobe. This signal is asserted by the DSP21020 during a read access. The T7904E outputs the current value of DMRD* when the DSP21020 is high Z. Data Memory Write strobe. This signal is asserted by the DSP21020 during a write access. The T7904E outputs the current value of DMWR* when the DSP21020 is high Z. Data Memory Data Write strobe. This signal is asserted by the T7904E in 3 configurations DMDWR* O DRAM implementation, Write access protection (plus one implicit wait state), Parity bit protection (plus one implicit wait state). DMTS* DMACK DMPAGE O O I/O Data Memory Three State Control. DMTS* is asserted to place the Data Memory address bus , data bus and control strobes of the DSP21020 in high impedance state. Data Memory Acknowledge. The T7904E asserts this signal when the Data Memory access is completed. Data Memory Page Boundary. This signal is asserted by the DSP21020 to signal that a Data Memory page boundary has been crossed. Data Memory Select lines. These pins are asserted by the DSP21020 as chip selects for the corresponding banks of data memory. Data Memory Row Address strobe. This signal is generated when a DRAM configuration is selected. Data Memory Column Address strobe. This signal is generated when a DRAM configuration is selected. Data Memory Parity Bit. DMPar I/O If the parity memory protection is selected, when the DS21020 performs a write operation, the T7904E generates the DMPar parity bit on DMD(39-0) data bus. During a read access, the T7904E checks the data parity. If no data parity protection is selected, DMPar is three-stated. DMWR* I/O DMS(3-0) DMRAS* DMCAS* I/O O O 34 Rev. C-24-Aug-01 PROGRAM MEMORY Interface PMA(19-0) PMD(47-0) PMRD* I/O I/O I/O Program Memory Address. The Program Memory Address bus is generated by the DSP21020 during a program memory access except during the Program Memory Initialization if performed by the T7904E. Program Memory Data bus. PMD(9) must be connected to a 10k Pull-Up. Program Memory Read strobe. This signal is asserted by the DSP21020 during a read access. The T7904E outputs the current value of PMRD* when the DSP21020 is high Z. Program Memory Write strobe. This signal is asserted by the DSP21020 during a write access. The T7904E outputs the current value of PMWR* when the DSP21020 is high Z. Program Memory Data Write strobe. This signal is asserted by the T7904E in 2 configurations PMDWR* O Write access protection (plus one implicit wait state), Parity bit protection (plus one implicit wait state), PMTS* PMACK PMS(1-0) O O I/O Program Memory Three State Control. PMTS* is asserted to place the Program Memory address bus, data bus and control strobes of the DSP21020 in high impedance state. Program Memory Acknowledge. The T7904E asserts this signal when the Program Memory access is completed. Program Memory Select lines. Program Memory ParityBit. PMPar I/O If the parity memory protection is selected, when the DS21020 performs a write operation, the T7904E generates the parity bit on PMPar. During a read access, the T7904E checks the data parity. If no memory protection is selected, PMPar is three-stated. Clocks, Reset and Miscellaneous ClkIn ClkOut SysReset* Reset* SysAv TestMode, ScanMode, Test Scan and T1Scan JTAG Interface TCK TMS TDI TDO TRST* I I I O I Test Clock. Provides a clock for the JTAG boundary scan. Test Mode Select. Used to control the JTAG state machine. Test Data Input. Provides serial data for the boundary scan logic. Test Data Output. Serial data output of the boundary scan logic. Test Reset. Resets the test state machine. I O I O O Input clock. The frequency of this clock is divided to be distributed to the system. System Clock. It is a 50% duty cycle clock used for clocking the DSP21020. System Hardware Reset. Assertion of this pin resets the T7904E and activates Reset* low. Reset pin. This pin is asserted low to reset the DSP21020. This occurs when either SysReset* is asserted or when the T7904E detects an error or on the generation of the software reset command by the DSP21020. System available. This signal is asserted high as long as no error is detected by the T7904E. PMWR* I/O I Test Mode Enable. Must be tied to zero. 35 T7904E Rev. C-24-Aug-01 T7904E User Extension Interface IOSel*(3-0) UEWr* UERd* UERdy2 UERdy3* UEEn* VIO port VIOP(15-0) Interrupt Interface IRQ* ExtIT(3-0) O I Interrupt Request. T7904E interrupt request to the DSP21020. External Interrupt. IO Versatile IO Port O O O I I O IO Chip Select . User Extension Write Strobe. User Extension Read Strobe. User Extension Data Ready. Indicates that the User Extension access in IO Area 2 is completed. (Active high) User Extension Data Ready. Indicates that the User Extension access in IO Area 3 is completed. (Active low) User Extension Enable. This signal is asserted when an access to bank 1, 2 or 3 is performed. It is used as an enable signal for the Data Memory extension bus buffer. 36 Rev. C-24-Aug-01 The following table shows the T7904E pin states after reset and after PMI. Pin Name DMA(24-0) DMAC(1-0) DMD(39-0) DMRD* DMWR* DMDWR* DMTS* DMACK DMPAGE DMS(3-0) DMPar PMA(19-0) PMD(47-0) PMRD* PMWR* PMDWR* PMTS* PMACK PMPar ClkOut SysAv Reset* IOSel*(3-0) UEWr* UERd* UEEn* VIOP(15-0) Value after reset Output depending on PMI mode Output, driven , value undefined Bidirectional Output driven high Output driven high Output driven high Output driven high Output driven low Output driven low Input Bidirectional, High impedance Output depending on PMI mode Bidirectional, value depending on PMI mode Output driven high Output driven high Output driven high Output driven high Output driven low Bidirectional, value depending on PMI mode Output Output driven low Output driven high output driven high, except IOSel*(0) depending on PMI mode Output driven high Output driven, value depending on PMI mode Output driven, value depending on PMI mode Bidirectional, High impedance Input Output, driven , value undefined Bidirectional, High impedance Input Input Output driven high Input Output driven low Input Input Bidirectional, High impedance Input Bidirectional, High impedance Input Input Output driven high Input Output driven low Bidirectional, High impedance Output Output Output driven high Output driven high Output driven high Output driven high Output driven high Bidirectional, High impedance Value after PMI 37 T7904E Rev. C-24-Aug-01 T7904E Pin Name IRQ* TDO Output driven high Output depending on TRST* and TCK Value after reset Output driven high Value after PMI 38 Rev. C-24-Aug-01 Characteristics Electrical interfaces The following data is provided for information only. Forguaranteed value refer to Atmel procurement specification. Table 48. Absolute maximum ratings Symbol Vdd Vi Ts Tj Rqjc Supply voltage Input voltage Storage temperature Maximum junction temperature Thermal resistance Parameter Min -0.5 -0.5 -65 Max 7 Vdd + 0.5V 150 165 10 Unit V V C C C/W Table 49. Recommended operating conditions Symbol Vdd To Vi Vo Supply voltage Operating temperature Input Voltage Output Voltage Parameter Min 4.5 -55 0 0 Typ 5.0 25 Vdd Vdd Max 5.5 125 Vdd Vdd Unit V C V V Table 50. DC characteristics Symbol Vil Vih Input low voltage Input high voltage Vdd = Min Iol = 3 mA Vdd = Min Ioh = -3 mA Vdd = Max 0 Vout Vdd Vdd = Max 0 Vin Vdd Vdd = Max Vout = 0v Vdd = Max f = 40MHz (ClkIn) 2.2 Parameter Conditions Min Max 0.8 Unit V V Vol Output voltage low level 0.4 V Voh Output voltage high level 2.4 V Ioz Output leakage current -5 5 uA Iiz Input leakage current -5 5 uA Isc output short circuit current (one output at a time during 1s max) 48 mA Iccop Dynamic Supply current 350 mA 39 T7904E Rev. C-24-Aug-01 T7904E Capacitance ratings Parameters Cin Cout Cio Description Input capacitance Output capacitance Input/output bus capacitance Max (pF) 5 7 10 AC characteristics Table 51. Clock and Reset Symbol Description Ref. Edge min Clk frequency (divided by 2 in the T7904E to get ClkOut) : T/2 With parity protection Without parity protection t01 Reset Assertion Time 2T 35 40 MHz MHz Spec max Unit Figure 4. Clock and Reset T/2 Clk ClkOut t01 SysReset* Table 52. Fast Page Mode Read Cycle Symbol Description Ref. Edge min t10 t11 DMCAS* delay DMCAS* de-assertion time ClkOut + ClkOut + 3T/8 T/8 Spec max 3T/8 + 10 T/8 + 10 ns ns Unit 40 Rev. C-24-Aug-01 Figure 5. DRAM Fast Page Mode Read cycle ClkOut DMA(24-0) DMCAS* t10 t11 DMRD* Data from RAM HZ DMRMD(39-0) Table 53. Fast Page Mode Delayed Write Cycle Symbol Description Ref. Edge min t20 t21 t22 t23 DMDWR* falling edge: One implicit extra wait-state Data Write Strobe width Data including parity bit Set Up Data including parity bit Hold Time DMDWR*DMDWR*ClkOut + 11T/8 T/4 0 10 11T/8+15 T/4 ns ns ns ns Spec max Unit 41 T7904E Rev. C-24-Aug-01 T7904E Figure 6. DRAM Fast Page Mode Delayed Write cycle ClkOut DMA(24-0) DMCAS* DMWR* t20 t21 DMDWR* DMD(39-0) DMPar t22 t23 SRAM Read Cycle Refer to TSC21020 Data Sheet for chronogram and timing 42 Rev. C-24-Aug-01 Table 54. Parity protected SRAM Write Cycle Symbol Description Ref. Edge min t24 Parity generation time Data Bus Spec max 15 ns Unit Figure 7. SRAM Write cycle (Parity protected) ClkOut Address Bus WR* Data from DSP Data Bus Parity bit t24 * * * * * Address bus is PMA(19-0) or DMA(19-0), WR* is PMWR*, DMWR*, DWR* is PMDWR*, DMDWR*, Data bus is PMD(47-0), DMD(39-0), Parity bit is PMPar, DMPar. Table 55. User Extension Read Cycle Symbol Description Ref. Edge min t31 t33 t34 t35 t36 t37 t38 t39 t40 t43 t46 t47 DMACK output delay (falling edge) UEEn* output delay (falling edge) IOSel* output delay UERdy* set up UERdy* hold time DMACK output delay (rising edge) UERd*, UEEn* output delay (rising edge) Data Bus set up Data Bus hold time Data Bus Output Delay in case of Automatic Conversion DMAC(1-0) output delay UERd* output delay (falling edge) ClkOut ClkOut Address Change ClkOut ClkOut ClkOut ClkOut + ClkOut ClkOut ClkOut ClkOut + DMRd*5 25 -1/2 T/4 + 15 25 15 1/2 T/4 2 T/4 T 10 1/2 T/4 + 15 Spec max 15 3/2 T/4 + 15 17 ns ns ns ns ns ns ns ns ns ns ns ns Unit 43 T7904E Rev. C-24-Aug-01 T7904E Figure 8. User Extension Read Cycle without Automatic Conversion ClkOut Address Bus IOSel* DMRd* t37 t34 DMACK UERd* UEEn* t47 t31 t38 t33 UERdy* t35 t36 Data Bus t39 t40 44 Rev. C-24-Aug-01 User Extension Read Cycle with Automatic Conversion * UERdy* stands for UERdy2 or UERdy3*. It must be asserted only in case of access in IO Area2 or IO Area3. Figure 9. User Extension Read Cycle with Automatic Conversion ClkOut Address Bus DMAC(1-0) 00 t46 IOSel* DMRd* t34 t37 DMACK UERd* UEEn* t47 t31 t38 t33 UERdy* t35 t36 Data Bus D driven by UEI t39 t40 D driven by UEI t43 D driven by DPC First byte or first 16-bit word is read by the DPC (2 Clk Out periods if zero wait-state) 2 last Clk Out periods dedicated to the data concatenation by the DPC, and then to the data sampling by the DSP 45 T7904E Rev. C-24-Aug-01 T7904E Table 56. User Extension Write Cycle Symbol Description Ref. Edge min t31 t32 t33 t37 t38 t41 t42 t44 t45 t48 DMACK output delay (falling edge) UEWr* output delay (rising edge) UEEn* output delay (falling edge) DMACK output delay (rising edge) UEEn* output delay (rising edge) Data Set Up Data Hold Time DMTS* output delay in case of Automatic Conversion UEWr* output delay (falling edge) in case of Automatic Conversion UEWr* output delay (falling edge) ClkOut ClkOut ClkOut ClkOut ClkOut + UEWr* + UEWr* + ClkOut + ClkOut DMWr* 5/2 T/4 5 0 3/2 T/4 + 15 1/2 T/4 + 15 15 Spec max 15 1/2 T/4 + 15 3/2 T/4 + 15 10 1/2 T/4 + 15 ns ns ns ns ns ns ns ns ns Unit Figure 10. User Extension Write Cycle Without Automatic Conversion ClkOut Address Bus IOSel* DMWr* t37 t34 DMACK UEWr* UEEn* t48 t31 t32 t38 t33 UERdy* t35 t36 Data Bus t41 t42 * UERdy* stands for UERdy2 or UERdy3*. It must be asserted only in case of access in IO Area2 or IO Area3. 46 Rev. C-24-Aug-01 Figure 11. User Extension Write Cycle with Automatic Conversion ClkOut Address Bus DMAC(1-0) DMTS* t44 t44 00 IOSel* DMWr* t37 DMACK UEWr* UEEn* t31 t48 t32 t45 t38 t33 UERdy* t35 t36 DMD(39-0) D driven by DSP, then by DPC t41 t42 First byte or first 16-bit word is written in the UEI (2 Clk Out periods if zero wait-state) Last Clk Out period for DSP Acknowledge * UERdy* stands for UERdy2 or UERdy3*. It must be asserted only in case of access in IO Area2 or IO Area3. Table 57. User Extension Read Cycle during Program Memory Initialization Symbol Description Ref. Edge min t46 t47 t48 UERd* output delay Address Bus Active output delay Address Bus HZ output delay ClkOut ClkOut + ClkOut + Spec max 15 10 10 ns ns ns Unit 47 T7904E Rev. C-24-Aug-01 T7904E Figure 12. User Extension Read Cycle during Program Memory Initialization ClkOut Address Bus t47 7 Clkout periods Generated by DPC t48 IOSel*(0) t34 UERd* UEEn* t46 t38 t33 Data Bus t39 t40 Table 58. General Purpose IO Port Symbol Description Ref. Edge min t50 t51 t52 t53 t54 t55 t56 t57 t57 CKO/CKI period (Tck) DO0 output delay DOn output delay CKO/CKI output delay CKO/CKI output delay DIn set up Din hold CKO falling edge to DVALO falling edge CKI rising edge to DVALI falling edge DVALO + CKO DVALO + DVALI + DRO + CKI + CKI + CKO CKI + -5 2 Tck 2 Tck 10 10 2 Tck 20 T Tck + 15 10 Spec max ns ns ns ns ns ns ns ns ns Unit 48 Rev. C-24-Aug-01 Figure 13. Synchronous Output Serial Link DVALO t53 DRO CKO DO t51 t54 t50 t57 DO0 (MSB) t52 DO1 DO2 DOn-1 DOn Figure 14. Synchronous Input Serial Link DVALI t53 t58 CKI DI DO0 (MSB) DO1 t56 t55 DO2 DOn-1 DOn Table 59. JTAG interface Symbol Description Ref. Edge min t70 t71 t72 t73 TCK period TDI, TMS set-up TDI, TMS hold TDO output delay Spec max Unit T TCK + TCK + TCK 5 6 15 ns ns ns ns 49 T7904E Rev. C-24-Aug-01 T7904E Figure 15. JTAG interface t70 TCK TMS, TDI t71 t72 TDO t73 Mechanical interfaces Packaging The T7904E can be procured in a 256 pin MQFPF ceramic package. 50 Rev. C-24-Aug-01 Table 60. Pin Assignment Pin 64 62 63 60 61 58 59 56 57 54 55 53 52 51 50 49 48 47 46 45 44 43 41 42 39 40 240 243 238 236 241 239 234 237 Function PMD(25) PMD(26) PMD(27) PMD(28) PMD(29) VSSB VSSA VSSB PMD(30) PMD(31) PMD(32) PMD(33) PMD(34) PMD(35) PMD(36) PMD(37) PMD(38) PMD(39) VCC VCC PMD(40) PMD(41) PMD(42) PMD(43) PMD(44) PMD(45) TMS TDI TDO TRST* IRQ* ExtIT(0) ExtIT(1) ExtIT(2) BIOT6 BIOT6 BIOT6 BIOT6 BIOT6 BIOT6 BINTUP BINTUP B3STA3 BINTUP BOUT3 BINTTL BINTTL BINTTL BIOT6 BIOT6 BIOT6 BIOT6 BIOT6 BIOT6 BIOT6 BIOT6 BIOT6 BIOT6 Buffer Type BIOT6 BIOT6 BIOT6 BIOT6 BIOT6 37 35 38 33 36 34 31 32 29 30 27 28 25 26 23 24 21 22 19 20 17 18 15 16 13 14 210 209 208 207 205 206 204 203 Pin Function PMD(46) PMD(47) VSS VSS PMA(0) PMA(1) PMA(2) PMA(3) PMA(4) PMA(5) PMA(6) PMA(7) PMA(8) PMA(9) PMA(10) PMA(11) PMA(12) PMA(13) PMA(14) PMA(15) PMA(16) PMA(17) PMA(18) PMA(19) VCC VCC IOSel*(0) IOSel*(1) IOSel*(2) IOSel*(3) UEWr* UERd* UERdy2 UERdy3* BOUT3 BOUT3 BOUT3 BOUT3 BOUT3 BOUT3 BINTTL BINTTL BIOT3 BIOT3 BIOT3 BIOT3 BIOT3 BIOT3 BIOT3 BIOT3 BIOT3 BIOT3 BIOT3 BIOT3 BIOT3 BIOT3 BIOT3 BIOT3 BIOT3 BIOT3 BIOT3 BIOT3 Buffer Type BIOT6 BIOT6 11 12 9 10 7 8 5 3 6 1 4 2 256 254 252 255 250 253 248 251 246 249 244 247 242 245 180 179 178 177 176 175 174 171 Pin VCC PMPar PMRD* PMWR* PMDWR* PMTS* PMACK PMS*(0) PMS*(1) VSS VSSPLLA VCCPLLA PLLOUT VSSPLL VCCPLL VSS ClkIn ClkOut SysReset* Reset* SysAv TESTMODE SCANMODE TESTSCAN T1SCAN TCK DMD(17) DMD(18) DMD(19) VCC VCC VCC DMD(20) DMD(21) BIOT6 BIOT6 BINTTL BIOT6 BINTTL BOUT3 BOUT3 BINTTL BINTTL BINTTL BINTTL BINTTL BIOT6 BIOT6 BIOT6 BIOT6 BIOT3 BIOT3 BOUT6 BOUT3 BOUT6 BIOT3 BIOT3 Function Buffer Type 51 T7904E Rev. C-24-Aug-01 T7904E Pin 232 235 230 233 228 231 229 226 227 224 225 223 222 221 220 219 218 217 216 215 212 211 146 144 141 142 139 140 137 138 135 136 133 134 131 Function ExtIT(3) VIOP(0) VIOP(1) VCC VCC VIOP(2) VIOP(3) VIOP(4) VIOP(5) VIOP(6) VIOP(7) VIOP(8) VIOP(9) VIOP(10) VSS VSS VSS VIOP(11) VIOP(12) VIOP(13) VIOP(14) VIOP(15) DMAC(1) VCC VCC DMA(0) DMA(1) DMA(2) DMA(3) DMA(4) DMA(5) DMA(6) DMA(7) DMA(8) DMA(9) BIOT3 BIOT3 BIOT3 BIOT3 BIOT3 BIOT3 BIOT3 BIOT3 BIOT3 BIOT3 BIOT3 BIOT3 BIOT3 BIOT3 BIOT3 BOUT3 BIOT3 BIOT3 BIOT3 BIOT3 BIOT3 BIOT3 BIOT3 BIOT3 BIOT3 Buffer Type BINTTL BIOT3 BIOT3 Pin 202 201 200 199 197 198 195 196 193 194 192 190 191 188 189 186 187 184 185 183 182 181 121 116 119 114 117 112 115 110 113 111 108 109 106 Function UEEn* VCC VCC DMD(0) DMD(1) DMD(2) DMD(3) DMD(4) DMD(5) DMD(6) DMD(7) DMD(8) DMD(9) VSS VSS DMD(10) DMD(11) DMD(12) DMD(13) DMD(14) DMD(15) DMD(16) DMA(22) DMA(23) DMA(24) VSS VSS DMPar DMRD* DMWR* DMDWR* DMTS* DMACK DMPAGE DMS*(0) BIOT6DN BIOT3 BIOT3 BOUT6 BOUT3 BOUT6 BIOT3 BIOT3 BIOT6 BIOT6 BIOT6 BIOT6 BIOT6 BIOT6 BIOT6 BIOT3 BIOT3 BIOT3 BIOT6 BIOT6 BIOT6 BIOT6 BIOT6 BIOT6 BIOT6 BIOT6 BIOT6 BIOT6 Buffer Type BOUT3 Pin 170 167 166 164 163 162 161 160 158 157 156 155 153 154 151 152 149 150 147 148 145 143 89 88 87 86 85 84 81 79 76 75 74 73 72 Function DMD(22) DMD(23) DMD(24) DMD(25) DMD(26) DMD(27) DMD(28) DMD(29) VSS VSS VSS DMD(30) DMD(31) DMD(32) DMD(33) DMD(34) DMD(35) DMD(36) DMD(37) DMD(38) DMD(39) DMAC(0) PMD(9) VSS VSS PMD(10) PMD(11) PMD(12) PMD(13) PMD(14) PMD(15) PMD(16) PMD(17) PMD(18) PMD(19) BIOT6 BIOT6 BIOT6 BIOT6 BIOT6 BIOT6 BIOT6 BIOT6 BIOT6 BIOT6 BIOT6 BIOT6 BIOT6 BIOT6 BIOT6 BIOT6 BIOT6 BIOT6 BIOT6 BIOT6 BOUT3 BIOT6 Buffer Type BIOT6 BIOT6 BIOT6 BIOT6 BIOT6 BIOT6 BIOT6 BIOT6 52 Rev. C-24-Aug-01 Pin 132 129 130 NC NC NC NC NC 128 126 124 127 122 125 120 123 118 Function DMA(10) DMA(11) DMA(12) NC NC NC NC NC DMA(13) DMA(14) DMA(15) DMA(16) DMA(17) DMA(18) DMA(19) DMA(20) DMA(21) Buffer Type BIOT3 BIOT3 BIOT3 Pin 107 104 105 102 100 103 98 101 Function DMS*(1) DMS*(2) DMS*(3) DMRAS* DMCAS* VCC VCC VCC PMD(0) PMD(1) PMD(2) PMD(3) PMD(4) PMD(5) PMD(6) PMD(7) PMD(8) Buffer Type BIOT3 BIOT3 BIOT3 BOUT3 BOUT6 71 70 69 67 68 65 Pin VCC VCC Function Buffer Type PMD(20) PMD(21) PMD(22) PMD(23) BIOT6 BIOT6 BIOT6 BIOT6 BIOT3 BIOT3 BIOT3 BIOT3 BIOT3 BIOT3 BIOT3 BIOT3 BIOT3 99 96 97 94 95 93 92 91 90 BIOT6 BIOT6 BIOT6 BIOT6 BIOT6 BIOT6 BIOT6 BIOT6 BIOT6 Abbreviations ASIC CRC DPC DMA DRAM DSP PMI SEU SIL SOL SRAM TAP UEI Application Specific Integrated Circuit Cyclic Redundancy Code DSP Peripheral Controller Direct Memory Access Dynamic Random Access Memory Digital Signal Processing Program Memory Initialization Single Event Upsets Serial Input Link Serial Output Link Static RAM Test Access Port User Extension Interface 53 T7904E Rev. C-24-Aug-01 T7904E Annex 1 : Boundary register 628 627 626 625 624 623 622 621 620 619 618 617 616 615 614 613 612 611 610 609 608 607 606 605 604 603 602 601 600 599 598 597 596 595 594 593 592 591 590 589 588 587 577 IRQ_N output RorW_N + observe_only ExtIT(0) observe_only EFlag_N + output ExtIT(1) observe_only HFlag_N + output ExtIT(2) observe_only FFlag_N + output ExtIT(3) observe_only DFIFO(0) + output X 617 DFIFO(0) + observe_only control + DFIFO Output Enable VIOP(0) output X 614 VIOP(0) observe_only control VIOP(0) Output Enable DFIFO(1) + output X 617 DFIFO(1) + observe_only VIOP(1) output X 609 VIOP(1) observe_only control VIOP(1) Output Enable DFIFO(2) + output X 617 DFIFO(2) + observe_only VIOP(2) output X 604 VIOP(2) observe_only control VIOP(2) Output Enable DFIFO(3) + output X 617 DFIFO(3) + observe_only VIOP(3) output X 599 VIOP(3) observe_only control VIOP(3) Output Enable DFIFO(4) + output X 617 DFIFO(4) + observe_only VIOP(4) output X 594 VIOP(4) observe_only control VIOP(4) Output Enable DFIFO(5) + output X 617 DFIFO(5) + observe_only VIOP(5) output X 589 VIOP(5) observe_only control VIOP(5) Output Enable DFIFO(6) + output X 617 DFIFO(8) + output X 617 DFIFO(8) + observe_only 576 575 574 573 572 571 570 569 568 567 566 565 564 563 562 561 560 559 558 557 556 555 554 553 552 551 550 549 548 547 546 545 544 543 542 541 540 539 538 537 536 535 534 VIOP(8) output X 574 VIOP(8) observe_only control VIOP(8) Output Enable DFIFO(9) + output X 617 DFIFO(9) + observe_only VIOP(9) output X 569 VIOP(9) observe_only control VIOP(9) Output Enable DFIFO(10) + output X 617 DFIFO(10) + observe_only VIOP(10) output X 564 VIOP(10) observe_only control VIOP(10) Output Enable DFIFO(11) + output X 617 DFIFO(11) + observe_only VIOP(11) output X 559 VIOP(11) observe_only control VIOP(11) Output Enable DFIFO(12) + output X 617 DFIFO(12) + observe_only VIOP(12) output X 554 VIOP(12) observe_only control VIOP(12) Output Enable DFIFO(13) + output X 617 DFIFO(13) + observe_only VIOP(13) output X 549 VIOP(13) observe_only control VIOP(13) Output Enable DFIFO(14) + output X 617 DFIFO(14) + observe_only VIOP(14) output X 544 VIOP(14) observe_only control VIOP(14) Output Enable DFIFO(15) + output X 617 DFIFO(15) + observe_only VIOP(15) output X 539 VIOP(15) observe_only control VIOP(15) Output Enable DFIFO(16) + output X 617 DFIFO(16) + observe_only IOSel_N(0) output DFIFO(17) + output X 617 DFIFO(17) + observe_only 54 Rev. C-24-Aug-01 533 532 531 530 529 528 527 526 525 524 523 522 521 520 519 518 517 516 515 514 513 512 511 510 509 508 507 506 505 504 503 502 501 500 499 498 497 496 495 494 493 492 491 490 489 488 487 486 IOSel_N(1) output DFIFO(18) + output X 617 DFIFO(18) + observe_only IOSel_N(2) output DFIFO(19) + output X 617 DFIFO(19) + observe_only IOSel_N(3) output UEWR_N output UERD_N output UERdy2 observe_only UERdy3_N observe_only UEEn_N output DMRMD(0) + output X 519 DMRMD(0) + observe_only control + DMRMD Output Enable DMD(0) output X 516 DMD(0) observe_only control DMD Output Enable DMRMD(1) + output X 519 DMRMD(1) + observe_only DMD(1) output X 516 DMD(1) observe_only DMRMD(2) + output X 519 DMRMD(2) + observe_only DMD(2) output X 516 DMD(2) observe_only DMRMD(3) + output X 519 DMRMD(3) + observe_only DMD(3) output X 516 DMD(3) observe_only DMRMD(4) + output X 501 DMRMD(4) + observe_only control + DMRMD Output Enable DMD(4) output X 498 DMD(4) observe_only control DMD Output Enable DMRMD(5) + output X 519 DMRMD(5) + observe_only DMD(5) output X 516 DMD(5) observe_only DMRMD(6) + output X 519 DMRMD(6) + observe_only DMD(6) output X 516 DMD(6) observe_only DMRMD(7) + output X 519 DMRMD(7) + observe_only DMD(7) output X 516 DMD(7) observe_only 485 484 483 482 481 480 479 478 477 476 475 474 473 472 471 470 469 468 467 466 465 464 463 462 461 460 459 458 457 456 455 454 453 452 451 450 449 448 447 446 445 444 443 442 441 440 439 438 DMRMD(8) + output X 519 DMRMD(8) + observe_only DMD(8) output X 516 DMD(8) observe_only DMRMD(9) + output X 519 DMRMD(9) + observe_only DMD(9) output X 516 DMD(9) observe_only DMRMD(10) + output X 519 DMRMD(10) + observe_only DMD(10) output X 516 DMD(10) observe_only DMRMD(11) + output X 519 DMRMD(11) + observe_only DMD(11) output X 516 DMD(11) observe_only DMRMD(12) + output X 519 DMRMD(12) + observe_only DMD(12) output X 516 DMD(12) observe_only DMRMD(13) + output X 519 DMRMD(13) + observe_only DMD(13) output X 516 DMD(13) observe_only DMRMD(14) + output X 519 DMRMD(14) + observe_only DMD(14) output X 516 DMD(14) observe_only DMRMD(15) + output X 519 DMRMD(15) + observe_only DMD(15) output X 516 DMD(15) observe_only DMRMD(16) + output X 519 DMRMD(16) + observe_only DMD(16) output X 516 DMD(16) observe_only DMRMD(17) + output X 519 DMRMD(17) + observe_only DMD(17) output X 516 DMD(17) observe_only DMRMD(18) + output X 519 DMRMD(18) + observe_only DMD(18) output X 516 DMD(18) observe_only DMRMD(19) + output X 519 DMRMD(19) + observe_only DMD(19) output X 498 DMD(19) observe_only 55 T7904E Rev. C-24-Aug-01 T7904E 437 436 435 434 433 432 431 430 429 428 427 426 425 424 423 422 421 420 419 418 417 416 415 414 413 412 411 410 409 408 407 406 405 404 403 402 401 400 399 398 397 396 395 394 393 392 391 390 DMRMD(20) + output X 519 DMRMD(20) + observe_only DMD(20) output X 516 DMD(20) observe_only DMRMD(21) + output X 519 DMRMD(21) + observe_only DMD(21) output X 516 DMD(21) observe_only DMRMD(22) + output X 519 DMRMD(22) + observe_only DMD(22) output X 516 DMD(22) observe_only DMRMD(23) + output X 519 DMRMD(23) + observe_only DMD(23) output X 516 DMD(23) observe_only DMRMD(24) + output X 519 DMRMD(24) + observe_only DMD(24) output X 498 DMD(24) observe_only DMRMD(25) + output X 501 DMRMD(25) + observe_only DMD(25) output X 516 DMD(25) observe_only DMRMD(26) + output X 501 DMRMD(26) + observe_only DMD(26) output X 516 DMD(26) observe_only DMRMD(27) + output X 519 DMRMD(27) + observe_only DMD(27) output X 498 DMD(27) observe_only DMRMD(28) + output X 519 DMRMD(28) + observe_only DMD(28) output X 516 DMD(28) observe_only DMRMD(29) + output X 501 DMRMD(29) + observe_only DMD(29) output X 516 DMD(29) observe_only DMRMD(30) + output X 519 DMRMD(30) + observe_only DMD(30) output X 498 DMD(30) observe_only DMRMD(31) + output X 501 DMRMD(31) + observe_only DMD(31) output X 516 DMD(31) observe_only 389 388 387 386 385 384 383 382 381 380 379 378 377 376 375 374 373 372 371 370 369 368 367 366 365 364 363 362 361 360 359 358 357 356 355 354 353 352 351 350 349 348 347 346 345 344 343 342 DMRMD(32) + output X 519 DMRMD(32) + observe_only DMD(32) output X 498 DMD(32) observe_only DMRMD(33) + output X 501 DMRMD(33) + observe_only DMD(33) output X 516 DMD(33) observe_only DMRMD(34) + output X 519 DMRMD(34) + observe_only DMD(34) output X 516 DMD(34) observe_only DMRMD(35) + output X 519 DMRMD(35) + observe_only DMD(35) output X 498 DMD(35) observe_only DMRMD(36) + output X 501 DMRMD(36) + observe_only DMD(36) output X 498 DMD(36) observe_only DMRMD(37) + output X 519 DMRMD(37) + observe_only DMD(37) output X 516 DMD(37) observe_only DMRMD(38) + output X 501 DMRMD(38) + observe_only DMD(38) output X 516 DMD(38) observe_only DMRMD(39) + output X 519 DMRMD(39) + observe_only DMD(39) output X 516 DMD(39) observe_only DMAC(0) output DMAC(1) output DMA(0) output X 353 DMA(0) observe_only control DMA Output Enable DMA(1) output X 353 DMA(1) observe_only DMA(2) output X 353 DMA(2) observe_only DMA(3) output X 353 DMA(3) observe_only DMA(4) output X 353 DMA(4) observe_only DMA(5) output X 353 DMA(5) observe_only DMA(6) output X 353 56 Rev. C-24-Aug-01 341 340 339 338 337 336 335 334 333 332 331 330 329 328 327 326 325 324 323 322 321 320 319 318 317 316 315 314 313 312 311 310 309 308 307 306 305 304 303 302 301 300 299 298 297 296 295 294 DMA(6) observe_only DMA(7) output X 353 DMA(7) observe_only DMA(8) output X 353 DMA(8) observe_only DMA(9) output X 353 DMA(9) observe_only DMA(10) output X 353 DMA(10) observe_only DMA(11) output X 353 DMA(11) observe_only DMA(12) output X 353 DMA(12) observe_only DMA(13) output X 353 DMA(13) observe_only DMA(14) output X 353 DMA(14) observe_only DMA(15) output X 353 DMA(15) observe_only DMA(16) output X 353 DMA(16) observe_only DMA(17) output X 353 DMA(17) observe_only DMA(18) output X 353 DMA(18) observe_only DMA(19) output X 353 DMA(19) observe_only DMA(20) output X 353 DMA(20) observe_only DMA(21) output X 353 DMA(21) observe_only DMA(22) output X 353 DMA(22) observe_only DMA(23) output X 353 DMA(23) observe_only DMA(24) output X 353 DMA(24) observe_only DMPar output X 302 DMPar observe_only control DMPar Output Enable DMCB(1) + output X 519 DMCB(1) + observe_only DMRD_N output X 353 DMRD_N observe_only DMCB(2) + output X 519 DMCB(2) + observe_only DMWR_N output X 353 DMWR_N observe_only 293 292 291 290 289 288 287 286 285 284 283 282 281 280 279 278 277 276 275 274 273 272 271 270 269 268 267 266 265 264 263 262 261 260 259 258 257 256 255 254 253 252 251 250 249 248 247 246 DMCB(3) + output X 519 DMCB(3) + observe_only DMDWR_N output DMCB(4) + output X 519 DMCB(4) + observe_only DMTS_N output DMCB(5) + output X 519 DMCB(5) + observe_only DMACK output DMCB(6) + output X 519 DMCB(6) + observe_only DMPAGE output X 353 DMPAGE observe_only DMS_N(0) output X 353 DMS_N(0) observe_only DMS_N(1) output X 353 DMS_N(1) observe_only DMS_N(2) output X 353 DMS_N(2) observe_only DMS_N(3) output X 353 DMS_N(3) observe_only DMRAS_N output DMCAS_N output PMRMD(0) + output X 268 PMRMD(0) + observe_only control PMRMD Output Enable PMD(0) output X 265 PMD(0) observe_only control PMD Output Enable PMRMD(1) + output X 268 PMRMD(1) + observe_only PMD(1) output X 265 PMD(1) observe_only PMRMD(2) + output X 268 PMRMD(2) + observe_only PMD(2) output X 265 PMD(2) observe_only PMRMD(3) + output X 268 PMRMD(3) + observe_only PMD(3) output X 265 PMD(3) observe_only PMRMD(4) + output X 268 PMRMD(4) + observe_only PMD(4) output X 265 PMD(4) observe_only PMRMD(5) + output X 268 PMRMD(5) + observe_only PMD(5) output X 265 57 T7904E Rev. C-24-Aug-01 T7904E 245 244 243 242 241 240 239 238 237 236 235 234 233 232 231 230 229 228 227 226 225 224 223 222 221 220 219 218 217 216 215 214 213 212 211 210 209 208 207 206 205 204 203 202 201 200 199 198 PMD(5) observe_only PMRMD(6) + output X 268 PMRMD(6) + observe_only PMD(6) output X 265 PMD(6) observe_only PMRMD(7) + output X 268 PMRMD(7) + observe_only PMD(7) output X 265 PMD(7) observe_only PMRMD(8) + output X 268 PMRMD(8) + observe_only PMD(8) output X 265 PMD(8) observe_only PMRMD(9) + output X 268 PMRMD(9) + observe_only PMD(9) output X 265 PMD(9) observe_only PMRMD(10) + output X 268 PMRMD(10) + observe_only PMD(10) output X 265 PMD(10) observe_only PMRMD(11) + output X 268 PMRMD(11) + observe_only PMD(11) output X 265 PMD(11) observe_only PMRMD(12) + output X 268 PMRMD(12) + observe_only PMD(12) output X 265 PMD(12) observe_only PMRMD(13) + output X 268 PMRMD(13) + observe_only PMD(13) output X 265 PMD(13) observe_only PMRMD(14) + output X 268 PMRMD(14) + observe_only PMD(14) output X 265 PMD(14) observe_only PMRMD(15) + output X 268 PMRMD(15) + observe_only PMD(15) output X 265 PMD(15) observe_only PMRMD(16) + output X 268 PMRMD(16) + observe_only PMD(16) output X 265 PMD(16) observe_only PMRMD(17) + output X 268 PMRMD(17) + observe_only PMD(17) output X 265 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 PMD(17) observe_only PMRMD(18) + output X 268 PMRMD(18) + observe_only PMD(18) output X 265 PMD(18) observe_only PMRMD(19) + output X 268 PMRMD(19) + observe_only PMD(19) output X 265 PMD(19) observe_only PMRMD(20) + output X 268 PMRMD(20) + observe_only PMD(20) output X 265 PMD(20) observe_only PMRMD(21) + output X 268 PMRMD(21) + observe_only PMD(21) output X 265 PMD(21) observe_only PMRMD(22) + output X 268 PMRMD(22) + observe_only PMD(22) output X 265 PMD(22) observe_only PMRMD(23) + output X 268 PMRMD(23) + observe_only PMD(23) output X 265 PMD(23) observe_only PMRMD(24) + output X 268 PMRMD(24) + observe_only PMD(24) output X 265 PMD(24) observe_only PMRMD(25) + output X 268 PMRMD(25) + observe_only PMD(25) output X 265 PMD(25) observe_only PMRMD(26) + output X 268 PMRMD(26) + observe_only PMD(26) output X 265 PMD(26) observe_only PMRMD(27) + output X 268 PMRMD(27) + observe_only PMD(27) output X 265 PMD(27) observe_only PMRMD(28) + output X 268 PMRMD(28) + observe_only PMD(28) output X 265 PMD(28) observe_only PMRMD(29) + output X 268 PMRMD(29) + observe_only PMD(29) output X 265 58 Rev. C-24-Aug-01 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 PMD(29) observe_only PMRMD(30) + output X 146 PMRMD(30) + observe_only control PMRMD Output Enable PMD(30) output X 265 PMD(30) observe_only PMRMD(31) + output X 146 PMRMD(31) + observe_only PMD(31) output X 265 PMD(31) observe_only PMRMD(32) + output X 146 PMRMD(32) + observe_only PMD(32) output X 135 PMD(32) observe_only control PMD Output Enable PMRMD(33) + output X 146 PMRMD(33) + observe_only PMD(33) output X 135 PMD(33) observe_only PMRMD(34) + output X 146 PMRMD(34) + observe_only PMD(34) output X 135 PMD(34) observe_only PMRMD(35) + output X 146 PMRMD(35) + observe_only PMD(35) output X 135 PMD(35) observe_only PMRMD(36) + output X 146 PMRMD(36) + observe_only PMD(36) output X 135 PMD(36) observe_only PMRMD(37) + output X 146 PMRMD(37) + observe_only PMD(37) output X 135 PMD(37) observe_only PMRMD(38) + output X 146 PMRMD(38) + observe_only PMD(38) output X 135 PMD(38) observe_only PMRMD(39) + output X 146 PMRMD(39) + observe_only PMD(39) output X 135 PMD(39) observe_only PMRMD(40) + output X 146 PMRMD(40) + observe_only PMD(40) output X 135 PMD(40) observe_only PMRMD(41) + output X 146 101 PMRMD(41) + observe_only 100 PMD(41) output X 135 99 PMD(41) observe_only 98 PMRMD(42) + output X 146 97 PMRMD(42) + observe_only 96 PMD(42) output X 135 95 PMD(42) observe_only 94 PMRMD(43) + output X 146 93 PMRMD(43) + observe_only 92 PMD(43) output X 135 91 PMD(43) observe_only 90 PMRMD(44) + output X 146 89 PMRMD(44) + observe_only 88 PMD(44) output X 135 87 PMD(44) observe_only 86 PMRMD(45) + output X 146 85 PMRMD(45) + output X 135 79 PMD(46) observe_only 78 PMRMD(47) + output X 146 77 PMRMD(47) + observe_only 76 PMD(47) output X 135 75 PMD(47) observe_only 74 PMA(0) output X 72 73 PMA(0) observe_only 72 control PMA Output Enable 71 PMA(1) output X 72 70 PMA(1) observe_only 69 PMA(2) output X 72 68 PMA(2) observe_only 67 PMA(3) output X 72 66 PMA(3) observe_only 65 PMA(4) output X 72 64 PMA(4) observe_only 63 PMA(5) output X 72 62 PMA(5) observe_only 61 PMA(6) output X 72 60 PMA(6) observe_only 59 PMA(7) output X 72 58 PMA(7) observe_only 57 PMA(8) output X 72 56 PMA(8) observe_only 55 PMA(9) output X 72 54 PMA(9) observe_only 53 PMA(10) output X 72 52 PMA(10) observe_only 51 PMA(11) output X 72 50 PMA(11) observe_only 49 PMA(12) output X 72 59 T7904E Rev. C-24-Aug-01 T7904E 48 PMA(12) observe_only 47 PMA(13) output X 72 46 PMA(13) observe_only 45 PMA(14) output X 72 44 PMA(14) observe_only 43 PMA(15) output X 72 42 PMA(15) observe_only 41 PMA(16) output X 72 40 PMA(16) observe_only 39 PMA(17) output X 72 38 PMA(17) observe_only 37 PMA(18) output X 72 36 PMA(18) observe_only 35 PMA(19) output X 72 34 PMA(19) observe_only 33 PMPar output X 31 32 PMPar observe_only 31 control PMPar Output Enable 30 PMCB(1) + output X 268 29 PMCB(1) + observe_only 28 PMRD_N output X 72 27 PMRD_N observe_only 26 PMCB(2) + output X 268 25 PMCB(2) + observe_only 24 PMWR_N output X 72 23 PMWR_N observe_only 22 PMCB(3) + output X 268 21 PMCB(3) + observe_only 20 PMDWR_N output 19 PMCB(4) + output X 268 18 PMCB(4) + observe_only 17 PMTS_N output 16 PMCB(5) + output X 268 15 PMCB(5) + observe_only 14 PMACK output 13 PMCB(6) + output X 268 12 PMCB(6) + observe_only 11 PMS_N(0) output X 72 10 PMS_N(0) observe_only 9 PMS_N(1) output X 72 8 PMS_N(1) observe_only 7 ClkIn observe_only 6 SysRes_N observe_only 5 4 3 2 1 0 Reset_N output SysAv output TestMode observe_only ScanMode observe_only TestScan observe_only T1Scan input Note: + signals available on the die, not on the package. Can be set to any state during scan. 60 Rev. C-24-Aug-01 Ordering information Part-number T7904EK2-E T7904EK2 T7904EK2/883* T7904EK2S/883* T7904EK2SC T7904EK2SB T7904EK2MQ T7904EK2SV T7904EDD-E T7904EDDMQ T7904EDDSV Temperature range +25C -55 to +125C -55 to +125C -55 to +125C -55 to +125C -55 to +125C -55 to +125C -55 to +125C +25 -55 to +125 -55 to +125 Package MQFPF256 MQFPF256 MQFPF256 MQFPF256 MQFPF256 MQFPF256 MQFPF256 MQFPF256 Die Die Die Flow Engineering Samples MIL MIL 883 B MIL 883 S SCC C SCC B QML Q QML V Engineering Samples QML Q QML V Note: (*)contact factory 61 T7904E Rev. C-24-Aug-01 Atmel Wireless & Microcontrollers Sales Offices France 3, Avenue du Centre 78054 St.-Quentin-en-Yvelines Cedex France Tel: 33130 60 70 00 Fax: 33130 60 71 11 Sweden Kavallerivaegen 24, Rissne 17402 Sundbyberg Sweden Tel: 468587 48 800 Fax: 468587 48 850 Hong Kong 77 Mody Rd., Tsimshatsui East, Rm.1219 East Kowloon Hong Kong Tel: 85223789 789 Fax: 85223755 733 United Kingdom Easthampstead Road Bracknell, Berkshire RG12 1LX United Kingdom Tel: 441344707 300 Fax: 441344427 371 Germany Erfurter Strasse 31 85386 Eching Germany Tel: 49893 19 70 0 Fax: 49893 19 46 21 Kruppstrasse 6 45128 Essen Germany Tel: 492 012 47 30 0 Fax: 492 012 47 30 47 Theresienstrasse 2 74072 Heilbronn Germany Tel: 4971 3167 36 36 Fax: 4971 3167 31 63 Korea Ste.605,Singsong Bldg. Youngdeungpo-ku 150-010 Seoul Korea Tel: 8227851136 Fax: 8227851137 USA 2325 Orchard Parkway San Jose California 95131 USA-California Tel: 1408441 0311 Fax: 1408436 4200 1465 Route 31, 5th Floor Annandale New Jersey 08801 USA-New Jersey Tel: 1908848 5208 Fax: 1908848 5232 Singapore 25 Tampines Street 92 Singapore 528877 Rep. of Singapore Tel: 65260 8223 Fax: 65787 9819 Taiwan Wen Hwa 2 Road, Lin Kou Hsiang 244 Taipei Hsien 244 Taiwan, R.O.C. Tel: 88622609 5581 Fax: 88622600 2735 Italy Via Grosio, 10/8 20151 Milano Italy Tel: 390238037-1 Fax: 390238037-234 Japan 1-24-8 Shinkawa, Chuo-Ku 104-0033 Tokyo Japan Tel: 8133523 3551 Fax: 8133523 7581 Spain Principe de Vergara, 112 28002 Madrid Spain Tel: 3491564 51 81 Fax: 3491562 75 14 Web site http://www.atmel-wm.com (c) Atmel Nantes SA, 2001. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems. Printed on recycled paper. |
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