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| MSP53C391, MSP53C392 SLAVE SPEECH SYNTHESIZERS SPSS024 - NOVEMBER 1999 D D D D D D D D Slave Speech Synthesizers, LPC, MELP, CELP Two Channel FM Synthesis, PCM 8-Bit Microprocessor With 61 instructions 3.3V to 6.5V CMOS Technology for Low Power Dissipation Direct Speaker Drive Capability Internal Clock Generator That Requires No External Components Two Software-Selectable Clock Speeds 10-kHz or 8-kHz Speech Sample Rate MSP53C391 N PACKAGE (TOP VIEW) DATA2/EOS DATA1 DATA0 OUT2 OUT1 EOS R/W OSC IN 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 DATA3/BUSY STROB IRQ DAC+ DAC- VDD VSS INIT description The MSP53C391 and MSP53C392 are catalog MSP50C3x codes which implements the functionality of a slave speech synthesizer. They communicate with a master microprocessor using two control lines (R/W and STROBE) and either a 4-bit data bus (MSP53C391) or an 8-bit data bus (MSP53C392). Either the MSP53C391 or the MSP53C392 can synthesize speech using several different compression algorithms; LPC, MELP, or CELP. They also can synthesize two-channel music using FM synthesis. See the MSP50C3x User's Guide (literature number: SLOU006B) for more information about the MSP50C3x family. Table 1. MSP53C39x Family DEVICE MSP53C391 MSP53C392 4-bit data bus 8-bit data bus FEATURES MSP53C392 N PACKAGE (TOP VIEW) DATA6/EOS DATA5 DATA4 DATA3 DATA2 DATA1 R/W OSC IN 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 DATA7/BUSY STROB DATA0 DAC+ DAC- VDD VSS INIT Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 1999, Texas Instruments Incorporated POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 MSP53C391, MSP53C392 SLAVE SPEECH SYNTHESIZERS SPSS024 - NOVEMBER 1999 absolute maximum ratings over operating free-air temperature range Supply voltage range, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 8 V Supply current, IDD or ISS (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to VDD + 0.3 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to VDD + 0.3 V Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 30C to 125C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltages are with respect to ground. 2. The total supply current includes the current out of all the I/O terminals and DAC terminals as well as the operating current of the device. recommended operating conditions MAX VDD VIH Supply voltage High-level input voltage VDD = 3.3 V VDD = 5 V VDD = 6 V VDD = 3.3 V VIL TA Rspeaker Low-level input voltage Operating free-air temperature Minimum speaker impedance VDD = 5 V VDD = 6 V Device functionality Direct speaker drive using 2 pin push-pull DAC option 3.3 2.5 3.8 4.5 0 0 0 0 32 MAX 6.5 3.3 5 6 0.65 1 1.3 70 C V V UNIT V Unless otherwise noted, all voltages are with respect to VSS. 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MSP53C391, MSP53C392 SLAVE SPEECH SYNTHESIZERS SPSS024 - NOVEMBER 1999 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VT T+ VT T- Vh hys IIkg Istandby IDD Positive going threshold voltage (INIT) Positive-going Negative-going Negative going threshold voltage (INIT) Hysteresis ( VT - VT- ) (INIT) T+ T Input leakage current (except for OSC IN) Standby current (INIT low, SETOFF) Supply current VDD = 3.3 V, VDD = 5 V, VDD = 6 V, VDD = 3.3 V, High-level output current g (DATA0 - DATA7, OUT1, OUT2) VDD = 5 V, VDD = 6 V, VDD = 3.3 V, VDD = 5 V, VDD = 6 V, VDD = 3.3 V, Low-level output current (DATA0 - DATA7, OUT1, OUT2) VDD = 5 V, VDD = 6 V, VDD = 3.3 V, VDD = 5 V, VDD = 6 V, VDD = 3.3 V, VDD = 5 V, VDD = 6 V, VDD = 3.3 V, VDD = 5 V, VDD = 6 V, VDD = 3.3 V, VDD = 5 V, VDD = 6 V, VDD = 3.3 V, VDD = 5 V, VDD = 6 V, VDD = 5 V, VOH = 2.75 V VOH = 4.5 V VOH = 5.5 V VOH = 2.75 V VOH = 4.5 V VOH = 5.5 V VOH = 2.2 V VOH = 3.33 V VOH = 4 V VOL = 0.5 V VOL = 0.5 V VOL = 0.5 V VOL = 1.1 V VOL = 1.67 V VOL = 2 V VOH = 2.75 V VOH = 4.5 V VOH = 5.5 V VOH = 2.3 V VOH = 4 V VOH = 5 V VOL = 0.5 V VOL = 0.5 V VOL = 0.5 V VOL = 1 V VOL = 1 V VOL = 1 V TA = 25C, -4 -5 -6 -8 -14 - 20 5 5 5 10 20 25 - 30 -35 -40 - 50 -90 - 100 50 70 80 100 140 150 14.89 14 89 18.62 18 62 15.36 15 36 19.2 19 2 15.86 15 86 19.7 19 7 MHz MHz 2.1 3.1 4.5 -12 -14 - 15 -20 - 40 - 51 9 9 9 19 29 35 -50 -60 - 65 -90 - 140 - 150 80 90 110 140 mA mA mA mA mA mA mA mA mA TEST CONDITIONS VDD = 3.5 V VDD = 6 V VDD = 3.5 V VDD = 6 V VDD = 3.5 V VDD = 6 V MIN TYP 2 3.4 1.6 2.3 0.4 1.1 2 10 MAX UNIT V V V A A IOH IOL IOH High-level High level output current (DAC) IOL Low level output current (DAC) Low-level fosc(low) (l ) fosc(high) (hi h) Oscillator frequency freq enc Oscillator frequency freq enc Target frequency = 15.36 MHz VDD = 5 V, TA = 25C, Target frequency = 19.2 MHz Operating current assumes all inputs are tied to either VSS or VDD with no input currents due to programmed pullup resistors. The DAC output and other outputs are open circuited. The frequency of the internal clock has a temperature coefficient of approximately - 0.2 % / C and a VDD coefficient of approximately 1%/V. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 MSP53C391, MSP53C392 SLAVE SPEECH SYNTHESIZERS SPSS024 - NOVEMBER 1999 switching characteristics PARAMETER tr tf Rise time, DATA0 - DATA7, DAC Fall time, DATA0- DATA7, DAC VDD = 3.3 V, VDD = 3.3 V, TEST CONDITIONS CL = 100 pF, CL = 100 pF, 10% to 90% 10% to 90% MIN NOM 50 50 MAX UNIT ns ns timing requirements MIN Initialization tINIT INIT pulsed low while the MSP53C39x has power applied (see Figure 1) 1 5 20 100 20 30 100 50 50 s ms ns ns ns ns ns ns ns MAX UNIT tSETUP Delay between rising edge of INIT and device initialization complete Writing (Slave Mode) tsu1(R/W) tsu(d) th1(R/W) th(d) tw tr tf tsu2(R/W) th2(R/W) tdis tw tr tf td Setup time, R/W low before STROB goes low (see Figure 2) Setup time, data valid before STROB goes high (see Figure 2) Hold time, R/W low after STROB goes high (see Figure 2) Hold time, data valid after STROB goes high (see Figure 2) Pulse duration, STROB low (see Figure 2) Rise time, STROB (see Figure 2) Fall time, STROB (see Figure 2) Reading (Slave Mode) Setup time, R/W before STROB goes low (see Figure 3) Hold time, R/W after STROB goes high (see Figure 3) Output disable time, data valid after STROB goes high (see Figure 3) Pulse duration, STROB low (see Figure 3) Rise time, STROB (see Figure 3) Fall time, STROB (see Figure 3) Delay time for STROB low to data valid (see Figure 3) 20 20 0 100 50 50 50 30 ns ns ns ns ns ns ns PARAMETER MEASUREMENT INFORMATION INIT tINIT Figure 1. Initialization Timing Diagram 4 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MSP53C391, MSP53C392 SLAVE SPEECH SYNTHESIZERS SPSS024 - NOVEMBER 1999 PARAMETER MEASUREMENT INFORMATION R/W tsu1(R/W) tw STROB tf tr tsu(d) th(d) DATA Data Valid th1(R/W) Figure 2. Write Timing Diagram (Slave Mode) R/W tsu2(R/W) tw STROB tf td DATA Data Valid tr tdis th2(R/W) Figure 3. Read Timing Diagram (Slave Mode) POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 MSP53C391, MSP53C392 SLAVE SPEECH SYNTHESIZERS SPSS024 - NOVEMBER 1999 MECHANICAL DATA N (R-PDIP-T**) 16 PIN SHOWN PINS ** DIM A 16 9 A MAX PLASTIC DUAL-IN-LINE PACKAGE 14 0.775 (19,69) 0.745 (18,92) 16 0.775 (19,69) 0.745 (18,92) 18 0.920 (23.37) 0.850 (21.59) 20 0.975 (24,77) 0.940 (23,88) A MIN 0.260 (6,60) 0.240 (6,10) 1 8 0.070 (1,78) MAX 0.035 (0,89) MAX 0.020 (0,51) MIN 0.310 (7,87) 0.290 (7,37) 0.200 (5,08) MAX Seating Plane 0.125 (3,18) MIN 0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0- 15 0.010 (0,25) NOM 0.010 (0,25) M 14/18 PIN ONLY 4040049/C 08/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001 (20 pin package is shorter then MS-001.) 6 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof. Copyright (c) 1999, Texas Instruments Incorporated |
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