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TMS320C6712 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS148 - AUGUST 2000
D Best Price/Performance Floating-Point
Digital Signal Processor (DSP) TMS320C6712 - 10-ns Instruction Cycle Time - 100-MHz Clock Rate - Eight 32-Bit Instructions/Cycle - 600 MFLOPS - C6712 and C6211/C6711 are Pin-Compatible VelociTITM Advanced Very Long Instruction Word (VLIW) C67xTM DSP Core - Eight Highly Independent Functional Units: - Four ALUs (Floating- and Fixed-Point) - Two ALUs (Fixed-Point) - Two Multipliers (Floating- and Fixed-Point) - Load-Store Architecture With 32 32-Bit General-Purpose Registers - Instruction Packing Reduces Code Size - All Instructions Conditional Instruction Set Features - Hardware Support for IEEE Single-Precision and Double-Precision Instructions - Byte-Addressable (8-, 16-, 32-Bit Data) - 8-Bit Overflow Protection - Saturation - Bit-Field Extract, Set, Clear - Bit-Counting - Normalization L1/L2 Memory Architecture - 32K-Bit (4K-Byte) L1P Program Cache (Direct Mapped) - 32K-Bit (4K-Byte) L1D Data Cache (2-Way Set-Associative) - 512K-Bit (64K-Byte) L2 Unified Mapped RAM/Cache (Flexible Data/Program Allocation) - 1024M-Byte Addressable External Memory Space Device Configuration - Boot Mode: 8- and 16-Bit ROM Boot - Endianness: Little Endian, Big Endian
GFN 256-PIN BALL GRID ARRAY (BGA) PACKAGE (BOTTOM VIEW)
Y W V U T R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
D
D 16-Bit External Memory Interface (EMIF)
- Glueless Interface to Synchronous Memories: SDRAM and SBSRAM - Glueless Interface to Asynchronous Memories: SRAM and EPROM Enhanced Direct-Memory-Access (EDMA) Controller Two Multichannel Buffered Serial Ports (McBSPs) - Direct Interface to T1/E1, MVIP, SCSA Framers - ST-Bus-Switching Compatible - Up to 256 Channels Each - AC97-Compatible - Serial-Peripheral-Interface (SPI) Compatible (MotorolaTM) Two 32-Bit General-Purpose Timers Flexible Phase-Locked-Loop (PLL) Clock Generator IEEE-1149.1 (JTAG) Boundary-Scan-Compatible 256-Pin Ball Grid Array (BGA) Package (GFN Suffix) 0.18-m/5-Level Metal Process - CMOS Technology 3.3-V I/Os, 1.8-V Internal
D
D D
D
D D D D D D
D
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. VelociTI and C67x are trademarks of Texas Instruments. Motorola is a trademark of Motorola, Inc. IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
Copyright (c) 2000, Texas Instruments Incorporated
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PRODUCT PREVIEW
TMS320C6712 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS148 - AUGUST 2000
Table of Contents
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 device characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 device compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 functional block and CPU (DSP core) diagram . . . . . . . . . . . 5 CPU (DSP core) description . . . . . . . . . . . . . . . . . . . . . . . . . . 6 signal groups description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 terminal functions table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 documentation support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 clock PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 power-supply sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 absolute maximum ratings over operating case temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 recommended operating conditions . . . . . . . . . . . . . . . . . . . 24 electrical characteristics over recommended ranges of supply voltage and operating case temperature . 24 parameter measurement information . . . . . . . . . . . . . . . input and output clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . asynchronous memory timing . . . . . . . . . . . . . . . . . . . . . synchronous-burst memory timing . . . . . . . . . . . . . . . . . synchronous DRAM timing . . . . . . . . . . . . . . . . . . . . . . . . HOLD/HOLDA timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . BUSREQ timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . external interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . multichannel buffered serial port timing . . . . . . . . . . . . . timer timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JTAG test-port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 26 29 32 34 40 41 42 44 45 56 57 58
PRODUCT PREVIEW
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TMS320C6712 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS148 - AUGUST 2000
description
The TMS320C67xTM DSPs (including the TMS320C6712 device) are the floating-point DSP family in the TMS320C6000TM DSP platform. The TMS320C6712 (C6712) device is based on the high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for multichannel and multifunction applications. With performance of up to 600 million floating-point operations per second (MFLOPS) at a clock rate of 100 MHz, the C6712 device is the lowest-cost DSP in the C6000TM DSP platform. The C6712 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight functional units provide four floating-/fixed-point ALUs, two fixed-point ALUs, and two floating-/fixed-point multipliers. The C6712 can produce two multiply-accumulates (MACs) per cycle for a total of 200 million MACs per second (MMACS). The C6712 uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 32-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 32-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 512-Kbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.The peripheral set includes two multichannel buffered serial ports (McBSPs), two general-purpose timers, and a glueless 16-bit external memory interface (EMIF) capable of interfacing to SDRAM, SBSRAM, and asynchronous peripherals. The C6712 has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a WindowsTM debugger interface for visibility into source code execution.
TMS320C67x, TMS320C6000, and C6000 are trademarks of Texas Instruments. Windows is a registered trademark of the Microsoft Corporation.
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PRODUCT PREVIEW
TMS320C6712 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS148 - AUGUST 2000
device characteristics
Table 1 provides an overview of the C6712 DSP. The table shows significant features of the C6712 device, including the capacity of on-chip RAM, the peripherals, the execution time, and the package type with pin count. Table 1. Characteristics of the C6712 Processor
HARDWARE FEATURES EMIF EDMA Peripherals McBSPs 32-Bit Timers Size (Bytes) On-Chip Memory Organization MHz ns Core (V) I/O (V) CLKIN frequency multiplier 27 x 27 mm m Product Preview (PP) Advance Information (AI) Production Data (PD) (For more details on the C6000TM DSP part numbering, see Figure 4) C6712 (FLOATING-POINT DSP) 1 (16-bit) 1 2 2 72K 4K-Byte (4KB) L1 Program (L1P) Cache 4KB L1 Data (L1D) Cache 64KB Unified Mapped RAM/Cache (L2) 100 10 ns ('6712-100 [Lowest-Cost Device]) 1.8 3.3 Bypass (x1), x4 256-Pin BGA (GFN) 0.18 m PP
Frequency Cycle Time
PRODUCT PREVIEW
Voltage PLL Options BGA Package Process Technology Product Status
Device Part Numbers
TMX320C6712GFN
device compatibility
The TMS320C6712 and C6211/C6711 devices are pin-compatible; thus, making new system designs easier and providing faster time to market. The following list summarizes the device characteristic differences between the C6211, C6711, and C6712 devices:
D The C6211 device has a fixed-point C62x DSP core, while the C6711/C6712 device has a floating-point
C67x DSP core.
D The C6211/C6711 device has a 32-bit EMIF, while the C6712 has a 16-bit EMIF. D The C6211/C6711 device features an HPI, while the C6712 does not. D The C6712 device has dedicated device configuration pins, BOOTMODE and LENDIAN, that specify the
boot-load operation and device endianness, respectively, during reset. On the C6211/C6711 device, these configuration pins are integrated with the HPI pins.
D The 100-MHz C6712 is the lowest-cost entry in the TMS320C6000TM platform.
For a more detailed discussion on the similarities/differences between the C6211, C6711, and C6712 devices, see the How to Begin Development Today with the TMS320C6211 DSP, How to Begin Development Today with the TMS320C6711 DSP, and How to Begin Development Today with the TMS320C6712 DSP application reports (literature number SPRA474, SPRA522, and SPRA693, respectively).
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TMS320C6712 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS148 - AUGUST 2000
functional block and CPU (DSP core) diagram
SBSRAM SRAM ROM/FLASH I/O Devices
16
External Memory Interface (EMIF)
Timer 0
Timer 1 Enhanced DMA Controller (16 channel)
Interrupt Selector
L1D Cache 2-Way Set Associative 4K Bytes Total Power-Down Logic
PLL (x1, x4)
Boot Configuration
In addition to fixed-point instructions, these functional units execute floating-point instructions.
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PRODUCT PREVIEW
Framing Chips: H.100, MVIP, SCSA, T1, E1 AC97 Devices, SPI Devices, Codecs
Multichannel Buffered Serial Port 1 (McBSP1)
Multichannel Buffered Serial Port 0 (McBSP0)
AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA
L2 Memory 4 Banks 64K Bytes Total
SDRAM
C6712 Digital Signal Processor
L1P Cache Direct Mapped 4K Bytes Total
C67x CPU (DSP Core) Instruction Fetch Instruction Dispatch Instruction Decode Data Path A A Register File Data Path B B Register File Control Registers Control Logic Test In-Circuit Emulation Interrupt Control
.L1 .S1 .M1 .D1
.D2 .M2 .S2 .L2
TMS320C6712 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS148 - AUGUST 2000
CPU (DSP core) description
The CPU fetches VelociTI advanced very-long instruction words (VLIW) (256 bits wide) to supply up to eight 32-bit instructions to the eight functional units during every clock cycle. The VelociTI VLIW architecture features controls by which all eight units do not have to be supplied with instructions if they are not ready to execute. The first bit of every 32-bit instruction determines if the next instruction belongs to the same execute packet as the previous instruction, or whether it should be executed in the following clock as a part of the next execute packet. Fetch packets are always 256 bits wide; however, the execute packets can vary in size. The variable-length execute packets are a key memory-saving feature, distinguishing the C67x CPU from other VLIW architectures. The CPU features two sets of functional units. Each set contains four units and a register file. One set contains functional units .L1, .S1, .M1, and .D1; the other set contains units .D2, .M2, .S2, and .L2. The two register files each contain 16 32-bit registers for a total of 32 general-purpose registers. The two sets of functional units, along with two register files, compose sides A and B of the CPU [see functional block and CPU (DSP Core) diagram and Figure 1]. The four functional units on each side of the CPU can freely share the 16 registers belonging to that side. Additionally, each side features a single data bus connected to all the registers on the other side, by which the two sets of functional units can access data from the register files on the opposite side. While register access by functional units on the same side of the CPU as the register file can service all the units in a single clock cycle, register access using the register file across the CPU supports one read and one write per cycle.
PRODUCT PREVIEW
The C67x CPU executes all C62x instructions. In addition to C62x fixed-point instructions, the six out of eight functional units (.L1, .M1, .D1, .D2, .M2, and .L2) also execute floating-point instructions. The remaining two functional units (.S1 and .S2) also execute the new LDDW instruction which loads 64 bits per CPU side for a total of 128 bits per cycle. Another key feature of the C67x CPU is the load/store architecture, where all instructions operate on registers (as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for all data transfers between the register files and the memory. The data address driven by the .D units allows data addresses generated from one register file to be used to load or store data to or from the other register file. The C67x CPU supports a variety of indirect addressing modes using either linear- or circular-addressing modes with 5- or 15-bit offsets. All instructions are conditional, and most can access any one of the 32 registers. Some registers, however, are singled out to support specific addressing or to hold the condition for conditional instructions (if the condition is not automatically "true"). The two .M functional units are dedicated for multiplies. The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with results available every clock cycle. The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory. The 32-bit instructions destined for the individual functional units are "linked" together by "1" bits in the least significant bit (LSB) position of the instructions. The instructions that are "chained" together for simultaneous execution (up to eight in total) compose an execute packet. A "0" in the LSB of an instruction breaks the chain, effectively placing the instructions that follow it in the next execute packet. If an execute packet crosses the fetch-packet boundary (256 bits wide), the assembler places it in the next fetch packet, while the remainder of the current fetch packet is padded with NOP instructions. The number of execute packets within a fetch packet can vary from one to eight. Execute packets are dispatched to their respective functional units at the rate of one per clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch packet have been dispatched. After decoding, the instructions simultaneously drive all active functional units for a maximum execution rate of eight instructions every clock cycle. While most results are stored in 32-bit registers, they can be subsequently moved to memory as bytes or half-words as well. All load and store instructions are byte-, half-word, or word-addressable.
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TMS320C6712 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS148 - AUGUST 2000
CPU (DSP core) description (continued)
src1
.L1 src2
dst long dst long src
8
8
LD1 32 MSB ST1
32 32
Data Path A
src2
dst src1 .M1 src2
LD1 32 LSB
DA1
.D1
dst src1 src2
2X 1X
DA2
.D2
src2 src1 dst
LD2 32 LSB
src2
.M2 src1 dst
src2
Data Path B
.S2
src1 dst long dst long src
8
Register File B (B0-B15)
8
LD2 32 MSB ST2
32 32 8 8
src1
In addition to fixed-point instructions, these functional units execute floating-point instructions.
Figure 1. TMS320C67xTM CPU (DSP Core) Data Paths
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A A A A A
long src long dst dst .L2 src2
Control Register File
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PRODUCT PREVIEW
A A A A A A A A A
long src long dst dst .S1 src1
8 8
A AAAAA AAAAA AAAAA AAAAA A AAAAA AAAAA AAAAA A AAAAA AAAAA A AAAAA AAAAA AAAAA A AAAAA AAAAA AAAAA A A AAAAA A AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA A A A AAAAA AAAAA AAAAA A AAAAA AAAAA AAAAA A AAAAA AAAAA AAAAA A AAAAA AAAAA A AAAAA AAAAA AAAAA
Register File A (A0-A15)
A A A A A
AAAA A AAAA A A A AAAA AAAA AAAA AAAA AAAA AAAA A AAAA A A AAAA A AAAA AAAA AAAA A AAAA A AAAA AAAA A AAAA A A A AAAA A AAAA AAAA A AAAA A A AAAA A AAAA AAAA A AAAA A AAAA AAAA A AAAA AAAA AAAA A AAAA A A AAAA A AAAA AAAA AAAA
A A A A A A
TMS320C6712 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS148 - AUGUST 2000
signal groups description
RESET NMI EXT_INT7 EXT_INT6 EXT_INT5 EXT_INT4
CLKIN CLKOUT2 CLKOUT1 CLKMODE0 PLLV PLLG PLLF
Reset and Interrupts Clock/PLL
BIG/LITTLE ENDIAN TMS TDO TDI TCK TRST EMU0 EMU1 EMU2 EMU3 EMU4 EMU5
LENDIAN
RSV5 RSV4 RSV3 RSV2 RSV1 RSV0
PRODUCT PREVIEW
IEEE Standard 1149.1 (JTAG) Emulation
Reserved
BOOTMODE Control/Status
BOOTMODE1 BOOTMODE0
16 ED[15:0] CE3 CE2 CE1 CE0 EA[21:2] BE3 BE2 BE1 BE0 20 Data Memory Control Memory Map Space Select ECLKIN ECLKOUT ARE/SDCAS/SSADS AOE/SDRAS/SSOE AWE/SDWE/SSWE ARDY
Address Bus Arbitration Byte Enables EMIF (16-bit) (External Memory Interface)
HOLD HOLDA BUSREQ
Figure 2. CPU (DSP Core) and Peripheral Signals
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TMS320C6712 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS148 - AUGUST 2000
signal groups description (continued)
TOUT1 TINP1
Timer 1
Timer 0
TOUT0 TINP0
Timers
McBSP1
McBSP0
CLKX1 FSX1 DX1
Transmit
Transmit
CLKX0 FSX0 DX0
Receive
Receive
CLKS1
Clock
Clock
CLKS0
McBSPs (Multichannel Buffered Serial Ports)
Figure 3. Peripheral Signals
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PRODUCT PREVIEW
CLKR1 FSR1 DR1
CLKR0 FSR0 DR0
TMS320C6712 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS148 - AUGUST 2000
Terminal Functions Table
SIGNAL NAME NO. TYPE IPD/ IPU CLOCK/PLL CLKIN CLKOUT1 CLKOUT2 CLKMODE0 PLLV PLLG PLLF TMS TDO TDI TCK A3 D7 Y12 C4 A4 C6 B5 B7 A8 A7 A6 B6 B12 C11 B10 D10 B9 D9 I O O I A A A I O/Z I I I I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z IPU IPU IPU IPU IPD IPU IPU IPU IPU IPU IPU IPU IPD IPD IPU Clock Input Clock output at device speed Clock output at half of device speed Clock mode select * Selects whether the CPU clock frequency = input clock frequency x4 or x1 PLL analog VCC connection for the low-pass filter PLL analog GND connection for the low-pass filter PLL low-pass filter connection to external components and a bypass capacitor JTAG EMULATION JTAG test-port mode select JTAG test-port data out JTAG test-port data in JTAG test-port clock JTAG test-port reset Emulation pin 5. Reserved for future use, leave unconnected. Emulation pin 4. Reserved for future use, leave unconnected. Emulation pin 3. Reserved for future use, leave unconnected. Emulation pin 2. Reserved for future use, leave unconnected. Emulation pin 1# Emulation pin 0# BOOTMODE BOOTMODE1 BOOTMODE0 C19 C20 I I IPD IPU Bootmode[1:0] 00 - Reserved, do not use 01 - 8 bit ROM boot with default timings 8-bit 10 - 16-bit ROM boot with default timings 11 - Reserved, do not use LITTLE/BIG ENDIAN FORMAT LENDIAN B17 I IPU Device Endian mode 0 - Big Endian 1 - Little Endian RESETS AND INTERRUPTS RESET NMI EXT_INT7 EXT_INT6 EXT_INT5 A13 C13 E3 D2 C1 I IPU External interrupts interru ts * Edge-driven ( g (rising edge) g g) I I IPU IPD Device reset Nonmaskable interrupt * Edge-driven (rising edge) DESCRIPTION
PRODUCT PREVIEW
TRST EMU5 EMU4 EMU3 EMU2 EMU1 EMU0
EXT_INT4 C2 I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k resistor should be used.) PLLV and PLLG are not part of external voltage supply or ground. See the CLOCK/PLL documentation for information on how to connect these pins. A = Analog signal (PLL Filter) # The EMU0 and EMU1 pins are internally pulled up with 30-k resistors; therefore, for emulation and normal operation, no external pullup/pulldown resistors are necessary. However, for boundary scan operation, pull down the EMU1 and EMU0 pins with a dedicated 1-k resistor.
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TMS320C6712 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS148 - AUGUST 2000
Terminal Functions Table (Continued)
SIGNAL NAME CE3 CE2 CE1 CE0 BE3 BE2 BE1 BE0 HOLDA HOLD BUSREQ ECLKIN ECLKOUT ARE/SDCAS/ SSADS AOE/SDRAS/ SSOE AWE/SDWE/ SSWE ARDY EA21 EA20 EA19 EA18 EA17 EA16 EA15 EA14 EA13 EA12 EA11 EA10 EA9 EA8 NO. V6 W6 W18 V17 V5 Y4 U19 V20 J18 J17 J19 Y11 Y10 V11 W10 V12 Y5 U18 Y18 W17 Y16 V16 Y15 W15 Y14 W14 V14 W13 V10 Y9 V9 O/Z IPU External address (word address) TYPE IPD/ IPU DESCRIPTION
EMIF - CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY O/Z O/Z O/Z O/Z O/Z O/Z O/Z O/Z O/Z I O/Z I O O/Z O/Z O/Z I IPU IPU IPU IPU IPU IPU IPU IPU IPU IPU IPU IPD IPD IPU IPU IPU IPU Byte-enable control * Decoded from the two lowest bits of the internal address y y y * Byte-write enables for most types of memory * C be directly connected to SDRAM read and write mask signal (SDQM) Can b di tl t dt d d it ki l EMIF - BUS ARBITRATION Hold-request-acknowledge to the host Hold request from the host Bus request output EMIF input clock EMIF output clock (based on ECLKIN) Asynchronous memory read enable/SDRAM column-address strobe/SBSRAM address strobe Asynchronous memory output enable/SDRAM row-address strobe/SBSRAM output enable Asynchronous memory write enable/SDRAM write enable/SBSRAM write enable Asynchronous memory ready input EMIF - ADDRESS Memory space enables * Enabled by bits 28 through 31 of the word address * Only one asserted during any external data access
EMIF - ASYNCHRONOUS/SYNCHRONOUS DRAM/SYNCHRONOUS BURST SRAM MEMORY CONTROL
EA7 Y8 I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k resistor should be used.)
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PRODUCT PREVIEW
TMS320C6712 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS148 - AUGUST 2000
Terminal Functions Table (Continued)
SIGNAL NAME EA6 EA5 EA4 EA3 EA2 ED15 ED14 ED13 ED12 ED11 ED10 ED9 NO. W8 V8 W7 V7 Y6 EMIF - DATA T19 T20 T18 R20 R19 P20 P18 N20 N19 N18 M20 M19 L19 L18 K19 K18 TIMERS TOUT1 TINP1 TOUT0 TINP0 CLKS1 CLKR1 CLKX1 DR1 DX1 FSR1 F1 F2 G1 G2 E1 M1 L3 M2 L2 M3 O I O I I I/O/Z I/O/Z I O/Z I/O/Z IPD IPD IPD IPD IPD IPD IPD IPU IPU IPD Timer 1 or general-purpose output Timer 1 or general-purpose input Timer 0 or general-purpose output Timer 0 or general-purpose input External clock source (as opposed to internal) Receive clock Transmit clock Receive data Transmit data Receive frame sync I/O/Z IPU External data O/Z IPU External address (word address) TYPE IPD/ IPU DESCRIPTION EMIF - ADDRESS (CONTINUED)
PRODUCT PREVIEW
ED8 ED7 ED6 ED5 ED4 ED3 ED2 ED1 ED0
MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1)
FSX1 L1 I/O/Z IPD Transmit frame sync I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k resistor should be used.)
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TMS320C6712 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS148 - AUGUST 2000
Terminal Functions Table (Continued)
SIGNAL NAME CLKS0 CLKR0 CLKX0 DR0 DX0 FSR0 FSX0 RSV0 RSV1 RSV2 RSV3 RSV4 RSV5 NO. K3 H3 G3 J1 H2 J3 H1 C12 D12 A5 D3 N2 Y20 A15 A16 A18 B14 B16 B18 C14 C15 C16 C17 RSV D18 D20 E18 E19 E20 F18 F20 G18 G19 G20 H19 I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k resistor should be used.) Reserved (leave unconnected, do not connect to power or ground) ower TYPE IPD/ IPU DESCRIPTION
MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0) I I/O/Z I/O/Z I O/Z I/O/Z I/O/Z O O O O O O IPD IPD IPD IPU IPU IPD IPD IPU IPU IPU External clock source (as opposed to internal) Receive clock Transmit clock Receive data Transmit data Receive frame sync Transmit frame sync RESERVED FOR TEST Reserved (leave unconnected, do not connect to power or ground) Reserved (leave unconnected, do not connect to power or ground) Reserved (leave unconnected, do not connect to power or ground) Reserved (leave unconnected, do not connect to power or ground) Reserved (leave unconnected, do not connect to power or ground) ADDITIONAL RESERVED FOR TEST Reserved (leave unconnected, do not connect to power or ground)
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PRODUCT PREVIEW
TMS320C6712 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS148 - AUGUST 2000
Terminal Functions Table (Continued)
SIGNAL NAME NO. H20 J20 N3 P1 P2 P3 R2 R3 T1 RSV T2 U1 U2 U3 Reserved (leave unconnected, do not connect to power or ground) unconnected TYPE IPD/ IPU DESCRIPTION
ADDITIONAL RESERVED FOR TEST (CONTINUED)
PRODUCT PREVIEW
V1 V2 V4 W4 Y3 I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
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Terminal Functions Table (Continued)
SIGNAL NAME NO. A17 B3 B8 B13 C5 C10 D1 D16 D19 F3 H18 J2 M18 N1 DVDD R1 R18 T3 U5 U7 U12 U16 V13 V15 V19 W3 W9 W12 Y7 Y17 A9 A10 A12 B2 B19 C3 CVDD C7 C18 D5 D6 D11 D14 I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground S 1.8-V 1 8 V supply voltage S 3.3 V su ly 3.3-V supply voltage TYPE DESCRIPTION SUPPLY VOLTAGE PINS
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TMS320C6712 FLOATING POINT DIGITAL SIGNAL PROCESSOR
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Terminal Functions Table (Continued)
SIGNAL NAME NO. D15 F4 F17 K1 K4 K17 L4 L17 L20 R4 CVDD R17 U6 U10 S 1.8-V 1 8 V supply voltage TYPE DESCRIPTION SUPPLY VOLTAGE PINS (CONTINUED)
PRODUCT PREVIEW
U11 U14 U15 V3 V18 W2 W19 GROUND PINS A1 A2 A11 A14 A19 A20 B1 B4 B11 VSS B15 B20 C8 C9 D4 D8 D13 D17 E2 I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground GND Ground pins
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Terminal Functions Table (Continued)
SIGNAL NAME NO. E4 E17 F19 G4 G17 H4 H17 J4 K2 K20 M4 M17 N4 N17 P4 P17 P19 VSS T4 T17 U4 U8 U9 U13 U17 U20 W1 W5 W11 W16 W20 Y1 Y2 Y13 Y19 I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground GND Ground pins TYPE DESCRIPTION GROUND PINS (CONTINUED)
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TMS320C6712 FLOATING POINT DIGITAL SIGNAL PROCESSOR
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development support
TI offers an extensive line of development tools for the TMS320C6000TM DSP platform, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. The following products support development of C6000-based applications: Software Development Tools: Code Composer StudioTM Integrated Development Environment (IDE): including Editor C/C++/Assembly Code Generation, and Debug plus additional development tools Scalable, Real-Time Foundation Software (DSP BIOS), which provides the basic run-time target software needed to support any DSP application. Hardware Development Tools: Extended Development System (XDSTM) Emulator (supports C6000TM DSP multiprocessor system debug) EVM (Evaluation Module) The TMS320 DSP Development Support Reference Guide (SPRU011) contains information about development-support products for all TMS320TM DSP family member devices, including documentation. See this document for further information on TMS320TM DSP documentation or any TMS320TM DSP support products from Texas Instruments. An additional document, the TMS320 Third-Party Support Reference Guide (SPRU052), contains information about TMS320TM DSP-related products from other companies in the industry. To receive TMS320TM DSP literature, contact the Literature Response Center at 800/477-8924. For a complete listing of development-support tools for the TMS320C6000TM DSP platform, visit the Texas Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL) and under "Development Tools", select "Digital Signal Processors". For information on pricing and availability, contact the nearest TI field sales office or authorized distributor.
PRODUCT PREVIEW
Code Composer Studio, XDS, C6000, and TMS320 are trademarks of Texas Instruments.
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device and development-support tool nomenclature To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all TMS320TM DSP devices and support tools. Each TMS320TM DSP family member has one of three prefixes: TMX, TMP, or TMS. Texas Instruments recommends two of three possible prefix designators for support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS). Device development evolutionary flow: TMX Experimental device that is not necessarily representative of the final device's electrical specifications Final silicon die that conforms to the device's electrical specifications but has not completed quality and reliability verification Fully qualified production device
TMP
TMS
Support tool development evolutionary flow: TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing. Fully qualified development-support product
TMDS
TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer: "Developmental product is intended for internal evaluation purposes." TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies. Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used. TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type, the temperature range (for example, blank is the default commercial temperature range), and the device speed range in megahertz (for example, -100 is 100 MHz). Figure 4 provides a legend for reading the complete device name for any TMS320C6000TM DSP family member.
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TMS320C6712 FLOATING POINT DIGITAL SIGNAL PROCESSOR
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device and development-support tool nomenclature (continued)
TMS 320 PREFIX TMX = TMP = TMS = SMJ = SM = Experimental device Prototype device Qualified device MIL-STD-883C High Rel (non-883C) C 6712 GFN () 100 DEVICE SPEED RANGE 100 MHz 120 MHz 150 MHz 167 MHz 200 MHz 233 MHz 250 MHz 300 MHz
DEVICE FAMILY 320 = TMS320 family
TEMPERATURE RANGE (DEFAULT: 0C TO 90C) Blank = 0C to 90C, commercial temperature A = -40C to 105C, extended temperature PACKAGE TYPE GFN = 256-pin plastic BGA GGP = 352-pin plastic BGA GJC = 352-pin plastic BGA GJL = 352-pin plastic BGA GLS = 384-pin plastic BGA GLW = 340-pin plastic BGA GHK = 288-pin plastic MicroStar BGAt
TECHNOLOGY C = CMOS
PRODUCT PREVIEW
DEVICE '6x DSP: 6201 6202 6202B 6203
6204 6205 6211 6701
6711 6712
BGA =
Ball Grid Array
Figure 4. TMS320C6000TM DSP Platform Device Nomenclature (Including the TMS320C6712 Device)
MicroStar BGA is a trademark of Texas Instruments.
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documentation support
Extensive documentation supports all TMS320t DSP family generations of devices from product announcement through applications development. The types of documentation available include: data sheets, such as this document, with design specifications; complete user's reference guides for all devices and tools; technical briefs; development-support tools; on-line help; and hardware and software applications. The following is a brief, descriptive list of support documentation specific to the C6000t DSP devices: The TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189) describes the C6000t DSP core (CPU) architecture, instruction set, pipeline, and associated interrupts. The TMS320C6000 Peripherals Reference Guide (literature number SPRU190) describes the functionality of the peripherals available on the C6000t DSP platform of devices, such as the 64-/32-/16-bit external memory interfaces (EMIFs), 32-/16-bit host-port interfaces (HPIs), multichannel buffered serial ports (McBSPs), direct-memory-access (DMA), enhanced direct-memory-access (EDMA) controller, expansion bus (XB), peripheral component interconnect (PCI), clocking and phase-locked loop (PLL); and power-down modes. This guide also includes information on internal data and program memories. The TMS320C6000 Technical Brief (literature number SPRU197) gives an introduction to the C62x/C67x devices, associated development tools, and third-party support.
See the Worldwide Web URL for the application report How To Begin Development Today with the TMS320C6712 DSP (literature number SPRA693), which describes in more detail the compatibility and similarities/differences between the C6711 and C6712 devices.
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PRODUCT PREVIEW
The tools support documentation is electronically available within the Code Composer StudioTM Integrated Development Environment (IDE). For a complete listing of C6000t DSP latest documentation, visit the Texas Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL).
TMS320C6712 FLOATING POINT DIGITAL SIGNAL PROCESSOR
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clock PLL
All of the internal C6712 clocks are generated from a single source through the CLKIN pin. This source clock either drives the PLL, which multiplies the source clock in frequency to generate the internal CPU clock, or bypasses the PLL to become the internal CPU clock. To use the PLL to generate the CPU clock, the external PLL filter circuit must be properly designed. Figure 5 shows the external PLL circuitry for either x1 (PLL bypass) or x4 PLL multiply modes. Figure 6 shows the external PLL circuitry for a system with ONLY x1 (PLL bypass) mode. To minimize the clock jitter, a single clean power supply should power both the C6712 device and the external clock oscillator circuit. Noise coupling into PLLF will directly impact PLL clock jitter. The minimum CLKIN rise and fall times should also be observed. For the input clock timing requirements, see the input and output clocks electricals section.
3.3V PLLV EMI Filter
PLL
CLKMODE0 C3 10 mF C4 0.1 mF CLKIN CLKIN LOOP FILTER PLLMULT PLLCLK
Internal to C6712
PRODUCT PREVIEW
1 0
CPU CLOCK
Available Multiply Factors CLKMODE0 0 1 PLL Multiply Factors x1(BYPASS) x4 CPU Clock Frequency f(CPU CLOCK) 1 x f(CLKIN) 4 x f(CLKIN) C2 C1 PLLG (For C1, C2, and R1 values, see Table 2.) R1 1 0 PLLF
NOTES: A. Keep the lead length and the number of vias between the PLLF pin, the PLLG pin, and R1, C1, and C2 to a minimum. In addition, place all PLL external components (R1, C1, C2, C3, C4, and the EMI Filter) as close to the C6000TM DSP device as possible. For the best performance, TI recommends that all the PLL external components be on a single side of the board without jumpers, switches, or components other than the ones shown. B. For reduced PLL jitter, maximize the spacing between switching signals and the PLL external components (R1, C1, C2, C3, C4, and the EMI filter). C. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DVDD. D. EMI filter manufacturer: TDK part number ACF451832-333, 223, 153, 103. Panasonic part number EXCCET103U.
Figure 5. External PLL Circuitry for Either PLL x4 Mode or x1 (Bypass) Mode
3.3V PLLV CLKMODE0 Internal to C6712
PLL
PLLMULT PLLCLK
CLKIN
CLKIN LOOP FILTER
CPU CLOCK
NOTES: A. For a system with ONLY PLL x1 (bypass) mode, short the PLLF terminal to the PLLG terminal. B. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DVDD.
Figure 6. External PLL Circuitry for x1 (Bypass) Mode Only
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PLLG
PLLF
TMS320C6712 FLOATING POINT DIGITAL SIGNAL PROCESSOR
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clock PLL (continued)
Table 2. C6712 PLL Component Selection Table
CLKIN RANGE (MHz) CPU CLOCK FREQUENCY (CLKOUT1) RANGE (MHz) CLKOUT2 RANGE (MHz) R1 () C1 (nF) C2 (pF) TYPICAL LOCK TIME (s)
CLKMODE
x4 16.3-37.5 65-150 32.5-75 60.4 27 560 75 Under some operating conditions, the maximum PLL lock time may vary as much as 150% from the specified typical value. For example, if the typical lock time is specified as 100 s, the maximum value may be as long as 250 s.
power-supply sequencing
TI DSPs do not require specific power sequencing between the core supply and the I/O supply. However, systems should be designed to ensure that neither supply is powered up for extended periods of time if the other supply is below the proper operating voltage. system-level design considerations
power-supply design considerations For systems using the C6000TM DSP platform of devices, the core supply may be required to provide in excess of 2 A per DSP until the I/O supply is powered up. This extra current condition is a result of uninitialized logic within the DSP(s) and is corrected once the CPU sees an internal clock pulse. With the PLL enabled, as the I/O supply is powered on, a clock pulse is produced stopping the extra current draw from the supply. With the PLL disabled, an external clock pulse may be required to stop this extra current draw. A normal current state returns once the I/O power supply is turned on and the CPU sees a clock pulse. Decreasing the amount of time between the core supply power up and the I/O supply power up can minimize the effects of this current draw. A dual-power supply with simultaneous sequencing, such as available with TPS563xx controllers or PT69xx plug-in power modules, can be used to eliminate the delay between core and I/O power up [see the Using the TPS56300 to Power DSPs application report (literature number SLVA088)]. A Schottky diode can also be used to tie the core rail to the I/O rail, effectively pulling up the I/O power supply to a level that can help initialize the logic within the DSP. Core and I/O supply voltage regulators should be located close to the DSP (or DSP array) to minimize inductance and resistance in the power delivery path. Additionally, when designing for high-performance applications utilizing the C6000TM platform of DSPs, the PC board should include separate power planes for core, I/O, and ground, all bypassed with high-quality low-ESL/ESR capacitors.
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PRODUCT PREVIEW
System-level design considerations, such as bus contention, may require supply sequencing to be implemented. In this case, the core supply should be powered up at the same time as, or prior to (and powered down after), the I/O buffers. This is to ensure that the I/O buffers receive valid inputs from the core before the output buffers are powered up, thus, preventing bus contention with other chips on the board.
TMS320C6712 FLOATING POINT DIGITAL SIGNAL PROCESSOR
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absolute maximum ratings over operating case temperature range (unless otherwise noted)
Supply voltage range, CVDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 2.3 V Supply voltage range, DVDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 4 V Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 4 V Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 4 V Operating case temperature range, TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0_C to 90_C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65_C to 150_C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
MIN CVDD DVDD VSS VIH VIL IOH IOL TC Supply voltage, Core Supply voltage, I/O Supply ground High-level input voltage Low-level input voltage All signals except CLKOUT1, CLKOUT2, and ECLKOUT High-level High level output current Low level output current Low-level Operating case temperature CLKOUT1, CLKOUT2, and ECLKOUT All signals except CLKOUT1, CLKOUT2, and ECLKOUT CLKOUT1, CLKOUT2, and ECLKOUT 0 1.71 3.14 0 2 0.8 -4 -8 4 8 90 NOM 1.8 3.3 0 MAX 1.89 3.46 0 UNIT V V V V V mA mA mA mA _C
PRODUCT PREVIEW
electrical characteristics over recommended ranges of supply voltage and operating case temperature (unless otherwise noted)
PARAMETER VOH VOL II IOZ IDD2V IDD2V IDD3V Ci High-level output voltage Low-level output voltage Input current Off-state output current Supply current, CPU + CPU memory access Supply current, peripherals Supply current, I/O pins Input capacitance TEST CONDITIONS DVDD = MIN, DVDD = MIN, VI = VSS to DVDD VO = DVDD or 0 V CVDD = NOM, CPU clock = 100 MHz CVDD = NOM, CPU clock = 100 MHz DVDD = NOM, CPU clock = 100 MHz TBD TBD TBD 7 IOH = MAX IOL = MAX MIN 2.4 0.6 150 10 TYP MAX UNIT V V uA uA mA mA mA pF
Co Output capacitance 7 pF For test conditions shown as MIN, MAX, or NOM, use the appropriate value specified in the recommended operating conditions table. Measured with average activity (50% high/50% low power). For more details on CPU, peripheral, and I/O activity, see the TMS320C6000 Power Consumption Summary application report (literature number SPRA486).
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PARAMETER MEASUREMENT INFORMATION
IOL Tester Pin Electronics 50 Output Under Test
Vcomm
CT IOH
Where:
Typical distributed load circuit capacitance
IOL IOH Vcomm CT
= = = =
2 mA 2 mA 0.8 V 10-15-pF typical load-circuit capacitance
Figure 7. Test Load Circuit for AC Timing Measurements
signal transition levels
All input and output timing parameters are referenced to 1.5 V for both "0" and "1" logic levels.
Vref = 1.5 V
Figure 8. Input and Output Voltage Reference Levels for ac Timing Measurements All rise and fall transition timing parameters are referenced to 20% for "0" logic levels (low) and 80% for "1" logic levels (high) of VIH or VOH.
Vref = 80% (High)
Vref = 20% (Low)
Figure 9. Rise and Fall Transition Time Voltage Reference Levels
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TMS320C6712 FLOATING POINT DIGITAL SIGNAL PROCESSOR
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INPUT AND OUTPUT CLOCKS timing requirements for CLKIN (see Figure 10)
-100 NO. 1 2 3 tc(CLKIN) tw(CLKINH) tw(CLKINL) tt(CLKIN) Cycle time, CLKIN Pulse duration, CLKIN high Pulse duration, CLKIN low CLKMODE = x4 MIN 40 0.4C 0.4C 5 MAX CLKMODE = x1 MIN 10 0.45C 0.45C 1 MAX ns ns ns ns UNIT
4 Transition time, CLKIN The reference points for the rise and fall transitions are measured at 20% and 80% of VIH. C = CLKIN cycle time in ns. For example, when CLKIN frequency is 10 MHz, use C = 100 ns. Minimum period on CLKIN is tested at 4x mode with ECLKIN = 1/4 CLKIN.
1 2
4
PRODUCT PREVIEW
CLKIN 3 4
Figure 10. CLKIN Timings
switching characteristics over recommended operating conditions for CLKOUT1#|| (see Figure 11)
-100 NO. 1 2 3 4 tc(CKO1) tw(CKO1H) tw(CKO1L) tt(CKO1) PARAMETER Cycle time, CLKOUT1 Pulse duration, CLKOUT1 high Pulse duration, CLKOUT1 low Transition time, CLKOUT1 CLKMODE = x4 MIN P - 0.7 (P/2) - 0.7 (P/2) - 0.7 MAX P + 0.7 (P/2 ) + 0.7 (P/2 ) + 0.7 0.6 CLKMODE = x1 MIN P - 0.7 PH - 0.7 PL - 0.7 MAX P + 0.7 PH + 0.7 PL + 0.7 0.6 ns ns ns ns UNIT
The reference points for the rise and fall transitions are measured at 20% and 80% of VOH. # PH is the high period of CLKIN in ns and PL is the low period of CLKIN in ns. || P = 1/CPU clock frequency in nanoseconds (ns)
1 2 CLKOUT1 3
4
4
Figure 11. CLKOUT1 Timings
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INPUT AND OUTPUT CLOCKS (CONTINUED) switching characteristics over recommended operating conditions for CLKOUT2 (see Figure 12)
-100 NO NO. 1 2 3 tc(CKO2) tw(CKO2H) tw(CKO2L) tt(CKO2) Cycle time, CLKOUT2 Pulse duration, CLKOUT2 high Pulse duration, CLKOUT2 low PARAMETER MIN 2P - 0.7 P - 0.7 P - 0.7 MAX 2P + 0.7 P + 0.7 P + 0.7 0.6 UNIT ns ns ns ns
4 Transition time, CLKOUT2 P = 1/CPU clock frequency in ns The reference points for the rise and fall transitions are measured at 20% and 80% of VOH. 1 2 CLKOUT2 3 4
Figure 12. CLKOUT2 Timings
timing requirements for ECLKIN (see Figure 13)
-100 NO. NO 1 2 3 4 tc(EKI) tw(EKIH) tw(EKIL) tt(EKI) Cycle time, ECLKIN Pulse duration, ECLKIN high Pulse duration, ECLKIN low Transition time, ECLKIN MIN 15 6.8 6.8 3 MAX UNIT ns ns ns ns
The reference points for the rise and fall transitions are measured at 20% and 80% of VIH. Minimum period on ECLKIN is tested with CLKIN = ECLKIN. 1 2 ECLKIN 3 4
4
Figure 13. ECLKIN Timings
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PRODUCT PREVIEW
4
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INPUT AND OUTPUT CLOCKS (CONTINUED) switching characteristics over recommended operating conditions for ECLKOUT (see Figure 14)
-100 NO. NO 1 2 3 4 5 tc(EKO) tw(EKOH) tw(EKOL) tt(EKO) td(EKIH-EKOH) td(EKIL-EKOL) PARAMETER Cycle time, ECLKOUT Pulse duration, ECLKOUT high Pulse duration, ECLKOUT low Transition time, ECLKOUT Delay time, ECLKIN high to ECLKOUT high 1 1 MIN E - 0.7 EH - 0.7 EL - 0.7 MAX E + 0.7 EH + 0.7 EL + 0.7 0.6 7 7 UNIT ns ns ns ns ns ns
6 Delay time, ECLKIN low to ECLKOUT low The reference points for the rise and fall transitions are measured at 20% and 80% of VOH. E = ECLKIN period in ns EH is the high period of ECLKIN in ns and EL is the low period of ECLKIN in ns.
PRODUCT PREVIEW
ECLKIN 6 5 ECLKOUT 2 1 3
4
4
Figure 14. ECLKOUT Timings
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TMS320C6712 FLOATING POINT DIGITAL SIGNAL PROCESSOR
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ASYNCHRONOUS MEMORY TIMING timing requirements for asynchronous memory cycles (see Figure 15-Figure 16)
-100 NO. NO 3 4 6 7 tsu(EDV-AREH) th(AREH-EDV) tsu(ARDY-EKOH) th(EKOH-ARDY) Setup time, EDx valid before ARE high Hold time, EDx valid after ARE high Setup time, ARDY valid before ECLKOUT high Hold time, ARDY valid after ECLKOUT high MIN 13 1 6 1 MAX UNIT ns ns ns
ns To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. The ARDY signal is recognized in the cycle for which the setup and hold time is met. To use ARDY as an asynchronous input, the pulse width of the ARDY signal should be wide enough (e.g., pulse width = 2E) to ensure setup and hold time is met. RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are programmed via the EMIF CE space control registers.
switching characteristics over recommended operating conditions for asynchronous memory cycles (see Figure 15-Figure 16)
NO. NO 1 2 5 8 9 10 tosu(SELV-AREL) toh(AREH-SELIV) td(EKOH-AREV) tosu(SELV-AWEL) toh(AWEH-SELIV) td(EKOH-AWEV) PARAMETER Output setup time, select signals valid to ARE low Output hold time, ARE high to select signals invalid Delay time, ECLKOUT high to ARE vaild Output setup time, select signals valid to AWE low Output hold time, AWE high to select signals invalid Delay time, ECLKOUT high to AWE vaild MIN RS * E - 3 RH * E - 3 1.5 WS * E - 3 WH * E - 3 1.5 11 11 MAX UNIT ns ns ns ns ns
ns RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are programmed via the EMIF CE space control registers. E = ECLKOUT period in ns Select signals include: CEx, BE[3:0], EA[21:2], AOE; and for writes, include ED[15:0].
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PRODUCT PREVIEW
-100
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ASYNCHRONOUS MEMORY TIMING (CONTINUED)
Setup = 2 ECLKOUT 1 CEx 1 BE[3:0] 1 EA[21:2] Address 3 4 ED[15:0] 1 AOE/SDRAS/SSOE 5 ARE/SDCAS/SSADS AWE/SDWE/SSWE 6 ARDY AOE/SDRAS/SSOE, ARE/SDCAS/SSADS, and AWE/SDWE/SSWE operate as AOE (identified under select signals), ARE, and AWE, respectively, during asynchronous memory accesses. Read Data 2 5 BE 2 2 2 Strobe = 3 Not Ready Hold = 2
PRODUCT PREVIEW
7 6
7
Figure 15. Asynchronous Memory Read Timing
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ASYNCHRONOUS MEMORY TIMING (CONTINUED)
Setup = 2 ECLKOUT 8 CEx 8 BE[3:0] 8 EA[21:2] 8 ED[15:0] AOE/SDRAS/SSOE ARE/SDCAS/SSADS 10 AWE/SDWE/SSWE 7 6 ARDY AOE/SDRAS/SSOE, ARE/SDCAS/SSADS, and AWE/SDWE/SSWE operate as AOE (identified under select signals), ARE, and AWE, respectively, during asynchronous memory accesses. 6 7 10 Write Data Address 9 BE 9 9 9 Strobe = 3 Not Ready Hold = 2
Figure 16. Asynchronous Memory Write Timing
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TMS320C6712 FLOATING POINT DIGITAL SIGNAL PROCESSOR
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SYNCHRONOUS-BURST MEMORY TIMING timing requirements for synchronous-burst SRAM cycles (see Figure 17)
-100 NO. NO 6 7 tsu(EDV-EKOH) th(EKOH-EDV) Setup time, read EDx valid before ECLKOUT high Hold time, read EDx valid after ECLKOUT high MIN 6 1 MAX UNIT ns
ns The C6712 SBSRAM interface takes advantage of the internal burst counter in the SBSRAM. Accesses default to incrementing 4-word bursts, but random bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain continuous data flow.
switching characteristics over recommended operating conditions for synchronous-burst SRAM cycles (see Figure 17 and Figure 18)
-100 NO. NO 1 2 3 4 5 8 9 10 11 12 td(EKOH-CEV) td(EKOH-BEV) td(EKOH-BEIV) td(EKOH-EAV) td(EKOH-EAIV) td(EKOH-ADSV) td(EKOH-OEV) td(EKOH-EDV) td(EKOH-EDIV) td(EKOH-WEV) PARAMETER Delay time, ECLKOUT high to CEx valid Delay time, ECLKOUT high to BEx valid Delay time, ECLKOUT high to BEx invalid Delay time, ECLKOUT high to EAx valid Delay time, ECLKOUT high to EAx invalid Delay time, ECLKOUT high to ARE/SDCAS/SSADS valid Delay time, ECLKOUT high to, AOE/SDRAS/SSOE valid Delay time, ECLKOUT high to EDx valid Delay time, ECLKOUT high to EDx invalid Delay time, ECLKOUT high to AWE/SDWE/SSWE valid 1.5 1.5 11 1.5 1.5 1.5 11 11 11 1.5 11 MIN 1.5 MAX 11 11 UNIT ns ns ns ns ns ns ns ns ns
PRODUCT PREVIEW
ns The C6712 SBSRAM interface takes advantage of the internal burst counter in the SBSRAM. Accesses default to incrementing 4-word bursts, but random bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain continuous data flow. ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM accesses.
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TMS320C6712 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS148 - AUGUST 2000
SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED)
ECLKOUT 1 CEx BE[3:0] EA[21:2] 6 ED[15:0] 8 ARE/SDCAS/SSADS 9 AOE/SDRAS/SSOE AWE/SDWE/SSWE ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM accesses. 9 8 Q1 2 BE1 4 EA 7 Q2 Q3 Q4 3 BE2 BE3 5 BE4 1
Figure 17. SBSRAM Read Timing
ECLKOUT 1 CEx 2 BE1 4 EA[21:2] 10 Q1 8 ARE/SDCAS/SSADS AOE/SDRAS/SSOE 12 AWE/SDWE/SSWE 12 8 EA 11 Q2 Q3 Q4 3 BE2 BE3 5 BE4 1
BE[3:0]
ED[15:0]
ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM accesses.
Figure 18. SBSRAM Write Timing
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PRODUCT PREVIEW
TMS320C6712 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS148 - AUGUST 2000
SYNCHRONOUS DRAM TIMING timing requirements for synchronous DRAM cycles (see Figure 19)
-100 NO. NO 6 tsu(EDV-EKOH) th(EKOH-EDV) Setup time, read EDx valid before ECLKOUT high MIN 6 MAX UNIT ns
7 Hold time, read EDx valid after ECLKOUT high 1 ns The C6712 SDRAM interface takes advantage of the internal burst counter in the SDRAM. Accesses default to incrementing 4-word bursts, but random bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain continuous data flow.
switching characteristics over recommended operating conditions for synchronous DRAM cycles (see Figure 19-Figure 25)
-100 NO. NO 1 2 3 4 5 8 9 10 11 td(EKOH-CEV) td(EKOH-BEV) td(EKOH-BEIV) td(EKOH-EAV) td(EKOH-EAIV) td(EKOH-CASV) td(EKOH-EDV) td(EKOH-EDIV) td(EKOH-WEV) td(EKOH-RAS) PARAMETER Delay time, ECLKOUT high to CEx valid Delay time, ECLKOUT high to BEx valid Delay time, ECLKOUT high to BEx invalid Delay time, ECLKOUT high to EAx valid Delay time, ECLKOUT high to EAx invalid Delay time, ECLKOUT high to ARE/SDCAS/SSADS valid Delay time, ECLKOUT high to EDx valid Delay time, ECLKOUT high to EDx invalid Delay time, ECLKOUT high to AWE/SDWE/SSWE valid 1.5 1.5 11 1.5 1.5 11 11 1.5 11 MIN 1.5 MAX 11 11 UNIT ns ns ns ns ns ns ns ns ns
PRODUCT PREVIEW
12 Delay time, ECLKOUT high to, AOE/SDRAS/SSOE valid 1.5 11 ns The C6712 SDRAM interface takes advantage of the internal burst counter in the SDRAM. Accesses default to incrementing 4-word bursts, but random bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain continuous data flow. ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses.
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TMS320C6712 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS148 - AUGUST 2000
SYNCHRONOUS DRAM TIMING (CONTINUED)
READ ECLKOUT 1 CEx BE[3:0] 4 Bank 4 Column 4 EA12 6 ED[15:0] AOE/SDRAS/SSOE 8 ARE/SDCAS/SSADS AWE/SDWE/SSWE ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses. 8 D1 7 D2 D3 D4 2 BE1 5 3 BE2 BE3 BE4 1
EA[21:13] EA[11:2]
5
5
Figure 19. SDRAM Read Command (CAS Latency 3)
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PRODUCT PREVIEW
TMS320C6712 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS148 - AUGUST 2000
SYNCHRONOUS DRAM TIMING (CONTINUED)
WRITE ECLKOUT 1 CEx 2 BE[3:0] 4 EA[21:13] 4 EA[11:2] 4 EA12 9 ED[15:0] D1 9 D2 D3 D4 10 Column 5 Bank 5 BE1 5 4 BE2 BE3 BE4 3 2
PRODUCT PREVIEW
AOE/SDRAS/SSOE 8 ARE/SDCAS/SSADS 11 AWE/SDWE/SSWE ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses. 11 8
Figure 20. SDRAM Write Command
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TMS320C6712 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS148 - AUGUST 2000
SYNCHRONOUS DRAM TIMING (CONTINUED)
ACTV ECLKOUT 1 CEx BE[3:0] 4 Bank Activate 4 Row Address 4 Row Address 5 1
EA[21:13] EA[11:2]
5
5
EA12 ED[15:0]
12 AOE/SDRAS/SSOE ARE/SDCAS/SSADS AWE/SDWE/SSWE
12
ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses.
Figure 21. SDRAM ACTV Command
DCAB ECLKOUT 1 CEx BE[3:0] EA[21:13, 11:2] 4 EA12 ED[15:0] 12 AOE/SDRAS/SSOE ARE/SDCAS/SSADS 11 AWE/SDWE/SSWE ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses. 11 12 5 1
Figure 22. SDRAM DCAB Command
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PRODUCT PREVIEW
TMS320C6712 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS148 - AUGUST 2000
SYNCHRONOUS DRAM TIMING (CONTINUED)
DEAC ECLKOUT 1 CEx BE[3:0] 4 EA[21:13] EA[11:2] 4 EA12 ED[15:0] 12 AOE/SDRAS/SSOE 12 5 Bank 5 1
PRODUCT PREVIEW
ARE/SDCAS/SSADS 11 AWE/SDWE/SSWE ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses. 11
Figure 23. SDRAM DEAC Command
REFR ECLKOUT 1 CEx BE[3:0] EA[21:2] EA12 ED[15:0] 12 AOE/SDRAS/SSOE 8 ARE/SDCAS/SSADS AWE/SDWE/SSWE ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses. 8 12 1
Figure 24. SDRAM REFR Command
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TMS320C6712 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS148 - AUGUST 2000
SYNCHRONOUS DRAM TIMING (CONTINUED)
MRS ECLKOUT 1 CEx BE[3:0] 4 MRS value 5 1
EA[21:2] ED[15:0]
12 AOE/SDRAS/SSOE 8 ARE/SDCAS/SSADS 11 AWE/SDWE/SSWE
12
8
11
ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses.
Figure 25. SDRAM MRS Command
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PRODUCT PREVIEW
TMS320C6712 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS148 - AUGUST 2000
HOLD/HOLDA TIMING timing requirements for the HOLD/HOLDA cycles (see Figure 26)
-100 NO. NO 3 toh(HOLDAL-HOLDL) E = ECLKIN period in ns Hold time, HOLD low after HOLDA low MIN E MAX UNIT ns
switching characteristics over recommended operating conditions for the HOLD/HOLDA cycles (see Figure 26)
NO. 1 2 4 5 td(HOLDL-EMHZ) td(EMHZ-HOLDAL) td(HOLDH-EMLZ) td(EMLZ-HOLDAH) PARAMETER Delay time, HOLD low to EMIF Bus high impedance Delay time, EMIF Bus high impedance to HOLDA low Delay time, HOLD high to EMIF Bus low impedance Delay time, EMIF Bus low impedance to HOLDA high -100 -150 MIN 2E 0 2E 0 MAX 2E 7E 2E UNIT ns ns ns
PRODUCT PREVIEW
ns E = ECLKIN period in ns EMIF Bus consists of CE[3:0], BE[3:0], ED[15:0], EA[21:2], ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE. All pending EMIF transactions are allowed to complete before HOLDA is asserted. If no bus transactions are occurring, then the minimum delay time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1. DSP Owns Bus External Requestor Owns Bus 3 HOLD 2 HOLDA EMIF Bus 1 C6712 4 C6712 5 DSP Owns Bus
EMIF Bus consists of CE[3:0], BE[3:0], ED[15:0], EA[21:2], ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE.
Figure 26. HOLD/HOLDA Timing
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TMS320C6712 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS148 - AUGUST 2000
BUSREQ TIMING switching characteristics over recommended operating conditions for the BUSREQ cycles (see Figure 27)
-100 NO. NO 1 td(EKOH-BUSRV) PARAMETER Delay time, ECLKOUT high to BUSREQ valid MIN 2 MAX 11 UNIT ns
ECLKOUT
1 BUSREQ
1
Figure 27. BUSREQ Timing
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PRODUCT PREVIEW
TMS320C6712 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS148 - AUGUST 2000
RESET TIMING timing requirements for reset (see Figure 28)
-100 NO. NO Width of the RESET pulse (PLL stable) 1 14 15 tw(RST) tsu(BOOT) th(BOOT) Width of the RESET pulse (PLL needs to sync up) Setup time, BOOTMODE[1:0] configuration bits valid before RESET high Hold time, BOOTMODE[1:0] configuration bits valid after RESET high MIN 10P 250 2P 2P MAX UNIT ns s ns
ns P = 1/CPU clock frequency in ns. For example, when running parts at 100 MHz, use P = 10 ns. This parameter applies to CLKMODE x1 when CLKIN is stable, and applies to CLKMODE x4 when CLKIN and PLL are stable. This parameter applies to CLKMODE x4 only (it does not apply to CLKMODE x1). The RESET signal is not connected internally to the clock PLL circuit. The PLL, however, may need up to 250 s to stabilize following device power up or after PLL configuration has been changed. During that time, RESET must be asserted to ensure proper device operation. See the clock PLL section for PLL lock times.
switching characteristics over recommended operating conditions during reset# (see Figure 28)
-100 NO. NO PARAMETER td(RSTL-ECKI) td(RSTH-ECKI) td(RSTL-EMIFZHZ) td(RSTH-EMIFZV) td(RSTL-EMIFHIV) td(RSTH-EMIFHV) td(RSTL-EMIFLIV) td(RSTH-EMIFLV) td(RSTL-ZHZ) td(RSTH-ZV) Delay time, RESET low to ECLKIN synchronized internally Delay time, RESET high to ECLKIN synchronized internally Delay time, RESET low to EMIF Z group high impedance Delay time, RESET high to EMIF Z group valid Delay time, RESET low to EMIF high group invalid Delay time, RESET high to EMIF high group valid Delay time, RESET low to EMIF low group invalid Delay time, RESET high to EMIF low group valid Delay time, RESET low to Z group high impedance Delay time, RESET high to Z group valid 2P 2P 2P + 3E 3P + 4E 2P + 3E 3P + 4E
PRODUCT PREVIEW
MIN 2P + 3E 2P + 3E 2P + 3E
MAX 3P + 4E 3P + 4E 3P + 4E
UNIT ns ns ns ns ns ns ns ns ns ns
2 3 4 5 6 7 8 9 12 13
P = 1/CPU clock frequency in ns. For example, when running parts at 100 MHz, use P = 10 ns. E = ECLKIN period in ns # EMIF Z group consists of: EA[21:2], ED[15:0], CE[3:0], BE[3:0], ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE EMIF high group consists of: HOLDA EMIF low group consists of: BUSREQ Z group consists of: CLKX0, CLKX1, FSX0, FSX1, DX0, DX1, CLKR0, CLKR1, FSR0, FSR1, TOUT0, and TOUT1.
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TMS320C6712 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS148 - AUGUST 2000
RESET TIMING (CONTINUED)
CLKOUT1 CLKOUT2 1 14 RESET 2 ECLKIN 4 EMIF Z Group 6 EMIF High Group 8 EMIF Low Group 12 9 13 7 5 3 15
BOOTMODE[1:0] EMIF Z group consists of: EMIF high group consists of: EMIF low group consists of: Z group consists of: EA[21:2], ED[15:0], CE[3:0], BE[3:0], ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE HOLDA BUSREQ CLKX0, CLKX1, FSX0, FSX1, DX0, DX1, CLKR0, CLKR1, FSR0, FSR1, TOUT0, and TOUT1.
Figure 28. Reset Timing
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PRODUCT PREVIEW
Z Group
TMS320C6712 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS148 - AUGUST 2000
EXTERNAL INTERRUPT TIMING timing requirements for external interrupts (see Figure 29)
-100 NO. NO 1 tw(ILOW) tw(IHIGH) Width of the interrupt pulse low Width of the interrupt pulse high MIN 2E 2E MAX UNIT ns ns
2 E = ECLKIN period in ns
1 EXT_INT, NMI
2
Figure 29. External/NMI Interrupt Timing
PRODUCT PREVIEW
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TMS320C6712 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS148 - AUGUST 2000
MULTICHANNEL BUFFERED SERIAL PORT TIMING timing requirements for McBSP (see Figure 30)
-100 NO. NO 2 3 5 6 7 8 10 11 tc(CKRX) tw(CKRX) tsu(FRH-CKRL) th(CKRL-FRH) tsu(DRV-CKRL) th(CKRL-DRV) tsu(FXH-CKXL) th(CKXL-FXH) Cycle time, CLKR/X Pulse duration, CLKR/X high or CLKR/X low Setup time external FSR high before CLKR low time, Hold time, external FSR high after CLKR low time Setup time DR valid before CLKR low time, Hold time, DR valid after CLKR low time Setup time, external FSX high before CLKX low time Hold time external FSX high after CLKX low time, CLKR/X ext CLKR/X ext CLKR int CLKR ext CLKR int CLKR ext CLKR int CLKR ext CLKR int CLKR ext CLKX int CLKX ext CLKX int CLKX ext MIN 4P P-1 20 1 6 3 22 3 3 4 23 6 3 ns 1 ns ns ns ns ns MAX UNIT ns ns
CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted. P = 1/CPU clock frequency in ns. The maximum bit rate for McBSP-to-McBSP communications is 25 MHz; therefore, the minimum CLKR/X clock cycle is either four times the CPU cycle time (4P), or 40 ns (25 MHz), whichever value is larger. For example, when running parts at 100 MHz (P = 10 ns), use 40 ns as the minimum CLKR/X clock cycle (by setting the appropriate CLKGDV ratio or external clock source). The maximum bit rate for McBSP-to-McBSP communications applies to the following hardware configuration: the serial port is a master of the clock and frame syncs (with CLKR connected to CLKX, FSR connected to FSX, CLKXM = FSXM = 1, and CLKRM = FSRM = 0) in data delay 1 or 2 mode (R/XDATDLY = 01b or 10b) and the other device the McBSP communicates to is a slave.
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PRODUCT PREVIEW
TMS320C6712 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS148 - AUGUST 2000
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) switching characteristics over recommended operating conditions for McBSP (see Figure 30)
-100 NO. NO 1 2 3 4 9 12 13 td(CKSH-CKRXH) tc(CKRX) tw(CKRX) td(CKRH-FRV) td(CKXH-FXV) tdis(CKXH-DXHZ) td(CKXH-DXV) PARAMETER Delay time, CLKS high to CLKR/X high for internal CLKR/X generated from CLKS input Cycle time, CLKR/X Pulse duration, CLKR/X high or CLKR/X low Delay time, CLKR high to internal FSR valid Delay time, CLKX high to internal FSX valid time Disable time, DX high impedance following last data bit im edance from CLKX high Delay time CLKX high to DX valid time, Delay time, FSX high to DX valid 14 td(FXH-DXV) ONLY applies when in data delay 0 (XDATDLY = 00b) mode CLKR/X int CLKR/X int CLKR int CLKX int CLKX ext CLKX int CLKX ext CLKX int CLKX ext FSX int FSX ext MIN 4 4P C - 1# -11 -11 3 -9 3 -9+ D|| 3 + D|| -1 3 MAX 26 UNIT ns ns C + 1# 3 3 9 4 9 4 + D|| 19 + D|| 3 ns 9 ns ns ns ns ns
PRODUCT PREVIEW
CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted. Minimum delay times also represent minimum output hold times. P = 1/CPU clock frequency in ns. For example, when running parts at 100 MHz, use P = 10 ns. The maximum bit rate for McBSP-to-McBSP communications is 25 MHz; therefore, the minimum CLKR/X clock cycle is either four times the CPU cycle time (4P), or 40 ns (25 MHz), whichever value is larger. For example, when running parts at 100 MHz (P = 10 ns), use 40 ns as the minimum CLKR/X clock cycle (by setting the appropriate CLKGDV ratio or external clock source). The maximum bit rate for McBSP-to-McBSP communications applies to the following hardware configuration: the serial port is a master of the clock and frame syncs (with CLKR connected to CLKX, FSR connected to FSX, CLKXM = FSXM = 1, and CLKRM = FSRM = 0) in data delay 1 or 2 mode (R/XDATDLY = 01b or 10b) and the other device the McBSP communicates to is a slave. # C = H or L S = sample rate generator input clock = 2P if CLKSM = 1 (P = 1/CPU clock frequency) = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the 25 MHz limit. || Extra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR. D = extra delay from CLKX high to DX vaild = 0 if DXENA = 0 = extra delay from CLKX high to DX vaild = 2P if DXENA = 1
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TMS320C6712 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS148 - AUGUST 2000
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
CLKS 1 3 3 CLKR 4 FSR (int) 5 FSR (ext) 7 DR 2 3 CLKX 9 3 Bit(n-1) 8 (n-2) (n-3) 6 4 2
11 10 FSX (ext) FSX (XDATDLY=00b) 12 DX Bit 0 14 13 Bit(n-1) 13 (n-2) (n-3)
Figure 30. McBSP Timings
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PRODUCT PREVIEW
FSX (int)
TMS320C6712 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS148 - AUGUST 2000
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for FSR when GSYNC = 1 (see Figure 31)
-100 NO. NO 1 2 tsu(FRH-CKSH) th(CKSH-FRH) Setup time, FSR high before CLKS high Hold time, FSR high after CLKS high MIN 4 4 MAX UNIT ns ns
CLKS 1 FSR external CLKR/X (no need to resync) CLKR/X (needs resync) 2
Figure 31. FSR Timing When GSYNC = 1
PRODUCT PREVIEW
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TMS320C6712 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS148 - AUGUST 2000
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0 (see Figure 32)
-100 NO. 4 5 tsu(DRV-CKXL) th(CKXL-DRV) Setup time, DR valid before CLKX low Hold time, DR valid after CLKX low MASTER MIN 26 4 MAX SLAVE MIN 2 - 6P 6 + 12P MAX ns ns UNIT
P = 1/CPU clock frequency in ns. For example, when running parts at 100 MHz, use P = 10 ns. For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics over recommended operating conditions for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0 (see Figure 32)
-100 NO. 1 2 3 6 7 th(CKXL-FXL) td(FXL-CKXH) td(CKXH-DXV) tdis(CKXL-DXHZ) tdis(FXH-DXHZ) PARAMETER Hold time, FSX low after CLKX low Delay time, FSX low to CLKX high# Delay time, CLKX high to DX valid Disable time, DX high impedance following last data bit from CLKX low Disable time, DX high impedance following last data bit from FSX high MASTER MIN T-9 L-9 -9 L-9 MAX T+9 L+9 9 L+9 2P + 3 6P + 20 6P + 4 10P + 20 SLAVE MIN MAX ns ns ns ns UNIT ns
8 td(FXL-DXV) Delay time, FSX low to DX valid 4P + 2 8P + 20 ns P = 1/CPU clock frequency in ns. For example, when running parts at 100 MHz, use P = 10 ns. For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. S = Sample rate generator input clock = 2P if CLKSM = 1 (P = 1/CPU clock frequency) = Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP # FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX).
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TMS320C6712 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS148 - AUGUST 2000
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
CLKX 1 FSX 7 6 DX Bit 0 4 DR Bit 0 Bit(n-1) 8 3 Bit(n-1) 5 (n-2) (n-3) (n-4) (n-2) (n-3) (n-4) 2
Figure 32. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
PRODUCT PREVIEW
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TMS320C6712 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS148 - AUGUST 2000
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0 (see Figure 33)
-100 NO. 4 5 tsu(DRV-CKXH) th(CKXH-DRV) Setup time, DR valid before CLKX high Hold time, DR valid after CLKX high MASTER MIN 26 4 MAX SLAVE MIN 2 - 6P 6 + 12P MAX ns ns UNIT
P = 1/CPU clock frequency in ns. For example, when running parts at 100 MHz, use P = 10 ns. For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics over recommended operating conditions for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0 (see Figure 33)
-100 NO. 1 2 3 6 th(CKXL-FXL) td(FXL-CKXH) td(CKXL-DXV) tdis(CKXL-DXHZ) PARAMETER Hold time, FSX low after CLKX low Delay time, FSX low to CLKX high# Delay time, CLKX low to DX valid Disable time, DX high impedance following last data bit from CLKX low MASTER MIN L-9 T-9 -9 -9 MAX L+9 T+9 9 9 6P + 4 6P + 3 10P + 20 10P + 20 SLAVE MIN MAX ns ns ns UNIT ns
7 td(FXL-DXV) Delay time, FSX low to DX valid H-9 H+9 4P + 2 8P + 20 ns P = 1/CPU clock frequency in ns. For example, when running parts at 100 MHz, use P = 10 ns. For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. S = Sample rate generator input clock = 2P if CLKSM = 1 (P = 1/CPU clock frequency) = Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP # FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX).
CLKX 1 FSX 6 Bit 0 7 Bit(n-1) 4 DR Bit 0 Bit(n-1) 3 (n-2) 5 (n-2) (n-3) (n-4) (n-3) (n-4) 2
DX
Figure 33. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
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PRODUCT PREVIEW
TMS320C6712 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS148 - AUGUST 2000
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1 (see Figure 34)
-100 NO. 4 5 tsu(DRV-CKXH) th(CKXH-DRV) Setup time, DR valid before CLKX high Hold time, DR valid after CLKX high MASTER MIN 26 4 MAX SLAVE MIN 2 - 6P 6 + 12P MAX ns ns UNIT
P = 1/CPU clock frequency in ns. For example, when running parts at 100 MHz, use P = 10 ns. For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics over recommended operating conditions for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1 (see Figure 34)
-100 NO. 1 2 3 6 7 th(CKXH-FXL) td(FXL-CKXL) td(CKXL-DXV) tdis(CKXH-DXHZ) tdis(FXH-DXHZ) PARAMETER Hold time, FSX low after CLKX high Delay time, FSX low to CLKX low# Delay time, CLKX low to DX valid Disable time, DX high impedance following last data bit from CLKX high Disable time, DX high impedance following last data bit from FSX high MASTER MIN MAX T+9 H+9 9 H+9 2P + 3 6P + 20 6P + 4 10P + 20 T-9 H-9 -9 H-9 SLAVE MIN MAX ns ns ns ns ns UNIT
PRODUCT PREVIEW
8 td(FXL-DXV) Delay time, FSX low to DX valid 4P + 2 8P + 20 ns P = 1/CPU clock frequency in ns. For example, when running parts at 100 MHz, use P = 10 ns. For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. S = Sample rate generator input clock = 2P if CLKSM = 1 (P = 1/CPU clock frequency) = Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP # FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX).
52
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TMS320C6712 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS148 - AUGUST 2000
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
CLKX 1 FSX 7 6 DX Bit 0 4 DR Bit 0 Bit(n-1) 8 Bit(n-1) 5 (n-2) (n-3) (n-4) 3 (n-2) (n-3) (n-4) 2
Figure 34. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
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PRODUCT PREVIEW
TMS320C6712 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS148 - AUGUST 2000
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1 (see Figure 35)
-100 NO. 4 5 tsu(DRV-CKXH) th(CKXH-DRV) Setup time, DR valid before CLKX high Hold time, DR valid after CLKX high MASTER MIN 26 4 MAX SLAVE MIN 2 - 6P 6 + 12P MAX ns ns UNIT
P = 1/CPU clock frequency in ns. For example, when running parts at 100 MHz, use P = 10 ns. For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics over recommended operating conditions for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1 (see Figure 35)
-100 NO. 1 2 3 6 th(CKXH-FXL) td(FXL-CKXL) td(CKXH-DXV) tdis(CKXH-DXHZ) PARAMETER Hold time, FSX low after CLKX high Delay time, FSX low to CLKX low# Delay time, CLKX high to DX valid Disable time, DX high impedance following last data bit from CLKX high MASTER MIN MAX H+9 T+9 9 9 6P + 4 6P + 3 10P + 20 10P + 20 H-9 T-9 -9 -9 SLAVE MIN MAX ns ns ns ns UNIT
PRODUCT PREVIEW
7 td(FXL-DXV) Delay time, FSX low to DX valid L-9 L+9 4P + 2 8P + 20 ns P = 1/CPU clock frequency in ns. For example, when running parts at 100 MHz, use P = 10 ns. For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. S = Sample rate generator input clock = 2P if CLKSM = 1 (P = 1/CPU clock frequency) = Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP # FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX).
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TMS320C6712 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS148 - AUGUST 2000
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
CLKX 1 FSX 6 DX Bit 0 4 DR Bit 0 Bit(n-1) 7 Bit(n-1) 3 (n-2) 5 (n-2) (n-3) (n-4) (n-3) (n-4) 2
Figure 35. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
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PRODUCT PREVIEW
TMS320C6712 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS148 - AUGUST 2000
TIMER TIMING timing requirements for timer inputs (see Figure 36)
-100 NO. NO 1 tw(TINPH) tw(TINPL) Pulse duration, TINP high MIN 2P 2P MAX UNIT ns ns
2 Pulse duration, TINP low P = 1/CPU clock frequency in ns. For example, when running parts at 100 MHz, use P = 10 ns.
switching characteristics over recommended operating conditions for timer outputs (see Figure 36)
-100 NO. NO 3 4 tw(TOUTH) tw(TOUTL) Pulse duration, TOUT high Pulse duration, TOUT low PARAMETER MIN 4P-3 4P-3 MAX UNIT ns ns
P = 1/CPU clock frequency in ns. For example, when running parts at 100 MHz, use P = 10 ns.
PRODUCT PREVIEW
2 1 TINPx 3 TOUTx 4
Figure 36. Timer Timing
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TMS320C6712 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS148 - AUGUST 2000
JTAG TEST-PORT TIMING timing requirements for JTAG test port (see Figure 37)
-100 NO. NO 1 3 4 tc(TCK) tsu(TDIV-TCKH) th(TCKH-TDIV) Cycle time, TCK Setup time, TDI/TMS/TRST valid before TCK high Hold time, TDI/TMS/TRST valid after TCK high MIN 35 10 9 MAX UNIT ns ns ns
switching characteristics over recommended operating conditions for JTAG test port (see Figure 37)
-100 NO. NO 2 td(TCKL-TDOV) PARAMETER Delay time, TCK low to TDO valid MIN -3 MAX 18 UNIT ns
1 TCK 2 TDO 4 3 TDI/TMS/TRST 2
Figure 37. JTAG Test-Port Timing
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PRODUCT PREVIEW
TMS320C6712 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS148 - AUGUST 2000
MECHANICAL DATA
GFN (S-PBGA-N256)
27,20 SQ 26,80 24,70 SQ 23,95 Y W V U T R P N M L K J H G F E D C B A 1 2 2,32 MAX 3 4 5 6 7 8 9 10 11 13 15 17 19 12 14 16 18 20
PLASTIC BALL GRID ARRAY
24,13 TYP 1,27 0,635
PRODUCT PREVIEW
1,17 NOM
Seating Plane 0,40 0,30 0,90 0,60 0,15 M 0,15
0,70 0,50
4040185-2/B 11/97 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice.
thermal resistance characteristics (S-PBGA package)
NO 1 2 3 4 RJC RJA RJA RJA Junction-to-case Junction-to-free air Junction-to-free air Junction-to-free air C/W 6.4 25.2 23.1 21.9 20.6 Air Flow LFPM N/A 0 100 250 500
5 RJA Junction-to-free air LFPM = Linear Feet Per Minute
58
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0,635
1,27
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Copyright (c) 2000, Texas Instruments Incorporated

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