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TMS370 Microcontroller Family User's Guide
Literature Number: SPNU127A Manufacturing Part Number: 1604927-9761 revision C February 1997
Printed on Recycled Paper
Chapter Title--Attribute Reference
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IMPORTANT NOTICE Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current. TI warrants performance of its semiconductor products and related software to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage ("Critical Applications"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. Inclusion of TI products in such applications is understood to be fully at the risk of the customer. Use of TI products in such applications requires the written approval of an appropriate TI officer. Questions concerning potential risk applications should be directed to TI through a local SC sales office. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards should be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. Nor does TI warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used.
Copyright (c) 1997, Texas Instruments Incorporated
Preface
Read This First
About This Manual
This user's guide describes the TMS370 family of microcontroller devices. These devices have robust features that enhance performance and enable new application technologies. The specifications and descriptions included in this user's guide apply to the TMS370CxxxA devices; all differences for the TMS370Cxxx devices are described in Appendix A. The objective of this user's guide is to provide the information you need to implement a microcontroller design using a TMS370 device. The user's guide contains the following chapters: Chapter 1 Introduction to the TMS370 Family Devices. Discusses the key features and the major components of the TMS370 family devices. Also includes block diagrams for each device category. TMS370 Family Pinouts and Pin Descriptions. Provides pinouts and pin descriptions for the TMS370 family device categories.
Chapter 2
Chapters 3-15 Describe the operation and programming of each major function in the TMS370 architecture. Chapter 16 Assembly Language Instruction Set. Describes the TMS370 addressing modes and each of the 73 instructions, including samples and examples. Development Support. Describes the hardware and software development tools available for the TMS370 devices.
Chapter 17
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About This Manual
Chapter 18
Electrical Specifications and Timings. Gives timing diagrams and electrical specifications for each of the device categories. Customer Information. Describes mask-ROM prototyping, TMS370 physical characteristics, and parts ordering. Differences Among the TMS370CxxxA, TMS370CxxxB, and TMS370Cxxx Devices (Contact Options). Points out the differences between the TMS370CxxxA and TMS370CxxxB devices as described in this manual and the TMS370Cxxx devices. Peripheral File Memory Map. Gives reference tables for the TMS370 control bits and registers. Block Diagrams. Gives reference block diagrams of the major circuits. ASCII Character Set. Lists the ASCII character set that the TMS370 assembler recognizes. Opcode/Instruction Cross-Reference. Gives an opcode-to-instruction cross-reference of all 73 mnemonics and 274 opcodes of the TMS370 instruction set. Instruction/Opcode Cross-Reference and Bus Activity Table. Gives an instruction-to-opcode cross-reference of all 73 mnemonics and 274 opcodes of the TMS370 instruction set and provides a cycle-by-cycle bus activity table. Device Pinouts. Provides pinouts for the individual device categories. PLCC-to-PGA Pinouts. Shows the pinouts for the standard PLCC-to-PGA sockets that are commonly used in prototype and production applications. You can use these pinouts when you wirewrap your breadboard with a socket. PACT.H. Gives PACT.H macros used with PACT example programs. Glossary. Defines acronyms and key terms used in this book.
Chapter 19
Appendix A
Appendix B
Appendix C Appendix D
Appendix E
Appendix F
Appendix G Appendix H
Appendix I Appendix J
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Style and Symbol Conventions
Style and Symbol Conventions
This document uses the following conventions.
Symbol or Term (xxxxxx.n) Example SPICTL.4 Description Bit location convention used in text and figures, where 'xxxxxx' is the name of the register (e.g., SPICTL) containing the bit and 'n' is the bit number (7 = MSB, 0 = LSB). Designates a number in the hexadecimal number system. Hexadecimal Peripheral File (PF) address used in instructions accessing the PF. (i.e., P012 = P18) Decimal Peripheral File (PF) address used in instructions accessing the PF. (i.e., P18 = P012). Hexadecimal Register File (RF) address used in instructions accessing the RF. (i.e., R010 = R16) Decimal Register File (RF) address used in instructions accessing the RF. (i.e., R16 = R010) When used in reference to bits, means to write a logic 1 to the bit. When used in reference to bits, means to write a logic 0 to the bit. Most significant byte Most significant bit Least significant byte Least significant bit bits per second
h P0n Pn R0n Rn set clear MSbyte MSB LSbyte LSB bps
1ABCh P012 P18 R010 R16
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Program listings, program examples, interactive displays, filenames, and symbol names are shown in a special typeface similar to a typewriter's. Here is a sample program listing:
LABEL SUB R19,B ;(B) minus (R19) is ;stored in B ;(A) minus 076h is stored ;in A ;(R9) minus (R4) is stored ;in R9
SUB #076h,A
SUB R4,R9
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Style and Symbol Conventions / Information About Cautions and Warnings
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In syntax descriptions, the instruction, command, or directive is in a bold typeface font, and parameters are in an italic typeface. Portions of a syntax that are in bold should be entered as shown; portions of a syntax that are in italics describe the type of information that should be entered. Here is an example of a directive syntax: MOV s,d MOV is the instruction. This instruction has two parameters, indicated by s and d.
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Braces ( { and } ) indicate a list. The symbol | (read as or ) separates items within the list. Here's an example of a command that has a list: TST {A| B} This provides two choices: TST A or TST B. Unless the list is enclosed in square brackets, you must choose one item from the list.
Information About Cautions and Warnings
This book may contain cautions and warnings.
This is an example of a caution statement. A caution statement describes a situation that could potentially damage your software or equipment.
This is an example of a warning statement. A warning statement describes a situation that could potentially cause harm to you.
The information in a caution or a warning is provided for your protection; please read each carefully.
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Related Documentation From Texas Instruments
Related Documentation From Texas Instruments
The following books describe the TMS370 family devices and related support tools. To obtain a copy of any of these TI documents, call the Texas Instruments Literature Response Center at (800) 477-8924. When ordering, please identify the book by its title and literature number.
TMS370 Microcontroller Family Applications Book (literature number SPNA017) provides examples of hardware setups and accompanying software routines for various applications of the TMS370 microcontroller. TMS370Cxxx 8-Bit Microcontrollers Data Sheets describe the features of the device and provide pinouts, electrical specifications, and timings for the following microprocessors: - TMS370Cx0x (literature number SPNS029) - TMS370Cx1x (literature number SPNS012) - TMS370Cx2x (literature number SPNS018) - TMS370Cx32 (literature number SPNS015) - TMS370Cx36 (literature number SPNS039) - TMS370Cx4x (literature number SPNS016) - TMS370Cx5x (literature number SPNS010) - TMS370Cx6x (literature number SPNS033) - TMS370Cx7x (literature number SPNS034) - TMS370Cx8x (literature number SPNS035) - TMS370Cx9x (literature number SPNS036) - TMS370CxAx (literature number SPNS037) - TMS370CxBx (literature number SPNS038) - TMS370CxCx (literature number SPNS040) TMS370 8-Bit Microcontrollers Data Book (literature number SPND003) is a collection of the TMS370Cxxx microcontroller data sheets into a single book with additional chapters that discuss ordering information, an overview of development tools, a selection guide with a cross-reference of device functions, and quality and reliability. TMS370 and TMS370C8 8-Bit Microcontroller Family Assembly Language Tools User's Guide (literature number SPNU010) describes the assembly language tools (assembler, linker, and other tools used to develop assembly code), assembler directives, macros, common object file format, and symbolic debugging directives for the TMS370/C8 8-bit family of devices. TMS370 and TMS370C8 8-Bit Microcontroller Family Optimizing C Compiler User's Guide (literature number SPNU022) describes the TMS370/C8 8-bit C compiler. This C compiler accepts ANSI standard C source code and produces assembly language source code for the TMS370/C8 8-bit family of devices.
Read This First
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Related Documentation From Texas Instruments / Trademarks
TMS370 Family C Source Debugger User's Guide (literature number SPNU028) tells you how to invoke the '370 XDS/22 emulator and application board versions of the C source debugger interface. This book discusses various aspects of the debugger interface, including window management, command entry, code execution, data management, and breakpoints, and includes a tutorial that introduces basic debugger functionality. It also includes an advanced tutorial that introduces the breakpoint, trace, and timing features.
Trademarks
CROSSTALK is a trademark of Microstuf, Inc. HP700 is a trademark of Hewlett-Packard Company. Kermit is a registered trademark of Columbia University. MS-DOS is a registered trademark of Microsoft Corp. PC-DOS is a trademark of International Business Machines Corp. PROCOMM is a registered trademark of Datastorm Technologies Inc. UNIX is a registered trademark of Unix System Laboratories, Inc. VAX and VMS are trademarks of Digital Equipment Corp. XDS is a trademark of Texas Instruments Incorporated.
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If You Need Assistance
If You Need Assistance. . .
If you want to. . . Request more information about Texas Instruments microcontroller products Do this. . . Write to: Texas Instruments Incorporated Market Communications Manager, MS 736 P.O. Box 1443 Houston, Texas 77251-1443 Call the TI Literature Response Center: (800) 477-8924 Call the Microcontroller Hotline: (713) 274-2370 FAX: (713) 274-4203 Web address: http://www.ti.com/sc/micro Product Information Center: (214) 644-5580 Report mistakes in this document or any other TI documentation Send your comments to: Texas Instruments Incorporated Technical Publications Manager, MS 702 P.O. Box 1443 Houston, Texas 77251-1443
Order Texas Instruments documentation Ask questions about product operation or report suspected problems Product information
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Contents
Contents
1 Introduction to the TMS370 Family Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Discusses the key features and the major components of the TMS370 family devices. Also includes block diagrams for each device category 1.1 1.2 1.3 1.4 1.5 1.6 1.7 2 Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Available Development Support Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 Device Families . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 Key Features of the TMS370 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Major Components of the TMS370 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 Summary of Components by Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 Device Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21
TMS370 Family Pinouts and Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Provides pinouts and pin descriptions for the TMS370 family device categories 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 2.14 TMS370Cx0x Pinouts and Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 TMS370Cx1x Pinouts and Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 TMS370Cx2x Pinouts and Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 TMS370Cx32 Pinouts and Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 TMS370Cx36 Pinout and Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 TMS370Cx4x Pinouts and Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 TMS370Cx5x Pinouts and Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 TMS370Cx6x Pinouts and Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 TMS370Cx7x Pinouts and Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24 TMS370Cx8x Pinouts and Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27 TMS370Cx9x Pinouts and Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30 TMS370CxAx Pinouts and Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-33 TMS370CxBx Pinouts and Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-35 TMS370CxCx Pinouts and Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-38
3
CPU and Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 The TMS370 has a register-to-register architecture. This chapter describes the CPU registers and memory organization. 3.1 3.2 CPU/Register File Interaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1 Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.2 Status Register (ST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.3 Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3-4 3-4 3-5 3-7
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3.3
3.4
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.3.1 Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.3.2 Peripheral File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 3.3.3 Data EEPROM Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 3.3.4 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 Memory Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 3.4.1 Microcomputer Single-Chip Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 3.4.2 Microcomputer Mode With External Expansion (All Devices With Memory Expansion and Internal Program Memory) . . . . . . . . . . . . . . . . . . 3-19 3.4.3 Microprocessor Mode Without Internal Memory (Memory Expansion Devices Only) 3-24 3.4.4 Microprocessor Mode With Internal Program Memory (Memory Expansion Devices Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26 3.4.5 Memory Mode Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28
4
System and Digital I/O Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Discusses the system and I/O configuration. Features and options are described, as well as the registers that control the configuration 4.1 System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.1.1 Privilege Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.1.2 Clock Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.1.3 Oscillator Fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.1.4 Automatic Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 Low-Power and Idle Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 4.2.1 Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 4.2.2 Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 4.2.3 Using Interrupts to Exit From the Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . 4-10 4.2.4 Oscillator Power Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 System Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13 4.3.1 System Control and Configuration Register 0 (SCCR0) . . . . . . . . . . . . . . 4-13 4.3.2 System Control and Configuration Register 1 (SCCR1) . . . . . . . . . . . . . . 4-15 4.3.3 System Control and Configuration Register 2 (SCCR2) . . . . . . . . . . . . . . 4-16 Digital I/O Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18 4.4.1 Configuration Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-27 4.4.2 Microprocessor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-29 4.4.3 Microcomputer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-29
4.2
4.3
4.4
5
Interrupts and System Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 Discusses the internal and external interrupts of the TMS370. The methods of device reset are also discussed. 5.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.1.1 Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5.1.2 External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
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5.2
5.3 5.4
Interrupt Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.1 Interrupt 1 Control Register (INT1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.2 Interrupt 2 Control Register (INT2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.3 Interrupt 3 Control Register (INT3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multiple Interrupt Servicing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.1 Simple Reset Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.2 Reset Circuitry With Low-Voltage Detection . . . . . . . . . . . . . . . . . . . . . . . .
5-12 5-12 5-14 5-16 5-18 5-19 5-20 5-22
6
EPROM and EEPROM Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 Discusses the architecture and programming of the data EEPROM modules of the TMS370 family and the program EPROM module of the TMS370C6xx and TMS370C7xx devices 6.1 6.2 Data EEPROM Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 Data EEPROM Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 6.2.1 Write Protection Register (WPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 6.2.2 Data EEPROM Control Register (DEECTL) . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 Programming the Data EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6 Program EPROM Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10 6.4.1 Erasing the EPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11 6.4.2 Program EPROM Control Register (EPCTLx) . . . . . . . . . . . . . . . . . . . . . . . 6-12 6.4.3 Programming the Program EPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13 6.4.4 Write Protection of the Program EPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15
6.3 6.4
7
Timer 1 (T1) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 Discusses the architecture and programming of the timer 1 module 7.1 T1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 7.1.1 Physical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 7.1.2 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 7.1.3 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 General-Purpose Timer Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 7.2.1 16-Bit Resettable Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 7.2.2 Compare Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 7.2.3 Capture/Compare Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8 Operating Modes of the General-Purpose Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10 7.3.1 Dual Compare Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10 7.3.2 Capture/Compare Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13 Edge-Detection Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-15 7.4.1 Dual Compare Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-15 7.4.2 Capture/Compare Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-15 Clock Prescaler/External Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16 7.5.1 Event Counter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-18 7.5.2 Pulse Accumulator Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-18 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-20
Contents
xiii
7.2
7.3
7.4
7.5
7.6
Contents
7.7
7.8
7.9
WD Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.7.1 Standard WD Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.7.2 Hard WD Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.7.3 Simple Counter Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.7.4 Summary of WD Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.8.1 Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.8.2 Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T1 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.9.1 T1 Control Register 1 (T1CTL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.9.2 T1 Control Register 2 (T1CTL2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.9.3 T1 Control Register 3 (T1CTL3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.9.4 T1 Control Register 4 (T1CTL4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.9.5 T1 Port Control Registers (T1PC1 and T1PC2) . . . . . . . . . . . . . . . . . . . . . 7.9.6 T1 Interrupt Priority Control Register (T1PRI) . . . . . . . . . . . . . . . . . . . . . . .
7-21 7-23 7-25 7-27 7-28 7-29 7-29 7-29 7-30 7-32 7-34 7-36 7-38 7-40 7-43
8
Timer 2A (T2A) and Timer 2B (T2B) Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 Discusses the architecture and programming of the timer 2 module 8.1 T2n Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 8.1.1 Physical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 8.1.2 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 8.1.3 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 T2n Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6 8.2.1 16-Bit Resettable Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6 8.2.2 Compare Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6 8.2.3 Capture Register (Dual Capture Mode Only) . . . . . . . . . . . . . . . . . . . . . . . . . 8-7 8.2.4 Capture/Compare Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10 8.3.1 Dual Compare Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10 8.3.2 Dual Capture Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11 Edge-Detection Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-13 8.4.1 Dual Compare Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-13 8.4.2 Dual Capture Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-13 Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-14 8.5.1 Event Counter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15 8.5.2 Pulse Accumulator Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-16 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-17 T2n Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-17 8.8.1 T2n Control Register 1 (T2nCTL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-19 8.8.2 T2n Control Register 2 (T2nCTL2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-20 8.8.3 T2n Control Register 3 (T2nCTL3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-23 8.8.4 T2n Port Control Registers (T2nPC1 and T2nPC2) . . . . . . . . . . . . . . . . . . 8-26 8.8.5 T2n Interrupt Priority Control Register (T2nPRI) . . . . . . . . . . . . . . . . . . . . . 8-29
8.2
8.3
8.4
8.5
8.6 8.7 8.8
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9
Serial Communications Interface 1 (SCI1) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 Discusses the architecture and programming of serial communication interface SCI1 9.1 SCI1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 9.1.1 Physical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 9.1.2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5 9.1.3 Communications Modes and Multiprocessing Modes . . . . . . . . . . . . . . . . . 9-5 9.1.4 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6 SCI1 Programmable Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7 Multiprocessor Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8 9.3.1 Idle Line Multiprocessor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9 9.3.2 Address Bit Multiprocessor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10 Communications Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12 9.4.1 Asynchronous Communications Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12 9.4.2 Isosynchronous Communications Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13 9.4.3 Receiver Signals in Communications Modes . . . . . . . . . . . . . . . . . . . . . . . 9-13 9.4.4 Transmitter Signals in Communications Modes . . . . . . . . . . . . . . . . . . . . . 9-14 Port Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15 Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-16 Initialization Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-18 9.7.1 RS-232-C Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-18 9.7.2 RS-232-C Multiprocessor Mode Example . . . . . . . . . . . . . . . . . . . . . . . . . . 9-19 SCI1 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-21 9.8.1 SCI Communication Control Register (SCICCR) . . . . . . . . . . . . . . . . . . . . 9-22 9.8.2 SCI Control Register (SCICTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-24 9.8.3 Baud Select Registers (BAUD MSB and BAUD LSB) . . . . . . . . . . . . . . . . 9-27 9.8.4 SCI Transmitter Interrupt Control and Status Register (TXCTL) . . . . . . . 9-28 9.8.5 SCI Receiver Interrupt Control and Status Register (RXCTL) . . . . . . . . . 9-29 9.8.6 SCI Receiver Data Buffer Register (RXBUF) . . . . . . . . . . . . . . . . . . . . . . . 9-31 9.8.7 SCI Transmitter Data Buffer Register (TXBUF) . . . . . . . . . . . . . . . . . . . . . . 9-31 9.8.8 SCI Port Control Register 1 (SCIPC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-32 9.8.9 SCI Port Control Register 2 (SCIPC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-33 9.8.10 SCI Priority Control Register (SCIPRI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-35
9.2 9.3
9.4
9.5 9.6 9.7
9.8
10 Serial Communications Interface 2 (SCI2) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 Discusses the architecture and programming of serial communication interface SCI2 10.1 SCI2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.1 Physical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.3 Communications Modes and Multiprocessing Modes . . . . . . . . . . . . . . . . 10.1.4 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmable Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multiprocessor Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3.1 Idle Line Multiprocessor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3.2 Address Bit Multiprocessor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents
10.2 10.3
10-2 10-2 10-3 10-4 10-4 10-6 10-7 10-8 10-9
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10.4
10.5 10.6 10.7
10.8
Asynchronous Communications Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4.1 Receiver Signals in the Communication Mode . . . . . . . . . . . . . . . . . . . . . 10.4.2 Transmitter Signals in the Communication Mode . . . . . . . . . . . . . . . . . . . Port Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Initialization Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.7.1 RS-232-C Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.7.2 RS-232-C Multiprocessor Mode Example . . . . . . . . . . . . . . . . . . . . . . . . . SCI2 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.8.1 SCI Communication Control Register (SCICCR) . . . . . . . . . . . . . . . . . . . 10.8.2 SCI Control Register (SCICTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.8.3 Baud Select Registers (BAUD MSB and BAUD LSB) . . . . . . . . . . . . . . . 10.8.4 SCI Transmitter Interrupt Control and Status Register (TXCTL) . . . . . . 10.8.5 SCI Receiver Interrupt Control and Status Register (RXCTL) . . . . . . . . 10.8.6 SCI Receiver Data Buffer Register (RXBUF) . . . . . . . . . . . . . . . . . . . . . . 10.8.7 SCI Transmitter Data Buffer Register (TXBUF) . . . . . . . . . . . . . . . . . . . . . 10.8.8 SCI Port Control Register 2 (SCIPC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.8.9 SCI Priority Control Register (SCIPRI) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-10 10-10 10-10 10-12 10-13 10-14 10-14 10-15 10-17 10-18 10-20 10-22 10-23 10-24 10-26 10-26 10-27 10-29
11 Serial Peripheral Interface (SPI) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 Discusses the architecture and programming of the serial peripheral interface 11.1 SPI Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 11.1.1 Physical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 11.1.2 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4 11.2 Communications Between the Master and the Slave . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 11.3 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6 11.3.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6 11.3.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6 11.4 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8 11.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9 11.6 Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10 11.7 Initialization Upon Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11 11.8 SPI Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12 11.9 SPI Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13 11.9.1 SPI Configuration Control Register (SPICCR) . . . . . . . . . . . . . . . . . . . . . 11-14 11.9.2 SPI Operation Control Register (SPICTL) . . . . . . . . . . . . . . . . . . . . . . . . . 11-16 11.9.3 Serial Input Buffer (SPIBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-18 11.9.4 Serial Data Register (SPIDAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-18 11.9.5 SPI Port Control Registers (SPIPC1 and SPIPC2) . . . . . . . . . . . . . . . . . . 11-19 11.9.6 SPI Interrupt Priority Control Register (SPIPRI) . . . . . . . . . . . . . . . . . . . . 11-22 12 Analog-To-Digital Converter 1 (ADC1) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Discusses the architecture and programming of the ADC1 12.1 Analog-to-Digital Converter 1 (ADC1) Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1.1 Physical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1.2 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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12-1 12-2 12-2 12-4
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12.2
12.3 12.4
ADC1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5 12.2.1 Input/Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5 12.2.2 Sampling Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6 12.2.3 ADC1 Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6 12.2.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7 12.2.5 Programming Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8 ADC1 Example Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9 ADC1 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-11 12.4.1 Analog Control Register (ADCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12 12.4.2 Analog Status and Interrupt Register (ADSTAT) . . . . . . . . . . . . . . . . . . . . 12-14 12.4.3 Analog Conversion Data Register (ADDATA) . . . . . . . . . . . . . . . . . . . . . . 12-15 12.4.4 Analog Port E Data Input Register (ADIN) . . . . . . . . . . . . . . . . . . . . . . . . . 12-15 12.4.5 Analog Port E Input Enable Register (ADENA) . . . . . . . . . . . . . . . . . . . . . 12-16 12.4.6 Analog Interrupt Priority Register (ADPRI) . . . . . . . . . . . . . . . . . . . . . . . . . 12-17
13 Analog-To-Digital Converter 2 (ADC2) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 Discusses the architecture and programming of the ADC2 13.1 Analog-to-Digital Converter 2 (ADC2) Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2 13.1.1 Physical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2 13.1.2 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4 13.2 ADC2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5 13.2.1 Input/Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5 13.2.2 Sampling Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5 13.2.3 ADC2 Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5 13.2.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6 13.2.5 Programming Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7 13.3 ADC2 Example Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8 13.4 ADC2 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-10 13.4.1 Analog Control Register (ADCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-11 13.4.2 Analog Status and Interrupt Register (ADSTAT) . . . . . . . . . . . . . . . . . . . . 13-13 13.4.3 Analog Conversion Data Register (ADDATA) . . . . . . . . . . . . . . . . . . . . . . 13-13 13.4.4 Analog Port E Data Input Register (ADIN) . . . . . . . . . . . . . . . . . . . . . . . . . 13-14 13.4.5 Analog Port E Input Enable Register (ADENA) . . . . . . . . . . . . . . . . . . . . . 13-14 13.4.6 Analog Interrupt Priority Register (ADPRI) . . . . . . . . . . . . . . . . . . . . . . . . . 13-15 14 Analog-To-Digital Converter 3 (ADC3) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Discusses the architecture and programming of the ADC3 14.1 Analog-to-Digital Converter 3 (ADC3) Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.1.1 Physical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.1.2 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2 ADC3 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.1 Input/Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.2 Sampling Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.3 ADC3 Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.5 Programming Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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14-1 14-2 14-2 14-4 14-5 14-5 14-5 14-6 14-7 14-8
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14.3 14.4
ADC3 Example Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-9 ADC3 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-11 14.4.1 Analog Control Register (ADCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-12 14.4.2 Analog Status and Interrupt Register (ADSTAT) . . . . . . . . . . . . . . . . . . . . 14-14 14.4.3 Analog Conversion Data Register (ADDATA) . . . . . . . . . . . . . . . . . . . . . . 14-15 14.4.4 Analog Port E Data Input Register (ADIN) . . . . . . . . . . . . . . . . . . . . . . . . . 14-15 14.4.5 Analog Port E Input Enable Register (ADENA) . . . . . . . . . . . . . . . . . . . . . 14-16 14.4.6 Analog Interrupt Priority Register (ADPRI) . . . . . . . . . . . . . . . . . . . . . . . . . 14-16
15 Programmable Acquisition and Control Timer (PACT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 Discusses the architecture and programming of the programmable acquisition and control timer (PACT) module. Even if you have extensive experience with microcontroller timers, you should read this chapter to fully understand how to use the TMS370 PACT module. 15.1 PACT Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2 15.1.1 Physical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2 15.1.2 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4 PACT Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5 15.2.1 Hardware Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5 15.2.2 Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5 15.2.3 Time Base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7 15.2.4 Command/Definition File Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7 15.2.5 Available Time Slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7 Dual-Port RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-9 Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-12 Control and Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-15 15.5.1 Standard Compare Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-16 15.5.2 Virtual Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-17 15.5.3 Double Event Compare Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-18 15.5.4 Offset Timer Definition--Time From the Last Event . . . . . . . . . . . . . . . . . 15-19 15.5.5 Conditional Compare Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-20 15.5.6 Baud Rate Timer Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-20 Command/Definition Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-21 15.6.1 Virtual Timer Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-22 15.6.2 Offset Timer Definition--Time From Last Event . . . . . . . . . . . . . . . . . . . . 15-23 15.6.3 Baud Rate Timer Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-24 15.6.4 Standard Compare Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-25 15.6.5 Double Event Compare Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-26 15.6.6 Conditional Compare Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-28 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-29 WD Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-31 Mini-Serial Communications Interface (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-32 PWM Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-33 15.10.1 Defining the Command/Definition Area . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-33 15.10.2 Copying the Command/Definition Area to Dual-Port RAM . . . . . . . . . . . 15-34 15.10.3 Initializing the PACT Peripheral Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-35
15.2
15.3 15.4 15.5
15.6
15.7 15.8 15.9 15.10
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15.11
PACT Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.11.1 Setup Control Register (PACTSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.11.2 Command/Definition Area Start Register (CDSTART) . . . . . . . . . . . . . . . 15.11.3 Command/Definition Area End Register (CDEND) . . . . . . . . . . . . . . . . . . 15.11.4 Buffer Pointer Register (BUFPTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.11.5 PACT-SCI Control Register (SCICTLP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.11.6 PACT-SCI RX Data Register (RXBUFP) . . . . . . . . . . . . . . . . . . . . . . . . . . 15.11.7 PACT-SCI TX Data Register (TXBUFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.11.8 Output Pins 1-8 State Register (OPSTATE) . . . . . . . . . . . . . . . . . . . . . . . 15.11.9 Command/Definition Entry Flags Register (CDFLAGS) . . . . . . . . . . . . . 15.11.10 Setup CP Control Register 1 (CPCTL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.11.11 Setup CP Control Register 2 (CPCTL2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.11.12 Setup CP Control Register 3 (CPCTL3) . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.11.13 CP Input Control Register (CPPRE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.11.14 Global Function Control Register (PACTPRI) . . . . . . . . . . . . . . . . . . . . . .
15-36 15-38 15-40 15-42 15-44 15-46 15-48 15-48 15-49 15-50 15-51 15-53 15-55 15-57 15-59
16 Assembly Language Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1 Summarizes the TMS370 family assembly language instruction set and provides individual instruction descriptions 16.1 16.2 16.3 Instruction Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2 Symbol Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4 16.3.1 Data Manipulation Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5 16.3.2 Program Flow Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-15 16.3.3 Additional Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-22 16.3.4 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-22 Instruction Set Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-23 Instruction Set Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-32
16.4 16.5
17 Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1 Discusses the key features of the TMS370 development tools. These tools are currently available for PC-DOS or MS-DOS systems. 17.1 17.2 17.3 17.4 TMS370 Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2 The Assembler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4 The Linker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-5 Additional Software Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-7 17.4.1 The Archiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-7 17.4.2 The Hex Conversion Utility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-7 The Optimizing C Compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-8 The C Source Debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-9 The XDS/22 System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-12 17.7.1 Breakpoint, Trace, and Timing (BTT) Functions . . . . . . . . . . . . . . . . . . . . 17-13 17.7.2 XDS System Configuration Requirements . . . . . . . . . . . . . . . . . . . . . . . . . 17-16 17.7.3 XDS System Operating Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-17 17.7.4 XDS Target Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-17
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17.5 17.6 17.7
Contents
17.8
17.9 17.10 17.11 17.12
The CDT370 (Compact Development Tool) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.8.1 The CDT370 PACT (Compact Development Tool PACT) . . . . . . . . . . . . 17.8.2 The CDT370 Timer (Compact Development Tool Timer) . . . . . . . . . . . . The Design Kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Starter Kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Microcontroller Programmer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reprogrammable EPROM and OTP Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17-18 17-19 17-19 17-20 17-24 17-25 17-26
18 Electrical Specifications and Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1 Contains electrical and timing information for the TMS370 family devices 18.1 18.2 18.3 18.4 18.5 18.6 18.7 Timing Parameter Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2 Parameter Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2 Absolute Maximum Ratings for All TMS370 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3 External Crystal/Clock Connections and Typical Circuits for Loads and Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-4 General-Purpose Output Signal Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-6 EPROM/EEPROM Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-7 TMS370Cx0xA and TMS370Cx0x Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-8 18.7.1 TMS370Cx0xA and TMS370Cx0x Electrical Specifications . . . . . . . . . . . 18-8 18.7.2 TMS370Cx0xA and TMS370Cx0x Timings . . . . . . . . . . . . . . . . . . . . . . . . 18-10 TMS370Cx1xA and TMS370Cx1xB Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-12 18.8.1 TMS370Cx1xA and TMS370Cx1xB Electrical Specifications . . . . . . . . . 18-12 18.8.2 TMS370Cx1xA and TMS370Cx1xB Timings . . . . . . . . . . . . . . . . . . . . . . . 18-14 TMS370Cx2xA and TMS370Cx2x Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-16 18.9.1 TMS370Cx2xA and TMS370Cx2x Electrical Specifications . . . . . . . . . . 18-16 18.9.2 TMS370Cx2xA and TMS370Cx2x Timings . . . . . . . . . . . . . . . . . . . . . . . . 18-18 TMS370Cx32A Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-20 18.10.1 TMS370Cx32A Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 18-20 18.10.2 TMS370Cx32A Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-22 TMS370Cx36A Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-24 18.11.1 TMS370Cx36A Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 18-24 18.11.2 TMS370Cx36A Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-27 TMS370Cx4xA Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-29 18.12.1 TMS370Cx4xA Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-29 18.12.2 TMS370Cx4xA Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-32 TMS370Cx5xA and TMS370Cx5xB Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-34 18.13.1 TMS370Cx5xA and TMS370Cx5xB Electrical Specifications . . . . . . . . . 18-34 18.13.2 TMS370Cx5xA and TMS370Cx5xB Timings . . . . . . . . . . . . . . . . . . . . . . . 18-38 TMS370Cx6xA Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-43 18.14.1 TMS370Cx6xA Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-43 18.14.2 TMS370Cx6xA Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-46 TMS370Cx7xA Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-51 18.15.1 TMS370Cx7xA Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-51 18.15.2 TMS370Cx7xA Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-54
18.8
18.9
18.10
18.11
18.12
18.13
18.14
18.15
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18.16
18.17
18.18
18.19
18.20
18.21 18.22 18.23 18.24 18.25
TMS370Cx8xA Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.16.1 TMS370Cx8xA Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.16.2 TMS370Cx8xA Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TMS370Cx9xA Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.17.1 TMS370Cx9xA Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.17.2 TMS370Cx9xA Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TMS370CxAxA Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.18.1 TMS370CxAxA Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 18.18.2 TMS370CxAxA Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TMS370CxBxA Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.19.1 TMS370CxBxA Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 18.19.2 TMS370CxBxA Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TMS370CxCxA Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.20.1 TMS370CxCxA Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 18.20.2 TMS370CxCxA Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCI Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog-to-Digital Converter 1 (ADC1) Module Specifications . . . . . . . . . . . . . . . . . . Analog-to-Digital Converter 2 (ADC2) Module Specifications . . . . . . . . . . . . . . . . . . Analog-to-Digital Converter 3 (ADC3) Module Specifications . . . . . . . . . . . . . . . . . .
18-57 18-57 18-59 18-62 18-62 18-65 18-68 18-68 18-70 18-73 18-73 18-76 18-79 18-79 18-81 18-84 18-86 18-89 18-92 18-94
19 Customer Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1 Describes mask-ROM prototyping, TMS370 physical characteristics, and parts ordering 19.1 Mask-ROM Prototype and Production Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2 19.2 Mechanical Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-6 19.3 TMS370 Family Numbering and Symbol Conventions . . . . . . . . . . . . . . . . . . . . . . . . 19-16 19.3.1 Production Device Prefix Designators . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-16 19.3.2 Support Device Prefix Designators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-17 19.3.3 Device Numbering Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-17 19.3.4 Device Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-17 19.3.5 Symbolization by Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-20 19.4 Ordering Information for Development Support Tools . . . . . . . . . . . . . . . . . . . . . . . . . 19-25 19.4.1 TMS370 Macro Assembler, Linker, C Compiler, and Utilities . . . . . . . . . 19-25 19.4.2 TMS370 Design Kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-25 19.4.3 TMS370 Starter Kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-25 19.4.4 TMS370 Microcontroller Programmer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-26 19.4.5 TMS370 XDS Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-26 19.4.6 TMS370 Compact Development Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-26 19.4.7 TMS370 Converter Socket . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-27 19.4.8 XDS Target Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-27 A Differences Among the TMS370CxxxA, TMS370C7xxB, and TMS370Cxxx Devices (Contact Options) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 Describes the differences found in comparing the different devices identified by the suffixes A, B, and no suffix. A.1 Watchdog (WD) Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2 A.2 Clock Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-3 A.3 Low-Power and Idle Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-4 A.4 Timer 1 Control Register 2 (T1CTL2) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-5
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A.5 A.6 A.7 A.8 A.9
A.10 B
System Control and Configuration Register 2 (SCCR2) Bits . . . . . . . . . . . . . . . . . . . . . A-5 AP Bit in the DEECTL Register (DEECTL.2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-6 Program EPROM Control Register (EPCTLx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-7 VCC1 and VCC2 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-7 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-8 A.9.1 Differences for TMS370Cx5x Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-8 A.9.2 Differences in SCI1 and SPI Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . A-9 A.9.3 Differences in EPROM Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-10 Summary of Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-11
Peripheral File Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1 Summarizes the peripheral file and control bit information B.1 Read/Write Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2 B.2 Peripheral File Frame 1: System Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . B-3 B.3 Peripheral File Frame 2: Digital Port Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . B-4 B.4 Peripheral File Frame 3: SPI Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-5 B.5 Peripheral File Frame 4: Timer 1 (T1) Control Registers . . . . . . . . . . . . . . . . . . . . . . . . B-6 B.6 Peripheral File Frame 4: PACT Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-7 B.7 Peripheral File Frame 5: SCI1 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-8 B.8 Peripheral File Frame 5: SCI2 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-9 B.9 Peripheral File Frame 6: Timer 2A (T2A) Control Registers . . . . . . . . . . . . . . . . . . . . . B-10 B.10 Peripheral File Frame 7: ADC1 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-11 B.11 Peripheral File Frame 7: ADC2 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-12 B.12 Peripheral File Frame 7: ADC3 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-13 B.13 Peripheral File Frame 8: Timer 2B (T2B) Control Registers . . . . . . . . . . . . . . . . . . . . . B-14 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1 Summarizes the block diagrams of the major circuits C.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-2 C.2 Timer 1 (T1) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-4 C.3 Timer 2n (T2n) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-8 C.4 Serial Communications Interface 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-10 C.5 Serial Communications Interface 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-11 C.6 Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-12 C.7 Analog-to-Digital Converter 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-13 C.8 Analog-to-Digital Converter 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-14 C.9 Analog-to-Digital Converter 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-15 ASCII Character Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-1 Lists the ASCII character set that the TMS370 assembler recognizes Opcode/Instruction Cross-Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-1 Contains an opcode-to-instruction cross-reference Instruction/Opcode Cross-Reference and Bus Activity Table . . . . . . . . . . . . . . . . . . . . . . . . F-1 Contains both an instruction-to-opcode cross reference and an instruction bus activity table. The bus activity table specifies the cycle-by-cycle actions of a given instruction. F.1 Instruction/Opcode Cross-Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F-2 F.2 Bus Activity Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F-6
C
D E F
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G
Device Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G-1 Provides pinouts for the individual device categories PLCC-to-PGA Socket Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . H-1 Shows the pinouts for the standard PLCC to PGA sockets that are commonly used in prototype and production applications. You can use these pinouts when you wirewrap your breadboard with a socket. PACT.H MACROS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-1 Lists and describes the macros that are defined in the PACT.H file I.1 General Comments About Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I.1.1 Addressing Commands and Definitions in Dual-Port RAM . . . . . . . . . . . . . . I.1.2 Defining Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I.1.3 Defining Actions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Comments About Specific Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I.2.1 Standard Compare Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I.2.2 Conditional Compare Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I.2.3 Virtual Timer Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I.2.4 Baud Timer Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PACT.H Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-2 I-2 I-3 I-3 I-4 I-4 I-4 I-4 I-4 I-5
H
I
I.2
I.3 J
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . J-1 Defines acronyms and key terms used in this book
Contents
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Figures
Figures
1-1 1-2 1-3 1-4 1-5 1-6 1-7 1-8 1-9 1-10 1-11 1-12 1-13 1-14 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8
xxiv
TMS370Cx0x Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21 TMS370Cx1x Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22 TMS370Cx2x Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-23 TMS370Cx32 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-24 TMS370Cx36 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25 TMS370Cx4x Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-26 TMS370Cx5x Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-27 TMS370Cx6x Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28 TMS370Cx7x Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-29 TMS370Cx8x Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-30 TMS370Cx9x Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-31 TMS370CxAx Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-32 TMS370CxBx Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-33 TMS370CxCx Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-34 Pinouts for TMS370Cx0x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Pinouts for TMS370Cx1x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 Pinouts for TMS370Cx2x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 Pinout for TMS370Cx32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 Pinout for TMS370Cx36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 Pinouts for TMS370Cx4x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 Pinouts for TMS370Cx5x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 Pinouts for TMS370Cx6x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 Pinouts for TMS370Cx7x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24 Pinouts for TMS370Cx8x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27 Pinouts for TMS370Cx9x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30 Pinouts for TMS370CxAx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-33 Pinouts for TMS370CxBx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-35 Pinouts for TMS370CxCx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-38 Programmer's Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Stack Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 Program Counter After Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 TMS370 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 Register File Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 Microcomputer Single-Chip Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 Microcomputer Mode With Function A Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22 Microcomputer Mode With Function B Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23
Figures
3-9 3-10 4-1 4-2 4-3 4-4 4-5 4-6 5-1 5-2 5-3 5-4 5-5 5-6 6-1 6-2 6-3 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 7-10 8-1 8-2 8-3 8-4 8-5 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 9-9 9-10 10-1 10-2
Microprocessor Mode Without Internal Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25 Microprocessor Mode With Internal Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28 Peripheral File Frame 1: System Configuration and Control Registers . . . . . . . . . . . . . . . . 4-2 Correct Method to Enter Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 Improper Method to Enter Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 Peripheral File Frames 2 and 3: Digital Port Control Registers . . . . . . . . . . . . . . . . . . . . . 4-21 Typical Control-Register Operation Using Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22 System Interface Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-30 Interrupt Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 Peripheral File Frame 1: External Interrupt Control Registers . . . . . . . . . . . . . . . . . . . . . . . 5-9 Interrupt 1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 Interrupts 2 and 3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 Simple Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21 Typical Reset Circuit Using a Supply Voltage Supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22 Write Protection Bits in an EEPROM Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 EEPROM Programming Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 EPROM Programming Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14 T1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 Dual Compare Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11 Capture/Compare Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14 T1 System Clock Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16 Pulse Accumulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-19 WD Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-22 Standard WD Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-23 Hard WD Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-25 Simple Counter Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-27 Peripheral File Frame 4: T1 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-31 T2n Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 Dual Compare Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11 Dual Capture Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12 T2n Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-14 Peripheral File Frames 6 (T2A) and 8 (T2B): T2n Control Registers . . . . . . . . . . . . . . . . . 8-18 SCI1 Block Diagram - Three Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 SCI1 Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7 Idle Line Multiprocessor Communication Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9 Double-Buffered WUT and TXSHF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9 Address Bit Multiprocessor Communication Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11 Asynchronous Communication Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12 Isosynchronous Communication Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13 SCI1 RX Signals in Communications Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14 SCI1 TX Signals in Communications Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14 Peripheral File Frame 5: SCI1 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-21 SCI2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 SCI2 Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6
Contents
xxv
Figures
10-3 10-4 10-5 10-6 10-7 11-1 11-2 11-3 12-1 12-2 12-3 13-1 13-2 13-3 14-1 14-2 14-3 15-1 15-2 15-3 15-4 15-5 15-6 15-7 15-8 15-9 15-10 16-1 16-2 16-3 16-4 16-5 16-6 16-7 16-8 16-9 16-10 16-11 16-12 16-13 16-14 16-15 16-16 16-17
xxvi
Idle Line Multiprocessor Communication Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8 Double-Buffered WUT and TXSHF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8 Address Bit Multiprocessor Communication Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9 SCI2 RX Signals in Communications Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10 SCI2 TX Signals in the Communication Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11 SPI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3 SPI Master/Slave Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 Peripheral File Frame 3: SPI Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13 Analog-to-Digital Converter1 (ADC1) Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3 Ratiometric Conversion Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7 Peripheral File Frame 7: ADC1 Converter Control Registers . . . . . . . . . . . . . . . . . . . . . . 12-11 Analog-to-Digital Converter 2 (ADC2) Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3 Ratiometric Conversion Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6 Peripheral File Frame 7: ADC2 Converter Control Registers . . . . . . . . . . . . . . . . . . . . . . 13-10 Analog-to-Digital Converter 3 (ADC3) Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3 Ratiometric Conversion Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-7 Peripheral File Frame 7: ADC3 Converter Control Registers . . . . . . . . . . . . . . . . . . . . . . 14-11 PACT Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3 TMS370 Memory Map Highlighting PACT Areas of the 'Cx36 and 'Cx32 . . . . . . . . . . . . . 15-6 Prescaler Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7 Dual-Port RAM Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-10 Input Capture Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-13 Output Control Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-15 Standard Compare Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-16 Virtual Timer Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-17 Interrupt Vector Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-29 Peripheral File Frame 4: PACT Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-37 Implied Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-6 Register Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-7 Peripheral Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-8 Immediate Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-9 Stack Pointer Relative Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-10 Direct Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-11 Indexed Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-12 Indirect Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-13 Offset Indirect Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-14 Program Counter Relative Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-16 Absolute Direct Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-17 Relative Direct Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-17 Absolute Indexed Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-18 Relative Indexed Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-19 Absolute Indirect Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-20 Relative Indirect Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-20 Absolute Offset Indirect Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-21
Figures
16-18 16-19 17-1 17-2 17-3 17-4 17-5 17-6 17-7 17-8 17-9 17-10 17-11 18-1 18-2 18-3 18-4 18-5 18-6 18-7 18-8 18-9 18-10 18-11 18-12 18-13 18-14 18-15 18-16 18-17 18-18 18-19 18-20 18-21 18-22 18-23 18-24 18-25 18-26 18-27 18-28 18-29 18-30 18-31
Relative Offset Indirect Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-22 Status Register (ST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-22 Software Development Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3 Linker Output Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-6 The Basic Debugger Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-9 Debugger Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-10 BTT Setup Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-13 Dialog Box for Defining Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-14 Example of the Inspect Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-14 Typical XDS System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-16 CDT370 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-19 Application Board (Design Kit Board) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-21 Starter Kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-24 Measurement Points for Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2 Recommended Crystal/Clock Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-4 Typical Output Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-4 Typical Buffer Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-5 Switching Time Measurement Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-6 External Clock Timing for Divide-by-4 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-10 External Clock Timing for Divide-by-1 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-11 SYSCLK TIming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-11 External Clock Timing for Divide-by-4 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-14 External Clock Timing for Divide-by-1 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-15 SYSCLK Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-15 External Clock Timing for Divide-by-4 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-18 External Clock Timing for Divide-by-1 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-19 SYSCLK Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-19 External Clock Timing for Divide-by-4 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-22 External Clock Timing for Divide-by-1 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-23 SYSCLK Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-23 External Clock Timing for Divide-by-4 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-27 External Clock Timing for Divide-by-1 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-28 SYSCLK Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-28 External Clock Timing for Divide-by-4 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-32 External Clock Timing for Divide-by-1 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-33 SYSCLK Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-33 External Clock Timing for Divide-by-4 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-38 External Clock Timing for Divide-by-1 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-39 External Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-41 External Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-42 External Clock Timing for Divide-by-4 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-46 External Clock Timing for Divide-by-1 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-47 External Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-49 External Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-50
Contents
xxvii
Figures
18-32 18-33 18-34 18-35 18-36 18-37 18-38 18-39 18-40 18-41 18-42 18-43 18-44 18-45 18-46 18-47 18-48 18-49 18-50 18-51 18-52 18-53 18-54 18-55 18-56 19-1 19-2 19-3 19-4 19-5 19-6 19-7 19-8 19-9 19-10 19-11 19-12 19-13 19-14 19-15 19-16 19-17 19-18 19-19
xxviii
External Clock Timing for Divide-by-4 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-54 External Clock Timing for Divide-by-1 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-55 SYSCLK Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-56 External Clock Timing for Divide-by-4 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-59 External Clock Timing for Divide-by-1 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-60 SYSCLK Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-61 External Clock Timing for Divide-by-4 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-65 External Clock Timing for Divide-by-1 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-66 SYSCLK Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-67 External Clock Timing for Divide-by-4 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-70 External Clock Timing for Divide-by-1 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-71 SYSCLK Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-72 External Clock Timing for Divide-by-4 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-76 External Clock Timing for Divide-by-1 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-77 SYSCLK Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-78 External Clock Timing for Divide-by-4 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-81 External Clock Timing for Divide-by-1 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-82 SYSCLK Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-83 SCI Isosynchronous Mode Timing for Internal Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-84 SCI Isosynchronous Mode Timing for External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-85 SPI Master Mode External Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-87 SPI Mode Slave External Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-88 Analog Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-91 Analog Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-93 Analog Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-96 Prototype and Production Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-4 Plastic Dual-In-Line Package (N Suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-8 40-Pin Plastic Shrink Dual-In-Line Package (NJ Suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-9 64-Pin Plastic Shrink Dual-In-Line Package, 70-mil Pin Spacing (NM Suffix) . . . . . . . . 19-10 Plastic-Leaded Chip Carrier Package (FN Suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-11 Ceramic (Side-Braze) Dual-In-Line Package (JD Suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . 19-12 40-Pin Ceramic Shrink (Side-Braze) Dual-In-Line Package (JC Suffix) . . . . . . . . . . . . . 19-13 64-Pin Ceramic Shrink Dual-In-Line Package (JN Suffix) . . . . . . . . . . . . . . . . . . . . . . . . . 19-14 Ceramic-J-Leaded Chip Carrier Package (FZ Suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-15 Development Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-16 TMS370 Family Number and Symbol Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-18 Typical Symbolization for 28-pin PLCC Mask-ROM Devices . . . . . . . . . . . . . . . . . . . . . . 19-20 Typical Symbolization for 44-pin PLCC Mask-ROM Devices . . . . . . . . . . . . . . . . . . . . . . 19-20 Typical Symbolization for 68-pin PLCC Mask-ROM Devices . . . . . . . . . . . . . . . . . . . . . . 19-20 Typical Symbolization for 28-pin PDIP Mask-ROM Devices . . . . . . . . . . . . . . . . . . . . . . 19-21 Typical Symbolization for 40-pin PDIP Mask-ROM Devices . . . . . . . . . . . . . . . . . . . . . . 19-21 Typical Symbolization for 40-pin PSDIP Mask-ROM Devices . . . . . . . . . . . . . . . . . . . . . 19-21 Typical Symbolization for 64-pin PSDIP Mask-ROM Devices . . . . . . . . . . . . . . . . . . . . . 19-21 Typical Symbolization for 28-pin PLCC Program EPROM Devices (OTP) . . . . . . . . . . . 19-22
Figures
19-20 19-21 19-22 19-23 19-24 19-25 19-26 19-27 19-28 19-29 19-30 C-1 C-2 C-3 C-4 C-5 C-6 C-7 C-8 C-9 C-10 C-11 C-12 C-13 C-14 G-1 G-2 G-3 G-4 G-5 G-6 G-7 G-8 G-9 G-10 G-11 G-12 G-13 G-14 H-1
Typical Symbolization for 44-pin PLCC Program EPROM Devices (OTP) . . . . . . . . . . . 19-22 Typical Symbolization for 68-pin PLCC Program EPROM Devices (OTP) . . . . . . . . . . . 19-22 Typical Symbolization for 28-pin PDIP Program EPROM Devices (OTP) . . . . . . . . . . . 19-22 Typical Symbolization for 40-pin PDIP Program EPROM Devices (OTP) . . . . . . . . . . . 19-22 Typical Symbolization for 40-pin PSDIP EPROM Devices (OTP) . . . . . . . . . . . . . . . . . . 19-22 Typical Symbolization for 64-pin PSDIP Reprogrammable EPROM . . . . . . . . . . . . . . . . . . . . . Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-23 Typical Symbolization for 28-pin and 40-pin CDIP Reprogrammable . . . . . . . . . . . . . . . . . . . . EPROM Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-23 Typical Symbolization for 40-pin CSDIP Reprogrammable EPROM . . . . . . . . . . . . . . . . . . . . Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-23 Typical Symbolization for 64-pin CSDIP Reprogrammable EPROM . . . . . . . . . . . . . . . . . . . . . Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-23 Typical Symbolization for 44-pin and 68-pin CLCC Reprogrammable . . . . . . . . . . . . . . . . . . . . EPROM Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-24 Typical Symbolization for 28-pin CLCC Reprogrammable EPROM Devices . . . . . . . . . 19-24 Interrupt 1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-2 Interrupts 2 and 3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-3 T1 System Clock Prescaler Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-4 WD Timer Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-5 T1: Dual Compare Mode Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-6 T1: Capture/Compare Mode Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-7 T2n: Dual Compare Mode Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-8 T2n: Dual Capture Mode Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-9 SCI1 Block Diagram - Three Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-10 SCI2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-11 SPI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-12 ADC1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-13 ADC2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-14 ADC3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-15 Pinouts for TMS370Cx0x Devices (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G-2 Pinouts for TMS370Cx1x Devices (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G-2 Pinouts for TMS370Cx2x Devices (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G-3 Pinouts for TMS370Cx32 Devices (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G-4 Pinouts for TMS370Cx36 Devices (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G-5 Pinouts for TMS370Cx4x Devices (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G-6 Pinouts for TMS370Cx5x Devices (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G-7 Pinouts for TMS370Cx6x Devices (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G-8 Pinouts for TMS370Cx7x Devices (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G-9 Pinouts for TMS370Cx8x Devices (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G-10 Pinouts for TMS370Cx9x Devices (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G-10 Pinouts for TMS370CxAx Devices (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G-11 Pinouts for TMS370CxBx Devices (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G-12 Pinouts for TMS370CxCx Devices (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G-13 28-Pin PGA Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . H-2
Contents
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Figures
H-2 H-3 H-4 H-5 H-6 H-7 H-8 H-9 H-10 H-11 H-12 H-13 H-14 H-15 H-16
TMS370Cx0x Device PGA Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . H-3 TMS370Cx1x Device PGA Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . H-4 TMS370CxCx Device PGA Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . H-5 44-Pin PGA Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . H-6 TMS370Cx2x Device PGA Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . H-7 TMS370Cx32 Device PGA Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . H-8 TMS370Cx36 Device PGA Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . H-9 TMS370Cx4x Device PGA Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . H-10 TMS370Cx8x Device PGA Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . H-11 TMS370Cx9x Device PGA Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . H-12 68-Pin PGA Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . H-13 TMS370Cx5x Device PGA Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . H-14 TMS370Cx6x Device PGA Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . H-15 TMS370Cx7x Device PGA Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . H-16 TMS370CxBx Device PGA Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . H-17
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Tables
1-1 1-2 1-3 1-4 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 5-1 5-2 Typical Applications for TMS370 Family Microcontroller Devices . . . . . . . . . . . . . . . . . . . . 1-2 TMS370 Families and Their Corresponding Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 Bits Per Port for TMS370 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 TMS370 Family Architecture, Memory, and Module Summary . . . . . . . . . . . . . . . . . . . . . 1-13 TMS370Cx0x Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 TMS370Cx1x Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 TMS370Cx2x Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 TMS370x32 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 TMS370Cx36 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 TMS370Cx4x Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 TMS370Cx5x Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 TMS370Cx6x Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 TMS370Cx7x Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25 TMS370Cx8x Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28 TMS370Cx9x Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31 TMS370CxAx Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-34 TMS370CxBx Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-36 TMS370CxC Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-39 Peripheral File Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 Vector Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 Memory Modes Available Per Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 Memory-Enabled Pins Activated when Memory Accessed . . . . . . . . . . . . . . . . . . . . . . . . . 3-20 Microcomputer Mode with Function A Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21 Microcomputer with Function B Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24 Microprocessor Mode with Internal Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27 Operating Mode Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29 Privilege-Mode Configuration Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 Wait-State Control Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 Powerdown/Idle Control Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 Digital I/O Pins by Device Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20 Port Configuration Registers Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23 Function A and B Signal Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24 TMS370 Family and Internal Program Memory (64- and 68-pin packages) . . . . . . . . . . . 4-25 TMS370 Family EDS External Memory Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26 Interrupts and Reset Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Module Interrupt Priority in Lowest-to-Highest Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
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5-3 5-4 5-5 6-1 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 8-1 8-2 8-3 8-4 8-5 8-6 9-1 9-2 9-3 9-4 9-5 10-1 10-2 10-3 10-4 10-5 10-6 11-1 11-2 12-1 13-1 14-1 14-2 15-1 15-2 15-3 15-4 15-5 15-6 15-7 15-8 15-9
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Interrupt Vector Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19 Control-Bit States Following a Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21 EPROM Memory Map Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11 Timer-System Solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 T1 I/O Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 T1 and WD Timer Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 T1 Compare Values: (5 MHz SYSCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8 Counter Overflow Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-18 WD Option Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-28 Counter Clock Sources for the WD Input Select 0-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-33 Clock Sources for the T1 General Purpose Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-33 System-Requirement Solutions Using T2n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 T2n I/O Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 T2n Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5 T2n Compare Values: (5-MHz SYSCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7 T2n Capture Register MSbyte and LSbyte Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8 T2n Capture/Compare Register MSbyte and LSbyte Addresses . . . . . . . . . . . . . . . . . . . . . 8-8 SCI1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6 Programming the Data Format Using SCICCR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7 Asynchronous Baud Register Values for Common SCI1 Bit Rates . . . . . . . . . . . . . . . . . . 9-17 Character Bit Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-23 Flags Affected by SCI SW RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-24 SCI2 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5 Programming the Data Format Using SCICCR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6 Asynchronous Baud Register Values for Common SCI2 Bit Rates . . . . . . . . . . . . . . . . . 10-13 Peripheral File Frame 5: SCI2 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-17 Character Bit Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-19 Flags Affected by SCI SW RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-20 SPI Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4 Common SPI Bit Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10 ADC1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4 ADC2 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4 ADC3 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4 Conversion Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-17 PACT Peripheral Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4 Number of Time Slots Available for Each Prescale Setting . . . . . . . . . . . . . . . . . . . . . . . . . 15-8 Bits That Control Functions on the Input Capture Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-12 Interrupt Vector Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-30 Bits Determining PACT-Module Time Base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-39 Bits Defining the Command/Definition Area Start Addresses . . . . . . . . . . . . . . . . . . . . . . 15-41 Bits Defining the Command/Definition Area End Addresses . . . . . . . . . . . . . . . . . . . . . . . 15-43 Buffer Pointer Address Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-45 Rising/Falling Edge Capture Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-51
Tables
15-10 15-11 16-1 16-2 16-3 16-4 16-5 16-6 17-1 18-1 18-2 18-3 18-4 18-5 18-6 18-7 18-8 18-9 18-10 18-11 18-12 18-13 18-14 18-15 18-16 18-17 18-18 18-19 18-20 18-21 18-22 18-23 18-24 18-25 18-26 18-27 18-28 18-29 18-30 18-31
Rising/Falling Edge Capture Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-53 Rising/Falling Edge Capture Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-55 TMS370 Symbols Defined . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3 Overview of Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4 TMS370 Family Instruction Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-23 TMS370 Family Opcode/Instruction Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-30 Compare Instruction Examples--Status Bit Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-44 Conditional-Jump Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-62 OTP and Reprogrammable EPROM Support of ROM Devices . . . . . . . . . . . . . . . . . . . . 17-27 Absolute Maximum Ratings Over Operating Free-Air Temperature Range . . . . . . . . . . . 18-3 General-Purpose Output Signal Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-6 EEPROM Timing Requirements for Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-7 Recommended EPROM Operating Conditions for Programming . . . . . . . . . . . . . . . . . . . 18-7 EPROM Timing Requirements for Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-7 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-8 Electrical Characteristics Over Recommended Operating Free-Air Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-9 External Clocking Requirements for Divide-by-4 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-10 External Clocking Requirements for Divide-by-1 Clock (PLL) . . . . . . . . . . . . . . . . . . . . . 18-11 Switching Characteristics and Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-11 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-12 Electrical Characteristics Over Recommended Operating Free-Air Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-13 External Clocking Requirements for Divide-by-4 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-14 External Clocking Requirements for Divide-by-1 Clock (PLL) . . . . . . . . . . . . . . . . . . . . . 18-15 Switching Characteristics and Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-15 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-16 Electrical Characteristics Over Recommended Operating Free-Air Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-17 External Clocking Requirements for Divide-by-4 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-18 External Clocking Requirements for Divide-by-1 Clock (PLL) . . . . . . . . . . . . . . . . . . . . . 18-19 Switching Characteristics and Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-19 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-20 Electrical Characteristics Over Recommended Operating Free-Air Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-21 External Clocking Requirements For Divide-by-4 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . 18-22 External Clocking Requirements for Divide-by-1 Clock (PLL) . . . . . . . . . . . . . . . . . . . . . 18-23 Switching Characteristics and Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-23 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-25 Electrical Characteristics Over Recommended Operating Free-Air Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-26 External Clocking Requirements for Divide-by-4 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-27 External Clocking Requirements For Divide-by-1 Clock (PLL) . . . . . . . . . . . . . . . . . . . . 18-28 Switching Characteristics and Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-28 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-30
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Tables
18-32 Electrical Characteristics Over Recommended Operating Free-Air Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-33 External Clocking Requirements for Divide-by-4 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-34 External Clocking Requirements for Divide-by-1 Clock (PLL) . . . . . . . . . . . . . . . . . . . . . 18-35 Switching Characteristics and Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-36 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-37 Electrical Characteristics Over Recommended Operating Free-Air Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-38 External Clocking Requirements for Divide-by-4 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-39 External Clocking Requirements for Divide-by-1 Clock (PLL) . . . . . . . . . . . . . . . . . . . . . 18-40 Switching Characteristics and Timing Requirements for External Read and Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-41 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-42 Electrical Characteristics Over Recommended Operating Free-Air Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-43 External Clocking Requirements for Divide-by-4 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-44 External Clocking Requirements for Divide-by-1 Clock (PLL) . . . . . . . . . . . . . . . . . . . . . . 18-45 Switching Characteristics and Timing Requirements for External Read and Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-46 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-47 Electrical Characteristics Over Recommended Operating Free-Air Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-48 External Clocking Requirements for Divide-by-4 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-49 External Clocking Requirements for Divide-by-1 Clock (PLL) . . . . . . . . . . . . . . . . . . . . . . 18-50 Switching Characteristics and TIming Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-51 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-52 Electrical Characteristics Over Recommended Operating Free-Air Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-53 External Clocking Requirements for Divide-by-4 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-54 External Clocking Requirements for Divide-by-1 Clock (PLL) . . . . . . . . . . . . . . . . . . . . . 18-55 Switching Characteristics and Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-56 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-57 Electrical Characteristics Over Recommended Operating Free-Air Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-58 External Clocking Requirements for Divide-by-4 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-59 External Clocking Requirements for Divide-by-1 Clock (PLL) . . . . . . . . . . . . . . . . . . . . . 18-60 Switching Characteristics and Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-61 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-62 Electrical Characteristics Over Recommended Operating Free-Air Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-63 External Clocking Requirements for Divide-by-4 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-64 External Clocking Requirements for Divide-by-1 Clock (PLL) . . . . . . . . . . . . . . . . . . . . . 18-65 Switching Characteristics and Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-66 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-67 Electrical Characteristics Over Recommended Operating Free-Air Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
xxxiv
18-31 18-32 18-33 18-33 18-35 18-36 18-38 18-39 18-40 18-44 18-45 18-46 18-47 18-48 18-52 18-53 18-54 18-55 18-56 18-57 18-58 18-59 18-60 18-61 18-63 18-64 18-65 18-66 18-67 18-68 18-69 18-70 18-71 18-72 18-74 18-75
Tables
18-68 18-69 18-70 18-71 18-72 18-73 18-74 18-75 18-76 18-77 18-78 18-79 18-80 18-81 18-82 18-83 18-84 18-85 18-86 18-87 18-88 19-1 19-2 A-1 A-2 A-3 A-4 A-5 A-6 A-7 A-8 A-9 A-10 A-11 E-1 F-1 F-2 F-3 F-4
External Clocking Requirements for Divide-by-4 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-76 External Clocking Requirements for Divide-by-1 Clock (PLL) . . . . . . . . . . . . . . . . . . . . . 18-77 Switching Characteristics and Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-78 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-79 Electrical Characteristics Over Recommended Operating Free-Air Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-80 External Clocking Requirements for Divide-by-4 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-81 External Clocking Requirements for Divide-by-1 Clock (PLL) . . . . . . . . . . . . . . . . . . . . . 18-82 Switching Characteristics and Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-83 SCI Isosynchronous Mode Timing Characteristics and Requirements for Internal Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-84 SCI Isosynchronous Mode Timing Characteristics and Requirements for External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-85 SPI Master Mode External Timing Characteristics and Requirements . . . . . . . . . . . . . . 18-86 SPI Slave Mode External Timing Characteristics and Requirements . . . . . . . . . . . . . . . 18-88 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-89 ADC1 Electrical Characteristics Over Recommended Operating Free-Air Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-90 Analog Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-91 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-92 ADC2 Electrical Characteristics Over Recommended Operating Free-Air Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-92 Analog Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-93 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-94 ADC3 Electrical Characteristics Over Recommended Operating Free-Air Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-95 Analog Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-96 Package Types and Associated Family Members . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-7 Symbolization Designators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-19 WD Option Summary for TMS370CxxxA Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2 Clock Option Summary for TMS370CxxxA Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-3 Summary for TMS370CxxxA, TMS370C7xxB, and TMS370Cxxx Devices . . . . . . . . . . . . A-4 EPROM Memory Map for TMS370C758 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-7 Switching Characteristics and Timing Requirements for External Read and Write . . . . . . A-8 IOL (Low-Level Output Current) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-9 SCI1 Isosynchronous Mode Timing Characteristics for Internal Clock . . . . . . . . . . . . . . . . A-9 SPI External Timing Characteristics and Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-9 Recommended EPROM Operating Conditions for Programming . . . . . . . . . . . . . . . . . . . A-10 Recommended EPROM Timing Requirements for Programming . . . . . . . . . . . . . . . . . . . A-10 Summary of Differences Among the TMS370Cxxx, TMS370CxxxA, and TMS370C7xxB Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-11 TMS370 Family Opcode/Instruction Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2 TMS370 Family Instruction/Opcode Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FF-3 Possible Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F-7 Internal Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F-7 Bus Activity Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FF-8
Contents
xxxv
Examples
Examples
4-1 6-1 6-2 7-1 11-1 15-1 15-2 15-3 19-1 I-1 Digital Port Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-28 Write Protection Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 Data EEPROM Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8 Standard WD Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-24 Register Values in an SPI Character-Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8 Routine to Perform a PWM FOR 'X32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-34 Example 1, if OP SET/CLR SELECT = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-49 Example 2, if OP SET/CLR SELECT = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-49 New Code Release Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-5 Macro Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-5
xxxvi
Chapter 1
Introduction to the TMS370 Family Devices
The TMS370 family consists of VLSI, 8-bit, CMOS microcontrollers with onchip EEPROM storage and peripheral support functions. These devices offer superior performance in complex, realtime control applications in demanding environments. They are available with mask-programmable ROM and OTP/ EPROM. This chapter covers the following topics:
Topic
1.1 1.2 1.3 1.4 1.5 1.6 1.7
Page
Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Available Development Support Products . . . . . . . . . . . . . . . . . . . . . . . 1-3 Device Families . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 Key Features of the TMS370 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Major Components of the TMS370 Architecture . . . . . . . . . . . . . . . . . . 1-7 Summary of Components by Device . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 Device Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21
Texas Instruments has added new, more robust features to the TMS370 family of devices. These features are designed to enhance performance and enable new application technologies. The improved features include new watchdog modes, low-power modes, clock module, ROM security, standby RAM, Analog-to-Digital Converters, Serial Communication Interface 2, Timer 2B, and I/O ports. All family members are software compatible, so you can run many existing applications on the improved devices without having to modify your software. (Refer to Appendix A for more information about compatibility.) There are 14 device families (see Table 1-2 on page 1-4 for a full listing). This chapter describes the key features and major components of each of the TMS370 microcontroller families, and includes block diagrams to illustrate controllers from each device family.
Introduction to the TMS370 Family Devices
1-1
Typical Applications
1.1 Typical Applications
In expanding its powerful TMS370 family of microcontrollers, TI offers many new configurable devices for specific applications. As microcontrollers have evolved, TI has added multiple peripheral functions to chips that originally had only a CPU, memory, and I/O blocks. Now, with the high-performance, software-compatible TMS370 microcontrollers, you can choose from over 78 standard products. Alternatively, you can use as many as 27 function modules to configure your new device quickly, easily, and cost effectively for your application. The TMS370 family of devices is the ideal choice for the applications shown in Table 1-1.
Table 1-1. Typical Applications for TMS370 Family Microcontroller Devices
Application Area Automotive Applications Climate control systems Cruise control Entertainment systems Instrumentation Keyboards Peripheral interface control Disk controllers Motor control Temperature controllers Process control Modems Intelligent phones Intelligent line card control Navigational systems Engine control Antilock braking Body controllers Terminals Tape Drives Meter control Medical instrumentation Security systems Telecopiers Debit cards
Computer
Industrial
Telecommunications
1-2
Available Development Support Products
1.2 Available Development Support Products
The TMS370 family is fully supported by development tools that facilitate simplified software development for bringing new products to market more quickly. These tools include an assembler, a linker, an optimizing C compiler, a C source debugger, a design kit, a starter kit (with simulator), an in-circuit emulator, and an OTP/EPROM programmer. All of these tools work together using an IBM-compatible personal computer (PC) as the host and central control element. This allows you to select the host computer method of text management, and editing tools according to your system requirements. The TMS370 in-circuit emulator (XDS --eXtended Development Support and the CDT370 Compact Development Tool) allows you to immediately begin designing, testing, and debugging your system. This is because the emulator is modular and configurable, eliminating the need to produce a complete new emulator for each TMS370 configuration. More detailed information on development support products is provided in Chapter17, Development Support.
Introduction to the TMS370 Family Devices
1-3
Device Families
1.3 Device Families
TMS370 devices are divided into 14 families as shown Table 1-2. All the families are supported by a full complement of development tools.
Table 1-2. TMS370 Families and Their Corresponding Devices
Family TMS370Cx0x TMS370Cx1x TMS370C002A SE370C702 TMS370C010A TMS370C311A TMS370C712B TMS370C020A TMS370C322A TMS370C032A SE370C732{ TMS370C036A TMS370C040A TMS370C042A TMS370C050A TMS370C058A TMS370C156A TMS370C350A TMS370C356A TMS370C456A TMS370C758B SE370C758A{ TMS370C067A TMS370C768A SE370C769A{ TMS370C077A TMS370C080 SE370C686A TMS370C090A TMS370C3A7A TMS370C0B6A TMS370C3C0A TMS370C6C2A SE370C6C2A Devices Included TMS370C302A TMS370C012A TMS370C312A SE370C712A TMS370C022A TMS370C722 TMS370C332A TMS370C736A TMS370C340A TMS370C342A TMS370C052A TMS370C059A TMS370C250A TMS370C352A TMS370C358A TMS370C756A TMS370C759A SE370C758B{ TMS370C068A TMS370C769A TMS370C777A TMS370C380A TMS370C792 TMS370C702 TMS370C310A TMS370C712A SE370C712B TMS370C320A SE370C722{ TMS370C732A SE370C736A{ TMS370C742A SE370C742A{ TMS370C056A TMS370C150A TMS370C256A TMS370C353A TMS370C452A TMS370C758A SE370C756A{ SE370C759A{ TMS370C069A SE370C768A SE370C777A TMS370C686A SE370C792
TMS370Cx2x TMS370Cx32 TMS370Cx36 TMS370Cx4x TMS370Cx5x
TMS370Cx6x
TMS370Cx7x TMS370Cx8x TMS370Cx9x TMS370CxAx TMS370CxBx TMS370CxCx
These devices are system evaluators and are used only in a prototype environment. Their reliability has not been characterized. These devices use the recommended TMS370C758 (with converter socket) for prototyping. This device uses the recommended TMS370C758 for prototyping. Refer to the TMS370CxBx Data Sheet (SPNS038) for pin-to-pin compatibility.
1-4
Key Features of the TMS370 Family
1.4 Key Features of the TMS370 Family
Each TMS370 device family has the following key features (not all features are available for all devices):
-
Compatibility for supporting software migration between current and future microcontrollers CMOS EPROM technology for providing reprogrammable EPROM and OTP (one-time programmable) program memory for prototypes and for small-volume or quick-turn production CMOS EEPROM technology for providing EEPROM programming with a single 5-V supply ADC technology for converting analog signals to digital values Static RAM/registers for offering numerous memory options Standby RAM that offers data protection during a power-off condition Flexible operating features:
J J
H H H J H H J H H
J J J J J J J
Power-reduction standby and halt modes Operating temperature options: 0C to 70C (L range) - 40C to 85C (A range) - 40C to 105C (T range) Temperature range by device: ROM devices: A, L, and T EPROM and ROMless: T only Input clock frequency options: Divide by 4 (0.5 to 5 MHz SYSCLK) standard oscillator Divide by 1 (2 to 5 MHz SYSCLK) phase-locked loop Operating voltage range: 5 V 10%
Flexible interrupt handling for design flexibility: Two programmable interrupt levels Programmable rising- or falling-edge detect
System integrity features that increase flexibility during the software development phase: Oscillator fault detection Privileged mode lockout Watchdog timer Memory security (ROM)
Introduction to the TMS370 Family Devices
1-5
Key Features of the TMS370 Family
-
Memory-mapped ports for easy addressing An optimizing C compiler that translates ANSI C programs into TMS370 assembly language source A high-level language debugger that lets you refine and correct code A modular library for quickly changing the device configuration. 18 addressing modes that use eight formats, including the following:
-
J J J J J
Implied Register-to-register arithmetic Indirect addressing Indexed and indirect branches and calls PC relative
250-mA typical latch-up immunity at 25C ESD (electrostatic discharge) protection that exceeds 2000 V per MILSTD-883C method 3015
1-6
Major Components of the TMS370 Architecture
1.5 Major Components of the TMS370 Architecture
In addition to the features listed in Section 1.4, the TMS370 families have the following architectural features. Table 1-4 on page 1-13 summarizes the features described below.
CPU
The TMS370 8-bit CPU has a status register, a program counter register, and a stack pointer. The CPU uses another feature, the register file, as working registers, accessed on the internal bus in one bus cycle. The 8-bit internal bus also allows access to memory and to the peripheral interfaces. The TMS370Cx5x, TMS370Cx6x, TMS370Cx7x, and TMS370CxBx devices allow external memory expansion through ports A, B, C, and D. Refer to Chapter 3, CPU and Memory Organization, for more complete information about the CPU.
Register File
The register file is located at the beginning of the TMS370 memory map. Register-access instructions in the TMS370 instruction set allow access to any of the first 256 registers (if available) in one bus cycle. The register file is used as general-purpose RAM and contains the stack. Chapter 3, CPU and Memory Organization, provides additional information about the register file.
RAM
RAM modules other than those contained in the register file are mapped after the register file. The TMS370 accesses this RAM in two cycles. Memory is described in full in Chapter 3, CPU and Memory Organization.
Data EEPROM
With the exception of the TMS370CxAx and TMS370CxCx families, all the devices in each product family use EEPROM. The data EEPROM modules provide in-circuit programmability and data retention in power-off mode. The modules contain 256 or 512 bytes of EEPROM. This memory is useful for constants and infrequently changed variables required by the application program. The EEPROM can be
Introduction to the TMS370 Family Devices
1-7
Major Components of the TMS370 Architecture
programmed and erased by using available EEPROM programmers or by the TMS370 itself under program control. The data EEPROM modules are described in Chapter 6, EPROM and EEPROM Modules.
Program Memory
The program memory provides alternatives to meet the needs of your application. The program memory modules presently contain 2K, 4K, 8K, 16K, 24K, 32K, or 48K bytes of memory. The program memory in TMS370C6xx, TMS370C7xx, SE370C6xx, and SE370C7xx devices is EPROM. EPROM, in a windowed ceramic package, can be programmed, erased, and reprogrammed for prototyping. EPROM devices in a non-windowed plastic package are one-time programmable (OTP) devices, used for small production runs. In TMS370C0xx, TMS370C3xx, and TMS370C4xx devices, the program memory is mask ROM that is programmed at the factory. ROM devices are appropriate for larger volume production. Program memory is discussed in Chapter 6, EPROM and EEPROM Modules.
Input/Output Ports
The TMS370 family of devices have varying numbers of I/O ports, and of various port widths. Table 1-3 lists the widths, in the number of bits, for each of the ports of the different TMS370 families. I/O ports are described in greater detail in Chapter 4, System and Digital I/O Configuration.
1-8
Major Components of the TMS370 Architecture
Table 1-3. Bits Per Port for TMS370 Devices
Bits for Ports A - H Families{ TMS370Cx0x, TMS370Cx1x TMS370Cx2x TMS370Cx32 TMS370Cx36 TMS370Cx4x TMS370Cx5x, (64 pin) TMS370Cx5x, (68 pin) TMS370Cx6x TMS370Cx7x (64 pin) TMS370Cx7x (68 pin) TMS370Cx8x (40 pin) TMS370Cx8x (44 pin) TMS370Cx9x TMS370CxAx TMS370CxBx (64 pin) TMS370CxBx (68 pin) TMS370CxCx A 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 1 8 8 3 8 8 8 8 8 8 8 8 8 8 8 8 6 8 8 1 B C D 5 5 4 5 5 6 8
5
G
H
6 8 5 5 5 5 6 8 4
6 6
8 8
1 1
For all families, the ports for these microcontrollers can be programmed, bit by bit, to function as either digital input or digital output. These ports can be configured by the software as the data bus, control bus, and address bus for external memory. Any bits not needed for external memory can be programmed to be either digital input or digital output.
Timer 1
Timer 1 is a 16-bit timer that can be configured in the following ways:
-
A programmable 8-bit prescaler (providing a 24-bit realtime timer) that determines the independent clock sources for the general-purpose timer and the watchdog timer A 16-bit event timer to keep a cumulative total of the transitions A 16-bit pulse accumulator to measure the pulse input width A 16-bit input-capture function that latches the counter value on the occurrence of an external input
Introduction to the TMS370 Family Devices
1-9
Major Components of the TMS370 Architecture
-
Two 16-bit compare registers that trigger when the counter matches the contents of a compare register A self-contained PWM (pulse-width modulated) output control function
The operation of the timer can generate an interrupt to the CPU, set flag bits, reset the timer counter, toggle an I/O line, or generate PWM outputs. The timer can provide as much as 200 ns of resolution with a system clock (SYSCLK) speed of 5 MHz. Timer 1 is described fully in Chapter 7.
Timer 2n
Timers 2A and 2B are 16-bit timers that can be configured in the following ways:
-
Four independent clock sources for the general-purpose timer A 16-bit event timer to keep a cumulative total of the transitions A 16-bit pulse accumulator to measure the input pulse duration Two 16-bit input-capture devices which change a counter value to match the contents of a compare register Two 16-bit compare registers which trigger when a counter matches the contents of a compare register A self-contained PWM (pulse-width modulated) output controller
The operation of timers 2A and 2B can generate an interrupt to the CPU, set flag bits, reset the timer counter, toggle an I/O line, or generate PWM outputs. These timers provide as many as 200ns of resolution with a SYSCLK speed of 5 MHz. Timers 2A and 2B are described fully in Chapter 8.
Watchdog Timer
The watchdog timer helps ensure system integrity. It can be programmed to generate a hardware reset when it times out. This function provides a hardware monitor over the software to avoid losing a program. If it is not needed as a watchdog, this timer can be used as a general-purpose timer. For more information about the watchdog timer, refer to Section 7.7, page 7-21.
1-10
Major Components of the TMS370 Architecture
PACT (Programmable Acquisition and Control Timer)
The PACT module in the TMS370Cx3x family is a programmable timing module that uses some of the on-chip RAM to store its commands as well as the timer values. Only the TMS370Cx36 device offers 256-bytes of standby RAM, which protects data stored there against power failures. The PACT module offers the following:
-
Input capture on as many as six pins, four of which can have a programmable prescaler One input capture pin that can drive an 8-bit event counter As many as eight timer-driven outputs A timer capability of as many as 20 bits Interaction between event counter and timer activity 18 independent interrupt vectors to allow the better servicing of events A watchdog timer with a selectable time-out period A mini-SCI (serial communications interface), which works as a fullduplex UART (universal asynchronous receiver transmitter)
Once set up, the PACT requires no CPU overhead except to service interrupts. The PACT module is described fully in Chapter 15, Programmable Acquisition and Control Timer (PACT).
SCI (Serial Communications Interfaces)
The SCI1 and SCI2 modules are built-in serial interfaces. SCI1 has a 3-pin configuration and SCI2 has a 2-pin configuration. The SCI1 model is programmable to be isosynchronous up to 2.5 Mbps, and both SCIs share the following features:
-
Programmable to be asynchronous (up to 156 kbps) Full-duplex, double-buffered receive (Rx) and transmit (Tx) Programmable format with error-checking capabilities
The SCI1 and SCI2 modules are described fully in Chapter 9, Serial Communications Interface (SCI1) Module, and Chapter 10, Serial Communications Interface (SCI2) Module.
Introduction to the TMS370 Family Devices
1-11
Major Components of the TMS370 Architecture / Summary of Components by Device
SPI (Serial Peripheral Interface)
The SPI module is a built-in serial interface that facilitates communication between the network master, slave CPUs, and external peripheral devices. This module provides synchronous data transmission up to 2.5 Mbps. Like SCI1 and SCI2, the SPI is set up by software. After that, the CPU takes no part in timing, data format, or protocol. Also, like the SCI, the CPU reads and writes to memory-mapped registers to receive and transmit data. A SPI interrupt alerts the CPU when received data is ready. The SPI module is described fully in Chapter 11, Serial Peripheral Interface (SPI) Module.
ADC (Analog-to-Digital Converter) Modules
The 8-bit ADC converter modules perform successive approximated conversion. The term ADC is a general term used for ADC1, ADC2, and ADC3 modules. The ADCs have the following input channels for each of the microcontroller families shown.
-
ADC1 has the following: Four channels in the 40-pin TMS370Cx4x family Eight channels in the 44-pin TMS370Cx4x, TMS370Cx32, and TMS370Cx36 families Eight channels in the 64- and 68-pin TMS370Cx5x, TMS370Cx6x, TMS370Cx7x, and TMS370CxBx families
J J J
-
ADC2 has four channels in the 28-pin TMS370CxCx family ADC3 has 15 channels in the 40- and 44-pin TMS370Cx9x families
The reference source and the input channels are selectable. You can program the conversion result to be the ratio of the input voltage to the reference voltage or the ratio of one analog input to another. Input lines that are not required for analog to digital conversion can be programmed as digital input lines. The ADC converter modules are described in Chapters 12, 13, and 14.
1.6 Summary of Components by Device
The major components of the TMS370 device family (described in Section 1.5) are summarized by device in Table 1-4 beginning on page 1-13.
1-12
Table 1-4. TMS370 Family Architecture, Memory, and Module Summary
Program Memory (bytes) Di Device Family Device ROM EPROM Data Memory (bytes) EEPROM RAM Off-Chip Mem. Exp. E (bytes) Serial Interface Modules Ti Timer Modules ADC Channels I/O Pins Cl k Clock Generator No. No of Pins/ Package@
'Cx0x
TMS370C002A TMS370C302A TMS370C702# SE370C702
8K 8K -- -- 4K 8K 4K 2K 8K -- -- -- --
-- -- 8K 8K -- -- -- -- -- 8K 8K 8K 8K
256 -- 256 256 256 256 -- -- -- 256 256 256 256
256 256 256 256 128 256 128 128 128 256 256 256 256
-- -- -- -- -- -- -- -- -- -- -- -- --
SCI1 SCI1 SCI1 SCI1 SPI SPI SPI SPI SPI SPI SPI SPI SPI
T1 T1 T1 T1 T1 T1 T1 T1 T1 T1 T1 T1 T1
-- -- -- -- -- -- -- -- -- -- -- -- --
22 22 22 22 22 22 22 22 22 22 22 22 22
'Cx1x
TMS370C010A TMS370C012A TMS370C310A TMS370C311A TMS370C312A TMS370C712A# TMS370C712B# SE370C712A SE370C712B
4 or 1 4 or 1 4 4 4 or 1 4 or 1 4 or 1 4 or 1 4 or 1 4 1 4 1
28PLCC 28PLCC 28PLCC 28CLCC 28PDIP/PLCC 28PDIP/PLCC 28PDIP/PLCC 28PDIP/PLCC 28PDIP/PLCC 28PDIP/PLCC 28PDIP/PLCC 28CDIP/CLCC 28CDIP/CLCC
Introduction to TMS370 Family of Devices
1-13
The PACT module has a mini-SCI. SCI1 has a 3-pin configuration and SCI2 has a 2-pin configuration. The timer 1 module includes a watchdog timer that you can program to serve as a general-purpose 16-bit timer. The PACT module includes a watchdog timer. 8 channels for the ADC1 module in the 44-pin package, and 4 channels for the ADC1 module in the 40-pin package In ROMless (microprocessor) mode, all address, data, and control lines are fixed as to their functions. # For OTP (PLCC) availability information, contact your local TI sales office or distributor System evaluator (reprogrammable EPROM) for use in a prototype environment only. k TMS370Cx59 and TMS370Cx69 can only operate up to 3 MHz SYSCLK. h TMS370C45x has ROM security, which inhibits the reading of data using any programmer. 256-byte standby RAM is general-purpose memory and is powered separately by the VCCSTBY pin. The data stored in this memory is protected against power failure on the main VCC1 pins. @Refer to Table 19-1 on page 19-7 for package type acronyms. Uses the recommended TMS370C758 EPROM devices (requiring converter socket) for prototyping. Uses the recommended TMS370C758 EPROM devices for prototyping. Refer to the TMS370CxBx Data Sheet (P/N SPNS038) for pin-to-pin compatibility, which requires software modification. Note: Temperature ranges: ROM: A (-40 C to 85 C), L (0 C to 70 C), and T (-40 C to 105 C); EPROM and ROMless: T only.
Summary of Components by Device
1-14
Summary of Components by Device
Table 1-4. TMS370 Family Architecture, Memory, and Module Summary (Continued)
Program Memory (bytes) Device Family Device ROM EPROM Data Memory (bytes) EEPROM RAM Off-Chip Mem. Exp. (bytes) Serial Interface Modules Timer Modules ADC Channels I/O Pins Clock Generator No. of Pins/ Package@
'Cx2x
TMS370C020A TMS370C022A TMS370C320A TMS370C322A TMS370C722# SE370C722
4K 8K 4K 8K -- -- 8K 8K -- --
-- -- -- -- 8K 8K -- -- 8K 8K
256 256 -- -- 256 256 256 -- 256 256
256 256 256 256 256 256 256 256 256 256
-- -- -- -- -- -- -- -- -- --
SCI1/SPI SCI1/SPI SCI1/SPI SCI1/SPI SCI1/SPI SCI1/SPI PACT- SCI PACT- SCI PACT- SCI PACT- SCI
T1 T1 T1 T1 T1 T1 PACT PACT PACT PACT
-- -- -- -- -- -- ADC1/8 ADC1/8 ADC1/8 ADC1/8
34 34 34 34 34 34 23 23 23 23
'Cx32
TMS370C032A TMS370C332A TMS370C732A# SE370C732A
4 or 1 4 or 1 4 or 1 4 or 1 4 1 4 or 1 4 or 1 4 4
40PDIP/PSDIP/44PLCC 40PDIP/PSDIP/44PLCC 40PDIP/PSDIP/44PLCC 40PDIP/PSDIP/44PLCC 40PDIP/PSDIP/44PLCC 40CDIP/CSDIP/44CLCC 44PLCC 44PLCC 44PLCC 44CLCC
The PACT module has a mini-SCI. SCI1 has a 3-pin configuration and SCI2 has a 2-pin configuration. The timer 1 module includes a watchdog timer that you can program to serve as a general-purpose 16-bit timer. The PACT module includes a watchdog timer. 8 channels for the ADC1 module in the 44-pin package, and 4 channels for the ADC1 module in the 40-pin package In ROMless (microprocessor) mode, all address, data, and control lines are fixed as to their functions. # For OTP (PLCC) availability information, contact your local TI sales office or distributor System evaluator (reprogrammable EPROM) for use in a prototype environment only. k TMS370Cx59 and TMS370Cx69 can only operate up to 3 MHz SYSCLK. h TMS370C45x has ROM security, which inhibits the reading of data using any programmer. 256-byte standby RAM is general-purpose memory and is powered separately by the VCCSTBY pin. The data stored in this memory is protected against power failure on the main VCC1 pins. @Refer to Table 19-1 on page 19-7 for package type acronyms. Uses the recommended TMS370C758 EPROM devices (requiring converter socket) for prototyping. Uses the recommended TMS370C758 EPROM devices for prototyping. Refer to the TMS370CxBx Data Sheet (P/N SPNS038) for pin-to-pin compatibility, which requires software modification. Note: Temperature ranges: ROM: A (-40 C to 85 C), L (0 C to 70 C), and T (-40 C to 105 C); EPROM and ROMless: T only.
Table 1-4. TMS370 Family Architecture, Memory, and Module Summary (Continued)
Program Memory (bytes) Device Family Device ROM EPROM Data Memory (bytes) EEPROM RAM Off-Chip Mem. Exp. (bytes) Serial Interface Modules Timer Modules ADC Channels I/O Pins Clock Generator No. of Pins/ Package@
'Cx36
TMS370C036A
16K
--
256
512
--
SPI/ PACT- SCI SPI/ PACT- SCI SPI/ PACT- SCI SCI1 SCI1 SCI1 SCI1 SCI1 SCI1
PACT
ADC1/8
25
4 or 1 4 4 4 or 1 4 or 1 4 or 1 4 or 1 4 4
44PLCC
TMS370C736A#
--
16K
256
512
--
PACT
ADC1/8
25
44PLCC
SE370C736
--
16K
256
512
--
PACT
ADC1/8
25
44CLCC
'Cx4x
TMS370C040A TMS370C042A TMS370C340A TMS370C342A
4K 8K 4K 8K -- --
-- -- -- -- 8K 8K
256 256 -- -- 256 256
256 256 256 256 256 256
-- -- -- -- -- --
T1/T2A T1/T2A T1/T2A T1/T2A T1/T2A T1/T2A
ADC1/4, 8 ADC1/4, 8 ADC1/4, 8 ADC1/4, 8 ADC1/4, 8 ADC1/4, 8
32/36 32/36 32/36 32/36 32/36 32/36
40PDIP/PSDIP 44PLCC 40PDIP/PSDIP 44PLCC 40PDIP/PSDIP 44PLCC 40PDIP/PSDIP 44PLCC 40PDIP/PSDIP 44PLCC 40CDIP/CSDIP 44CLCC
Introduction to TMS370 Family of Devices
1-15
TMS370C742A# SE370C742A
The PACT module has a mini-SCI. SCI1 has a 3-pin configuration and SCI2 has a 2-pin configuration. The timer 1 module includes a watchdog timer that you can program to serve as a general-purpose 16-bit timer. The PACT module includes a watchdog timer. 8 channels for the ADC1 module in the 44-pin package, and 4 channels for the ADC1 module in the 40-pin package In ROMless (microprocessor) mode, all address, data, and control lines are fixed as to their functions. # For OTP (PLCC) availability information, contact your local TI sales office or distributor System evaluator (reprogrammable EPROM) for use in a prototype environment only. k TMS370Cx59 and TMS370Cx69 can only operate up to 3 MHz SYSCLK. h TMS370C45x has ROM security, which inhibits the reading of data using any programmer. 256-byte standby RAM is general-purpose memory and is powered separately by the VCCSTBY pin. The data stored in this memory is protected against power failure on the main VCC1 pins. @Refer to Table 19-1 on page 19-7 for package type acronyms. Uses the recommended TMS370C758 EPROM devices (requiring converter socket) for prototyping. Uses the recommended TMS370C758 EPROM devices for prototyping. Refer to the TMS370CxBx Data Sheet (P/N SPNS038) for pin-to-pin compatibility, which requires software modification. Note: Temperature ranges: ROM: A (-40 C to 85 C), L (0 C to 70 C), and T (-40 C to 105 C); EPROM and ROMless: T only.
Summary of Components by Device
1-16
Summary of Components by Device
Table 1-4. TMS370 Family Architecture, Memory, and Module Summary (Continued)
Program Memory (bytes) Device Family Device ROM EPROM Data Memory (bytes) EEPROM RAM Off-Chip Mem. Exp. (bytes) Serial Interface Modules Timer Modules ADC Channels I/O Pins Clock Generator No. of Pins/ Package@
'Cx5x
TMS370C050A TMS370C052A TMS370C056A TMS370C058A TMS370C059Ak TMS370C150A TMS370C156A TMS370C250A TMS370C256A TMS370C350A TMS370C352A TMS370C353A TMS370C356A TMS370C358A
4K 8K 16K 32K 48K -- -- -- -- 4K 8K 12K 16K 32K
-- -- -- -- -- -- -- -- -- -- -- -- -- --
256 256 512 256 256 -- -- 256 512 -- -- -- -- --
256 256 512 1024 3584 256 512 256 512 256 256 1536 512 1024
112K 112K 112K 64K 20K 56K 56K 56K 56K 112K 112K 112K 112K 64K
SCI1/SPI SCI1/SPI SCI1/SPI SCI1/SPI SCI1/SPI SCI1/SPI SCI1/SPI SCI1/SPI SCI1/SPI SCI1/SPI SCI1/SPI SCI1/SPI SCI1/SPI SCI1/SPI
T1/T2A T1/T2A T1/T2A T1/T2A T1/T2A T1/T2A T1/T2A T1/T2A T1/T2A T1/T2A T1/T2A T1/T2A T1/T2A T1/T2A
ADC1/8 ADC1/8 ADC1/8 ADC1/8 ADC1/8 ADC1/8 ADC1/8 ADC1/8 ADC1/8 ADC1/8 ADC1/8 ADC1/8 ADC1/8 ADC1/8
53/55 53/55 53/55 53/55 55 55 55 55 55 53/55 53/55 55 53/55 53/55
4 or 1 4 or 1 4 or 1 4 or 1 4 or 1 4 4 4 4 4 or 1 4 or 1 4 or 1 4 or 1 4 or 1
64PSDIP 68PLCC 64PSDIP 68PLCC 64PSDIP 68PLCC 64PSDIP 68PLCC 68PLCC 68PLCC 68PLCC 68PLCC 68PLCC 64PSDIP/ 68PLCC 64PSDIP/ 68PLCC 68PLCC 64PSDIP/ 68PLCC 64PSDIP/ 68PLCC
The PACT module has a mini-SCI. SCI1 has a 3-pin configuration and SCI2 has a 2-pin configuration. The timer 1 module includes a watchdog timer that you can program to serve as a general-purpose 16-bit timer. The PACT module includes a watchdog timer. 8 channels for the ADC1 module in the 44-pin package, and 4 channels for the ADC1 module in the 40-pin package In ROMless (microprocessor) mode, all address, data, and control lines are fixed as to their functions. # For OTP (PLCC) availability information, contact your local TI sales office or distributor System evaluator (reprogrammable EPROM) for use in a prototype environment only. k TMS370Cx59 and TMS370Cx69 can only operate up to 3 MHz SYSCLK. h TMS370C45x has ROM security, which inhibits the reading of data using any programmer. 256-byte standby RAM is general-purpose memory and is powered separately by the VCCSTBY pin. The data stored in this memory is protected against power failure on the main VCC1 pins. @Refer to Table 19-1 on page 19-7 for package type acronyms. Uses the recommended TMS370C758 EPROM devices (requiring converter socket) for prototyping. Uses the recommended TMS370C758 EPROM devices for prototyping. Refer to the TMS370CxBx Data Sheet (P/N SPNS038) for pin-to-pin compatibility, which requires software modification. Note: Temperature ranges: ROM: A (-40 C to 85 C), L (0 C to 70 C), and T (-40 C to 105 C); EPROM and ROMless: T only.
Table 1-4. TMS370 Family Architecture, Memory, and Module Summary (Continued)
Program Memory (bytes) Device Family Device ROM EPROM Data Memory (bytes) EEPROM RAM Off-Chip Mem. Exp. (bytes) Serial Interface Modules Timer Modules ADC Channels I/O Pins Clock Generator No. of Pins/ Package@
'Cx5x (Cont.)
TMS370C452A TMS370C456A TMS370C756A# TMS370C758A# TMS370C758B# TMS370C759Ak# SE370C756A SE370C758A SE370C758B SE370C759Ak
8Kh 16Kh -- -- -- -- -- -- -- --
-- -- 16K 32K 32K 48K 16K 32K 32K 48K
256 512 512 256 256 256 512 256 256 256
256 512 512 1024 1024 3584 512 1024 1024 3584
112K 112K 112K 64K 64K 20K 112K 64K 64K 20K
SCI1/SPI SCI1/SPI SCI1/SPI SCI1/SPI SCI1/SPI SCI1/SPI SCI1/SPI SCI1/SPI SCI1/SPI SCI1/SPI
T1/T2A T1/T2A T1/T2A T1/T2A T1/T2A T1/T2A T1/T2A T1/T2A T1/T2A T1/T2A
ADC1/8 ADC1/8 ADC1/8 ADC1/8 ADC1/8 ADC1/8 ADC1/8 ADC1/8 ADC1/8 ADC1/8
55 55 53/55 53/55 53/55 55 53/55 53/55 53/55 55
4 or 1 4 or 1 4 4 1 4 4 4 1 4
68PLCC 68PLCC 64PSDIP/ 68PLCC 64PSDIP/ 68PLCC 64PSDIP/ 68PLCC 68PLCC 64CSDIP/ 68CLCC 64CSDIP/ 68CLCC 64CSDIP/ 68CLCC 68CLCC
The PACT module has a mini-SCI. SCI1 has a 3-pin configuration and SCI2 has a 2-pin configuration. The timer 1 module includes a watchdog timer that you can program to serve as a general-purpose 16-bit timer. The PACT module includes a watchdog timer. 8 channels for the ADC1 module in the 44-pin package, and 4 channels for the ADC1 module in the 40-pin package In ROMless (microprocessor) mode, all address, data, and control lines are fixed as to their functions. # For OTP (PLCC) availability information, contact your local TI sales office or distributor System evaluator (reprogrammable EPROM) for use in a prototype environment only. k TMS370Cx59 and TMS370Cx69 can only operate up to 3 MHz SYSCLK. h TMS370C45x has ROM security, which inhibits the reading of data using any programmer. 256-byte standby RAM is general-purpose memory and is powered separately by the VCCSTBY pin. The data stored in this memory is protected against power failure on the main VCC1 pins. @Refer to Table 19-1 on page 19-7 for package type acronyms. Uses the recommended TMS370C758 EPROM devices (requiring converter socket) for prototyping. Uses the recommended TMS370C758 EPROM devices for prototyping. Refer to the TMS370CxBx Data Sheet (P/N SPNS038) for pin-to-pin compatibility, which requires software modification. Note: Temperature ranges: ROM: A (-40 C to 85 C), L (0 C to 70 C), and T (-40 C to 105 C); EPROM and ROMless: T only.
Introduction to TMS370 Family of Devices
1-17
Summary of Components by Device
1-18
Summary of Components by Device
Table 1-4. TMS370 Family Architecture, Memory, and Module Summary (Continued)
Program Memory (bytes) Device Family Device ROM EPROM Data Memory (bytes) EEPROM RAM Off-Chip Mem. Exp. (bytes) Serial Interface Modules Timer Modules ADC Channels I/O Pins Clock Generator No. of Pins/ Package@
'Cx6x
TMS370C067A
24K
--
256
1024
24K
SCI1/SPI
T1/T2A/ T2B T1/T2A/ T2B T1/T2A/ T2B T1/T2A/ T2B T1/T2A/ T2B T1/T2A/ T2B T1/T2A/ T2B T1/T2A T1/T2A T1/T2A
ADC1/8
55
4 or 1 4 or 1 4 or 1 4 4 4 4 4 or 1 4 4
68PLCC
TMS370C068A TMS370C069Ak TMS370C768A# TMS370C769A#k SE370C768A SE370C769Ak
32K
--
256
1024
24K
SCI1/SPI
ADC1/8
55
68PLCC
48K
--
256
3584
8K
SCI1/SPI
ADC1/8
55
68PLCC
--
32K
256
1024
24K
SCI1/SPI
ADC1/8
55
68PLCC
--
48K
256
3584
8K
SCI1/SPI
ADC1/8
55
68PLCC
--
32K
256
1024
24K
SCI1/SPI
ADC1/8
55
68CLCC
--
48K
256
3584
8K
SCI1/SPI
ADC1/8
55
68CLCC
'Cx7x
TMS370C077A TMS370C777A# SE370C777A
24K -- --
-- 24K 24K
256 256 256
512 512 512
-- -- --
-- -- --
ADC1/8 ADC1/8 ADC1/8
53/55 53/55 53/55
64PSDIP/ 68PLCC 64PSDIP/ 68PLCC 64CSDIP/ 68CLCC
The PACT module has a mini-SCI. SCI1 has a 3-pin configuration and SCI2 has a 2-pin configuration. The timer 1 module includes a watchdog timer that you can program to serve as a general-purpose 16-bit timer. The PACT module includes a watchdog timer. 8 channels for the ADC1 module in the 44-pin package, and 4 channels for the ADC1 module in the 40-pin package In ROMless (microprocessor) mode, all address, data, and control lines are fixed as to their functions. # For OTP (PLCC) availability information, contact your local TI sales office or distributor System evaluator (reprogrammable EPROM) for use in a prototype environment only. k TMS370Cx59 and TMS370Cx69 can only operate up to 3 MHz SYSCLK. h TMS370C45x has ROM security, which inhibits the reading of data using any programmer. 256-byte standby RAM is general-purpose memory and is powered separately by the VCCSTBY pin. The data stored in this memory is protected against power failure on the main VCC1 pins. @Refer to Table 19-1 on page 19-7 for package type acronyms. Uses the recommended TMS370C758 EPROM devices (requiring converter socket) for prototyping. Uses the recommended TMS370C758 EPROM devices for prototyping. Refer to the TMS370CxBx Data Sheet (P/N SPNS038) for pin-to-pin compatibility, which requires software modification. Note: Temperature ranges: ROM: A (-40 C to 85 C), L (0 C to 70 C), and T (-40 C to 105 C); EPROM and ROMless: T only.
Table 1-4. TMS370 Family Architecture, Memory, and Module Summary (Continued)
Program Memory (bytes) Device Family Device ROM EPROM Data Memory (bytes) EEPROM RAM Off-Chip Mem. Exp. (bytes) Serial Interface Modules Timer Modules ADC Channels I/O Pins Clock Generator No. of Pins/ Package@
'Cx8x
TMS370C080 TMS370C380A TMS370C686A# SE370C686A
4K 4K -- -- 4K -- -- 24K 16K
-- -- 16K 16K -- 8K 8K -- --
256 -- -- -- 256 256 256 -- 256
128 128 256 256 128 128 128 512 384
-- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- SCI1 --
T1 T1 T1 T1 T1 T1 T1 T1/T2A T1
-- -- -- -- ADC3/15 ADC3/15 ADC3/15 -- ADC3/8
33 35 35 35 25 25 25 34 53/55
'Cx9x
TMS370C090A TMS370C792# SE370C792
'CxAx 'CxBx
TMS370C3A7A TMS370C0B6A
4 4 or 1 4 4 4 or 1 4 4 4 or 1 4 or 1
40PLCC 44PLCC 44PLCC 44CLCC 40PSDIP/ 44PLCC 40PSDIP/ 44PLCC 40CSDIP/ 44CLCC 40PDIP 64PSDIP/ 68PLCC
The PACT module has a mini-SCI. SCI1 has a 3-pin configuration and SCI2 has a 2-pin configuration. The timer 1 module includes a watchdog timer that you can program to serve as a general-purpose 16-bit timer. The PACT module includes a watchdog timer. 8 channels for the ADC1 module in the 44-pin package, and 4 channels for the ADC1 module in the 40-pin package In ROMless (microprocessor) mode, all address, data, and control lines are fixed as to their functions. # For OTP (PLCC) availability information, contact your local TI sales office or distributor System evaluator (reprogrammable EPROM) for use in a prototype environment only. k TMS370Cx59 and TMS370Cx69 can only operate up to 3 MHz SYSCLK. h TMS370C45x has ROM security, which inhibits the reading of data using any programmer. 256-byte standby RAM is general-purpose memory and is powered separately by the VCCSTBY pin. The data stored in this memory is protected against power failure on the main VCC1 pins. @Refer to Table 19-1 on page 19-7 for package type acronyms. Uses the recommended TMS370C758 EPROM devices (requiring converter socket) for prototyping. Uses the recommended TMS370C758 EPROM devices for prototyping. Refer to the TMS370CxBx Data Sheet (P/N SPNS038) for pin-to-pin compatibility, which requires software modification. Note: Temperature ranges: ROM: A (-40 C to 85 C), L (0 C to 70 C), and T (-40 C to 105 C); EPROM and ROMless: T only.
Introduction to TMS370 Family of Devices
1-19
Summary of Components by Device
1-20
Summary of Components by Device
Table 1-4. TMS370 Family Architecture, Memory, and Module Summary (Continued)
Program Memory (bytes) Device Family Device ROM EPROM Data Memory (bytes) EEPROM RAM Off-Chip Mem. Exp. (bytes) Serial Interface Modules Timer Modules ADC Channels I/O Pins Clock Generator No. of Pins/ Package@
'CxCx
TMS370C3C0A TMS370C6C2A# SE370C6C2A
4K -- --
-- 8K 8K
-- -- --
128 128 128
-- -- --
SCI2 SCI2 SCI2
T1 T1 T1
ADC2/4 ADC2/4 ADC2/4
22 22 22
4 or 1 4 4
28PLCC 28PLCC 28CLCC
The PACT module has a mini-SCI. SCI1 has a 3-pin configuration and SCI2 has a 2-pin configuration. The timer 1 module includes a watchdog timer that you can program to serve as a general-purpose 16-bit timer. The PACT module includes a watchdog timer. 8 channels for the ADC1 module in the 44-pin package, and 4 channels for the ADC1 module in the 40-pin package In ROMless (microprocessor) mode, all address, data, and control lines are fixed as to their functions. # For OTP (PLCC) availability information, contact your local TI sales office or distributor System evaluator (reprogrammable EPROM) for use in a prototype environment only. k TMS370Cx59 and TMS370Cx69 can only operate up to 3 MHz SYSCLK. h TMS370C45x has ROM security, which inhibits the reading of data using any programmer. 256-byte standby RAM is general-purpose memory and is powered separately by the VCCSTBY pin. The data stored in this memory is protected against power failure on the main VCC1 pins. @Refer to Table 19-1 on page 19-7 for package type acronyms. Uses the recommended TMS370C758 EPROM devices (requiring converter socket) for prototyping. Uses the recommended TMS370C758 EPROM devices for prototyping. Refer to the TMS370CxBx Data Sheet (P/N SPNS038) for pin-to-pin compatibility, which requires software modification. Note: Temperature ranges: ROM: A (-40 C to 85 C), L (0 C to 70 C), and T (-40 C to 105 C); EPROM and ROMless: T only.
Device Block Diagrams
1.7 Device Block Diagrams
This section contains functional block diagrams for each of the microcontroller device families. Each of these diagrams show the basic internal connections among the major architectural features summarized in Table 1-4. Refer to Chapter 2, TMS370 Family Pinouts and Pin Descriptions, for descriptions of the external connection names.
Figure 1-1. TMS370Cx0x Block Diagram
INT1 INT2 INT3 XTAL1 XTAL2/ CLKIN MC RESET
Interrupts
Clock options: divide-by-4 or divide-by-1 (PLL)
System control
CPU
RAM 256 bytes (usable as registers) Data EEPROM 0 or 256 bytes
SCI1
SCIRXD SCITXD SCICLK
Program memory ROM: 8K bytes EPROM: 8K bytes
Timer 1
T1IC/CR T1EVT T1PWM
Watchdog
VCC Port A 8 Port D VSS
II
Introduction to the TMS370 Family Devices
1-21
5
Device Block Diagrams
Figure 1-2. TMS370Cx1x Block Diagram
INT1 INT2 INT3 XTAL1 XTAL2/ CLKIN MC RESET
Interrupts
Clock options: divide-by-4 or divide-by-1 (PLL)
System control
SPI CPU RAM 128 or 256 bytes (usable as registers) Data EEPROM 0 or 256 bytes Timer 1
SPISOMI SPISIMO SPICLK
Program memory ROM: 2K, 4K, or 8K bytes EPROM: 8K bytes
T1IC/CR T1EVT T1PWM
Watchdog
VCC Port A Port D VSS
8
1-22
I I
5
I I
Device Block Diagrams
Figure 1-3. TMS370Cx2x Block Diagram
INT1 INT2 INT3 XTAL1 XTAL2/ CLKIN MC RESET
Interrupts
Clock options: divide-by-4 or divide-by-1 (PLL)
System control
CPU
RAM 256 bytes (usable as registers) SCI1
SCIRXD SCITXD SCICLK SPISOMI SPISIMO SPICLK T1IC/CR T1EVT T1PWM
Program memory ROM: 4K bytes or 8K bytes EPROM: 8K bytes
0 or 256 bytes data EEPROM
SPI
Timer 1
Watchdog VCC VSS Port A Port B Port C Port D
8
8
1
5
Introduction to the TMS370 Family Devices
1-23
Device Block Diagrams
Figure 1-4. TMS370Cx32 Block Diagram
INT1 INT2 INT3 XTAL1 XTAL2 / CLKIN MC RESET AN0-AN7
Interrupts
Clock options: divide-by-4 or divide-by-1 (PLL)
System control
ADC1
VCC3 VSS3
CP1
CP6 CPU RAM 256 bytes (usable as registers) PACT OP1 OP8 Program memory ROM: 8K bytes EPROM: 8K bytes Data EEPROM 0 or 256 bytes Mini SCI SCITXD SCIRXD
Watchdog
VCC1 VSS1 Port A Port D
8
4
NOTE: Three of port D's four I / O buffers (D4, D6, and D7) are internally connected to three of the PACT module's inputs (CP3, CP4, and CP5). The actual pins are D4 / CP3, D6 / CP4, and D7 / CP5.
1-24
Device Block Diagrams
Figure 1-5. TMS370Cx36 Block Diagram
INT1 XTAL2/ XTAL1 CLKIN MC RESET E0-E7 or AN0-AN7
Interrupts
Clock options: divide-by-4 or divide-by-1 (PLL)
System control
VCC3 ADC1 VSS3 SPISOMI SPISIMO SPICLK
SPI VCCSTBY Standby RAM 256 bytes Program memory ROM: 16K bytes EPROM: 16K bytes RAM 256 bytes (usable as registers) CPU
Port A 8 Note:
Four of port D's five I/O buffers (D4, D5, D6, and D7) are respectively connected internally to four of the PACT module's inputs (CP4, CP1, CP6, and CP5). The actual pins are D4/CP4, D5/CP1, D6/CP6, and D7/CP5.
AAAA A AAA AAAA IIIII IIIII
Data EEPROM 256 bytes 128 bytes dual port RAM Port D 5
. .
PACT
CP1 CP6
. .
Mini SCI Watchdog
OP1 OP8 SCITXD SCIRXD VCC1 V SS1
Introduction to the TMS370 Family Devices
1-25
Device Block Diagrams
Figure 1-6. TMS370Cx4x Block Diagram
INT1 INT2 INT3 XTAL2/ XTAL1 CLKIN MC RESET AN0-AN7
Interrupts
Clock options: divide-by-4 or divide-by-1 (PLL)
System control
VCC3 ADC1 (40-Pin: 4 CH 44-Pin: 8 CH) VSS3
CPU
RAM 256 bytes (usable as registers) SCI1
SCIRXD SCITXD SCICLK T2AIC1/CR T2AEVT T2AIC2/PWM T1IC/CR T1EVT T1PWM
Program memory ROM: 4K bytes or 8K bytes EPROM: 8K bytes
Data EEPROM 0 or 256 bytes
Timer 2A
Timer 1
Watchdog VCC VSS Port A 8 Port B 3 Port D 5
1-26
Device Block Diagrams
Figure 1-7. TMS370Cx5x Block Diagram
INT1 INT2 INT3 XTAL2/ XTAL1 CLKIN MC RESET E0 - E7 or AN0 - AN7
Interrupts
Clock options: divide-by-4 or divide-by-1 (PLL)
VCC3 System control ADC1 VSS3 SPISOMI SPISIMO SPICLK SCIRXD SCITXD SCICLK T2AIC1 / CR T2AEVT T2AIC2 / PWM T1IC / CR T1EVT T1PWM
CPU Program memory ROM: 4K, 8K, 12K, 16K, 32K, or 48K bytes EPROM: 16K, 32K, or 48K bytes
RAM 256, 512, 1K, 1.5K, or 3.5K bytes Data EEPROM 0, 256, or 512 bytes
SPI
SCI1
Timer 2A
Timer 1 Memory Expansion Address MSbyte Address LSbyte Watchdog Control Port D 8/6 VSS2 For the 64-pin devices, there are only six pins for port D. VCC2
Data
Port A 8
Port B 8
Port C 8
VCC1 VSS1
Introduction to the TMS370 Family Devices
1-27
Device Block Diagrams
Figure 1-8. TMS370Cx6x Block Diagram
INT1 INT2 XTAL2/ INT3 XTAL1 CLKIN MC RESET E0 - E7 or AN0 - AN7
Interrupts
Clock options: divide-by-4 or divide-by-1 (PLL)
VCC3 System control ADC1 VSS3 SPISOMI SPISIMO SPICLK SCIRXD SCITXD SCICLK T2BIC1 / CR T2BEVT T2BIC2 / PWM T2AIC1 / CR T2AEVT T2AIC2 / PWM T1IC / CR T1EVT T1PWM
SPI CPU Program memory ROM: 24K, 32K, or 48K bytes EPROM: 32K or 48K bytes RAM 1K or 3.5K bytes SCI1 Data EEPROM 256 bytes Timer 2B
Timer 2A Memory Expansion Address MSbyte Address LSbyte Timer 1 Control
Data
Watchdog
Port A 8
Port B 8
Port C 8
Port D 5 VSS2 VCC2
VCC1 VSS1
1-28
Device Block Diagrams
Figure 1-9. TMS370Cx7x Block Diagram
XTAL2/ INT3 XTAL1 CLKIN E0 - E7 or AN0 - AN7
INT1
INT2
MC
RESET
Interrupts
Clock options: divide-by-4 or divide-by-1 (PLL)
VCC3 System control ADC1 VSS3 T2AIC1 / CR T2AEVT T2AIC2 / PWM T1IC / CR T1EVT T1PWM
Timer 2A CPU RAM 512 bytes Timer 1 Program memory ROM: 24K bytes EPROM: 24K bytes Data EEPROM 256 bytes Watchdog
Port A 8
Port B 8
Port C 8
Port D 8/6
Port G 6 VSS2 VCC2
VCC1 VSS1
For the 64-pin devices, there are only six pins for port D.
Introduction to the TMS370 Family Devices
1-29
Device Block Diagrams
Figure 1-10. TMS370Cx8x Block Diagram
INT1 INT2 INT3 XTAL1 XTAL2/ CLKIN MC RESET
Interrupts
Clock options: divide-by-4 or divide-by-1 (PLL)
System control
CPU Program memory ROM: 4K bytes EPROM: 16K bytes
RAM 128 or 256 bytes (usable as registers) Data EEPROM 0 or 256 bytes Timer 1 T1IC/CR T1EVT T1PWM
Watchdog
VCC Port A Port B 8 Port C 8/6 Port D 5 VSS
For the 40-pin devices, there are only six pins for port C.
1-30
II
8
Device Block Diagrams
Figure 1-11.TMS370Cx9x Block Diagram
XTAL2/ XTAL1 CLKIN E0 - E7 or AN0 - AN7 AN8 - AN14
INT1
MC RESET
Interrupts
Clock options: divide-by-4 or divide-by-1 (PLL)
VCC3 System control ADC3 VSS3
CPU
RAM 128 bytes (usable as registers) Data EEPROM 256 bytes Timer 1
Program memory ROM: 4K bytes EPROM: 8K bytes
T1IC / CR T1EVT T1PWM
Watchdog
Port A 8
Port D 5
VCC VSS
Introduction to the TMS370 Family Devices
1-31
Device Block Diagrams
Figure 1-12. TMS370CxAx Block Diagram
INT1 INT2 XTAL2/ INT3 XTAL1 CLKIN MC RESET
Interrupts
Clock options: divide-by-4 or divide-by-1 (PLL)
System control SCIRXD SCITXD SCICLK T2AIC1 / CR T2AEVT T2AIC2 / PWM T1IC / CR T1EVT T1PWM
SCI1 RAM 512 bytes
CPU
Timer 2A
Program memory ROM: 24K bytes
Timer 1
Watchdog
Port A 8
Port B 8
Port C 1
Port D 5
1-32
Device Block Diagrams
Figure 1-13. TMS370CxBx Block Diagram
INT1 INT2 XTAL2/ INT3 XTAL1 CLKIN MC RESET E0 - E7 or AN0 - AN7
Interrupts
Clock options: System control divide-by-4 or divide-by-1(PLL)
VCC3 ADC1 VSS3
CPU
RAM 384 bytes Data EEPROM 256 bytes Timer 1 T1IC / CR T1EVT T1PWM
Program memory ROM: 16K bytes
Watchdog
VCC1 VSS1
Port A 8
Port B 8
Port C 8
Port D 8/6
Port G 8
Port H 1 VSS2 VCC2
For the 64-pin devices, there are only six pins for port D.
Introduction to the TMS370 Family Devices
1-33
Device Block Diagrams
Figure 1-14. TMS370CxCx Block Diagram
INT1 XTAL1 XTAL2/ CLKIN MC RESET E0 - E3 or AN0 - AN3
Interrupts
Clock options: divide-by-4 or divide-by-1 (PLL)
System control
ADC2
CPU
RAM 128 bytes (usable as registers)
SCI2
SCIRXD SCITXD
Program memory ROM: 4K bytes EPROM: 8K bytes Timer 1
T1IC/CR T1EVT T1PWM
Watchdog
VCC Port A 8 Port D 4 VSS
1-34
Running Title--Attribute Reference
Chapter 2
TMS370 Family Pinouts and Pin Descriptions
This chapter provides pinouts and pin descriptions for the individual device categories.
Topic
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9
Page
TMS370Cx0x Pinouts and Pin Descriptions . . . . . . . . . . . . . . . . . . . . . 2-2 TMS370Cx1x Pinouts and Pin Descriptions . . . . . . . . . . . . . . . . . . . . . 2-4 TMS370Cx2x Pinouts and Pin Descriptions . . . . . . . . . . . . . . . . . . . . . 2-6 TMS370Cx32 Pinout and Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . 2-8 TMS370Cx36 Pinouts and Pin Descriptions . . . . . . . . . . . . . . . . . . . . 2-11 TMS370Cx4x Pinouts and Pin Descriptions . . . . . . . . . . . . . . . . . . . . 2-14 TMS370Cx5x Pinouts and Pin Descriptions . . . . . . . . . . . . . . . . . . . . 2-16 TMS370Cx6x Pinouts and Pin Descriptions . . . . . . . . . . . . . . . . . . . . 2-20 TMS370Cx7x Pinouts and Pin Descriptions . . . . . . . . . . . . . . . . . . . . 2-24
2.10 TMS370Cx8x Pinouts and Pin Descriptions . . . . . . . . . . . . . . . . . . . . 2-27 2.11 TMS370Cx9x Pinouts and Pin Descriptions . . . . . . . . . . . . . . . . . . . . 2-30 2.12 TMS370CxAx Pinouts and Pin Descriptions . . . . . . . . . . . . . . . . . . . . 2-33 2.13 TMS370CxBx Pinouts and Pin Descriptions . . . . . . . . . . . . . . . . . . . . 2-35 2.14 TMS370CxCx Pinouts and Pin Descriptions . . . . . . . . . . . . . . . . . . . . 2-38
Chapter Title--Attribute Reference
2-1
TMS370Cx0x Pinouts and Pin Descriptions
2.1 TMS370Cx0x Pinouts and Pin Descriptions
The pinouts and pin descriptions for the TMS370Cx0x devices are shown in Figure 2-1 and in Table 2-1, respectively.
Figure 2-1. Pinouts for TMS370Cx0x
XTAL2 / CLKIN XTAL1 A6 A5 A4 A3 A2
5 6 7 8 9 10 11
V CC A7 D7 D6 D3 RESET D4 4 3 2 1 28 27 26 25 24 23 22 21 20 19 12 13 14 15 16 1718 V SS A1 A0 D5 INT1 INT2 INT3 SCITXD SCICLK SCIRXD T1IC / CR T1PWM T1EVT MC
A. 28-Pin PLCC (FN) B. 28-Pin CLCC (FZ)
2-2
TMS370Cx0x Pinouts and Pin Descriptions
Table 2-1. TMS370Cx0x Pin Descriptions
AAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAA A AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA A A A AA A AAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA A A A AA A AAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA A A A AA A AAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA A A A AA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A
28-Pin LCC Name A0 A1 A2 A3 A4 A5 A6 A7 No. 14 13 11 10 9 8 7 3 28 26 15 1 2 16 17 18 22 21 20 25 23 24 27 I / O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Description Port A is a general-purpose bidirectional I / O port. D3 D4 D5 D6 D7 Port D is a general-purpose bidirectional I / O port. D3 is also configurable as SYSCLK. INT1 INT2 INT3 I I/O I/O External (non-maskable or maskable) interrupt/general-purpose input pin. External maskable interrupt input / general-purpose bidirectional pin. External maskable interrupt input / general-purpose bidirectional pin. T1IC / CR T1PWM T1EVT SCITXD SCIRXD SCICLK RESET I/O I/O I/O I/O I/O I/O I/O Timer1 input capture / counter reset input pin / general-purpose bidirectional pin. Timer1 PWM output pin / general-purpose bidirectional pin. Timer1 external event input pin / general-purpose bidirectional pin. SCI transmit data output pin, general-purpose bidirectional pin (see Note). SCI receive data input pin / general-purpose bidirectional pin. SCI bidirectional serial clock pin / general-purpose bidirectional pin. System reset bidirectional pin; as input pin, RESET initializes the microcontroller; as open-drain output, RESET indicates that an internal failure was detected by watchdog or oscillator fault circuit. Mode control input pin; enables EEPROM write protection override (WPO) mode, also supplies EPROM VPP . Internal oscillator crystal input / External clock source input. Internal oscillator output for crystal. Positive supply voltage MC 19 5 6 4 I XTAL2 / CLKIN XTAL1 VCC I O VSS 12 Ground reference I = input, O = output Note: The three-pin SCI configuration is referred to as SCI1.
TMS370 Family Pinouts and Pin Descriptions
2-3
TMS370Cx1x Pinouts and Pin Descriptions
2.2 TMS370Cx1x Pinouts and Pin Descriptions
The pinouts and pin descriptions for the TMS370Cx1x devices are shown in Figure 2-2 and in Table 2-2, respectively.
Figure 2-2. Pinouts for TMS370Cx1x
RESET D4 SPISOM SPICLK SPISIM T1IC/C T1PWM T1EVT MC 24 23 22 21 INT2 INT3
D6 D7 A7 V CC XTAL2/CLKIN XTAL1 A6 A5 A4 A3 A2 VSS A1 A0
D7 A0
D6 D5
2 3 4 5 6 7 8 9 10 11 12 13 14
27 26 25 24 23 22 21 20 19 18 17 16 15
RESET D4 SPISOMI SPICLK SPISIMO T1IC/CR T1PWM T1EVT MC INT3 INT2 INT1 D5 XTAL2/CLKIN XTAL1 A6 A5 A4 5 6 7 8 9
4
3
2 1 28 27 26 25
20 A3 10 19 11 A2 12 13 14 15 16 17 18 V SS INT1 A1
A. 28-Pin PDIP (N) B. 28-Pin CDIP (JD)
C. 28-Pin PLCC (FN) D. 28-Pin CLCC (FZ)
2-4
D3
A7
1
28
D3
V CC
TMS370Cx1x Pinouts and Pin Descriptions
Table 2-2. TMS370Cx1x Pin Descriptions
28-Pin DIP/LCC Name A0 A1 A2 A3 A4 A5 A6 A7 D3 D4 D5 D6 D7 INT1 INT2 INT3 T1IC/CR T1PWM T1EVT SPISOMI SPISIMO SPICLK RESET No. 14 13 11 10 9 8 7 3 28 26 15 1 2 16 17 18 22 21 20 25 23 24 27 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I/O I/O I/O I/O I/O I/O I/O I/O I/O Description Port A is a general-purpose bidirectional I/O port
Port D is a general-purpose bidirectional I/O port; D3 is also configurable as SYSCLK
External (nonmaskable or maskable) interrupt/general-purpose input pin External maskable interrupt input/general-purpose bidirectional pin External maskable interrupt input/general-purpose bidirectional pin Timer 1 input capture/counter reset input pin/general-purpose bidirectional pin Timer 1 PWM output pin/general-purpose bidirectional pin Timer 1 external event input pin/general-purpose bidirectional pin SPI slave output pin, master input pin/general-purpose bidirectional pin SPI slave input pin, master output pin/general-purpose bidirectional pin SPI bidirectional serial clock pin/general-purpose bidirectional pin System reset bidirectional pin; as an input, RESET initializes the microcontroller; as an open-drain output, RESET indicates that an internal failure was detected by the watchdog or oscillator fault circuit Mode control input pin; enables EEPROM write protection override (WPO) mode, and also supplies EPROM Vpp. Internal oscillator crystal input/external clock source input Internal oscillator output for crystal Positive supply voltage Ground reference
MC XTAL2/CLKIN XTAL1 VCC VSS
19 5 6 4 12
I I O
I = input, O = output
TMS370 Family Pinouts and Pin Descriptions
2-5
TMS370Cx2x Pinouts and Pin Descriptions
2.3 TMS370Cx2x Pinouts and Pin Descriptions
The pinouts and pin descriptions for the TMS370Cx2x devices are shown in Figure 2-3 and Table 2-3, respectively.
Figure 2-3. Pinouts for TMS370Cx2x
B2 B3 B4 C0 RESET INT1 INT2 INT3 VCC A7 A6 VSS A5 A4 A3 A2 A1 A0 D7 D4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 B1 B0 SCITXD SCIRXD SCICLK D5 MC XTAL2/CLKIN XTAL1 T1IC/CR T1PWM T1EVT SPISOMI SPISIMO SPICLK B7 B6 B5 D6 D3 RESET C0 B4 B3 B2 B1 B0 SCITXD SCIRXD SCICLK D5 6 5 4 3 2 1 44 43 42 41 40 39 7 38 8 37 9 36 10 35 11 34 12 33 13 32 14 31 15 30 16 29 17 18 19 20 21 22 23 24 25 26 27 28 A2 A1 A0 D7 D4 D3 D6 NC B5 B6 B7
INT1 INT2 INT3 VCC NC A7 A6 VSS A5 A4 A3
MC XTAL2/CLKIN XTAL1 T1IC/CR T1PWM T1EVT NC SPISOMI SPISIMO SPICLK NC
A. 40-Pin PDIP (N) B. 40-Pin CDIP (JD) C. 40-Pin PSDIP (NJ) D. 40-Pin CSDIP (JC)
E. 44-Pin PLCC (FN) F. 44-Pin CLCC (FZ)
The NJ designator for the 40-pin plastic shrink DIP package was formerly known as N2.
The mechanical drawing of the NJ is identical to the N2 package and did not need to be requalified.
2-6
TMS370Cx2x Pinouts and Pin Descriptions
Table 2-3. TMS370Cx2x Pin Descriptions
Pin Pin No. DIP / LCC 40 44 18 17 16 15 14 13 11 10 39 40 1 2 3 23 24 25 4 21 20 35 22 19 38 37 36 6 7 8 31 30 29 28 27 26 5 20 19 18 17 16 15 13 12 44 1 2 3 4 26 27 28 5 23 22 40 24 21 43 42 41 7 8 9 36 35 34 32 31 30 6
Name A0 A1 A2 A3 A4 A5 A6 A7 B0 B1 B2 B3 B4 B5 B6 B7 C0 D3 D4 D5 D6 D7 SCITXD SCIRXD SCICLK INT1 INT2 INT3 T1IC/CR T1PWM T1EVT SPISOMI SPISIMO SPICLK RESET
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I/O I/O I/O I/O I/O I/O I/O I/O I/O
Description Port A is a general-purpose bidirectional I/O port
Port B is a general-purpose bidirectional I/O port
Port C is a general-purpose bidirectional I/O port Port D is a general-purpose bidirectional I/O port; D3 is also configurable as a SYSCLK
SCI transmit data output pin/general-purpose bidirectional pin (see Note) SCI receive data input pin/general-purpose bidirectional pin SCI bidirectional serial clock pin/general-purpose bidirectional pin External (nonmaskable or maskable) interrupt/general-purpose input pin External maskable interrupt input/general-purpose bidirectional pin External maskable interrupt input/general-purpose bidirectional pin Timer 1 input capture/counter reset input pin/general-purpose bidirectional pin Timer 1 PWM output pin/general-purpose bidirectional pin Timer 1 external event input pin/general-purpose bidirectional pin SPI slave output pin, master input pin/general-purpose bidirectional pin SPI slave input pin, master output pin/general-purpose bidirectional pin SPI bidirectional serial clock pin/general-purpose bidirectional pin System reset bidirectional pin; as an input, RESET initializes the microcontroller; as an open-drain output, RESET indicates an internal failure was detected by the watchdog or oscillator fault circuit Mode control input pin; enables the EEPROM write-protection override (WPO) mode, and also supplies EPROM Vpp. Internal oscillator output for crystal Internal oscillator crystal input/external clock source input No connections
MC XTAL1 XTAL2/CLKIN NC
34 32 33 - - - - 9 12
39 37 38 11 25 29 33 10 14
I O I
VCC VSS
Positive supply voltage Ground reference
I = input, O = output Note: The three-pin SCI configuration is referred to as SCI1.
TMS370 Family Pinouts and Pin Descriptions
2-7
TMS370Cx32 Pinouts and Pin Descriptions
2.4 TMS370Cx32 Pinouts and Pin Descriptions
The pinout and pin descriptions for the TMS370Cx32 devices are shown in Figure 2-4 and Table 2-4, respectively.
Figure 2-4. Pinout for TMS370Cx32
RESET OP8 OP7 OP6 OP5 OP4 OP3 OP2 OP1 SCITXD CP1 7 8 9 10 11 12 6 5 4 3 2 1 44 43 42 41 40
INT1 INT2 INT3 VCC1 VCC3 A7 A6 VSS1 A5 A4 A3
13 14
15 16 17 18 19 20 21 22 23 24 25 26 27 28
39 38 37 36 35 34 33 32 31 30 29
MC XTAL2/CLKIN XTAL1 CP2 SCIRXD CP6 AN7 AN6 AN5 AN4 VSS3
2-8
A2 A1 A0 D7/CP5 D4/CP3 D3 D6/CP4 AN0 AN1 AN2 AN3
A. 44-Pin PLCC (FN) B. 44-Pin CLCC (FZ)
TMS370Cx32 Pinouts and Pin Descriptions
Table 2-4. TMS370x32 Pin Descriptions
44-Pin LCC Name A0 A1 A2 A3 A4 A5 A6 A7 D3 D4/CP3 D6/CP4 D7/CP5 INT1 INT2 INT3 CP1 CP2 CP6 SCITXD SCIRXD OP1 OP2 OP3 OP4 OP5 OP6 OP7 OP8 AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 RESET No. 20 19 18 17 16 15 13 12 23 22 24 21 7 8 9 40 36 34 41 35 42 43 44 1 2 3 4 5 25 26 27 28 30 31 32 33 6 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I/O I/O I I I O I O O O O O O O O I I I I I I I I I/O Description Port A is a general-purpose bidirectional port
Port D is a general-purpose bidirectional port I/O pin: Also configurable as SYSCLK I/O pin: PACT input capture 3. I/O pin: PACT input capture 4. I/O pin: PACT input capture 5. External (nonmaskable or maskable) interrupt/general-purpose input pin External maskable interrupt input/general-purpose bidirectional pin External maskable interrupt input/general-purpose bidirectional pin PACT input capture pin 1 PACT input capture pin 2 PACT input capture pin 6; external event input pin (for event counter) PACT mini SCI transmit output pin PACT mini SCI receive input pin PACT output pin 1 PACT output pin 2 PACT output pin 3 PACT output pin 4 PACT output pin 5 PACT output pin 6 PACT output pin 7 PACT output pin 8 ADC1 analog input (AN0-AN7) or positive reference pins (AN1-AN7)
The analog port can be individually programmed as general-purpose input pins if it is not used as ADC1 converter analog input or positive reference input
System reset bidirectional pin; as input, RESET initializes the microcontroller; as an open-drain output, RESET indicates that an internal failure was detected by the watchdog or oscillator fault circuit Mode control input pin; enables EEPROM write-protection override (WPO) mode, and also supplies EPROM Vpp. Internal oscillator crystal input/external clock source input y Internal oscillator output for crystal
MC XTAL2/CLKIN XTAL1
39 38 37
I I O
Some of port D's digital I/O buffers are internally connected to some of the PACT module's input capture pins. This allows the microcontroller to read the level on the input capture pin or, if the port D pin is configured as an output, to generate a capture. Be careful to leave the port D pin configured as an input if the corresponding input capture pin is being driven by external circuitry. I = input, O = output
TMS370 Family Pinouts and Pin Descriptions
2-9
TMS370Cx32 Pinouts and Pin Descriptions
Table 2-4. TMS370x32 Pin Descriptions (Continued)
44-Pin LCC Name No. I/O Description VCC1 10 Positive supply voltage for digital logic and digital I/O pins VSS1 14 Ground reference for digital logic and digital I/O pins VCC3 11 ADC1 converter positive supply voltage and optional positive reference input VSS3 29 ADC1 converter ground supply and low reference input pin Some of port D's digital I/O buffers are internally connected to some of the PACT module's input capture pins. This allows the microcontroller to read the level on the input capture pin or, if the port D pin is configured as an output, to generate a capture. Be careful to leave the port D pin configured as an input if the corresponding input capture pin is being driven by external circuitry. I = input, O = output
2-10
TMS370Cx36 Pinouts and Pin Descriptions
2.5 TMS370Cx36 Pinout and Pin Descriptions
The pinout and pin descriptions for the TMS370Cx36 device family are shown in Figure 2-5 and Table 2-5, respectively.
Figure 2-5. Pinout for TMS370Cx36
AN3 AN4 AN5 AN6 AN7 D6/CP6 D7/CP5 D4/CP4 D5/CP1 OP1/CP3 OP2/CP2
AN2 AN1 AN0 VSS3 VCC3 VCC1 XTAL1 XTAL2/CLKIN V CCSTBY A7 A6
6543 2
7 8 9 10 111 21 31 41 51 61 7
1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30
29 18 19 20 21 22 23 24 25 26 27 28
A5 A4 A3 A2 A1 A0 MC RESET SPICLK SPISOMI SPISIMO
V SS1 SCIRXD SCITXD OP3 OP4 OP5 OP6 OP7 OP8 D3 INT1
A. 44-Pin PLCC (FN) B. 44-Pin CLCC (FZ)
TMS370 Family Pinouts and Pin Descriptions
2-11
TMS370Cx36 Pinouts and Pin Descriptions
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Table 2-5. TMS370Cx36 Pin Descriptions
44-Pin LCC Name A0 A1 A2 A3 A4 A5 A6 A7 No. 34 35 36 37 38 39 40 41 27 14 15 12 13 I / O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I I I I I I I Description Port A is a general-purpose bidirectional I / O port. D3 D4/CP4 D5/CP1 D6/CP6 D7/CP5 AN0/E0 AN1/E1 AN2/E2 AN3/E3 AN4/E4 AN5/E5 AN6/E6 AN7/E7 INT1 Port D is a general-purpose bidirectional port. Also configurable as SYSCLK (Note 1). PACT input capture 4 (Note 2). PACT input capture 1 (Note 2). PACT input capture 6 (Note 2). PACT input capture 5 (Note 2). ADC1 analog input pins (AN0 - AN7) / port E digital input pins (E0 - E7). 4 5 6 7 8 9 10 11 Port E can be programmed individually as a general-purpose digital input pin if it is not used as ADC1 analog input or positive reference input. 28 16 17 21 22 23 24 25 26 19 20 30 29 31 External (non-maskable or maskable) interrupt/general-purpose input pin PACT PWM output 1/input capture 3 (Note 3). PACT output pin 2/input capture 2 (Note 3). PACT PWM output 3 PACT PWM output 4 PACT PWM output 5 PACT PWM output 6 PACT PWM output 7 PACT PWM output 8 PACT mini SCI data receive input pin PACT mini SCI data transmit output pin OP1/CP3 OP2/CP2 OP3 OP4 OP5 OP6 OP7 OP8 SCIRXD SCITXD O O O O O O O O I O SPISOMI SPISIMO SPICLK I/O SPI slave output pin, master input pin / general-purpose bidirectional pin SPI slave input pin, master output pin / general-purpose bidirectional pin SPI bidirectional serial clock pin / general-purpose bidirectional pin I = input, O = output NOTES: 1. D3 can be configured as SYSCLK by appropriately programming the DPORT1 and DPORT2 registers. 2. These digital I/O buffers are connected internally to some of the PACT module's input capture pins. This allows the microcontroller to read the level on the input capture pin, or if the port D pin is configured as an output, to generate a capture. Be careful to leave the port D pin configured as an input if the corresponding input capture pin is being driven by external circuitry. 3. CP2 and CP3 are connected internally to OP2 and OP1. CP2 and CP3 can be used only to capture, respectively, OP2 and OP1, and not as external capture inputs.
2-12
TMS370Cx36 Pinouts and Pin Descriptions
Table 2-5 TMS370Cx36 Pin Descriptions (Continued)
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA A A AAA AA A AAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA A A AAA A AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA A AAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAA AAAAAA
44-Pin LCC Name No. 32 I / O I/O Description RESET System reset bidirectional pin; as input pin, RESET initializes the microcontroller; as open-drain output, RESET indicates that an internal failure was detected by the watchdog or oscillator fault circuit. MC 33 43 44 I Mode control input pin; enables EEPROM write protection override (WPO) mode, and also supplies EPROM Vpp. Internal oscillator crystal output/external clock source input Internal oscillator output for crystal XTAL2/CLKIN XTAL1 VCC1 VSS1 VCC3 VSS3 VCCSTBY I O 1 18 2 3 42 Positive supply voltage for digital logic and digital I/O pins Ground reference for digital logic and digital I/O pins ADC1 positive supply voltage and optional positive reference input ADC1 ground supply and low reference input pin Positive supply voltage pin for standby RAM I = input, O = output NOTES: 4. D3 can be configured as SYSCLK by appropriately programming the DPORT1 and DPORT2 registers. 5. These digital I/O buffers are connected internally to some of the PACT module's input capture pins. This allows the microcontroller to read the level on the input capture pin, or if the port D pin is configured as an output, to generate a capture. Be careful to leave the port D pin configured as an input if the corresponding input capture pin is being driven by external circuitry. 6. CP2 and CP3 are connected internally to OP2 and OP1. CP2 and CP3 can be used only to capture, respectively, OP2 and OP1, and not as external capture inputs.
TMS370 Family Pinouts and Pin Descriptions
2-13
TMS370Cx4x Pinouts and Pin Descriptions
2.6 TMS370Cx4x Pinouts and Pin Descriptions
The pinouts and pin descriptions for the TMS370Cx4x devices are shown in Figure 2-6 and Table 2-6, respectively.
Figure 2-6. Pinouts for TMS370Cx4x
RESET T2AIC1/CR T2AIC2/PWM T2AEVT B2 B1 B0 SCITXD SCIRXD SCICLK D5 6 5 4 3 2 1 44 43 42 41 40 39 7 38 8 37 9 36 10 35 11 34 12 33 13 32 14 31 15 30 16 29 17 18 19 20 21 22 23 24 25 26 27 28 A2 A1 A0 D7 D4 D3 D6 AN0 AN1 AN2 AN3
B2 T2AEVT T2AIC2/PWM T2AIC1/CR RESET INT1 INT2 INT3 VCC A7 A6 VSS A5 A4 A3 A2 A1 A0 D7 D4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
B1 B0 SCITXD SCIRXD SCICLK D5 MC XTAL2/CLKIN XTAL1 T1IC/CR T1PWM T1EVT AN7 AN6 VCC3 VSS3 AN3 AN2 D6 D3
INT1 INT2 INT3 VCC VCC3 A7 A6 VSS A5 A4 A3
MC XTAL2/CLKIN XTAL1 T1IC/CR T1PWM T1EVT AN7 AN6 AN5 AN4 VSS3
A. 40-Pin PDIP (N) B. 40-Pin CDIP (JD) C. 40-Pin PSDIP (NJ) D. 40-Pin CSDIP (JC)
E. 44-Pin PLCC (FN) F. 44-Pin CLCC (FZ)
The NJ designator for the 40-pin plastic shrink DIP package was formerly known as N2. The
mechanical drawing of the NJ is identical to the N2 package and did not need to be requalified.
2-14
TMS370Cx4x Pinouts and Pin Descriptions
Table 2-6. TMS370Cx4x Pin Descriptions
Pin Name A0 A1 A2 A3 A4 A5 A6 A7 B0 B1 B2 D3 D4 D5 D6 D7 AN0/E0 AN1/E1 AN2/E2 AN3/E3 AN4/E4 AN5/E5 AN6/E6 AN7/E7 VCC3 VSS3 INT1 INT2 INT3 T1IC/CR T1PWM T1EVT T2AIC1/CR T2AIC2/PWM T2AEVT SCITXD SCIRXD SCICLK RESET DIP (40) 18 17 16 15 14 13 11 10 39 40 1 21 20 35 22 19 -- -- 23 24 -- -- 27 28 26 25 6 7 8 31 30 29 4 3 2 38 37 36 5 LCC (44) 20 19 18 17 16 15 13 12 44 1 2 23 22 40 24 21 25 26 27 28 30 31 32 33 11 29 7 8 9 36 35 34 5 4 3 43 42 41 6 I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I I I I I I Description Port A is a general-purpose bidirectional I/O port
Port B is a general-purpose bidirectional I/O port
Port D is a general-purpose bidirectional I/O port; D3 is also configurable as a SYSCLK
ADC1 analog input channels or positive reference pins; any ADC1 channel can be programmed as general-purpose input pins (E port) if not used as an analog input or reference channel
ADC1 converter positive supply voltage and optional positive reference input pin ADC1 converter ground supply and low reference input pin External (nonmaskable or maskable) interrupt/general-purpose input pin External maskable interrupt input/general-purpose bidirectional pin External maskable interrupt input/general-purpose bidirectional pin Timer 1 input capture/counter reset input pin/general-purpose bidirectional pin Timer 1 PWM output pin/general-purpose bidirectional pin Timer 1 external event input pin/general-purpose bidirectional pin Timer 2A input capture/counter reset input pin/general-purpose bidirectional pin Timer 2A input capture 2/PWM output pin/general-purpose bidirectional pin Timer 2A external event Input pin/general-purpose bidirectional pin SCI transmit data output pin/general-purpose bidirectional pin (see Note) SCI receive data input pin/general-purpose bidirectional pin SCI bidirectional serial clock pin/general-purpose bidirectional pin System reset bidirectional pin; as input, RESET initializes the microcontroller; as an open-drain output, RESET indicates that an internal failure was detected by the watchdog or oscillator fault circuit Mode control input pin; enables the EEPROM write protection override (WPO) mode, and also supplies EPROM Vpp. Internal oscillator output for crystal Internal oscillator crystal input/external clock source input Positive supply voltage Ground reference
MC XTAL1 XTAL2/CLKIN VCC VSS
34 32 33 9 12
39 37 38 10 14
I I O
I = input, O = output Note: The three-pin SCI configuration is referred to as SCI1.
TMS370 Family Pinouts and Pin Descriptions
2-15
TMS370Cx5x Pinouts and Pin Descriptions
2.7 TMS370Cx5x Pinouts and Pin Descriptions
The pinout and pin descriptions for the TMS370Cx5x devices are shown in Figure 2-7 and Table 2-7, respectively.
Figure 2-7. Pinouts for TMS370Cx5x
B5 B6 B7 C0 MC C1 C2 VSS1 D1/CSH3 D2/CSH2 D3/SYSCLK D4/R/W D5/CSPF D6/CSH1/EDS D7/CSE1/WAIT RESET INT1 INT2 INT3 SPISOMI SPISIMO SPICLK T1IC/CR T1PWM T1EVT C3 C4 C5 C6 C7 AN0 A0 A1 A2 A3 A4 A5 A6 A7 T2AEVT T2AIC2/PWM T2AIC1/CR SCICLK SCIRXD SCITXD XTAL2/CLKIN XTAL1 VCC1 VCC3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
D0/CSE2/OCF V CC2 V SS2 V CC1
B4 B3 B2 B1 B0 D0/CSE2/OCF VSS1 VCC1 D1/CSH3 D3/SYSCLK D4/R/W D6/CSH1/EDS D7/CSE1/WAIT RESET INT1 INT2 INT3 SPISOMI SPISIMO SPICLK T1IC/CR T1PWM AN7 T1EVT VSS1 AN6 AN5 AN4 AN3 AN2 AN1 VSS3
V SS1
C2 C1 MC C0
B7 B6 B5 B4
4 3 2
9
8
7
6
5
1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45
C3 C4 C5 C6 C7 VCC2 VSS2 A0 A1 A2 A3 A4 A5 A6 A7 T2AEVT T2AIC2/PWM
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
XTAL1 V CC1 V CC3 V SS3
AN0 AN1 AN2 AN3
B3 B2 B1 B0
SCICLK SCIRXD SCITXD XTAL2/CLKIN
T2AIC1/CR
A. 68-Pin PLCC (FN) B. 68-Pin CLCC (FZ)
AN4 AN5 AN6 AN7
C. 64-Pin PSDIP (NM) D. 64-Pin CSDIP (JN)
2-16
TMS370Cx5x Pinouts and Pin Descriptions
Table 2-7. TMS370Cx5x Pin Descriptions
Pin Name A0 A1 A2 A3 A4 A5 A6 A7 B0 B1 B2 B3 B4 B5 B6 B7 C0 C1 C2 C3 C4 C5 C6 C7 INT1 INT2 INT3 I = input, O = output Alternate Function DATA0 (LSB) DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 (MSB) ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 NMI - - DIP (64) 15 16 17 18 19 20 21 22 60 61 62 63 64 1 2 3 4 6 7 9 10 11 12 13 50 49 48 LCC (68) 17 18 19 20 21 22 23 24 65 66 67 68 1 2 3 4 5 7 8 10 11 12 13 14 52 51 50 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I/O I/O Description Single-chip mode: port A is a general-purpose bidirectional port Expansion mode: port A can be individually programmed as the external bidirectional data bus (DATA0-DATA7)
Single-chip mode: port B is a general-purpose bidirectional I/O port Expansion modes: port B can be individually programmed as the low-order address output bus (ADDR0-ADDR7)
Single-chip mode: port C is a general-purpose bidirectional I/O port Expansion mode: port C can be individually programmed as the high-order address output bus (ADDR8-ADDR15)
External (nonmaskable or maskable) interrupt/general-purpose input pin External maskable interrupt input/general-purpose bidirectional pin External maskable interrupt input/general-purpose bidirectional pin
TMS370 Family Pinouts and Pin Descriptions
2-17
TMS370Cx5x Pinouts and Pin Descriptions
Table 2-7. TMS370Cx5x Pin Descriptions (Continued)
Pin Name Alternate Function DIP (64) LCC (68) I/O Description Single-chip mode: port D is a general-purpose bidirectional I/O port. Each of the port D pins can be individually configured as a general-purpose I/O pin, primary memory control signal (function A), or secondary memory control signal ( (function ( ) y y g B). All chip selects are independent and can be used for memory bank switching. 59 56 -- 55 54 -- 53 64 60 59 58 57 56 55 I/O I/O I/O I/O I/O I/O I/O I/O pin/A: chip-select eighth output 2 goes low during memory accesses. I/O pin/B: Opcode fetch goes low during the opcode fetch memory cycle I/O pin/A: chip-select half output 3 goes low during memory accesses. I/O pin/B: reserved. I/O pin/A: chip-select half output 2 goes low during memory accesses. I/O pin/B: reserved. I/O pin/A, B: internal clock signal is 1/1 (PLL) or 1/4 XTAL2/CLKIN frequency. I/O pin/A, B: read/write output pin I/O pin/A: chip-select peripheral output for peripheral file goes low during memory accesses. I/O pin/B: reserved. I/O pin/A: chip-select half output 1 goes low during memory accesses. I/O pin/B: external data strobe output goes low during memory accesses from external memory and has the same timings as the five chip selects. I/O pin/A: chip-select eighth output goes low during memory accesses. I/O pin/B: wait input pin extends bus signals Timer 1 input capture/counter reset input pin/general-purpose bidirectional pin Timer 1 PWM output pin/general-purpose bidirectional pin Timer 1 external event input pin/general-purpose bidirectional pin Timer 2A input capture 1/counter reset input pin/generalpurpose bidirectional pin Timer 2A input capture 2/PWM output pin/general-purpose bidirectional pin Timer 2A external event input pin/general-purpose bidirectional pin SPI slave output pin, master input pin/general-purpose bidirectional pin SPI slave input pin, master output pin/general-purpose bidirectional pin SPI bidirectional serial clock pin/general-purpose bidirectional pin
Function
A D0 D1 D2 D3 D4 D5 D6 CSE2 CSH3 CSH2 SYSCLK R/W CSPF CSH1
B OCF -- -- SYSCLK R/W -- EDS
D7
CSE1
WAIT
52
54
I/O
T1IC/CR T1PWM T1EVT T2AIC1/CR T2AIC2/PWM T2AEVT SPISOMI SPISIMO SPICLK
T1IO1 T1IO2 T1IO3 T2IO1 T2IO2 T2IO3 SPIIO1 SPIIO2 SPIIO3
44 43 41 25 24 23 47 46 45
46 45 44 27 26 25 49 48 47
I/O I/O I/O I/O I/O I/O I/O I/O I/O
I = input, O = output Port D3 can be configured as SYSCLK
2-18
TMS370Cx5x Pinouts and Pin Descriptions
Table 2-7. TMS370Cx5x Pin Descriptions (Continued)
Pin Name SCITXD SCIRXD SCICLK AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 VCC3 VSS3 RESET Alternate Function SCIIO1 SCIIO2 SCIIO3 E0 E1 E2 E3 E4 E5 E6 E7 DIP (64)6 28 27 26 14 34 35 36 37 38 39 42 32 33 51 LCC (68) 30 29 28 36 37 38 39 40 41 42 43 34 35 53 I/O I/O I/O I/O I/O I I I I I I I I Description SCI transmit data output pin/general-purpose bidirectional pin (see Note) SCI receive data input pin/general-purpose bidirectional pin SCI bidirectional serial clock pin/general-purpose bidirectional pin ADC1 analog input (AN0-AN7) or positive reference pins (AN1-AN7) Port E can be individually programmed as generalpurpose input pins if not used as ADC1 analog input or positive reference input
ADC1 positive supply voltage and optional positive reference input pin ADC1 ground supply and low reference input pin System reset bidirectional pin; as an input, RESET initializes microcontroller; as open-drain output, RESET indicates an internal failure was detected by the watchdog or oscillator fault circuit Mode control pin; enables EEPROM write protection override (WPO) mode, and also supplies EPROM Vpp. Internal oscillator crystal input/external clock source in ut input Internal oscillator output for crystal Positive supply voltage Positive supply voltage for digital I/O logic Ground reference for digital logic Ground reference for digital I/O pins
MC XTAL2/CLKIN XTAL1 VCC1 VCC2 VSS1 VSS2
5 29 30 31, 57 -- 8, 58 --
6 31 32 33, 61 15, 63 9 16, 62
I I O
I = input, O = output Note: The three-pin SCI configuration is referred to as SCI1.
TMS370 Family Pinouts and Pin Descriptions
2-19
TMS370Cx6x Pinouts and Pin Descriptions
2.8 TMS370Cx6x Pinouts and Pin Descriptions
The pinout and pin descriptions for the TMS370Cx6x devices are shown in Figure 2-8 and Table 2-8, respectively.
Figure 2-8. Pinouts for TMS370Cx6x
T2BIC1/CR
V CC2
9 C3 C4 C5 C6 C7 VCC2 VSS2 A0 A1 A2 A3 A4 A5 A6 A7 T2AEVT T2AIC2/PWM 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
8
7
6
5
4
B6
3
2
1
68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 T2BIC2 / PWM T2BEVT D3 / SYSCLK D4 / R / W D5 / CSPF D6/CSH1/EDS D7/CSE1/WAIT RESET INT1 INT2 INT3 SPISOMI SPISIMO SPICLK T1IC/CR T1PWM T1EVT
44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 V CC1 XTAL2/CLKIN T2AIC1/CR SCICLK XTAL1 V CC3 V SS3 AN0 AN1 AN2 AN3 AN4 AN5 AN6 SCIRXD SCITXD AN7
A. 68-Pin PLCC (FN) B. 68-Pin CLCC (FZ)
2-20
V CC1
V SS1
V SS2
MC
C2
C1
C0
B7
B5 B4
B3
B2
B1
B0
TMS370Cx6x Pinouts and Pin Descriptions
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Table 2-8. TMS370Cx6x Pin Descriptions
Pin Name A0 A1 A2 A3 A4 A5 A6 A7 B0 B1 B2 B3 B4 B5 B6 B7 Alternate Function DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 LCC (68) 17 18 19 20 21 22 23 24 65 66 67 68 1 2 3 4 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Description Single-chip mode: Port A is a general-purpose bidirectional I/O port. Expansion mode: Port A can be individually programmed as the external bidirectional data bus (DATA0 - DATA7). ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 Single-chip mode: Port B is a general-purpose bidirectional I/O port. Expansion mode: Port B can be individually programmed as the low-order address output bus (ADDR0 - ADDR7). C0 C1 C2 C3 C4 C5 C6 C7 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 NMI -- -- E0 E1 E2 E3 E4 E5 E6 E7 5 7 8 10 11 12 13 14 Single-chip mode: Port C is a general-purpose bidirectional I/O port. Expansion mode: Port C can be individually programmed as the high-order address output bus (ADDR8 - ADDR15). INT1 INT2 INT3 AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 52 51 50 36 37 38 39 40 41 42 43 34 35 53 I I/O I/O I I I I I I I I External (nonmaskable or maskable) interrupt/general-purpose input pin External maskable interrupt input/general-purpose bidirectional pin External maskable interrupt input/general-purpose bidirectional pin A DC1 analog input (AN0 - AN7) or positive reference pins (AN1 - AN7) Port E can be individually programmed as general-purpose input pins if not used as A DC1 converter analog input or positive reference input. VCC3 VSS3 A DC1 positive-supply voltage and optional positive-reference input pin A DC1 ground reference pin RESET I/O System reset bidirectional pin. RESET, as an input, initializes the microcontroller; as open-drain output, RESET indicates an internal failure was detected by the watchdog or oscillator fault circuit. I = input, O = output Ports A, B, C, and D can be configured only as general-purpose I/O pins. Also, port D3 can be configured as SYSCLK. Note: The three-pin SCI configuration is referred to as SCI1.
TMS370 Family Pinouts and Pin Descriptions
2-21
TMS370Cx6x Pinouts and Pin Descriptions
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAA A AAAAAAAAAAAAAA AAAAA A AAA A AAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA A A AAA AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAAAAAAAAAAAAAAAA A A A A A AAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAA AAA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAAA A AAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA A A A A AAAA A AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAA A A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA A A A A A AAAA A AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAA A AAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Table 2-8. TMS370Cx6x Pin Descriptions (Continued)
Pin Name Alternate Function LCC (68) 31 32 6 I/O I O I Description XTAL2/CLKIN XTAL1 MC Internal oscillator crystal input / external clock source input Internal oscillator output for crystal Mode control (MC) pin. MC enables EEPROM write-protection override (WPO) mode, and also supplies EPROM VPP. Positive supply voltage VCC1 VCC2 VSS1 VSS2 33,61 15,63 9 Positive supply voltage for digital I/O logic Ground reference for digital logic 16,62 Ground reference for digital I / O logic Function A B Single-chip mode: Port D is a general-purpose bidirectional I / O port. Each of the port D pins can be individually configured as a generalpin A) purpose I / O pin, primary memory control signal (function A), or secondary memory control signal (function B). All chip selects are independent and can be used for memory bank switching. I / O pin/A, B: Internal clock signal is 1 / 1 (PLL) or 1 / 4 XTAL2 / CLKIN frequency. I / O pin/A, B: Read / write output pin. D3 D4 D5 SYSCLK SYSCLK R/W R/W -- 58 57 56 I/O I/O I/O CSPF I / O pin/A: Chip select peripheral output for peripheral file goes low during memory accesses. I / O pin/B: Reserved. D6 CSH1 EDSAAA I/O I / O pin/A: Chip select half output 1 goes low during memory 55AAA accesses. I / O pin/B: External data strobe output goes low during memory accesses from external memory and has the same timings as the five chip selects. 54 I/O I / O pin/A: Chip select eighth output goes low during memory accesses. I / O pin/B: Wait input pin extends bus signals. D7 CSE1 WAIT SCITXD SCIIO1 SCIIO2 SCIIO3 T1IO1 T1IO2 T1IO3 30 29 28 46 45 44 I/O I/O I/O I/O I/O I/O SCIRXD SCICLK SCI transmit data output pin / general-purpose bidirectional pin (see Note) SCI receive data input pin / general-purpose bidirectional pin SCI bidirectional serial clock pin / general-purpose bidirectional pin T1IC / CR T1PWM T1EVT Timer 1 input capture / counter reset input pin / general-purpose bidirectional pin Timer 1 pulse width modulation (PWM) output pin / general-purpose bidirectional pin Timer 1 external event input pin / general-purpose bidirectional pin I = input, O = output Ports A, B, C, and D can be configured only as general-purpose I/O pins. Also, port D3 can be configured as SYSCLK. Note: The three-pin SCI configuration is referred to as SCI1.
2-22
TMS370Cx6x Pinouts and Pin Descriptions
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA A AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA A A AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAA
Table 2-8. TMS370Cx6x Pin Descriptions (Continued)
Pin Name Alternate Function T2AIO1 T2AIO2 T2AIO3 T2BIO1 T2BIO2 T2BIO3 SPIIO1 SPIIO2 SPIIO3 LCC (68) 27 26 25 64 60 59 49 48 47 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Description T2AIC1 / CR T2AIC2 / PWM T2AEVT Timer 2A input capture 1 / counter-reset input pin / general-purpose bidirectional pin Timer 2A input capture 2 / PWM output pin / general-purpose bidirectional pin Timer 2A external event input pin / general-purpose bidirectional pin Timer 2B input capture 1/counter reset input pin/general-purpose bidirectional pin Timer 2B input capture 2/PWM output pin/general-purpose bidirectional pin Timer 2B external event input pin/general-purpose bidirectional pin T2BIC1/CR T2BIC2/PWM T2BEVT SPISOMI SPISIMO SPICLK SPI slave output pin, master input pin / general-purpose bidirectional pin SPI slave input pin, master output pin / general-purpose bidirectional pin SPI bidirectional serial clock pin / general-purpose bidirectional pin I = input, O = output Ports A, B, C, and D can be configured only as general-purpose I/O pins. Also, port D3 can be configured as SYSCLK. Note: The three-pin SCI configuration is referred to as SCI1.
TMS370 Family Pinouts and Pin Descriptions
2-23
TMS370Cx7x Pinouts and Pin Descriptions
2.9 TMS370Cx7x Pinouts and Pin Descriptions
The pinout and pin descriptions for the TMS370Cx7x devices are shown in Figure 2-9 and Table 2-9, respectively.
Figure 2-9. Pinouts for TMS370Cx7x
B5 B6 B7 C0 MC C1 C2 VSS1 C3 C4 C5 C6 C7 AN0 A0 A1 A2 A3 A4 A5 A6 A7 T2AEVT T2AIC2 / PWM T2AIC1 / CR G0 G1 G2 XTAL2 / CLKIN XTAL1 VCC1 VCC3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
B4 B3 B2 B1 B0 D0 / CSE2 / OCF VSS1 VCC1 D1 / CSH3 D3 / SYSCLK D4 / R / W D6 / CSH1 / EDS D7 / CSE1 / WAIT RESET INT1 INT2 INT3 G5 G4 G3 T1IC / CR T1PWM AN7 T1EVT VSS1 AN6 AN5 AN4 AN3 AN2 AN1 VSS3
C3 C4 C5 C6 C7 VCC2 VSS2 A0 A1 A2 A3 A4 A5 A6 A7 T2AEVT T2AIC2/PWM
10 11 12 13 14 15 16
VSS1 C2 C1 MC C0 B7 B6 B5 B4 B3 B2 B1 B0 D0 / CSE2 / OCF VCC2 VSS2 VCC1 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 17 52 18 51 19 50 20 49 21 48 22 47 23 46 24 45 25 44 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 T2AIC1/CR G0 G1 G2 XTAL2/CLKIN XTAL1 V CC1 V CC3 V SS3 AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 D1 / CSH3 D2 / CSH2 D3 / SYSCLK D4 / R / W D5 / CSPF D6/CSH1/EDS D7/CSE1/WAIT RESET INT1 INT2 INT3 G5 G4 G3 T1IC/CR T1PWM T1EVT
A. 64-Pin PSDIP (NM) B. 64-Pin CSDIP (FZ)
C. 68-Pin PLCC (FN) D. 68-Pin CLCC (FZ)
2-24
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA A A A AAAA AA AAAAAAAAAAAAAA AAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA A A A AAAA A AAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA A A A A AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA A A A AAAA A AAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA A A A AAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA A A A AAAA A AAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA A A A AAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAA A A AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAA
I = input, O = output VSS3 VCC3 AN0/E0 AN1/E1 AN2/E2 AN3/E3 AN4/E4 AN5/E5 AN6/E6 AN7/E7 INT3 INT2 INT1/NMI C0 C1 C2 C3 C4 C5 C6 C7 B0 B1 B2 B3 B4 B5 B6 B7 A0 A1 A2 A3 A4 A5 A6 A7 Name
Table 2-9. TMS370Cx7x Pin Descriptions
Pin
DIP (64)
33
32
14 34 35 36 37 38 39 42
48
49
50
60 61 62 63 64 1 2 3
15 16 17 18 19 20 21 22
4 6 7 9 10 11 12 13
LCC (68)
35
34
36 37 38 39 40 41 42 43
50
51
52
65 66 67 68 1 2 3 4
17 18 19 20 21 22 23 24
5 7 8 10 11 12 13 14
I/O
I/O
I/O
I/O I/O I/O I/O I/O I/O I/O I/O
I/O I/O I/O I/O I/O I/O I/O I/O
I/O I/O I/O I/O I/O I/O I/O I/O
I I I I I I I I
I
TMS370 Family Pinouts and Pin Descriptions
Port C is a general-purpose bidirectional I/O port. Port B is a general-purpose bidirectional I/O port. Port A is a general-purpose bidirectional I/O port. Description
ADC1 positive-supply voltage and optional positive-reference input pin ADC1 ground reference pin
Port E can be individually programmed as general-purpose input pins if not used as ADC1 analog input or positive reference input.
A DC1 analog input (AN0 - AN7) or positive reference pins (AN1 - AN7)
External (nonmaskable or maskable) interrupt/general-purpose input pin External maskable interrupt input/general-purpose bidirectional pin External maskable interrupt input/general-purpose bidirectional pin
TMS370Cx7x Pinouts and Pin Descriptions
2-25
A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA A A A AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA A A A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA A A A AAAA AAAA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA A A A AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA A A A AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
2-26
G0 G1 G2 G3 G4 G5 D0 D1 D2 D3 D4 D5 D6 D7 MC
TMS370Cx7x Pinouts and Pin Descriptions
I = input, O = output T2AEVT T1EVT T1PWM VSS2 VSS1 VCC2 VCC1 XTAL1 RESET Name T2AIC2 / PWM T2AIC1 / CR T1IC / CR XTAL2/CLKIN
Table 2-9. TMS370Cx7x Pin Descriptions (Continued)
8, 40, 58
Pin
31, 57
DIP (64)
23 24 25 41 43 44 26 27 28 45 46 47 59 56 - 55 54 - 53 52 30 29 51 -- 5
33, 61
16,62
15,63
LCC (68)
25 26 27 44 45 46 28 29 30 47 48 49 64 60 59 58 57 56 55 54 32 31 53 9 6
I/O
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O I I
Description
Timer 2A input capture 1 / counter reset input pin / general-purpose bidirectional pin Timer 2A input capture 2 / PWM output pin / general-purpose bidirectional pin Timer 2A external event input pin / general-purpose bidirectional pin Timer 1 input capture / counter reset input pin / general-purpose bidirectional pin Timer 1 pulse-width-modulation (PWM) output pin / general-purpose bidirectional pin Timer 1 external event input pin / general-purpose bidirectional pin Port G is a general-purpose bidirectional port. Ground reference for digital I/O logic Ground reference for digital logic Positive supply voltage Positive supply voltage for digital I/O logic Internal oscillator crystal input / external clock source input Internal oscillator output for crystal
Port D is a general-purpose bidirectional I / O port that can be individually configured. D3 is also configurable as SYSCLK. Mode control (MC) pin. MC enables EEPROM write-protection override (WPO) mode, also supplies EPROM VPP. System reset bidirectional pin. RESET, as an input, initializes the microcontroller; as open-drain output, RESET indicates an internal failure was detected by the watchdog or oscillator fault circuit.
TMS370Cx8x Pinouts and Pin Descriptions
2.10 TMS370Cx8x Pinouts and Pin Descriptions
The pinout and pin descriptions for the TMS370Cx8x devices are shown in Figure 2-10 and Table 2-10, respectively.
Figure 2-10. Pinouts for TMS370Cx8x
C2 C3 C4 C5 RESET INT1 INT2 INT3 NC VCC A7 A6 A5 A4 A3 A2 A1 A0 D7 D4
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
INT1 INT2 INT3 VCC NC A7 A6 VSS A5 A4 A3
RESET C5 C4 C3 C2 C1 C0 B0 B1 B2 B3
7 8 9 10 11 12 13 14 15 16 654 3 2 1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 17 18 19 20 21 22 23 24 25 26 27 28 29
1
40
C1 C0 B0 B1 B2 B3 MC XTAL2/CLKIN XTAL1 B7 B6 B5 B4 VSS T1IC/CR T1PWM T1EVT D5 D6 D3
MC XTAL2/CLKIN XTAL1 B7 B6 B5 NC B4 C7 C6 NC
A. 40-pin PDIP (N)
TMS370 Family Pinouts and Pin Descriptions
A2 A1 A0 D7 D4 D3 D6 D5 T1EVT T1PWM T1IC/CR
B. 44-Pin PLCC (FN) C. 44-Pin CLCC (FZ)
2-27
A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAA A A A A A AA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAA A A A A A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA A A A A A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA A A A A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAA A A A A AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAA
2-28
MC D3 D4 D5 D6 D7 C0 C1 C2 C3 C4 C5 C6 C7 B0 B1 B2 B3 B4 B5 B6 B7 A0 A1 A2 A3 A4 A5 A6 A7
TMS370Cx8x Pinouts and Pin Descriptions
I = input, O = output XTAL2 / CLKIN XTAL1 RESET T1PWM T1EVT T1IC / CR INT1 INT2 INT3 Name Pins
Table 2-10. TMS370Cx8x Pin Descriptions
PDIP (40)
33 32 34 25 24 26 21 20 23 22 19 39 40 1 2 3 4 -- -- 38 37 36 35 28 29 30 31 18 17 16 15 14 13 12 11 5 6 7 8
LCC (44)
38 37 39 27 26 28 23 22 25 24 21 44 1 2 3 4 5 30 31 43 42 41 40 32 34 35 36 20 19 18 17 16 15 13 12 6 7 8 9
I/O
I/O
I/O I/O
I/O
I/O I/O I/O I/O I/O
I/O I/O I/O I/O I/O I/O I/O I/O
I/O I/O I/O I/O I/O I/O I/O I/O
I/O I/O I/O I/O I/O I/O I/O I/O
I I/O I/O
I O I
System reset bidirectional pin: as input pin, RESET initializes the microcontroller; as open-drain output, RESET indicates that an internal failure was detected by the watchdog or oscillator fault circuit.
Internal oscillator crystal input / external clock source input Internal oscillator output for crystal Port C is a general-purpose bidirectional I / O port. Port B is a general-purpose bidirectional I / O port. Port A is a general-purpose bidirectional I / O port. Description
Mode control pin; enables EEPROM write-protection override (WPO) mode, and also supplies EPROM VPP Timer 1 input capture / counter reset input pin / general-purpose bidirectional pin Timer 1 PWM output pin / general-purpose bidirectional pin Timer 1 external event input pin / general-purpose bidirectional pin External (non-maskable or maskable) interrupt / general-purpose input pin External maskable interrupt input / general-purpose bidirectional pin External maskable interrupt input / general-purpose bidirectional pin
Port D is a general-purpose bidirectional I / O port. D3 is also configurable as SYSCLK.
A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAA A A AAAAA A AAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AA AA A AA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAA AA AA A
Table 2-10. TMS370Cx8x Pin Descriptions (Continued)
I = input, O = output NC VSS VCC Name Pins PDIP (40) 27 10 9 11, 29, 33 LCC (44) 14 10 I/O These pins have no connection to the internal die. Ground reference for digital logic Positive supply voltage Description
TMS370 Family Pinouts and Pin Descriptions
TMS370Cx8x Pinouts and Pin Descriptions
2-29
TMS370Cx9x Pinouts and Pin Descriptions
2.11 TMS370Cx9x Pinouts and Pin Descriptions
The pinout and pin descriptions for the TMS370Cx9x devices are shown in Figure 2-11 and Table 2-11, respectively.
Figure 2-11.Pinouts for TMS370Cx9x
A3 A4 A5 A6 A7 RESET INT1 VCC VCC3 VSS3 AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
A2 A1 A0 T1EVT T1PWM MC T1IC/CR XTAL2/CLKIN XTAL1 VSS D7 D5 D4 D6 D3 AN14 AN13 AN12 AN11 AN10
RESET INT1 VCC VCC3 VSS3 AN0 AN1 AN2 AN3 AN4 NC
7 8 9
654
3 2 1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30
T1PWM
T1EVT
NC
A7 A6
A5
A4
A3
A2 A1
A0
10 11 12 13 14 15 16
29 17 18 19 20 21 22 23 24 25 26 27 28 AN10 AN11 AN5 AN6 AN7 AN8 AN9 NC AN12 AN13 AN14
MC T1IC/CR XTAL2/CLKIN NC XTAL1 VSS D7 D5 D4 D6 D3
A. 40-Pin PSDIP (NJ) B. 40-Pin CSDIP (JC)
C. 44-Pin PLCC (FN) D. 44-Pin CLCC (FZ)
The NJ designator for the 40-pin plastic shrink DIP package was formerly known as N2. The
mechanical drawing of the NJ is identical to the N2 package and did not need to be requalified.
2-30
A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA A A AA A A AAA AA A A AAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA A A AA A A AA A A AAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A AA A A AA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAA A A AA A A AA A A AAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA A A AA AA A A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AAAAAAAAAAAAAAAAAAAAAA A A AA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA A A AA AA A A A AAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA A A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA A A AA A A AA A A AAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA A A AA AA A A AAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAA A AAAAAAAAAAAAAAAAAAAA A A A AA AAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAA
VSS 31 I = input, O = output VCC XTAL2/CLKIN XTAL1 MC RESET T1IC/CR T1PWM T1EVT INT1 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN0/E0 AN1/E1 AN2/E2 AN3/E3 AN4/E4 AN5/E5 AN6/E6 AN7/E7 D3/SYSCLK D4 D5 D6 D7 A0 A1 A2 A3 A4 A5 A6 A7 Name
Table 2-11. TMS370Cx9x Pin Descriptions
Pin
SDIP (40)
33 32
35
34 36 37
19 20 21 22 23 24 25
26 28 29 27 30
38 39 40 1 2 3 4 5
11 12 13 14 15 16 17 18
8
6
7
LCC (44)
34
37 35
39
38 40 41
21 22 24 25 26 27 28
12 13 14 15 16 18 19 20
29 31 32 30 33
42 43 44 2 3 4 5 6
9
7
8
I/O
I/O
I/O I/O I/O
I/O I/O I/O I/O I/O
I/O I/O I/O I/O I/O I/O I/O I/O
I O
I
I
I I I I I I I
I I I I I I I I
System-reset bidirectional pin. RESET, as an input, initializes the microcontroller; as open-drain output, RESET indicates an internal failure was detected by the watchdog or oscillator fault circuit.
Ground reference for digital logic.
Positive supply voltage for digital logic.
Internal oscillator crystal input / external clock source input Internal oscillator output for crystal
Mode control (MC) pin. MC enables EEPROM write-protection override (WPO) mode, and also supplies EPROM VPP.
Timer 1 input capture/counter reset input pin/general-purpose bidirectional pin. Timer 1 PWM output pin/general-purpose bidirectional pin. Timer 1 external event input pin/general-purpose bidirectional pin.
External (nonmaskable or maskable) interrupt/general-purpose input pin
ADC3 analog input pins.
ADC3 analog input (AN0 - AN7) or positive reference pins (AN6 - AN7). Port E can be individually programmed as general-purpose input pins if not used as ADC3 analog input. Only AN6 and AN7 can be software-configured as positive reference input.
Port D is a general-purpose bidirectional I/O port. D3 is also configurable as SYSCLK.
Port A is a general-purpose bidirectional I/O port.
Description
TMS370 Family Pinouts and Pin Descriptions
TMS370Cx9x Pinouts and Pin Descriptions
2-31
A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAA A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
TMS370Cx9x Pinouts and Pin Descriptions
I = input, O = output NC
2-32 VSS3 VCC3
Name
Table 2-11. TMS370Cx9x Pin Descriptions (Continued)
Pin
SDIP (40)
10 9
--
1, 17, 23, 36 LCC (44) 10 11
I/O
These pins have no connection to the internal die. Ground reference for ADC3 Description Positive supply voltage for ADC3
TMS370CxAx Pinouts and Pin Descriptions
2.12 TMS370CxAx Pinouts and Pin Descriptions
The pinout and pin descriptions for the TMS370CxAx devices are shown in Figure 2-12 and Table 2-12, respectively.
Figure 2-12. Pinouts for TMS370CxAx
B2 T2AEVT T2AIC2 / PWM T2AIC1 / CR RESET INT1 INT2 INT3 VCC A7 A6 VSS A5 A4 A3 A2 A1 A0 D7 D4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
B1 B0 SCITXD SCIRXD SCICLK D5 MC XTAL2 / CLKIN XTAL1 T1IC / CR T1PWM T1EVT C0 B7 B6 B5 B4 B3 D6 D3
A. 40-Pin PDIP (N)
TMS370 Family Pinouts and Pin Descriptions
2-33
TMS370CxAx Pinouts and Pin Descriptions
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAAAA A A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA A A AA A AAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAAAA A A A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAA AAAAAAAAAAAAAAAAAAAAA A A A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA A A AA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA A A A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA A A AA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Table 2-12. TMS370CxAx Pin Descriptions
40-Pin PDIP Name A0 A1 A2 A3 A4 A5 A6 A7 B0 B1 B2 B3 B4 B5 B6 B7 No. 18 17 16 15 14 13 11 10 39 40 1 23 24 25 26 27 28 21 20 35 22 19 6 7 8 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Description Port A is a general-purpose bidirectional I / O port. Port B is a general-purpose bidirectional I / O port. C0 D3 D4 D5 D6 D7 Port C is a general-purpose bidirectional I / O port. Port D is a general-purpose bidirectional I / O port. D3 is also configurable as SYSCLK. INT1 INT2 INT3 I I/O I/O External (non-maskable or maskable) interrupt/ general-purpose input pin. External maskable interrupt input / general-purpose bidirectional pin. External maskable interrupt input / general-purpose bidirectional pin. T1IC / CR T1PWM T1EVT SCITXD SCIRXD SCICLK RESET 31 30 29 38 37 36 5 I/O Timer 1 input capture / counter reset input pin / general-purpose bidirectional pin. Timer 1 PWM output pin / general-purpose bidirectional pin. Timer 1 external event input pin / general-purpose bidirectional pin. SCI transmit data output pin, general-purpose bidirectional pin (see Note). SCI receive data input pin / general-purpose bidirectional pin. SCI bidirectional serial clock pin / general-purpose bidirectional pin. I/O I/O System reset bidirectional pin; as input pin, RESET initializes the microcontroller; as open-drain output, RESET indicates that an internal failure was detected by watchdog or oscillator fault circuit. Timer 2A input capture 1/counter reset input pin/general-purpose bidirectional pin. Timer 2A input capture 2/PWM output pin/general-purpose bidirectional pin. Timer 2A external event input pin/general-purpose bidirectional pin. Mode control input pin . T2AIC1/CR T2AIC2/PWM T2AEVT MC 4 3 2 I/O I 34 33 32 9 XTAL2 / CLKIN XTAL1 VCC I O Internal oscillator crystal input / external clock source input. Internal oscillator output for crystal. Positive supply voltage VSS 12 Ground reference I = input, O = output Note: The two SCI configuration pins are referred to as SCI2.The three-pin SCI configuration is referred to as SCI1.
2-34
TMS370CxBx Pinouts and Pin Descriptions
2.13 TMS370CxBx Pinouts and Pin Descriptions
The pinout and pin descriptions for the TMS370CxBx devices are shown in Figure 2-13 and Table 2-13, respectively.
Figure 2-13. Pinouts for TMS370CxBx
B5 B6 B7 C0 MC C1 C2 VSS1 C3 C4 C5 C6 C7 AN0 A0 A1 A2 A3 A4 A5 A6 A7 G0 G1 G2 G3 G4 G5 XTAL2 / CLKIN XTAL1 VCC1 VCC3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
B4 B3 B2 B1 B0 D0 / CSE2 / OCF VSS1 VCC1 D1 / CSH3 D3 / SYSCLK D4 / R / W D6 / CSH1 / EDS D7 / CSE1 / WAIT RESET INT1 INT2 INT3 H0 G7 G6 T1IC / CR T1PWM AN7 T1EVT VSS1 AN6 AN5 AN4 AN3 AN2 AN1 VSS3
C3 C4 C5 C6 C7 VCC2 VSS2 A0 A1 A2 A3 A4 A5 A6 A7 G0 G1
10 11 12 13 14 15 16
VSS1 C2 C1 MC C0 B7 B6 B5 B4 B3 B2 B1 B0 D0 / CSE2 / OCF VCC2 VSS2 VCC1 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 17 52 18 51 19 50 20 49 21 48 22 47 23 46 24 45 25 44 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 G2 G3 G4 G5 XTAL2/CLKIN XTAL1 V CC1 V CC3 V SS3 AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 D1 / CSH3 D2 / CSH2 D3 / SYSCLK D4 / R / W D5 / CSPF D6/CSH1/EDS D7/CSE1/WAIT RESET INT1 INT2 INT3 H0 G7 G6 T1IC/CR T1PWM T1EVT
A. 64-Pin PSDIP (NM)
B. 68-Pin PLCC (FN)
TMS370 Family Pinouts and Pin Descriptions
2-35
A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A AAAAAAAAAAAAAAAAA A A A AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAA AAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA A A A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA A A A AA A A AAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA A A A AA A A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
2-36
C0 C1 C2 C3 C4 C5 C6 C7 B0 B1 B2 B3 B4 B5 B6 B7 A0 A1 A2 A3 A4 A5 A6 A7
TMS370CxBx Pinouts and Pin Descriptions
I = input, O = output RESET VSS3 INT3 INT2 VCC3 Name AN0/E0 AN1/E1 AN2/E2 AN3/E3 AN4/E4 AN5/E5 AN6/E6 AN7/E7 INT1/NMI
Table 2-13. TMS370CxBx Pin Descriptions
Pin
PSDIP (64)
51 33 32 14 34 35 36 37 38 39 42 48 49 50 60 61 62 63 64 1 2 3 15 16 17 18 19 20 21 22
4 6 7 9 10 11 12 13
LCC (68)
53 35 34 36 37 38 39 40 41 42 43 50 51 52 65 66 67 68 1 2 3 4 17 18 19 20 21 22 23 24
5 7 8 10 11 12 13 14
I/O
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I I I I I I I
System reset bidirectional pin. RESET, as an input, initializes the microcontroller; as open-drain output, RESET indicates an internal failure was detected by the watchdog or oscillator fault circuit. ADC1 positive-supply voltage and optional positivereference input pin ADC1 ground reference pin Port C is a general-purpose bidirectional I/O port. Port B is a general-purpose bidirectional I/O port. Port A is a general-purpose bidirectional I/O port. Description External (nonmaskable or maskable) interrupt/general-purpose input pin External maskable interrupt input/general-purpose bidirectional pin External maskable interrupt input/general-purpose bidirectional pin
Port E can be individually programmed as general-purpose input pins if not used as ADC1 analog input or positive reference input.
ADC1 analog input (AN0 - AN7) or positive reference pins (AN1 - AN7)
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA A A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AAAAAAAAAAAAA AA AAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA A A AA A A AA A AA AAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA A A AA A A A AA AA A A AAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA A A A AA AA AAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A AAAAAAAAAAAAAAAAAA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAA
I = input, O = output T1EVT T1PWM T1IC / CR H0 G0 G1 G2 G3 G4 G5 G6 G7 D0 D1 D2 D3 D4 D5 D6 D7 VSS2 VSS1 VCC2 VCC1 XTAL2/CLKIN XTAL1 MC Name
Table 2-13. TMS370CxBx Pin Descriptions (Continued)
Pin
PSDIP (64)
8, 58, 40
31, 57
41
43
44
47
23 24 25 26 27 28 45 46
59 56 - 55 54 - 53 52
29 30
--
--
5
16,62
15,63
33,61
LCC (68)
44
45
46
49
25 26 27 28 29 30 47 48
64 60 59 58 57 56 55 54
31 32
9
6
I/O
I/O
I/O
I/O
I/O
I/O I/O I/O I/O I/O I/O I/O I/O
I/O I/O I/O I/O I/O I/O I/O I/O
I O
I
Description
I/O timer 1 input capture / counter reset input pin / general-purpose bidirectional pin I/O timer 1 pulse-width-modulation (PWM) output pin / general-purpose bidirectional pin I/O timer 1 external event input pin / general-purpose bidirectional pin
Port H is a general-purpose bidirectional port.
Port G is a general-purpose bidirectional port.
Port D is a general-purpose bidirectional I / O port. D3 is also configurable as SYSCLK.
Ground reference for digital I/O logic
Ground reference for digital logic
Positive supply voltage for digital I/O logic
Positive supply voltage
Internal oscillator crystal input / external clock source input Internal oscillator output for crystal
Mode control (MC) pin. MC enables EEPROM write-protection override (WPO) mode.
TMS370 Family Pinouts and Pin Descriptions
TMS370CxBx Pinouts and Pin Descriptions
2-37
TMS370CxCx Pinouts and Pin Descriptions
2.14 TMS370CxCx Pinouts and Pin Descriptions
The pinout and pin descriptions for the TMS370CxCx devices are shown in Figure 2-14 and Table 2-14, respectively.
Figure 2-14. Pinouts for TMS370CxCx
A7 D6 D3 V CC V SS RESET D4 4 3 2 1 28 27 26 XTAL2 / CLKIN XTAL1 A6 A5 A4 A3 A2 5 6 7 8 9 10 11 25 24 23 22 21 20 19 12 13 14 15 16 1718 D7 A1 A0 INT1 T1EVT T1PWM T1IC / CR AN3 AN2 AN1 AN0 SCITXD SCIRXD MC
VCC D3 D6 A7 XTAL2 / CLKIN XTAL1 A6 A5 A4 A3 A2 D7 A1 A0
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VSS RESET D4 AN3 AN2 AN1 AN0 SCITXD SCIRXD MC T1IC / CR T1PWM T1EVT INT1
A. 28-Pin PDIP (N) B. 28-Pin CDIP (JD)
C. 28-Pin PLCC (FN) D. 28-Pin CLCC (FZ)
2-38
TMS370CxCx Pinouts and Pin Descriptions
A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA A A AAA AAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA AA A AAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA A AAA AA AA AAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA A A AAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A AAAAAAAAAAAAAAAAAAAAAAA A AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAA
Table 2-14. TMS370CxC Pin Descriptions
28-Pin DIP/LCC Name No. 14 13 11 10 9 8 7 4 I / O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I I I Description A0 A1 A2 A3 A4 A5 A6 A7 Port A is a general-purpose bidirectional I / O port. D3 D4 D6 D7 2 26 3 12 Port D is a general-purpose bidirectional I / O port. D3 is also configurable as SYSCLK. INT1 15 22 23 24 25 18 17 16 21 20 27 External (non-maskable or maskable) interrupt/general-purpose input pin. AN0 /E0 AN1 / E1 AN2 / E2 AN3 / E3 ADC2 module analog input (AN0 - AN3) or positive reference pins (AN1 - AN3). Port E can be individually programmed as general-purpose input pins if not used as ADC2 analog input. Timer 1 input capture / counter reset input pin / general-purpose bidirectional pin. Timer 1 PWM output pin / general-purpose bidirectional pin. Timer 1 external event input pin / general-purpose bidirectional pin. SCI module transmit data output / general-purpose bidirectional pin. (See Note) SCI module receive data input pin / general-purpose bidirectional pin. T1IC / CR T1PWM T1EVT SCITXD SCIRXD RESET I/O I/O I/O I/O I/O I/OAAAAAAAAAAAAAAAAAAAAA System reset bidirectional pin; as input pin, RESET initializes the microcontroller; as open-drain output, RESET indicates that an internal failure was detected by watchdog or oscillator fault circuit. I Mode control input pin; and also supplies EPROM VPP. MC 19 5 6 1 XTAL2 / CLKIN XTAL1 VCC I O Internal oscillator crystal input / External clock source input. Internal oscillator output for crystal. Positive supply voltage VSS 28 Ground reference I = input, O = output Note: The two SCI configuration pins are referred to as SCI2.
TMS370 Family Pinouts and Pin Descriptions
2-39
2-40
Running Title--Attribute Reference
Chapter 3
CPU and Memory Organization
This chapter describes the CPU registers and memory organization. In the TMS370 register-to-register architecture, the CPU and up to the first 256 bytes of RAM act as a single unit with the program counter, stack pointer, and status register. This chapter covers the following topics:
Topic
3.1 3.2 3.3 3.4
Page
CPU/Register File Interaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 Memory Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
Chapter Title--Attribute Reference
3-1
CPU / Register File Interaction
3.1 CPU/Register File Interaction
The TMS370 architecture provides the following components:
-
CPU registers
J J J
A stack pointer, which points to the last entry in the memory stack A status register, which monitors the operation of the instructions and contains the global interrupt bits A program counter, which points to the memory location of the next instruction to be executed
-
Memory map
J J J J
A register file that can be accessed as general-purpose registers, data memory storage, program instructions, or part of the stack A peripheral file that provides access to all internal peripheral modules, system-wide control functions, and EEPROM/EPROM programming control Data EEPROM modules, which provide in-circuit programmability and data retention in power-off mode Program memory that provides alternatives to meet the needs of your application
Figure 3-1 illustrates the CPU registers and memory blocks. Note: Device Block Diagrams
Section 1.7 on page 1-21 contains a collection of block diagrams of each device family. These diagrams show each element of the TMS370 architecture (for example, TMS370Cx4x in Figure 1-6 on page 1-26.)
3-2
CPU / Register File Interaction
Figure 3-1. Programmer's Model
15 Program Counter (PC) 0
7 C 7 N
Status Register (ST) Z V IE2 IE1 --
0 -- 0
Stack Pointer (SP)
Legend: C= N= Z= V= IE2 = IE1 =
Carry Negative Zero Overflow Level 2 interrupt enable Level 1 interrupt enable
Register File (RAM) R0 (A) R1 (B) R2 R3
0000h 0001h 0002h 0003h 0100h
RAM expansion, peripheral file, and data EEPROM expansion
1FFFh 2000h
. . .
R127
007Fh
Program ROM/EPROM
7F9Bh 7F9Ch
PACT vectors
. . .
R255
00FFh
7FBFh 7FC0h
Traps 0-15
7FDFh 7FE0h 7FEBh 7FECh 7FFFh 8000h
Reserved Interrupt/reset vectors
Program ROM/EPROM
DFFFh E000h
Program memory expansion
FFFFh
CPU and Memory Organization
3-3
CPU Registers
3.2 CPU Registers
The CPU contains three registers to control the status and direction of the program. These are the stack pointer, status register, and program counter. These registers and their use are described in the following subsections.
3.2.1
Stack Pointer (SP)
The stack operates as a last-in, first-out, read/write memory. The stack is typically used to store the return address on subroutine calls and the status register contents during interrupts. The stack pointer (SP) is an 8-bit CPU register that points to the last entry or top of the stack. The SP is automatically incremented before data is pushed onto the stack and decremented after data is popped from the stack. The stack can be placed anywhere in the register file. During reset, the SP is loaded with a value of 01h. To control the area occupied by the stack, the application program must set the stack pointer and include code to monitor the stack size. The SP is loaded from register B (R1) by the assembly language instruction LDSP (load stack pointer). The LDSP instruction allows the stack to be located anywhere in the register file space. The SP can be read into register B by the STSP (store stack pointer) command. Figure 3-2 illustrates an example SP initialization and stack operation.
INIT MOV #60h,B LDSP ;Load register B with the value ;60h. ;Load the stack pointer with the ;contents of register B.
Figure 3-2. Stack Example
0000h Top of stack on reset = 0001h
* * *
Initial top of stack = 0060h 0061h
* * * * * *
PUSH
Increment then store
* *
POP
Fetch then decrement
Upper stack limit = 007Fh or 00FFh
3-4
CPU Registers
For devices with 256 (or more) bytes of RAM, if the stack is pushed beyond its limit of 00FFh, the SP register wraps around from 00FFh to 0000h without an error indication. For devices with only 128 bytes of RAM, the stack is not implemented beyond 007Fh; data pushed beyond this limit is lost. Your application program must guard against a stack overflow.
3.2.2
Status Register (ST)
The status register (ST) monitors the operation of the instructions and contains the global interrupt enable bits. The ST includes four status bits (condition flags - C, N, Z, and V), two interrupt enable bits (IE2 and IE1), and two reserved bits. The four status bits indicate the outcome of the previous instruction; conditional instructions (for example, the conditional jump instructions) use these status bits to determine the program flow.
Status Register (ST)
Bit #
7
C RW-0
6
N RW-0
5
Z RW-0
4
V RW-0
3
IE2 RW-0
2
IE1 RW-0
1
--
0
--
R = Read, W = Write, -n = Value of the bit after the register is reset
The ST, status bit notation, and status bit definitions are as follows: Bit 7 C. Carry. This status bit is set by arithmetic instructions as a carry bit or as a no-borrow bit. It is also affected by the rotate instructions. See each instruction in Chapter 16 for a detailed description of how the carry bit is used. Bit 6 N. Negative. The CPU sets this bit to the value of the most significant bit (sign bit) of the result of the previous operation. Bit 5 Z. Zero. This bit is set by the CPU if the result of the previous operation was 0; cleared otherwise.
CPU and Memory Organization
3-5
CPU Registers
Bit 4
V. Overflow. This bit is set by the CPU if a signed arithmetic overflow condition is detected during the previous instruction. The value of this flag is significant at the completion of the following instructions: ADC, ADD, INC, INCW, CMP, DEC, SUB, SBB, and DIV.
Instruction ADC, ADD, INC, INCW CMP, DEC, SUB, SBB DIV (Rs, A) V (Bit 4) Equals a 1 If (C XOR N) AND (bit 7{s} XNOR bit 7{d}) (C XOR N) AND (bit 7{s} XOR bit 7{d}) Rs A, which means quotient > 255
Bit 3
IE2. Level 2 Interrupt Enable, (daisy-chain order). This bit controls interrupt level 2 (lowest priority). 0 = Disables interrupt requests from priority level 2. 1 = Enables interrupt requests from priority level 2.
Bit 2
IE1. Level 1 Interrupt Enable. This bit controls interrupt level 1 (highest priority). 0 = Disables interrupt requests from priority level 1. 1 = Enables interrupt requests from priority level 1.
Bits 1-0
Reserved. Read data is indeterminate. When the CPU acknowledges an interrupt, the contents of the ST are automatically pushed onto the stack; then the ST is cleared (for more information about interrupt effects on the ST, see subsection 5.1.1, page 5-3). The RTI instruction implements a normal exit from an interrupt service routine. When the CPU executes the RTI instruction, it automatically restores the contents of the ST with a stack-pop operation. The four condition flags (C, N, Z, and V) are updated every time an instruction is executed that manipulates or moves data. As a result, conditional branches should be performed immediately after data is manipulated. The instructions that do not affect the contents of these flags are as follows: TRAP 0 to TRAP 15 CALL CALLR BR DJNZ JMP Jcnd (jump on condition instructions) IDLE NOP PUSH ST RTS STSP JMPL LDSP
The LDST instruction allows a program to change all bits in the status register. The byte following this instruction is loaded directly into the status register. The
3-6
CPU Registers
assembly language instructions DINT, EINT, EINTH, and EINTL enable specific interrupts. These instructions are converted to an LDST #iop8 opcode by the assembler so that #iop8 is the appropriate value to set or clear the specific interrupt (see Chapter 16 for more information on the LDST instruction). The carry (C) bit can be set with the SETC opcode and cleared with the CLRC opcode.
3.2.3
Program Counter (PC)
The contents of the program counter (PC) point to the memory location of the next instruction to be executed. The PC consists of two 8-bit registers in the CPU: the program counter high (PCH) and program counter low (PCL). These registers contain the MSbyte and LSbyte of a 16-bit address. During reset, the PCH (PC's MSbyte) is loaded with the contents of memory location 7FFEh, and the PCL (PC's LSbyte) is loaded with the contents of memory location 7FFFh. Figure 3-3 illustrates this operation using an example value of 7000h as the contents of memory locations 7FFEh and 7FFFh (reset vector).
Figure 3-3. Program Counter After Reset
Memory (8-bits) 0000h Program Counter (PC) PCH PCL 70 00
(16-bits)
7FFEh 7FFFh
70 00
CPU and Memory Organization
3-7
Memory Map
3.3 Memory Map
Figure 3-4 shows the memory map of the TMS370 family members. The partitioning of memory and physical location of memory (that is, the on- or off-chip) depends on the device used and the memory mode (C or P -- microcontroller or microprocessor, discussed in Section 3.4, page 3-16). Each device that has memory expansion can be programmed up to sixteen address bits. This allows access to up to 56K bytes of memory. In addition, memory expansion features allow using up to 112K bytes of external memory. (The expansion features are described further in subsection 3.4.2 page 3-19.)
3.3.1
Register File
The register file (RF) is located in on-chip RAM at memory addresses 0000h-00FFh.
-
In devices with 128 bytes of RAM, the RF has 128 memory locations treated as registers R0 through R127. In devices with 256 bytes of RAM, the RF has 256 memory locations treated as registers R0 through R255. If the device incorporates the PACT module:
J
128 bytes of dual-port RAM are mapped into memory locations 0080h-00FFh for 'x32 devices or 0180-01FFh for 'x36 devices. For the 'x32 device, any of this RAM not used by the PACT module can be used as registers or stack. For the 'x36 device, any of this RAM not used by the PACT can be used only as data memory storage. 256 bytes of standby RAM (only available in 'x36 devices) are mapped into memory locations 0200h-02FFh. The standby RAM is used as general-purpose memory, and cannot be used as RF or stack. The standby RAM is powered by pin VCCSTBY; therefore, data is saved if the main VCC1 power fails.
J
The memory addresses of the registers in the RF are shown in Figure 3-5 on page 3-10.
3-8
Memory Map
Figure 3-4. TMS370 Memory Map
0000h 128 bytes RAM (0000h - 007Fh) 256 bytes RAM (0000h - 00FFh) 512 bytes RAM (0000h - 01FFh 0200h 1K bytes RAM (0000h - 03FFh) 0400h 1.5K bytes RAM (0000h - 05FFh) 0600h 3.5K bytes RAM (0000h - 0DFFh) 0E00h Reserved 1000h Peripheral file 10C0h Peripheral expansion Reserved 512 bytes (1E00h - 1FFFh) data EEPROM 256 bytes (1F00h - 1FFFh) data EEPROM 24K bytes ROM/EPROM (2000h - 7FFFh) or uP mode memory expansion 16K bytes ROM/EPROM (4000h - 7FFFh) or uP mode memory expansion 12K bytes ROM (5000h - 7FFFh) or uP mode memory expansion 8K bytes ROM (6000h - 7FFFh) or uP mode memory expansion 4K bytes ROM (7000h - 7FFFh) or uP mode memory expansion 2K bytes ROM (7800h - 7FFFh) interrupts and RESET vectors; TRAP vectors 32K bytes ROM/EPROM (2000h - 9FFFh) or uP memory expansion A000h 48K bytes ROM/EPROM (2000h - DFFFh) or uP memory expansion E000h Memory expansion/external memory FFFFh In devices with more than 256 bytes of RAM, only the first 256-byte block can be used as registers or stack. 1100h 1E00h 1F00h 2000h 4000h 5000h 6000h 7000h 7800h 7FC0h 8000h 0080h 0100h
CPU and Memory Organization
3-9
Memory Map
Figure 3-5. Register File Addresses
1 byte R0 (A) R1 (B) R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh
D D D D
General-purpose registers Data memory storage Program execution Stack
R255
00FFh
The first two registers, R0 and R1, are also called registers A and B, respectively. Some instructions imply the use of register A or B. For example, the LDSP instruction assumes that the value to be loaded into the stack pointer is contained in register B. The partitioning of the RF is determined by the value loaded into the stack pointer and by the program's use of the RF. Locations within the RF address space can serve as either the CPU register file or general-purpose read/write memory. Program instructions can reside in and be executed from any location in the address space without restriction. The stack also occupies a portion of the RF. The multiple uses of the RF give you the flexibility to use the RF however you wish.
3-10
Memory Map
Any location in the RF can be accessed in one of three ways:
-
Register access using the register number as shown in the following example code:
MOV MOV A,R6 R12,R200 ;Move the ;Register ;Move the ;Register contents of Register A to R6. contents of Register 12 to R200.
-
Stack access using the stack pointer as shown in the following example code:
MOV LDSP PUSH #5,B A ;Move the value 5 into Register B. ;Move the contents of Register B to ;the stack pointer. ;Increment stack pointer to 6. ;Move contents of Register A to 0006h.
-
Normal memory access using 16-bit addresses as shown in the following example code:
MOV A,&0006 ;Move the contents of Register A to ;memory location 0006h.
When working with the RF, you must keep the following in mind:
3.3.2 Peripheral File
Access time. When the RF is used as a general-purpose register, the access time is a single-system clock cycle. Access to the RF for any other purpose takes two clock cycles. Reset operations. A reset operation has no effect on the contents of any memory location within the RF except for locations 0000h (register A) and 0001h (register B). Registers A and B are cleared in the beginning of the reset process. Halt, idle, and standby states. The halt, idle, and standby states have no effect on the contents of the RF or RAM. RAM outside of the RF. RAM that is not within the first 256 bytes (0000h-00FFh) is general-purpose RAM and is not considered part of the RF. Access to this RAM takes two clock cycles.
The peripheral file (PF) is a set of memory-mapped registers that provide access to all internal peripheral modules, system-wide control functions, and EEPROM/EPROM programming control. The PF includes 256 addresses in the memory map from 1000h-10FFh. The PF is divided into sixteen frames of 16 bytes each. Each peripheral frame is
CPU and Memory Organization
3-11
Memory Map
allocated its own set of control registers. In addition, some frames are dedicated to specific functions. The instruction set includes some instructions which access the peripheral file directly. These instructions designate the register by the number of the file register relative to 1000h, preceded by P0 for a hexadecimal designator or P for a decimal designator. For example, the system configuration control register 0 is located at address 1010h; its peripheral file hexadecimal designator is P010, and its decimal designator is P16. Table 3-1 shows the address map of the peripheral file for the different device families. The following describe frames 0 - 15 of the file:
-
Frame 0 of the peripheral file (memory addresses 1000h-100Fh) is reserved for factory testing. The results of access to this frame are unpredictable. Frame 1 (1010h-101Fh) contains system configuration and control functions. It also contains registers for controlling EEPROM/EPROM programming. EEPROM/EPROM module control registers are described in Chapter 6, EPROM and EEPROM Modules. Frame 2 (1020h-102Fh) contains the digital I/O pin configuration and control registers. The individual functions controlled by these registers are described in Section 4.4, page 4-18. Frames 3 through 8 are used by the internal peripherals. These peripherals and their control registers are described in the following chapters:
-
J J J J J J J J J J
Timer 1 registers -- Chapter 7 Timer 2A registers -- Chapter 8 Timer 2B registers -- Chapter 8 SCI1 registers -- Chapter 9 SCI2 registers -- Chapter 10 SPI registers -- Chapter 11 ADC1 registers -- Chapter 12 ADC2 registers -- Chapter 13 ADC3 registers -- Chapter 14 PACT registers -- Chapter 15
Frames 9 through 11 are reserved. Frames 12 through 15 are available for the external expansion of the peripheral file on devices that have a memory expansion capability. These frames are located in external memory and accessed by the external address and data buses.
3-12
Memory Map
Table 3-1. Peripheral File Address Map
Frame
No. Address Description Reserved for Factory Test System and EEPROM/EPROM Control Registers Digital I/O Port Control Registers SPI Registers Timer 1 Registers PACT Registers
TMS370 Device Families x0x x1x x2x -- Yes Yes NA Yes NA Yes NA NA NA NA NA NA NA NA NA NA -- Yes Yes Yes Yes NA NA NA NA NA NA NA NA NA NA NA NA -- Yes Yes Yes Yes NA Yes NA NA NA NA NA NA NA NA NA NA x32 -- Yes Yes NA NA Yes NA NA Yes NA NA NA NA NA NA NA NA x36 -- Yes Yes Yes NA Yes NA NA Yes NA NA NA NA NA NA NA NA x4x x5x x6x x7x x8x x9x -- Yes Yes NA Yes NA Yes Yes Yes NA NA NA NA NA NA NA NA -- Yes Yes Yes Yes NA Yes Yes Yes NA NA NA NA Yes Yes Yes Yes -- Yes Yes Yes Yes NA Yes Yes Yes Yes NA NA NA Yes Yes Yes Yes -- Yes Yes NA Yes NA NA Yes Yes NA NA NA NA NA NA NA NA -- Yes Yes NA Yes NA NA NA NA NA NA NA NA NA NA NA NA -- Yes Yes NA Yes NA NA NA Yes NA NA NA NA NA NA NA NA xAx -- NA Yes NA Yes NA Yes Yes NA NA NA NA NA NA NA NA NA xBx -- Yes Yes NA Yes NA NA NA Yes NA NA NA NA NA NA NA NA xCx -- Yes Yes NA Yes NA Yes NA Yes NA NA NA NA NA NA NA NA
0 1 2 3 4
1000h 1010h 1020h 1030h 1040h
5 6 7 8 9 10 11 12 13 14 15
1050h 1060h 1070h 1080h 1090h 10A0h 10B0h 10C0h 10D0h 10E0h 10F0h
SCI Registers Timer 2A Registers ADC Registers Timer 2B registers Reserved Reserved Reserved External Peripheral Control External Peripheral Control External Peripheral Control External Peripheral Control
NA = Not Available SCI refers to SCI1 and SCI2 ADC refers to ADC1, ADC2, and ADC3
3.3.3
Data EEPROM Modules
Data EEPROM modules are provided on all TMS370 family devices, except TMS370CxAx and TMS370CxCx device families. The data EEPROM modules are 256- and 512-byte arrays. The 256-byte array is located at memory addresses 1F00h through 1FFFh, with the WPR (write protection register) at 1F00h. The 512-byte array is located at memory addresses 1E00h through 1FFFh, with WPRs at 1E00h and 1F00h. Larger arrays will continue to grow toward the smaller memory addresses with WPRs located in the first byte of every 256-byte boundary. Each set of 256 bytes is configured into eight blocks of 32 bytes and has an associated WPR. Each block can be individually write protected by setting the
CPU and Memory Organization
3-13
Memory Map
appropriate bit in the WPR. This module can be programmed on the basis of an entire array, a byte, or a single bit. The read-access time for the EEPROM module is two system clock cycles. Programming of the data EEPROM array is controlled by the data EEPROM control register (DEECTL) at memory address 101Ah (P01A) and the corresponding WPRs. See subsections 6.2.1 (page 6-3) and 6.2.2 (page 6-4) for more details on the WPR and DEECTL registers.
3.3.4
Program Memory
The program memory options available for the TMS370 family allow a wide selection of memory types: ROM or EPROM, ranging in size from 2K to 48K bytes. The program memory is arranged as individually addressable bytes in the memory map. Data can be read or code can be executed directly from these locations. Memory addresses 7F9Ch through 7FBFh and 7FECh through 7FFFh are reserved for interrupt and reset vectors. Trap vectors, used with TRAP0 through TRAP15 instructions, are at addresses 7FC0h through 7FDFh. Table 3-2 gives the memory map for the reserved vector locations and describes the differences among the TMS370 family members.
Table 3-2. Vector Address Map
Available on TMS370 Family Members
Memory Address
Description PACT INT 1-18 Timer 2B Trap 0-15 Reserved ADC Timer 2A SCI TX SCI RX Timer 1 SPI Interrupt 3 Interrupt 2 Interrupt 1 Reset
x0x x1x x2x NA NA Yes Yes NA NA Yes Yes Yes NA Yes Yes Yes Yes NA NA Yes Yes NA NA NA NA Yes Yes Yes Yes Yes Yes NA NA Yes Yes NA NA Yes Yes Yes Yes Yes Yes Yes Yes
x32 Yes NA Yes Yes Yes NA NA NA NA NA Yes Yes Yes Yes
x36 Yes NA Yes Yes Yes NA NA NA NA Yes NA NA Yes Yes
x4x x5x x6x x7x x8x x9x NA NA Yes Yes Yes Yes Yes Yes Yes NA Yes Yes Yes Yes NA NA Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes NA Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes NA NA Yes Yes Yes Yes NA NA Yes NA Yes Yes Yes Yes NA NA Yes Yes NA NA NA NA Yes NA Yes Yes Yes Yes NA NA Yes Yes Yes NA NA NA Yes NA NA NA Yes Yes
xAx NA NA Yes Yes NA Yes Yes Yes Yes NA Yes Yes Yes Yes
xBx NA NA Yes Yes Yes NA NA NA Yes NA Yes Yes Yes Yes
xCx NA NA Yes Yes Yes NA Yes Yes Yes NA NA NA Yes Yes
No. No Bytes
7F9Ch 7FBEh 7FC0h 7FE0h 7FECh 7FEEh 7FF0h 7FF2h 7FF4h 7FF6h 7FF8h 7FFAh 7FFCh 7FFEh
36 2 32 12 2 2 2 2 2 2 2 2 2 2
NA = Not Available ADC refers to ADC1, ADC2, or ADC3. SCI refers to SCI1 or SCI2.
3-14
Memory Map
3.3.4.1
Program ROM Module (TMS370C0xx, TMS370C3xx, and TMS370C4xx Devices Only)
The program ROM module consists of read-only memory, which is programmed at the time of device fabrication. The present ROM module sizes are 2K, 4K, 8K, 12K, 16K, 24K, 32K, and 48K. All accesses to the ROM module require two system clock cycles. ROM security is a feature of the TMS370C45x devices which inhibits the reading of data using any programmer (secured memory feature). Note: All TMS370 family devices contain mask-ROM space reserved for TI use only. This space includes locations 7FE0h through 7FEBh. This reserved area should not be used in your software algorithm, nor should it be used during mask-ROM or firmware development. The contents of the reserved locations are changed by TI only.
3.3.4.2
ROM-less Devices (TMS370C1xx and TMS370C2xx Devices Only)
Program memory for ROM-less devices must be off-chip. The TMS370 must be in the microprocessor mode to operate.
3.3.4.3
Program EPROM Modules (TMS370C6xx and TMS370C7xx Devices Only)
The program EPROM modules replace the program ROM for systems in prototype or small production runs. The modules presently consist of 8K, 16K, 24K, 32K, and 48K bytes of EPROM and the necessary programming control logic. Read access to the program EPROM is performed as normal memory read cycles. Write cycles require a special sequence of events. See subsection 6.4.3, page 6-13, for a detailed discussion of programming the EPROM modules. The EPROM can be written to only when VPP is applied to the MC pin and the VPPS bit (EPCTLx.6) is set. When VPP is applied to the MC pin, all on-chip EEPROM is in write protect override (WPO) mode, regardless of the state of the VPPS bit. This allows the EPROM to be protected while the EEPROM is in WPO.
CPU and Memory Organization
3-15
Memory Operating Modes
3.4 Memory Operating Modes
Devices that have the memory expansion can operate in one of two major memory modes.
-
Microcomputer (C) modes
J J
Microcomputer single-chip mode Microcomputer with external expansion
Microprocessor (P) modes
J J
Microprocessor without internal program memory Microprocessor with internal program memory
Devices that do not have the memory expansion can operate only in the microcomputer single-chip mode. Table 3-3 shows the devices and the modes that they can operate in.
Table 3-3. Memory Modes Available Per Device
Member of TMS370C Family x0x, x1x, x2x, x32, x36, x4x, x32 x36 x4x x7x, x8x, x9x, xAx, xBx, xCx Yes No No No Described in 15x, 25x No No Yes No 05x, 35x, 45x, 75x, x6x Yes Yes Yes Yes Subsection 3.4.1 3.4.2 3.4.3 3.4.4 Page 3-17 3-19 3-24 3-26
Mode Microcomputer Single Chip Microcomputer External Expansion Microprocessor Without Internal Program Memory Microprocessor With Internal Program Memory
For devices that have the memory expansion, the basic microcomputer and microprocessor operating modes are selected by the voltage level applied to the dedicated MC pin when the RESET pin goes inactive (high).
-
If the MC pin is low when the RESET signal goes high, then the processor enters the microcomputer mode. If the MC pin is high when the RESET signal goes high, then the processor enters the microprocessor mode.
Changing the MC pin alone does not change the memory mode. To change the memory operating mode, change the MC pin and then reset the device. Applying 12 volts to the MC pin after the RESET signal goes inactive high forces the device to enter the WPO mode.
3-16
Memory Operating Modes
Note:
Consideration for MC-Pin Voltage Application
If 12 V is applied to the MC pin during the low-to-high transition of the RESET pin, the results are unpredictable.
If the processor resets into a microcomputer mode, the software can change the internal system configuration registers to select the desired memory expansion configuration. Part of this configuration setup involves digital I/O port D. Each pin of port D can be programmed to serve one of three purposes: digital I/O, function A signal, or function B signal. Function A includes chip-select signals, which can be used in the microcomputer mode with external memory expansion. Function B includes signals used in either the microcomputer or the microprocessor modes to access external memory chips.
3.4.1
Microcomputer Single-Chip Mode
In the microcomputer single-chip mode, a TMS370 device functions as a selfcontained microcomputer with all memory and peripherals on the chip. This mode has no external address or data memory and allows more pins (used for the external buses in other modes) to be programmed as input/output pins. The single-chip mode maximizes the general-purpose I/O capability for realtime control applications. Figure 3-6 on page 3-18 shows a memory map for the microcomputer single-chip mode. During reset, the MC pin must remain at a low level to successfully enter the microcomputer mode. While the device is operating in the single-chip mode, external circuitry can place 12 volts on the MC pin to enter the WPO mode to alter protected EEPROM. Use the following steps to set a TMS370 device to the microcomputer singlechip mode: 1) Place a low logic level on the MC pin. 2) Bring the RESET pin to active low, then return RESET to its inactive high state. Note: The preceding procedure must be followed for devices that do not have the memory expansion, even though they operate only in the microcomputer single-chip mode.
CPU and Memory Organization
3-17
Memory Operating Modes
Figure 3-6. Microcomputer Single-Chip Mode
0000h 128 bytes RAM (0000h - 007Fh) Register file/stack 256 bytes RAM (0000h - 00FFh) 512 bytes RAM (0000h - 01FFh) 1K bytes RAM (0000h - 03FFh) RAM expansion 1.5K bytes RAM (0000h - 05FFh 3.5K bytes RAM (0000h - 0DFFh) Reserved Peripheral file Peripheral file Not available Reserved Data EEPROM expansion 512 bytes (1E00h - 1FFFh) data EEPROM Data EEPROM 256 bytes (1F00h - 1FFFh) data EEPROM 24K bytes ROM/EPROM (2000h - 7FFFh) 16K bytes ROM/EPROM (4000h - 7FFFh) 12K bytes ROM (5000h - 7FFFh) 8K bytes ROM (6000h - 7FFFh) Program memory (ROM/EPROM) 4K bytes ROM (7000h - 7FFFh) 2K bytes ROM (7800h - 7FFFh) interrupts and RESET vectors; TRAP vectors 1000h 10C0h 1100h 1E00h 1F00h 2000h 4000h 5000h 6000h 7000h 7800h 7FC0h 8000h 32K bytes ROM/EPROM (2000h - 9FFFh) A000h 48K bytes ROM/EPROM (2000h - DFFFh) E000h FFFFh In devices with more than 256 bytes of RAM, only the first 256-byte block can be used as registers or stacks. 0080h 0100h 0200h 0400h 0600h 0E00h
Not available
3-18
Memory Operating Modes
3.4.2
Microcomputer Mode With External Expansion (All Devices With Memory Expansion and Internal Program Memory)
The microcomputer mode also supports memory expansion to external memory or peripherals, while all on-chip memory (register file, ROM, and EPROM) remains active. Digital I/O ports, under the control of their associated port control registers, become external memory as follows:
-
Port A: 8-bit data memory Ports B and C: 16-bit address memory Port D: 8-bit control memory
Each pin that is not used for address, data, or control memory can be individually programmed as a general-purpose input/output pin. These bits are programmed by setting the digital I/O control registers in the peripheral file (see Section 4.4, page 4-18, for further information on programming I/O pins). The address memory and data memory are nonmultiplexed, eliminating the requirement for an external address/data latch and thereby lowering system cost. External interface decode logic can be reduced further by using the precoded chip-select outputs. The port D outputs can be programmed on a pin-by-pin basis to provide direct memory/peripheral chip-select or chip-enable functions. Each port D pin can be individually set to function A, function B, or general-purpose I/O. Function A When port D is set up to drive the chip-selection signals (function A), memory accesses to certain ranges of memory activate pins (refer to Table 3-4 on page 3-20, and Figure 3-7 on page 3-22): Applications that use more than one chip-select signal for the same address should set the unused chip selects (i.e., chip selects not currently used to select memory banks) to general-purpose high-level outputs. For example, an application that uses both CSE1 and CSE2 can set one of these signals as the active chip-select function and set the other as a general-purpose high-level output. The CSH1, CSH2, and CSH3 signals can be used as memory bank select signals under software control. The CSPF signal can be used as a chip select for the external expansion of the peripheral file. These chip-select control lines allow access to more than 112K bytes of external memory.
CPU and Memory Organization
3-19
Memory Operating Modes
Table 3-4. Memory-Enabled Pins Activated when Memory Accessed
Amount of Internal Memory in Device 4K, 8K, 12K, or 16K bytes Memory Areas Accessed 10C0h - 10FFh 2000h - 3FFFh 8000h - FFFFh Pins Activated Pin CSPF for 68-pin x50, x52, x53, and x56 devices if the pin is enabled Pins CSE1 and CSE2 for 64- and 68-pin x50, x52, x53, and x56 devices Pins CSH1, CSH2, and CSE3 for 68-pin x50, x52, x53, and x56 devices Pins CSH1 and CSE3 for 64-pin x50, x52, and x56 devices 24K or 32K bytes 10C0h - 10FFh A000h - BFFFh Pin CSPF for 68-pin x58, x67, and x68 devices if the pin is enabled Pins CSE1 and CSE2 for 64- and 68-pin x58 devices Pin CSE1 for 68-pin x67 and x68 devices C000h - FFFFh Pins CSH1 and CSH3 for 64-pin x58 devices Pins CSH1, CSH2, and CSH3 for 68-pin x58 devices Pin CSH1 for 68-pin x67 and x68 devices 48K bytes 10C0h - 10FFh E000h - EFFFh Pin CSPF for 68-pin x59 and x69 devices if the pin is enabled Pins CSE1 and CSE2 for 68-pin x59 devices Pin CSE1 for 68-pin x69 devices F000h - FFFFh Pins CSH1, CSH2, and CSH3 for 68-pin x59 devices Pin CSH1 for 68-pin x69 devices
These pins are activated providing that the pins are enabled by the appropriate port control register(s).
See Section 4.4 (page 4-18) for a description of the digital I/O port control registers and how the chip-select signals are enabled. Table 3-5 on page 3-21 shows a memory map for the microcomputer mode with function A expansion. Note: Areas Not Available for External Access
The RAM, data EEPROM, and internal memory expansion areas are not available for external access.
3-20
Memory Operating Modes
Table 3-5. Microcomputer Mode with Function A Expansion
Internal Program g Memory (R=ROM E=EPROM) 4KB R ('x50) Function A: Chip-Select Signals (Showing Memory Areas) Maximum External Memory 112KB CSE1 64/68 pin 2000h- 3FFFh (8KB) 2000h- 3FFFh (8KB) 2000h- 3FFFh (8KB) 2000h- 3FFFh (8KB) A000h- BFFFh (8KB) A000h- BFFFh (8KB) E000h- EFFFh (4KB) CSE2 64/68 pin 2000h- 3FFFh (8KB) 2000h- 3FFFh (8KB) 2000h- 3FFFh (8KB) 2000h- 3FFFh (8KB) A000h- BFFFh (8KB) A000h- BFFFh (8KB) E000h- EFFFh (4KB) CSH1 64/68 pin 8000h- FFFFh (32KB) 8000h- FFFFh (32KB) 8000h- FFFFh (32KB) 8000h- FFFFh (32KB) C000h- FFFFh (16KB) C000h- FFFFh (16KB) F000h- FFFFh (4KB) CSH2 68 pin 8000h- FFFFh (32KB) 8000h- FFFFh (32KB) 8000h- FFFFh (32KB) 8000h- FFFFh (32KB) C000h- FFFFh (16KB) C000h- FFFFh (16KB) F000h- FFFFh (4KB) CSH3 64/68 pin 8000h- FFFFh (32KB) 8000h- FFFFh (32KB) 8000h- FFFFh (32KB) 8000h- FFFFh (32KB) C000h- FFFFh (16KB) C000h- FFFFh (16KB) F000h- FFFFh (4KB) CSPF 68 pin 10C0h- 10FFh (64 B) 10C0h- 10FFh (64 B) 10C0h- 10FFh (64 B) 10C0h- 10FFh (64 B) 10C0h- 10FFh (64 B) 10C0h- 10FFh (64 B) 10C0h- 10FFh (64 B)
8KB R ('x52)
112KB
12KB R ('x53)
112KB
16KB R/E ('x56)
24KB R/E
112KB
('x67)
32KB R/E ('x58, 'x68)
24KB/'x67 64KB/'x77
64KB/'x58 24KB/'x68
48KB R/E ('x59, 'x69)
20KB/'x59 8KB/'x69
Chip-select pins CSE2, CSH2, and CSH3 are not available for the 'x6x device family. Devices '150, '250, '156, and '256 are ROMless. These devices cannot operate in microcomputer mode function A. KB = kilobytes, where 1KB = 102410.
CPU and Memory Organization
3-21
Memory Operating Modes
Figure 3-7. Microcomputer Mode With Function A Expansion
Chip Select Signals Function A Off Chip 'x50, 'x52, 'x53, & 'x56 Address 0000h 00FFh 0100h On-Chip Register file/stack RAM expansion 0FFFh 1000h CSPF 10BFh 10C0h 10FFh 1100h Peripheral file 0FFFh 1000h 10BFh 10C0h 10FFh 1100h Address 0000h 00FFh 0100h 'x58, 'x67, & 'x68 On-Chip Register file/stack RAM expansion Peripheral file 0FFFh 1000h 10BFh 10C0h 10FFh Data EEPROM expansion Data EEPROM 1100h Data EEPROM expansion Data EEPROM Address 0000h 00FFh 0100h 'x59 & 'x69 On-Chip Register file/stack RAM expansion Peripheral file
Peripheral expansion
Data EEPROM expansion Data EEPROM
1EFFh 1F00h CSE1 CSE2 Memory expansion 3FFFh 4000h 1FFFh 2000h
1EFFh 1F00h 1FFFh 2000h
1EFFh 1F00h 1FFFh 2000h
CSH1 CSH2 7FFFh CSH3
Program memory (ROM/EPROM) 4K bytes or 8K bytes or 12K bytes or 16K bytes 9FFFh A000h BFFFh C000h
Program memory (ROM/EPROM)
Program memory (ROM/EPROM)
24K bytes or 32K bytes
48K bytes
Memory expansion
DFFFh E000h EFFFh F000h
FFFFh
FFFFh
FFFFh
1) Chip select signals CSH2 and CSPF are not available in 64-pin devices. 2) Chip select signals CSE1, CSH2, and CSH3 are not available for x6x devices. '150, '250, '156, and '256 are ROMless devices. These devices cannot operate in Microcomputer Mode Function A.
3-22
Memory Operating Modes
Figure 3-8. Microcomputer Mode With Function B Expansion
Chip Select Signals Function B Off Chip 'x50, 'x52, 'x53, & 'x56 Address 0000h 00FFh 0100h EDS 0FFFh 1000h 10BFh 10C0h 10FFh 1100h On-Chip Register file/stack RAM expansion Peripheral file 0FFFh 1000h 10BFh 10C0h 10FFh 1100h Address 0000h 00FFh 0100h 'x58, 'x67, & 'x68 On-Chip Register file/Stack RAM expansion Peripheral file 0FFFh 1000h 10BFh 10C0h 10FFh 1100h Address 0000h 00FFh 0100h 'x59 & 'x69 On-Chip Register file/stack RAM expansion Peripheral file
Peripheral expansion
Data EEPROM expansion Data EEPROM
Data EEPROM expansion Data EEPROM
Data EEPROM expansion Data EEPROM
1EFFh 1F00h 1FFFh 2000h Memory expansion 3FFFh 4000h
1EFFh 1F00h 1FFFh 2000h
1EFFh 1F00h 1FFFh 2000h
7FFFh
Program memory (ROM/EPROM) 4K bytes or 8K bytes or 12K bytes or 16K bytes 9FFFh A000h
Program memory (ROM/EPROM)
Program memory (ROM/EPROM)
24K bytes or 32K bytes 48K bytes
Memory expansion
DFFFh E000h
FFFFh
FFFFh
FFFFh
Function B All predecoded chip selects have the same timing as the external data strobe (EDS) signal (see Chapter 18, Electrical Specifications). EDS is a function B (microprocessor mode) signal that goes low whenever an access to external memory is made. Figure 3-8 shows a memory map for the microcomputer mode with function B expansion.
CPU and Memory Organization
3-23
Memory Operating Modes
Table 3-6. Microcomputer with Function B Expansion
Internal Program Memory (R=ROM, E=EPROM) 4K bytes R ('x50) 8K bytes R ('x52) 12K bytes R ('x53) 16K bytes R/E ('x56) 24K bytes R/E ('x67) 32K bytes R/E ('x58, 'x68) 48K bytes R/E ('x59, 'x69) Function B: Chip-Select Signal EDS 64/68 Pins 10C0h to 10FFh (64 bytes) 2000h to 3FFFh (8K bytes) 8000h to FFFFh (32K bytes) 10C0h to 10FFh (64 bytes) 2000h to 3FFFh (8K bytes) 8000h to FFFFh (32K bytes) 10C0h to 10FFh (64 bytes) 2000h to 3FFFh (8K bytes) 8000h to FFFFh (32K bytes) 10C0h to 10FFh (64 bytess) 2000h to 3FFFh (8K bytes) 8000h to FFFFh (32K bytes) 10C0h to 10FFh (64 bytes) A000h to FFFFh (24K bytes) 10C0h to 10FFh (64 bytes) A000h to FFFFh (24K bytes) 10C0h to 10FFh (64 bytes) E000h to EFFFh (4K bytes) Maximum External Memory 40K bytes
40K bytes
40K bytes
40K bytes
24K bytes 24K bytes 4K bytes
Table 3-6 shows the memory addresses for the function B chip-select signal. See Section 4.4 on page 4-18 for a description of the digital I/O port control registers and how the chip-select signals are enabled. To place a device in to the microcomputer mode with external expansion (the device must have bus expansion), execute the following steps: 1) Place a low logic level on the MC pin. 2) Pull the RESET pin active low, then return RESET to its inactive high state. 3) Program the digital I/O registers to select the chip-select or control signals needed (function A or function B).
3.4.3
Microprocessor Mode Without Internal Memory (Memory Expansion Devices Only)
When a device is activated in the microprocessor mode, the register file and data EEPROM remain active, but the on-chip program ROM or EPROM is disabled. The EDS signal goes low when a memory access is made to addresses 1020h-102Fh, 10C0h-10FFh, and 2000h-FFFFh. The program area, the re-
3-24
Memory Operating Modes
set vector, interrupt vectors, and trap vectors must be located in off-chip memory locations. When a device is reset into the microprocessor mode, the digital I/O port D registers are set to function B expansion memory control signals. The chip-select signals are not available in function B. Ports B and C are set up as the external address bus, and port A is set up to be the external data bus. Software cannot change the digital I/O configuration. Figure 3-9 shows a memory map for the microprocessor mode without internal memory.
Figure 3-9. Microprocessor Mode Without Internal Memory
Microprocessor chip-select signals Address 0000h Register file/stack
EDS
On-chip
00FFh 0100h RAM expansion Off-chip Peripheral expansion 0FFFh 1000h Peripheral file 101Fh 1020h 102Fh 1030h 10BFh 10C0h 10FFh 1100h
Peripheral expansion
1EFFh 1F00h 1FFFh 2000h
Data EEPROM expansion Data EEPROM
Memory expansion
FFFFh
CPU and Memory Organization
3-25
Memory Operating Modes
To place a device in the microprocessor mode without internal memory, do the following: 1) Place a high logic level on the MC pin. 2) Pull the RESET pin to active low, then return RESET to its inactive high state.
3.4.4
Microprocessor Mode With Internal Program Memory (Memory Expansion Devices Only)
Once the device is in microprocessor mode, the internal program memory can be re-enabled by clearing the MEMORY DISABLE bit (SCCR1.2). This mode is exactly the same as the microprocessor mode without internal memory except that when the internal memory is enabled, the EDS signal is no longer active during memory accesses to addresses 1020h-102Fh, and addresses that internal memory occupies. For example, when the MEMORY DISABLE bit (SCCR1.2) is cleared, memory accesses to addresses 1020h-102Fh and 5000h-7FFFh (x53 device) addresses access internal program memory; while EDS maintains the ability to access external memory locations 2000h-4FFFh and 8000h-FFFFh. This is shown in Table 3-7 and in Figure 3-10 (page 3-28), together with other TMS370 memory expansion devices. The actual amount of program memory available depends on the device. In this mode, accesses to memory addresses 1020h through 102Fh are not valid for external memory or for the internal port control registers. This peripheral frame should not be used in this mode. To use this mode, external memory must be implemented at memory addresses 7FFEh and 7FFFh to contain the reset vector. This memory can be switched in and out with the internal memory by clearing and setting the memory disable bit. Figure 3-10 (page 3-28) shows a memory map for the microprocessor mode with internal program memory.
3-26
Memory Operating Modes
Table 3-7. Microprocessor Mode with Internal Program Memory
Internal Memory Disabled (SCCR1.2=1) Device TMS370Cx50 Active Internal Memory -- Active External Memory 10C0h - 10FFh 2000h - FFFFh 10C0h - 10FFh 2000h - FFFFh 10C0h - 10FFh 2000h - FFFFh 10C0h - 10FFh 2000h - FFFFh 10C0h - 10FFh 2000h - FFFFh 10C0h - 10FFh 2000h - FFFFh 10C0h - 10FFh 2000h - FFFFh Internal Memory Enabled (SCCR1.2=0) Active Internal Memory 1020h - 102Fh 7000h - 7FFFh 1020h - 102Fh 6000h - 7FFFh 1020h - 102Fh 5000h - 7FFFh 1020h - 102Fh 4000h - 7FFFh 1020h - 102Fh 2000h - 7FFFh 1020h - 102Fh 2000h - 9FFFh 1020h - 102Fh 2000h - DFFFh Active External Memory 10C0h - 10FFh 2000h - 6FFFh 8000h - FFFFh 10C0h - 10FFh 2000h - 5FFFh 8000h - FFFFh 10C0h - 10FFh 2000h - 4FFFh 8000h - FFFFh 10C0h - 10FFh 2000h - 3FFFh 8000h - FFFFh 10C0h - 10FFh 2000h - 1FFFh 8000h - FFFFh 10C0h - 10FFh 2000h - 1FFFh A000h - FFFFh 10C0h - 10FFh 2000h - 1FFFh E000h - FFFFh
TMS370Cx52
--
TMS370Cx53
--
TMS370Cx56
--
TMS370Cx67
--
TMS370Cx58, TMS370Cx68 TMS370Cx59, TMS370Cx69
--
--
To place a device in the microprocessor mode with internal program memory, use the following steps: 1) Place a high logic level on the MC pin. 2) Take the RESET pin active low, then return RESET to its inactive high state. 3) The CPU reads the reset vectors from external memory (7FFEh/7FFFh). The program pointed to by the vectors must include code to clear the MEMORY DISABLE bit (SCCR1.2) to enable the internal memory. The internal program memory becomes available. (The SCCR1 register is described in subsection 4.3.2 on page 4-15).
CPU and Memory Organization
3-27
Memory Operating Modes
Figure 3-10. Microprocessor Mode With Internal Program Memory
Chip select signals 'x50 On-chip 0000h Register file/stack RAM expansion Peripheral file Data EEPROM expansion Data EEPROM 2000h 'x52 On-chip Register file/stack RAM expansion Peripheral file Data EEPROM expansion Data EEPROM 'x53 On-chip Register file/stack RAM expansion Peripheral file Data EEPROM expansion Data EEPROM 'x56 On-chip Register file/stack RAM expansion Peripheral file Data EEPROM expansion Data EEPROM 'x67 On-chip Register file/stack RAM expansion Peripheral file Data EEPROM expansion Data EEPROM 'x58 & 'x68 On-chip Register file/stack RAM expansion Peripheral file Data EEPROM expansion Data EEPROM 'x59 & 'x69 On-chip Register file/stack RAM expansion Peripheral file Data EEPROM expansion Data EEPROM Address 0000h 0100h
EDS Off-chip
1000h 10C0h 1100h 1F00h 2000h
4000h 5000h ROM/ EPROM 16K bytes ROM/ EPROM 24K bytes ROM/ EPROM 32K bytes
4000h 5000h ROM/ EPROM 48K bytes 6000h 7000h 8000h A000h
SCCR1.2
set to 0 ROM 4K bytes 8000h ROM 8K bytes
ROM 12K bytes
E000h FFFFh x59 & x69 x58 & x68 x67 x56 x53 x52 x50 FFFFh
After the P is reset, the CPU reads the reset vectors from external memory (7FFEh/7FFFh) until the MEMORY DISABLE bit (SCCR1.2) is cleared by software, then the internal memory is enabled.
3.4.5
Memory Mode Summary
Table 3-8 summarizes the features of each memory mode and outlines the procedure for putting the TMS370 device into each mode.
3-28
Memory Operating Modes
Table 3-8. Operating Mode Summary
Computer
Feature Devices Single-Chip Mode All TMS370s with internal program memory Internal Digital I/O Computer With Expanded Memory Mode Devices with memory expansion and internal program memory Internal Digital I/O Function A Function B Optional 1) Place logic 0 on the MC pin. 2) Set the RESET pin to active low, then release RESET. 3) Set digital I/O registers to function A/B. Processor with Internal Memory Mode Devices with memory expansion and internal program memory Internal and external Function B
Processor Mode Devices with memory expansion External Function B
Program Memory Ports A, B,C,D
Predecoded CS (chip selects) Procedure to enter the mode
No 1) Place logic 0 on the MC pin. 2) Set the RESET pin to active low, then release RESET.
No 1) Place logic 1 on the MC pin. 2) Take the RESET pin active low, then release RESET. 3) Enable internal memory (clear SCCR1.2).
No 1) Place logic 1 on the MC pin. 2) Take the RESET pin active low, then release RESET.
Function A: Port D= Chip-select signals for 68-pin CSE1, CSE2, CSH1, CSH2, CSH3, and CSPF (see Section 4.4, pp. 4-18). = Chip-select signals for 64 pin CSE1, CSE2, CSH1, and CSH3 (see Section 4.4). Function B: Port D = Expansion memory control signals OCF, EDS, and WAIT (see Section 4.4).
CPU and Memory Organization
3-29
3-30
Running Title--Attribute Reference
Chapter 4
System and Digital I/O Configuration
This chapter discusses the system and I/O configuration. Features and options are described, as well as the registers that control the configuration. Examples of how to set specific configurations are also given. This chapter covers the following topics:
Topic
4.1 4.2 4.3 4.4
Page
System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 Low-Power and Idle Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 System Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13 Digital I/O Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18
Chapter Title--Attribute Reference
4-1
System Configuration
4.1 System Configuration
The system configuration is controlled and monitored by the first three registers of peripheral file frame 1. These registers' names, designations, addresses, and peripheral file (PF) register numbers are shown below and in Figure 4-1. The PF numbers are used by peripheral file instructions; for example, MOV #00h,P010 clears PF P010 at address 1010h. Name System control and configuration register 0 System control and configuration register 1 System control and configuration register 2 Designation Address PF SCCR0 SCCR1 SCCR2 1010h 1011h 1012h P010 P011 P012
Figure 4-1. Peripheral File Frame 1: System Configuration and Control Registers
Bit Names/Functions Register Name
SCCR0
Addr
1010h
PF
P010
Bit 7
COLD START (RW-*)
Bit 6
OSC POWER (RP-0)
Bit 5
PF AUTOWAIT (RP-0)
Bit 4
OSC FLT FLAG (RW-0) AUTOWAIT DISABLE (RP-0) BUS STEST (RP-0)
Bit 3
MC PIN WPO (R-0)
Bit 2
MC PINDATA (R-*) MEMORY DISABLE (RP-*)
Bit 1
--
Bit 0
P/C MODE (R-*)
SCCR1
1011h
P011
-- HALT/ STANDBY (RP-0)
-- PWRDWN/ IDLE (RP-0)
--
--
--
-- PRIVILEGE DISABLE (RS-0)
SCCR2
1012h
P012
--
CPU STEST (RP-1)
--
INT1 NMI (RP-0)
Note:
Shaded boxes denote privileged mode bits that can be written to only in the privileged mode.
4.1.1
Privilege Mode
The TMS370 architecture allows you to configure the system and peripherals by software to meet the requirements of a variety of applications. The privilege mode of operation ensures the integrity of the system configuration, once it is defined for an application. The shaded boxes in Figure 4-1 denote privilege mode bits; that is, you can write to these bits only in the privilege mode. Following a hardware reset, the processor operates in the privilege mode. In this mode, peripheral file registers have unrestricted read/write access. The application program can configure the system during the initialization sequence following a reset. As the last step of a system initialization, set the PRIVILEGE DISABLE bit (SCCR2.0) to enter the nonprivilege mode and prevent changes to specific control bits within the peripheral file.
4-2
System Configuration
Table 4-1 shows the system configuration bits that are write-protected during the nonprivilege mode. These bits should be configured by software before exiting the privilege mode.
Table 4-1. Privilege-Mode Configuration Bits
Register SCCR0 SCCR1 SCCR2 Bit PF AUTOWAIT OSC POWER MEMORY DISABLE AUTOWAIT DISABLE PRIVILEGE DISABLE INT NMI CPU STEST BUS STEST PWRDWN/IDLE HALT/STANDBY SPI STEST SPI PRIORITY SPI ESPEN SCI STEST SCITX PRIORITY SCIRX PRIORITY SCI ESPEN T1 STEST T1 PRIORITY T2A STEST T2A PRIORITY T2B STEST T2B PRIORITY AD STEST AD PRIORITY AD ESPEN PACT WD PRESCALE SELECT 0 PACT WD PRESCALE SELECT 1 PACT MODE SELECT PACT GROUP 3 PRIORITY PACT GROUP 2 PRIORITY PACT GROUP 1 PRIORITY PACT STEST PACT PRESCALE SELECT 0 PACT PRESCALE SELECT 1 PACT PRESCALE SELECT 2 PACT PRESCALE SELECT 3 FAST MODE SELECT Bit Name Peripheral File Automatic Wait Cycle y Oscillator Power Memory Disable Automatic Wait-State Disable Privilege Mode Disable Interrupt 1, Nonmaskable Interrupt CPU Factory Test BUS Factory Test Powerdown/Idle Halt/Standby SPI Factory Test SPI Interrupt Priority Select SPI emulator suspend enable SCI Factory Test SCI Transmitter Interrupt Priority Select SCI Receiver Interrupt Priority Select SCI emulator suspend enable Timer 1 Factory Test Timer 1 Interrupt Priority Select Timer 2A Factory Test Timer 2A Interrupt Priority Select Timer 2B Factory Test Timer 2B Interrupt Priority Select AD Factory Test AD Interrupt Priority Select AD emulator suspend enable PACT Watchdog Prescale Select 0 PACT Watchdog Prescale Select 1 PACT Mode Select PACT Group 3 Priority Select PACT Group 2 Priority Select PACT Group 1 Priority Select PACT Stest PACT Prescale Select 0 PACT Prescale Select 1 PACT Prescale Select 2 PACT Prescale Select 3 Fast Mode Select
SPIPRI
SCIPRI
T1PRI T2APRI T2BPRI ADPRI
PACTPRI
PACTSCR
The only way to change the privilege bits after leaving the privilege mode is to reset the processor and program the control registers. The write protection override (WPO) used for the EEPROM has no effect on the privilege bits. Note that privilege mode has no effect on timer 1 (T1) watchdog (WD) bits. These bits are protected in a separate manner.
System and Digital I/O Configuration
4-3
System Configuration
4.1.2
Clock Options
The TMS370 family provides two clock options which are referred to as divideby-1 (phase-locked loop) and divide-by-4 (standard oscillator). Both, the divide-by-1 and divide-by-4 options are configurable during the manufacturing process of a TMS370 microcontroller. The ROM-masked devices offer both options to meet system engineering requirements. Only one of the two clock options is allowed on each ROM device. The divide-by-1 clock module option provides the capability for reduced electromagnetic interference (EMI) with no added cost. The divide-by-1 option provides a one-to-one match of the external resonator frequency (CLKIN) to the internal system clock (SYSCLK) frequency, whereas the divide-by-4 option produces a SYSCLK which is one-fourth the frequency of the external resonator. Inside the divide-by-1 module, the frequency of the external resonator is multiplied by four, and the clock module then divides the resulting signal by four to provide the four internal system clock signals. The resulting SYSCLK is equal to the resonator frequency. These are formulated as follows:
Divide-by-4 option: Divide-by-1 option: SYSCLK = SYSCLK = external resonator frequency 4 = CLKIN 4
external resonator frequency x 4 = CLKIN 4
The main advantage of choosing a divide-by-1 oscillator is the improved EMI performance. The harmonics of low-speed resonators extend through less of the emissions spectrum than the harmonics of faster resonators. The divideby-1 option also reduces the resonator speed by 4x, resulting in a steeper decay of emissions produced by the oscillator.
4.1.3
Oscillator Fault
The processor contains a system of circuits to monitor the oscillator operation and to detect and contain major oscillator problems. This enhances processor and system reliability and aids in system recovery from a crash that is caused by a temporary fault. The circuit stops the processor whenever circuitry detects an out-of-range oscillator operation. The oscillator fault detection circuitry consists of:
4-4
An amplitude detector to detect whether the oscillator signal has a proper voltage level. A frequency detector to sense when the oscillator frequency goes too low. The oscillator fault detection circuit will always trigger below 20 kHz and never above 500 kHz.
System Configuration
The oscillator circuitry is designed to delay operation of the device until a stable clock signal is received. This protects against slow crystal startup times coming out of a halt mode or after an oscillator fault when the input clock cannot be operating at the correct voltage range. Device operation remains suspended until the input clock signal is within the required voltage range. Whenever the oscillator fault detection circuitry detects a major oscillator problem, the processor generates a reset by pulling the RESET pin low for at least eight cycles; this causes external devices to reset with the processor. After a reset, the program checks the oscillator fault flag (OSC FLT FLAG, SCCR0.4), the cold start flag (COLD START, SCCR0.7), and the watchdog reset key (WDRST) to determine the source of the reset. A reset does not clear these flags.
4.1.4
Automatic Wait States
If an application system uses peripherals or expansion memory with access times slower than those of the TMS370 processor, wait states are required. Other microprocessors require complex additional circuitry, but the TMS370 series provides for the automatic addition of wait states that can slow the processor's access time to a compatible period. The TMS370 series has a WAIT pin that can hold the processor in a wait state indefinitely. The following two bits control the insertion of the automatic wait state:
-
The PF AUTOWAIT bit (SCCR0.5) that controls the external frames of the peripheral file so that these frames can access off-chip peripherals. The AUTOWAIT DISABLE bit (SCCR1.4) that controls all other external memory.
When the AUTOWAIT DISABLE bit equals 1, any access to external memory (excluding the PF file) takes two system clock cycles to complete. When AUTOWAIT DISABLE bit equals 0, the access takes three system clock (SYSCLK) cycles. The reset value of this bit selects the slower 3-cycle access.
When the PF AUTOWAIT bit equals 1, memory access to the external peripheral files takes four SYSCLK cycles. This bit does not affect the accesses to the internal registers. When the PF AUTOWAIT bit equals 0, the memory is treated like any external memory, and the AUTOWAIT DISABLE bit selects the number of SYSCLK cycles per access as either two or three cycles. Table 4-2 summarizes the effects of the wait-state control bits.
System and Digital I/O Configuration
4-5
System Configuration
Table 4-2. Wait-State Control Bits
Wait State Control Bits PF AUTOWAIT Bit (SCCR0.5) 0 0 1 1 AUTOWAIT DISABLE Bit (SCCR1.4) 0 1 0 1 No. of Clock Cycles per Access
PF File 3 2 4 4
External Memory 3 2 3 2
An external device can pull the WAIT input pin low and cause the processor to wait an indefinite number of clock cycles for its data. When the wait line is released, the processor resynchronizes with the rising edge of the SYSCLK signal and continues with the program. The WAIT pin is sampled only during external memory cycles. Note: Tie Un-needed WAIT Line to VCC
When constructing an application circuit with expansion memory, do not forget to connect any unneeded WAIT line to VCC.
4-6
Low-Power and Idle Modes
4.2 Low-Power and Idle Modes
The OTP, mask-ROM, and reprogrammable EPROM devices have two lowpower (powerdown) modes and an idle mode. For mask-ROM devices, lowpower modes can be disabled permanently through a programmable contact at the time when the mask is manufactured (refer to Chapter 19, Customer Information, for order information about mask-ROM devices). Note: Low-Power Mode Difference
Low-power modes operate differently for TMS370Cxxx, TMS370CxxxA, and TMS370CxxxB devices. Refer to Section A.3, page A-4. The low-power modes reduce the operating power by reducing or stopping the activity of various modules. The processor has the following two types of lowpower modes: the halt mode and the standby mode (see Table 4-3). Bits 6 and 7 of register SCCR2 select the halt, standby, or idle modes.
-
The standby mode stops the internal clock in every module except the T1 module. The T1 module continues to run and can bring the processor out of the standby mode. In devices with the PACT module, only the default timer and the first command are active in standby mode. The halt mode stops the internal clock. This stops processing in all of the modules, resulting in the lowest amount of power consumption. The idle mode (which is not a low-power mode) is a state that waits for the next interrupt.
Executing an IDLE instruction causes the processor to enter one of the two low-power modes or the simple idle mode, depending on SCCR2.6 and SCCR2.7. The low-power and idle-mode selection bits are summarized in Table 4-3.
Table 4-3. Powerdown/Idle Control Bits
Powerdown Control Bits PWRDWN/IDLE (SCCR2.6) 1 1 0 HALT/STANDBY (SCCR2.7) 0 1 Don't care Mode Selected Standby Halt Idle
When low-power modes are disabled through a programmable contact in the mask-ROM devices, writing to the SCCR2.6-7 bits is ignored. In addition, if you execute an IDLE instruction when low-power modes are disabled through a programmable contact, the device always enters the idle mode.
System and Digital I/O Configuration
4-7
Low-Power and Idle Modes
To provide a method of exiting low-power modes for mask-ROM devices, INT1 is automatically enabled as a nonmaskable interrupt (NMI) during low-power modes when the hard WD mode is selected. This means that the NMI is always generated, regardless of the status of the interrupt enable flags and the values of the status bits (INT1 PRIORITY bit [INT1.1], INT1 ENABLE bit [INT1.0], INT1 NMI bit [SCCR2.1]), and global interrupt enable flags of the status register (IE1 and IE2). See subsection 7.7.2.1, page 7-26, for more information. The low-power modes and the methods of exiting these modes are discussed further in subsections 4.2.1 and 4.2.2 on page 4-9. In the standby and halt modes, the digital output ports remain active. In addition, the following information is retained:
-
The CPU registers: Program counter (PC) Status (ST) Stack pointer (SP)
J J J
The contents of the RAM The digital output data registers Control and status registers of all the modules, including the timer contents and the WD counter
If the serial peripheral interface (SPI) or serial communications interface (SCI--SCI1 or SCI2) is in the process of receiving or transmitting data when a low-power mode is entered, the data received or transmitted can be lost. The results of an analog-to-digital (AD) conversion (ADC1, ADC2, or ADC3) or an EEPROM write process is invalid when a low-power mode is entered. Use caution when using low-power modes in conjunction with the WD mode; the WD stops counting in both low-power modes. In the standard WD option, if the program executes an IDLE instruction without the interrupts enabled (described in subsections 4.2.1 and 4.2.2, page 4-9), then only a reset can start the processor running again. For additional information regarding WD operation during low-power modes, see subsection 7.7.2.1 (page 7-26) and Section 7.8 (page 7-29).
4.2.1
Standby Mode
The standby mode uses less power than the normal operating mode but more than the halt mode. The standby mode stops the clocks to every module except the T1 module or the PACT module. These modules can bring the processor out of this low-power mode if the interrupts are enabled. To enter the standby mode, use the following steps:
4-8
Low-Power and Idle Modes
-
Set the PWRDWN/IDLE bit (SCCR2.6) Clear the HALT/STANDBY bit (SCCR2.7). The next execution of an IDLE instruction causes the processor to enter the standby mode.
You can cause the processor to exit the standby mode by any one of the following methods: A reset An external interrupt 1, 2, or 3 (if enabled) A low level on the SCIRXD pin if the SCI RX interrupt and receiver are enabled (described in Chapter 9, Serial Communications Interface 1 (SCI1) Module -- subsections 9.8.2 (page 9-24) and 9.8.5 (page 9-29), and Chapter 10, Serial Communications Interface 2 (SCI2) Module -- subsections 10.8.2 (page 10-20) and 10.8.5 (page 10-24)).
Note: When using the SCIRXD pin as a method of exiting the standby mode, the first character received will wake-up the device; therefore, the first character will be misinterrupted and not be treated as valid data. Subsequent data transmissions are valid.
-
A T1 or PACT's first command/definition entry interrupt, if enabled
For additional standby mode power savings, see subsection 4.2.3 on page 4-10.
4.2.2
Halt Mode
The halt mode stops all internal operations and clocks (including T1 and the PACT counter) and uses the least power of the low-power modes. T1 cannot bring the processor out of this low-power mode. To select the halt mode, use the following steps:
-
Set the PWRDWN/IDLE bit (SCCR2.6) Set HALT/STANDBY bit (SCCR2.7) Execute an IDLE instruction.
Note: The OSC power bit (SCCR0.6) must be cleared before entering the HALT mode in order to exit the HALT mode properly.
System and Digital I/O Configuration
4-9
Low-Power and Idle Modes
You can cause the processor to exit the halt mode by any one of the following methods:
-
A reset An external Interrupt 1, 2, or 3 if enabled A low level on the SCIRXD pin if the SCI RX interrupt and receiver are enabled (described in Chapter 9, Serial Communications Interface 1 (SCI1) Module, and Chapter 10, Serial Communications Interface 2 (SCI2) Module.
Note: When using the SCIRXD pin as a method of exiting the halt mode, the first character received will wake-up the device; therefore, the first character will be misinterrupted and not be treated as valid data. Subsequent data transmissions are valid.
4.2.3
Using Interrupts to Exit From the Halt Mode
You must be aware of the following items when using an interrupt to exit the halt mode:
-
Interrupts enabled during the halt mode are level-sensitive and not edgesensitive. The interrupt must be at the inactive level when the device enters the halt mode. The processor exits the halt mode when the interrupt goes from the inactive level to the active level. Bit 2 in the interrupt control register determines the active and inactive levels.
J J
When the INT2 POLARITY bit (INT2.2) is selected to be triggered on the rising edge, the active level is high. When the INT2 POLARITY bit is selected to be triggered on the falling edge, the active level is low.
-
The interrupt should be at an active level until the oscillator is stable enough to generate an interrupt.
4-10
Low-Power and Idle Modes
-
If the halt mode is entered with the interrupt at an active level, the following actions occur:
J J
For devices with a divide-by-4 clock, the processor exits the halt mode and enters the idle mode. For devices with a PLL clock, an oscillator fault flag (SCCR0.4) is set causing a system reset to occur.
-
When the selected interrupt edge is detected, the program continues.
Refer to Figure 4-2 and Figure 4-3 for the differences between the correct and incorrect methods for entering the halt mode.
Figure 4-2. Correct Method to Enter Halt Mode
Exits halt mode INTx pin (Polarity = 0 active low)
Execute IDLE instruction
SYSCLK
Figure 4-3. Improper Method to Enter Halt Mode
Exits idle mode INTx pin (Polarity = 0 active low)
Execute IDLE instruction Enters idle mode instead of halt mode
SYSCLK
System and Digital I/O Configuration
4-11
Low-Power and Idle Modes
If this halt-mode condition exists and the device uses the WD, then the WD can reset while the program is waiting and unable to service the WD in the normal power idle mode. The same considerations apply when you use the SCIRXD pin to exit the halt mode. The processor exits halt mode anytime an enabled SCI receiver and pin detect a low level on SCIRXD.
4.2.4
Oscillator Power Bit
The OSC POWER bit (SCCR0.6) allows additional standby mode power savings. When in effect, this feature reduces the oscillator drive current and disables the oscillator fault detection circuitry. The OSC POWER bit can be used effectively with a frequency of up to 3-MHz SYSCLK. If the SYSCLK frequency is greater than 3 MHz, this bit must be cleared. For power reduction specifications, see Chapter 18, Electrical Specifications.
4-12
System Control Registers
4.3 System Control Registers
Each system control register is summarized in the following charts with definitions of each control bit.
4.3.1
System Control and Configuration Register 0 (SCCR0)
System Control and Configuration Register 0 (SCCR0) [Memory Address 1010h]
Bit #
P010
7
COLD START RW-*
6
OSC POWER RP-0
5
PF AUTOWAIT RP-0
4
OSC FLT FLAG RW-0
3
MC PIN WPO R-0
2
MC PIN DATA R-*
1
--
0
P/C MODE R-*
R = Read, W = Write, P= Privilege write only, C = Clear only, -n = Value of the bit after the register is reset, -* = See bit description Bit 7 COLD START. Cold Start Flag. This bit indicates whether the microcontroller is coming out of a powerup reset. This bit does not change during a reset under normal power. 0 = No full-power cycle occurred since last writing a 0 to this bit. This setting is used to determine the source of a reset. 1 = A full-power cycle has occurred since last writing a 0 to this bit. If the application does not zero this bit, the bit has no meaning. Only writing a 0 to this bit can clear the COLD START flag. This bit is set to 1 only after the VCC is off for several hundred milliseconds. As a result, you cannot use this bit to detect short VCC glitches or brownout conditions. Note: COLD START Bit Considerations The COLD START bit is not designed to detect short VCC glitches or brownout conditions. Bit 6 OSC POWER. Oscillator Power. This bit controls an oscillator power reduction feature. When this feature is in effect, the oscillator drive current is reduced, and the oscillator fault detection circuitry is powered down. Current reduction is most useful in the standby mode. However, when this bit is set during normal operation, the operating mode power consumption can be slightly reduced. Before entering the HALT mode, the OSC POWER bit (SCCR0.6) must be cleared in order to exit the HALT mode properly. This feature is effective up to a 3-MHz maximum SYSCLK frequency. If the SYSCLK frequency is greater than 3 MHz, this bit must be cleared. For power reduction specifications, see Chapter 18, Electrical Specifications.
System and Digital I/O Configuration
4-13
System Control Registers
0 = No oscillator drive current reduction. 1 = Oscillator drive current reduction. Bit 5 PF AUTOWAIT. Peripheral File Automatic Wait Cycle. 0 = Any access to the peripheral file will take two system clock cycles with no system auto wait (bit 4 of SCCR1=1), or three system clock cycles with the system autowait on (bit 4 of SCCR1=0). (See subsection 4.1.4, page 4-5.) 1 = Any access to the upper four frames of the peripheral file (address 10C0h to 10FFh) will take four system clock cycles to complete. This eases interface requirements for peripheral devices slower than the TMS370 processor. Normal full-speed operation consists of two system clock cycles per access. Bit 4 OSC FLT FLAG. Oscillator Fault Flag. This flag is reset upon an initial power-up reset. A reset under power does not affect this flag. Therefore, this bit can be polled to determine the source of a reset. 0 = No oscillator fault found. 1 = Oscillator fault found. Oscillator period is now or was out of the correct operating range. The oscillator fault detect circuit always triggers below 20 KHz and never above 500 kHz. Bit 3 MC PIN WPO. Mode Control Pin Write Protect Override Status. This bit indicates whether the voltage on the MC pin is adequate for WPO functions. (If this bit is set, then bit 2 is also set.) 0 = Voltage on the MC pin is not enough to override write protection. 1 = Voltage on the MC pin is enough for write-protect override. Protected bits in data EEPROM and program EPROM can now be written to. Override voltage is nominally 12 volts. Bit 2 MC PIN DATA. Mode Control Pin Data. This bit shows the current status of the MC pin. 0 = Voltage on the MC pin is a logic 0 level. 1 = Voltage on the MC pin is a logic 1 level. Bit 1 Bit 0 Reserved. Read data is indeterminate. P/C MODE. Microprocessor/Microcomputer Mode. This bit indicates the current operating mode (as described in subsection 3.4, page 3-16). 0 = Currently operating in microcomputer mode. 1 = Currently operating in microprocessor mode.
4-14
System Control Registers
4.3.2
System Control and Configuration Register 1 (SCCR1)
System Control and Configuration Register 1 (SCCR1) [Memory Address 1011h]
Bit #
P011
7
--
6
--
5
--
4
AUTOWAIT DISABLE RP-0
3
--
2
MEMORY DISABLE RP-*
1
--
0
--
R = Read, P= Privilege write only, -n = Value of the bit after the register is reset, -* = See bit description Bits 7-5 Bit 4 Reserved. Read data is indeterminate. AUTOWAIT DISABLE. Automatic Wait State Disable. This bit is cleared after a reset, and causes an extra cycle to be added to all external bus accesses to accommodate slower memory. 0 = Enables the autowait feature and makes the external bus access three system clock cycles long. 1 = Disables the autowait feature and makes the external bus access two system clock cycles long. Changes to this bit can occur only in the privilege mode. If the PF AUTOWAIT bit in SCCR0 is set, external peripheral file access takes four SYSCLK cycles, regardless of the AUTOWAIT DISABLE bit. Bit 3 Bit 2 Reserved. Read data is indeterminate. MEMORY DISABLE. This bit enables or disables the internal program memory (memory addresses affected are device dependent -- refer to Table 3-6 on page 3-24). This bit does not affect data EEPROM or internal RAM. A reset initializes this bit to the state of the MC pin. Changes to this bit can occur only in the privilege mode. 0 = Enables internal program memory and accesses internal memory locations. The EDS memory signal will not appear during accesses to internal ROM/EPROM programming memory and 1020h-102Fh. These ranges are accessed as on-chip memory. 1 = Disables internal program memory and accesses external memory (see Table 3-6 on page 3-24 for the external memory locations). An operation on these locations generates an external memory bus cycle with the EDS memory signal validating the access. This bit disables the program EPROM control register, EPCTL (described in Section 6.4, on page 6-10), if applicable, and disables 1020h-102Fh. These ranges are accessed as off-chip memory. Bits 1-0 Reserved. Read data is indeterminate.
System and Digital I/O Configuration
4-15
System Control Registers
4.3.3
System Control and Configuration Register 2 (SCCR2)
System Control and Configuration Register 2 (SCCR2) [Memory Address 1012h]
Bit #
P012
7
HALT/ STANDBY RP-0
6
PWRDWN/ IDLE RP-0
5
--
4
BUS STEST RP-0
3
CPU STEST RP-1
2
--
1
INT1 NMI RP-0
0
PRIVILEGE DISABLE RS-0
R = Read, P= Privilege write only, S = Set only, -n = Value of the bit after the register is reset Bit 7 HALT/STANDBY. The following descriptions apply only if the PWRDWN/IDLE bit is set; otherwise, the HALT/STANDBY bit has no effect. See subsection 4.2, on page 4-7 for a description of the halt and standby modes. Changes to this bit can occur only in the privilege mode. 0 = When an IDLE instruction executes, the processor enters the standby mode, which stops the program's execution and disables the SYSCLK to all nonessential peripherals. The SYSCLK to the T1 continues to run, and the timer generates an interrupt to bring the processor out of the standby mode. 1 = When an IDLE instruction executes, the processor enters the halt mode, which stops the internal oscillator and suspends the system and peripheral operations. This mode provides the lowest power consumption. Bit 6 PWRDWN/IDLE. Powerdown/Idle. This bit determines the mode entered by the CPU when an IDLE instruction is executed. Changes to this bit can occur only in the privilege mode. 0 = The processor enters an idle mode when the program executes an IDLE instruction. The processor waits at the IDLE instruction until any enabled interrupt occurs. The processor then enters the interrupt routine and returns to the instruction after the IDLE instruction. The idle is not a lowpower mode. 1 = The processor enters a low-power mode when the program executes an IDLE instruction. The HALT/STANDBY bit determines the type of lowpower mode. Bit 5 Reserved. For TMS370CxxxA or 'CxxxB devices, read data is indeterminate and writing to this bit has no effect, and an oscillator fault generates a system reset, regardless of this bit's status. Note: Bit 5 Operation Depends on Device
Bit 5 operates differently for TMS370Cxxx devices than for TMS370CxxxA or TMS370CxxxB devices. Refer to Section A.5, page A-5.
4-16
System Control Registers
Bit 4
BUS STEST. BUS STEST bit. This bit must be cleared (0) to ensure a proper operation.
Bit 3
CPU STEST. CPU STEST bit. This bit is used only during a factory test and has no effect in normal operating modes.
Bit 2
Reserved. For TMS370CxxxA or 'CxxxB devices, read data is indeterminate and writing to this bit has no effect. Note: Bit 2 Operation Depends on Device
Bit 2 operates differently for TMS370Cxxx devices than for TMS370CxxxA or TMS370CxxxB devices. Refer to Section A.5, page A-5. Bit 1 INT1 NMI. Interrupt 1, Nonmaskable Interrupt. This bit determines whether interrupt 1 is maskable or nonmaskable. When interrupt 1 is nonmaskable, it is the second highest priority interrupt (reset is highest) and is unaffected by the interrupt mask described in subsection 5.1.2, on page 5-8. The NMI mode disables the enable and priority select bits of the interrupt 1 control register. The program can change this bit only in the privilege mode. When programming an EEPROM, you must ensure that nonmaskable interrupt routines do not access the EEPROM between an EEPROM write instruction and the point when the EXE bit (DEECTL.0) is set to 1, or data will be corrupted. 0 = Interrupt 1 is maskable. 1 = Interrupt 1 is nonmaskable (NMI). Bit 0 PRIVILEGE DISABLE. Privilege Mode Disable. Many bits controlling the system configuration can be changed only while in the privilege mode. After setting the system configuration bits, write a 1 to the PRIVILEGE DISABLE bit to disable the privilege mode and lock out any changes to the privilege protected bits. Only a reset can clear this bit. 0 = System is operating in privilege mode. 1 = System is not operating in privilege mode.
System and Digital I/O Configuration
4-17
Digital I/O Configuration
4.4 Digital I/O Configuration
On TMS370 devices, the power, reset, MC, and crystal pins are dedicated to one function. The remaining pins can be programmed to be general-purpose input and/or output pins, or special function pins. Some of these pins are associated with the functions of the peripheral modules. The pins are briefly described below and are summarized in Table 4-4.
-
On TMS370Cx0x devices, 13 of a possible 22 I/O pins are dedicated to ports A and D. Port A contains eight pins, and port D contains five pins. On TMS370Cx1x devices, 13 of a possible 22 I/O pins are dedicated to ports A and D. Port A contains eight pins, and port D contains five pins. On TMS370Cx2x devices, 22 of a possible 34 I/O pins are dedicated to ports A, B, C, and D. Ports A and B each have eight pins. Port C contains one pin, and port D contains five pins. On TMS370Cx32 devices, 12 of a possible 23 I/O pins are dedicated to ports A and D. Port A contains eight pins. Port D contains four pins. On TMS370Cx36 devices, 13 of a possible 25 I/O pins are dedicated to ports A and D. Port A contains eight pins. Port D contains five pins. On TMS370Cx4x devices:
J J
On 40-pin devices, 16 of a possible 32 I/O pins are dedicated to ports A, B, and D. Port A contains eight pins, port B contains three pins, and port D contains five pins. On 44-pin devices, 16 of a possible 36 I/O pins are dedicated to ports A, B, and D. Port A contains eight pins, port B contains three pins, and port D contains five pins.
-
On TMS370Cx5x devices:
J J
On 68-pin devices, 32 of a possible 55 I/O pins are dedicated to ports A, B, C, and D; each port has eight pins. On 64-pin devices, 30 of a possible 53 I/O pins are dedicated to ports A, B, C, and D; ports A, B, and C each have eight pins, and port D has six.
4-18
On TMS370Cx6x devices, 29 of a possible 55 I/O pins are dedicated to ports A, B, C, and D; ports A, B, and C each have eight pins, and port D has five pins.
Digital I/O Configuration
-
On TMS370Cx7x devices:
J J
On 68-pin devices, 38 of a possible 55 I/O pins are dedicated to ports A, B, C, D, and G. Ports A, B, C, and D each have eight pins, and port D has six pins. On 64-pin devices, 36 of a possible 53 I/O pins are dedicated to ports A, B, C, D, and G. Ports A, B, and C each have eight pins, and ports D and G each have six pins.
-
On TMS370Cx8x devices:
J J
On 44-pin devices, 29 of a possible 35 I/O pins are dedicated to ports A, B, C, and D; ports A, B, and C each have eight pins, and port D has five pins. On 40-pin devices, 27 of a possible 33 I/O pins are dedicated to ports A, B, C, and D; ports A and B each have eight pins, port C has six pins, and port D has five pins.
-
On TMS370Cx9x devices, 13 of a possible 25 I/O pins are dedicated to ports A and D. Port A contains eight pins, and port D contains five pins. On TMS370CxAx devices, 22 of a possible 34 I/O pins are dedicated to ports A, B, C, and D; ports A and B each have eight pins, port C has one pin, and port D has five pins. On TMS370CxBx devices:
J J
On 68-pin devices, 41 of a possible 55 I/O pins are dedicated to ports A, B, C, D, G, and H; ports A, B, C, D, and G each have eight pins, and port H has one pin. On 64-pin devices, 39 of a possible 53 I/O pins are dedicated to ports A, B, C, D, G, and H; ports A, B, C, and G each have eight pins, port D has six pins, and port H has one pin.
-
On TMS370CxCx devices, 12 of a possible 22 I/O pins are dedicated to ports A and D. Port A contains eight pins, and port D contains four pins.
Frames 2 and 3 of the peripheral file (memory addresses 1020h to103Bh) contain the control registers for reading, writing, and configuring ports A, B, C, D, G, and H. These registers are shown in Figure 4-4 on page 4-21.
System and Digital I/O Configuration
4-19
Digital I/O Configuration
Table 4-4. Digital I/O Pins by Device Family
Maximum Digital General Purpose I/O Device Family TMS370Cx0x TMS370Cx1x TMS370Cx2x TMS370Cx32 TMS370Cx36 TMS370Cx4x TMS370Cx5x TMS370Cx6x TMS370Cx7x TMS370Cx8x TMS370Cx9x TMS370CxAx TMS370CxBx TMS370CxCx Bidirectional 21 21 33 14 16 27 46/44 46 46/44 34/32 16 33 46/44 17 Input Only 1 1 1 9 9
9/5
9 9 9 1 9 1 9 5
5 input pins for 40-pin devices; 9 input pins for 44-pin devices 46 bidirectional pins for 68-pin devices; 44 bidirectional pins for 64-pin devices 34 bidirectional pins for 44-pin devices; 32 bidirectional pins for 40-pin devices
4-20
Digital I/O Configuration
Figure 4-4. Peripheral File Frames 2 and 3: Digital Port Control Registers
Designation APORT1 APORT2 ADATA ADIR BPORT1 BPORT2 BDATA BDIR CPORT1 CPORT2 CDATA CDIR DPORT1 DPORT2 DDATA DDIR ADDR 1020h 1021h 1022h 1023h 1024h 1025h 1026h 1027h 1028h 1029h 102Ah 102Bh 102Ch 102Dh 102Eh 102Fh 1030h to 1035h GDATA GDIR 1036h 1037h 1038h 1039h HDATA HDIR 103Ah 103Bh PF P020 P021 P022 P023 P024 P025 P026 P027 P028 P029 P02A P02B P02C P02D P02E P02F P030 to P035 P036 P037 P038 P039 P03A P03B Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reserved Port A Control Register 2 Port A Data Port A Direction Reserved Port B Control Register 2 Port B Data Port B Direction Reserved Port C Control Register 2 Port C Data Port C Direction Port D Control Register 1 Port D Control Register 2 Port D Data Port D Direction Reserved Port G Data Port G Direction Reserved Reserved Port H Data Port H Direction
Each port has as many as four associated control registers, as follows:
-
Port x control register 1 (xPORT1) -- found only as DPORT1 in port D) Port x control register 2 (xPORT2) -- found in APORT2, BPORT2, CPORT2, and DPORT2 Port x data (xDATA) -- found in ADATA, BDATA, CDATA, DDATA, GDATA, and HDATA Port x direction (xDIR) -- found in ADIR, BDIR, CDIR, DDIR, GDIR, and HDIR
System and Digital I/O Configuration
4-21
Digital I/O Configuration
The same bit position of each of these registers affects the corresponding bit in the port. For example, bit 0 of registers DPORT1, DPORT2, DDATA, and DDIR control port D, bit 0, as illustrated in Figure 4-5.
Figure 4-5. Typical Control-Register Operation Using Port D
D7 Port D D6 D5 D4 D3 D2 D1 D0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Port D Control Register 1 (DPORT1) Port D Control Register 2 (DPORT2) Port D Data (DDATA) Port D Direction (DDIR)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
DPORT1 and DPORT2 values (00, 01, or 11) set mode (as specified in Table 4-5)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Data bits received or to be sent Direction of general purpose I/O bits
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bits from the DPORT1 and xPORT2 registers determine the function of the corresponding port pin to be an I/O, data, address, or control signal, depending on the port. The same bit from the xDIR register determines the direction (input or output) if the pin has been defined as an I/O pin. The same bit from the xDATA register is the bit to write to or read from if the pin has been defined as an I/O pin. Table 4-5 shows the function that each pin can serve, depending on which port contains the pin. Memory expansion signals for function A and function B are defined in Table 4-6 on page 4-24.
4-22
Digital I/O Configuration
Table 4-5. Port Configuration Registers Setup
When RESET Goes High MC Pin Low General-Purpose I/O DPORT1 =0 xPORT2 = 0 xDATA = Data In xDIR = 0 = Input Port A B C D D D D D D D D G H Pin 0-7 0-7 0-7 0 1 2 3 4 5 6 7 0-7 0 Data In Modek Data In = y Data In = y Data In = y Data In = y Data In = y Data In = y Data In = y Data In = y Data In = y Data In = y Data In = y Data In = y Data In = y DPORT1 = 0 xPORT2 = 0 xDATA = Data Out xDIR = 1 = Output Data Out Modeh Data Out = q Data Out = q Data Out = q Data Out = q Data Out = q Data Out = q Data Out = q Data Out = q Data Out = q Data Out = q Data Out = q Data Out = q Data Out = q Microcomputer Mode DPORT1 = 0 xPORT2 = 1 xDATA (not used) xDIR (not used) Function A DATA BUS LOW ADDR HI ADDR CSE2 CSH3 CSH2 SYSCLK R/W CSPF CSH1 CSE1 DPORT1 = 1 xPORT2 = 1 xDATA (not used) xDIR (not used) Function B DATA BUS LOW ADDR HI ADDR OCF SYSCLK R/W EDS WAIT MC Pin High
Microprocessor Mode DATA BUS LOW ADDR HI ADDR OCF SYSCLK R/W EDS WAIT
Registers DPORT1 and xPORT2 determine whether the port is configured as I/O, data bus, address bus, or control signal. If DPORT1 = 1 and xPORT2 = 0, the function is not valid. The variable x represents port A, B, C, D, G, and H. DPORT1 exists for port D only. These pins can be configured only as general-purpose I/O. Pins D1, D2, D5, G0 - G7, and H0 are not available in microprocessor mode. # Ports vary for each device. See the applicable device pin descriptions in Chapter 2 for ports available on each device. Function A and B signals are defined in Table 4-6 on page 4-24. k y is the value read from the xDATA register. h q is the value written to the xDATA register.
System and Digital I/O Configuration
4-23
Digital I/O Configuration
Table 4-6. Function A and B Signal Definitions
Signal
CSE1
Definition
Chip-select eighth 1. This signal selects a bank of external memory. It has the same timing as EDS. Setting this pin to a high-level general-purpose output disables the external memory bank connected to CSE1. Table 4-7 lists CSE1 external memory accesses for the entire line of TMS370 devices. Chip-select eighth 2. This signal selects a bank of external memory. It has the same timing as EDS. Setting this pin to a high-level general-purpose output disables the external memory bank connected to CSE2. Table 4-7 lists CSE2 external memory accesses for the entire line of TMS370 devices. Chip-select peripheral file. This signal has the same timing as EDS, but it goes active only during an access to the external frames of the peripheral file (locations 10C0h-10FFh). Chip-select half 1. This signal selects a bank of external memory. It has the same timing as EDS. Setting this pin to a high-level general-purpose output disables the external memory bank connected to CSH1. Table 4-7 lists CSH1 external memory accesses for the entire line of TMS370 devices. Chip-select half 2. This signal selects a bank of external memory. It has the same timing as EDS. Setting this pin to a high-level general-purpose output disables the external memory bank connected to CSH2. Table 4-7 lists CSH2 external memory accesses for the entire line of 68-pin TMS370 devices. Chip-select half 3. This signal selects a bank of external memory. It has the same timing as EDS. Setting this pin to a high-level general-purpose output disables the external memory bank connected to CSH3. Table 4-7 lists CSH3 external memory accesses for the entire line of TMS370 devices. System clock. This signal synchronizes external peripherals. It outputs the SYSCLK signal. External data bus. Input and output. External data strobe. This signal goes low during external memory operations. The rising edge of EDS validates the read input data; the write data is available after the falling edge of EDS. Table 4-8 lists EDS external memory accesses for the entire line of TMS370 devices. External memory address bus. Output only.
CSE2
CSPF
CSH1
CSH2
CSH3
SYSCLK DATA BUS EDS
LOW ADDR/ HI ADDR R/W
Read or write operation. Goes high at the beginning of read operations and low during write operations. This line is active during both internal and external accesses.
4-24
Digital I/O Configuration
Table 4-6. Function A and B Signal Definitions (Continued)
Signal OCF Definition Opcode fetch. Goes low at the beginning of a memory read operation that fetches the first byte of an instruction. It then resumes its high level at the end of the opcode fetch(es). Wait input. An external, low signal applied to this pin, when sampled, causes the processor to hold the information on the expansion bus for one or more extra clockout cycles. This pin is sampled during the rising edge of SYSCLK after EDS goes active.
WAIT
Table 4-7. TMS370 Family and Internal Program Memory (64- and 68-pin packages)
Microcomputer-Mode Function-A Chip-Select Signals (64- and 68-pin devices) Signal CSE1 CSE2 CSH1 CSH2 CSH3 'x50 (4K) 2000h- 3FFFh 2000h- 3FFFh 8000h- FFFFh 8000h- FFFFh 8000h- FFFFh 'x52 (8K) 2000h- 3FFFh 2000h- 3FFFh 8000h- FFFFh 8000h- FFFFh 8000h- FFFFh 'x53 (12K) 2000h- 3FFFh 2000h- 3FFFh 8000h- FFFFh 8000h- FFFFh 8000h- FFFFh 'x56 (16K) 2000h- 3FFFh 2000h- 3FFFh 8000h- FFFFh 8000h- FFFFh 8000h- FFFFh 'x67 (24K) A000h- BFFFh A000h- BFFFh C000h- FFFFh C000h- FFFFh C000h- FFFFh 'x58/'x68 (32K) A000h- BFFFh A000h- BFFFh C000h- FFFFh C000h- FFFFh C000h- FFFFh 'x59/'x69 (48K) E000h- EFFFh E000h- EFFFh F000h- FFFFh F000h- FFFFh F000h- FFFFh
The TMS370C150, TMS370C156, TMS370C250, and TMS370C256 devices are ROMless. These devices cannot operate in microcomputer mode function A.
System and Digital I/O Configuration
4-25
Digital I/O Configuration
Table 4-8. TMS370 Family EDS External Memory Accesses
Microcomputer Mode, Function B EDS 10C0h-10FFh 2000h-3FFFh 8000h-FFFFh 10C0h-10FFh 2000h-3FFFh 8000h-FFFFh 10C0h-10FFh 2000h-3FFFh 8000h-FFFFh 10C0h-10FFh 2000h-3FFFh 8000h-FFFFh 10C0h-10FFh 2000h-3FFFh 8000h-FFFFh -- Microprocessor Mode With Internal Program Memory Bit SCCR1.2 = 0 EDS 10C0h-10FFh 2000h-6FFFh 8000h-FFFFh 10C0h-10FFh 2000h-5FFFh 8000h-FFFFh 10C0h-10FFh 2000h-3FFFh 8000h-FFFFh 10C0h-10FFh 8000h-FFFFh 10C0h-10FFh A000h-5FFFh Bit SCCR1.2 = 1 EDS 10C0h-10FFh 2000h-FFFFh 10C0h-10FFh 2000h-FFFFh 10C0h-10FFh 2000h-FFFFh 10C0h-10FFh 2000h-FFFFh 10C0h-10FFh 2000h-FFFFh Microcprocessor Mode Without Internal Memory EDS -- --
TMS370 Device TMS370Cx50
TMS370Cx52
TMS370Cx56
-- --
TMS370Cx67
TMS370Cx58 TMS370Cx68 TMS370C150 TMS370C156 TMS370C250 TMS370C256
-- 1020h-102Fh 10C0h-10FFh 2000h-FFFFh
--
--
The TMS370C150, TMS370C250, TMS370C156, and TMS370C256 devices are ROMless. These devices cannot operate in microcomputer mode function B or microprocessor mode with internal program memory. When clearing the MEMORY DISABLE bit (SCCR1.2 = 0) in the microprocessor mode with internal program memory, the EDS signal cannot access off-chip memory that has the same locations as internal program memory.
4-26
Digital I/O Configuration
4.4.1
Configuration Example
The predecoded chip selects (CSE1, CSE2, and CSH1 to CSH3) allow the TMS370 to access external addresses with a minimum of external logic. In many cases, no external logic is necessary between the TMS370 and the peripheral device, because of the predecoded chip selects, autowait features, and the nonmultiplexed bus. Chip selects also make it easy to do memory bank selection. Without bank selection, the CSH1, CSE1, and CSPF signals can easily access about 40K bytes of memory in the three different areas. With bank selection, the processor can access as many as 112K bytes of memory. To illustrate configuring the digital ports, assume that a TMS370C050 is to operate in an expanded microcomputer mode, and that 2K bytes of memory are needed at 2000h to 27FFh. The top half of Example 4-1 shows the desired port configuration.
-
Port A is set as the external data bus. Port B contains the low-order address bits of the 11 bits necessary to access 2K bytes of memory. Bits 4 through 7 of port C are set as I/O input. In port D, bit 7 is the chip-select signal to access 2000h to 3FFFh, and bit 4 is for external memory control signal R/W. The remaining bits of port D are used as I/O output.
The bottom half of Example 4-1 shows the port control registers set up to establish the configuration shown in the top half. To determine the bits needed to set the registers, use Table 4-5 on page 4-23. For example, to set port A as the data bus in microcomputer mode, function A, find Port A at the left-hand column of Table 4-5. Look across the row to find the data bus, then follow the column up to the bit settings for the desired mode (microcomputer or microprocessor) and function in the column heading:
DPORT1 = 0 xPORT2 = 1 xDATA (not used) xDIR (not used)
The assembly language instructions in the right column of Example 4-1 show one method of setting up the registers to the left. The Pxxx operand indicates peripheral file access (see Chapter 16, Assembly Language Instruction Set, for more information on peripheral file instructions).
System and Digital I/O Configuration
4-27
Digital I/O Configuration
Example 4-1. Digital Port Setup
Bit 7 Port A Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Data Bus
Port B
Address Bus
Port C
I/O In
Address Bus
Port D
CSE1 CS
I/O In
R/W
I/O Out
Port A Control Registers APORT2 ADATA ADIR 1021h 1022h 1023h 1 dc dc 1 dc dc 1 dc dc 1 dc dc 1 dc dc 1 dc dc 1 dc dc 1 dc dc MOV #0FFh, P021
Port B Control Registers BPORT2 BDATA BDIR 1025h 1026h 1027h 1 dc dc 1 dc dc 1 dc dc 1 dc dc 1 dc dc 1 dc dc 1 dc dc 1 dc dc MOV #0FFh, P025
Port C Control Registers CPORT2 CDATA CDIR 1029h 102Ah 102Bh 0 y 0 0 y 0 0 y 0 0 y 0 0 y 0 1 dc dc 1 dc dc 1 dc dc MOV #0, P02B MOV #007h, P029
Port D Control Registers DPORT1 DPORT2 DDATA DDIR 102Ch 102Dh 102Eh 102Fh 0 1 dc dc 0 0 y 0 0 0 y 0 0 1 dc dc 0 0 q 1 0 0 q 1 0 0 q 1 0 0 q 1 MOV #00Fh, P02F MOV #0, P02C MOV #090h, P02D
Legend: dc = y= q=
don't care data value read data value written
When the device operates with internal program memory disabled, any access to the port peripheral frame, 1020h-102Fh, is decoded as an external
4-28
Digital I/O Configuration
address. Memory accesses to this frame can control external hardware that emulates the digital I/O functions.
4.4.2
Microprocessor Mode
Initializing a device with bus expansion to the microprocessor mode forces ports A, B, C, and D to function B as shown in Table 4-5, page 4-23. Port A is the data bus, port B is the low-order address bus, and port C is the high-order address bus in this mode. Devices that are not defined for operation in a memory expansion mode must be powered up in the microcomputer singlechip mode.
4.4.3
Microcomputer Mode
Initializing the device to the microcomputer mode forces ports A, B, C, and D to general-purpose high-impedance inputs. The program can set the control bits to change the function of the port pins to one of four functions: generalpurpose output, general-purpose input, function A, or function B. When you change a pin from a general-purpose input pin to an output pin, write to the data register first to set up the data; then, set the data direction register. This prevents unknown data on the pin from interfering with the external circuitry. The TMS370 in the microcomputer mode can individually reconfigure any address, data, or control signal to use only the necessary signals and leave the other signals on the port for general-purpose I/O operations. Figure 4-6 shows an example of the TMS370C050 interfaced to 112K bytes of external memory (see the TMS370 8-bit Microcontroller Applications Manual [SPNA019] for detailed examples). The function A chip-select signals enable one of three banks of EPROM, an external peripheral device, and one of two banks of static RAM. In this example, all eight bits of port A are the data bus, all eight bits of port B are the address LSbyte, and seven port C bits complete the 15-bit address bus.
System and Digital I/O Configuration
4-29
Digital I/O Configuration
Figure 4-6. System Interface Example
VCC 10 k (All)
U1 R/W CSE2 CSE1 CSPF CSH3 CSH2 CSH1
U2 E G E G
U3 E G
U4
U5
U6
WE
E
CS1
VCC
CS2 OE
A Address 0-14 Data 0-7 MC 15 8
Q VSS
A
Q VSS
A
Q
A
D
A
I/O
VSS
VSS
U1 = TMS370C050 8-bit microprocessor U2, U3, U4 = TMS27C256 32K x 8 bit EEPROM U5 = Unspecified 64-byte peripheral U6, U7 = 8K x 8 bit static RAM
4-30
IIII IIII IIII IIII IIII IIII IIII IIII
U7 WE CS1 CS2 OE A I/O
III III III III III III III III
CCC CCC CCC CCC CCC CCC CCC CCC
Running Title--Attribute Reference
Chapter 5
Interrupts and System Reset
This chapter discusses the internal and external interrupts of the TMS370. Device reset methods are also discussed. This chapter covers the following topics:
Topic
5.1 5.2 5.3 5.4
Page
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Interrupt Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 Multiple Interrupt Servicing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19
Chapter Title--Attribute Reference
5-1
Interrupts
5.1
Interrupts
The TMS370 programmable interrupt structure allows flexible on-chip and external interrupt configurations to meet real-time interrupt-driven application requirements. Whenever an internal or external circuit requests an enabled interrupt, the processor finishes the current instruction and then fetches the address of the appropriate interrupt service routine from the interrupt table. The processor then pushes the contents of the program counter and status register onto the stack and begins execution at the interrupt service routine address found in the interrupt table. When the interrupt service routine completes its execution, the program executes an RTI (return from interrupt) instruction, which pops the previous status register and program counter contents from the stack. The processor resumes execution from the point of interruption. Table 5-1 shows the interrupt and reset vectors by device category.
Table 5-1. Interrupts and Reset Vectors
Device Category TMS370Cx0x TMS370Cx1x TMS370Cx2x TMS370Cx32 TMS370Cx36 TMS370Cx4x TMS370Cx5x TMS370Cx6x TMS370Cx7x TMS370Cx8x TMS370Cx9x TMS370CxAx TMS370CxBx TMS370CxCx Interrupts/Reset External 4 4 4 4 2 4 4 4 4 4 2 4 4 2 Vectors Total 7 6 8 23 22 9 10 11 7 5 4 8 6 6 Sources Total 15 13 16 25 24 22 23 29 19 12 11 21 13 14
Three external interrputs and a reset for all devices except 'x36, 'x9x, and 'xCx which have one external interrupt and a reset.
5-2
Interrupts
5.1.1
Interrupt Operation
The hardware interrupt structure includes two selectable priority levels as shown in Figure 5-1. Interrupt level 1 has a higher priority than interrupt level 2. The two priority levels can be independently masked by clearing the global interrupt enable bits (IE1 and IE2) of the status register (described in subsection 3.2.2, page 3-5. Note: All the peripheral modules are connected in a daisy-chain order, shown running horizontally in the center of Figure 5-1. For the same level (1 or 2), the module connected closest to the CPU (right side of figure) has a higher priority than the modules that are further away. For example, the order of priority shown in the figure is INT1, followed by INT2, INT3, SPI, TIMER 1, SCI, TIMER 2A, PACT, ADC, and TIMER 2B. The devices and their modules are listed in Table 5-2 on page 5-5. During system initialization, the application program can assign system interrupts to either the high or low priority level. The program can reassign priority levels at any time, except for those priority levels that are protected by the privileged mode. Within each level, the hardware determines the interrupt priority. The processor services the pending interrupts after executing the current instructions, depending on the interrupt mask and priority conditions. The processor services all enabled level 1 interrupts before servicing any level 2 interrupts. Within each level, the processor services the highest priority interrupts first. Table 5-2 (page 5-5) shows the hardware priorities (starting at 1 for highest) of the devices at the time of this printing. The TMS370 architecture allows up to 128 independent interrupt vectors, located within the memory addresses 7F00h to 7FFFh. This memory space also contains the trap tables, and 12 bytes are reserved for Texas Instruments' use. If the device does not define this memory for an interrupt vector, it can be used for program memory. Table 5-3 shows the interrupt vector source(s) and corresponding address(es). Note that a system interrupt can have multiple interrupt sources. The application program can individually enable or disable all of the interrupt sources via local interrupt enable control bits in the associated peripheral file. Also, the software can read each interrupt source's flag bit to determine which interrupt source generated the system interrupt.
Interrupts and System Reset
5-3
Interrupts
Figure 5-1. Interrupt Control
EXT INT 3 INT 3 EXT INT 2 INT 2 INT3 PRI
TIMER 2B INT Overflow Compare1 Ext edge Compare2 Input capture 1 Input capture 2
TIMER 2A INT Overflow Compare1 Ext edge Compare2 Input capture 1 Input capture 2
TIMER 1 INT Overflow Compare1 Ext Edge Compare2 Input capture 1 Watchdog
INT2 PRI EXT INT1 INT1 CPU NMI
T2B PRI
T2A PRI
T1 PRI
INT1 PRI STATUS REG IE1 IE2
Priority Logic
Interrupt Daisy Chain
Level 1 INT Level 2 INT SPI INT SPI PRI
ADC INT AD PRI
Enable
SCI INT A/D
PACT 3 PRI Cmd/def entry 0 Cmd/def entry 1 Cmd/def entry 2 Cmd/def entry 3 Cmd/def entry 4 Cmd/def entry 5 Cmd/def entry 6 Cmd/def entry 7 GROUP 3 GROUP 2
SCI RXINT SCI TXINT
PACT INT
PACT 2 PRI PACT 1 PRI
TX TXPRI
RX
SPI
Circular buffer CP6 Edge CP5 Edge CP4 Edge CP3 Edge CP2 Edge CP1 Edge Overflow default timer GROUP 1
TXRDY
RXPRI BRKDT RXRDY
Note:
Figure 5-1 shows the daisy chain order of all peripheral modules. The modules connected closest to the CPU have a higher priority than those further away. For instance, the following are in priority order as shown above: INT1, INT2, INT3, SPI, TIMER 1, SCI (SCI1 or SCI2), TIMER 2A, PACT, ADC (ADC1, ADC2, or ADC3), TIMER 2B. Not all peripheral modules are available on any given device. Refer to Table 5-2 for device module availability and priority for each family.
5-4
Interrupts
The processor acknowledges an interrupt if its flag bit equals 1 and the interrupt is enabled. To avoid immediately re-entering the same interrupt service routine, the interrupt service routine must clear all appropriate flag bits before leaving the routine. For example, clear the INT1 flag bit as shown in Figure 5-2 on page 5-9.
Table 5-2. Module Interrupt Priority in Lowest-to-Highest Order
Vector Start Address 7FBEh 7FECh 7F9Ch Device Module Priority Module Timer 2B ADC|| P Grp3 Grp2 Grp1 7FEEh 7FF0h Timer 2A SCIk TX RX# 7FF4h 7FF6h 7FF8h 7FFAh 7FFCh 7FFEh Timer 1 SPI External INT3 External INT2 External INT1 RESET x0x NA NA NA NA NA NA 7 6 5 NA 4 3 2 1 x1x NA NA NA NA NA NA NA NA 6 5 4 3 2 1 x2x NA NA NA NA NA NA 8 7 6 5 4 3 2 1 x32 NA 8 7 6 5 NA NA NA NA NA 4 3 2 1 x36 NA 7 6 5 4 NA NA NA NA 3 NA NA 2 1 x4x NA 9 NA NA NA 8 7 6 5 NA 4 3 2 1 x5x NA 10 NA NA NA 9 8 7 6 5 4 3 2 1 x6x 11 10 NA NA NA 9 8 7 6 5 4 3 2 1 x7x NA 7 NA NA NA 6 NA NA 5 NA 4 3 2 1 x8x NA NA NA NA NA NA NA NA 5 NA 4 3 2 1 x9x NA 4 NA NA NA NA NA NA 3 NA NA NA 2 1 xAx NA NA NA NA NA 8 7 6 5 NA 4 3 2 1 xBx NA 6 NA NA NA NA NA NA 5 NA 4 3 2 1 xCx NA 6 NA NA NA NA 5 4 3 NA NA NA 2 1 2 2 2 2 2 2 2 4 Module Vector Bytes 2 2 36
Modules are listed in order of lowest priority at the top, highest priority (1) on the bottom. The in-circuit emulator with PACT (TMS370Cx32 and TMS370x36) has the PACT module as the lowest priority interrupt, while the rest of the device family has (depending on the resident modules) timer 2B as the lowest priority, followed by the ADC, timer 2A, and so forth. The priority interrupts are shown in the table from the lowest to the highest priority. PACT module Transmit # Receive || ADC refers to ADC1, ADC2, or ADC3 k SCI refers to SCI1 or SCI2
Interrupts and System Reset
5-5
Interrupts
Table 5-3. Interrupt Vector Sources
Module Timer 2B Vector Address 7FBEh, 7FBFh Interrupt Source Timer 2B Overflow Timer 2B compare 1 Timer 2B compare 2 Timer 2B external edge Timer 2B input capture 1 Timer 2B input capture 2 ADC PACT (Group 3) 7FECh, 7FEDh 7FA0h, 7FA1h 7FA2h, 7FA3h 7FA4h, 7FA5h 7FA6h, 7FA7h 7FA8h, 7FA9h 7FAAh, 7FABh 7FACh, 7FADh 7FAEh, 7FAFh PACT (Group 2) PACT (Group 1) 7F9Eh, 7F9Fh 7F9Ch, 7F9Dh 7FB0h, 7FB1h 7FB2h, 7FB3h 7FB4h, 7FB5h 7FB6h, 7FB7h 7FB8h, 7FB9h 7FBAh, 7FBBh 7FBCh, 7FBDh 7FBEh, 7FBFh ADC conversion complete PACT cmd/def entry 0 PACT cmd/def entry 1 PACT cmd/def entry 2 PACT cmd/def entry 3 PACT cmd/def entry 4 PACT cmd/def entry 5 PACT cmd/def entry 6 PACT cmd/def entry 7 PACT SCI RXINT PACT SCI TXINT PACT circular buffer (half/full) PACT CP6 edge PACT CP5 edge PACT CP4 edge PACT CP3 edge PACT CP2 edge PACT CP1 edge PACT default timer overflow Interrupt Flag T2B OVRFL INT FLAG T2BC1 INT FLAG T2BC2 INT FLAG T2BEDGE INT FLAG T2BIC1 INT FLAG T2BIC2 INT FLAG AD INT FLAG CMD/DEF INT 0 FLAG CMD/DEF INT 1 FLAG CMD/DEF INT 2 FLAG CMD/DEF INT 3 FLAG CMD/DEF INT 4 FLAG CMD/DEF INT 5 FLAG CMD/DEF INT 6 FLAG CMD/DEF INT 7 FLAG PACT RXRDY PACT TXRDY BUFFER HALF/FULL INT FLAG CP6 INT FLAG CP5 INT FLAG CP4 INT FLAG CP3 INT FLAG CP2 INT FLAG CP1 INT FLAG DEFTIM OVRFL INT FLAG ADINT CDINT0 CDINT1 CDINT2 CDINT3 CDINT4 CDINT5 CDINT6 CDINT7 PRXINT PTXINT BUFINT CP6INT CP5INT CP4INT CP3INT CP2INT CP1INT POVRFL INT 1 1 2 3 4 5 6 7 8 1 2 1 2 3 4 5 6 7 8 System Interrupt T2BINT Priority in Group 1
1 is the highest priority. The table, top to bottom, is in lowest to highest priority order. ADC refers to ADC1, ADC2, or ADC3.
5-6
Interrupts
Table 5-3. Interrupt Vector Sources (Continued)
Module Timer 2A Vector Address 7FEEh, 7FEFh Interrupt Source Timer 2A overflow Timer 2A compare 1 Timer 2A compare 2 Timer 2A external edge Timer 2A input capture 1 Timer 2A input capture 2 SCI TX SCI RX 7FF0h, 7FF1h 7FF2h, 7FF3h SCI TX data register empty SCI RX data register full SCI RX break detect Timer 1 7FF4h, 7FF5h Timer 1 overflow Timer 1 compare 1 Timer 1 compare 2 Timer 1 external edge Timer 1 input capture 1 Watchdog overflow SPI External INT 7FF6h, 7FF7h 7FF8h, 7FF9h 7FFAh, 7FFBh 7FFCh, 7FFDh RESET 7FFEh, 7FFFh SPI RX/TX complete External INT3 External INT2 External INT1 External RESET Watchdog overflow Oscillator fault detect Interrupt Flag T2A OVRFL INT FLAG T2AC1 INT FLAG T2AC2 INT FLAG T2AEDGE INT FLAG T2AIC1 INT FLAG T2AIC2 INT FLAG TXRDY FLAG RXRDY FLAG BRKDT FLAG T1 OVRFL INT FLAG T1C1 INT FLAG T1C2 INT FLAG T1EDGE INT FLAG T1IC1 INT FLAG WD OVRFL INT FLAG SPI INT FLAG INT3 FLAG INT2 FLAG INT1 FLAG COLD START WD OVRFL INT FLAG OSC FLT FLAG SPIINT INT3 INT2 INT1 RESET 1 1 1 1 1 T1INT 1 TXINT RXINT 1 1 System Interrupt T2AINT Priority in Group 1
1 is the highest priority. The table, top to bottom, is in lowest to highest priority order. SCI refers to SCI1 or SCI2.
Interrupts are sampled and arbitrated by the CPU during every opcode fetch. If one or more requests are pending (and the appropriate enable bits are set in the status register for maskable interrupts), then at the normal completion of the opcode fetch, the interrupt context switch begins. The new opcode is discarded, and the program counter is rewound to point to the discarded instruction. Moreover, at the completion of the interrupt service routine, the discarded instruction is fetched again.
Interrupts and System Reset
5-7
Interrupts
The context switch routine proceeds as follows: 1) Increments the stack pointer (SP) and stores the contents of the status register (ST) at the location pointed to by the SP. 2) Resets the ST to 00h (disables further interrupt recognition). 3) Obtains the identity of the interrupting peripheral. 4) Rewinds the program counter (PC) to point to the aborted opcode. 5) Increments SP and stores the original PC high byte (PCH) at the location pointed to by the SP. 6) Gets the interrupt-service-routine address (low byte) and stores it in the PC low byte (PCL). 7) Increments SP and stores the original PCL at the location pointed to by SP. 8) Gets the address (high byte) of the interrupt service routine and stores it in the PCH. 9) Resumes instruction execution with the new PC contents. A minimum of 15 cycles is required from the time that an interrupt is triggered until the first instruction of the interrupt service routine is read. The moment at which the interrupt is asserted, and the place in the instruction at which the interrupt is asserted, depend on the instruction in progress. The worst case happens if the interrupt occurs near the start of a divide instruction; the processor may require up to 78 clock cycles to enter the interrupt service routine. If wait states are needed, the appropriate number of cycles must be added. Also, an external interrupt (INT1, INT2, or INT3) requires two extra clock cycles to synchronize before the processor can detect it.
5.1.2
External Interrupts
External pins INT1, INT2, and INT3 allow external devices to interrupt the program and enter a specific interrupt service routine. The INT1, INT2, and INT3 control registers in peripheral file frame 1 govern the software configuration of the external interrupts. Figure 5-2 shows these registers.
5-8
Interrupts
Figure 5-2. Peripheral File Frame 1: External Interrupt Control Registers
Designation INT1 Address PF Bit 7 INT1 FLAG (RC-0) INT2 FLAG (RC-0) INT3 FLAG (RC-0) Bit 6 INT1 PIN DATA (R-0) INT2 PIN DATA (R-0) INT3 PIN DATA (R-0) Bit 5 Bit 4 Bit 3 Bit 2 INT1 POLARITY (RW-0) INT2 POLARITY (RW-0) INT3 POLARITY (RW-0) Bit 1 INT1 PRIORITY (RW-0) INT2 PRIORITY (RW-0) INT3 PRIORITY (RW-0) Bit 0 INT1 ENABLE (RW-0) INT2 ENABLE (RW-0) INT3 ENABLE (RW-0)
1017h
P017
--
-- INT2 DATA DIR (RW-0) INT3 DATA DIR (RW-0)
-- INT2 DATA OUT (RW-0) INT3 DATA OUT (RW-0)
INT2
1018h
P018
--
INT3
1019h
P019
--
The software uses the interrupt polarity bits to individually configure each external interrupt to trigger on either a rising edge or a falling edge. If the interrupt function is not required, the software can configure INT1 to be an input pin, and INT2 and INT3 to be general-purpose input/output pins. INT1 can be programmed as a maskable or nonmaskable interrupt. When INT1 is nonmaskable, it cannot be masked by the individual or global mask bits. Remember that the INT1 NMI bit (SCCR2.1) is protected during nonprivileged operations and should be configured during the system initialization sequence following a reset (see the INT1 NMI bit description in subsection 4.3.3, page 4-17). The nonmaskable interrupt is used for events that you want to respond to immediately. For example, this event could be derived from monitoring the power supply and saving important data to EEPROM whenever a brownout/power loss condition occurs. Notes:
-
When a nonmaskable interrupt (NMI) is used, the interrupt is taken on every active edge of the INT1 pin. This pin should be debounced to avoid multiple interrupts that could cause the stack to overflow. Once the stack overflows, the program may not operate as expected. To provide a method of exiting low-power modes, INT1 is automatically enabled as an NMI during low-power modes when the hard watchdog mode is selected. This means that the NMI is always generated regardless of the interrupt enable flags and the values of the status bits (that is, INT1 PRIORITY bit [INT1.1], INT1 ENABLE bit [INT1.0], INT1 NMI bit [SCCR2.1], and the global interrupt enable flags of the status register [IE1 and IE2]). See subsection 7.7.2.1, page 7-26, for more information.
Interrupts and System Reset
5-9
Interrupts
The application program must configure the following bits for each interrupt to function correctly (refer to Figure 5-3 and Figure 5-4 on page 5-10).
-
The INTx PRIORITY bit configures the interrupt as either a level 1 or a level 2 interrupt. The INTx POLARITY bit selects the trigger as either a falling edge or a rising edge. The INTx ENABLE bit allows the request to be transmitted to the CPU if either the IE1 or IE2 enable bit, whichever is appropriate, is enabled.
Figure 5-3. Interrupt 1 Block Diagram
P017.0 Enable Wake-up P017.6
External pin connection
NMI
Pin Data 1 1 = Rising D
CLR 1 Q 0
P012.1 NMI enable P017.0 Enable ST Level 2 Int request Level 1 Int request
INT 1 0 = Falling P017.2 Polarity
IE2 1 0
CLR
Write Read INT flag
Priority Select P017.7 P017.1 Other Level 2 interrupts Other Level 1 interrupts
IE1
ST Status register Global interrupts Enable bits
This bit is ignored if you are using the hard watchdog option.
5-10
Interrupts
Figure 5-4. Interrupts 2 and 3 Block Diagram
External pin connection
P018.6 P019.6 Input pin data 1
P018.3 P019.3 Data out
Other Level 2 interrupts Other Level 1 interrupts P018.0 P019.0 Enable IE2 ST
Wake-up
INT
(Int 2 or 3 pin)
0
1 1 = Rising
D Q
1 0 IE1 ST Priority select
Level 2 Int request Level 1 Int request
Data dir P018.4 P019.4
0 = Falling Polarity P018.2 P019.2
CLR
Write Read INT flag P018.7 P019.7
P018.1 P019.1
Status register Global interrupts Enable bits
-
The INTx FLAG indicates that the selected edge (rising or falling) has occurred. If the enables are set, an interrupt is requested. This bit remains a 1 until the software or a RESET clears it. The INTx FLAG bit is useful for programs that poll the interrupt flag instead of generating a system interrupt. The INTx PIN DATA bit shows the condition presently on the interrupt pin. On interrupts 2 and 3, the INTx DATA DIR determines whether the pin functions as a general-purpose output pin or as an input/interrupt pin. If you select the general-purpose output function for a pin, then the value written by software to the INTx DATA OUT bit determines the value of the output.
-
All external interrupts can bring the processor out of both the halt and the standby low-power modes if the interrupt enable and the interrupt level mask are enabled. Note that in halt mode, the interrupt is detected on the level and not the edge. For further information, refer to subsection 4.2.3, page 4-10.
Interrupts and System Reset
5-11
Interrupt Control Registers
5.2 Interrupt Control Registers
The interrupt control registers control the configuration of the external interrupts.
5.2.1
Interrupt 1 Control Register (INT1)
The INT1 register controls the interrupt configuration for the INT1 pin. INT1 is available for all TMS370 devices.
Interrupt 1 Control Register (INT1) [Memory Address 1017h]
Bit #
P017
7
INT1 FLAG RC-0
6
INT1 PIN DATA R-0
5
--
4
--
3
--
2
INT1 POLARITY RW-0
1
INT1 PRIORITY RW-0
0
INT1 ENABLE RW-0
R = Read, W = Write, C = Clear only, -n = Value of the bit after the register is reset
Bit 7
INT1 FLAG. Interrupt 1 Flag. When set, this bit indicates that the selected transition on INT1 has occurred. An interrupt can occur as long as this bit remains set; as a result, the application program must clear this bit during the interrupt handling routine. This bit is set, even if the INT1 ENABLE bit is cleared. This flag is not set if INT1 is configured as an NMI. 1 = Transition detected 0 = No transition
Bit 6
INT1 PIN DATA. Interrupt 1 Pin Data. This bit displays the current condition of the INT1 pin. 1 = High-level input voltage (VIH) at the INT1 pin 0 = Low-level input voltage (VIL) at the INT1 pin
Bits 5,4,3 Bit 2
Reserved. Read data is indeterminate. INT1 POLARITY. Interrupt 1 Polarity. This bit determines whether INT1 triggers on a rising edge or on a falling edge. 1 = Triggers on a rising edge (low-to-high transition) 0 = Triggers on a falling edge (high-to-low transition)
5-12
Interrupt Control Registers
Bit 1
INT1 PRIORITY. Interrupt 1 Priority. This bit determines the interrupt level of the INT1 pin --either a high, level-1 interrupt or a low, level-2 interrupt. This bit is ignored if INT1 NMI = 1. 1 = Level 2 interrupt (low level) 0 = Level 1 interrupt (high level)
Bit 0
INT1 ENABLE. Interrupt 1 Enable. When set, this bit enables the interrupts for the INT1 pin. This bit is ignored if INT1 NMI = 1. 1 = Enables INT1 interrupts 0 = Disables INT1 interrupts
Interrupts and System Reset
5-13
Interrupt Control Registers
5.2.2
Interrupt 2 Control Register (INT2)
The INT2 register controls the interrupt configuration for the INT2 pin. INT2 is available for all TMS370 devices except 'x36, 'x9x, and 'xCx devices.
Interrupt 2 Control Register (INT2) [Memory Address 1018h]
Bit #
P018
7
INT2 FLAG RC-0
6
INT2 PIN DATA R-0
5
--
4
INT2 DATA DIR RW-0
3
INT2 DATA OUT RW-0
2
INT2 POLARITY RW-0
1
INT2 PRIORITY RW-0
0
INT2 ENABLE RW-0
R = Read, W = Write, C = Clear only, -n = Value of the bit after the register is reset
Bit 7
INT2 FLAG. Interrupt 2 Flag. This bit indicates that the selected transition on INT2 has occurred. An interrupt can occur as long as this bit remains set; as a result, the program must clear this bit during the interrupt handling routine. This bit is set, even if the INT2 ENABLE bit is cleared. 1 = Transition detected 0 = No transition
Bit 6
INT2 PIN DATA. Interrupt 2 Pin Data. This bit displays the current value of the INT2 pin. 1 = High-level input voltage (VIH) at the INT2 pin 0 = Low-level input voltage (VIL) at the INT2 pin
Bit 5 Bit 4
Reserved. Read data is indeterminate. INT2 DATA DIR. Interrupt 2 Data Direction. The INT2 pin can be configured as either an output pin or as an input/interrupt pin. 1 = INT2 pin is an output pin 0 = INT2 pin is an input/interrupt pin
Bit 3
INT2 DATA OUT. Interrupt 2 Data Out. If the software configures the INT2 pin as an output pin (INT2 DATA DIR = 1), then the value that the software writes to the INT2 DATA OUT bit determines the value of that output pin.
5-14
Interrupt Control Registers
Bit 2
INT2 POLARITY. Interrupt 2 Polarity. This bit determines whether INT2 triggers on a rising edge or on a falling edge. 1 = Triggers on a rising edge (low-to-high transition) 0 = Triggers on a falling edge (high-to-low transition)
Bit 1
INT2 PRIORITY. Interrupt 2 Priority. This bit determines the interrupt level of the INT2 pin --either a high, level-1 interrupt or a low, level-2 interrupt. 1 = Level 2 interrupt (low level) 0 = Level 1 interrupt (high level)
Bit 0
INT2 ENABLE. Interrupt 2 Enable. When set, this bit enables the interrupts for the INT2 pin. 1 = Enables INT2 interrupts 0 = Disables INT2 interrupts
Interrupts and System Reset
5-15
Interrupt Control Registers
5.2.3
Interrupt 3 Control Register (INT3)
The INT3 register controls the interrupt configuration for the INT3 pin. INT3 is available for all TMS370 devices except 'x36, 'x9x, and 'xCx devices.
Interrupt 3 Control Register (INT3) [Memory Address 1019h]
Bit #
P019
7
INT3 FLAG RC-0
6
INT3 PIN DATA R-0
5
--
4
INT3 DATA DIR RW-0
3
INT3 DATA OUT RW-0
2
INT3 POLARITY RW-0
1
INT3 PRIORITY RW-0
0
INT3 ENABLE RW-0
R = Read, W = Write, C = Clear only, -n = Value of the bit after the register is reset
Bit 7
INT3 FLAG. Interrupt 3 Flag. This bit indicates that the selected transition on INT3 has occurred. An interrupt can occur as long as this bit remains set; as a result, the program must clear this bit during the interrupt handling routine. This bit will be set, even if the INT3 ENABLE bit is cleared. 1 = Transition detected 0 = No transition
Bit 6
INT3 PIN DATA. Interrupt 3 Pin Data. This bit displays the current condition of the INT3 pin. 1 = High-level input voltage (VIH) at the INT3 pin 0 = Low-level input voltage (VIL) at the INT3 pin
Bit 5 Bit 4
Reserved. Read data is indeterminate. INT3 DATA DIR. Interrupt 3 Data Direction. The INT3 pin can be configured as either an output pin or as an input/interrupt pin. 1 = INT3 pin is an output pin 0 = INT3 pin is an input/interrupt pin
Bit 3
INT3 DATA OUT. Interrupt 3 Data Out. If software configures the INT3 pin as an output pin (INT3 DATA DIR=1), then the value that the software writes to the INT3 DATA OUT bit determines the value of that output pin.
5-16
Interrupt Control Registers
Bit 2
INT3 POLARITY. Interrupt 3 Polarity. This bit determines whether INT3 triggers on a rising edge or on a falling edge. 1 = Triggers on a rising edge (low-to-high transition) 0 = Triggers on a falling edge (high-to-low transition)
Bit 1
INT3 PRIORITY. Interrupt 3 Priority. This bit determines the interrupt level of the INT1 pin --either a high, level-1 interrupt or a low, level-2 interrupt. 1 = Level-2 interrupt (low level) 0 = Level-1 interrupt (high level)
Bit 0
INT3 ENABLE. Interrupt 3 Enable. This bit enables the interrupts for the INT3 pin. 1 = Enables INT3 interrupts 0 = Disables INT3 interrupts
Interrupts and System Reset
5-17
Multiple Interrupt Servicing
5.3 Multiple Interrupt Servicing
When servicing an interrupt, the processor automatically clears the global interrupt enable bits IE1 and IE2 in the status register. This prevents all other interrupts from being recognized during the execution of the interrupt service routine. Once the service routine is completed by executing the RTI (return from interrupt) instruction, the old status register contents are popped from the stack. This returns bits IE1 and IE2 to their original conditions and allows any pending interrupts to be recognized. An interrupt service routine allows nested interrupts by executing the EINT, EINTL, or EINTH instructions to set the global interrupt enable bits in the status register. This permits other interrupts to be recognized during the service routine execution. When a nested interrupt service routine completes, it returns to the previous interrupt service routine when the RTI instruction executes. Too many nested interrupts could overflow the stack, and cause a program failure.
5-18
Resets
5.4 Resets
The TMS370 has three possible reset sources:
-
A low input to the RESET pin A programmable watchdog timer timeout (described in Section 7.7 and Section 15.2) A programmable oscillator fault failure (described in subsection 4.1.3)
After a reset, the program can interrogate the status bits (shown in Table 5-4) to determine the source of the reset in order to take appropriate action. If none of the sources shown in Table 5-4 caused the reset, then the RESET pin was pulled low by external hardware or the PACT module watchdog. The RESET pin starts the hardware initialization and ensures an orderly software startup. The RESET pin is an input/output pin. A low-level pulse initiates the reset sequence. The processor may detect short reset pulses of a few nanoseconds, but a low level (active) of one SYSCLK cycle is necessary to guarantee that the device sees the reset signal. The microcontroller is held in reset until the RESET pin goes inactive (high). If the reset input signal remains low for less than eight system clock cycles (SYSCLK), the processor holds the external RESET pin low for eight system clock cycles to reset the external system components. The basic operating mode (microcomputer or microprocessor) is determined by the voltage level applied to the MC pin when the RESET pin goes inactive (high). The RESET pin can be pulled low at any time during its operation to start the reset sequence.
Table 5-4. Reset Sources
Register SCCR0 SCCR0 T1CTL2 Address 1010h 1010h 104Ah PF P010 P010 P04A Bit No. 7 4 5 Control Bit COLD START OSC FLT FLAG WD OVRFL INT FLAG Source of Reset Cold or warm start reset Oscillator out of range Watchdog timer timeout
Interrupts and System Reset
5-19
Resets
The sequence of events during reset is as follows: 1) CPU registers are initialized (ST = 00h and SP = 01h). 2) Registers A and B are initialized to 00h (no other RAM is changed). 3) Contents of 7FFFh are read and stored in the PCL (PC low). 4) Contents of 7FFEh are read and stored in the PCH (PC high). 5) Program execution is started with an opcode fetch from the address pointed to by the PC. The reset sequence takes 20 SYSCLK cycles in the microcomputer mode (22 SYSCLK cycles in the microprocessor mode) from the time the reset pulse is released until the first opcode fetch begins. When a watchdog overflow or an oscillator fault detection circuit generates a reset, the RESET pin is pulled low so that it resets other external components in the system. During a reset, RAM contents (except for register A and register B) remain unchanged, and the majority of the peripheral file bits are cleared to 0, with the exception of the control bits shown in Table 5-5.
5.4.1
Simple Reset Circuitry
An application must activate the RESET pin at power-up with an external input to RESET or an RC power-up circuit. The RESET pin must be held low until the clock signal is valid and VCC is within operating range. Figure 5-5 shows a simple reset circuit that holds RESET low during the power-up. The simple reset circuit shown in Figure 5-5 cannot handle short brownouts or power supply glitches. Voltage glitches can occur when a power switch is closed or power wires are connected. If your design is subject to these conditions, refer to the Reset Circuitry with Low-Voltage Detection (subsection 5.4.2, page 5-22). The TMS370 devices are not guaranteed to operate properly when VCC is outside of the recommended voltage range (4.5 to 5.5 volts).
5-20
Resets
Table 5-5. Control-Bit States Following a Reset
Register SCCR0 Control Bit P/C Mode MC PIN DATA COLD START OSC FLT FLAG Power-up Power- p Microcomputer 0 0 1 0 0 0 0 1 1 1 1 Warm Reset Microcomputer 0 0 See Note 1 See Note 1 0 0 See Note 1 1 1 1 1 Microprocessor 1 1 See Note 1 See Note 1 1 1 See Note 1 1 1 1 1
xPORT1 All 8 bits (See Note 2) xPORT2 All 8 bits (See Note 2) T1CTL2 TXCTL ADSTAT PACT
Notes:
WD OVRFL FLAG TX EMPTY TXRDY AD READY PACT TXRDY
1) State determined by cause of reset. See bit descriptions in Section 5.2. 2) Refers to port control registers with x = A, B, C, or D.
Figure 5-5. Simple Reset Circuit
VCC (4.5-5.5V) To other devices' resets
D1
10 k
TMS370
Reset in 2.7 k Manual reset 0.47 mF Reset out
Interrupts and System Reset
5-21
Resets
-
-
The RC network of 10 kW and 0.47mF provides a power-up rise time. If this power-up rise time is not long enough (depending on the rise time of the power supply you are using), you can use a larger capacitor. However, replacing the 10 kW resistor with a larger resistor can cause the voltage at the RESET pin to be less than VIH. The 2.7-kW resistor protects the RESET pin from the capacitor discharging directly into the pin when the pin is pulled low internally. The diode allows the capacitor to discharge quickly during a brownout or power-off situation.
Capacitors should not discharge directly into the RESET pin. Protect this pin from damage by using a resistor such as the 2.7 kW resistor shown in Figure 5-5.
5.4.2
Reset Circuitry With Low-Voltage Detection
It is recommended to have an asserted RESET during low-power or brownout conditions. In these instances, an active reset circuit with a low-voltage detection feature can be connected to the RESET pin. Figure 5-6 shows a typical circuit for using a supply voltage supervisor to assert RESET.
Figure 5-6. Typical Reset Circuit Using a Supply Voltage Supervisor
VCC To other devices' resets
Supply voltage supervisor
10 k
TMS370
Reset in Reset out Reset out
The supply voltage supervisor must not cause a drive conflict with the TMS370 RESET pin. Most importantly, the supply voltage supervisor should not drive
5-22
Resets
RESET high since the TMS370 can drive the pin low. However, a pull-up resistor is needed. To ensure the integrity of the contents of volatile memory (EEPROM, RAM), devices incorporating such memory require that the external RESET pin is active (low) while VCC is below its minimum specified operating level. Active reset circuitry prevents the EEPROM contents from being corrupted by improper instruction execution due to an insufficient VCC supply voltage and ensures that the EEPROM write control register (DEECTL) powers up in the correct state when VCC returns to its specified operating range. To guarantee the retention of RAM data when power is at 3.0 V to 4.5 V, RESET must be externally asserted and released only while VCC is within the recommended operating range of 4.5 V to 5.5 V.
Interrupts and System Reset
5-23
5-24
Running Title--Attribute Reference
Chapter 6
EPROM and EEPROM Modules
This chapter discusses the architecture and programming of the following:
-
Data EEPROM modules of the TMS370 family Program EPROM modules of the TMS370C6xx and TMS370C7xx devices.
Additional information about these modules is included in Chapter 18, Electrical Specifications and Timings, and in the TMS370 Family Applications Book (SPNA017). This chapter covers the following topics:
Topic
6.1 6.2 6.3 6.4
Page
Data EEPROM Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 Data EEPROM Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 Programming the Data EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6 Program EPROM Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10
Chapter Title--Attribute Reference
6-1
Data EEPROM Module
6.1 Data EEPROM Module
The entire TMS370 family (except TMS370CxAx and the TMS370xCx) contains data EEPROM modules. The TMS370 data EEPROM module contains a 256-byte array configured into eight 32-byte blocks. Devices can have multiple 256-byte arrays. Each additional array is also configured with eight 32-byte blocks. The first byte of each 256-byte array is the write protection register (WPR) for that array. This module also contains a voltage generator that provides a special precise programming voltage to the EEPROM array. This special voltage helps increase the reliability of the EEPROM and allows the TMS370 to program the EEPROM with a single VCC source. Reading the EEPROM module is identical to reading other internal memory and takes two system clock cycles. The CPU can fetch data and execute instructions from the EEPROM arrays. The data EEPROM module can be programmed on an array, a byte, or a single-bit basis. The memory can also be protected from inadvertent writing with a write-protect feature. The data EEPROM control register (DEECTL) and the WPR control the data EEPROM. The DEECTL register contains the bits needed to initiate and monitor EEPROM programming. The WPR of the given array contains the write protection bits for each 32-byte block of that data EEPROM array.
6-2
Data EEPROM Control Registers
6.2 Data EEPROM Control Registers
The data EEPROM can be write-protected, block by block (32 bytes), with the WPR(s). The DEECTL register determines the programming mode and when programming is initiated.
6.2.1
Write Protection Register (WPR)
The WPR(s) provide write protection for the data EEPROM contents. The WPR is the first byte of each 256-byte data EEPROM array and is located in BLK0 of this array, generally at address 1x00h (where x is either E or F). This implies that the WPR, for the 256-byte array, is itself protected whenever the BLK0 bit of that array is protected. There are eight blocks of equal size in the data EEPROM array. Each bit in the WPR corresponds to one of the blocks. Setting a bit to a 1 in this register protects the corresponding block. Figure 6-1 shows the block protected by each bit.
Figure 6-1. Write Protection Bits in an EEPROM Array
MSB 1x00h Write protection register BLK7 BLK6 BLK5 BLK4 BLK3 BLK2 BLK1 BLK0 BLK0 1x20h BLK1 1x40h BLK2 1x60h 1x80h 1xA0h BLK5 1xC0h BLK6 1xE0h BLK7 1xFFh BLK3 BLK4 0 = Write access allowed to the associated block 1 = Write protect block (write accesses not allowed to the associated block) Write protection register (WPR) [Memory address 1x00h] LSB
Once block 0 is protected, the write-protect configuration cannot be altered unless write protection is overridden by placing the microcomputer into the writeprotection override mode. (To enter the WPO mode, apply 12 volts to the MC pin while the RESET pin is a logic 1.) There is no write protection during a writeprotection override, and the WPR is considered a normal data location within the data EEPROM array during this time.
EPROM and EEPROM Modules
6-3
Data EEPROM Control Registers
Example 6-1 illustrates one way to program the WPR. In this example, the program protects blocks 0 and 2. Also, assume that the WPR contains the value 00h before the example begins.
Example 6-1. Write Protection Register Programming
DINT MOV MOV MOV EINT MOVW INCW JC MOV . . . #05,A A,&1F00h #3,P01A #2778,R011 #-1,R011 DELAY #0,P01A ;Disable interrupt ;Protect bits for BLK0 and ;BLK2 ;Set DEECTL to program 1's ;Set W1W0 and EXE bits ;Enable interrupt ;10 ms delay loop ;Clear W1W0 and EXE bits
DELAY
See TMS370 Family Applications Book (SPNA017) for more examples of programming the EEPROM module.
6.2.2
Data EEPROM Control Register (DEECTL)
The DEECTL register is located in the peripheral file at address P01A (101Ah), and controls the data EEPROM programming.
Data EEPROM Control Register (DEECTL) [Memory Address 101Ah]
Bit #
P01A
7
BUSY R-*
6
--
5
--
4
--
3
--
2
AP RW-0
1
W1W0 RW-0
0
EXE RW-0
R = Read, W = Write, -n = Value of the bit after the register is reset (-* = see the individual bit description)
Bit 7
BUSY. This bit is set during data EEPROM programming to indicate that an operation is in progress. Reading any location of the EEPROM during programming returns the data being programmed. In order to let the EEPROM voltages stabilize, the BUSY bit is set for 128 SYSCLK cycles:
-
After a reset, After an exit from a low-power mode, and After programming the EEPROM.
6-4
Data EEPROM Control Registers
If an attempt is made to access the EEPROM during this 128-cycle period, the data EEPROM holds the execution of the processor by asserting the WAIT signal until the 128 SYSCLK cycles are complete. 0 = EEPROM array is ready for access 1 = EEPROM array is not ready for access Bit 6-3 Bit 2 Reserved. Read data is indeterminate. AP. Array Program. Note: This bit operates differently for TMS370Cxxx devices (vs. '370CxxxA or '370CxxxB devices). See Section A.6, AP Bit in the DEECTL Register (DEECTL.2) on page A-6. The following applies to devices with a single or a multiple 256-byte array: In a single programming cycle, this bit programs the entire array space with the value specified by the W1W0 bit. However, the device must be in the WPO mode for the array to be programmed. Moreover, there is no write protection during WPO mode; the WPR is considered a normal data location within the data EEPROM array during this time. If the device is not in the WPO mode, the AP bit has no effect on the programming operation, and a single byte is programmed. 0 = Disables array programming 1 = Enables array programming Bit 1 W1W0. Write1/Write0. This bit determines whether to use the ones or zeroes programming mode (see Section 6.3, Programming the Data EEPROM, on page 6-6). This bit is write protected whenever the EXE bit is set. 0 = Write zeros 1 = Write ones Bit 0 EXE. Execute. This bit initiates the write operation defined by the remaining control register bits. When cleared, this bit terminates a programming operation in progress. If the application program reads a data EEPROM location while the EXE bit is set, the processor reads the data being programmed into the EEPROM. If software attempts a write to the EEPROM while the EXE bit is set, the data byte is ignored. 0 = Inactive 1 = Active
EPROM and EEPROM Modules
6-5
Programming the Data EEPROM
6.3 Programming the Data EEPROM
The DEECTL (P01A) register and the associated array's WPR (1x00h) register control the programming of the data EEPROM. Individual bits are programmed to a 1 or 0 under the control of the W1W0 bit and the EXE bit in the DEECTL register.
-
When the W1W0 bit is set, bit positions set to 1 in the data byte are programmed to 1 in the EEPROM byte; zeros are not changed. When the W1W0 bit is cleared, bit positions cleared to 0 in the data byte are programmed to 0 in the EEPROM byte; ones are not changed.
The EXE bit initiates EEPROM programming when set and disables programming when cleared. The WPR (1x00h) registers must have the corresponding protection bit cleared or be in the WPO mode to enable a data EEPROM write operation. (To enter the WPO mode, apply 12 volts to the MC pin while the RESET pin is a logic 1.) To load the data byte into the EEPROM module: 1) Perform a memory-write operation to the EEPROM at the desired address. The data byte is latched in the module, ready for the Execute command (EXE bit = 1). To prevent data corruption, ensure that nonmaskable interrupt routines do not access the EEPROM between the EEPROM write instruction and the point when the EXE bit is set to 1. 2) Following the memory cycle to the EEPROM address, write 03h (for W1W0 = 1) or 01h (for W1W0 = 0) to the DEECTL register to set the W1W0 and EXE bits. The W1W0 and the EXE bits must remain unchanged for the duration of the EEPROM timing parameter of tW(PGM)B to ensure proper programming. 3) When the program time has elapsed, reset the EXE bit with another write operation to the DEECTL register. If W1W0 = 1, the data that now resides in the programmed EEPROM location is the logical OR of the previous data stored in the location and the data written to the location. If W1W0 = 0, the data that now resides in the programmed EEPROM location is the logical AND of the previous data stored in the location and the data written to the location.
6-6
Programming the Data EEPROM
If a data value cannot be programmed by writing only ones or zeros, first perform the write-ones operation and follow it with a write-zeros operation (or write zeros followed by write ones). Figure 6-2 illustrates these operations. In the programming operations, only the EEPROM bits that do not match the data bits are programmed. Therefore, there is no need to read the EEPROM value to determine which bits to program.
Figure 6-2. EEPROM Programming Example
Data Byte (5Ah) 0 1 0 1 1 0 1 0
Write Ones (W1W0 = 1)
EEPROM Byte (1F60h)
X
X
X
X
X
X
X
X
Result (Logical OR)
X
1
X
1
1
X
1
X
Data Byte (5Ah)
0
1
0
1
1
0
1
0
Write Zeros (W1W0 = 0)
EEPROM Byte (1F60h)
X
1
X
1
1
X
1
X
Result (Logical AND)
0
1
0
1
1
0
1
0
The software should end the programming operation before entering a halt or standby state. When the microcomputer is in the halt or standby low-power mode, all operations of the data EEPROM module are stopped, and all DEECTL bits are cleared. Any EEPROM programming operation in progress is aborted when the halt is entered, and the data at the address being programmed is indeterminate. The subroutine in Example 6-2 loads the data byte 5Ah into the data EEPROM location 1F60h. Figure 6-2 illustrates the result of this subroutine.
EPROM and EEPROM Modules
6-7
Programming the Data EEPROM
Example 6-2. Data EEPROM Programming
The following subroutine loads the data byte 5Ah into the data EEPROM location 1F60h.
(a) (b) (c) (d) (e) (f) (g) (h) (i) (j) (k) (l) (m) (n) (o) (p) DATA DINT MOV MOV MOV EINT MOVW INCW JC MOV DINT MOV MOV MOV EINT MOVW INCW JC MOV . . . #5Ah,A A,&1F60h #03,P01A ; Disable all interrupts ; Write 5A to location 1F60h
DELAY1
DELAY2
; Write Ones: W1W0=1, EXE=1 ; Enable all interrupts #2778,R017 ; Begin tW(PGM)B delay (10 ms) #-1,R017 ; Decrement R017 DELAY1 ; Jump to DELAY1 if R017>0 #0,P01A ; Clear DEECTL. EXE=0 ; Disable all interrupts #5Ah,A ; Write 5A to location 1F60h A,&1F60h #01,P01A ; Write zeros: W1W0=0 EXE=1 ; Enable all interrupts #2778,R017 ; Begin tW(PGM)B delay (10 ms) #-1,R017 ; Decrement R017 DELAY2 ; Jump to DELAY2 if R017>0 #0,P01A ; Clear DEECTL. EXE=0
-
Disable all interrupts. When programming the data EEPROM, you must ensure that nonmaskable interrupt routines do not access the EEPROM between an EEPROM write instruction and the point when the EXE bit is set to 1 (steps a and i in Example 6-2), or data will be corrupted. Load the value 5Ah into the data EEPROM address 1F60h (step b). Begin a write-ones programming sequence (step c) by setting the W1W0 and EXE bits in the DEECTL register to a 1. Re-enable all interrupts (step d). The programming delay parameter, tW(PGM)B, (10 ms for this example--see Chapter 18, Electrical Specifications and Timings, for the required timing) is taken care of with a delay loop (steps f and g).
6-8
Programming the Data EEPROM
-
The number of loops required is 2778 (step e) and is derived in the following manner:
J J J
The delay loop (steps f and g) requires 18 SYSCLK cycles to complete if a jump is taken. An operating frequency of 5-MHz SYSCLK results in a system cycle time of 200 ns. The number of loops required is calculated as follows: loop count = tW(PGM)B / (system cycle time x delay loop cycle count) loop count = 10 ms / (200 ns x 18) = 10 ms / 3.6 s = 2778 Note: As an alternative, a timer can be used for this delay.
-
After the delay, clear the EXE bit (step h), re-enable all interrupts, and continue the write-zeros routine (steps i through p). The value 5Ah has now been programmed into location 1F60h of the data EEPROM.
-
Following an EEPROM write operation, the EEPROM voltage must stabilize before an EEPROM read operation is performed. The BUSY flag indicates the status of the EEPROM voltage. When BUSY is set, the EEPROM is not ready for a read operation. The BUSY flag is cleared to zero (0) by the EEPROM control logic when 128 system clock cycles have elapsed following the time that the EXE bit is cleared to 0.The BUSY bit remains set for 128 SYSCLK cycles: After a reset, After exit from a low-power mode, and After programming the EEPROM.
If an attempt is made to access the EEPROM during this 128 SYSCLK cycle period, the data EEPROM holds execution of the processor by asserting the WAIT signal until the 128 SYSCLK cycles are completed.
To prevent data corruption of the read or write EEPROM location, do not access EEPROM locations between writing data to the EEPROM address and setting the EXE bit to 1. In addition, you should disable interrupts during this time.
EPROM and EEPROM Modules
6-9
Program EPROM Modules
6.4
Program EPROM Modules
The program EPROM modules used in the TMS370 family replace the 2K- and 48K-byte program ROM within the TMS370 families for system prototypes or small production runs. The CPU can fetch data and execute instructions from these memory spaces. These modules consist of either an 8K-byte array or a 16K-byte array of EPROM. The following describes each EPROM device by total memory size:
-
8K- or 16K-byte EPROM devices Address area: 8K-byte array: 6000h - 7FFFh 16K-byte array: 4000h - 7FFFh Arrays controlled by register EPCTLM (address 101Ch, P01C)
J
-
J J
H H
24K-byte EPROM device (one 16K- and one 8K-byte array of EPROM) Address area: First 16K-byte array: 2000h - 5FFFh Next 8K-byte array: 6000h - 7FFFh Arrays controlled by: First 16K-byte array: register EPCTLL (address 101Eh, P01E) Next 8K-byte array: register EPCTLM (address 101Ch, P01C)
-
H H J H H
J
32K-byte EPROM device (two 16K-byte arrays of EPROM) Address area: First 16K-byte array: 2000h - 5FFFh Second 16K-byte array: 6000h - 9FFFh Arrays controlled by: First 16K-byte array: register EPCTLL (address 101Eh, P01E) Second 16K-byte array: register EPCTLM (address 101Ch, P01C)
H H J H H
Note:
EPCTLx Register Differs According to Device
The EPCTLL and EPCTLM registers operate differently for TMS370C758, TMS370C758A, and TMS370C758B. Refer to Section A.7 on page A-7.
-
48K-byte EPROM device (three 16K-byte arrays of EPROM) Address area: First 16K-byte array: 2000h - 5FFFh Second 16K-byte array: 6000h - 9FFFh Third 16K-byte array: A000h - DFFFh
J
H H H
6-10
Program EPROM Modules
J
Arrays are controlled by: H First 16K-byte array: register EPCTLL (address 101Eh, P01E) H Second 16K-byte array: register EPCTLM (address 101Ch, P01C) H Third 16K-byte array: register EPCTLH (address 1014h, P014)
Table 6-1 is a summary of the memory addresses and corresponding control registers for each EPROM size. The CPU accesses the arrays with normal memory read cycles. Write cycles to the program EPROM require a special sequence of events. This sequence is described in subsection 6.4.3, Programming the Program EPROM, page 6-13. An external voltage supply is needed at the MC pin to provide the necessary VPP for programming. The EPCTLL, EPCTLM, and EPCTLH registers in the peripheral file control the programming.
Table 6-1. EPROM Memory Map Summary
Device Parameter EPROM Size Memory Mapped '370C7x2 8K bytes 8K 6000h- 7FFFh '370C7x6 16K bytes 16K 4000h- 7FFFh '370C7x7 24K bytes 16K 2000h- 5FFFh 8K 6000h- 7FFFh EPCTLM P01C '370C7x8 32K bytes First 16K 2000h- 5FFFh EPCTLL P01E Second 16K 6000h- 9FFFh EPCTLM P01C First 16K 2000h- 5FFFh EPCTLL P01E '370C7x9 48K bytes Second 16K 6000h- 9FFFh EPCTLM P01C Third 16K A000h- DFFFh EPCTLH P014
Control EPCTLM EPCTLM EPCTLL Registers P01C P01C P01E Program EPROM control register--low array Program EPROM control register--middle array Program EPROM control register--high array
6.4.1
Erasing the EPROM
Before programming (windowed versions), the EPROM module is erased by exposing the device through the transparent window to high-intensity ultraviolet (UV) light (wavelength of 2537 angstroms). The recommended minimum exposure dose (UV intensity exposure time) is 15 watt-seconds per square centimeter. A typical 12 milliwatt-per-square-centimeter, filterless UV lamp will erase the device in 21 minutes. The lamp should be located about 2.5 centimeters above the chip during erasure. After erasure, the entire array is at logic 1 state. A programmed 0 can be erased to 1 only by exposure to ultraviolet light. Note that normal ambient light contains the correct wavelength for erasure. Therefore, when using a programmed device, you should cover the window with an opaque label. All devices are erased to a logical 1 at the factory.
EPROM and EEPROM Modules
6-11
Program EPROM Modules
Exposing the EPROM module to the ultraviolet light may also cause erasure in any EEPROM module. Any useful data stored in the EEPROM must be reprogrammed after exposure to UV light.
6.4.2
Program EPROM Control Register (EPCTLx)
The EPCTLL, EPCTLM, or EPCTLH (collectively referred to as "EPCTLx" in section 6.4.3) registers at addresses 101Eh, 101Ch, or 1014h, respectively, in the peripheral file control the programming of the program EPROM.
Program EPROM Control Register (EPCTLx) [Memory Addresses 101Eh, 101Ch, or 104Eh]
Bit #
P01C, P01E or P014
7
BUSY R-0
6
VPPS RW-0
5
--
4
--
3
--
2
--
1
W0 RW-0
0
EXE RW-0
R = Read, W = Write, -n = Value of the bit after the register is reset
Bit 7
BUSY. This bit reflects the value of the EXE bit.
Bit 6
VPPS. This bit determines whether the programming voltage (VPP) at the MC pin is connected to the EPROM module. 0 = Disables programming 1 = Enables programming
Bit 5-2 Bit 1
Reserved. Read data is indeterminate. W0. Write 0. This bit determines whether the programming of the zero bits (in the byte written) is enabled. 0 = Enables programming of 0 bits 1 = Disables programming of 0 bits
Bit 0
EXE. Execute. This bit initiates the write operation defined by the other control register bits. When cleared, this bit terminates the operation. 0 = Inactive 1 = Active
6-12
Program EPROM Modules
6.4.3
Programming the Program EPROM
Programming zero (0) to the EPROM is controlled by the EPCTLx register via the EXE bit and the VPPS bit.
-
The EXE bit initiates EPROM programming when set and disables programming when cleared. The VPPS bit connects the programming voltage (VPP) at the MC pin to the EPROM module.
VPPS (EPCTLx.6) and EXE (EPCTLx.0) should be set separately, and the VPPS bit should be set at least two microseconds before the EXE bit is set. After programming, the application should wait for four microseconds before any read attempt is made. Perform the programming operation (see Figure 6-3 on page 6-14) in the following sequence: 1) Supply the programming voltage to the MC pin. 2) Set (to 1) bit EPCTLx.6 (VPPS). 3) Write to the target EPROM location. 4) Set bit EPCTLx.0 (EXE). Wait at least two microseconds after step 2. 5) Wait for program time to elapse (250 microsecond). 6) Clear bit EPCTLx.0. Leave VPPS set to 1. 7) Read the byte being programmed; if the correct data is not read, repeat steps 4 through 6 for count (a number of) times to a maximum of 25. 8) Set bit EPCTLx.0 for final programming. 9) Wait for the program time to elapse (2 times count duration). 10) Clear bits EPCTLx.0 and EPCTLx.6.
EPROM and EEPROM Modules
6-13
Program EPROM Modules
Figure 6-3. EPROM Programming Operation
Start
VCC = 6 V MC = 13.2 V
Write to EPCTLx; set both VPPS and EXE bits to 1 Wait for 250 s
Count = 0
Write to EPCTL; clear EXE bit Write to EPCTLx; Set VPPS to 1 Increment Count Write to EPROM location
Count = 25?
Yes
No
Not OK Verify EPROM data OK Program the byte for count x 250 s
Clear both EXE and VPPS Note: VPPS and EXE are bits 6 and 0, respectively, of registers EPCTLx.
Programming operations require an external power supply at VPP (13.2 V), IPP (30 mA). Programming voltage (VPP) is supplied via the MC pin. This also automatically puts the microcontroller in the write protection override (WPO) mode. Programming voltage can be applied via the MC pin anytime after the RESET signal goes inactive high, and the MC pin can remain at VPP after programming (after the EXE bit is cleared). Applying programming voltage while RESET is active will set the microcontroller to reserved mode, where programming operations are inhibited.
6-14
Program EPROM Modules
6.4.4
Write Protection of the Program EPROM
To override the EPROM write protection, the VPP must be applied to the MC pin, and the VPPS bit (EPCTL.6) must be set. This dual requirement ensures that the program EPROM is not accidentally overwritten during data EEPROM operations when VPP is applied to the MC pin. Data EEPROM can be programmed when the VPPS bit is set.
EPROM and EEPROM Modules
6-15
6-16
Running Title--Attribute Reference
Chapter 7
Timer 1 (T1) Module
This chapter discusses the architecture and programming of the T1 module and covers the following topics:
Topic
7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9
Page
T1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 General-Purpose Timer Components . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 Operating Modes of the General-Purpose Timer . . . . . . . . . . . . . . . . 7-10 Edge-Detection Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-15 Clock Prescaler/External Clock Source . . . . . . . . . . . . . . . . . . . . . . . . 7-16 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-20 WD Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-21 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-29 T1 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-30
Chapter Title--Attribute Reference
7-1
T1 Overview
7.1
T1 Overview
The T1 module of the TMS370 family provides enhanced timer resources to perform realtime system control. This module contains a general-purpose timer and a watchdog (WD) timer. Both timers allow the program selection of input clock sources (realtime, external event, or pulse accumulate) with multiple 16-bit registers (input capture and compare) for special timer function control. Table 7-1 shows timer solutions for different system requirements.
Table 7-1. Timer-System Solutions
Requirement Realtime system control Input pulse-width measurement External event synchronization Timer output control PWM output control System integrity Timer Solution Interval timers with interrupts Pulse accumulate or input capture functions Event count function Compare function PWM output function WD function
7.1.1
Physical Description
The T1 module, shown in Figure 7-1, has the following components:
-
A 16-bit general-purpose timer that provides capture, compare, and event functions.
J J J
The capture function latches the counter value to the occurrence of an external input. The event function keeps a cumulative total of the transitions on the T1EVT pin. The compare function triggers when the counter matches the contents of a compare register.
7-2
A 16-bit WD timer that software can reconfigure as a simple counter/timer, an event counter, or a pulse accumulator if the WD feature is not needed. A prescaler/clock source that determines the independent clock sources for the general-purpose timer and for the WD timer. A selectable edge-detection circuitry that senses active transitions on the T1IC/CR pin.
T1 Overview
-
Interrupts The module can be programmed to issue interrupts on the occurrence of the following:
-
J J J J
A capture A compare equal A counter overflow An external edge detect
I/O pins The T1 module has three I/O pins that can be dedicated for counter functions or as general-purpose I/O pins. These are as follows:
J J J
T1EVT, an input to the event counter or the external clock source T1IC/CR, an input to the input capture, counter reset, or PWM circuit T1PWM, the PWM output
Table 7-2 on page 7-4 shows the definitions of these pins, according to operating mode.
Timer 1 (T1) Module
7-3
T1 Overview
Figure 7-1. T1 Block Diagram
External pin connections
T1IC/CR
Edge select
16-bit capt/comp register
External pin connection
MUX
16-bit counter
16
PWM toggle
T1PWM
T1EVT
8-bit prescaler
16-bit compare register
Interrupt logic
MUX
16-bit WD counter (aux. timer)
Interrupt logic
Table 7-2. T1 I/O Pin Definitions
Pin T1IC/CR T1PWM T1EVT Dual Compare Mode Counter reset input PWM output External event input or pulse accumulate input Capture/Compare Mode Input capture 1 input PWM output External event input or pulse accumulate input
7.1.2
Operating Modes
The general-purpose T1 module has the following two modes of operation:
-
Dual compare mode. The timer is configured to provide two compare registers, an external or software timer reset, an internal or external clock source, and a programmable pulse-width modulated (PWM) output. The PWM output can be configured to toggle on specified events. Capture/compare mode. The timer is configured to provide one input capture register and one compare register for use with the general-purpose timer. The compare register can be used to provide periodic interrupts to the TMS370 CPU. The capture register can be configured to capture the current timer value upon either edge of an external input.
7-4
T1 Overview
7.1.3
Control Registers
The T1 control registers are located at addresses 1040h to 104Fh and occupy peripheral file frame 4. The function of each location is shown in Table 7-3.
Table 7-3. T1 and WD Timer Memory Map
Peripheral File Location P040 P041 P042 P043 P044 P045 P046 P047 P048 P049 P04A P04B P04C P04D P04E P04F Symbol T1CNTR T1C T1CC WDCNTR WDRST T1CTL1 T1CTL2 T1CTL3 T1CTL4 T1PC1 T1PC2 T1PRI Name T1 Counter -- MSbyte T1 Counter -- LSbyte Compare Register -- MSbyte Compare Register -- LSbyte Capture/Compare Register -- MSbyte Capture/Compare Register -- LSbyte WD Counter -- MSbyte WD Counter -- LSbyte WD Reset Key T1 Control Register 1 T1 Control Register 2 T1 Control Register 3 T1 Control Register 4 T1 Port Control Register 1 T1 Port Control Register 2 T1 Interrupt Priority Control Register Description 16-bit resettable counter 16-bit compare register 16-bit capture/compare register 16-bit WD counter Resets the WD timer. Controls the prescaler inputs to the WD timer and to the general-purpose timer. Controls the T1 and WD overflow interrupts and contains the T1 software reset bit. Controls the edge-detect and compare interrupts. Controls the mode of operation and various functions of the T1 input and output pins. Controls the I/O functions of the T1 module and T1EVT pin. Controls the I/O functions of the T1 module, T1IC/CR pin, and T1PWM pin. Controls the level of the T1 interrupt.
Timer 1 (T1) Module
7-5
General-Purpose Timer Components
7.2 General-Purpose Timer Components
The general-purpose timer uses a 16-bit counter, a compare register, and a capture/compare register to provide event, compare, and capture functions.
7.2.1
16-Bit Resettable Counter
The free-running, 16-bit counter (T1CNTR) is clocked by the output of the prescaler/clock source. The program can access the 16-bit counter at P040 (T1 counter MSbyte) and P041 (T1 counter LSbyte) in peripheral file frame 4.
-
During initialization, the counter is loaded with the value 0000h and begins its count. If the counter is not reset before reaching FFFFh, the counter rolls over to 0000h and continues counting. Upon counter rollover, the T1 OVRFL INT FLAG bit (T1CTL2.3) is set, and a timer interrupt is generated if the T1 OVRFL INT ENA bit (T1CTL2.4) is set. During counting, the counter can be reset to 0000h by any of the following:
J J J J
A 1 written to the T1 SW RESET bit (T1CTL2.0) A compare equal condition from the dedicated T1 compare function A system reset An external pulse on the T1IC/CR pin (dual compare mode only) if the T1CR RST ENA bit (T1CTL4.1) is set to a 1.
You can select the external-transition direction on the T1IC/CR pin, low-to-high or high-to-low, to reset the counter. To do this, use the T1EDGE POLARITY bit (T1CTL4.2). Special circuitry prevents the contents of the T1CNTR register from changing in the middle of a 16-bit read operation. See the note in Section 7.9 on page 7-30.
7.2.2
Compare Register
The compare register circuit consists of a 16-bit wide, read/write data register (T1C) and logic to compare the counter's current value with the value stored in the compare register. The program can access the 16-bit compare register at P042 (compare register MSbyte) and P043 (compare register LSbyte) in peripheral file frame 4.
7-6
General-Purpose Timer Components
When the counter's value matches the compare register value, then the circuit performs the following actions:
-
Sets the T1C1 INT FLAG bit (T1CTL3.5) to 1. Clocks the output latch to toggle the T1PWM output pin if the T1C1 OUT ENA bit (T1CTL4.6) is set. Generates a T1 interrupt if the T1C1 INT ENA bit (T1CTL3.0) is set. Resets the counter if the T1C1 RST ENA bit (T1CTL4.4) is set (dual compare mode only).
The compare register is initialized to 0000h following a reset. Special circuitry prevents the contents of the T1C register from changing in the middle of a 16-bit read operation. See the note in Section 7.9 on page 7-30. Note: If the counter is programmed to reset when its value equals the contents of the compare register, the reset occurs on the following counter clock cycle (after a prescale). However, the compare flag is set and the interrupt event occurs during the clock cycle that incremented the counter to equal the compare-equal value. As a result, there could be a delay of up to 256 system clock cycles (depending on the prescale tap in use) from the time that the event is recognized by the program until the counter actually resets to zero. If the program writes to the compare register during this interval, the counter cannot be reset during the following counter clock cycle. The compare register value required for a specific timing application can be calculated using the following formula: t Compare Value = PS x 1 SYSCLK -1
where: t= SYSCLK = = PS = desired timer compare period (seconds) CLKIN/4 for divide-by-4 (external clock frequency) CLKIN/1 for divide-by-1 clock 1, 4, 16, 64, or 256, depending on the prescale tap selected
Table 7-4 provides some sample compare register values to achieve the various desired timings using a 5 MHz SYSCLK.
Timer 1 (T1) Module
7-7
General-Purpose Timer Components
Table 7-4. T1 Compare Values: (5 MHz SYSCLK)
Time Seconds 0.0005 0.001 0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.5 1.0 2.0 3.0 mSeconds 0.5 1 2 5 10 20 50 100 200 500 1000 2000 3000 Prescale None None None None None /4 /4 /16 /16 /64 /256 /256 /256 T1 Compare Register Value (N) Decimal 2499 4999 9999 24999 49999 24999 62499 31249 62499 39062 19530 39061 58593 Hex 009C3h 01387h 0270Fh 061A7h 0C34Fh 061A7h 0F423h 07A11h 0F423h 09896h 04C4Ah 09895h 0E4E1h Percent Error (See Note) 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.001 0.001 0.001
Note: Percent of error induced by the T1 formula. This error margin varies, depending on the desired timer compare period and the minimum timer resolution (PS x (1/SYSCLK)).
7.2.3
Capture/Compare Register
The 16-bit wide capture/compare register (T1CC) serves one of two functions, depending on the operating mode. The T1CC register is located at P044 (capture/compare register MSbyte) and P045 (capture/compare register LSbyte) in peripheral file frame 4. Special circuitry prevents the contents of the T1CC register from changing in the middle of a 16-bit read operation. See the note in Section 7.9 on page 7-30.
7.2.3.1
Dual Compare Mode
In the dual compare mode, the T1CC register acts as a read/write compare register. It functions exactly like the compare register described in subsection 7.2.2 except that T1CC cannot reset the counter. When the counter value matches the capture/compare register value, the circuit performs the following:
7-8
Sets the T1C2 INT FLAG bit (T1CTL3.6) to 1. Clocks the output latch to toggle the T1PWM output pin if the T1C2 OUT ENA bit (T1CTL4.5) is set. Generates a T1 interrupt if the T1C2 INT ENA bit (T1CTL3.1) is set.
General-Purpose Timer Components
7.2.3.2
Capture/Compare Mode
In the capture/compare mode, the edge detection signal captures the current counter content, loads it into the T1CC register, and sets the T1EDGE INT FLAG bit (T1CTL3.7).
Timer 1 (T1) Module
7-9
Operating Modes of the General-Purpose Timer
7.3 Operating Modes of the General-Purpose Timer
The operating mode of the T1 general-purpose timer determines whether the capture/compare register functions as a capture register in the capture/ compare mode or as a compare register in the dual compare mode. The T1 MODE bit (T1CTL4.7) selects the mode as follows: T1 MODE = 0 = dual compare mode T1 MODE = 1 = capture/compare mode
7.3.1
Dual Compare Mode
The dual compare mode provides the following:
-
A 16-bit compare register (called compare 1) A 16-bit capture/compare register that acts as a compare register (called compare 2) A 16-bit external, resettable counter A timer output pin
These components allow the timer to act as an interval timer, a PWM output, simple output toggle, or to perform other timer functions. The dual compare mode is shown in Figure 7-2. The dual compare mode continuously compares the contents of the two compare registers to the current value of the 16-bit counter.
-
If the compare 1 register equals the counter, the circuit conducts the following:
J J J J
Sets the T1C1 INT FLAG bit (T1CTL3.5) to 1. Clocks the output latch to toggle the T1PWM output pin if the T1C1 OUT ENA bit (T1CTL4.6) is set. Generates a timer 1 interrupt if the T1C1 INT ENA bit (T1CTL3.0) is set. Initiates a counter reset if the T1C1 RST ENA bit (T1CTL4.4) is set.
Additionally, you can program an interval timer function by using the compare-equal condition to generate a system interrupt combined with the counter reset function.
7-10
Operating Modes of the General-Purpose Timer
-
If the compare 2 register equals the counter, then the circuit conducts the following:
J J J
Sets the T1C2 INT FLAG bit (T1CTL3.6) to 1. Clocks the output latch to toggle the T1PWM output pin if the T1C2 OUT ENA bit (T1CTL4.5) is set. Generates a T1 interrupt if the T1C2 INT ENA bit (T1CTL3.1) is set.
The compare 2 register can be used as an additional system timing function.
Figure 7-2. Dual Compare Mode
T1CC.15-0
16-bit LSB capture/compare register MSB T1C2 INT FLAG
Prescaler clock source
T1CTL3.6 T1CTL3.1 T1C2 INT ENA
Output enable
T1CNTR.15-0
LSB MSB 16-bit counter Reset T1C1 RST ENA
Compare= 16 Compare=
T1CTL4.5
T1C2 OUT ENA Toggle 1 Level 2 Int
External pin connection
T1PC2.7-4
T1PWM
T1C1 INT FLAG T1CTL3.5
T1CTL4.6
T1C1 OUT ENA
T1C.15-0
16-bit LSB compare register MSB
T1CTL3.0 T1C1 INT ENA
T1CTL4.3
T1CR OUT ENA
External pin connection
T1CTL2.0 T1 SW RESET
T1CTL4.4
T1PC2.3-0
T1IC/CR
T1CTL4.1 T1CR RST ENA
Edge select
T1 OVRFL INT FLAG T1CTL2.3
T1CTL2.4 T1 OVRFL INT ENA
T1EDGE INT FLAG
T1 PRIORITY T1PRI.6 Level 1 Int 0
T1CTL4.0 T1EDGE DET ENA T1CTL4.2 T1EDGE POLARITY
T1CTL3.7 T1CTL3.2 T1EDGE INT ENA
Note:
The annotations on this diagram identify the register and the bit(s) in the peripheral frame. For example, the actual address of T1CTL2.0 is 104Ah, bit 0, in the T1CTL2 register.
Timer 1 (T1) Module
7-11
Operating Modes of the General-Purpose Timer
7.3.1.1
PWM Applications
Either compare register can be used to toggle the T1PWM output pin when a compare-equal condition occurs. Using both compare registers to control the T1PWM pin allows direct PWM generation with minimal CPU software overhead. In typical PWM applications, the compare registers are loaded as follows:
-
The compare 1 register is loaded with the periodic interval and configured to allow a counter reset on a compare-equal condition. The compare 2 (capture/compare) register is loaded with the pulse width to be generated within that interval. The program pulse width can be changed by the application program during the timer operation to alter the PWM output. For high-speed control applications, a minimum pulse width of 200 ns and a period as low as 400 ns can be maintained when a 5-MHz SYSCLK is used.
7.3.1.2
The PWM output can be used to support time-critical control applications. In these applications, an external input (T1IC/CR) is typically used to: Reset the counter. Generate a timer interrupt. Toggle the T1PWM pin to start the PWM output.
The compare function then toggles the output after the programmed pulse width has elapsed.
Input Edge Detect
The input edge detect function is enabled under program control by the T1EDGE DET ENA bit (T1CTL4.0); upon the next occurrence of the selected edge transition, the following occurs:
-
The T1EDGE INT FLAG bit (T1CTL3.7) is set. A timer interrupt is generated (if T1EDGE INT ENA = 1). The T1PWM output pin is toggled (if T1CR OUT ENA = 1).
The T1EDGE POLARITY bit (T1CTL4.2) selects the active input transition. In the dual compare mode, the edge detect function must be re-enabled after each valid edge detect.
7-12
Operating Modes of the General-Purpose Timer
7.3.1.3
Clock Input
The clock input to the 16-bit counter (T1CNTR) is either the internal system clock, with or without prescale, or the external clock (T1EVT). The clock pulse to the counter is always synchronized with the system clock. The counter (T1CNTR) is free-running except when it receives a reset pulse from one of the following sources:
-
A 1 written to the T1 SW RESET (T1CTL2.0) bit A compare equal condition from the dedicated T1 compare function A system reset An external pulse on the T1IC/CR pin (dual compare mode)
The counter rolls over to 0000h if it is not reset before a count of FFFFh. When this rollover occurs, the counter sets the T1 OVRFL INT FLAG (T1CTL2.3), generates an interrupt if the T1 OVRFL INT ENA bit (T1CTL2.4) is set, and continues counting.
7.3.2
Capture/Compare Mode
In the capture/compare mode, T1 provides the following:
-
A 16-bit input capture register for external timing and pulse-width measurement. A 16-bit compare register for use as a programmable interval timer. This register functions the same as compare 1 does in the dual compare mode described in subsection 7.3.1, including the ability to toggle the PWM pin.
The capture/compare mode is shown in Figure 7-3.
Timer 1 (T1) Module
7-13
Operating Modes of the General-Purpose Timer
Figure 7-3. Capture/Compare Mode
T1CC.15-0
Toggle LSB 16-bit capture/compare MSB register T1C1 OUT ENA
External pin connection
T1PC2.7-4
T1PWM
Prescaler clock source
T1CTL4.6
T1CNTR.15-0
LSB MSB 16-bit counter 16 T1C1 INT FLAG Compare= Reset
T1 PRIORITY
T1CTL3.5 T1CTL3.0
T1C.15-0
T1 SW RESET T1C1 T1CTL2.0 RST ENA 16-bit LSB compare register MSB
T1C1 INT ENA
T1 OVRFL INT FLAG
T1CTL4.4
External pin connection
T1CTL2.3 T1CTL2.4
T1 OVRFL INT ENA T1EDGE DET ENA T1EDGE INT FLAG
T1PC2.3-0
T1IC/CR Edge select
T1CTL3.7 T1CTL4.0 T1CTL3.2 T1CTL4.2
T1EDGE POLARITY T1EDGE INT ENA
On the occurrence of valid input on the T1IC/CR pin, the following occurs:
-
The current counter value is loaded into the 16-bit input capture register. The T1EDGE INT FLAG bit (T1CTL3.7) is set. If T1EDGE INT ENA bit (T1CTL3.2) is set, a timer interrupt is generated.
The input detect function is enabled by the T1EDGE DET ENA bit (T1CTL4.0), with the T1EDGE POLARITY bit (T1CTL4.2) selecting the active input transition. In the capture/compare mode, the edge detect function, once enabled, remains enabled following a valid edge detect.
7-14
IIII
Level 1 Int 0 1 Level 2 Int
T1PRI.6
Edge-Detection Circuitry
7.4 Edge-Detection Circuitry
The edge detection circuitry senses active transitions on the T1 input capture/ counter reset pin (T1IC/CR). The T1EDGE POLARITY bit (T1CTL4.2) determines whether the active transition is low-to-high or high-to-low. The module sets the T1EDGE INT FLAG (T1CTL3.7) when an active transition is detected. The program must reset this flag.
7.4.1
Dual Compare Mode
In this mode, the program must set the T1EDGE DET ENA bit (T1CTL4.0) to re-enable the circuit after each edge detection. Writing a 1 to this bit enables the detect circuit to look for the next correct level transition. After this active transition occurs, the T1EDGE DET ENA bit is cleared. When the edge detection circuit is enabled and detects the appropriate edge transition, the T1EDGE INT FLAG bit (T1CTL3.7) is set. When the T1CR RST ENA bit (T1CTL4.1) is set, the selected edge resets the counter. If the T1CR OUT ENA bit (T1CTL4.3) is set, the selected edge toggles the T1PWM output latch. The T1EDGE POLARITY bit (T1CTL4.2) determines which edge polarity (rising or falling) is detected.
7.4.2
Capture/Compare Mode
When the appropriate (rising or falling) transition is detected, the edge detection circuit signals the capture register to load the current counter value if the T1 EDGE DET ENA bit is set. The T1EDGE POLARITY bit determines which edge of the signal on the T1IC/CR pin to detect. The input detect function is enabled by the T1EDGE DET ENA bit, with T1EDGE POLARITY selecting the active input transition. In the capture/ compare mode, the edge detect function, once enabled, remains enabled following a valid edge detect.
Timer 1 (T1) Module
7-15
Clock Prescaler / External Clock Source
7.5 Clock Prescaler/External Clock Source
A prescaler is a circuit that slows the rate of a clocking source to a counter. This block, illustrated in Figure 7-4, allows the selection of the clock inputs (sources) to the general-purpose counter and to the WD counter independently. Each counter has three bits in the T1CTL1 register (see subsection 7.9.1, page 7-32) that determine whether the counter is clocked by one of the prescaled system clock values or by the external clock source (T1EVT).
Figure 7-4. T1 System Clock Prescaler
Event
Accumulation General-purpose counter clock Frequency (SYSCLK)
External pin connection
4
16
64
256 T1 Select
Prescaler WD Select 4 16 64 256
T1EVT
SYNC WD counter clock
Accumulation Event
For the hard WD configuration of the mask-ROM device, the clock source comes only from one of the four taps from the prescaler that provide a system clock divided by 4, 16, 64, or 256.
The counter clock sources can be any of the following:
7-16
A system clock with no prescale No clock (the counter is stopped) An external source that is synchronized with the system clock (event counter operation) A system clock while the external input is high (pulse accumulation) One of four taps from the prescaler that provide a system clock divided by 4, 16, 64, or 256
Clock Prescaler / External Clock Source
The external clock input to the module (T1EVT) must not exceed SYSCLK/2. If the application does not require the external clock, the T1EVT pin can be reconfigured as a digital I/O pin. The event input is not routed through the prescaler, so the T1 module can use different taps of the prescaler for T1 and the WD timer. The maximum counter duration when the internal clock is used is determined by the internal system clock time (SYSCLK) and the prescale tap. These relationships are shown below: Maximum Counter Duration (seconds) Counter Resolution where: SYSCLK PS = = = = = = = = = 216 x PS x (1/SYSCLK) PS x (1/SYSCLK) CLKIN/4 for divide-by-4 clock CLKIN/1 for divide-by-1 clock 1 for no prescale 4 for divide by 4 16 for divide by 16 64 for divide by 64 256 for divide by 256
Table 7-5 gives the real-time counter overflow rates for various crystal and prescaler values. Software can configure the overflow rates for the WD counter as shown in Table 7-5 or as the value shown divided by two if the WD OVRFL TAP SEL bit (T1CTL1.7) is set (see Section 7.7 on page 7-21). This bit configures the WD counter as either a 15-bit counter when set or a 16-bit counter when cleared.
Timer 1 (T1) Module
7-17
Clock Prescaler / External Clock Source
Table 7-5. Counter Overflow Rates
SYSCLK Frequency (MHz) 0.5 Register T1CTL1 Bits SELECT2 0 0 0 0 1 1 1 1 SELECT1 0 0 1 1 0 0 1 1 SELECT0 0 1 0 1 0 1 0 1 Divide By 216 (P.A.) (Event) (Stop) 218 220 222 224 2000 0.131 0.524 2.10 8.39 33.6 1 2.5 5
System Clock Period (ns) 1000 0.066 0.262 1.05 4.19 16.8 400 0.026 0.105 0.419 1.68 6.71 200 0.013 0.052 0.210 0.839 3.355
Time is given in seconds. Not applicable. Divide-by-1 clock can operate only from a minimum of 2 MHz SYSCLK to a maximum of 5 MHz SYSCLK.
7.5.1
Event Counter Mode
When you use the event counter clock source, the 16-bit counter is programmable as a 16-bit event counter. An external high-to-low transition on the T1EVT pin provides the clock for the internal timer.
7.5.2
Pulse Accumulator Mode
When you use the pulse accumulator clock source, the 16-bit counter is programmable as a 16-bit pulse accumulator. An external input on the T1EVT pin is used to gate the internal system clock to the internal timers. While T1EVT input is logic one (high), the timer is clocked at the system clock rate and counts system clock pulses until the T1EVT pin returns to logic zero. The pulse accumulator mode keeps a cumulative count of SYSCLK pulses gated by the T1EVT signal as shown in Figure 7-5.
7-18
Clock Prescaler / External Clock Source
Figure 7-5. Pulse Accumulation
T1EVT
SYSCLK
Counter Value
Timer 1 (T1) Module
7-19
Interrupts
7.6 Interrupts
In dual compare mode, any of the following four separate events can generate an interrupt:
-
Compare equal from compare register 2 if the T1C2 INT ENA bit (T1CTL3.1) is set Compare equal from compare register 1 if the T1C1 INT ENA bit (T1CTL3.0) is set Counter overflow if the T1 OVRFL INT ENA bit (T1CTL2.4) is set Edge detect is set if the T1EDGE INT ENA bit (T1CTL3.2) is set
In the capture/compare mode, any of the following three separate events can generate an interrupt: Compare equal if the T1C1 INT ENA bit (T1CTL3.0) is set Counter overflow if the T1 OVRFL INT ENA bit (T1CTL2.4) is set Input capture acknowledge if the T1EDGE INT ENA bit (T1CTL3.2) is set
Note: All set and enabled interrupt flags must be cleared before the processor exits the T1 interrupt routine. If the flags are not reset, the processor enters the T1 interrupt routine again before continuing with the mainstream program. If the flag bits are never reset, the program continually enters the interrupt service routine.
7-20
WD Timer
7.7
WD Timer
The WD timer can be configured as one of the three different mask options.
-
A standard WD (see note below):
J J J
For ROMless devices with revision A: TMS370C1xxA and TMS370C2xxA For Mask-ROM devices with revision A: TMS370C0xxA, TMS370C3xxA, and TMS370C4xxA For EPROM devices with revision A: TMS370C6xxA, TMS370C7xxA, SE370C6xxA, and SE370C7xxA
-
A hard WD (see note below):
J J
For Mask-ROM devices with revision A: TMS370C0xxA, TMS370C3xxA, and TMS370C4xxA For EPROM devices with revision B: TMS370C7xxB and SE370C7xxB
-
A simple counter (see note below) for mask-ROM devices with revision A: TMS370C0xxA, TMS370C3xxA, and TMS370C4xxA Hard WD and Simple Counter Advantages
Note:
The hard WD and simple counter options provide an improvement to the WD counter circuitry: the hard WD option enables the WD counter reset ability at all times and the simple counter option disables the WD counter reset ability at all times. The additional simple counter option is available only on TMS370CxxxA devices. The hard WD option is available on both TMS370CxxxA and TMS370C7xxB devices. Refer to Section A.1, page A-2, for the differences between each TMS370Cxxx device. ROM devices with revision A can be configured with any of the three options listed above. All ROMless devices with revision A are configured as a standard WD. All EPROM devices with revision A are configured as a standard WD, and EPROM devices with revision B are configured as a hard WD. The WD timer, shown in Figure 7-6, consists of the following blocks:
-
A 16-bit, resettable WD/event counter that provides up to 224 clock cycles between counter overflows, depending on the prescaler tap used. The program can read the contents of this counter at locations P046 (WD counter MSbyte) and P047 (WD counter LSbyte) in the peripheral file.
Timer 1 (T1) Module
7-21
WD Timer
Figure 7-6. WD Timer
A prescaled clock input selection or external clock that functions the same as in the general-purpose timer (see Section 7.2, on page 7-6). A WD reset key that is used to reset the WD counter (WDRST-P048). An overflow flag that is set whenever the WD counter overflows.
WDCNTR.15-0
16-bit WD counter Clock prescaler Reset
WD OVRFL INT FLAG
T1CTL2.5
T1CTL1.7
WD OVRFL TAP SEL WD reset key
WDRST.7-0
7-22
WD Timer
7.7.1
Standard WD Configuration
The standard WD can be configured as either a WD or as a simple counter through setting or clearing the WD OVRFL RST ENA bit (T1CTL2.7) in the software. Figure 7-7 illustrates the block diagram of the standard WD.
Figure 7-7. Standard WD Block Diagram
WDCNTR.15-0
16-bit WD counter WD OVRFL INT FLAG
T1CTL2.6
Interrupt WD OVRFL INT ENA
T1CTL2.5
Reset
Clock Prescaler
T1CTL1.7
WD OVRFL TAP SEL WD reset key
T1CTL2.7
System reset WD OVRFL RST ENA
WDRST.7-0
The standard WD can be configured in one of two modes: WD mode or nonWD mode.
7.7.1.1
WD Mode
In the WD mode (WD OVRFL RST ENA = 1), the WD timer generates a system reset if the counter overflows or if the WD counter is reinitialized by an incorrect value; a system reset pulls the RESET pin low for eight system clock cycles. The required reinitialization frequency is determined by the system clock frequency, the prescaler/clock source selected, and whether the WD OVRFL TAP SEL bit (T1CTL1.7) is set for 15- or 16-bit counter rollover. The WD overflow times are the same as those given in Table 7-5, page 7-18, when the timer is configured as a 16-bit counter (WD OVRFL TAP SEL = 0). Divide the times in Table 7-5 in half when the timer is configured as a 15-bit counter (WD OVRFL TAP SEL =1). With a 5-MHz SYSCLK, the WD-counter overflow times range from 6.55 ms to 3.35 seconds. These values are selected before the timer enters the WD mode because once the software enables the WD reset function (WD OVRFL RST ENA = 1), subsequent writes to these control bits are ignored. Writes to these WD control bits can occur only following a reset.
Timer 1 (T1) Module
7-23
WD Timer
To reinitialize the WD counter, write a predefined value to the WD reset key (WDRST) located in the peripheral file at P048. The correct reset key alternates between 55h and AAh, beginning with 55h following the enable of the WD reset function. Writes of the correct values must occur before the timer overflow period. A write of any value other than the correct predefined value to the WD reset key is interpreted as a lost program, and a system reset is initiated. A WDcounter overflow or incorrect reset key sets the WD OVRFL INT FLAG bit (T1CTL2.5) to 1. The program can read this flag after a reset to determine the source of the reset. WD resets are not prevented when the flag is set. Note: A standard WD is disabled in low-power mode (see Section 7.8 on page 7-29). The routine in Example 7-1 initializes the WD in the standard WD mode to generate a system reset when the counter overflows. The watchdog counter is set to 16 bits in length, and the full 8-bit prescale tap is used.
Example 7-1. Standard WD Initialization
. . ;Set up WD timer for a 24-bit countdown time. ; OR #70h,P049 ; Set the WD overflow tap to 16 bits ; and select the /256 prescale value OR #0C0h,P04A ; WD timer reset is enabled along ; with enabling the WD timer ; interrupt. . . The WD timer has now been initialized to cause a system reset if the counter is not reset before reaching FFFFh. To reset the counter, the code must write an alternating 55h and AAh, starting with 55h, to the WD timer reset key register (P048), such as: . . MOV #55h,P048 ; First write to WD RESET KEY . . MOV #0AAh,P048 ; Next write to WD RESET KEY . . MOV #55h,P048 ; Next write to WD RESET KEY . .
7-24
WD Timer
7.7.1.2
Non-WD Mode
In the non-WD mode (WD OVRFL RST ENA bit = 0), the WD counter can be used as an event counter, a pulse accumulator, or an interval timer. In this mode, the system reset function is disabled; to reinitialize the WD counter, write any value to the WD reset key (WDRST). In realtime control applications, the timer overflow rates are determined by the system clock frequency, the prescaler/clock source value selected, and the value of the WD OVRFL TAP SEL bit. If the WD counter is not reset before overflowing, the counter rolls over to either 0000h or 8000h, as determined by the WD OVRFL TAP SEL bit, and continues counting. Upon counter overflow, the WD OVRFL INT FLAG bit is set, and a timer interrupt is generated if the WD OVRFL INT ENA bit is set. Alternately, an external input on the T1EVT pin can be used with the WD timer to provide an additional 16-bit event counter or pulse accumulator.
7.7.2
Hard WD Configuration
In the hard WD configuration, you can operate the WD timer only as a WD. Upon the powerup reset, the hard WD is enabled, and the WD INPUT SELECT0-1 bits (T1CTL1.4-5) are cleared (system clock/4). Figure 7-8 is a block diagram of the hard WD.
Figure 7-8. Hard WD Block Diagram
WDCNTR.15-0
16-bit WD counter WD OVRFL INT FLAG
T1CTL2.5
Reset
Clock prescaler
T1CTL1.7 WD OVRFL TAP SEL
WD reset key
System reset
WDRST.7-0
The hard WD provides additional system integrity. If the counter overflows or if the WD timer is reinitialized by an incorrect value, the hard WD generates a system reset, which pulls the RESET pin low for eight system clock cycles. The required reinitialization frequency is determined by the system clock freTimer 1 (T1) Module
7-25
WD Timer
quency, WD INPUT SELECT0 and 1 (T1CTL1.4 and T1CTL1.5), the prescaler/clock source selected, and whether the WD OVRFL TAP SEL bit is set for 15- or 16-bit counter rollover. The WD INPUT SELECT2 bit (T1CTL1.6) is functionally interpreted as 1 at all times. The WD INPUT SELECT0-1 bits and WD OVRFL TAP SEL bit can be modified at any time. Your program should reinitialize these bits after a reset, and periodically thereafter, to ensure a corrected counter overflow rate and to protect against any hardware or software corruptions. The WD timer is reinitialized by writing a predefined value to the WD reset key (WDRST) located in the peripheral file at P048. The correct reset key alternates between 55h and AAh, beginning with 55h following a system reset. Writes of the correct value must occur before the timer overflow period, or the WD generates a reset. A write to the WD reset key of any value other than the correct predefined value is interpreted as a lost program, and a system reset is initiated. A WD-counter overflow or incorrect reset key sets the WD OVRFL INT FLAG bit (T1CTL2.5) to 1. After a reset, the program can read this flag to determine the source of the reset. WD resets are not prevented when the flag is set. Note: A hard WD is disabled in low-power mode (see Section 7.8 on page 7-29).
7.7.2.1
INT1 Operation During an Inadvertent Low-Power Mode
When the hard WD mask option is selected, INT1 is enabled as a non-maskable interrupt (NMI) during low-power modes. This NMI is generated regardless of the interrupt enable flags and the values of the following status bits: INT1 PRIORITY bit (INT1.1), INT1 ENABLE bit (INT1.0), INT1 NMI bit (SCCR2.1), and the global interrupt enable flags in the status register (IE1 and IE2). INT1 is configured as an NMI in the hard WD to provide a method of exiting a low-power mode. Normally, when the halt or standby mode is entered, the WD counter clock source is disabled, which disables the ability of the WD counter to generate a reset. Note that an active edge on the NMI INT1 pin brings the device out of the low-power mode, and the WD counter is activated. Additionally, if the halt or standby mode is entered while INT1 pin is active (low if the INT1 POLARITY bit is cleared to 0 or high if the INT1 POLARITY bit is set to 1), an NMI is generated immediately.
7-26
WD Timer
7.7.3
Simple Counter Configuration
In the simple counter configuration, the WD timer can be used as an event counter, a pulse accumulator, or an interval timer (similar to the non-WD mode in the standard WD configuration). However, in this configuration, the system reset function of the WD timer is disabled. Figure 7-9 is a block diagram of a simple counter.
Figure 7-9. Simple Counter Block Diagram
WDCNTR.15-0
16-bit WD counter WD OVFL INT FLAG
T1CTL2.6
Interrupt WD OVRFL INT ENA
T1CTL2.5
Reset Clock prescaler
T1CTL1.7 WD OVRFL TAP SEL
WD reset key
WDRST.7-0
To reinitialize the WD counter, write any value to the WD reset key (WDRST). The timer overflow rates are determined by the system clock frequency, the WD INPUT SELECT0-2 bits (T1CTL1.4-6), and the value of the WD OVRFL TAP SEL bit (T1CTL1.7). If the WD OVRFL RST ENA bit is set to 1, subsequent writes to WD INPUT SELECTs and WD OVRFL TAP SEL bits are ignored. Once the WD OVRFL RST ENA bit is set, these control bits can be changed only after a powerup reset.
Timer 1 (T1) Module
7-27
WD Timer
7.7.4
Summary of WD Options
Table 7-6 summarizes the features of each watchdog option and specifies the options available to ROMless, mask-ROM, and EPROM devices.
Table 7-6. WD Option Summary
Standard WD Option WD OVRFL TAP SEL bit and WD INPUT SELECT0-2 bits WD Once the WD OVRFL RST ENA is set, the values of these bits can be changed only after a system reset. Non-WD These bits can be changed at any time, as long as WD OVRFL RST ENA is not set. Hard WD The values of these WD bits can be changed at any time, even if WD OVRFL RST ENA bit is set. However, the WD INPUT SELECT2 bit is not available. Simple Counter Once the WD OVRFL RST ENA is set, the values of these bits can be changed only after a system reset.
Generates an interrupt when the WD counter overflows? Generates a system reset? WD OVRFL RST ENA bit
No
Yes
No
Yes
Yes Select to be a WD. If bit=1, WD counter does initiate a reset upon overflow. This bit is cleared by any system reset.
No Select to be a nonWD. If bit = 0, WD counter does not initiate reset upon overflow.
Yes This bit is ignored.
No If bit=0, WD bits and WD OVRFL TAP SELECT are not locked. If bit=1, WD bits and WD OVRFL TAP SELECT are locked.
INT1 during low-pow- Controlled by INT1 er modes ENABLE bit (INT1.0) and INT1 NMI bit (SCCR2.1). Available Devices All devices
Controlled by INT1 ENABLE bit (INT1.0) and INT1 NMI bit (SCCR2.1). All devices
Enabled as an NMI.
Controlled by INT1 ENABLE bit (INT1.0) and INT1 NMI bit (SCCR2.1). Mask-ROM devices
Mask-ROM and EPROM devices
7-28
Low-Power Modes
7.8
Low-Power Modes
The T1 module supports low-power (powerdown) modes that aid in reducing power consumption during periods of inactivity. These modes are the halt and the standby modes. For more information on low-power modes, see Section 4.2, page 4-7.
7.8.1
Halt Mode
The halt mode is entered when the CPU executes an IDLE instruction while the HALT/STANDBY bit (SCCR2.7) and the PWRDWN/IDLE bit (SCCR2.6) are set (the SCCR2 register is described in detail in subsection 4.3.3, page 4-16). During the halt mode, all T1 module functions (including the WD timer) hold the prehalt status of all other storage elements. The module holds the state of each external pin constant, regardless of whether the pins are used as timer pins or as dedicated I/O pins. That is, inputs remain inputs, output low levels remain low, and output high levels remain high.
7.8.2
Standby Mode
You can put the timer in standby mode by executing an IDLE instruction when the PWRDWN/IDLE (SCCR2.6) bit is set and the HALT/STANDBY bit (SCCR2.7) is cleared. During the standby mode, the WD counter clock input is halted while the rest of the T1 module remains fully functional.
Timer 1 (T1) Module
7-29
T1 Control Registers
7.9
T1 Control Registers
Seven registers control the configuration of T1 global functions, prescale values, WD timing, optional uses for the associated I/O pins, and other counter functions (refer to Figure 7-10). The bits that are shown in shaded boxes are privilege mode bits; that is, they can be written to only in the privilege mode. Note: 16-bit Register Read/Write Protocol
Special circuitry prevents 16-bit registers from changing in the middle of a 16-bit read or write operation. When you read a 16-bit register, read the least significant byte (LSbyte) first to lock in the value, and then read the most significant byte (MSbyte). When you write to a 16-bit register, write the MSbyte first and then write the LSbyte. The register value does not change between reading and writing the bytes when they are done in this order. While you are reading or writing to a 16-bit register, do not read or write from a second 16-bit register within this module until the process is complete with the first register. Otherwise, the correct value for the first register's MSbyte will not be correct. The 16-bit read/write operation actually occurs when you access the LSbyte. In summary, the order of read/write operations is as follows: Read: Write: LSbyte then MSbyte MSbyte then LSbyte
7-30
T1 Control Registers
Figure 7-10. Peripheral File Frame 4: T1 Control Registers
Designation T1CNTR T1CNTR T1C T1C T1CC T1CC WDCNTR WDCNTR WDRST T1CTL1 ADDR 1040h 1041h 1042h 1043h 1044h 1045h 1046h 1047h 1048h 1049h PF P040 P041 P042 P043 P044 P045 P046 P047 P048 P049
Bit 7
Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 7 WD OVRFL TAP SEL (RP-0) WD OVRFL RST ENA (RS-0)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 0
T1 Counter MSbyte T1 Counter LSbyte Compare Register MSbyte Compare Register LSbyte Capture/Compare Register MSbyte Capture/Compare Register LSbyte WD Counter MSbyte WD Counter LSbyte WD Reset Key WD INPUT SELECT2 (RP-0) WD INPUT SELECT1 (RP-0) WD INPUT SELECT0 (RP-0) T1 OVRFL INT ENA (RW-0) T1 INPUT SELECT2 (RW-0) T1 INPUT SELECT1 (RW-0)
T1CTL2
104Ah
P04A
T1CTL3
104Bh
P04B
T1CTL4
104Ch
P04C
T1PC1
104Dh
P04D -- -- T1PWM DATA OUT (RW-0) T1 PRIORITY (RP-0) -- T1PWM FUNCTION (RW-0) -- -- T1PWM DATA DIR (RW-0) --
T1PC2
104Eh
P04E
T1PRI
104Fh
P04F
IIII IIIIIIIIIIII I I IIII I IIIIIIIIIIII I I IIII III I IIIIIIIIIIII
WD OVRFL INT ENA (RW-0) WD OVRFL INT FLAG (RC-*) T1EDGE INT FLAG (RC-0) T1C2 INT FLAG (RC-0) T1C1 INT FLAG (RC-0) -- T1EDGE INT FLAG (RC-0) -- T1C1 INT FLAG (RC-0) -- T1 MODE = 0 (RW-0) T1C1 OUT ENA (RW-0) T1C2 OUT ENA (RW-0) T1C1 RST ENA (RW-0) T1 MODE = 1 (RW-0) T1C1 OUT ENA (RW-0) -- T1C1 RST ENA (RW-0) T1PWM DATA IN (R-0) T1 STEST (RP-0)
--
T1 INPUT SELECT0 (RW-0) T1 SW RESET (S-0)
T1 OVRFL INT FLAG (RC-0)
--
--
Dual Compare Mode T1EDGE INT ENA (RW-0) T1C2 INT ENA (RW-0) T1C1 INT ENA (RW-0)
--
Capture / Compare Mode T1EDGE INT ENA (RW-0) T1C1 INT ENA (RW-0)
--
--
Dual Compare Mode T1CR OUT ENA (RW-0) T1EDGE POLARITY (RW-0) T1CR RST ENA (RW-0) T1EDGE DET ENA (RW-0)
Capture / Compare Mode -- T1EDGE POLARITY (RW-0) -- T1EDGE DET ENA (RW-0)
T1EVT DATA IN (R-0) T1IC/CR DATA IN (R-0) --
T1EVT DATA OUT (RW-0) T1IC/CR DATA OUT (RW-0) --
T1EVT FUNCTION (RW-0) T1IC/CR FUNCTION (RW-0) --
T1EVT DATA DIR (RW-0) T1IC/CR DATA DIR (RW-0) --
Once the WD OVRFL RST ENA bit is set, these bits cannot be changed until a reset occurs; this applies only to the standard WD and to the simple counter. In the hard WD, these bits can be modified at any time; the WD INPUT SELECT2 bit is ignored.
Timer 1 (T1) Module
7-31
T1 Control Registers
7.9.1
T1 Control Register 1 (T1CTL1)
The T1CTL1 register controls the prescaler inputs to the WD timer and the general-purpose timer.
T1 Control Register 1 (T1CTL1) [Memory Address 1049h]
Bit #
P049
7
WD OVRFL TAP SEL RP-0
6
WD INPUT SELECT2 RP-0
5
WD INPUT SELECT1 RP-0
4
WD INPUT SELECT0 RP-0
3
--
2
T1 INPUT SELECT2 RW-0
1
T1 INPUT SELECT1 RW-0
0
T1 INPUT SELECT0 RW-0
R = Read, W = Write, P = Write protected when WD OVRFL RST ENA=1 (only in standard WD and simple counter configurations), -n = Value of the bit after the register is reset
Bit 7
WD OVRFL TAP SEL. WD Overflow Tap Select This bit determines whether the WD counter operates as a 15-bit or a 16-bit counter in the standard WD, hard WD, and simple counter options. The default is the full 16 bits of the counter. If a shorter WD counter overflow rate is needed, then the most significant bit of the counter can be forced to remain at 1. This, in effect, changes the WD counter to a 15-bit counter with an overflow period half that of a 16-bit counter. This tap select feature, combined with the clock prescaler, allows WD overflow rates from 215 to 224 system clock cycles. Once the WD RST ENA bit is set, this bit can be changed only after a reset (for the non-WD mode of the standard WD and simple counter). In the hard WD, this bit can be changed at any time. 0 = 16-bit WD counter overflow 1 = 15-bit WD counter overflow
Bits 6-4
WD INPUT SELECT2-0. WD Input Select 2-0
Standard WD and simple counter: These three bits select one of eight possible clock sources. Once the WD OVRFL RST ENA bit is set, the values of these three bits can be changed only after a reset; a write to this bit has no effect when the WD OVRFL RST ENA bit is set. Hard WD: The WD INPUT SELECT0 and WD INPUT SELECT1 bits are used to select one of the four possible clock sources. The clock sources come from one of the four taps from the 8-bit prescaler, which provides the system clock divided by 4, 16, 64, or 256. Note that the WD INPUT SELECT2 bit is functionally interpreted as 1. The combinations are shown in Table 7-7.
7-32
T1 Control Registers
Table 7-7. Counter Clock Sources for the WD Input Select 0-2
WD INPUT SELECT2 0 0 0 0 1 1 1 1 WD INPUT SELECT1 0 0 1 1 0 0 1 1 WD INPUT SELECT0 0 1 0 1 0 1 0 1 Counter Clock Source System clock Pulse accumulation Event input No clock input System clock/4 System clock/16 System clock/64 System clock/256
These options are not available for the hard WD
Bit 3 Bit 2-0
Reserved. Read data is indeterminate T1 INPUT SELECT2-0. T1 Input Select 2-0 These three bits select one of eight possible clock sources for the T1 generalpurpose counter. These sources are as follows:
-
The system clock with no prescale (system clock) The system clock when the external input T1EVT is high (pulse accumulation) An external source synchronized with the system clock (event input) No system clock source (no clock input) One of four taps from the 8-bit prescaler, which provides the system clock divided by 4, 16, 64, or 256
The combinations are shown in Table 7-8:
Table 7-8. Clock Sources for the T1 General Purpose Counter
T1 INPUT SELECT2 0 0 0 0 1 1 1 1 T1 INPUT SELECT1 0 0 1 1 0 0 1 1 T1 INPUT SELECT0 0 1 0 1 0 1 0 1 Counter Clock Source System clock Pulse accumulation Event input No clock input System clock/4 System clock/16 System clock/64 System clock/256
Timer 1 (T1) Module
7-33
T1 Control Registers
7.9.2
T1 Control Register 2 (T1CTL2)
The T1CTL2 register controls the T1 and WD overflow interrupts and contains the T1 software reset bit.
T1 Control Register 2 (T1CTL2) [Memory Address 104Ah]
Bit #
P04A
7
WD OVRFL RST ENA RS-0
6
WD OVRFL INT ENA RW-0
5
WD OVRFL INT FLAG RC-*
4
T1 OVRFL INT ENA RW-0
3
T1 OVRFL INT FLAG RC-0
2
--
1
--
0
T1 SW RESET S-0
R = Read, S = Set only, W = Write, C = Clear only, -n = Value of the bit after the register is reset, -* = see bit description
Bit 7
WD OVRFL RST ENA. WD Overflow Reset Enable Note: This bit operates differently for TMS370Cxxx devices than TMS370CxxxA and TMS370C7xxB devices. Refer to Section A.4, page A-5.
Standard WD: This bit controls the ability of a WD timer to generate a reset. The WD timer is a simple counter pulse accumulator when cleared. Once set, this bit can be cleared only by any system reset and locks the values of other WD bits so that they can be changed only after a reset.
0 = WD counter does not initiate a reset upon overflow. 1 = WD counter does initiate a reset upon overflow.
Simple counter: This bit protects the WD INPUT SELECT and WD OVRFL TAP SEL bits. Once set, subsequent writes to these control bits are ignored; they can be changed only after reset.
0 = Other WD bits are not protected 1 = Locks the value of other WD bits
Hard WD: This bit is ignored.
Bit 6 WD OVRFL INT ENA. Watchdog Overflow Interrupt Enable This bit controls the WD overflow interrupting capability. 0 = Disables WD interrupt 1 = Enables WD interrupt
7-34
T1 Control Registers
Bit 5
WD OVRFL INT FLAG. Watchdog Overflow Interrupt Flag Note: This bit operates differently for TMS370Cxxx devices than TMS370CxxxA and TMS370CxxB devices. Refer to Section A.4, page A-5. This bit is set if the last reset is initiated by the WD counter. Setting this bit will not prevent WD resets. This bit is cleared by writing a zero to it or by any system reset that is not initiated by the WD counter. 0 = WD interrupt is inactive. 1 = WD counter has overflowed or the incorrect value is written to the WD reset key register.
Bit 4
T1 OVRFL INT ENA. T1 Overflow Interrupt Enable. This bit controls the T1 overflow interrupting capability. 0 = Disables interrupt 1 = Enables interrupt
Bit 3
T1 OVRFL INT FLAG. T1 Overflow Interrupt Flag This bit indicates the status of the T1 overflow interrupt. 0 = General-purpose overflow interrupt is inactive. 1 = General-purpose overflow interrupt is pending.
Bits 2-1 Bit 0
Reserved. Read values are indeterminate. T1 SW RESET. T1 Software Reset This bit is always read as a 0; however, when a 1 is written to this bit, the counter resets to 0000h on the next system clock cycle. Note: Be careful using the AND, OR, XOR, CMPBIT, SBIT0, or SBIT1 instructions to modify this register. The read/modify/write nature of these instructions can inadvertently clear an interrupt flag that was set between the read and the write cycles. If the state of the interrupt enable bits is known, the MOV #iop8, Pd instruction can be used. If the state of the interrupt enable bits is not known, a sequence similar to the example shown below should be used.
;clearing the T1 OVRFL INT FLAG: MOV P04A,A OR #028H,A AND #0F7H,A MOV A,P04A
Timer 1 (T1) Module
7-35
T1 Control Registers
7.9.3
T1 Control Register 3 (T1CTL3)
The T1CTL3 register controls the edge-detect and compare interrupts. The six active bits in this register serve different functions for each mode, as shown below:
T1 Control Register 3 (T1CTL3) [Memory Address 104Bh] Mode: Dual Compare
Bit #
P04B
7
T1EDGE INT FLAG RC-0
6
T1C2 INT FLAG RC-0
5
T1C1 INT FLAG RC-0
4
--
3
--
2
T1EDGE INT ENA RW-0
1
T1C2 INT ENA RW-0
0
T1C1 INT ENA RW-0
Mode: Compare/Capture
Bit #
P04B
7
T1EDGE INT FLAG RC-0
6
--
5
T1C1 INT FLAG RC-0
4
--
3
--
2
T1EDGE INT ENA RW-0
1
--
0
T1C1 INT ENA RW-0
R = Read, W = Write, C = Clear only, -n = Value of the bit after the register is reset
Bit 7
T1EDGE INT FLAG. T1 Edge Interrupt Flag This bit indicates when an external pulse transition of the correct polarity is detected on the T1 input capture/counter reset (T1IC/CR) pin. This bit also indicates an input capture in the capture/compare mode. 0 = No transition 1 = Transition detected
Bit 6
T1C2 INT FLAG. T1 Compare 2 Interrupt Flag
Dual compare mode: This bit is set when the capture/compare register first matches the counter value.
0 = Interrupt inactive 1 = Interrupt pending
Capture/compare mode: Reserved. Read data is indeterminate.
Bit 5 T1C1 INT FLAG. T1 Compare 1 Interrupt Flag This bit is set when the compare register first matches the counter value. 0 = Interrupt inactive 1 = Interrupt pending Bit 4-3
7-36
Reserved. Read data is indeterminate.
T1 Control Registers
Bit 2
T1EDGE INT ENA. T1 Edge Interrupt Enable This bit determines whether or not the active edge input to the T1IC/CR pin generates an interrupt. The T1EDGE DET ENA bit (T1CTL4.0) must be set before an edge can be detected. 0 = Disables interrupt 1 = Enables interrupt
Bit 1
T1C2 INT ENA. T1 Compare 2 Interrupt Enable
Dual compare mode only: This bit determines whether or not the capture/ compare register flag can generate an interrupt.
0 = Disables interrupt 1 = Enables interrupt
Capture/compare mode: Reserved. Read data is indeterminate.
Bit 0 T1C1 INT ENA. T1 Compare 1 Interrupt Enable This bit determines whether or not the compare register flag can generate an interrupt. 0 = Disables interrupt 1 = Enables interrupt Note: Be careful using the AND, OR, XOR, CMPBIT, SBIT0, or SBIT1 instructions to modify this register. The read/modify/write nature of these instructions can inadvertently clear an interrupt flag that was set between the read and the write cycles. If the state of the interrupt enable bits is known, the MOV #iop8, Pd, instruction can be used. If the state of the interrupt enable bits is not known, a sequence similar to the example shown below should be used.
;Clearing the T1C1 INT FLAG MOV P04B,A OR #0E0h,A AND #0DFh,A MOV A,P04B
Timer 1 (T1) Module
7-37
T1 Control Registers
7.9.4
T1 Control Register 4 (T1CTL4)
The T1CTL4 register controls the mode of operation and various functions of the T1 input and output pins. The bits in this register serve different functions, depending on the mode.
T1 Control Register 4 (T1CTL4) [Memory Address 104Ch] Mode: Dual Compare
Bit #
P04C
7
T1 MODE=0 RW-0
6
T1C1 OUT ENA RW-0
5
T1C2 OUT ENA RW-0
4
T1C1 RST ENA RW-0
3
T1CR OUT ENA RW-0
2
T1EDGE POLARITY RW-0
1
T1CR RST ENA RW-0
0
T1EDGE DET ENA RW-0
Mode: Compare/Capture
Bit #
P04C
7
T1 MODE=1 RW-0
6
T1C1 OUT ENA RW-0
5
--
4
T1C1 RST ENA RW-0
3
--
2
T1EDGE POLARITY RW-0
1
--
0
T1EDGE DET ENA RW-0
R = Read, W = Write, -n = Value of the bit after the register is reset
Bit 7
T1 MODE. T1 Mode Select This bit selects the general-purpose counter mode. 0 = Dual compare mode 1 = Capture/compare mode
Bit 6
T1C1 OUT ENA. T1 Output-Compare Output Enable 1 When this bit is set and the compare register 1 is equal to the counter, the T1PWM pin toggles (when configured as a PWM pin). 0 = Disables pulse-to-toggle output 1 = Enables pulse-to-toggle output
Bit 5
T1C2 OUT ENA. T1 Output-Compare Output Enable 2
Dual Compare Mode: When this bit is set and compare register 2 is equal to the counter, the T1PWM pin toggles (when configured as a PWM pin).
0 = Disables pulse-to-toggle output 1 = Enables pulse-to-toggle output
Capture/compare mode: Reserved. Read data is indeterminate.
7-38
T1 Control Registers
Bit 4
T1C1 RST ENA. T1 Compare 1 Reset Enable When this bit is set and compare register 1 is equal to the counter, the counter will reset on the next counter increment. 0 = Disables counter reset upon compare equal 1 = Enables counter reset upon compare equal
Bit 3
T1CR OUT ENA. T1 External Edge Output Enable
Dual compare mode: This bit determines whether the input signal on the T1IC/CR pin can toggle the output signal on the T1PWM pin.
0 = Disables pulse-to-toggle output 1 = Enables pulse-to-toggle output
Capture/compare mode: Reserved. Read data is indeterminate.
Bit 2 T1EDGE POLARITY. T1 Edge Polarity This bit determines the transition direction on the T1IC/CR pin to trigger a capture or counter reset, depending on the counter mode selected. 0 = Triggers on a high-to-low transition 1 = Triggers on a low-to-high transition Bit 1 T1CR RST ENA. T1 External Reset Enable
Dual compare mode: This bit determines whether an external signal can reset the counter.
0 = Disables external reset of the counter 1 = Enables external reset of the counter on the next valid edge detect
Capture/compare mode: Reserved. Read data is indeterminate.
Bit 0 T1EDGE DET ENA. T1 Edge Detect Enable
Dual compare mode: This bit enables the edge detection circuit to sense the next level transition on the T1IC/CR pin. This bit is cleared after the selected transition is detected and during a reset.
0 = Disables edge detection 1 = Enables edge detection
Capture/compare mode: This bit enables the input capture circuit to capture the current counter value upon the next level transition on the counter reset/input capture pin, as determined by the T1EDGE POLARITY bit. This bit remains unchanged after the selected transition is detected.
0 = Disables input capture 1 = Enables input capture
Timer 1 (T1) Module
7-39
T1 Control Registers
7.9.5
T1 Port Control Registers (T1PC1 and T1PC2)
Port control registers (PCRs) T1PC1 and T1PC2 are organized to allow all functions for a pin to be programmed in one write cycle. Each module pin is controlled by a nibble in one of the PCRs.
7.9.5.1
T1 Port Control Register 1 (T1PC1)
The T1PC1 register controls the I/O functions of the T1 module, T1EVT pin.
T1 Port Control Register 1 (T1PC1) [Memory Address 104Dh]
Bit #
P04D
7
--
6
--
5
--
4
--
3
T1EVT DATA IN R-0
2
T1EVT DATA OUT RW-0
1
T1EVT FUNCTION RW-0
0
T1EVT DATA DIR RW-0
R = Read, W = Write, -n = Value of the bit after the register is reset
Bits 7-4 Bit 3
Reserved. Read data is indeterminate. T1EVT DATA IN. T1EVT Pin Data In This bit contains the data present on the T1EVT pin. A write operation to this bit has no effect.
Bit 2
T1EVT DATA OUT. T1EVT Pin Data Out This bit contains the data to be output on the T1EVT pin if the following conditions are met: a. Bit TIEVT DATA DIR = 1 b. Bit T1EVT FUNCTION = 0
Bit 1
T1EVT FUNCTION. T1EVT Pin Function Select This bit determines the function of the T1EVT pin. 0 = The T1EVT is a general-purpose digital I/O pin. 1 = The T1EVT is the event-input pin.
Bit 0
T1EVT DATA DIR. T1 Event-Pin Data Direction This bit selects the T1EVT pin as an input or output if the T1EVT FUNCTION bit = 0. 0 = Enables T1EVT pin as data input 1 = Enables T1EVT pin as data output
7-40
T1 Control Registers
7.9.5.2
T1 Port Control Register 2 (T1PC2)
The T1PC2 register controls the I/O functions of the T1IC/CR and T1PWM pins.
T1 Port Control Register 2 (T1PC2) [Memory Address 104Eh]
Bit #
P04E
7
T1PWM DATA IN R-0
6
T1PWM DATA OUT RW-0
5
T1PWM FUNCTION RW-0
4
T1PWM DATA DIR RW-0
3
T1IC/CR DATA IN R-0
2
T1IC/CR DATA OUT RW-0
1
T1IC/CR FUNCTION RW-0
0
T1IC/CR DATA DIR RW-0
R = Read, W = Write, -n = Value of the bit after the register is reset
Bit 7
T1PWM DATA IN. T1PWM Pin Data In 1 This bit contains the data input on pin T1PWM. A write operation to this bit has no effect.
Bit 6
T1PWM DATA OUT. T1PWM Pin Data Out This bit contains the data to be output on the T1PWM pin if the following conditions are met: a. Bit T1PWM DATA DIR = 1 b. Bit T1PWM FUNCTION = 0
Bit 5
T1PWM FUNCTION. T1PWM Pin Function Select This bit determines the function of the T1PWM pin. 0 = The T1PWM pin is a general-purpose digital I/O pin. 1 = The T1PWM pin is the PWM output.
Bit 4
T1PWM DATA DIR. T1PWM Pin Data Direction This bit selects the T1PWM pin as an input or output if the T1PWM FUNCTION bit = 0. 0 = Enables T1PWM pin data input 1 = Enables T1PWM pin data output
Bit 3
T1IC/CR DATA IN. T1IC/CR Pin Data In This pin contains the data input on pin T1IC/CR. A write operation to this bit has no effect.
Timer 1 (T1) Module
7-41
T1 Control Registers
Bit 2
T1IC/CR DATA OUT. T1IC/CR Pin Data Out This bit contains the data output on pin T1IC/CR if the following conditions are met: a. Bit T1IC/CR DATA DIR = 1 b. Bit T1IC/CR FUNCTION = 0
Bit 1
T1IC/CR FUNCTION. T1IC/CR Pin Function Select This bit determines the function of the T1IC/CR pin. 0 = The T1IC/CR pin is a general-purpose digital I/O pin. 1 = The T1IC/CR pin is the input capture/counter reset pin.
Bit 0
T1IC/CR DATA DIR. T1IC/CR Pin Data Direction This bit selects the T1IC/CR pin as an input or output if the T1IC/CR FUNCTION bit = 0. 0 = Enables T1IC/CR pin data input 1 = Enables T1IC/CR pin data output
7-42
Timer 1 Control Registers
7.9.6
T1 Interrupt Priority Control Register (T1PRI)
The T1PRI register controls the level of the T1 interrupt. You can write to this register only in the privilege mode. During normal operation, this is a read-only register.
T1 Interrupt Priority Control Register (T1PRI) [Memory Address 104Fh]
Bit #
P04F
7
T1 STEST RP-0
6
T1 PRIORITY RP-0
5
--
4
--
3
--
2
--
1
--
0
--
R = Read, P = Privilege write only, -n = Value of the bit after register is reset
Bit 7
T1 STEST. T1 STEST This bit must be cleared (0) to ensure proper operation.
Bit 6
T1 PRIORITY. T1 Interrupt Priority Select This bit determines the level of the interrupt generated by T1. 0 = Interrupts are level 1 (high priority) requests. 1 = Interrupts are level 2 (low priority) requests.
Bits 5-0
Reserved. Read data is indeterminate.
Timer 1 (T1) Module
7-43
7-44
Running Title--Attribute Reference
Chapter 8
Timer 2A (T2A) and Timer 2B (T2B) Modules
This chapter discusses the architecture and programming of the T2A and T2B modules and covers the following topics:
Topic
8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8
Page
T2n Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 T2n Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10 Edge-Detection Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-13 Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-14 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-16 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-17 T2n Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-17
Chapter Title--Attribute Reference
8-1
T2n Overview
8.1 T2n Overview
The T2n module (T2A or T2B) is a 16-bit general-purpose timer. Depending on the TMS370 device, there may be 0, 1, or 2 on-chip T2 modules. For devices with one T2 module, the timer is referred to as T2A. Devices ('x6x) with two T2 modules are referred to as T2A and T2B. The term T2n is used to refer to the T2A or T2B timer modules throughout this chapter. The T2n module is composed of a 16-bit resettable counter, a 16-bit compare register with associated compare logic, a 16-bit capture register, and a 16-bit register that functions as a capture register in one mode and as a compare register in the other mode. The T2n module adds an additional timer that provides event count, input capture, and compare functions. The T2n solutions to different system requirements are shown in Table 8-1.
Table 8-1. System-Requirement Solutions Using T2n
Requirement Realtime system control Input pulse-width measurement External event synchronization Timer output control PWM output control Timer Solution Interval timers with interrupts Pulse accumulate or input capture functions Event count function Compare function PWM output function
8.1.1
Physical Description
The T2n module has the following features. The T2n module is shown in Figure 8-1 on page 8-3:
-
A 16-bit resettable counter A 16-bit compare register with associated compare logic A 16-bit capture register A 16-bit capture/compare register Selectable edge-detection circuitry Interrupts The T2n module has maskable interrupts for the following:
J J J J
8-2
Two input captures Two output compares Counter overflow External edge detect
T2n Overview
-
I/O Pins The T2n module has three I/O pins that can be dedicated as timer functions or used as general-purpose I/O pins. The following list describes each I/O pin:
J J J
T2nEVT, which provides for input to the event counter or the external clock source T2nIC1/CR, which provides for input to the counter reset, input capture, or pulse-width modulation (PWM) circuit T2nIC2/PWM, which provides for PWM output or a second input capture
The definitions of these pins are contained in the two port control registers located at addresses P06E and P06D of peripheral file frame 6 for T2A, and P08E and P08D of peripheral file frame 8 for T2B. Table 8-2 on page 8-4 defines the functions of the three T2n I/O pins for both operating modes.
Figure 8-1. T2n Block Diagram
External pin connections
T2nIC1 / CR
Edge detect Edge detect 16-bit capt/comp register
T2nIC2 / PWM (Dual-capture mode)
External pin connection
16-bit capture register
INT logic
PWM toggle
T2nIC2/PWM (Dual-compare mode)
16
T2nEVT
Clock select
16-bit counter
16-bit compare register
Timer 2A (T2A) and Timer 2B (T2B) Modules
8-3
T2n Overview
Table 8-2. T2n I/O Pin Definitions
Pin T2nIC1/CR T2nIC2/PWM T2nEVT Dual Compare Mode Counter reset input PWM output External event input or pulse accumulate input Dual Capture Mode Input capture 1 input Input capture 2 input External event input or pulse accumulate input
8.1.2
Operating Modes
-
Dual compare mode. The timer is configured to provide dual compare registers, an external or software reset of the counter, an internal or external clock source, and a programmable PWM output. The T2nIC2/PWM pin can also be configured to toggle upon an external input edge. The external clock source can be selected for use as an event counter or pulse accumulator. Dual capture mode. The timer is configured to provide dual input capture registers and one compare register for use as a general-purpose timer. The compare register can provide periodic interrupts to the rest of the microcomputer. Each capture register can be configured to capture the current counter value upon either edge of an external input.
-
8.1.3
Control Registers
The T2A control registers are located at addresses 1060h to 106Fh, with locations 1068h and 1069h reserved; T2B control registers are located at 1080h to 108Fh, with locations 1088h and 1089h reserved. The functions of these locations are shown in Table 8-3 on page 8-5.
8-4
T2n Overview
Table 8-3. T2n Memory Map
Peripheral File 6 Location T2A P060 P061 P062 P063 P064 P065 P066 P067 P068 P069 P06A Peripheral File 8 Location T2B P080 P081 P082 P083 P084 P085 P086 P087 P088 P089 P08A T2nCTL1 T2nIC T2nCC T2nC
Symbol T2nCNTR
Name T2n Counter -- MSbyte T2n Counter -- LSbyte Compare Register -- MSbyte Compare Register -- LSbyte Capture/Compare Register -- MSbyte Capture/Compare Register -- LSbyte Capture Register -- MSbyte Capture Register -- LSbyte Reserved Reserved T2n Control Register 1
Description 16-bit resettable counter
16-bit compare register
16-bit capture/compare register
16-bit capture register
Controls the clock input selection, counter overflow interrupts, and counter software reset. Contains interrupt flags and controls the module's capability to issue interrupts. Controls the mode of operation, outputs, active transition polarity, and counter reset. Assigns the I/O function of the T2nEVT pin as either a general-purpose digital I/O or external event input of the module. Assigns the I/O functions of the T2nIC1/CR and T2nIC2/PWM pins as either general-purpose digital I/O pins or the input capture/counter reset and PWM output pins, respectively. Assigns the priority level of interrupts generated by the T2n module.
P06B
P08B
T2nCTL2
T2n Control Register 2
P06C
P08C
T2nCTL3
T2n Control Register 3
P06D
P08D
T2nPC1
T2n Port Control Register 1
P06E
P08E
T2nPC2
T2n Port Control Register 2
P06F
P08F
T2nPRI
T2n Interrupt Priority Control Register
Timer 2A (T2A) and Timer 2B (T2B) Modules
8-5
T2n Components
8.2 T2n Components
The T2n module uses a 16-bit counter, a compare register, a capture register, and a capture/compare register to provide event, compare, and capture functions.
8.2.1
16-Bit Resettable Counter
The 16-bit free-running, read-only counter (T2nCNTR) is clocked by the system clock, the external event, or the system clock during the occurrence of an active external event (pulse accumulate).
-
During initialization, the counter is loaded with 0000h and begins its count. If the counter is not reset before reaching FFFFh, the counter rolls over to 0000h and continues counting. When the counter rolls over, the T2n OVRFL INT FLAG bit (T2nCTL1.3) is set; a timer interrupt is generated if the T2n OVRFL INT ENA bit (T2nCTL1.4) is set. The counter can be reset to 0000h during counting by any of the following:
J J J J
A 1 written to the T2n SW RESET bit (T2CTL1.0) A compare equal condition from the dedicated T2n compare function System reset An external pulse on the T2nIC1/CR pin (dual compare mode only) if the T2nC1 RST ENA bit (T2nCTL3.4) is set.
To reset the counter, you can select the external transition on the T2nIC1/CR pin to be either low-to-high or high-to-low. To do this, use the T2nEDGE1 POLARITY bit (T2nCTL3.2). Special circuitry prevents the contents of the T2nCNTR register from changing in the middle of a 16-bit read operation. See the note in Section 8.8 on page 8-17.
8.2.2
Compare Register
The compare register circuit consists of a 16-bit wide, read/write data register (T2nC) and logic to compare the counter's current value with the value stored in the compare register. When the counter value matches the compare register value, the circuit performs the following:
8-6
Sets the T2nC1 INT FLAG bit (T2CTL2.5) to 1. Generates a T2n interrupt if the T2nC1 INT ENA bit (T2nCTL2.0) is set. Resets the counter if the T2nC1 RST ENA bit (T2nCTL3.4) is set. Toggles the PWM output pin if the T2nC1 OUT ENA bit (T2nCTL3.6) is set (dual compare mode only).
T2n Components
Once the T2nC1 INT FLAG bit is set by a compare-equal condition and then cleared, it will not be set again if the same compare-equal condition still exists (that is, the same compare-equal condition can set the T2nC1 INT FLAG bit only once). This flag causes various events to occur, depending on the mode of operation and on which enable bits are set. Special circuitry prevents the T2nC register from changing in the middle of a 16-bit read or write operation. See the note in Section 8.8. The compare register value required for a specific timing application can be calculated using the following formula:
Compare Value =
t 1 SYSCLK
-1
where: t= SYSCLK = desired timer compare period (seconds) CLKIN/4 for divide-by-4 clock (external clock frequency) CLKIN/1 for divide-by-1 clock
Table 8-4 provides some sample compare register values to achieve various desired timings with a 5-MHz SYSCLK.
Table 8-4. T2n Compare Values: (5-MHz SYSCLK)
Time Seconds 0.0005 0.001 0.002 0.005 0.010 0.013 m Seconds 0.5 1 2 5 10 13 T2n Compare Register Decimal 2499 4999 9999 24999 49999 64999 Hex 009C3h 01387h 0270Fh 061A7h 0C34Fh 0FDE7h % Error (See Note) 0.0000 0.0000 0.0000 0.0000 0.0000 0.0000
Note: The percent of error induced by the T2n formula varies, depending on the desired timer compare period and the minimum timer resolution (1/SYSCLK).
8.2.3
Capture Register (Dual Capture Mode Only)
The 16-bit capture register (T2nIC) is a read-only data register. This register captures the counter values when an input capture pulse (pin T2nIC2/PWM) is received. The capture register can be read at the addresses shown in Table 8-5. Writes to this register are ignored, so the capture register retains
Timer 2A (T2A) and Timer 2B (T2B) Modules
8-7
T2n Components
the last counter value captured until another input capture pulse loads a new value in the register.
Table 8-5. T2n Capture Register MSbyte and LSbyte Addresses
Timer T2AIC T2BIC MSbyte P066 P086 LSbyte P067 P087
On receipt of a capture pulse, the circuit conducts the following:
-
Loads the value of the 16-bit counter into the capture register. Sets the T2nEDGE2 INT FLAG bit (T2nCTL2.6) to indicate that the capture register has latched the current counter value. If the T2nC2 INT ENA bit (T2nCTL2.1) is set, generates an interrupt.
Special circuitry prevents the T2nIC register from changing in the middle of a 16-bit read or write operation. See the note in Section 8.8 on page 8-17.
8.2.4
Capture/Compare Register
The 16-bit capture/compare register (T2nCC) can serve one of two functions, depending on the operating mode. Table 8-6 shows the T2nCC locations.
Table 8-6. T2n Capture/Compare Register MSbyte and LSbyte Addresses
Timer T2ACC T2BCC MSbyte P064 P084 LSbyte P065 P085
Special circuitry prevents the T2nCC register from changing in the middle of a 16-bit read or write operation. See the note in Section 8.8 on page 8-17.
8.2.4.1
Dual Compare Mode
In the dual compare mode, the T2nCC register becomes a read/write compare register. It functions exactly as the one described in subsection 8.2.2, on page 8-6, except that T2nCC cannot reset the counter. When the 16-bit counter value matches the capture/compare register value, the circuit conducts the following:
8-8
Sets the T2nC2 INT FLAG bit (T2nCTL2.6) to 1.
T2n Components
8.2.4.2
Toggles the PWM output pin if the T2nC2 OUT ENA bit (T2nCTL3.5) is set. Generates a T2n interrupt if the T2nC2 INT ENA bit (T2nCTL2.1) is set.
Dual Capture Mode
In the dual capture mode, the capture/compare register becomes a read-only capture register. When an external pulse appears on pin T2nIC1/CR, the following events occur if the T2nEDGE1 DET ENA bit (T2nCTL3.0) is set:
-
The current counter value is latched into the capture/compare register. The T2nEDGE1 INT FLAG bit (T2nCTL2.7) is set. Generates an interrupt if the T2nEDGE1 INT ENA bit (T2nCTL2.2) is set.
Timer 2A (T2A) and Timer 2B (T2B) Modules
8-9
Operating Modes
8.3 Operating Modes
The T2n operating mode is determined by the T2n MODE bit (T2nCTL3.7). T2n MODE = 0 = dual compare mode T2n MODE = 1 = dual capture mode
8.3.1
Dual Compare Mode
The dual compare mode provides the following:
-
A 16-bit compare register (called compare 1) A 16-bit capture/compare register that acts as a compare register (called compare 2) A 16-bit externally resettable counter A timer output pin
These components allow T2n to act as an interval timer, a PWM output, simple output toggle, or many other timer functions. In the dual compare mode, the operation of the T2n module is identical to that of the T1 module, with the exception of the clock sources. The dual compare mode is shown in Figure 8-2.
8-10
Operating Modes
Figure 8-2. Dual Compare Mode
T2nCC.15-0
16-bit LSB capture/compare register MSB T2nC2 INT FLAG
Clock source
Output enable
T2nCTL2.6 T2nCNTR.15-0
LSB MSB 16-Bit counter Reset T2nC1 RST ENA T2nCTL3.4 Compare= 16 Compare=
T2nCTL3.5
T2nC2 OUT ENA External pin connection
T2nCTL2.1 T2nC2 INT ENA
T2nC1 INT FLAG T2nCTL2.5
Toggle
T2nCTL3.6
T2nC1 OUT ENA
T2nPC2.7-4
T2nIC2/ PWM
T2nC.15-0
16-bit LSB compare register MSB
T2nCTL2.0 T2nC1 INT ENA
T2nCTL3.3
T2nEDGE1 OUT ENA
External pin connection
T2nCTL1.0 T2n SW RESET
T2n OVRFL INT FLAG
T2nPC2.3-0
T2nIC1/ CR
T2nCTL3.1 T2nEDGE1 RST ENA
Edge 1 select
T2nCTL1.3 T2nCTL1.4
T2n OVRFL INT ENA T2nEDGE1 INT FLAG T2n PRIORITY
T2nCTL3.0 T2nEDGE1 DET ENA T2nCTL3.2
T2nEDGE1 POLARITY
T2nPRI.6 Level 1 Int 0
1 Level 2 Int
T2nCTL2.7 T2nCTL2.2 T2nEDGE1 INT ENA
Note:
The annotations on the diagram identify the register and the bit (s) in the peripheral frame. For example, the actual address of T2nCTL2.0 is 106Bh (n=A) or 108Bh (n=B), bit 0, in the T2nCTL2 register.
8.3.2
Dual Capture Mode
In the dual capture mode, T2n provides the following:
-
A 16-bit compare register for use as a programmable interval timer A 16-bit capture register 2 for external input time and pulse width measurement A 16-bit capture/compare register 1 that acts as a capture register for external input timing and pulse width measurement
The dual capture mode is shown in Figure 8-3 on page 8-12.
Timer 2A (T2A) and Timer 2B (T2B) Modules
8-11
Operating Modes
Figure 8-3. Dual Capture Mode
T2nCC.15-0
16-bit LSB capture/compare register 1 MSB
T2nIC.15-0
16-bit capture register 2 LSB MSB
Clock source
T2nCNTR.15-0
LSB MSB 16-bit counter 16 T2nC1 INT FLAG T2nCTL2.5
T2n PRIORITY T2nPRI.6 Level 1 Int 0 1 Level 2 Int
Compare = Reset
T2nCTL2.0 T2nC.15-0
External pin connections T2n SW RESET T2nCTL1.0 T2nC1 RST ENA 16-bit compare register LSB MSB T2nC1 INT ENA T2n OVRFL INT FLAG T2nCTL1.3
T2nCTL1.4 T2nCTL3.4 T2nCTL3.0 T2nEDGE1 DET ENA
Edge1 select T2n OVRFL INT ENA T2nEDGE1 INT FLAG T2nCTL2.7
T2nPC2.3-0
T2nIC1/CR
T2nCTL3.2 T2nEDGE1 POLARITY T2nCTL3.1 T2nEDGE2 DET ENA
T2nCTL2.2 T2nEDGE1 INT ENA
T2nPC2.7-4
T2nIC2/PWM Edge 2 select
T2nEDGE2 INT FLAG T2nCTL2.6
T2nCTL3.3
T2nEDGE2 POLARITY
T2nCTL2.1
T2nEDGE2 INT ENA
Note: The annotations on the diagram identify the register and the bit (s) in the peripheral frame. For example, the actual address of T2nCTL2.0 is 106Bh (n=A) or 108Bh (n=B), bit 0, in the T2nCTL2 register. Each input capture pin (T2nIC1/CR and T2nIC2/PWM) has an input edge detect function enabled by the associated DET ENA control bit, with the associated POLARITY bit selecting the active input transition. On the occurrence of a valid input on the T2nIC1/CR or T2nIC2/PWM pin, the current counter value is loaded into the 16-bit capture/compare register or 16-bit input capture register, respectively. In addition, the respective input capture INT FLAG bit is set, and a timer interrupt is generated if the respective INT ENA bit is set.
8-12
Edge-Detection Circuitry
8.4 Edge-Detection Circuitry
This edge detection circuitry senses an active pulse transition on the input pins and provides appropriate output transitions to the rest of the module.
8.4.1
Dual Compare Mode
In this mode, the edge detection circuitry is connected to the module's T2nIC1/CR pin. The program must set the T2nEDGE1 DET ENA bit (T2nCTL3.0) to re-enable the T2n module after each edge detection. When the T2n module detects an active transition (while enabled), then the module performs the following:
-
Clears the T2nEDGE1 DET ENA bit. Sets the T2nEDGE1 INT FLAG bit (T2nCTL2.7). Resets the counter if T2nEDGE1 RST ENA bit (T2nCTL3.1) is set. Toggles the output flip-flop if the T2nEDGE1 OUT ENA bit (T2nCTL3.3) is set.
In the dual compare mode, the T2nEDGE1 POLARITY bit (T2nCTL3.2) determines whether the active transition is low-to-high or high-to-low.
8.4.2
Dual Capture Mode
In this mode, the edge detection circuitry is connected to both the T2nIC1/CR pin and the T2nIC2/PWM pin. When the edge 1 detect circuit detects an active edge transition on the T2nIC1/CR pin, the T2n module conducts the following:
-
Loads the capture/compare register with the current counter value. Sets the T2nEDGE1 INT FLAG bit (T2nCTL2.7).
When the edge 2 detect circuit detects an active edge transition on the T2nIC2/PWM pin, the module performs the following: Loads the capture register with the current counter value. Sets the T2nEDGE2 INT FLAG bit (T2nCTL2.6).
The T2nEDGE1 POLARITY bit (T2nCTL3.2) and the T2nEDGE2 POLARITY bit (T2nCTL3.3) determine the transition (rising or falling) to be detected.
Timer 2A (T2A) and Timer 2B (T2B) Modules
8-13
Clock Sources
8.5 Clock Sources
The T2n clock sources are shown in Figure 8-4 and can be any of the following:
External pin connection
System clock No clock (the counter is stopped) External clock synchronized to the system clock (event counter) System clock while external input is high (pulse accumulation)
Figure 8-4. T2n Clock Sources
Event T2nEVT Sync Accum Counter clock Frequency (SYSCLK)
Select
The T2n INPUT SELECT0 bit (T2nCTL1.1) and the T2n INPUT SELECT1 bit (T2nCTL1.2) select one of four clock sources (refer to subsection 8.8.1 on page 8-19 ). The maximum counter duration with an internal clock is based on the internal system clock time (SYSCLK) as follows: Maximum Counter Duration Counter Resolution where: SYSCLK = = = = 216 x (1/SYSCLK) 1/SYSCLK CLKIN/4 for divide-by-4 clock CLKIN/1 for divide-by-1 clock
The external event frequency input to the module cannot exceed SYSCLK/2. All external event inputs are synchronized with the system clock. When the timer is using the system clock input, the 16-bit timer generates an overflow rate of 13.1 ms with 200-ns resolution (5-MHz SYSCLK).
8-14
Clock Sources
8.5.1
Event Counter Mode
When you use the event counter clock source, the 16-bit counter is programmable as a 16-bit event counter. An external low-to-high transition on the T2nEVT pin provides the clock for the internal timer. The T2nEVT external clock frequency cannot exceed the system clock frequency divided by 2.
8.5.2
Pulse Accumulator Mode
When you use the pulse accumulator clock source, the 16-bit counter is programmable as a 16-bit pulse accumulator. An external input on the T2nEVT pin is used to gate the internal system clock to the internal timers. While Tn2EVT input is logic one (high), the timer is clocked at the system clock rate and counts system clock pulses until the T2nEVT pin returns to logic zero.
Timer 2A (T2A) and Timer 2B (T2B) Modules
8-15
Interrupts
8.6 Interrupts
Interrupts can be enabled to occur upon an output compare equal, counter overflow, and/or an external edge detect ( input capture). In dual compare mode, the following four separate events can generate an interrupt:
-
A compare-equal for the dedicated compare register if the T2nC1 INT ENA bit (T2nCTL2.0) is set A compare-equal for the capture/compare register if the T2nC2 INT ENA bit (T2nCTL2.1) is set A counter overflow if the T2n OVERFL INT ENA bit (T2nCTL1.4) is set An external edge detect if the T2nEDGE1 DET ENA and T2nEDGE1 INT ENA bits are set (T2nCTL3.0 and T2nCTL2.2, respectively)
In dual capture mode, four separate events can generate an interrupt. These events are as follows: A compare-equal for the dedicated compare register if the T2nC1 INT ENA bit (T2nCTL2.0) is set A counter overflow if the T2n OVERFL INT ENA bit (T2nCTL1.4) is set An external edge 1 detect if the T2nEDGE1 DET ENA and T2nEDGE1 INT ENA bits are set (T2nCTL3.0 and T2nCTL2.2) An external edge 2 detect if the T2nEDGE2 DET ENA and T2nEDGE2 INT ENA bits are set (T2nCTL3.1 and T2nCTL2.1)
Note: All set and enabled interrupt flags must be cleared before the processor exits the T2n interrupt routine. If the flags are not reset, the processor will enter the T2n interrupt routine again instead of continuing the mainstream program. If the flag bits are never cleared, the program will continually enter the interrupt service routine.
8-16
Low-Power Modes/T2n Control Registers
8.7 Low-Power Modes
The T2n module supports low-power (powerdown) modes that aid in reducing power consumption during periods of inactivity. These modes are the halt and the standby modes. In both the halt and standby modes, no clocks or external inputs are recognized. If the PWRDWN/IDLE bit (SCCR2.6) is set, the low-power modes are entered when an IDLE instruction is executed by the CPU. During the low-power mode, the T2n module holds the pre-idle status of all storage elements. All external pins are held constant, regardless of the pin function: inputs remain inputs, output low levels remain low, and output high levels remain high. When the idle state is exited, the I/O timer module continues from where it entered the idle state.
8.8 T2n Control Registers
Six registers control the T2n module operating mode selection, interrupt enable, status flags, and output configuration. These registers are shown in Figure 8-5. The bits that are shown in shaded boxes are privilege mode bits; that is, they can be written to only in the privilege mode. Note: Special circuitry prevents 16-bit registers from changing in the middle of a 16-bit read or write operation. When you read a 16-bit register, read the least significant byte (LSbyte) first to lock in the value, and then read the most significant byte (MSbyte). When you write to a 16-bit register, write the MSbyte first and then write the LSbyte. The register value does not change between reading and writing the bytes when they are done in this order. While you access a 16-bit register, do not read or write from a second 16-bit register within this module; if you do, the value for the first register's MSbyte will not be correct. The 16-bit read/write operation actually occurs when you access the LSbyte. In summary, the read/write operation should be conducted in the following order: Read: Write: LSbyte then MSbyte MSbyte then LSbyte
Timer 2A (T2A) and Timer 2B (T2B) Modules
8-17
T2n Control Registers
Figure 8-5. Peripheral File Frames 6 (T2A) and 8 (T2B): T2n Control Registers
Designation T2nCNTR T2nCNTR T2nC T2nC T2nCC T2nCC T2nIC T2nIC ADDR T2A/T2B 1060h/1080h 1061h/1081h 1062h/1082h 1063h/1083h 1064h/1084h 1065h/1085h 1066h/1086h 1067h/1087h 1068h/1088h 1069h/1089h T2nCTL1 106Ah/108Ah PF T2A/T2B P060/P080 P061/P081 P062/P082 P063/P083 P064/P084 P065/P085 P066/P086 P067/P087 P068/P088 P069/P089 P06A/P08A -- -- -- Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 T2n INPUT SELECT1 (RW-0) T2n INPUT SELECT0 (RW-0) T2n SW RESET (S-0)
T2n Counter MSbyte T2n Counter LSbyte Compare Register MSbyte Compare Register LSbyte Capture/Compare Register MSbyte Capture/Compare Register LSbyte Capture Register 2 MSbyte Capture Register 2 LSbyte Reserved Reserved T2n OVRFL INT ENA (RW-0) T2n OVRFL INT FLAG (RC-0)
In Dual Compare Mode T2nCTL2 106Bh/108Bh P06B/P08B T2nEDGE1 INT FLAG (RC-0) T2nC2 INT FLAG (RC-0) T2nC1 INT FLAG (RC-0) -- -- T2nEDGE1 INT ENA (RW-0) T2nC2 INT ENA (RW-0) T2nC1 INT ENA (RW-0)
In Dual Capture Mode T2EDGE1 INT FLAG (RC-0) T2EDGE2 INT FLAG (RC-0) T2nC1 INT FLAG (RC-0) -- -- T2nEDGE1 INT ENA (RW-0) T2nEDGE2 INT ENA (RW-0) T2nC1 INT ENA (RW-0)
In Dual Compare Mode T2nCTL3 106Ch/108Ch P06C/P08C T2n MODE= 0 (RW-0) T2nC1 OUT ENA (RW-0) T2nC2 OUT ENA (RW-0) T2nC1 RST ENA (RW-0) T2nEDGE1 OUT ENA (RW-0) T2nEDGE1 POLARITY (RW-0) T2nEDGE1 RST ENA (RW-0) T2nEDGE1 DET ENA (RW-0)
In Dual Capture Mode T2n MODE= 1 (RW-0) -- -- T2nC1 RST ENA (RW-0) T2nEDG2 POLARITY (RW-0) T2nEDGE1 POLARITY (RW-0) T2nEDGE2 DET ENA (RW-0) T2nEDGE1 DET ENA (RW-0)
In Dual Compare and Dual Capture Mode T2nPC1 106Dh/108Dh P06D/P08D -- T2nPC2 106Eh/108Eh P06E/P08E T2nIC2/ PWM DATA IN (R-0) T2n STEST (RP-0) --
T2nIC2/PWM
--
T2nIC2/PWM
--
T2nIC2/PWM
T2nEVT DATA IN (R-0) T2nIC1/CR DATA IN (R-0)
T2nEVT DATA OUT (RW-0) T2nIC1/CR DATA OUT (RW-0)
T2nEVT FUNCTION (RW-0) T2nIC1/CR FUNCTION (RW-0)
T2nEVT DATA DIR (RW-0) T2nIC1/CR DATA DIR (RW-0)
DATA OUT (RW-0) T2n PRIORITY (RP-0)
FUNCTION (RW-0)
DATA DIR (RW-0)
T2nPRI
106Fh/108Fh
P06F/P08F
--
--
--
--
--
--
8-18
T2n Control Registers
8.8.1
T2n Control Register 1 (T2nCTL1)
The T2nCTL1 register controls the clock input selection, counter overflow interrupts, and counter software reset.
T2n Control Register 1 (T2nCTL1) [Memory Address 106Ah (T2A) or 108Ah (T2B)]
Bit #
P06A or P08A
7
--
6
--
5
--
4
T2n OVRFL INT ENA RW-0
3
T2n OVRFL INT FLAG RC-0
2
T2n INPUT SELECT1 RW-0
1
T2n INPUT SELECT0 RW-0
0
T2n SW RESET S-0
R = Read, W = Write, S = Set only, C = Clear only, -n = Value of the bit after the register is reset
Bits 7-5 Bit 4
Reserved. Read data is indeterminate. T2n OVRFL INT ENA. T2n Overflow Interrupt Enable This bit controls the T2n overflow interrupting capability. 0 = Disables interrupt 1 = Enables interrupt from overflow
Bit 3
T2n OVRFL INT FLAG. T2n Overflow Interrupt Flag This bit is the T2n counter overflow bit. 0 = Overflow interrupt is inactive. 1 = Overflow interrupt is pending.
Bits 2-1
T2n INPUT SELECT1-0. T2n Input Select These two bits select one of four clock sources as an input to the counter. The four options are:
- System clock with no prescale - System clock when external input is high (pulse accumulation) - External source synchronized with system clock (event input) - No clock
The combinations are shown below:
T2n INPUT SELECT2 0 0 1 1 T2n INPUT SELECT1 0 1 0 1 System clock Pulse accumulation Event input No clock input
Counter Clock Source
Bit 0
T2n SW RESET. T2n Software Reset When a 1 is written to this bit, the counter will reset to 0000h on the next system clock cycle; however, this bit is always read as a zero.
Timer 2A (T2A) and Timer 2B (T2B) Modules
8-19
T2n Control Registers
8.8.2
T2n Control Register 2 (T2nCTL2)
The T2nCTL2 register contains interrupt flags and controls the capability of the module to issue interrupts. Each of these registers is paired (P06B/P08B and P06C/P08C) with a T2n control register 3 (described in subsection 8.8.3 on page 8-23). The registers are used in the dual compare mode or in the dual capture mode depending on the mode set in the T2n control register 3, bit 7.
T2n Control Register 2 (T2nCTL2) [Memory Address 106Bh (T2A) or 108Bh (T2B)] Mode: Dual Compare
Bit #
P06B or P08B
7
T2nEDGE1 INT FLAG RC-0
6
T2nC2 INT FLAG RC-0
5
T2nC1 INT FLAG RC-0
4
--
3
--
2
T2nEDGE1 INT ENA RW-0
1
T2nC2 INT ENA RW-0
0
T2nC1 INT ENA RW-0
Mode: Dual Capture
Bit #
P06B or P08B
7
T2nEDGE1 INT FLAG RC-0
6
T2nEDGE2 INT FLAG RC-0
5
T2nC1 INT FLAG RC-0
4
--
3
--
2
T2nEDGE1 INT ENA RW-0
1
T2nEDGE2 INT ENA RW-0
0
T2nC1 INT ENA RW-0
R = Read, W = Write, C = Clear only, -n = Value of the bit after the register is reset
Bit 7
T2nEDGE1 INT FLAG. T2n External Edge 1 Interrupt Flag This bit is set when the appropriate edge is detected on the T2nIC1/CR pin. 0 = Interrupt inactive 1 = Interrupt pending from edge 1 detect circuitry Note: Be careful using the AND, OR, XOR, CMPBIT, SBIT0, or SBIT1 instruction to modify this register. The read/modify/write nature of these instructions can inadvertently clear an interrupt flag that was set between the read and the write cycles. If the state of the interrupt enable bits is known, the MOV #iop8, Pd instruction can be used. If the state of the interrupt enable bits is not known, a sequence similar to the example shown below should be used.
; Clearing the T2AC1 INT FLAG MOV P06B,A OR #0E0h,A AND #0DFh,A MOV A,P06B
8-20
T2n Control Registers
Bit 6
Dual Compare Mode:
T2nC2 INT FLAG. T2n Output Compare 2 Interrupt Flag This bit is set when the capture/compare register first matches the counter value. 0 = Interrupt inactive 1 = Interrupt pending from compare 2
Dual Capture Mode: T2nEDGE2 INT FLAG. T2n Edge 2 Interrupt Flag This bit is set when the appropriate edge is detected on T2nIC2/PWM and indicates that the capture register was loaded.
0 = Interrupt inactive 1 = Interrupt pending from edge 2 detect Bit 5 T2nC1 INT FLAG. T2n Output Compare 1 Interrupt Flag This bit is set when the output compare register first matches the counter value. 0 = Interrupt inactive 1 = Interrupt pending from compare 1 Bits 4-3 Bit 2 Reserved. Read data is indeterminate. T2nEDGE1 INT ENA. T2n External Edge 1 Interrupt Enable This bit determines whether or not the active edge input to the T2nIC1/CR pin generates an interrupt. 0 = Disables interrupt 1 = Enables interrupt Bit 1
Dual Compare Mode:
T2nC2 INT ENA. T2n Output Compare 2 Interrupt Enable This bit controls the interrupting capability of the compare 2 register. 0 = Disables interrupt 1 = Enables interrupt from compare 2 register
Dual Capture Mode: T2nEDGE2 INT ENA. T2n External Edge 2 Interrupt Enable This bit determines whether or not the active edge input to the T2nlC2/PWM pin generates an interrupt.
0 = Disables interrupt 1 = Enables interrupt
Timer 2A (T2A) and Timer 2B (T2B) Modules
8-21
T2n Control Registers
Bit 0
T2nC1 INT ENA. T2n Compare 1 Interrupt Enable This bit controls the interrupting capability of the compare 1 register. 0 = Disables interrupt 1 = Enables interrupt from compare 1 register
8-22
T2n Control Registers
8.8.3
T2n Control Register 3 (T2nCTL3)
The T2nCTL3 register controls the T2n module mode of operation (dual compare or dual capture as set by bit 7), outputs, active transition polarity, and counter reset. Each of these registers is paired with a T2n control register 2 (P06B/P08B and P06C/P08C) described in subsection 8.8.2 on page 8-20.
T2n Control Register 3 (T2nCTL3) [Memory Address 106Ch (T2A) or 108Ch (T2B)] Mode: Dual Compare
Bit #
P06C or P08C
7
T2n MODE= 0 RW-0
6
T2nC1 OUT ENA RW-0
5
T2nC2 OUT ENA RW-0
4
T2nC1 RST ENA RW-0
3
T2nEDGE1 OUT ENA RW-0
2
T2nEDGE1 POLARITY RW-0
1
T2nEDGE1 RST ENA RW-0
0
T2nEDGE1 DET ENA RW-0
Mode: Dual Capture
Bit #
P06C or P08C
7
T2n MODE=1 RW-0
6
--
5
--
4
T2nC1 RST ENA RW-0
3
T2nEDGE2 POLARITY RW-0
2
T2nEDGE1 POLARITY RW-0
1
T2nEDGE2 DET ENA RW-0
0
T2nEDGE1 DET ENA RW-0
R = Read, W = Write, -n = Value of the bit after the register is reset
Bit 7
T2n MODE. T2n Mode Select This bit selects the operating mode for the counter. 0 = Dual compare mode 1 = Dual capture mode
Bit 6
Dual Compare Mode:
T2nC1 OUT ENA. T2n Output Compare 1 Enable This bit controls whether or not the compare equal pulse from the compare register toggles T2nIC2/PWM pin. 0 = Disables pulse from toggling output 1 = Enables pulse to toggle output
Dual Capture Mode: Reserved. Read data is indeterminate.
Timer 2A (T2A) and Timer 2B (T2B) Modules
8-23
T2n Control Registers
Bit 5
Dual Compare Mode: T2nC2 OUT ENA. T2n Output Compare 2 Enable This bit controls whether or not the output compare equal pulse from the capture/compare register toggles the T2nIC2/PWM output pin. 0 = Disables pulse to toggle output 1 = Enables pulse to toggle output Dual Capture Mode: Reserved. Read data is indeterminate.
T2nC1 RST ENA. T2n Output Compare 1 Reset Enable This bit controls whether or not the compare equal pulse from the compare register resets the counter on the next counter increment. 0 = Disables reset upon compare equal 1 = Enables reset upon compare equal
Bit 4
Bit 3
Dual Compare Mode: T2nEDGE1 OUT ENA. T2n Edge 1 Detect Output Enable This bit controls whether or not the pulse indicating an external edge detect toggles the module's output pin. 0 = Disables pulse to toggle output 1 = Enables pulse to toggle output Dual Capture Mode: T2nEDGE2 POLARITY. T2n Edge 2 Polarity Select This bit controls which transition level on the T2nIC2/PWM pin is active. 0 = Triggers on high-to-low transition 1 = Triggers on low-to-high transition
T2nEDGE1 POLARITY. T2n Edge 1 Polarity Select This bit controls which transition level on the T2nIC1/CR pin is active. 0 = Triggers on high-to-low transition 1 = Triggers on low-to-high transition
Bit 2
Bit 1
Dual Compare Mode: T2nEDGE1 RST ENA. T2n Edge 1 Detect Reset Enable This bit controls whether or not an external signal can reset the counter. 0 = Disables external reset of the counter 1 = Enables external reset of the counter Dual Capture Mode: T2nEDGE2 DET ENA. T2n External Edge 2 Detect Enable This bit enables the edge detection circuit to sense the next active level transition on the T2nIC2/PWM pin. This bit remains unchanged after the selected transition is detected and during reset. 0 = Disables edge detect 1 = Enables edge detect
8-24
T2n Control Registers
Bit 0
Dual Compare Mode:
T2nEDGE1 DET ENA. T2n Edge 1 Detect Enable This bit enables the edge detection circuit to sense the next active level transition on the T2nIC1/CR pin. This bit is cleared after the selected transition is detected and during reset. 0 = Disables edge 1 detect 1 = Enables edge 1 detect
Dual Capture Mode: T2nEDGE1 DET ENA. T2n Edge 1 Detect Enable This bit enables the edge detection circuit to sense the next active level transition on the T2nIC1/CR pin. This bit remains unchanged after the selected transition is detected and during reset.
0 = Disables input capture. 1 = Enables input capture.
Timer 2A (T2A) and Timer 2B (T2B) Modules
8-25
T2n Control Registers
8.8.4
T2n Port Control Registers (T2nPC1 and T2nPC2)
The port control registers (PCRs) control the functions of the I/O pins. Each module pin is controlled by a nibble in one of the PCRs.
8.8.4.1
T2n Port Control Register 1 (T2nPC1)
The T2nPC1 register assigns the I/O function of the T2nEVT pin as either a general-purpose digital I/O or external event input of the module.
T2n Port Control Register 1 (T2nPC1) [Memory Address 106Dh (T2A) or 108Dh (T2B)]
Bit #
P06D or P08D
7
--
6
--
5
--
4
--
3
T2nEVT DATA IN R-0
2
T2nEVT DATA OUT RW-0
1
T2nEVT FUNCTION RW-0
0
T2nEVT DATA DIR RW-0
R = Read, W = Write, -n = Value of the bit after the register is reset
Bits 7-4 Bit 3
Reserved. Read data is indeterminate. T2nEVT DATA IN. T2n Event Pin Data In This bit contains the data to be input from the T2nEVT pin. A write to this bit has no effect.
Bit 2
T2nEVT DATA OUT. T2n Event Pin Data Out This bit contains the data to be output on the T2nEVT pin if the following conditions are met: a. Bit T2nEVT DATA DIR = 1 b. Bit T2nEVT FUNCTION = 0
Bit 1
T2nEVT FUNCTION. T2n Event Pin Function Select This bit selects the function of the T2EVT pin. 0 = T2nEVT is a general-purpose digital I/O pin. 1 = T2nEVT is the event input pin.
Bit 0
T2nEVT DATA DIR. T2n Event Pin Data Direction This bit determines the data direction on the T2nEVT pin if the T2nEVT FUNCTION bit = 0. 0 = T2nEVT is configured as input. 1 = T2nEVT is configured as output.
8-26
T2n Control Registers
8.8.4.2
T2n Port Control Register 2 (T2nPC2)
The T2nPC2 register assigns the I/O functions of the T2nIC1/CR and T2nIC2/PWM pins as either general-purpose digital I/O pins or the input capture/counter reset and PWM output pins, respectively.
T2n Port Control Register 2 (T2nPC2) [Memory Address 106Eh (T2A) or 108Eh (T2B)]
Bit #
P06E or P08E
7
T2nIC2/ PWM DATA IN R-0
6
T2nIC2/ PWM DATA OUT RW-0
5
T2nIC2/ PWM FUNCTION RW-0
4
T2nIC2/ PWM DATA DIR RW-0
3
T2nIC1/CR DATA IN R-0
2
T2nIC1/CR DATA OUT RW-0
1
T2nIC1/CR FUNCTION RW-0
0
T2nIC1/CR DATA DIR RW-0
R = Read, W = Write, -n = Value of the bit after the register is reset
Bit 7
T2nIC2/PWM DATA IN. T2n IC2/PWM Data In This bit contains the data input on the T2nIC2/PWM pin. A write to this bit has no effect.
Bit 6
T2nIC2/PWM DATA OUT. T2n IC2/PWM Data Out This bit contains the data output on the T2nIC2/PWM pin if the following conditions are true: a. Bit T2nIC2/PWM DATA DIR = 1 b. Bit T2nIC2/PWM FUNCTION = 0
Bit 5
T2nIC2/PWM FUNCTION. T2n IC2/PWM Function Select This bit determines the function of the T2nIC2/PWM pin. 0 = T2nIC2/PWM is a general-purpose digital I/O pin. 1 = T2nIC2/PWM is the input capture/PWM output pin.
Bit 4
T2nIC2/PWM DATA DIR. T2n IC2/PWM Data Direction This bit determines the direction of data on the T2nIC2/PWM pin if the T2nIC2/PWM FUNCTION bit = 0. 0 = T2nIC1/PWM is an input. 1 = T2nIC2/PWM is an output.
Bit 3
T2nIC1/CR DATA IN. T2n IC1/CR Data In This bit contains the data input on the T2nIC1/CR pin. A write to this bit has no effect.
Timer 2A (T2A) and Timer 2B (T2B) Modules
8-27
T2n Control Registers
Bit 2
T2nIC1/CR DATA OUT. T2n IC1/CR Data Out This bit contains the data output on the T2nIC1/CR pin if the following conditions are true: a. Bit T2nIC1/CR DATA DIR = 1 b. Bit T2nIC1/CR FUNCTION = 0
Bit 1
T2nIC1/CR FUNCTION. T2n IC1/CR Function Select This bit determines the function of the T2nIC1/CR pin. 0 = T2nIC1/CR is a general-purpose digital I/O pin. 1 = T2nIC1/CR is the input capture/counter reset pin.
Bit 0
T2nIC1/CR DATA DIR. T2n IC1/CR Data Direction This bit determines the direction of data on the T2nIC1/CR pin if the T2nIC1/CR FUNCTION bit = 0. 0 = T2nIC1/CR is an input. 1 = T2nIC1/CR is an output.
8-28
T2n Control Registers
8.8.5
T2n Interrupt Priority Control Register (T2nPRI)
The T2nPRI register assigns the priority level of interrupts generated by the T2n module. You can write to this register only in the privilege mode. During normal operation, this is a read-only register.
T2n Priority Control Register (T2nPRI) [Memory Address 106Fh (T2A) or 108Fh (T2B)]
Bit #
P06F or P08F
7
T2n STEST RP-0
6
T2n PRIORITY RP-0
5
--
4
--
3
--
2
--
1
--
0
--
R = Read, P = Privilege write only, -n = Value of the bit after the register is reset
Bit 7
T2n STEST. T2n STEST This bit must be cleared to ensure proper operation.
Bit 6
T2n PRIORITY. T2n Interrupt Priority Select This bit determines the level of T2n interrupts. 0 = Interrupts are level 1 (high priority) requests. 1 = Interrupts are level 2 (low priority) requests.
Bits 5-0
Reserved. Read data is indeterminate.
Timer 2A (T2A) and Timer 2B (T2B) Modules
8-29
8-30
Running Title--Attribute Reference
Chapter 9
Serial Communications Interface 1 (SCI1) Module
The SCI is described in Chapter 9 (SCI1: 3 I/O pins, asynchronous and isosynchronous modes) and Chapter 10 (SCI2: 2 I/O pins, asynchronous mode). This chapter describes SCI1 and covers the following topics:
Topic
9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8
Page
SCI1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 SCI1 Programmable Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7 Multiprocessor Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8 Communications Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12 Port Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15 Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-16 Initialization Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-18 SCI1 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-21
Chapter Title--Attribute Reference
9-1
SCI1 Overview
9.1
SCI1 Overview
The serial communications interface 1 (SCI 1) module is a programmable I/O port that facilitates digital communications between the TMS370 device and other asynchronous peripherals and uses the standard NRZ (nonreturn to zero) format. The SCI1 transmits and receives serial data, one bit at a time, at a programmable bit rate. Both the SCI1 receiver and transmitter are doublebuffered and have their own separate enable and interrupt bits. They can be operated independently or simultaneously in the full duplex mode. The SCI1 module is available in the following families: TMS370Cx0x, TMS370Cx2x, TMS370Cx4x, TMS370Cx5x, TMS370Cx6x, and TMS370CxAx.
9.1.1
Physical Description
The three-pin SCI1 module, shown in Figure 9-1, key features:
-
Three I/O pins:
-
J J J
SCIRXD (SCI1 receive data input) SCITXD (SCI1 transmit data output) SCICLK (SCI1 bidirectional serial clock)
Two communications formats:
J J J J
Asynchronous Isosynchronous
Programmable bit rates to over 65,000 different speeds through a 16-bit baud select register Asynchronous:
H H H H
Range at 5 MHz SYSCLK--3 bits/s to 156 Kbits/s Number of bit rates--64K
Isosynchronous: Range at 5 MHz SYSCLK--39 bits/s to 2.5 Mbits/s Number of bit rates--64K
-
Programmable data word length from 1 to 8 bits Programmable stop bits of either 1 or 2 bits in length Error detection flags that ensure data integrity:
J J J J
Parity error Overrun error Framing error Break detect
9-2
SCI1 Overview
-
Two wake-up multiprocessor modes that can be used with either communications format:
J J
Idle line wake-up Address bit wake-up
Full duplex operation Separate transmitter and receiver interrupts for polled or interrupt-driven operation Double-buffered receive and transmit functions Separate enable bits for the transmitter and receiver NRZ (nonreturn to zero) format
Serial Communications Interface 1 (SCI1) Module
9-3
SCI1 Overview
Figure 9-1. SCI1 Block Diagram - Three Pin Configuration
Frame format and mode PARITY EVEN/ ODD ENABLE TXWAKE SCICTL.3 1 WUT 8 TX EMPTY TXCTL.6 TXENA
TXBUF.7 - 0
Transmit data buffer reg. SCI TX Interrupt SCI TX TXRDY INT ENA TXCTL.7
SCITX PRIORITY SCIPRI.6 Level 1 Int
0 1
SCICCR.6 SCICCR.5
TXCTL.0
Level 2 Int
External pin connections
SCIPC2.7 - 4
SCITXD SCITXD
BAUD MSB. 7 - 0
Baud rate MSbyte reg.
TXSHF Reg. CLOCK
SCICTL.1 SCIPC1.3 - 0
SYSCLK
SCICTL.4 BAUD LSB. 7 - 0
Baud rate LSbyte reg. RXSHF reg. RXWAKE RXCTL.1 RXENA RX ERROR SCIRXD SCIRX PRIORITY SCIPRI.5 Level 1 Int
0 1
SCICLK
SCIPC2.3 - 0
SCIRXD
SCI RX interrupt RXRDY RXCTL.6 BRKDT RXCTL.5 SCI RX INT ENA
SCICTL.0
8
RXCTL.7
ERR
RXCTL.4-2
FE OE PE Receive data buffer reg.
RXCTL.0
Level 2 Int
RXBUF.7 - 0
Note: SCI1 registers are described in detail in Section 9.8.1 beginning on page 9-22.
9-4
SCI1 Overview
9.1.2
Architecture
The major elements of the full-duplex SCI1 are shown in Figure 9-1 and include:
-
A transmitter (SCITX)
J J
TXBUF -- the transmitter buffer register that contains data, written by the CPU, to be transmitted TXSHF -- the transmitter shift register that is loaded from TXBUF and shifts data onto the SCITXD pin, one bit at a time
-
A receiver (SCIRX)
J J
RXSHF -- the receiver shift register that shifts data in from the SCIRXD pin, one bit at a time RXBUF -- the receiver buffer register that contains data that is to be read by the CPU and that is received from the remote processor and loaded from RXSHF
-
A programmable baud generator Memory-mapped control and status registers
The SCI1 receiver and transmitter can operate independently and simultaneously. A third port line, SCICLK, is available for an optional synchronizing clock line in the isosynchronous mode.
9.1.3
Communications Modes and Multiprocessing Modes
The SCI1 offers the following universal asynchronous receiver/transmitter (UART) communications modes for interfacing with many popular peripherals:
-
Asynchronous mode (discussed in subsection 9.4.1 on page 9-12) requires two lines to interface with many standard devices such as terminals and printers that use RS-232-C formats. Isosynchronous mode (discussed in subsection 9.4.2 on page 9-13) permits high transmission rates and requires a synchronizing clock signal between the receiver and transmitter.
Data transmission characteristics include: 1 start bit 1 to 8 data bits (SCICCR.0-2) An even/odd parity bit or no parity bit (SCICCR.6) 1 or 2 stop bits (SCICCR.7)
Serial Communications Interface 1 (SCI1) Module
9-5
SCI1 Overview
The SCI1 also has two multiprocessor modes: the idle line multiprocessor mode (see subsection 9.3.1 on page 9-9) and the address bit multiprocessor mode (see subsection 9.3.2 on page 9-10). These modes allow efficient data transfer between multiple processors and can be used with either the isosynchronous or standard asynchronous formats.
9.1.4
Control Registers
The SCI1 control registers are located at addresses 1050h to 105Fh and occupy peripheral file frame 5. The function of each location is shown in Table 9-1.
Table 9-1. SCI1 Memory Map
Peripheral File Location P050 P051 Symbol SCICCR SCICTL Name SCI Communication Control Register SCI Control Register Description Defines the character format, protocol, and communications mode used by the SCI1. Controls the RX/TX enable, TXWAKE and SLEEP functions, internal clock enable, and the SCI1 software reset. Stores the data required to generate the bit rate. See Page 9-22 9-24
P052 P053 P054
BAUD MSB BAUD LSB TXCTL
Baud Select MSbyte Register Baud Select LSbyte Register SCI Transmitter Interrupt Control and Status Register SCI Receiver Interrupt Control and Status Register Reserved
9-27
Contains the transmitter interrupt enable, the transmitter ready flag, and the transmitter empty flag. Contains one interrupt enable bit and seven receiver status flags.
9-28
P055 P056 P057 P058 P059 P05A-P05C P05D P05E P05F
RXCTL
9-29
RXBUF
SCI Receiver Data Buffer Reserved
Contains the current data from the receiver shift register.
9-31
TXBUF
SCI Transmit Data Buffer Reserved
Stores data bits to be transmitted by the SCITX.
9-31
SCIPC1 SCIPC2 SCIPRI
SCI Port Control Register 1 SCI Port Control Register 2 SCI Interrupt Priority Control Register
Controls the SCICLK pin functions. Controls the SCIRXD and SCITXD pin functions. Contains the receiver and transmitter interrupt priority select bits.
9-32 9-33 9-35
9-6
SCI1 Programmable Data Format
9.2 SCI1 Programmable Data Format
SCI1 data, both receive and transmit, is in NRZ (nonreturn to zero) format. The NRZ data format is illustrated in Figure 9-2 and consists of:
-
1 start bit 1 to 8 data bits An even/odd parity bit (optional) 1 or 2 stop bits An optional extra bit to distinguish addresses from data (address bit mode only).
The basic unit of data is called a character and is 1 to 8 bits in length. Each character of data is formatted with a start bit, 1 or 2 stop bits, and optional parity and address bits. A character of data with its formatting information is called a frame and is shown in Figure 9-2.
Figure 9-2. SCI1 Data Formats
Start LSB 2 3 4 5 6 7 MSB Parity Stop
Idle Line Mode (Normal Nonmultiprocessor Communications)
Start
LSB
2
3
4
5
6
7
MSB
Addr/ Data
Parity
Stop
Address Bit Mode
To program the data format, use the SCICCR register (described in subsection 9.8.1 on page 9-22). The bits that you use to program the data format are shown in Table 9-2.
Table 9-2. Programming the Data Format Using SCICCR
Bit Name SCI CHAR0-2 Designation SCICCR.0-2 Function Character length selection. Selects the character (data) length (1 to 8 bits). Refer to the bit listings on page 9-22 for additional information. Enables the parity function if set to 1 or disables the parity function if cleared to 0. If parity is enabled, selects odd parity if cleared to 0 or even parity if set to 1. Determines the number of stop bits transmitted--one stop bit if cleared to 0 or two stop bits if set to 1.
PARITY ENABLE EVEN/ODD PARITY STOP BITS
SCICCR.5 SCICCR.6 SCICCR.7
Serial Communications Interface 1 (SCI1) Module
9-7
Multiprocessor Communications
9.3 Multiprocessor Communications
The multiprocessor communication format allows one processor to efficiently send blocks of data to other processors on the same serial link. You can have only one talker on a serial line at a time. The first byte of a block of information that the talker sends contains an address byte that is read by all listeners. Only listeners with the correct address can be interrupted by the data bytes that follow the address byte. The listeners with an incorrect address remain uninterrupted until the next address byte. All processors on the serial link set their SLEEP bit (SCICTL.2) to 1 so that they are interrupted only when the address byte is detected. When a processor reads a block address that corresponds to the CPU's device address as set by software, your program must clear the SLEEP bit to enable the SCI1 to generate an interrupt on receipt of each data byte. Although the receiver still operates when the SLEEP bit is 1, it does not set RXRDY, RXINT, or the error status bits to 1 unless the address byte is detected and the address bit in the received frame is a 1. The SCI1 does not alter the SLEEP bit; your software must alter the SLEEP bit. A processor recognizes an address byte according to the multiprocessor mode:
-
The idle line mode leaves a quiet space before the address byte. This mode does not have an extra address/data bit and is more efficient than the address bit mode for handling blocks that contain more than 10 bytes of data. The address bit mode adds an extra bit into every byte to distinguish addresses from data. This mode is more efficient in handling many small blocks of data because, unlike the idle mode, it does not have to wait between blocks of data. However, at high transmit speeds, the program is not fast enough to avoid a 10-bit idle in the transmission stream.
You can select the multiprocessor mode via the ADDRESS/IDLE WUP bit (SCICCR.3). Both modes use the TXWAKE flag bit (SCICTL.3), RXWAKE flag bit (RXCTL.1), and the SLEEP flag bit (SCICTL.2) to control the SCITX and SCIRX features of these modes. In both multiprocessor modes, the sequence is: 1) The SCI1 port wakes up (requests an interrupt) at the start of a block and reads the first frame that contains the destination address. 2) A software routine is entered through the interrupt and checks the RXWAKE flag bit. If the RXWAKE bit is a 1, the incoming byte is an address
9-8
Multiprocessor Communications
(otherwise the byte is data) and this address byte is checked against its device address byte stored in memory. 3) If the check shows that the block is addressed to the microcontroller, the CPU clears the SLEEP bit and reads the rest of the block; if not, the software routine exits with the SLEEP bit still set and does not receive SCI interrupts until the next block start.
9.3.1
Idle Line Multiprocessor Mode
In the idle line multiprocessor mode (ADDRESS/IDLE WUP bit = 0), blocks are separated by having a longer idle time between the blocks than between frames in the blocks. An idle time of 10 or more bits after a frame indicates the start of a new block. The idle line multiprocessor communication format is shown in Figure 9-3. (ADDRESS/IDLE WUP bit is SCICCR.3.)
Figure 9-3. Idle Line Multiprocessor Communication Format
Blocks of Frames
RXD/TXD EXPANDED Last data
Sp
St
Addr
Sp St
Data
Sp
St Last data
Sp
St
Addr Sp
Idle period greater than 10 bits
First frame within block is address, it follows idle period of 10 bits or more
Frame within Idle period block less than 10 bits
Idle period greater than 10 bits
Note:
In the figure, "St" = start and "Sp" = stop
There are two ways to send a block start signal.
-
The first method is to deliberately leave an idle time of 10 bits or more by delaying the time between the transmission of the last frame of data in the previous block and the transmission of the address frame of the new block. In the second method, the SCI1 port uses the TXWAKE bit (SCICTL.3) to send an idle time of exactly 11 bits. Thus, the serial communications line is not idle any longer than necessary.
Associated with the TXWAKE bit is the wake-up temporary or WUT flag bit. WUT is an internal flag, double buffered with TXWAKE. When TXSHF is loaded from TXBUF, WUT is loaded from TXWAKE, and the TXWAKE bit is cleared to 0. This arrangement is shown in Figure 9-4.
Figure 9-4. Double-Buffered WUT and TXSHF
TXWAKE TXBUF
WUT
TXSHF
Serial Communications Interface 1 (SCI1) Module
9-9
Multiprocessor Communications
To send out a block start signal of exactly one frame time: 1) Write a 1 to the TXWAKE bit. 2) Write a data word (don't care) to TXBUF. (The first data word written is suppressed while the block start signal is sent out, and ignored after that.) When TXSHF is free again, TXBUF's contents are shifted to TXSHF, the TXWAKE value is shifted to WUT, and then the TXWAKE bit is cleared. If TXWAKE bit was set to a 1, the start, data, and parity bits are replaced by an idle period of 11 bits transmitted following the last stop bit of the previous frame. 3) Write an address value to the TXBUF. The receiver operates regardless of the SLEEP bit. The receiver does not set RXRDY, RXINT, or the error status bits until an address frame is detected.
9.3.2
Address Bit Multiprocessor Mode
In the address bit mode (ADDRESS/IDLE WUP bit = 1), frames have an extra bit, called an address bit, that immediately follows the last data bit. The address bit is set to 1 in the first frame of the block and to 0 in all other frames. The idle period timing is irrelevant (see Figure 9-5). (ADDRESS/IDLE WUP bit is SCICCR.3.) The TXWAKE bit value is placed in the address bit. In SCITX, when the TXBUF and TXWAKE are loaded into TXSHF and WUT, TXWAKE is reset to 0, and WUT is the value of the address bit of the current frame. Thus, to send an address: 1) Set the TXWAKE bit to a 1 and write the appropriate address value to the TXBUF. 2) When this address value is transferred to TXSHF and shifted out, its address bit is sent as a 1, which flags the other processors on the serial link to read the address. 3) Since TXSHF and WUT are both double-buffered, TXBUF and TXWAKE can be written to immediately after TXSHF and WUT are loaded. 4) To transmit nonaddress frames in the block, leave the TXWAKE bit at 0.
9-10
Multiprocessor Communications
Figure 9-5. Address Bit Multiprocessor Communication Format
Blocks of Frames
RXD/TXD EXPANDED Last data 0
Sp
St
Addr 1 Sp St
Data 0
Sp
St Last data 0
Sp
St Addr 1 Sp
Idle period is of no significance
First frame within block is address (ADDR/DATA bit is a 1)
ADDR/DATA Idle period is of no bit is a 0 for frame within significance block
Idle period is of no significance
Note:
In the figure, "St" = start and "Sp" = stop
Serial Communications Interface 1 (SCI1) Module
9-11
Communications Modes
9.4 Communications Modes
The SCIRX/SCITX (receiver/transmitter) has two operating modes: asynchronous and isosynchronous. The ASYNC/ISOSYNC bit (SCICCR.4) determines the mode of operation. Either of these two modes can be used with either of the two forms of multiprocessor protocol: idle line and address bit.
9.4.1
Asynchronous Communications Mode
The SCI1 asynchronous communication mode uses either single-line (oneway) or two-line (two-way) communications. In this mode, the frame consists of a start bit, one to eight data bits, an optional even/odd parity bit, and one or two stop bits. There are 16 SCICLK periods per data bit. The receiver begins operation on receipt of a valid start bit. A valid start bit consists of eight consecutive zero bits. If any bit is not zero, then the processor starts over and begins looking for another start bit. For the bits following the start bit, the processor determines the bit value by making three samples in the middle of the bits. These samples occur on the seventh, eighth, and ninth SCICLK period and are read on a majority (two out of three) basis. Figure 9-6 illustrates the asynchronous communication format, with a start bit showing how edges are found and where a majority vote is taken.
Figure 9-6. Asynchronous Communication Format
Falling Edge Detected SCICLK 1 2 3 4 5 6 7 8 9 10 11 1213 14 15 16 1 2 3 4 5 6 7 8 9 10 11 1213 14 1516 1 RXD Start Bit LSB of Data Majority Vote
Since the receiver synchronizes itself to frames, the external transmitting and receiving devices do not have to use a synchronized serial clock; the clock can be generated locally. If the CLOCK bit (SCICTL.4) and SCICLK FUNCTION bit (SCIPC1.1) are set, then the serial clock is output continuously on the SCICLK pin.
9-12
Communications Modes
9.4.2
Isosynchronous Communications Mode
The SCI1 isosynchronous communication mode uses either two-line (oneway) or three-line (two-way) communications. The extra line (serial clock) in each case is required for data synchronization. In the isosynchronous mode, each bit of data requires only one serial clock pulse for transmission or reception. Thus, the data bit period equals the SCICLK period, and data bits are read on a single sample basis. Since the receiver does not synchronize itself to data bits, the transmitter and receiver must be supplied with a common serial clock. If the internal serial clock is used, it must be output continuously on the SCICLK pin. The arrival of a valid start bit, which consists of a low on the RXD line at the time of a rising SCICLK edge, initiates receiver operation. Figure 9-7 illustrates the isosynchronous communication format. A complete frame consists of a start bit, one to eight data bits, an optional even/odd parity bit, and one or two stop bits.
Figure 9-7. Isosynchronous Communication Format
SCICLK
TXD
Bit Out
Bit Out
Bit Out
RXD
Bit In
Bit In
9.4.3
Receiver Signals in Communications Modes
Figure 9-8 illustrates receiver signal timing that assumes these conditions:
-
Address bit wake-up mode (address bit would not appear in idle line mode) 6 bits per character
Serial Communications Interface 1 (SCI1) Module
9-13
Communications Modes
Figure 9-8. SCI1 RX Signals in Communications Modes
RXENA A RXRDY B SCIRXD Pin STR 0 1 2 3 4 5 C D E STR 0 1 2 F
AD PA
STP
A) RX ENA goes high to enable the receiver. B) Data arrives on the SCIRXD pin; start bit detected. C) RXRDY goes high to signal that a new character has been received; data is shifted to RXBUF; an interrupt is requested. D) The program reads the RXBUF register; RXRDY is automatically cleared. E) The next byte of data arrives on the SCIRXD pin; start bit detected, then cleared. F) RX ENA goes low to disable the receiver; data continues to be assembled in the RXSHF register but is not transferred to the RXBUF register.
9.4.4
Transmitter Signals in Communications Modes
Figure 9-9 illustrates transmitter signal timing that assumes these conditions:
-
Address bit wake-up mode (address bit would not appear in idle line mode) 3 bits per character
Figure 9-9. SCI1 TX Signals in Communications Modes
TXENA A TX EMPTY TXRDY BC SCITXD Pin D E G F
STR
0
1
2
AD PA STP STR 0
1
2
AD PA
ST
A) TX ENA goes high to enable the transmitter to send data. B) Write to TXBUF; TXBUF is no longer empty. C) SCI transfers data to shift register; TXBUF is ready for new character and requests an interrupt. D) Program writes new character to TXBUF after TXRDY goes high (item C). E) Finished transmitting first character; transfer new character to shift register. F) TX ENA goes low to disable transmitter; SCI finishes transmitting current character. G) Finished transmitting character; TXBUF is empty and ready for new character.
9-14
Port Interrupts
9.5 Port Interrupts
The SCI1 provides independent interrupt requests and vectors for the receiver and transmitter.
-
If the SCI RX INT ENA bit (RXCTL.0) is set, the receiver interrupt is asserted when one of the following events occurs:
J J
The SCI1 receives a complete frame and transfers the data in the RXSHF register to the RXBUF register. This action sets the RXRDY flag (RXCTL.6) and initiates an interrupt. A break detect condition occurs (the SCIRXD is low for 10 bit periods following a stop bit). This action sets the BRKDT flag bit (RXCTL.5) and initiates an interrupt.
-
If the SCI TX INT ENA bit (TXCTL.0) is set, the transmitter interrupt is asserted whenever the data in the TXBUF register is transferred to the TXSHF register, indicating that the CPU can write to the TXBUF; this action sets the TXRDY flag bit (TXCTL.7) and initiates an interrupt.
SCI1 interrupts can be programmed onto different priority levels by the SCI RX PRIORITY (SCIPRI.5) and SCI TX PRIORITY (SCIPRI.6) control bits. When both RX and TX interrupt requests are made on the same level, the receiver always has higher priority than the transmitter; this reduces the possibility of receiver overrun.
Serial Communications Interface 1 (SCI1) Module
9-15
Clock Sources
9.6 Clock Sources
The SCI1 port can be driven by an internal or external baud generator. The CLOCK bit (SCICTL.4) configures the SCI1 clock source as either an input or an output:
-
If an external clock source is selected (CLOCK = 0) and the SCICLK FUNCTION bit (SCIPC1.1) is set, the SCICLK pin functions as the highimpedance serial clock input pin. If an internal clock source is selected (CLOCK = 1), the SCICLK pin can be used as a general-purpose I/O pin or as the serial clock output pin. If the serial clock output is selected (SCICLK FUNCTION = 0), a 50-percent duty cycle clock signal is output on the SCICLK pin that makes it a serial clock output pin.
The SCI1 receives data on rising clock edges and transmits data on falling clock edges. The internally generated serial clock is determined by the TMS370 SYSCLK frequency and the baud select registers. The SCI1 uses the 16-bit value of the baud select registers to select one of 64K different serial clock rates for the communication modes in the following manner:
-
Asynchronous Baud = SYSCLK / [(BAUD REG + 1) x 32] BAUD REG = [SYSCLK / (Asynchronous Baud x 32)] - 1 Isosynchronous Baud = SYSCLK / [(BAUD REG + 1) x 2] BAUD REG = [SYSCLK / (Isosynchronous Baud x 2)] - 1 SCICLK frequency = SYSCLK / [(BAUD REG + 1) x 2] BAUD REG = [SYSCLK / (SCICLK frequency x 2)] - 1
where BAUD REG = The 16-bit value in the baud select registers. Refer to Table 9-3. The baud select registers are further defined in subsection 9.8.3 on page 9-27.
9-16
Clock Sources
Table 9-3. Asynchronous Baud Register Values for Common SCI1 Bit Rates
SYSCLK Frequency (MHz) 0.6144 Baud 75 300 600 1200 2400 4800 9600 19200 38400 156000 Baud Reg 255 63 31 15 7 3 1 0 % Error 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 1.8432 Baud Reg 767 191 95 47 23 11 5 2 % Error 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 4.9152 Baud Reg 2047 511 255 127 63 31 15 7 3 % Error 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 5.0 Baud Reg 2082 520 259 129 64 32 15 7 3 0 % Error 0.02 -0.03 0.16 0.16 0.16 -1.38 1.73 1.73 1.73 0.16
Baud Reg = 16-bit baud register value Divide-by-1 clock can only operate from a minimum of 2 MHz SYSCLK to a maximum of 5 MHz SYSCLK.
Note: When the device is using an externally generated SCICLK in isosynchronous mode, the maximum speed at which the SCICLK can run is limited to SYSCLK/10. This is necessary so that the internal clocks of the SCI1 have time to synchronize with the external clock. For this reason, it is recommended to use the TMS370 to drive the master serial clock in a system where maximum throughput is a major concern. You can determine the current logic level on the SCICLK pin by reading the SCICLK DATA IN bit (SCIPC1.3).
Serial Communications Interface 1 (SCI1) Module
9-17
Initialization Examples
9.7 Initialization Examples
This section contains two examples that initialize the serial port. In each example, the data is moved to and from the buffers in the interrupt routines. 1) The first example shows a typical RS-232 application that connects to a terminal. 2) The second example illustrates the address bit mode in a multiprocessor application. In both examples, assume that the register mnemonics have been equated (EQU) with the corresponding peripheral-file location. For more examples using the TMS370 SCI, consult Using the TMS370 SPI and SCI Modules Application Report.
9.7.1
RS-232-C Example
This example initializes the transmitter and receiver to accept data at 9600 baud with a format of 8 data bits, 1 stop bit, and even parity.
B9600 HI
.EQU .EQU
15 00
AND
#01Fh, SCICTL
MOV MOV MOV MOV MOV MOV MOV MOV MOV EINT MOV
#000h,SCIPRI #005h,SCIPC1 #022h,SCIPC2 #HI,BAUDMSB #B9600,BAUDLSB #077h,SCICCR #033h,SCICTL #001h,TXCTL #001h,RXCTL #00,TXBUF
;Value for counter for 9600 baud ;value = (SYSCLK/32/baud) - 1 = ;(5 MHz/32/9600) - 1 = 15.27 ~ 15 ;1.8 percent error ;Make sure that SCI SW RESET bit is ;clear before writing to the SCI ;configuration registers ;Set TX and RX to high priority ;Set SCLK for general-purpose output ;Set pins for RXD and TXD functions ;Set bit rate for 9600 (MSbyte) ;Set bit rate for 9600 (LSbyte) ;1 stop bit, even parity, ;and enable 8 data bits/char ;Enable Rx, Tx, clock is internal ;Enable TX interrupt ;Enable RX interrupt ;Let the interrupts begin ;Start transmitter by sending null ;character
9-18
Initialization Examples
9.7.2
RS-232-C Multiprocessor Mode Example
This example initializes the transmitter and receiver to accept data at 9600 baud with a format of 8 data bits, 1 stop bit, and even parity. It uses the address bit wake-up mode to implement the multiprocessor protocol.
B9600 HI
.EQU .EQU
15 00
MOV MOV MOV MOV MOV MOV MOV MOV MOV EINT EINT
#000h,SCIPRI #005h,SCIPC1 #022h,SCIPC2 #HI,BAUDMSB #B9600,BAUDLSB #07Fh,SCICCR #037h,SCICTL #001h,TXCTL #001h,RXCTL
;Value for counter for 9600 baud ;value = (SYSCLK/32/baud) - 1 = ;(5 MHz/32/9600) - 1 = 15.27 ~ 15 ;1.8 percent error ;Set TX and RX to high priority ;Set SCLK for general-purpose output ;Set pins for RXD and TXD functions ;Set bit rate for 9600 (MSbyte) ;Set bit rate for 9600 (LSbyte) ;1 stop bit, even parity, ;and enable 8 data bits/char ;Enable Rx, Tx; RX to sleep, ;clock is internal ;Enable TX interrupt ;Enable RX interrupt ;Let the interrupts begin ; ;MAIN ROUTINES ; ;Main line routine; set TXWAKE ;wake bit ;Transmit address stored in ADDR ;INTERRUPT ROUTINES ; ;The locations of the SCI transmitter and ;receiver routines, SENDATA and GETDATA, ;need to be stored in the interrupt vec ;tor table at locations 70F0h and 7FF2h, ;respectively. ;SCI1 TRANSMITTER INTERRUPT ROUTINE
SENDADD
OR MOV RTS
#8,SCICTL ADDR,TXBUF
SENDDATA
PUSH MOV . . . POP RTI
A OUTDATA,TXBUF
A
;Address has already been sent by ;the SENDADD ;Output character that is ;stored in DATA ; ;Other transmitter code ; ;Restore and exit
Serial Communications Interface 1 (SCI1) Module
9-19
Initialization Examples
. GETDATA PUSH BTJZ MOV CMP JNE AND JMP ISDATA MOV . . . POP RTI A #2,RXCTL,ISDATA RXBUF,A #MYADDR,A RXEXIT #0FBh,SCICTL RXEXIT RXBUF,INDATA
;SCI1 RECEIVER INTERRUPT ROUTINE ;Receive a new character ;Is this address or data byte? ;Get new character and clear ;interrupt flag ;Is this my address or ;another processor's address ;Exit if another's; still ;in sleep mode ;If my address get out of sleep mode ;Exit and wait for data ; ;Put incoming data in register ; ;Other receiver code ; ;Restore and exit
RXEXIT
A
9-20
SCI1 Control Registers
9.8
SCI1 Control Registers
The SCI1 is controlled and accessed through registers in peripheral file frame 5. These registers are listed in Figure 9-10 and described in the following subsections. The bits shown in shaded boxes in Figure 9-10 are privilege mode bits; that is, they can only be written to in the privilege mode.
Figure 9-10. Peripheral File Frame 5: SCI1 Control Registers
Designation SCICCR ADDR 1050h PF P050
Bit 7
STOP BITS (RW-0) --
Bit 6
EVEN/ODD PARITY (RW-0) -- BAUDE (RW-0) BAUD6 (RW-0) TX EMPTY (R-1) RXRDY (R-0)
Bit 5
PARITY ENABLE (RW-0) SCI SW RESET (RW-0) BAUDD (RW-0) BAUD5 (RW-0) -- BRKDT (R-0)
Bit 4
ASYNC/ ISOSYNC (RW-0) CLOCK (RW-0) BAUDC (RW-0) BAUD4 (RW-0) -- FE (R-0) Reserved
Bit 3
ADDRESS/ IDLE WUP (RW-0) TXWAKE (RS-0) BAUDB (RW-0) BAUD3 (RW-0) -- OE (R-0)
Bit 2
SCI CHAR2 (RW-0) SLEEP (RW-0) BAUDA (RW-0) BAUD2 (RW-0) -- PE (R-0)
Bit 1
SCI CHAR1 (RW-0) TXENA (RW-0) BAUD9 (RW-0) BAUD1 (RW-0) -- RXWAKE (R-0)
Bit 0
SCI CHAR0 (RW-0) RXENA (RW-0) BAUD8 (RW-0) BAUD0 (LSB) (RW-0) SCI TX INT ENA (RW-0) SCI RX INT ENA (RW-0)
SCICTL
1051h
P051
BAUD MSB
1052h
P052
BAUDF (MSB) (RW-0) BAUD7 (RW-0) TXRDY (R-1) RX ERROR (R-0)
BAUD LSB
1053h
P053
TXCTL
1054h
P054
RXCTL
1055h
P055
1056h RXBUF 1057h 1058h TXBUF 1059h 105Ah 105Bh 105Ch SCIPC1 105Dh
P056 P057 P058 P059 P05A P05B P05C P05D -- -- SCITXD DATA OUT (RW-0) SCITX PRIORITY (RP-0) -- SCITXD FUNCTION (RW-0) SCIRX PRIORITY (RP-0) -- TXDT7 (RW-0) TXDT6 (RW-0) TXDT5 (RW-0) RXDT7 (R-0) RXDT6 (R-0) RXDT5 (R-0)
RXDT4 (R-0)
RXDT3 (R-0)
RXDT2 (R-0)
RXDT1 (R-0)
RXDT0 (R-0)
Reserved TXDT4 (RW-0) TXDT3 (RW-0) TXDT2 (RW-0) TXDT1 (RW-0) TXDT0 (RW-0)
Reserved
SCICLK DATA IN (R-0) SCIRXD DATA IN (R-0) --
SCICLK DATA OUT (RW-0) SCIRXD DATA OUT (RW-0) --
SCICLK FUNCTION (RW-0) SCIRXD FUNCTION (RW-0) --
SCICLK DATA DIR (RW-0) SCIRXD DATA DIR (RW-0) --
SCIPC2
105Eh
P05E
SCITXD DATA IN (R-0) SCI STEST (RP-0)
SCITXD DATA DIR (RW-0) SCI ESPEN (RP-0)
SCIPRI
105Fh
P05F
Note:
Shaded boxes indicate privilege mode.
Serial Communications Interface 1 (SCI1) Module
9-21
SCI1 Control Registers
9.8.1
SCI Communication Control Register (SCICCR)
The SCICCR register defines the character format, protocol, and communications modes used by the SCI1.
SCI Communication Control Register (SCICCR) [Memory Address 1050h]
Bit #
P050
7
STOP BITS RW-0
6
EVEN/ODD PARITY RW-0
5
PARITY ENABLE RW-0
4
ASYNC/ ISOSYNC RW-0
3
ADDRESS/ IDLE WUP RW-0
2
SCI CHAR2 RW-0
1
SCI CHAR1 RW-0
0
SCI CHAR0 RW-0
R = Read, W = Write, -n = Value of the bit after the register is reset
Bit 7
STOP BITS. SCI1 Number of Stop Bits. This bit determines the number of stop bits transmitted. The receiver checks for one stop bit only. 0 = One stop bit 1 = Two stop bits
Bit 6
EVEN/ODD PARITY. SCI1 Parity Enable. If the PARITY ENABLE bit is set, this bit selects odd or even parity (odd or even number of one bits in both transmitted and received characters). 0 = Sets odd parity 1 = Sets even parity
Bit 5
PARITY ENABLE. SCI1 Parity Enable. This bit enables or disables the parity function. When parity is enabled during the address bit multiprocessor mode, the address bit is included in the parity calculation. 0 = Disables parity. No parity bit is generated during transmission or expected during reception. 1 = Enables parity
Bit 4
ASYNC/ISOSYNC. SCI1 communications Mode Control Bit. This bit determines the SCI1 communications mode. 0 = Selects isosynchronous mode. In this mode, the bit period is equal to the SCICLK period; bits are read on a single-sample basis. 1 = Selects asynchronous mode. In this mode, the bit period is 16 times the SCICLK period; bits are read on a two-out-of-three majority basis.
9-22
SCI1 Control Registers
Bit 3
ADDRESS/IDLE WUP. SCI1 Multiprocessor Mode Control Bit. This bit selects the multiprocessor mode. 0 = Selects idle line mode 1 = Selects address bit mode The idle line mode is usually used for normal communications because the address bit mode adds an extra bit to the frame; the idle line mode does not add this extra bit and is compatible with RS-232-type communications. Multiprocessor communication is different from the other communications modes because it uses TXWAKE and SLEEP functions.
Bits 2-0
SCI CHAR2-0. SCI1 Character Length Control Bits 2-0. These bits select the SCI character (data) bit length, from 1 to 8 bits. Characters of less than 8 bits are right-justified in RXBUF and TXBUF, and are padded with leading 0s in RXBUF. TXBUF need not be padded with leading zeros.
Table 9-4. Character Bit Length
SCI CHAR2 0 0 0 0 1 1 1 1 SCI CHAR1 0 0 1 1 0 0 1 1 SCI CHAR0 0 1 0 1 0 1 0 1 Character Length 1 2 3 4 5 6 7 8
Serial Communications Interface 1 (SCI1) Module
9-23
SCI1 Control Registers
9.8.2
SCI Control Register (SCICTL)
The SCICTL register controls the RX/TX enable, TXWAKE and SLEEP functions, internal clock enable, and the SCI1 software reset.
SCI Control Register (SCICTL) [Memory Address 1051h]
Bit #
P051
7
--
6
--
5
SCI SW RESET RW-0
4
CLOCK RW-0
3
TXWAKE RS-0
2
SLEEP RW-0
1
TXENA RW-0
0
RXENA RW-0
R = Read, W = Write, S = Set only, -n = Value of the bit after the register is reset
Bits 7-6 Bit 5
Reserved. Read data is indeterminate. SCI SW RESET. SCI1 Software Reset (Active Low). Writing a 0 to this bit initializes the SCI state machines and operation flags to the reset condition (shown in Table 9-5). The CLOCK bit retains its state prior to the assertion of SCI SW RESET. If SCICLK is configured as an output (by bits SCIPC1.0 and1), the SCICLK resets (low level). All affected logic is held in the reset state until a 1 is written to the SCI SW RESET bit. Thus, after a system reset, you must re-enable the SCI by writing a 1 to this bit. This bit must be cleared after a receiver break detect. SCI SW RESET affects the operating flags of the SCI1. This bit does not affect the configuration bits, nor does it put in the reset values. The flags listed in Table 9-5 are set to the values shown when SCI SW RESET is cleared. The operating flags are frozen until the SCI SW RESET bit is set again.
Table 9-5. Flags Affected by SCI SW RESET
SCI1 Flag TXRDY TXEMPTY RXWAKE PE OE FE BRKDT RXRDY RX ERROR Designation TXCTL.7 TXCTL.6 RXCTL.1 RXCTL.2 RXCTL.3 RXCTL.4 RXCTL.5 RXCTL.6 RXCTL.7 Value After SCI SW RESET 1 1 0 0 0 0 0 0 0
9-24
SCI1 Control Registers
Note:
First Clear SCI SW RESET Bit
The SCI SW RESET bit must be cleared before the SCI1 configuration registers can be set up or altered. The application program should set up all configuration registers before it sets the SCI SW RESET bit. Bit 4 CLOCK. SCI1 Internal Clock Enable. This bit determines the source of the SCICLK. Clearing this bit selects an external SCICLK, which is input on the high-impedance SCICLK line and bypasses the baud generator.
- For isosynchronous transactions, one bit is transmitted or received per SCICLK period. - For asynchronous transactions, one bit is transmitted or received per 16 SCICLK
periods.
The maximum frequency for the externally sourced SCICLK is CLKIN/16. Setting the CLOCK bit selects an internal SCICLK, derived from the baud generator. This signal can be output on the SCICLK line. 0 = External SCICLK 1 = Internal SCICLK Bit 3 TXWAKE. SCI1 Transmitter Wake-up. The TXWAKE bit controls the transmit features of the multiprocessor communication modes. This bit is cleared only by system reset. The SCI hardware clears this bit, once it has been transferred to wake-up temporary (WUT). Bit 2. SLEEP. SCI1 Sleep. This bit controls the receive features of the multiprocessor communication modes. You must clear this bit to bring the SCI1 out of sleep mode. 0 = Disables sleep mode 1 = Enables sleep mode Bit 1 TXENA. SCI1 Transmit Enable. Data transmission through the SCITXD pin occurs only when this bit is set. If this bit is reset, the transmission is not halted until all the data previously written to TXBUF has been sent. 0 = Disables SCI1 transmitter 1 = Enables SCI1 transmitter
Serial Communications Interface 1 (SCI1) Module
9-25
SCI1 Control Registers
Bit 0
RXENA. SCI1 Receive Enable. When this bit is set, received characters are transferred into RXBUF, and the RXRDY flag is set. When cleared, this bit prevents received characters from being transferred into the receiver buffer (RXBUF), and no receiver interrupts are generated. However, the receiver shift register continues to assemble characters. As a result, if RXENA is set during the reception of a character, the complete character is transferred into RXBUF. 0 = Disables SCI1 receiver 1 = Enables SCI1 receive
9-26
SCI1 Control Registers
9.8.3
Baud Select Registers (BAUD MSB and BAUD LSB)
The BAUD MSB and BAUD LSB registers store the value used to generate the bit rate. The SCI1 uses the combined 16-bit value, BAUD REG, of the baud select registers to set the SCI1 clock frequency as follows: SCICLK frequency = SYSCLK / [(BAUD Reg + 1) or BAUD REG where BAUD REG = The 16-bit value in the baud select registers. For example, if the SYSCLK frequency is 5 MHz, the maximum internal SCICLK frequency would be [5 MHz / 2] or 2.5 MHz. SYSCLK ) 1 + 2(SCICLK) 2]
-
For asynchronous mode communication, data is transmitted and received at the rate of one bit for each 16 SCICLK periods. For isosynchronous mode communication, data is transmitted and received at the rate of one bit for each SCICLK period.
The asynchronous and isosynchronous bit rates are calculated as follows: Asynchronous Baud = SYSCLK / [(BAUD REG + 1) Isosynchronous Baud = SYSCLK / [(BAUD REG + 1)
Baud Select Register (BAUD MSB) [Memory Address 1052h]
32] 2]
Bit #
P052
7
BAUDF (MSB) RW-0
6
BAUDE RW-0
5
BAUDD RW-0
4
BAUDC RW-0
3
BAUDB RW-0
2
BAUDA RW-0
1
BAUD9 RW-0
0
BAUD8 RW-0
Baud Select Register (BAUD LSB) [Memory Address 1053h]
Bit #
P053
7
BAUD7 RW-0
6
BAUD6 RW-0
5
BAUD5 RW-0
4
BAUD4 RW-0
3
BAUD3 RW-0
2
BAUD2 RW-0
1
BAUD1 RW-0
0
BAUD0 (LSB) RW-0
R = Read, W = Write, -n = Value of the bit after the register is reset
Serial Communications Interface 1 (SCI1) Module
9-27
SCI1 Control Registers
9.8.4
SCI Transmitter Interrupt Control and Status Register (TXCTL)
The TXCTL register contains the transmitter interrupt enable bit, the transmitter ready flag, and the transmitter empty flag. The status flags are updated each time a compete character is transmitted.
SCI Transmitter Interrupt Control and Status Register (TXCTL) [Memory Address 1054h]
Bit #
P054
7
TXRDY R-1
6
TX EMPTY R-1
5
--
4
--
3
--
2
--
1
--
0
SCI TX INT ENA RW-0
R = Read, W = Write, -n = Value of the bit after the register is reset
Bit 7
TXRDY. SCI1 Transmitter Ready. The TXRDY bit is set by the transmitter to indicate that TXBUF is ready to receive another character. The bit is automatically cleared when a character is loaded into TXBUF. This flag asserts a transmitter interrupt if the interrupt enable bit SCI TX INT ENA (TXCTL.0) is set. TXRDY is a read-only flag. It is set to 1 by an SCI SW RESET (SCICTL.5) or by a system reset. 0 = TXBUF is full. 1 = TXBUF is ready to receive a character.
Bit 6
TX EMPTY. SCI1 Transmitter Empty. This bit indicates the status of the transmitter-shift register and the TXBUF register. TX EMPTY is set to 1 by an SCI SW RESET or by a system reset. 0 = The CPU has written data to the TXBUF register; the data has not been completely transmitted. 1 = TXBUF and TXSHF registers are empty.
Bits 5-1 Bit 0
Reserved. Read data is indeterminate. SCI TX INT ENA. SCI1 Transmitter Ready Interrupt Enable. This bit controls the ability of the TXRDY bit to request an interrupt but does not prevent the TXRDY bit from being set. The SCI TX INT ENA bit (TXCTL.0) is set to 0 by a system reset. 0 = Disables SCI TXRDY interrupt 1 = Enables SCI TXRDY interrupt
9-28
SCI1 Control Registers
9.8.5
SCI Receiver Interrupt Control and Status Register (RXCTL)
The RXCTL register contains one interrupt enable bit and seven receiver status flags (two of which can generate interrupt requests). The status flags are updated each time a complete character is transferred to the RXBUF and are cleared each time RXBUF is read.
SCI Receiver Interrupt Control and Status Register (RXCTL) [Memory Address 1055h]
Bit #
P055
7
RX ERROR R-0
6
RXRDY R-0
5
BRKDT R-0
4
FE R-0
3
OE R-0
2
PE R-0
1
RXWAKE R-0
0
SCI RX INT ENA RW-0
R = Read, W = Write, -n = Value of the bit after the register is reset
Bit 7
RX ERROR. SCI1 Receiver Error Flag. The RX ERROR flag indicates that at least one of the error flags (bits 5-2 - BRKDT, FE, OE, PE) in the RXCTL register is set. It is a logical OR of the parity, overrun, framing error, and break detect flags. The bit can be used for fast error condition checking during the interrupt service routine because a negative value of the status register indicates that an error condition has occurred. This error flag cannot be cleared directly but is cleared when no individual error flags are set. This bit is cleared by an SCI SW RESET, by a system reset, or by reading RXBUF. 0 = No error flag set 1 = Error flag(s) set
Bit 6
RXRDY. SCI1 Receiver Ready. The receiver sets this bit to indicate that RXBUF is ready with a new character and clears the bit when the character is read. A receiver interrupt is generated if the SCI RX INT ENA bit is a 1. RXRDY is reset by an SCI1 SW RESET (SCICTL.5) or by a system reset.
Bit 5
BRKDT. SCI1 Break Detect Flag. The SCI1 sets this bit when a break condition occurs. A break condition occurs when the SCIRXD line remains continuously low for at least 10 bits, beginning after a missing first stop bit. The occurrence of a break causes a receiver interrupt to be generated if the SCI RX INT ENA bit is a 1, but it does not cause the receiver buffer to be loaded. A BRKDT interrupt can occur, even if the receiver SLEEP bit is set to 1. 0 = No break condition occurred 1 = Break condition occurred. Set RX ERROR bit BRKDT is cleared by an SCI1 SW RESET or by a system reset. It is not cleared by receipt of a character after the break is detected. To receive more characSerial Communications Interface 1 (SCI1) Module
9-29
SCI1 Control Registers
ters, the SCI1 must be reset by toggling the SCI SW RESET bit or by a system reset. Bit 4 FE. SCI1 Framing Error Flag. The SCI1 sets this bit when it doesn't find an expected stop bit. Only the first stop bit is checked. The missing stop bit indicates that synchronization with the start bit has been lost and that the character is incorrectly framed. It is reset by an SCI1 SW RESET, by a system reset, or by reading RXBUF. 0 = No framing error detected 1 = Framing error detected. Set RX ERROR bit Bit 3. OE. SCI1 Overrun Error Flag. The SCI1 sets this bit when a character is transferred into RXBUF before the previous character has been read out. The previous character is overwritten and lost. The OE flag is reset by an SCI1 SW RESET, by a system reset, or by reading RXBUF. 0 = No Overrun error detected 1 = Overrun error detected. Set RX ERROR bit Bit 2 PE. SCI1 Parity Error Flag. This flag bit is set when a character is received with a mismatch between the number of 1s and its parity bit (SCICCR.6 selects parity). The parity checker includes the address bit in the calculation. If parity generation and detection are not enabled, the PE flag is disabled and read as 0. The PE bit is reset by an SCI1 SW RESET, by a system reset, or by reading RXBUF. 0 = No parity error or parity is disabled. 1 = Parity error detected. Set RX ERROR bit Bit 1 RXWAKE. Receiver Wake-up Detect. The SCI1 sets this bit when a receiver wake-up condition is detected. In the address bit multiprocessor mode (SCICCR.3 = 1), RXWAKE reflects the value of the address bit for the character contained in RXBUF. In the idle line multiprocessor mode, RXWAKE is set if an idle SCIRXD line is detected. RXWAKE, a read-only flag, (SCICCR.3 = 0) is cleared by transfer of the first byte after the address byte to RXBUF, by reading the address character in RXBUF, by an SCI SW RESET, or by a system reset. Bit 0 SCI RX INT ENA. SCI1 Receiver Interrupt Enable. The SCI RX INT ENA bit controls the ability of the RXRDY and the BRKDT bits to request an interrupt but does not prevent these flags from being set. 0 = Disables RXRDY/BRKDT interrupt 1 = Enables RXRDY/BRKDT interrupt
9-30
SCI1 Control Registers
9.8.6
SCI Receiver Data Buffer Register (RXBUF)
The RXBUF register contains current data from the receiver shift register. RXBUF is cleared by a system reset.
SCI Receiver Data Buffer Register (RXBUF) [Memory Address 1057h]
Bit #
P057
7
RXDT7 R-0
6
RXDT6 R-0
5
RXDT5 R-0
4
RXDT4 R-0
3
RXDT3 R-0
2
RXDT2 R-0
1
RXDT1 R-0
0
RXDT0 R-0
R = Read, -n = Value of the bit after the register is reset
9.8.7
SCI Transmitter Data Buffer Register (TXBUF)
The TXBUF register is a read/write register that stores data bits to be transmitted by SCITX. Data written to TXBUF are right-justified because the leftmost bits are ignored for characters less than eight bits long.
SCI Transmit Data Buffer Register (TXBUF) [Memory Address 1059h]
Bit #
P059
7
TXDT7 RW-0
6
TXDT6 RW-0
5
TXDT5 RW-0
4
TXDT4 RW-0
3
TXDT3 RW-0
2
TXDT2 RW-0
1
TXDT1 RW-0
0
TXDT0 RW-0
R = Read, W = Write, -n = Value of the bit after the register is reset
Serial Communications Interface 1 (SCI1) Module
9-31
SCI1 Control Registers
9.8.8
SCI Port Control Register 1 (SCIPC1)
The SCIPC1 register controls the SCICLK pin functions.
SCI Port Control Register 1 (SCIPC1) [Memory Address 105Dh]
Bit #
P05D
7
--
6
--
5
--
4
--
3
SCICLK DATA IN R-0
2
SCICLK DATA OUT RW-0
1
SCICLK FUNCTION RW-0
0
SCICLK DATA DIR RW-0
R = Read, W = Write, -n = Value of the bit after the register is reset
Bits 7-4 Bit 3
Reserved. Read data is indeterminate. SCICLK DATA IN. The SCICLK DATA IN bit contains the current value on the SCICLK pin.
Bit 2
SCICLK DATA OUT. This bit contains the data to be output on the SCICLK pin if the following conditions are met:
- Pin SCICLK is a general-purpose I/O. - Pin SCICLK's data direction is defined as output.
Bit 1
SCICLK FUNCTION. This bit defines the function of the SCICLK pin. 0 = Pin SCICLK is a general-purpose digital I/O pin. 1 = Pin SCICLK is the SCI serial clock pin.
BIT 0
SCICLK DATA DIR. SCICLK Data Direction. This bit determines the data direction on the SCICLK pin if SCICLK has been configured as a general-purpose I/O pin. 0 = Pin SCICLK is a general-purpose input pin. 1 = Pin SCICLK is a general-purpose output pin.
9-32
SCI1 Control Registers
9.8.9
SCI Port Control Register 2 (SCIPC2)
The SCIPC2 register controls the SCIRXD and SCITXD pin functions.
SCI Port Control Register 2 (SCIPC2) [Memory Address 105Eh]
Bit #
P05E
7
SCITXD DATA IN R-0
6
SCITXD DATA OUT RW-0
5
SCITXD FUNCTION RW-0
4
SCITXD DATA DIR RW-0
3
SCIRXD DATA IN R-0
2
SCIRXD DATA OUT RW-0
1
SCIRXD FUNCTION RW-0
0
SCIRXD DATA DIR RW-0
R = Read, W = Write, -n = Value of the bit after the register is reset
Bit 7
SCITXD DATA IN. This bit contains the current value on the SCITXD pin.
Bit 6
SCITXD DATA OUT. This bit contains the data to be output on the SCITXD pin if the following conditions are met:
- Pin SCITXD has been defined as a general-purpose I/O pin. - Pin SCITXD's data direction has been defined as output.
Bit 5
SCITXD FUNCTION. This bit defines the function of the SCITXD pin. 0 = Pin SCITXD is a general-purpose digital I/O pin. 1 = Pin SCITXD is the SCI1 transmit pin.
Bit 4
SCITXD DATA DIR. SCITXD Data Direction. This bit determines the data direction on the SCITXD pin if SCITXD has been defined as a general-purpose I/O pin. 0 = Pin SCITXD is a general-purpose input pin. 1 = Pin SCITXD is a general-purpose output pin.
Bit 3
SCIRXD DATA IN. This bit contains the current value on the SCIRXD pin.
Bit 2
SCIRXD DATA OUT. This bit contains the data to be output on the SCIRXD pin if the following conditions are met:
- Pin SCIRXD has been defined as a general-purpose I/O pin. - Pin SCIRXD's data direction has been defined as output.
Serial Communications Interface 1 (SCI1) Module
9-33
SCI1 Control Registers
Bit 1
SCIRXD FUNCTION. This bit defines the function of the SCIRXD pin. 0 = Pin SCIRXD is a general-purpose digital I/O pin. 1 = Pin SCIRXD is the SCI1 receiver pin.
Bit 0
SCIRXD DATA DIR. SCIRXD Data Direction. This bit determines the data direction on the SCIRXD pin if SCIRXD has been defined as a general-purpose I/O pin. 0 = Pin SCIRXD is a general-purpose input pin. 1 = Pin SCIRXD is a general-purpose output pin.
9-34
SCI1 Control Registers
9.8.10 SCI Priority Control Register (SCIPRI)
The SCIPRI register contains the receiver and transmitter interrupt priority select bits. This register is read-only during normal operation but can be written to in the privilege mode.
SCI Priority Control Register (SCIPRI) [Memory Address 105Fh]
Bit #
P05F
7
SCI STEST RP-0
6
SCITX PRIORITY RP-0
5
SCIRX PRIORITY RP-0
4
SCI ESPEN RP-0
3
--
2
--
1
--
0
--
R = Read, W = Privilege write only, -n = Value of the bit after the register is reset
Bit 7
SCI STEST. SCI1 STEST. This bit must be cleared to ensure proper operation.
Bit 6
SCI TX PRIORITY. SCI1 Transmitter Interrupt Priority Select. This bit assigns the interrupt priority level of the SCI1 transmitter interrupts. 0 = Transmitter interrupts are level 1 (high-priority) requests. 1 = Transmitter interrupts are level 2 (low-priority) requests.
Bit 5
SCI RX PRIORITY. SCI1 Receiver Interrupt Priority Select. This bit assigns the interrupt priority level of the SCI1 receiver interrupts. 0 = Receiver interrupts are level 1 (high-priority) requests. 1 = Receiver interrupts are level 2 (low-priority) requests.
Bit 4
SCI ESPEN. SCI1 Emulator Suspend Enable. This bit has no effect except when you are using the XDS emulator to debug a program. Then, this bit determines how the SCI1 operates when the program is suspended by an action such as a hardware or software breakpoint. 0 = When the emulator is suspended, the SCI1 continues to work until the current transmit or receive sequence is complete. 1 = When the emulator is suspended, the SCI1 state machine is frozen so that the state of the SCI1 can be examined at the point that the emulator was suspended.
Bits 3-0
Reserved. Read data is indeterminate.
Serial Communications Interface 1 (SCI1) Module
9-35
9-36
Chapter 10
Serial Communications Interface 2 (SCI2) Module
The SCI is described in Chapter 9 (SCI1: 3 I/O pins, asynchronous and isosynchronous modes) and Chapter 10 (SCI2: 2 I/O pins, asynchronous mode). This chapter describes SCI2 and covers the following topics:
Topic
Page
10.1 SCI2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 10.2 Programmable Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6 10.3 Multiprocessor Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7 10.4 Asynchronous Communication Mode . . . . . . . . . . . . . . . . . . . . . . . . . 10-10 10.5 Port Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12 10.6 Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13 10.7 Initialization Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-14 10.8 SCI2 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-17
10-1
SCI2 Overview
10.1 SCI2 Overview
The serial communications interface (SCI2) module is a programmable I/O port that facilitates digital communications between the TMS370 device and other asynchronous peripherals and uses the standard NRZ (nonreturn to zero) format. The SCI2 transmits and receives serial data, one bit at a time, at a programmable bit rate. Both the SCI2 receiver and transmitter are doublebuffered and have their own separate enable and interrupt bits. They can be operated independently or simultaneously in the full duplex mode. The SCI2 module is available only in the TMS370CxCx family.
10.1.1 Physical Description
The two-pin SCI2 module, shown in Figure 10-1 key features:
-
Two I/O pins:
J J
SCIRXD (SCI2 receive data input) SCITXD (SCI2 transmit data output)
Asynchronous communications format with programmable bit rates to over 65,000 different speed through a 16-bit baud select register
H H
Range at 5 MHz SYSCLK --3 bits/s to 156 kbits/s Number of bit rates--64K
Programmable data word length from 1 to 8 bits Programmable stop bits of either 1 or 2 bits in length Error detection flags that ensure data integrity:
10-2
J J J J J J
Parity error Overrun error Framing error Break detect
Two wake-up multiprocessor modes that can be used with either communications format: Idle line wake-up Address bit wake-up
Full duplex operation Separate transmitter and receiver interrupts for polled or interrupt-driven operation Double-buffered receive and transmit functions
SCI2 Overview
Frame format and mode PARITY EVEN/ ODD ENABLE
Separate enable bits for the transmitter and receiver NRZ (nonreturn to zero) format
Figure 10-1. SCI2 Block Diagram
TXWAKE SCICTL.3 1 WUT 8 TX EMPTY TXCTL.6 TXENA
TXBUF.7 - 0
Transmit data buffer reg. SCI TX Interrupt SCI TX TXRDY INT ENA TXCTL.7
SCITX PRIORITY SCIPRI.6 Level 1 Int
0 1
SCICCR.6 SCICCR.5
TXCTL.0
Level 2 Int
External pin connections
SCIPC2.7 - 4
SCITXD SCITXD
BAUD MSB. 7 - 0
Baud rate MSbyte reg.
TXSHF Reg. CLOCK ENA
SCICTL.1
SYSCLK
SCICTL.4 BAUD LSB. 7 - 0
Baud rate LSbyte reg. RXSHF reg. RXWAKE RXCTL.1 RXENA RX ERROR SCIRXD SCIRX PRIORITY SCIPRI.5 Level 1 Int
0 1
SCIPC2.3 - 0
SCIRXD
SCI RX interrupt RXRDY RXCTL.6 BRKDT RXCTL.5 SCI RX INT ENA
SCICTL.0
8
RXCTL.7
ERR
RXCTL.4-2
FE OE PE Receive data buffer reg.
RXCTL.0
Level 2 Int
RXBUF.7 - 0
10.1.2 Architecture
The major elements of the full-duplex SCI2 are shown in Figure 10-1 and include:
-
A transmitter (SCITX)
J J
TXBUF -- the transmitter buffer register that contains data, written by the CPU, to be transmitted TXSHF -- the transmitter shift register that is loaded from TXBUF and shifts data onto the SCITXD pin, one bit at a time
Serial Communications Interface 2 (SCI2) Module
10-3
SCI2 Overview
-
A receiver (SCIRX)
J J
RXSHF -- the receiver shift register that shifts data in from the SCIRXD pin, one bit at a time RXBUF -- the receiver buffer register that contains data that is to be read by the CPU and that is received from remote processor and loaded from RXSHF
-
A programmable baud generator Memory-mapped control and status registers
The SCI2 receiver and transmitter can operate independently and simultaneously.
10.1.3 Communications Modes and Multiprocessing Modes
The SCI2 offers the following universal asynchronous receiver/transmitter (UART) communications modes for interfacing with many popular peripherals. Asynchronous mode (discussed in subsection 9.4.1 on page 9-12) requires two lines to interface with many standard devices such as terminals and printers that use RS-232-C formats. This mode can be programmed to contain:
-
1 start bit, 1 to 8 data bits, An even/odd parity bit or no parity bit, and 1 or 2 stop bits.
The SCI2 also has two multiprocessor modes: the idle line multiprocessor mode (see subsection 10.3.1) and the address bit multiprocessor mode (see subsection 10.3.2). These modes allow efficient data transfer between multiple processors.
10.1.4 Control Registers
The SCI2 control registers are located at addresses 1050h to 105Fh and occupy peripheral file frame 5. The function of each location is shown in Table 12-1.
10-4
SCI2 Overview
Table 10-1. SCI2 Memory Map
Peripheral File Location P050 Register Symbol SCICCR See Page 10-18
Name SCI Communication Control Register SCI Control Register
Description Defines the character format, protocol, and asynchronous enable used by the SCI2. Controls the RX/TX enable, TXWAKE and SLEEP functions, internal clock enable, and the SCI2 software reset. Stores the data required to generate the bit rate.
P051
SCICTL
10-20
P052 P053 P054
BAUD MSB BAUD LSB TXCTL
Baud Select MSbyte Register Baud Select LSbyte Register SCI Transmitter Interrupt Control and Status Register SCI Receiver Interrupt Control and Status Register Reserved
10-22
Contains the transmitter interrupt enable, the transmitter ready flag, and the transmitter empty flag. Contains one interrupt enable bit and seven receiver status flags.
10-23
P055 P056 P057 P058 P059 P05A-P05D P05E P05F
RXCTL
10-24
RXBUF
SCI Receiver Data Buffer Reserved
Contains the current data from the receiver shift register.
10-26
TXBUF
SCI Transmit Data Buffer Reserved
Stores data bits to be transmitted by the SCITX.
10-26
SCIPC2 SCIPRI
SCI Port Control Register 2 SCI Interrupt Priority Control Register
Controls the SCIRXD and SCITXD pin functions. Contains the receiver and transmitter interrupt priority select bits.
10-27 10-29
Serial Communications Interface 2 (SCI2) Module
10-5
Programmable Data Format
10.2 Programmable Data Format
SCI2 data, both receive and transmit, is in NRZ (nonreturn to zero) format, which means that in active state the SCIRX and SCITX lines will be held logic one. The NRZ data format is illustrated in Figure 10-2 and consists of:
-
1 start bit 1 to 8 data bits An even/odd parity bit (optional) 1 or 2 stop bits An extra bit to distinguish addresses from data (address bit mode only).
The basic unit of data is called a character and is 1 to 8 bits in length. Each character of data is formatted with a start bit, 1 or 2 stop bits, and optional parity and address bits. A character of data along with its formatting information is called a frame and is shown in Figure 10-2.
Figure 10-2. SCI2 Data Formats
Start LSB 2 3 4 5 6 7 MSB Parity Stop
Idle Line Mode (Normal Nonmultiprocessor Communications)
Start
LSB
2
3
4
5
6
7
MSB
Addr/ Data
Parity
Stop
Address Bit Mode
To program the data format, use the SCICCR register (described in subsection 10.8.1 on page 10-18). The bits that you use to program the data format are shown in Table 10-2:
Table 10-2. Programming the Data Format Using SCICCR
Bit Name SCI CHAR0-2 Designation SCICCR.0-2 Function Select the character (data) length (1 to 8 bits). Refer to the bit listings on page 10-18 and 10-19 for additional information. Enables the parity function if set to 1 or disables the parity function if cleared to 0. If parity is enabled, selects odd parity if cleared to 0 or even parity if set to 1. Determines the number of stop bits transmitted--one stop bit if cleared to 0 or two stop bits if set to 1.
PARITY ENABLE EVEN/ODD PARITY STOP BITS
SCICCR.5 SCICCR.6 SCICCR.7
10-6
Multiprocessor Communications
10.3 Multiprocessor Communications
The multiprocessor communication format allows one processor to efficiently send blocks of data to other processors on the same serial link. You can have only one talker on a serial line at a time. The first byte of a block of information that the talker sends contains an address byte that is read by all listeners. Only listeners with the correct address can be interrupted by the data bytes that follow the address byte. The listeners with an incorrect address remain uninterrupted until the next address byte. All processors on the serial link set their SLEEP bit (SCICTL.2) to 1 so that they are interrupted only when the address byte is detected. When a processor reads a block address that corresponds to the CPU's device address as set by software, your program must clear the SLEEP bit to enable the SCI2 to generate an interrupt on receipt of each data byte. Although the receiver still operates when the SLEEP bit is 1, it does not set RXRDY, RXINT, or the error status bits to 1 unless the address byte is detected and the address bit in the received frame is a 1. The SCI2 does not alter the SLEEP bit; your software must alter the SLEEP bit. A processor recognizes an address byte according to the multiprocessor mode:
-
The idle line mode leaves a quiet space before the address byte. This mode does not have an extra address/data bit and is more efficient than the address bit mode in handling blocks that contain more than 10 bytes of data. The address bit mode adds an extra bit into every byte to distinguish addresses from data. This mode is more efficient in handling many small blocks of data because, unlike the idle mode, it does not have to wait between blocks of data. However, at high transmit speeds, the program is not fast enough to avoid a 10-bit idle in the transmission stream.
You can select the multiprocessor mode via the ADDRESS/IDLE WUP bit (SCICCR.3). Both modes use the TXWAKE flag bit (SCICTL.3), RXWAKE flag bit (RXCTL.1), and the SLEEP flag bit (SCICTL.2) to control the SCITX and SCIRX features of these modes. In both multiprocessor modes, the sequence is: 1) The SCI2 port wakes up (requests an interrupt) at the start of a block and reads the first frame that contains the destination address. 2) A software routine is entered through the interrupt which checks the RXWAKE flag bit. If the RXWAKE flag bit is a 1, the incoming byte is an
Serial Communications Interface 2 (SCI2) Module
10-7
Multiprocessor Communications
address (otherwise the byte is data), and the incoming byte is checked against the device address byte stored in memory. 3) If the check shows that the block is addressed to the microcontroller, the CPU clears the SLEEP bit and reads the rest of the block; if not, the software routine exits with the SLEEP bit still set and does not receive SCI2 interrupts until the next block start.
10.3.1 Idle Line Multiprocessor Mode
In the idle line multiprocessor mode (ADDRESS/IDLE WUP bit = 0), blocks are separated by having a longer idle time between the blocks than between frames in the blocks. An idle time of 10 or more bits after a frame indicates the start of a new block. The idle line multiprocessor communication format is shown in Figure 10-3. (The ADDRESS/IDLE WUP bit is SCICCR.3.)
Figure 10-3. Idle Line Multiprocessor Communication Format
Blocks of Frames
RXD/TXD EXPANDED Last data
Sp
St
Addr
Sp St
Data
Sp
St Last data
Sp
St
Addr Sp
Idle period greater than 10 bits
First frame within block is address, it follows idle period of 10 bits or more
Frame within Idle period block less than 10 bits
Idle period greater than 10 bits
Note:
In the figure, "St" = start and "Sp" = stop
There are two ways to send a block start signal.
-
The first method is to deliberately leave an idle time of 10 bits or more by delaying the time between the transmission of the last frame of data in the previous block and the transmission of the address frame of the new block. In the second method, the SCI2 port uses the TXWAKE bit (SCICTL.3) to send an idle time of exactly 11 bits. Therefore, the serial communications line is not idle any longer than necessary.
Associated with the TXWAKE bit is the wake-up temporary or WUT flag bit. WUT is an internal flag, double buffered with TXWAKE. When TXSHF is loaded form TXBUF, WUT is loaded from TXWAKE, and the TXWAKE bit is cleared to 0. This arrangement is shown in Figure 10-4.
Figure 10-4. Double-Buffered WUT and TXSHF
TXWAKE TXBUF
WUT
TXSHF
10-8
Multiprocessor Communications
To send out a block start signal of exactly one frame time: 1) Write a 1 to the TXWAKE bit. 2) Write a data word (don't care) to TXBUF. (The first data word written is suppressed while the block start signal is sent out, and ignored after that.) When TXSHF is free again, TXBUF's contents are shifted to TXSHF, the TXWAKE value is shifted to WUT, and then the TXWAKE bit is cleared. If TXWAKE bit was set to a 1, the start, data, and parity bits are replaced by an idle period of 11 bits transmitted following the last stop bit of the previous frame. 3) Write an address value to the TXBUF. The receiver operates regardless of the SLEEP bit. The receiver does not set RXRDY, RXINT, or the error status bits until an address frame is detected.
10.3.2 Address Bit Multiprocessor Mode
In the address bit mode (ADDRESS/IDLE WUP bit = 1), frames have an extra bit, called an address bit, that immediately follows the last data bit. The address bit is set to 1 in the first frame of the block and to 0 in all other frames. The idle period timing is irrelevant. (The ADDRESS/IDLE WUP bit is SCICCR.3.) The TXWAKE bit sets the address bit. In SCITX, when the TXBUF and TXWAKE are loaded into TXSHF and WUT, TXWAKE is reset to 0, and WUT is the value of the address bit of the current frame. Thus, to send an address, set the TXWAKE bit to a 1 and write the appropriate address value to the TXBUF. When this address value is transferred to TXSHF and shifted out, its address bit is sent as a 1, which flags the other processors on the serial link to read the address. Since TXSHF and WUT are both double-buffered, TXBUF and TXWAKE can be written to immediately after TXSHF and WUT are loaded. To transmit nonaddress frames in the block, leave the TXWAKE bit at 0.
Figure 10-5. Address Bit Multiprocessor Communication Format
Blocks of Frames
RXD/TXD EXPANDED Last data
1 Sp
St
Addr
1 Sp St Data
0
Sp
St Last data 0
Sp
St Addr 1 Sp
Idle period is of no significance.
First frame within block is address. The ADDR/DATA bit is 1.
ADDR/DATA Idle period is of no sigbit is nificance. 0 for frame within block.
Idle period is of no significance.
Note:
In the figure, "St" = start and "Sp" = stop
Serial Communications Interface 2 (SCI2) Module
10-9
Asynchronous Communications Mode
10.4 Asynchronous Communications Mode
The SCI2 asynchronous communication mode uses either single-line (oneway) or two-line (two-way) communications. In this mode, the frame consists of a start bit, one to eight data bits, an optional even/odd parity bit, and one or two stop bits. The receiver begins operation on receipt of a valid start bit. A valid start bit consists of eight consecutive zero bits. If any bit is not zero, then the processor starts over and begins looking for another start bit.
10.4.1 Receiver Signals in the Communication Mode
Figure 10-6 illustrates receiver signal timing that assumes these conditions:
RXENA
Address bit wake-up mode (address bit would not appear in idle line mode) 6 bits per character
Figure 10-6. SCI2 RX Signals in Communications Modes
A RXRDY B SCIRXD Pin STR 0 1 2 3 4 5 C D E STR 0 1 2 F
AD PA
STP
A) RX ENA goes high to enable the receiver. B) Data arrives on the SCIRXD pin; start bit detected. C) RXRDY goes high to signal that a new character has been received; data is shifted to RXBUF; an interrupt is requested. D) The program reads the RXBUF register; RXRDY is automatically cleared. E) The next byte of data arrives on the SCIRXD pin; start bit detected, then cleared. F) RX ENA goes low to disable the receiver; data continues to be assembled in the RXSHF register but is not transferred to the RXBUF register.
10.4.2 Transmitter Signals in the Communication Mode
Figure 10-7 illustrates transmitter signal timing that assumes these conditions:
10-10
Address bit wake-up mode (address bit would not appear in idle line mode) 3 bits per character
Asynchronous Communications Mode
Figure 10-7. SCI2 TX Signals in the Communication Mode
TXENA A TX EMPTY TXRDY BC SCITXD Pin D E G F
STR
0
1
2
AD PA STP STR 0
1
2
AD PA
ST
A) TX ENA goes high to enable the transmitter to send data. B) Write to TXBUF; TXBUF is no longer empty. C) SCI transfers data to shift register; TXBUF is ready for new character and requests an interrupt. D) Program writes new character to TXBUF after TXRDY goes high (item C). E) Finished transmitting first character; transfer new character to shift register. F) TX ENA goes low to disable transmitter; SCI finishes transmitting current character. G) Finished transmitting character; TXBUF is empty and ready for new character.
Serial Communications Interface 2 (SCI2) Module
10-11
Port Interrupts
10.5 Port Interrupts
The SCI2 provides independent interrupt requests and vectors for the receiver and transmitter.
-
If the SCI RX INT ENA bit (RXCTL.0) is set, the receiver interrupt is asserted when one of the following events occurs:
J J
The SCI2 receives a complete frame and transfers the data in the RXSHF register to the RXBUF register. This action sets the RXRDY flag (RXCTL.6) and initiates an interrupt. A break detect condition occurs (the SCIRXD is low for 10 bit periods following a stop bit). This action sets the BRKDT flag bit (RXCTL.5) and initiates an interrupt.
-
If the SCI TX INT ENA bit (TXCTL.0) is set, the transmitter interrupt is asserted whenever the data in the TXBUF register is transferred to the TXSHF register, indicating that the CPU can write to the TXBUF; this action sets the TXRDY flag bit (TXCTL.7) and initiates an interrupt.
SCI2 interrupts can be programmed onto different priority levels by the SCI RX PRIORITY (SCIPRI.5) and SCI TX PRIORITY (SCIPRI.6) control bits. When both RX and TX interrupt requests are made on the same level, the receiver always has higher priority than the transmitter; this reduces the possibility of receiver overrun.
10-12
Clock Sources
10.6 Clock Source
The SCI2 port can be driven by an internal or external baud generator. The internally generated serial clock is determined by the TMS370 SYSCLK frequency and the baud select registers. The SCI2 uses the 16-bit value of the baud select registers to select one of 64K different serial clock rates for the asynchronous communication mode in the following manner:
-
Asynchronous Baud = SYSCLK / [(BAUD REG + 1) x 32] BAUD REG = [SYSCLK / (Asynchronous Baud x 32)] - 1
where BAUD REG = The 16-bit value in the baud select registers. Refer to Table 10-3.
Table 10-3. Asynchronous Baud Register Values for Common SCI2 Bit Rates
SYSCLK Frequency (MHz) 0.6144 Baud 75 300 600 1200 2400 4800 9600 19200 38400 156000 Baud Reg 255 63 31 15 7 3 1 0 % Error 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 1.8432 Baud Reg 767 191 95 47 23 11 5 2 % Error 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 4.9152 Baud Reg 2047 511 255 127 63 31 15 7 3 % Error 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 5.0 Baud Reg 2082 520 259 129 64 32 15 7 3 0 % Error 0.02 -0.03 0.16 0.16 0.16 -1.38 1.73 1.73 1.73 0.16
Baud Reg = 16-bit baud register value Divide-by-1 clock can only operate from a minimum of 2 MHz SYSCLK to a maximum of 5 MHz SYSCLK.
Serial Communications Interface 2 (SCI2) Module
10-13
Initialization Examples
10.7 Initialization Examples
This section contains two examples that initialize the serial port. In each example, the data is moved to and from the buffers in the interrupt routines. 1) The first example shows a typical RS-232 application that connects to a terminal. 2) The second example illustrates the address bit mode in a multiprocessor application. In both examples, assume that the register mnemonics have been equated (EQU) with the corresponding peripheral-file location. For more examples using the TMS370 SCI, consult Using the TMS370 SPI and SCI Modules Application Report.
10.7.1 RS-232-C Example
This example initializes the transmitter and receiver to accept data at 9600 baud with a format of 8 data bits, 1 stop bit, and even parity.
B9600 HI .EQU .EQU 15 00 ;Value for counter. For 9600 baud ;value = (SYSCLK/32/baud) - 1 = ;(5 MHz/32/9600) - 1 = 15.27 ~ 5 ;1.8 percent error ;Make sure that SCI SW RESET bit is ;clear before writing to the SCI ;configuration registers ;Set TX and RX to high priority ;Set pins for RXD and TXD functions ;Set bit rate for 9600 (MSbyte) ;Set bit rate for 9600 (LSbyte) ;1 stop bit, even parity, enable ;asynchronous, and enable 8 data bits/char ;Enable Rx and Tx, enable internal clock ;Enable TX interrupt ;Enable RX interrupt ;Let the interrupts begin ;Start transmitter by sending null ;character
AND
#01Fh, SCICTL
MOV MOV MOV MOV MOV MOV MOV MOV EINT MOV
#000h,SCIPRI #022h,SCIPC2 #HI,BAUDMSB #B9600,BAUDLSB #077h,SCICCR #033h,SCICTL #001h,TXCTL #001h,RXCTL #00,TXBUF
10-14
Initialization Examples
10.7.2 RS-232-C Multiprocessor Mode Example
This example initializes the transmitter and receiver to accept data at 9600 baud with a format of 8 data bits, 1 stop bit, and even parity. It uses the address bit wake-up mode to implement the multiprocessor protocol.
B9600 HI .EQU .EQU 15 00 ;Value for counter for 9600 baud ;value = (SYSCLK/32/baud) - 1 = ;(5 MHz/32/9600) - 1 = 15.27 ~ 15 ;1.8 percent error ;Set TX and RX to high priority ;Set pins for RXD and TXD functions ;Set bit rate. For 9600 (MSbyte) ;Set bit rate for 9600 (LSbyte) ;1 stop bit, even parity, enable ;asynchronous, and enable 8 data bits/char ;Enable Rx, Tx; RX to sleep, enable ;internal clock ;Enable TX interrupt ;Enable RX interrupt ;Let the interrupts begin ; ;MAIN ROUTINES ; ;Main line routine; set TXWAKE ;wake bit ;Transmit address stored in ADDR ;INTERRUPT ROUTINES ; ;The locations of the SCI transmitter and ;receiver routines, SENDATA and GETDATA, ;need to be stored in the interrupt vector ;table at locations 70F0h and 7FF2h, ;respectively.
MOV MOV MOV MOV MOV MOV MOV MOV EINT
#000h,SCIPRI #022h,SCIPC2 #HI,BAUDMSB #B9600,BAUDLSB #07Fh,SCICCR #037h,SCICTL #001h,TXCTL #001h,RXCTL
SENDADD
OR MOV RTS
#8,SCICTL ADDR,TXBUF
Serial Communications Interface 2 (SCI2) Module
10-15
Initialization Examples
;SCI2 TRANSMITTER INTERRUPT ROUTINE SENDDATA PUSH MOV . . . POP RTI . GETDATA PUSH BTJZ MOV CMP JNE AND JMP ISDATA MOV . . . POP RTI A OUTDATA,TXBUF ;Address has already been sent by ;the SENDADD ;Output character that is ;stored in DATA ; ;Other transmitter code ; ;Restore and exit ;SCI2 RECEIVER INTERRUPT ROUTINE A #2,RXCTL,ISDATA RXBUF,A #MYADDR,A RXEXIT #0FBh,SCICTL RXEXIT RXBUF,INDATA ;Receive a new character ;Is this address or data byte? ;Get new character and clear ;interrupt flag ;Is this my address or ;another processor's address ;Exit if another's; still ;in sleep mode ;If my address get out of sleep mode ;Exit and wait for data ; ;Put incoming data in register ; ;Other receiver code ; ;Restore and exit
A
RXEXIT
A
10-16
SCI2 Control Registers
10.8 SCI2 Control Registers
The SCI2 is controlled and accessed through registers in peripheral file frame 5. These registers are listed in Table 10-4 and described in the following subsections. The bits shown in shaded boxes in Table 10-4 are privilege mode bits; that is, they can only be written to in the privilege mode.
Table 10-4. Peripheral File Frame 5: SCI2 Control Registers
Designation SCICCR ADDR 1050h PF P050
Bit 7
STOP BITS (RW-0) --
Bit 6
EVEN/ODD PARITY (RW-0) -- BAUDE (RW-0) BAUD6 (RW-0) TX EMPTY (R-1) RXRDY (R-0)
Bit 5
PARITY ENABLE (RW-0) SCI SW RESET (RW-0) BAUDD (RW-0) BAUD5 (RW-0) -- BRKDT (R-0)
Bit 4
ASYNC ENABLE (RW-0) CLOCK ENABLE (RW-0) BAUDC (RW-0) BAUD4 (RW-0) -- FE (R-0) Reserved
Bit 3
ADDRESS/ IDLE WUP (RW-0) TXWAKE (RS-0) BAUDB (RW-0) BAUD3 (RW-0) -- OE (R-0)
Bit 2
SCI CHAR2 (RW-0) SLEEP (RW-0) BAUDA (RW-0) BAUD2 (RW-0) -- PE (R-0)
Bit 1
SCI CHAR1 (RW-0) TXENA (RW-0) BAUD9 (RW-0) BAUD1 (RW-0) -- RXWAKE (R-0)
Bit 0
SCI CHAR0 (RW-0) RXENA (RW-0) BAUD8 (RW-0) BAUD0 (LSB) (RW-0) SCI TX INT ENA (RW-0) SCI RX INT ENA (RW-0)
SCICTL
1051h
P051
BAUD MSB
1052h
P052
BAUDF (MSB) (RW-0) BAUD7 (RW-0) TXRDY (R-1) RX ERROR (R-0)
BAUD LSB
1053h
P053
TXCTL
1054h
P054
RXCTL
1055h
P055
1056h RXBUF 1057h 1058h TXBUF 1059h 105Ah 105Bh 105Ch 105Dh SCIPC2 105Eh
P056 P057 P058 P059 P05A P05B P05C P05D P05E SCITXD DATA IN (R-0) SCI STEST (RP-0) SCITXD DATA OUT (RW-0) SCITX PRIORITY (RP-0) SCITXD FUNCTION (RW-0) SCIRX PRIORITY (RP-0) TXDT7 (RW-0) TXDT6 (RW-0) TXDT5 (RW-0) RXDT7 (R-0) RXDT6 (R-0) RXDT5 (R-0)
RXDT4 (R-0)
RXDT3 (R-0)
RXDT2 (R-0)
RXDT1 (R-0)
RXDT0 (R-0)
Reserved TXDT4 (RW-0) TXDT3 (RW-0) TXDT2 (RW-0) TXDT1 (RW-0) TXDT0 (RW-0)
Reserved
SCITXD DATA DIR (RW-0) SCI ESPEN (RP-0)
SCIRXD DATA IN (R-0) --
SCIRXD DATA OUT (RW-0) --
SCIRXD FUNCTION (RW-0) --
SCIRXD DATA DIR (RW-0) --
SCIPRI
105Fh
P05F
Serial Communications Interface 2 (SCI2) Module
10-17
SCI2 Control Registers
10.8.1 SCI Communication Control Register (SCICCR)
The SCICCR register defines the character format, protocol, and communications modes used by the SCI2.
SCI Communication Control Register (SCICCR) [Memory Address 1050h]
Bit #
P050
7
STOP BITS RW-0
6
EVEN/ODD PARITY RW-0
5
PARITY ENABLE RW-0
4
ASYNC ENABLE
3
ADDRESS/ IDLE WUP RW-0
2
SCI CHAR2 RW-0
1
SCI CHAR1 RW-0
0
SCI CHAR0 RW-0
R = Read, W = Write, -n = Value of the bit after the register is reset
Bit 7
STOP BITS. SCI2 Number of Stop Bits. This bit determines the number of stop bits transmitted. The receiver checks for one stop bit only. 0 = One stop bit. 1 = Two stop bits.
Bit 6
EVEN/ODD PARITY. SCI2 Parity Enable. If the PARITY ENABLE bit is set, this bit selects odd or even parity (odd or even number of one bits in both transmitted and received characters). 0 = Sets odd parity. 1 = Sets even parity.
Bit 5
PARITY ENABLE. SCI2 Parity Enable. This bit enables or disables the parity function. When parity is enabled during the address bit multiprocessor mode, the address bit is included in the parity calculation. 0 = Disables parity. No parity bit is generated during transmission or expected during reception. 1 = Enables parity.
Bit 4
ASYNC ENABLE. SCI2 Asynchronous Mode Enable. This bit enables the asynchronous mode function. For SCI2 operation, this bit must be written as a 1 when you write to the SCICCR register. 0 = Disables asynchronous mode (SCI2 will not operate). 1 = Enables asynchronous mode (SCI2 operates).
10-18
SCI2 Control Registers
Bit 3
ADDRESS/IDLE WUP. SCI2 Multiprocessor Mode Control Bit. This bit selects the multiprocessor mode. 0 = Selects idle line mode. 1 = Selects address bit mode. The idle line mode is usually used for normal communications because the address bit mode adds an extra bit to the frame; the idle line mode does not add this extra bit and is compatible with RS-232-type communications. Multiprocessor communication is different from the other communications modes because it uses TXWAKE and SLEEP functions.
Bits 2-0
SCI CHAR2-0. SCI2 Character Length Control Bits 2-0. These bits select the SCI2 character (data) bit length, from 1 to 8 bits. Characters of less than 8 bits are right-justified in RXBUF and TXBUF, and are padded with leading 0s in RXBUF. TXBUF need not be padded with leading zeros.
Table 10-5. Character Bit Length
SCI CHAR2 0 0 0 0 1 1 1 1 SCI CHAR1 0 0 1 1 0 0 1 1 SCI CHAR0 0 1 0 1 0 1 0 1 Character Length 1 2 3 4 5 6 7 8
Serial Communications Interface 2 (SCI2) Module
10-19
SCI2 Control Registers
10.8.2 SCI Control Register (SCICTL)
The SCICTL register controls the RX/TX enable, TXWAKE and SLEEP functions, internal clock enable, and the SCI2 software reset.
SCI Control Register (SCICTL) [Memory Address 1051h]
Bit #
P051
7
--
6
--
5
SCI SW RESET RW-0
4
CLOCK ENABLE
3
TXWAKE RS-0
2
SLEEP RW-0
1
TXENA RW-0
0
RXENA RW-0
R = Read, W = Write, S = Set only, -n = Value of the bit after the register is reset
Bits 6-7 Bit 5
Reserved. Read data is indeterminate. SCI SW RESET. SCI2 Software Reset (Active Low). Writing a 0 to this bit initializes the SCI2 state machines and operation flags to the reset condition. All affected logic is held in the reset state until a 1 is written to the SCI SW RESET bit. Thus, after a system reset, you must re-enable the SCI2 by writing a 1 to this bit. This bit must be cleared after a receiver break detect. SCI SW RESET affects the operating flags of the SCI2. This bit does not affect the configuration bits, nor does it put in the reset values. The flags listed in Table 10-6 are set to the values shown when SCI SW RESET is cleared. The operating flags are frozen until the SCI SW RESET bit is set again.
Table 10-6. Flags Affected by SCI SW RESET
SCI Flag TXRDY TXEMPTY RXWAKE PE OE FE BRKDT RXRDY RX ERROR Designation TXCTL.7 TXCTL.6 RXCTL.1 RXCTL.2 RXCTL.3 RXCTL.4 RXCTL.5 RXCTL.6 RXCTL.7 Value After SCI SW RESET 1 1 0 0 0 0 0 0 0
Note: The SCI SW RESET bit must be cleared before the SCI2 configuration registers can be set up or altered. The application program should set up all configuration registers before it sets the SCI SW RESET bit.
10-20
SCI2 Control Registers
Bit 4
CLOCK ENABLE. SCI2 Internal Clock Enable. This bit enables or disables the SCI2 internal clock. For SCI2 operation, this bit must be written as a 1 when you write to the SCICTL register. 0 = Disables SCI2 internal clock (stops SCI2 operation). 1 = Enables SCI2 internal clock (SCI2 operates).
Bit 3
TXWAKE. SCI2 Transmitter Wake-up. The TXWAKE bit controls the transmit features of the multiprocessor communication modes. This bit is cleared only by system reset. The SCI2 hardware clears this bit, once it has been transferred to wake-up temporary (WUT).
Bit 2
SLEEP. SCI2 Sleep. This bit controls the receive features of the multiprocessor communication modes. You must clear this bit to bring the SCI2 out of sleep mode. 0 = Disables sleep mode. 1 = Enables sleep mode.
Bit 1
TXENA. SCI2 Transmit Enable. Data transmission through the SCITXD pin occurs only when this bit is set. If this bit is reset, the transmission is not halted until all the data previously written to TXBUF has been sent. 0 = Disables SCI2 transmitter. 1 = Enables SCI2 transmitter.
Bit 0
RXENA. SCI2 Receive Enable. When this bit is set, received characters are transferred into RXBUF, and the RXRDY flag is set. When cleared, this bit prevents received characters from being transferred into the receiver buffer (RXBUF), and no receiver interrupts are generated. However, the receiver shift register continues to assemble characters. As a result, if RXENA is set during the reception of a character, the complete character is transferred into RXBUF. 0 = Disables SCI2 receiver. 1 = Enables SCI2 receiver.
Serial Communications Interface 2 (SCI2) Module
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SCI2 Control Registers
10.8.3 Baud Select Registers (BAUD MSB and BAUD LSB)
The BAUD MSB and BAUD LSB registers store the data required to generate the bit rate. The asynchronous bit rates are calculated as follows: Asynchronous Baud = SYSCLK/ [(BAUD REG + 1)
Baud Select Register (BAUD MSB) [Memory Address 1052h]
32]
Bit #
P052
7
BAUDF (MSB) RW-0
6
BAUDE RW-0
5
BAUDD RW-0
4
BAUDC RW-0
3
BAUDB RW-0
2
BAUDA RW-0
1
BAUD9 RW-0
0
BAUD8 RW-0
Baud Select Register (BAUD LSB) [Memory Address 1053h]
Bit #
P053
7
BAUD7 RW-0
6
BAUD6 RW-0
5
BAUD5 RW-0
4
BAUD4 RW-0
3
BAUD3 RW-0
2
BAUD2 RW-0
1
BAUD1 RW-0
0
BAUD0 (LSB) RW-0
R = Read, W = Write, -n = Value of the bit after the register is reset
10-22
SCI2 Control Registers
10.8.4 SCI Transmitter Interrupt Control and Status Register (TXCTL)
The TXCTL register contains the transmitter interrupt enable bit, the transmitter ready flag, and the transmitter empty flag. The status flags are updated each time a compete character is transmitted.
SCI Transmitter Interrupt Control and Status Register (TXCTL) [Memory Address 1054h]
Bit #
P054
7
TXRDY R-1
6
TX EMPTY R-1
5
--
4
--
3
--
2
--
1
--
0
SCI TX INT ENA RW-0
R = Read, W = Write, -n = Value of the bit after the register is reset
Bit 7
TXRDY. SCI2 Transmitter Ready. The TXRDY bit is set by the transmitter to indicate that TXBUF is ready to receive another character. The bit is automatically cleared when a character is loaded into TXBUF. This flag asserts a transmitter interrupt if the interrupt enable bit SCI TX INT ENA (TXCTL.0) is set. TXRDY is a read-only flag. It is set to 1 by an SCI SW RESET or by a system reset. 0 = TXBUF is full. 1 = TXBUF is ready to receive a character.
Bit 6
TX EMPTY. SCI2 Transmitter Empty. This bit indicates the status of the transmitter-shift register and the TXBUF register. TX EMPTY is set to 1 by an SCI SW RESET or by a system reset. 0 = The CPU has written data to the TXBUF register; the data has not been completely transmitted. 1 = TXBUF and TXSHF registers are empty.
Bits 5-1 Bit 0
Reserved. Read data is indeterminate. SCI TX INT ENA. SCI2 Transmitter Ready Interrupt Enable. This bit controls the ability of the TXRDY bit to request an interrupt but does not prevent the TXRDY bit from being set. The SCI TX INT ENA bit is set to 0 by a system reset. 0 = Disables SCI TXRDY interrupt. 1 = Enables SCI TXRDY interrupt.
Serial Communications Interface 2 (SCI2) Module
10-23
SCI2 Control Registers
10.8.5 SCI Receiver Interrupt Control and Status Register (RXCTL)
The RXCTL register contains one interrupt enable bit and seven receiver status flags (two of which can generate interrupt requests). The status flags are updated each time a complete character is transferred to the RXBUF. They are cleared each time RXBUF is read.
SCI Receiver Interrupt Control and Status Register (RXCTL) [Memory Address 1055h]
Bit #
P055
7
RX ERROR R-0
6
RXRDY R-0
5
BRKDT R-0
4
FE R-0
3
OE R-0
2
PE R-0
1
RXWAKE R-0
0
SCI RX INT ENA RW-0
R = Read, W = Write, -n = Value of the bit after the register is reset
Bit 7
RX ERROR. SCI2 Receiver Error Flag. The RX ERROR flag indicates that one of the error flags in the receiver status register is set. It is a logical OR of the parity, overrun, framing error, and break detect flags. The bit can be used for fast error condition checking during the interrupt service routine because a negative value of the status register indicates that an error condition has occurred. This error flag cannot be cleared directly but is cleared if no individual error flags are set. This bit is cleared by an SCI SW RESET, by a system reset, or by reading RXBUF.
Bit 6
RXRDY. SCI2 Receiver Ready. The receiver sets this bit to indicate that RXBUF is ready with a new character and clears the bit when the character is read. A receiver interrupt is generated if the SCI RX INT ENA bit is a 1. RXRDY is reset by an SCI SW RESET or by a system reset.
Bit 5
BRKDT. SCI2 Break Detect Flag. The SCI2 sets this bit when a break condition occurs. A break condition occurs when the SCIRXD line remains continuously low for at least 10 bits, beginning after a missing first stop bit. The occurrence of a break causes a receiver interrupt to be generated if the SCI RX INT ENA bit is a 1, but it does not cause the receiver buffer to be loaded. A BRKDT interrupt can occur, even if the receiver SLEEP bit is set to 1. BRKDT is cleared by an SCI SW RESET or by a system reset. It is not cleared by receipt of a character after the break is detected. In order to receive more characters, the SCI2 must by reset through toggling the SCI SW RESET bit or by a system reset. 0 = No parity error or parity is disabled. 1 = Parity error detected.
10-24
SCI2 Control Registers
Bit 4
FE. SCI2 Framing Error Flag. The SCI2 sets this bit when it doesn't find a stop bit that it expects. Only the first stop bit is checked. The missing stop bit indicates that synchronization with the start bit has been lost and that the character is incorrectly framed. It is reset by an SCI SW RESET, by a system reset, or by reading RXBUF. 0 = No framing error detected. 1 = Framing error detected.
Bit 3
OE. SCI2 Overrun Error Flag. The SCI2 sets this bit when a character is transferred into RXBUF before the previous character has been read out. The previous character is overwritten and lost. The OE flag is reset by an SCI SW RESET, by a system reset, or by reading RXBUF. 0 = No Overrun error detected. 1 = Overrun error detected.
Bit 2
PE. SCI2 Parity Error Flag. This flag bit is set when a character is received with a mismatch between the number of 1s and its parity bit. The parity checker includes the address bit in the calculation. If parity generation and detection are not enabled, the PE flag is disabled and read as 0. The PE bit is reset by an SCI SW RESET, by a system reset, or by reading RXBUF.
Bit 1
RXWAKE. Receiver Wake-Up Detect. The SCI2 sets this bit when a receiver wake-up condition is detected. In the address bit multiprocessor mode, RXWAKE reflects the value of the address bit for the character contained in RXBUF. In the idle line multiprocessor mode, RXWAKE is set if an idle SCIRXD line is detected. RXWAKE is a read-only flag. It is cleared by transfer of the first byte after the address byte to RXBUF, by reading the address character in RXBUF, by an SCI SW RESET, or by a system reset.
Bit 0
SCI RX INT ENA. SCI2 Receiver Interrupt Enable. The SCI RX INT ENA bit controls the ability of the RXRDY and the BRKDT bits to request an interrupt but does not prevent these flags from being set. 0 = Disables RXRDY/BRKDT interrupt. 1 = Enables RXRDY/BRKDT interrupt.
Serial Communications Interface 2 (SCI2) Module
10-25
SCI2 Control Registers
10.8.6 SCI Receiver Data Buffer Register (RXBUF)
The RXBUF register contains current data from the receiver shift register. RXBUF is cleared by a system reset.
SCI Receiver Data Buffer Register (RXBUF) [Memory Address 1057h]
Bit #
P057
7
RXDT7 R-0
6
RXDT6 R-0
5
RXDT5 R-0
4
RXDT4 R-0
3
RXDT3 R-0
2
RXDT2 R-0
1
RXDT1 R-0
0
RXDT0 R-0
R = Read, -n = Value of the bit after the register is reset
10.8.7 SCI Transmitter Data Buffer Register (TXBUF)
The TXBUF register is a read/write register that stores data bits to be transmitted by SCITX. Data written to TXBUF must be right-justified because the left-most bits are ignored for characters less than eight bits long.
SCI Transmit Data Buffer Register (TXBUF) [Memory Address 1059h]
Bit #
P059
7
TXDT7 RW-0
6
TXDT6 RW-0
5
TXDT5 RW-0
4
TXDT4 RW-0
3
TXDT3 RW-0
2
TXDT2 RW-0
1
TXDT1 RW-0
0
TXDT0 RW-0
R = Read, W = Write, -n = Value of the bit after the register is reset
10-26
SCI2 Control Registers
10.8.8 SCI Port Control Register 2 (SCIPC2)
The SCIPC2 register controls the SCIRXD and SCITXD pin functions.
SCI Port Control Register 2 (SCIPC2) [Memory Address 105Eh]
Bit #
P05E
7
SCITXD DATA IN R-0
6
SCITXD DATA OUT RW-0
5
SCITXD FUNCTION RW-0
4
SCITXD DATA DIR RW-0
3
SCIRXD DATA IN R-0
2
SCIRXD DATA OUT RW-0
1
SCIRXD FUNCTION RW-0
0
SCIRXD DATA DIR RW-0
R = Read, W = Write, -n = Value of the bit after the register is reset
Bit 7
SCITXD DATA IN. This bit contains the current value on the SCITXD pin.
Bit 6
SCITXD DATA OUT. This bit contains the data to be output on the SCITXD pin if the following conditions are met:
- SCITXD pin has been defined as a general-purpose I/O pin. - SCITXD pin data direction has been defined as output.
Bit 5
SCITXD FUNCTION. This bit defines the function of the SCITXD pin. 0 = SCITXD pin is a general-purpose digital I/O pin. 1 = SCITXD pin is the SCI transmit pin.
Bit 4
SCITXD DATA DIR. SCITXD Data Direction. This bit determines the data direction on the SCITXD pin if SCITXD has been defined as a general-purpose I/O pin. 0 = SCITXD pin is a general-purpose input pin. 1 = SCITXD pin is a general-purpose output pin.
Bit 3
SCIRXD DATA IN. This bit contains the current value on the SCIRXD pin.
Bit 2
SCIRXD DATA OUT. This bit contains the data to be output on the SCIRXD pin if the following conditions are met:
- SCIRXD pin has been defined as a general-purpose I/O pin. - SCIRXD pin data direction has been defined as output.
Serial Communications Interface 2 (SCI2) Module
10-27
SCI2 Control Registers
Bit 1
SCIRXD FUNCTION. This bit defines the function of the SCIRXD pin. 0 = SCIRXD pin is a general-purpose digital I/O pin. 1 = SCIRXD pin is the SCI receiver pin.
Bit 0
SCIRXD DATA DIR. SCIRXD Data Direction. This bit determines the data direction on the SCIRXD pin if SCIRXD has been defined as a general-purpose I/O pin. 0 = Pin SCIRXD is a general-purpose input pin. 1 = Pin SCIRXD is a general-purpose output pin.
10-28
SCI2 Control Registers
10.8.9 SCI Priority Control Register (SCIPRI)
The SCIPRI register contains the receiver and transmitter interrupt priority select bits. This register is read-only during normal operation but can be written to in the privilege mode.
SCI Priority Control Register (SCIPRI) [Memory Address 105Fh]
Bit #
P05F
7
SCI STEST RP-0
6
SCITX PRIORITY RP-0
5
SCIRX PRIORITY RP-0
4
SCI ESPEN RP-0
3
--
2
--
1
--
0
--
R = Read, W = Privilege write only, -n = Value of the bit after the register is reset
Bit 7
SCI STEST. SCI2 STEST. This bit must be cleared to ensure proper operation.
Bit 6
SCI TX PRIORITY. SCI2 Transmitter Interrupt Priority Select. This bit assigns the interrupt priority level of the SCI2 transmitter interrupts. 0 = Transmitter interrupts are level 1 (high-priority) requests. 1 = Transmitter interrupts are level 2 (low-priority) requests.
Bit 5
SCI RX PRIORITY. SCI2 Receiver Interrupt Priority Select. This bit assigns the interrupt priority level of the SCI2 receiver interrupts. 0 = Receiver interrupts are level 1 (high-priority) requests. 1 = Receiver interrupts are level 2 (low-priority) requests.
Bit 4
SCI ESPEN. SCI2 Emulator Suspend Enable. This bit has no effect except when you are using the XDS emulator to debug a program. Then, this bit determines how the SCI2 operates when the program is suspended by an action such as a hardware or software breakpoint. 0 = When the emulator is suspended, the SCI2 continues to work until the current transmit or receive sequence is complete. 1 = When the emulator is suspended, the SCI2 state machine is frozen so that the state of the SCI2 can be examined at the point that the emulator was suspended.
Bits 3-0
Reserved. Read data is indeterminate.
Serial Communications Interface 2 (SCI2) Module
10-29
10-30
Running Title--Attribute Reference
Chapter 11
Serial Peripheral Interface (SPI) Module
This chapter discusses the architecture and programming of the serial peripheral interface module and covers the following topics:
Topic
Page
11.1 SPI Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 11.2 Communications Between the Master and the Slave . . . . . . . . . . . . 11-5 11.3 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6 11.4 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8 11.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9 11.6 Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10 11.7 Initialization Upon Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11 11.8 SPI Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12 11.9 SPI Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13
Chapter Title--Attribute Reference
11-1
SPI Overview
11.1 SPI Overview
The SPI module is a high-speed synchronous serial I/O port that allows a serial bit stream of programmed length (one to eight bits) to be shifted into and out of the device at a programmed bit-transfer rate. The SPI is normally used for communications between the microcontroller and external peripherals or another microcontroller. Typical applications include external I/O or peripheral expansion using devices such as shift registers, display drivers, and A/D converters. Multiprocessor communications are also supported by the master/ slave operation of the SPI.
11.1.1 Physical Description
The SPI module, as shown in Figure 11-1, consists of:
-
Three I/O pins:
J J J
SPISIMO--SPI slave in, master out SPISOMI--SPI slave out, master in SPICLK--SPI clock
SPIBUF--the buffer register that contains the data received from the network that is ready for the CPU to read SPIDAT--the data shift register that serves as the transmit/receive shift register State control logic Memory-mapped control and status registers
11-2
SPI Overview
Figure 11-1.SPI Block Diagram
SPIBUF.7-0
SPIBUF buffer register RECEIVER OVERRUN
SPICTL.7
SPIPRI.6
8 SPI INT FLAG
SPICTL.0
LeveI 1 INT 0 1
SPICTL.6
SPIINT ENA
External pin connections
Level 2 INT
SPIDAT data register
SPIPC2.7-4
SPISIMO
SPIDAT.7-0
SPICTL.1 SPIPC2.3-0
TALK SPISOMI
State control
SPI CHAR
SPICCR.2-0
2 System Clock 1 0
MASTER/SLAVE
SPICTL.2 SPIPC1.3-0
SPICCR.5-3
5 4 3
SPICCR.6
CLOCK POLARITY
SPICLK
SPI BIT RATE The diagram is shown in slave mode.
Serial Peripheral Interface (SPI) Module
11-3
SPI Overview
11.1.2 Control Registers
The SPI control registers are located at addresses 1030h to 103Fh and occupy peripheral file frame 3. The function of each location is shown in Table 11-1.
Table 11-1. SPI Memory Map
Peripheral File Location P030 P031 P032-P036 P037 P038 P039 P03A-P03C P03D P03E P03F SPIPC1 SPIPC2 SPIPRI SPIDAT SPIBUF Symbol SPICCR SPICTL
Name SPI Configuration Control Register SPI Operation Control Register Reserved Serial Input Buffer Reserved Serial Data Register Reserved SPI Port Control Register 1 SPI Port Control Register 2 SPI Interrupt Priority Control Register Controls the SPICLK pin functions. Controls the SPISOMI and SPISIMO pin functions. Selects the interrupt priority level of the SPI interrupt. Serves as the transmit/receive shift register. Contains the data received from the network that is ready for the CPU to read. Description Controls the setup of the SPI for operation. Controls data transmission, the SPI's ability to generate interrupts, and the operating mode (slave or master).
11-4
Communications Between the Master and the Slave
11.2 Communications Between the Master and the Slave
Figure 11-2 shows a typical connection of the SPI for communications between two microcontrollers: the master and the slave. The master initiates data transfer by sending the SPICLK signal. For both the slave and the master, data is shifted out of the shift registers on one edge of the clock and latched into the shift register on the opposite clock edge. As a result, both controllers send and receive data at the same time. The application software determines whether the data is meaningful or dummy data. There are three possible cases for data transmission:
-
Master sends data, and slave sends dummy data Master sends data, and slave sends data Master sends dummy data, and slave sends data
The master can initiate data transfer at any time because it controls the SPICLK. However, the software protocol determines how the master detects when the slave is ready to broadcast data.
Figure 11-2.SPI Master/Slave Connection
SPI master (MASTER/SLAVE = 1) SIMO Slave in/ Master out SPI slave (MASTER/SLAVE = 0) SIMO
SPIBUF.7-0
Serial input buffer (SPIBUF)
SPIBUF.7-0
Serial input buffer (SPIBUF)
Shift register (SPIDAT) MSB
SOMI LSB SPICLK
Slave out/ Master in Serial clock
SOMI MSB SPICLK
Shift register (SPIDAT)
SPIDAT.7-0
Processor 1
SPIDAT.7-0
Processor 2
LSB
Note: SIMO = Slave In, Master Out; SOMI = Slave Out, Master In
Serial Peripheral Interface (SPI) Module
11-5
Operating Modes
11.3 Operating Modes
The MASTER/SLAVE bit (SPICTL.2) selects the operating mode and the source of SPICLK. The SPI module can operate as a master or a slave.
11.3.1 Master Mode
In the master mode (MASTER/SLAVE = 1), the SPI provides the serial clock on the SPICLK pin for the entire serial communications network. Data is output on the SPISIMO pin on the first SPICLK edge and latched from the SPISOMI pin on the opposite edge of SPICLK. The SPI BIT RATE0-2 bits of the SPICCR register determine the bit transfer rate for the network, both transmit and receive. Eight data transfer rates can be selected by these control bits as shown in Table 11-2 on page 11-10. Data written to the SPIDAT register initiates data transmission on the SPISIMO pin, MSB first. Simultaneously, received data is shifted in the SPISOMI pin into the SPIDAT register. When the selected number of bits have been transmitted, the data is transferred to the SPIBUF (double-buffered receiver) for reading by the CPU to permit new transactions to take place. Data is shifted into the SPI MSB first. It is stored right-justified in SPIBUF. To initiate a character transaction when the SPI is operating as a master, data must be written to the SPIDAT. When the specified number of data bits have been shifted through the SPIDAT register, the following events occur:
-
The SPI INT FLAG bit (SPICTL.6) is set, The SPIDAT register contents transfer to the SPIBUF register, and If the SPI INT ENA bit (SPICTL.1) is set to 1, an interrupt is asserted.
Writing to the SPIDAT register before transmission is complete corrupts the current transmission.
11.3.2 Slave Mode
In the slave mode (MASTER/SLAVE = 0), data shifts out on the SPISOMI pin and in on the SPISIMO pin. The SPICLK pin is used as the input for the serial shift clock, which is supplied from the external network master. The transfer rate is defined by this clock. The SPICLK input frequency should be no greater than the SYSCLK frequency divided by 8.
11-6
Operating Modes
Data written to the SPIDAT register is transmitted to the network when the SPICLK is received from the network master. To receive data, the SPI waits for the network master to send SPICLK and then shifts the data on the SPISIMO pin into the SPIDAT register. If data is to be transmitted by the slave simultaneously, it must be written to the SPIDAT register before the beginning of SPICLK. When the TALK bit (SPICTL.1) is cleared, data transmission is disabled, and the output line is put into a high-impedance state. This allows many slave devices to be tied together on the network, but only one slave at a time is allowed to talk.
Serial Peripheral Interface (SPI) Module
11-7
Data Format
11.4 Data Format
Three character-length bits (SPICCR.2-0) specify the number of bits in the data character (1-8 bits). This information directs the state control logic to count the number of bits received or transmitted to determine when a complete character has been processed. For characters with fewer than 8 bits:
-
Data must be written left-justified to the SPIDAT register. Data must be read back right-justified from the SPIBUF register. The SPIBUF register contains the most recently received character, rightjustified, plus any bits that remain from previous transmission(s) and have been shifted to the MSB position.
Example 11-1. Register Values in an SPI Character-Write Operation
For example: If the character length = 1 bit, and the value written into SPIDAT = 07Bh, then:
SPIDAT (before transmission) 0 1 1 1 1 0 1 1
SPIDAT (after transmission) (transmitted) 0 1 1 1 1 0 1 1 x
(received)
SPIBUF (after transmission) 1
Note:
1
1
1
0
1
1
x
x = 1 if SOMI is held high; x = 0 if SOMI is held low
11-8
Interrupts
11.5 Interrupts
The interrupt for the SPI is controlled by bits in two registers:
-
The SPI INT ENA bit (SPICTL.0), when set, allows assertion of an interrupt request when an interrupt condition occurs. The SPI PRIORITY bit (SPIPRI.6) determines whether SPI interrupts are level 1 or level 2 priority requests.
-
When a complete character has been shifted into or out of the SPIBUF register, the SPI interrupt flag (SPI INT FLAG) of the SCICTL register is set, and an interrupt is generated if enabled by SPI INT ENA bit (SPICTL.0). The interrupt flag remains set until it is cleared by one of the following four events: The CPU reads the SPI receiver buffer (SPIBUF), The CPU enters the halt or standby mode with an IDLE instruction, Software sets the SPI SW RESET bit (SPICCR.7), or A system reset occurs.
An interrupt request must be explicitly cleared by one of the four methods listed above to avoid generating another interrupt. An interrupt request can be temporarily disabled by clearing the SPI INT ENA bit. However, unless the SPI INT FLAG itself is cleared, the interrupt request will be reasserted when the enable bit (SPI INT ENA) is again set to 1. The priority level of the SPI interrupt is specified by the SPI PRIORITY bit (SPIPRI.6). If SPI PRIORITY = 0, a level 1 priority interrupt is generated. If SPI PRIORITY = 1, a level 2 priority interrupt is generated.
-
When the SPI INT FLAG bit is set, a character has been placed into the SPIBUF register and is ready to be read. If the CPU does not read the character by the time the next complete character has been received, the new character is written into the SPIBUF, and the RECEIVER OVERRUN bit (SPICTL.7) is set. This indicates that the last character of data has been overwritten with new data before the previous character could be read.
Serial Peripheral Interface (SPI) Module
11-9
Clock Sources
11.6 Clock Sources
The CLOCK POLARITY bit (SPICCR.6) selects the active edge of the clock, either rising or falling.
-
In the slave mode, the SPI clock is received from an external source and can be no greater than the SYSCLK frequency divided by 8. In the master mode, the SPI clock is generated by the SPI and is output on the SPICLK pin.
The SPI BIT RATE0-2 bits (SPICCR.5-3) determine the bit transfer rate for sending and receiving the data. This transfer rate is defined by: SPI BAUD RATE = SYSCLK / (2 x 2b) where b = bit rate in SPICCR.5 -3 (range 0 -7). Table 11-2 shows the bit rates for common crystal frequencies versus the SPI bit rate values.
Table 11-2. Common SPI Bit Rates
SPI Value 0 1 2 3 4 5 6 7 Divide by 2 4 8 16 32 64 128 256 SYSCLK Frequency (MHz) 0.5 250 125 62.5 31.25 15.625 7.8125 3.90625 1.953125 1.25 625 312.5 156.25 78.125 39.0625 19.53125 9.765625 4.882813 2.5 1250 625 312.5 156.25 78.125 39.0625 19.53125 9.765625 3 1500 750 375 187.5 93.75 46.875 23.4375 11.71875 5 2500 1250 625 312.5 156.25 78.125 39.0625 19.53125 Bit Rate kbps kbps kbps kbps kbps kbps kbps kbps
Divide-by-1 clock can only operate from a minimum of 2 MHz SYSCLK to a maximum of 5 MHz SYSCLK. kbps = kilobits/second.
11-10
Initialization Upon Reset
11.7 Initialization Upon Reset
A system reset forces the SPI peripheral module into the following default configuration:
-
The unit is configured as a slave module (MASTER/SLAVE = 0). The transmit capability is disabled (TALK = 0). Data is latched at the input on the falling edge of SPICLK. Character length is assumed to be 1 bit. The SPI interrupts are disabled. Data in the SPI data register is set to 00h.
To change this SPI configuration: Set the SPI SW RESET bit (SPICCR.7) to 1, Make any changes that you want in the configuration described above, and Clear the SPI SW RESET bit.
Using the above procedure prevents unwanted and unforeseen events from occurring during or as a result of a mode change.
Serial Peripheral Interface (SPI) Module
11-11
SPI Example
11.8 SPI Example
The following timing diagrams illustrate an SPI data transfer between two TMS370 devices using a character length of five bits. The lettered notes following the first diagram are keyed to the letter labels in the diagram.
5 Bits per Character Master SPI int flag Slave SPI int flag AB SPI SOMI from slave 7 SPI SIMO from master 7 Clock polarity = 0 Clock polarity = 1 A. B. C. D. E. F. G. H. I. Slave writes 0D0h to SPIDAT and waits for the master to shift out the data. Master writes 058h to SPIDAT, which starts the transmission procedure. First byte is finished and sets the interrupt flags. Slave reads 0Bh from its SPIBUF register (right justified). Slave writes 04Ch to SPIDAT and waits for the master to shift out the data. Master writes 06Ch to SPIDAT, which starts the transmission procedure. Master reads 01Ah from the SPIBUF register (right justified). Second byte is finished and sets the interrupt flags. Master receives 89h, and the slave receives a 8Dh (right justified). Caution should be taken because the SPIBUF register not only contains the five new data (right justified) received, but also the three LSBs of data left over from the previous SPIBUF register (value written to SPInDAT). The user's software routine should mask-off the unused bits. 6 5 4 3 7 6 5 4 3 6 5 4 3 7 6 5 4 3 C DEF G H I
Signals Connecting to Master Processor SPI SIMO output SPI SOMI input sampled SPICLK out (clock polarity = 0) SPICLK out (clock polarity = 1) Bit 4 Bit 3 Bit 2
11-12
SPI Control Registers
11.9 SPI Control Registers
The SPI is controlled and accessed through registers in peripheral file frame 3. These registers are listed in Figure 11-3 and described in the following subsections. The bits shown in shaded boxes in Figure 11-3 are privilege mode bits; that is, they can be written to only in the privilege mode.
Figure 11-3.Peripheral File Frame 3: SPI Control Registers
Designation SPICCR ADDR 1030h PF P030 Bit 7 SPI SW RESET (RW-0) RECEIVER OVERRUN (R-0) Bit 6 CLOCK POLARITY (RW-0) SPI INTFLAG (R-0) Bit 5 SPI BIT RATE2 (RW-0) -- Bit 4 SPI BIT RATE1 (RW-0) -- Bit 3 SPI BIT RATE0 (RW-0) -- Bit 2 SPI CHAR2 (RW-0) MASTER/ SLAVE (RW-0) Bit 1 SPI CHAR1 (RW-0) TALK (RW-0) Bit 0 SPI CHAR0 (RW-0) SPI INT ENA (RW-0)
SPICTL
1031h
P031
1032h to 1036h SPIBUF 1037h 1038h SPIDAT 1039h 103Ah to 103Ch SPIPC1 103Dh
P032 to P036 P037 P038 P039 P03A to P03C P03D -- -- SPISIMO DATA OUT (RW-0) SPI PRIORITY (RP-0) -- SPISIMO FUNCTION (RW-0) SPI ESPEN (RP-0) -- SPISIMO DATA DIR (RW-0) -- SPICLK DATA IN (R-0) SPISOMI DATA IN (R-0) -- SPICLK DATA OUT (RW-0) SPISOMI DATA OUT (RW-0) -- SPICLK FUNCTION (RW-0) SPISOMI FUNCTION (RW-0) -- SPICLK DATA DIR (RW-0) SPISOMI DATA DIR (RW-0) -- Reserved SDAT7 (RW-0) SDAT6 (RW-0) SDAT5 (RW-0) RCVD7 (R-0) RCVD6 (R-0) RCVD5 (R-0) RCVD4 (R-0) RCVD3 (R-0) RCVD2 (R-0) RCVD1 (R-0) RCVD0 (R-0) Reserved
Reserved SDAT4 (RW-0) SDAT3 (RW-0) SDAT2 (RW-0) SDAT1 (RW-0) SDAT0 (RW-0)
SPIPC2
103Eh
P03E
SPISIMO DATA IN (R-0) SPI STEST (RP-0)
SPIPRI
103Fh
P03F
Serial Peripheral Interface (SPI) Module
11-13
SPI Control Registers
11.9.1 SPI Configuration Control Register (SPICCR)
The SPICCR register controls the setup of the SPI for operation.
SPI Configuration Control Register (SPICCR) [Memory Address 1030h]
Bit #
P030
7
SPI SW RESET RW-0
6
CLOCK POLARITY RW-0
5
SPI BIT RATE2 RW-0
4
SPI BIT RATE1 RW-0
3
SPI BIT RATE0 RW-0
2
SPI CHAR2 RW-0
1
SPI CHAR1 RW-0
0
SPI CHAR0 RW-0
R = Read, W = Write, -n = Value of the bit after the register is reset
Bit 7
- Writing a 1 to this bit initializes the SPI circuitry and operating flags to the
SPI SW RESET. SPI Software Reset.
- When a 0 is written to SPI SW RESET, the SPI is ready to transmit or re-
reset condition. Specifically, the RECEIVER OVERRUN and SPI INT FLAG flags are cleared. The SPI configuration remains unchanged. If the module is operating as a master, the SPICLK output level returns to its inactive level. ceive the next character. A character written to the transmitter when SPI SW RESET is a 1 will not be shifted out when the SPI SW RESET bit is cleared. A new character must be written to the serial data register. Use this bit to change any configuration bits (see Section 11.7).
Bit 6
CLOCK POLARITY. Shift Clock Polarity. The CLOCK POLARITY bit controls the polarity of the SPICLK signal. 0 = The inactive level is low; data is output by the rising edge of SPICLK; input data is latched by the falling edge of SPICLK. 1 = The inactive level is high; data is output by the falling edge of SPICLK; input data is latched by the rising edge of SPICLK.
11-14
SPI Control Registers
Bits 5-3
SPI BIT RATE2-0. SPI Bit Rate Control Bits 2-0. These bits determine the bit transfer rate if the SPI is the network master. Eight data transfer rates (each a function of the system clock) can be selected. The system clock is divided by an 8-bit, free-running prescaler from which eight taps are available for use as the shift clock. One data bit is shifted per SPICLK cycle.
SPI BIT RATE2 SPI BIT RATE1 SPI BIT RATE0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 SPI Clock Frequency SYSCLK/2 SYSCLK/4 SYSCLK/8 SYSCLK/16 SYSCLK/32 SYSCLK/64 SYSCLK/128 SYSCLK/256
If the SPI is a network slave, then the module receives a clock on the SPICLK pin from
the network master, and these bits have no effect on SPICLK. The frequency of the input clock should be no greater than the SYSCLK frequency divided by 8.
Bits 2-0
SPI CHAR2-0. Character Length Control Bits 2-0. These three bits determine the number of bits to be shifted in or out as a single character during one shift sequence. The value of these bits is represented in the following table.
SPI CHAR2 0 0 0 0 1 1 1 1 SPI CHAR1 0 0 1 1 0 0 1 1 SPI CHAR0 0 1 0 1 0 1 0 1 Character Length 1 2 3 4 5 6 7 8
Serial Peripheral Interface (SPI) Module
11-15
SPI Control Registers
11.9.2 SPI Operation Control Register (SPICTL)
The SPI operation control register controls data transmission, the SPI's ability to generate interrupts, and the operating mode (slave or master).
SPI Operation Control Register (SPICTL) [Memory Address 1031h]
Bit #
P031
7
RECEIVER OVERRUN R-0
6
SPI INT FLAG R-0
5
--
4
--
3
--
2
MASTER/ SLAVE RW-0
1
TALK RW-0
0
SPI INT ENA RW-0
R = Read, W = Write, -n = Value of the bit after the register is reset
Bit 7
RECEIVER OVERRUN. This bit is a read-only flag that the SPI hardware sets when a receive or transmit operation completes before the previous character is read from the receive buffer. It indicates that the last received character has been overwritten and, therefore, has been lost. RECEIVER OVERRUN is cleared when the receiver buffer is read. It is also cleared by SPI SW RESET or by a system reset.
Bit 6
SPI INT FLAG. Serial Peripheral Interrupt Flag. The SPI hardware sets this bit to indicate that it has completed sending or receiving the last bit and is ready to be serviced. A character received is placed in the receiver buffer at the time the SPI INT FLAG bit is set. The SPI INT FLAG is cleared when the receiver buffer is read. It is also cleared by an SPI software reset (SPI SW RESET) or by a system reset.
Bits 5-3 Bit 2
Reserved. Read data is indeterminate. MASTER/SLAVE. SPI Network Mode Control. This bit determines whether the SPI is a network master or slave. During reset initialization, the SPI is automatically configured as a slave. 0 = SPI configured as a slave 1 = SPI configured as a master
Bit 1
TALK. Master/Slave Transmit Enable. This bit disables data transmission (master or slave) by placing the serial data output in a high-impedance state. TALK is cleared (disabled) by a system reset. 0 = Disables transmission; if not programmed as a general-purpose I/O pin, the SPI serial output is in a high-impedance state. 1 = Enables transmission
11-16
SPI Control Registers
Bit 0
SPI INT ENA. SPI Interrupt Enable. This bit controls the SPI's ability to generate an interrupt. The SPI INT FLAG is unaffected by this bit. 0 = Disables interrupt 1 = Enables interrupt
Serial Peripheral Interface (SPI) Module
11-17
SPI Control Registers
11.9.3 Serial Input Buffer (SPIBUF)
The SPIBUF register contains the data received from the network ready for the CPU to read.
Serial Input Buffer (SPIBUF) [Memory Address 1037h]
Bit #
P037
7
RCVD7 (MSB) R-0
6
RCVD6 R-0
5
RCVD5 R-0
4
RCVD4 R-0
3
RCVD3 R-0
2
RCVD2 R-0
1
RCVD1 R-0
0
RCVD0 (LSB) R-0
R = Read, -n = Value of the bit after the register is reset
Once the serial data register has received the complete character, the character is then transferred to the SPIBUF register, where it can be read. The SPI INT FLAG bit (SPICTL.6) is set to indicate that the data is available when the received character is transferred. Since data is shifted into the SPI most significant bit first, it is stored, right-justified, in the SPIBUF while the previous LSB(s) data occupies the remaining MSB(s). The user's software routine should mask off the unused bits.
11.9.4 Serial Data Register (SPIDAT)
The SPIDAT register is the transmit/receive shift register. Data written to the SPIDAT is shifted out on subsequent SPICLK cycles. For every bit shifted out of the SPI, a bit is shifted into the other end of the shift register.
Serial Data Register (SPIDAT) [Memory Address 1039h]
Bit #
P039
7
SDAT7 RW-0
6
SDAT6 RW-0
5
SDAT5 RW-0
4
SDAT4 RW-0
3
SDAT3 RW-0
2
SDAT2 RW-0
1
SDAT1 RW-0
0
SDAT0 RW-0
R = Read, W = Write, -n = Value of the bit after the register is reset Writing to the SPIDAT performs two functions: It provides data to be output on the serial output pin if the TALK bit is set. It initiates a transaction when the SPI is operating as a master.
-
A receiver sequence is initiated when dummy data is written to the register. Since the data is not hardware justified for characters that are shorter than eight bits, transmit data must be written in left-justified form and received data read in right-justified form.
11-18
SPI Control Registers
11.9.5 SPI Port Control Registers (SPIPC1 and SPIPC2)
Two port control registers (SPIPC1 and SPIPC2) allow you to control all of the functions for a SPI port pin in one write cycle. Each module pin is controlled by a nibble in one of the SPIPCs.
11.9.5.1
SPI Port Control Register 1 (SPIPC1)
This register controls the SPICLK pin.
Port Control Register 1 (SPIPC1) [Memory Address 103Dh]
Bit #
P03D
7
--
6
--
5
--
4
--
3
SPICLK DATA IN R-0
2
SPICLK DATA OUT RW-0
1
SPICLK FUNCTION RW-0
0
SPICLK DATA DIR RW-0
R = Read, W = Write, -n = Value of the bit after the register is reset
Bits 7-4
Reserved. Read data is indeterminate. Note: SPICLK Pin in Slave Mode
The SPICLK pin always functions as the SPICLK input pin in the slave mode (i.e., SPICTL.2 = 0), even if SPICLK FUNCTION = 0. Bit 3 SPICLK DATA IN. SPICLK Pin Port Data In. This bit contains the current value on the SPICLK pin, regardless of the mode. A write to this bit has no effect. Bit 2 SPICLK DATA OUT. SPICLK Port Data Out. This bit contains the data to be output on the SPICLK pin if both the following conditions are met:
-
SPICLK pin has been defined as a general-purpose I/O pin. SPICLK pin data direction has been defined as output.
Bit 1
SPICLK FUNCTION. SPICLK Pin Function Select. This bit defines the function of the SPICLK pin. 0 = SPICLK pin is a general-purpose digital I/O pin. 1 = SPICLK pin contains the SPI clock.
Bit 0
SPICLK DATA DIR. SPICLK Data Direction. This bit determines the data direction on the SPICLK pin if SPICLK has been defined as a general-purpose I/O pin. 0 = SPICLK pin is a general-purpose input pin. 1 = SPICLK pin is a general-purpose output pin.
Serial Peripheral Interface (SPI) Module
11-19
SPI Control Registers
11.9.5.2
SPI Port Control Register 2 (SPIPC2)
The SPIPC2 register controls the SPISOMI and SPISIMO pin functions.
Port Control Register 2 (SPIPC2) [Memory Address 103Eh]
Bit #
P03E
7
SPISIMO DATA IN R-0
6
SPISIMO DATA OUT RW-0
5
SPISIMO FUNCTION RW-0
4
SPISIMO DATA DIR RW-0
3
SPISOMI DATA IN R-0
2
SPISOMI DATA OUT RW-0
1
SPISOMI FUNCTION RW-0
0
SPISOMI DATA DIR RW-0
R = Read, W = Write, -n = Value of the bit after the register is reset
Bit 7
SPISIMO DATA IN. SPISIMO Pin Data In. This bit contains the current value on the SPISIMO pin, regardless of the mode. A write to this bit has no effect.
Bit 6
SPISIMO DATA OUT. SPISIMO Pin Data Out. This bit contains the data to be output on the SPISIMO pin if both the following conditions are met:
- SPISIMO pin has been defined as a general-purpose I/O pin. - SPISIMO pin data direction has been defined as output.
Bit 5 SPISIMO FUNCTION. SPISIMO Pin Function Select. This bit defines the function of the SPISIMO pin. 0 = SPISIMO pin is a general-purpose digital I/O pin. 1 = SPISIMO pin contains the SPI data. Bit 4 SPISIMO DATA DIR. SPISIMO Data Direction.
This bit determines the data direction on the SPISIMO pin if SPISIMO has been defined as a general-purpose I/O pin. 0 = SPISIMO pin is a general-purpose input pin. 1 = SPISIMO pin is a general-purpose output pin. Bit 3 SPISOMI DATA IN. SPISOMI Pin Data In. This bit contains the current value on the SPISOMI pin, regardless of the mode. A write to this bit has no effect. Bit 2 SPISOMI DATA OUT. SPISOMI Pin Data Out. This bit contains the data to be output on the SPISOMI pin if both the following conditions are met:
- The SPISOMI pin has been defined as a general-purpose I/O pin. - The SPISOMI pin data direction has been defined as output.
11-20
SPI Control Registers
Bit 1
SPISOMI FUNCTION. SPISOMI Pin Function Select. This bit defines the function of the SPISOMI pin. When SPISOMI is an input and SPISOMI FUNCTION and SPISOMI DATA DIR are disabled, SPICLK still clocks the internal circuitry. 0 = SPISOMI pin is a general-purpose digital I/O pin. 1 = SPISOMI pin contains the SPI data.
Bit 0
SPISOMI DATA DIR. SPISOMI Data Direction. This bit determines the data direction on the SPISOMI pin if SPISOMI has been defined as a general-purpose I/O pin. 0 = SPISOMI pin is a general-purpose input pin. 1 = SPISOMI pin is a general-purpose output pin.
Serial Peripheral Interface (SPI) Module
11-21
SPI Control Registers
11.9.6 SPI Interrupt Priority Control Register (SPIPRI)
The SPIPRI register selects the interrupt priority level of the SPI interrupt. The register is read only during normal operation but can be written to in the privilege mode.
SPI Interrupt Priority Control Register (SPIPRI) [Memory Address 103Fh]
Bit #
P03F
7
SPI STEST RP-0
6
SPI PRIORITY RP-0
5
SPI ESPEN RP-0
4
--
3
--
2
--
1
--
0
--
R = Read, P = Privilege write only, -n = Value of the bit after the register is reset
Bit 7
SPI STEST. SPI STEST. This bit must be cleared to ensure proper operation.
Bit 6
SPI PRIORITY. Interrupt Priority Select. 0 = Interrupts are level 1 (high-priority) requests. 1 = Interrupts are level 2 (low-priority) requests.
Bit 5
SPI ESPEN. Emulator Suspend Enable. This bit has no effect, except when you are using the XDS emulator to debug a program; then, this bit determines SPI operation when the program is suspended by an action such as a hardware or software breakpoint. 0 = When the emulator is suspended, the SPI continues to work until the current transmit/receive sequence is complete. 1 = When the emulator is suspended, the the state of the SPI is frozen so that it can be examined at the point that the emulator was suspended.
Bits 4-0
Reserved. Read data is indeterminate.
11-22
Running Title--Attribute Reference
Chapter 12
Analog-To-Digital Converter 1 (ADC1) Module
The TMS370 family contains three different ADC modules (ADC1, ADC2, and ADC3). This chapter discusses the architecture and programming of the analog-to-digital converter 1 (ADC1) module and covers the following topics:
Topic
Page
12.1 Analog-to-Digital Converter 1 (ADC1) Overview . . . . . . . . . . . . . . . . 12-2 12.2 ADC1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5 12.3 ADC1 Example Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9 12.4 ADC1 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-11
Chapter Title--Attribute Reference
12-1
Analog-to-Digital Converter 1 (ACD1) Overview
12.1 Analog-to-Digital Converter 1 (ADC1) Overview
The analog-to-digital converter 1 module is an 8-bit, successive approximation converter with internal sample-and-hold circuitry. The module has eight multiplexed analog input channels that allow the processor to convert the voltage levels from up to eight different sources. The ADC1 module is available in the following families: TMS370Cx32, TMS370Cx36, TMS370Cx4x, TMS370Cx5x, TMS370Cx6x, TMS370Cx7x, and TMS370CxBx.
12.1.1 Physical Description
The ADC1 module, shown in Figure 12-1, consists of:
-
The ADC1 conversion block An ADC1 input selector (INPUT)
J J
For all family devices (except the TMS370Cx4x 40-pin device), eight analog input channels (AN0-AN7), any of which can be software-configured as digital inputs (E0-E7) if not needed as analog channels For the TMS370Cx4x 40-pin device, four analog input channels (AN2, AN3, AN6, and AN7), any of which can be software-configured as digital inputs (E2, E3, E6, and E7) if not needed as analog channels
-
A +VREF input selector (+VREF)
J J
For all family devices except the TMS370Cx4x 40-pin device, eight positive input voltage references (AN1-AN7 and VCC3). For the TMS370Cx4x 40-pin device, five positive input voltage references (AN2, AN3, AN6, AN7, and VCC3)
-
The ADDATA register, which contains the digital value of a completed conversion ADC1 module control registers
The input channels can be routed through either the channel selector or the positive voltage selector. The ADC1 converter then processes these signals and puts the result in the ADDATA register. The ADC1 interrupt circuit informs the rest of the system when a conversion is completed.
For the TMS370Cx4x 40 pin device, the ADC1 module has four multiplexed analog input channels and five positive input voltage references.
12-2
Analog-to-Digital Converter 1 (ACD1) Overview
Figure 12-1. Analog-to-Digital Converter1 (ADC1) Block Diagram
External pin connections
Port E input ENA 0
Port E data AN 0
ADENA.0
AN0
Port E input ENA 1
ADIN.0
2
1
0
SAMPLE START
CONVERT START
ADCTL.2 - 0
Port E data AN 1 AD INPUT SELECT
ADCTL.6
ADCTL.7
ADENA.1
AN1 Port E input ENA 2
ADIN.1
ADENA.2 AN2
Port E input ENA 3
Port E data AN 2
ADIN.2
ADENA.3 AN3
Port E input ENA 4
Port E data AN 3 ADIN.3
AD
ADENA.4 AN4
Port E input ENA 5
Port E data AN 4 ADIN.4
ADDATA.7 - 0
ADC data register AD READY
ADENA.5 AN5
Port E input ENA 6
Port E data AN 5 ADIN.5
ADSTAT.2
AD PRIORITY
Port E data AN 6
ADENA.6 AN6
Port E input ENA 7
ADIN.6
5
4
3
ADPRI.6 Level 1 Int 0
1 Level 2 Int
ADCTL.5 - 3
Port E data AN 7 REF VOLTS SELECT
ADENA.7 AN7 VCC3 VSS3
ADIN.7
AD INT FLAG
ADSTAT.1 ADSTAT.0
AD INT ENA These pins are not implemented in the TMS370Cx4x 40-pin device.
Analog-to-Digital Converter 1 (ADC1) Module
12-3
Analog-to-Digital Converter 1 (ACD1) Overview
12.1.2 Control Registers
The ADC1 control registers are located at addresses 1070h to 107Fh and occupy peripheral file frame 7, as shown in Table 12-1.
Table 12-1. ADC1 Memory Map
Peripheral File Location P070 Symbol
ADCTL
Name Analog Control Register
Description Controls the input selection, reference voltage selection, sample start, and conversion start. Indicates the converter and interrupt status. Contains the digital result of the last ADC1 conversion.
P071 P072 P073-P07C P07D
ADSTAT
Analog Status and Interrupt Register Analog Conversion Data Register Reserved
ADDATA
ADIN
Analog Port E Data Input Register
Contains digital input data when one or more of the AN0-AN7 pins are used as digital ports. Controls the function of the AN0-AN7 pins. Selects the interrupt priority level of the ADC1 interrupt.
P07E P07F
ADENA
Analog Port E Input Enable Register Analog Interrupt Priority Register
ADPRI
12-4
ADC1 Operation
12.2 ADC1 Operation
The following subsections describe the functions and options of the ADC1 module.
12.2.1 Input/Output Pins
The ADC1 module contains up to ten pins.
-
The TMS370Cx32, TMS370Cx36, 44-pin TMS370Cx4x, TMS370Cx5x, TMS370Cx6x, TMS370Cx7x, and TMS370CxBx use 10 pins: eight analog channels, VCC3, and VSS3. These pins are described below:
J J J
Eight (AN0-AN7) of the ten pins are analog channels and can be individually configured as general-purpose input pins (E0-E7) when not used as analog inputs. Seven (AN1-AN7) of the eight analog channels are also available as the positive input voltage reference. This feature allows a weighted measurement or ratio of one channel to another. The analog voltage supply pins, VCC3 and VSS3, isolate the ADC1 module from digital switching noise that can be present on the other power supply pins. This isolation provides a more accurate conversion.
-
The TMS370Cx4x 40-pin device uses 6 pins: four analog channels, VCC3, and VSS3. These pins are described below:
J J J
Four (AN2, AN3, AN6, and AN7) of the six pins are analog channels and can be individually configured as general-purpose input pins when not used as analog inputs. Four (AN2, AN3, AN6, and AN7) analog channels are also available as the positive input voltage reference. This feature allows a weighted measurement or ratio of one channel to another. The analog voltage supply pins, VCC3 and VSS3, isolate the ADC1 module from digital switching noise that can be present on the other power supply pins. This isolation provides a more accurate conversion. To further reduce noise and produce a more accurate conversion, you should run the power to the VCC3 and VSS3 pins on separate conductors from the other power lines. Additionally, the power conductors to the VCC3 and VSS3 should be as short as possible, and the two lines should be properly decoupled. Use other standard noise-reduction techniques to help provide a more accurate conversion.
Analog-to-Digital Converter 1 (ADC1) Module
12-5
ADC1 Operation
Note that you can select the VREF pin to be either VCC3 or one of the analog input channels AN1 to AN7. VCC3 must provide power to the ADC1 module even if it does not provide the voltage reference. A channel configured as the +VREF for one conversion can be changed to an analog input channel for the next conversion.
12.2.2 Sampling Time
The application program controls the length of the sample time, which provides the flexibility to optimize the conversion process for both high- and lowimpedance sources. The program should wait 1 s for each kilohm of source output impedance or a minimum of 1 s for low-impedance sources.
12.2.3 ADC1 Conversion
The digital result of the conversion process is given in the following formula. digital result = 255 x input voltage reference voltage
The conversion process requires 164 SYSCLK cycles and results in a conversion time of 32.8 microseconds at 5 MHz SYSCLK. A maximum of 27,600 conversions per second is possible at 5 MHz SYSCLK, including setting up the conversion, sampling, converting, and saving the results. In ratiometric conversions, the conversion value is a ratio of the VREF source to the analog input. As VREF is increased, the input voltage that is required in order to produce a certain conversion value changes; however, all conversion values keep the same relationship to VREF. That is, one half of VREF always results in the value 080h, regardless of the value of VREF (assuming that VREF is in the range of 2.5 to 5.5 volts above VSS3).
12-6
ADC1 Operation
Figure 12-2 shows an example of ratiometric conversion. In this example, the digital result of the conversion indicates the position of the potentiometer wiper, even if the battery loses voltage over time. The ADC1 conversion always gives the ratio of the resistor values on either side of the wiper, even if VREF drops from 5.0 to 2.5 volts.
Figure 12-2. Ratiometric Conversion Example
2.5-5 V +VREF
+ Battery - VSS3 Analog In
12.2.4 Interrupts
The ADC1 module sets the AD INT FLAG bit (ADSTAT.1) at the end of the conversion process. If both the AD INT FLAG and the AD INT ENA bit (ADSTAT.0) are set, then the module generates an interrupt request. This interrupt request can be asserted on either high-priority level 1 or the lower-priority level 2, depending on the AD PRIORITY bit (ADPRI.6). The program must clear the AD INT FLAG bit before exiting the interrupt service routine (ISR), or else the same interrupt will cause the CPU to enter the interrupt routine again. If the AD INT ENA bit is cleared without clearing the flag, the interrupt is reasserted when the AD INT ENA bit is again set.
Analog-to-Digital Converter 1 (ADC1) Module
12-7
ADC1 Operation
12.2.5 Programming Considerations
Follow these steps to obtain data from the ADC1: 1) Write to the ADCTL register (described on page 12-12) to: a) Select the analog channel (ADCTL.2- 0). b) Select the VREF source (ADCTL.5 -3). c) Set the SAMPLE START bit to 1 (ADCTL.6) to begin sampling. 2) Wait for the sample time to elapse. The program should wait 1 s for each kilohm of source output impedance or a minimum of 1 s for low impedance sources. 3) When the sample time completes, set the CONVERT START bit (ADCTL.7); leave the SAMPLE START bit (ADCTL.6) set. 4) Wait for either the interrupt flag to be set or the ADC1 interrupt to occur. 5) Read the conversion data register (ADDATA). 6) Clear the interrupt flag bit (ADSTAT.1). Eighteen SYSCLK cycles after the program sets the CONVERT START bit, the ADC1 module clears both the SAMPLE START and CONVERT START bits to signify the end of the internal sampling phase. After these bits are cleared, the program can change the input channel without affecting the conversion process. The voltage reference source VREF should remain constant throughout the conversion. To stop a conversion in progress, set the SAMPLE START (ADCTL.6) bit to 1 anytime after the ADC1 clears this bit. The entire conversion process requires 164 SYSCLK cycles after the program sets the CONVERT START bit (ADCTL.7).
12-8
ADC1 Example Program
12.3 ADC1 Example Program
This example program (next page) samples and converts data from all eight channels and stores the digital results into a table beginning at ATABLE. The routine stops interrupting the main program after it finishes all eight channels. If the main program wants more recent data, it needs to execute only the code at RESTART, and the ADC1 routine will again sample and convert all eight channels of data. The AD INT ENA bit (ADSTAT.0) is cleared by the ADC1 interrupt routine as a signal to the main program that all eight channels have been processed. The address of the label ATOD must be placed into the interrupt vector table located at 7FECh and 7FEDh.
Analog-to-Digital Converter 1 (ADC1) Module
12-9
ADC1 Example Program
ADCTL ADSTAT ADDATA ADENA
.EQU .EQU .EQU .EQU .REG .REG MOV CALL
P070 P071 P072 P07E ADCHANL ATABLE,8 #0,ADENA RESTART
;ADC1 control register ;ADC1 status register ;ADC1 conversion results ;ADC1 input enable ;keeps current channel number ;8 byte table that stores ; channel data, LSB first ;all channels to ADC1 inputs ; (reset condition) ;start taking data
; INIT ; ; ; ;
; ; ; ; ; SUBROUTINE SECTION RESTART CLR ADCHANL MOV #001h,ADSTAT MOV MOV RTS ; ; ATOD #040h,ADCTL #0C0h,ADCTL
MAIN PROGRAM GOES HERE . . CALL RESTART ;start taking more data . . MORE MAIN PROGRAM ;initialize channel ;enable interrupts, clear ; any flag ;start sampling (approx. 2 s ; delay) ;start converting now; enter ; main program
INTERRUPT ROUTINE FOR ANALOG TO DIGITAL CONVERTER1 PUSH A ;save registers PUSH B MOV ADCHANL,B ;get channel number MOV ADDATA,A ;get ADC1 conversion value MOV A,*ATABLE[B] ;store in a table according to ; channel number INC B ;point to next channel BTJZ #8,B,GOCNVRT ;stop when all channels sampled ;(bit3 =1) CLR ADCHANL ;reset the ADC1 channel MOV #0,ADSTAT ;turn off interrupt and ; clear flag JMP EXITA2D ;all 8 channels taken, enable ;set to 0 now ; GOCNVRT MOV B,ADCHANL ;store current ADC1 channel MOV #01h,ADSTAT ;clear interrupt flag OR #040h,B ;set up sample bit in value MOV B,ADCTL ;start sampling channel data OR #080h,ADCTL ;start converting data ; EXITA2D POP B ;Restore data POP A RTI
12-10
ADC1 Control Registers
12.4 ADC1 Control Registers
The ADC1 module control registers occupy peripheral file frame 7, as shown in Figure 12-3. The bits shown in shaded boxes in Figure 12-3 are privilege mode bits; that is, they can be written only to in the privilege mode.
Figure 12-3. Peripheral File Frame 7: ADC1 Converter Control Registers
Designation ADCTL ADDR 1070h PF P070
Bit 7
CONVERT START (RW-0) --
Bit 6
SAMPLE START (RW-0) --
Bit 5
REF VOL SELECT2 (RW-0) --
Bit 4
REF VOL SELECT1 (RW-0) --
Bit 3
REF VOL SELECT0 (RW-0) --
Bit 2
AD INPUTSELECT2 (RW-0) AD READY (R-0)
Bit 1
AD INPUTSELECT1 (RW-0) AD INT FLAG (RC-0)
Bit 0
AD INPUTSELECT0 (RW-0) AD INT ENA (RW-0)
ADSTAT
1071h
P071
ADDATA
1072h 1073h to 107Ch
P072 P073 to P07C P07D P07E P07F AD STEST (RP-0) AD PRIORITY (RP-0) AD ESPEN (RP-0)
A-to-D Conversion Data Register (R-0) Reserved Port E Data Input Register (R-0) Port E Input Enable Register (RW-0) -- -- -- -- --
ADIN ADENA ADPRI
107Dh 107Eh 107Fh
Analog-to-Digital Converter 1 (ADC1) Module
12-11
ADC1 Control Registers
12.4.1 Analog Control Register (ADCTL)
The ADCTL register controls the input selection, reference voltage selection, sample start, and conversion start.
Analog Control Register (ADCTL) [Memory Address 1070h]
Bit #
P070
7
CONVERT START RW-0
6
SAMPLE START RW-0
5
REF VOLT SELECT2 RW-0
4
REF VOLT SELECT1 RW-0
3
REF VOLT SELECT0 RW-0
2
AD INPUT SELECT2 RW-0
1
AD INPUT SELECT1 RW-0
0
AD INPUT SELECT0 RW-0
R = Read, W = Write, -n = Value of the bit after the register is reset Bit 7 CONVERT START. Conversion Start.
Setting this bit starts the conversion. This bit is cleared by the ADC1 18 system clock cycles after the program sets the CONVERT START bit. Entering halt or standby mode clears this bit and aborts any conversion in progress. Bit 6 SAMPLE START. Sample Start. Setting this bit stops any ongoing conversion and starts sampling the selected input channel to begin a new conversion. This bit is cleared by the ADC1 module 18 system-clock cycles after the program sets the CONVERT START bit. Entering halt or standby mode clears this bit and aborts any sampling in progress. Bits 5-3 REF VOLT SELECT2-0. Reference Voltage (+VREF) Select Bits 2-0. These bits select the channel the ADC1 uses for the positive voltage reference. The REF VOLT SELECT bits must not change during the entire conversion.
REF VOLT SELECT2 0 0 0 0 1 1 1 1 REF VOLT SELECT1 0 0 1 1 0 0 1 1 REF VOLT SELECT0 0 1 0 1 0 1 0 1 +VREF Source
VCC3 AN1 AN2 AN3 AN4 AN5 AN6 AN7
Pin AN0 cannot be selected as positive voltage reference. AN0, AN1, AN4, and AN5 are not implemented on the 40-pin TMS370Cx4x device; thus, they cannot be used as positive voltage references.
12-12
ADC1 Control Registers
Bits 2-0
AD INPUT SELECT2-0. Analog Input Channel Select Bits 2-0. These bits select the channel used for conversion. Channels should be changed only after the ADC1 has cleared the SAMPLE START and CONVERT START bits. Changing the channel while either the SAMPLE START bit or the CONVERT START bit is 1 invalidates the conversion in progress.
AD INPUT SELECT2 0 0 0 0 1 1 1 1 AD INPUT SELECT1 0 0 1 1 0 0 1 1 AD INPUT SELECT0 0 1 0 1 0 1 0 1
Channel AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7
AN0, AN1, AN4, and AN5 are not implemented on the 40-pin TMS370Cx4x device.
Analog-to-Digital Converter 1 (ADC1) Module
12-13
ADC1 Control Registers
12.4.2 Analog Status and Interrupt Register (ADSTAT)
The ADSTAT register indicates the converter and interrupt status.
Analog Status and Interrupt Register (ADSTAT) [Memory Address 1071h]
Bit #
P071
7
--
6
--
5
--
4
--
3
--
2
AD READY R-0
1
AD INT FLAG RC-0
0
AD INT ENA RW-0
R = Read, W = Write, C = Clear only, -n = Value of the bit after the register is reset
Bits 7-3 Bit 2
Reserved. Read data is indeterminate. AD READY. ADC1 Converter Ready. The ADC1 module sets this bit whenever a conversion is not in progress and the ADC1 is ready for a new conversion to start. Writing to this bit has no effect on its state. 0 = Conversion in process. 1 = Converter ready.
Bit 1
AD INT FLAG. ADC1 Interrupt Flag. The ADC1 module sets this bit at the end of an ADC1 conversion. If this bit is set while the AD INT ENA bit is set, an interrupt request is generated. Clearing this flag clears pending ADC1 interrupt requests. This bit is cleared by the system reset. Software cannot set this bit.
Bit 0
AD INT ENA. ADC1 Interrupt Enable. This bit controls the ADC1 module's ability to generate an interrupt. 0 = Disables ADC1 interrupt. 1 = Enables ADC1 interrupt.
12-14
ADC1 Control Registers
12.4.3 Analog Conversion Data Register (ADDATA)
The ADDATA register contains the digital result of the last ADC1 conversion.
Analog Conversion Data Register (ADDATA) [Memory Address 1072h]
Bit #
P072
7
DATA7 R-0
6
DATA6 R-0
5
DATA5 R-0
4
DATA4 R-0
3
DATA3 R-0
2
DATA2 R-0
1
DATA1 R-0
0
DATA0 R-0
R = Read, -n = Value of the bit after the register is reset
The analog-to-digital conversion data is loaded into this register at the end of a conversion and remains there until replaced through another conversion.
12.4.4 Analog Port E Data Input Register (ADIN)
The ADIN register contains digital input data when one or more of the AN0 through AN7 pins are used as digital ports.
Analog Port E Data Input Register (ADIN) [Memory Address 107Dh]
Bit #
P07D
7
PORT E DATA AN 7 R-0
6
PORT E DATA AN 6 R-0
5
PORT E DATA AN 5 R-0
4
PORT E DATA AN 4 R-0
3
PORT E DATA AN 3 R-0
2
PORT E DATA AN 2 R-0
1
PORT E DATA AN 1 R-0
0
PORT E DATA AN 0 R-0
R = Read, -n = Value of the bit after the register is reset
The ADIN register shows the data present at the AN0-AN7 pins when they are configured for general-purpose input instead of for ADC1 channels. A bit is configured as a general-purpose input if the corresponding bit of the port enable register is a 1. Pins configured as ADC1 channels are read as 0s. Writing to this address has no effect.
Analog-to-Digital Converter 1 (ADC1) Module
12-15
ADC1 Control Registers
12.4.5 Analog Port E Input Enable Register (ADENA)
The ADENA register controls the function of the AN0 through AN7 pins.
Analog Port E Data Input Enable Register (ADENA) [Memory Address 107Eh]
Bit #
P07E
7
PORT E INPUT ENA 7 RW-0
6
PORT E INPUT ENA 6 RW-0
5
PORT E INPUT ENA 5 RW-0
4
PORT E INPUT ENA 4 RW-0
3
PORT E INPUT ENA 3 RW-0
2
PORT E INPUT ENA 2 RW-0
1
PORT E INPUT ENA 1 RW-0
0
PORT E INPUT ENA 0 RW-0
R = Read, W = Write, -n = Value of the bit after the register is reset
The ADENA register individually configures the AN0-AN7 pins as either analog input channels or as general-purpose input pins. 0 = For pins AN1-AN7, the pin becomes an analog input or reference channel for the ADC1; for pin AN0, the pin becomes an analog input channel for the ADC1. When the bit is 0, the corresponding bit in the ADIN register reads as a 0. 1 = Enables the pin as a general-purpose input pin; its digital value can be read from the corresponding bit in the port E data input register.
12-16
ADC1 Control Registers
12.4.6 Analog Interrupt Priority Register (ADPRI)
The ADPRI register selects the interrupt priority level of the ADC1 interrupt.
Analog Interrupt Priority Register (ADPRI) [Memory Address 107Fh]
Bit #
P07F
7
AD STEST RP-0
6
AD PRIORITY RP-0
5
AD ESPEN RP-0
4
--
3
--
2
--
1
--
0
--
R = Read, P = Privilege write only, -n = Value of the bit after the register is reset
Bit 7 Bit 6
AD STEST. This bit must be cleared (0) to ensure proper operation. AD PRIORITY. ADC1 Interrupt Priority Select. This bit selects the priority level of the ADC1 interrupt. 0 = ADC1 interrupt is a higher priority (level 1) request. 1 = ADC1 interrupt is a lower priority (level 2) request.
Bit 5
AD ESPEN. Emulator Suspend Enable. Normally, this bit has no effect. However, when you are using the XDS emulator to debug a program, this bit determines what happens to the ADC1 when the program is suspended by an action such as a hardware or software breakpoint. 0 = When the emulator is suspended, the ADC1 continues to work until the current conversion is complete. 1 = When the emulator is suspended, the ADC1 is frozen so that its state can be examined at the point that the emulator was suspended. The conversion data is indeterminate upon restart.
Bits 4-0
Reserved. Read data is indeterminate.
Analog-to-Digital Converter 1 (ADC1) Module
12-17
12-18
Running Title--Attribute Reference
Chapter 13
Analog-To-Digital Converter 2 (ADC2) Module
The TMS370 family contains three different ADC modules (ADC2, ADC2, and ADC3). This chapter discusses the architecture and programming of the analog-to-digital converter 2 (ADC2) module and covers the following topics:
Topic
Page
13.1 Analog-to-Digital Converter 2 (ADC2) Overview . . . . . . . . . . . . . . . . 13-2 13.2 ADC2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5 13.3 ADC2 Example Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8 13.4 ADC2 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-10
Chapter Title--Attribute Reference
13-1
Analog-to-Digital Converter 2 (ACD2) Overview
13.1 Analog-to-Digital Converter 2 (ADC2) Overview
The analog-to-digital converter 2 module is an 8-bit, successive approximation converter with internal sample-and-hold circuitry. The module has four multiplexed analog input channels that allow the processor to convert the voltage levels from up to four different sources. Note: ADC2 Module Availability
The ADC2 module is available for the TMS370CxCx family.
13.1.1 Physical Description
The ADC2 module, shown in Figure 13-1, consists of:
-
The ADC2 conversion block Four analog input channels (AN0-AN3), any of which can be softwareconfigured as digital inputs (E0-E3) if not needed as analog channels An ADC2 input selector (INPUT) A +VREF input selector (+VREF) The ADDATA register, which contains the digital value of a completed conversion ADC2 module control registers
The input channels can be routed through either the channel selector or the positive voltage selector. The ADC2 converter then processes these signals and puts the result in the ADDATA register. The ADC2 interrupt circuit informs the rest of the system when a conversion is completed.
13-2
Analog-to-Digital Converter 2 (ACD2) Overview
Figure 13-1. Analog-to-Digital Converter 2 (ADC2) Block Diagram
External pin connections
Port E input ENA 0
Port E data AN 0
ADENA.0 AN0
Port E input ENA 1
ADIN.0
1
0
SAMPLE START
CONVERT START
ADCTL.1- 0
Port E data AN 1 AD INPUT SELECT
ADCTL.6
ADCTL.7
ADENA.1 AN1
Port E input ENA 2
ADIN.1
Port E data AN 2
ADENA.2 AN2
Port E input ENA 3
ADIN.2
Port E data AN 3
AD
ADENA.3 AN3
ADIN.3 ADDATA.7 - 0
ADC data register 4 3 AD READY
ADCTL.4 - 3
REF VOLTS SELECT
ADSTAT.2
AD PRIORITY
VCC VSS
ADPRI.6 Level 1 Int 0
1 Level 2 Int
AD INT FLAG
ADSTAT.1 ADSTAT.0
AD INT ENA
Analog-to-Digital Converter 2 (ADC2) Module
13-3
Analog-to-Digital Converter 2 (ACD2) Overview
13.1.2 Control Registers
The ADC2 control registers are located at addresses 1070h to 107Fh and occupy peripheral file frame 7, as shown in Table 13-1.
Table 13-1. ADC2 Memory Map
Peripheral File Location P070 P071 P072 P073-P07C P07D P07E P07F
ADIN
Symbol
ADCTL
Name Analog Control Register Analog Status and Interrupt Register Analog Conversion Data Register Reserved Analog Port E Data Input Register Analog Port E Input Enable Register Analog Interrupt Priority Register
Description Controls the input selection, reference voltage selection, sample start, and conversion start. Indicates the converter and interrupt status. Contains the digital result of the last ADC2 conversion. Contains digital input data when one or more of the AN0-AN3 pins are used as digital ports. Controls the function of the AN0-AN3 pins. Selects the interrupt priority level of the ADC2 interrupt.
ADSTAT ADDATA
ADENA ADPRI
13-4
ADC2 Operation
13.2 ADC2 Operation
The following subsections describe the functions and options of the ADC2 module.
13.2.1 Input/Output Pins
The ADC2 module uses six pins to connect itself to the external world: AN0-AN3, VCC and VSS. These pins are described below:
-
Four pins (AN0-AN3) are analog channels and can be individually configured as general-purpose input pins (E0-E3) when not used as analog inputs. Three (AN1-AN2) of the four analog channels are also available as the positive input voltage reference. This feature allows a weighted measurement or ratio of one channel to another.
Note that you can select the VREF pin to be either VCC or one of the analog input channels AN1 to AN3. A channel configured as the +VREF for one conversion can be changed to an analog input channel for the next conversion.
13.2.2 Sampling Time
The application program controls the length of the sample time, which provides the flexibility to optimize the conversion process for both high- and lowimpedance sources. The program should wait 1 s for each kilohm of source output impedance or a minimum of 1 s for low-impedance sources.
13.2.3 ADC2 Conversion
The digital result of the conversion process is given in the following formula: digital result = 255 x input voltage reference voltage
The conversion process requires 164 SYSCLK cycles and results in a conversion time of 32.8 microseconds at 5 MHz SYSCLK. A maximum of 27,600 conversions per second is possible at 5 MHz SYSCLK, including setting up the conversion, sampling, converting, and saving the results. In ratiometric conversions, the conversion value is a ratio of the VREF source to the analog input. As VREF is increased, the input voltage that is required in order to produce a certain conversion value changes; however, all conversion
Analog-to-Digital Converter 2 (ADC2) Module
13-5
ADC2 Operation
values keep the same relationship to VREF. That is, one half of VREF always results in the value 080h, regardless of the value of VREF (assuming that VREF is in the range of 2.5 to 5.5 volts above VSS). Figure 13-2 shows an example of ratiometric conversion. In this example, the digital result of the conversion indicates the position of the potentiometer wiper, even if the battery loses voltage over time. The ADC2 conversion always gives the ratio of the resistor values on either side of the wiper, even if VREF drops from 5.0 to 2.5 volts.
Figure 13-2. Ratiometric Conversion Example
2.5-5 V +VREF
+ Battery - VSS Analog In
13.2.4 Interrupts
The ADC2 module sets the AD INT FLAG bit (ADSTAT.1) at the end of the conversion process. If both the AD INT FLAG and the AD INT ENA bit (ADSTAT.0) are set, then the module generates an interrupt request. This interrupt request can be asserted on either high-priority level 1 or the lower-priority level 2, depending on the AD PRIORITY bit (ADPRI.6). The program must clear the AD INT FLAG bit before exiting the interrupt service routine (ISR), or else the same interrupt will cause the CPU to enter the interrupt routine again. If the AD INT ENA bit is cleared without clearing the flag, the interrupt is reasserted when the AD INT ENA bit is again set.
13-6
ADC2 Operation
13.2.5 Programming Considerations
Follow these steps to obtain data from the ADC2: 1) Write to the ADCTL register (described on page 13-11) to: a) Select the analog channel (ADCTL.1- 0). b) Select the VREF source (ADCTL.4-3). c) Set the SAMPLE START bit to 1 (ADCTL.6) to begin sampling. 2) Wait for the sample time to elapse. The program should wait 1 s for each kilohm of source output impedance or a minimum of 1 s for low impedance sources. 3) When the sample time completes, set the CONVERT START bit (ADCTL.7); leave the SAMPLE START bit (ADCTL.6) set. 4) Wait for either the interrupt flag to be set or the ADC2 interrupt to occur. 5) Read the conversion data register (ADDATA). 6) Clear the interrupt flag bit (ADSTAT.1). Eighteen SYSCLK cycles after the program sets the CONVERT START bit, the ADC2 module clears both the SAMPLE START and CONVERT START bits to signify the end of the internal sampling phase. After these bits are cleared, the program can change the input channel without affecting the conversion process. The voltage reference source VREF should remain constant throughout the conversion. To stop a conversion in progress, set the SAMPLE START (ADCTL.6) bit to 1 anytime after the ADC2 clears this bit. The entire conversion process requires 164 SYSCLK cycles after the program sets the CONVERT START bit (ADCTL.7).
Analog-to-Digital Converter 2 (ADC2) Module
13-7
ADC2 Example Program
13.3 ADC2 Example Program
This example program (next page) samples and converts data from all four channels and stores the digital results into a table beginning at ATABLE. The routine stops interrupting the main program after it finishes all four channels. If the main program wants more recent data, it needs to execute only the code at RESTART, and the ADC2 routine will again sample and convert all four channels of data. The AD INT ENA bit (ADSTAT.0) is cleared by the ADC2 interrupt routine as a signal to the main program that all four channels have been processed. The address of the label ATOD must be placed into the interrupt vector table located at 7FECh and 7FEDh.
13-8
ADC2 Example Program
ADCTL ADSTAT ADDATA ADENA
.EQU .EQU .EQU .EQU .REG .REG MOV CALL
P070 P071 P072 P07E ADCHANL ATABLE,8 #0,ADENA RESTART
;ADC2 control register ;ADC2 status register ;ADC2 conversion results ;ADC2 input enable ;keeps current channel number ;8 byte table that stores ; channel data, LSB first ;all channels to ADC2 inputs ; (reset condition) ;start taking data
; INIT ; ; ; ;
; ; ; ; ; SUBROUTINE SECTION RESTART CLR ADCHANL MOV #001h,ADSTAT MOV MOV RTS ; ; ATOD #040h,ADCTL #0C0h,ADCTL
MAIN PROGRAM GOES HERE . . CALL RESTART ;start taking more data . . MORE MAIN PROGRAM ;initialize channel ;enable interrupts, clear ; any flag ;start sampling (approx. 2 s ; delay) ;start converting now; enter ; main program
INTERRUPT ROUTINE FOR ANALOG TO DIGITAL CONVERTER2 PUSH A ;save registers PUSH B MOV ADCHANL,B ;get channel number MOV ADDATA,A ;get ADC2 conversion value MOV A,*ATABLE[B] ;store in a table according to ; channel number INC B ;point to next channel BTJZ #4,B,GOCNVRT ;stop when all channels sampled ;(bit3 =1) CLR ADCHANL ;reset the ADC2 channel MOV #0,ADSTAT ;turn off interrupt and ; clear flag JMP EXITA2D ;all four channels taken, enable ;set to 0 now ; GOCNVRT MOV B,ADCHANL ;store current ADC2 channel MOV #01h,ADSTAT ;clear interrupt flag OR #040h,B ;set up sample bit in value MOV B,ADCTL ;start sampling channel data OR #080h,ADCTL ;start converting data ; EXITA2D POP B ;Restore data POP A RTI
Analog-to-Digital Converter 2 (ADC2) Module
13-9
ADC2 Control Registers
13.4 ADC2 Control Registers
The ADC2 module control registers occupy peripheral file frame 7, as shown in Figure 13-3. The bits shown in shaded boxes in Figure 13-3 are privilege mode bits; that is, they can be written only to in the privilege mode.
Figure 13-3. Peripheral File Frame 7: ADC2 Converter Control Registers
Designation ADCTL ADDR 1070h PF P070
Bit 7
CONVERT START (RW-0) --
Bit 6
SAMPLE START (RW-0) --
Bit 5
--
Bit 4
REF VOLT SELECT1 (RW-0) --
Bit 3
REF VOLT SELECT0 (RW-0) --
Bit 2
-- AD READY (R-0)
Bit 1
AD INPUT SELECT1 (RW-0) AD INT FLAG (RC-0)
Bit 0
AD INPUT SELECT0 (RW-0) AD INT ENA (RW-0)
ADSTAT
1071h
P071 --
ADDATA
1072h 1073h to 107Ch
P072 P073 to P07C P07D P07E P07F -- -- AD STEST (RP-0) -- -- AD PRIORITY (RP-0) -- --
A-to-D Conversion Data Register (R-0) Reserved -- -- -- -- Port E Data Input Register (R-0) Port E Input Enable Register (RW-0) -- -- --
ADIN
107Dh 107Eh 107Fh
ADENA ADPRI
AD ESPEN (RP-0)
13-10
ADC2 Control Registers
13.4.1 Analog Control Register (ADCTL)
The ADCTL register controls the input selection, reference voltage selection, sample start, and conversion start.
Analog Control Register (ADCTL) [Memory Address 1070h]
Bit #
P070
7
CONVERT START RW-0
6
SAMPLE START RW-0
5
-
4
REF VOLT SELECT1 RW-0
3
REF VOLT SELECT0 RW-0
2
-
1
AD INPUT SELECT1 RW-0
0
AD INPUT SELECT0 RW-0
R = Read, W = Write, -n = Value of the bit after the register is reset Bit 7 CONVERT START. Conversion Start.
Setting this bit starts the conversion. This bit is cleared by the ADC2 18 system clock cycles after the program sets the CONVERT START bit. Entering halt or standby mode clears this bit and aborts any conversion in progress. Bit 6 SAMPLE START. Sample Start. Setting this bit stops any ongoing conversion and starts sampling the selected input channel to begin a new conversion. This bit is cleared by the ADC2 module 18 system-clock cycles after the program sets the CONVERT START bit. Entering halt or standby mode clears this bit and aborts any sampling in progress. Bit 5 Bits 4-3 Reserved. Read data is indeterminate. REF VOLT SELECT1-0. Reference Voltage (+VREF) Select Bits 1-0. These bits select the channel the ADC2 uses for the positive voltage reference. The REF VOLT SELECT bits must not change during the entire conversion.
REF VOLT SELECT1 0 0 1 1 REF VOLT SELECT0 0 1 0 1 +VREF Source VCC AN1 AN2 AN3
Pin AN0 cannot be selected as positive voltage reference.
Bit 2
Reserved. Read data is indeterminate
Analog-to-Digital Converter 2 (ADC2) Module
13-11
ADC2 Control Registers
Bits 1-0
AD INPUT SELECT1-0. Analog Input Channel Select Bits 1-0. These bits select the channel used for conversion. Channels should be changed only after the ADC2 has cleared the SAMPLE START and CONVERT START bits. Changing the channel while either the SAMPLE START bit or the CONVERT START bit is 1 invalidates the conversion in progress.
AD INPUT SELECT1 0 0 1 1 AD INPUT SELECT0 0 1 0 1 Channel AN0 AN1 AN2 AN3
13-12
ADC2 Control Registers
13.4.2 Analog Status and Interrupt Register (ADSTAT)
The ADSTAT register indicates the converter and interrupt status.
Analog Status and Interrupt Register (ADSTAT) [Memory Address 1071h]
Bit #
P071
7
--
6
--
5
--
4
--
3
--
2
AD READY R-0
1
AD INT FLAG RC-0
0
AD INT ENA RW-0
R = Read, W = Write, C = Clear only, -n = Value of the bit after the register is reset
Bits 7-3 Bit 2
Reserved. Read data is indeterminate. AD READY. ADC2 Converter Ready. The ADC2 module sets this bit whenever a conversion is not in progress and the ADC2 is ready for a new conversion to start. Writing to this bit has no effect on its state. 0 = Conversion in process. 1 = Converter ready.
Bit 1
AD INT FLAG. ADC2 Interrupt Flag. The ADC2 module sets this bit at the end of an ADC2 conversion. If this bit is set while the AD INT ENA bit is set, an interrupt request is generated. Clearing this flag clears pending ADC2 interrupt requests. This bit is cleared by the system reset. Software cannot set this bit.
Bit 0
AD INT ENA. ADC2 Interrupt Enable. This bit controls the ADC2 module's ability to generate an interrupt. 0 = Disables ADC2 interrupt. 1 = Enables ADC2 interrupt.
13.4.3 Analog Conversion Data Register (ADDATA)
The ADDATA register contains the digital result of the last ADC2 conversion.
Analog Conversion Data Register (ADDATA) [Memory Address 1072h]
Bit #
P072
7
DATA7 R-0
6
DATA6 R-0
5
DATA5 R-0
4
DATA4 R-0
3
DATA3 R-0
2
DATA2 R-0
1
DATA1 R-0
0
DATA0 R-0
R = Read, -n = Value of the bit after the register is reset
The ADC2 data is loaded into this register at the end of a conversion and remains until replaced by another conversion.
Analog-to-Digital Converter 2 (ADC2) Module
13-13
ADC2 Control Registers
13.4.4 Analog Port E Data Input Register (ADIN)
The ADIN register contains digital input data when one or more of the AN0 through AN3 pins are used as digital ports.
Analog Port E Data Input Register (ADIN) [Memory Address 107Dh]
Bit #
P07D
7
- R-0
6
- R-0
5
- R-0
4
- R-0
3
PORT E DATA AN 3 R-0
2
PORT E DATA AN 2 R-0
1
PORT E DATA AN1 R-0
0
PORT E DATA AN 0 R-0
R = Read, -n = Value of the bit after the register is reset
The ADIN register shows the data present at the AN0-AN3 pins when they are configured for general-purpose input instead of for ADC2 channels. A bit is configured as a general-purpose input if the corresponding bit of the port enable register is a 1. Pins configured as ADC2 channels are read as 0s. Writing to this address has no effect.
13.4.5 Analog Port E Input Enable Register (ADENA)
The ADENA register controls the function of the AN0 through AN3 pins.
Analog Port E Data Input Enable Register (ADENA) [Memory Address 107Eh]
Bit #
P07E
7
- RW-0
6
- RW-0
5
- RW-0
4
- RW-0
3
PORT E INPUT ENA 3 RW-0
2
PORT E INPUT ENA 2 RW-0
1
PORT E INPUT ENA 1 RW-0
0
PORT E INPUT ENA 0 RW-0
R = Read, W = Write, -n = Value of the bit after the register is reset
The ADENA register individually configures the AN0-AN3 pins as either analog input channels or as general-purpose input pins. 0 = For pins AN1-AN3, the pin becomes an analog input or reference channel for the ADC2; for pin AN0, the pin becomes an analog input channel for the ADC2. When the bit is 0, the corresponding bit in the ADIN register reads as a 0. 1 = Enables the pin as a general-purpose input pin; its digital value can be read from the corresponding bit in the port E data input register.
13-14
ADC2 Control Registers
13.4.6 Analog Interrupt Priority Register (ADPRI)
The ADPRI register selects the interrupt priority level of the ADC2 interrupt.
Analog Interrupt Priority Register (ADPRI) [Memory Address 107Fh]
Bit #
P07F
7
AD STEST RP-0
6
AD PRIORITY RP-0
5
AD ESPEN RP-0
4
--
3
--
2
--
1
--
0
--
R = Read, P = Privilege write only, -n = Value of the bit after the register is reset
Bit 7 Bit 6
AD STEST. This bit must be cleared (0) to ensure proper operation. AD PRIORITY. ADC2 Interrupt Priority Select. This bit selects the priority level of the ADC2 interrupt. 0 = ADC2 interrupt is a higher priority (level 1) request. 1 = ADC2 interrupt is a lower priority (level 2) request.
Bit 5
AD ESPEN. Emulator Suspend Enable. Normally, this bit has no effect. However, when you are using the XDS emulator to debug a program, this bit determines what happens to the ADC2 when the program is suspended by an action such as a hardware or software breakpoint. 0 = When the emulator is suspended, the ADC2 continues to work until the current conversion is complete. 1 = When the emulator is suspended, the ADC2 is frozen so that its state can be examined at the point that the emulator was suspended. The conversion data is indeterminate upon restart.
Bits 4-0
Reserved. Read data is indeterminate.
Analog-to-Digital Converter 2 (ADC2) Module
13-15
13-16
Running Title--Attribute Reference
Chapter 14
Analog-To-Digital Converter 3 (ADC3) Module
The TMS370 family contains three different ADC modules (ADC1, ADC2, and ADC3). This chapter discusses the architecture and programming of the analog-to-digital converter 3 (ADC3) module and covers the following topics:
Topic
Page
14.1 Analog-to-Digital Converter 3 (ADC3) Overview . . . . . . . . . . . . . . . . 14-2 14.2 ADC3 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-5 14.3 ADC3 Example Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-9 14.4 ADC3 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-11
Analog-to-Digital Converter 3 (ADC3) Module
14-1
Analog-to-Digital Converter 3 (ACD3) Overview
14.1 Analog-to-Digital Converter 3 (ADC3) Overview
The analog-to-digital converter 3 module is an 8-bit, successive approximation converter with internal sample-and-hold circuitry. The module has 15 analog input channels that allow the processor to convert the voltage levels from up to 15 different sources. Note: ADC3 Module Availability
The ADC3 module is available for the TMS370Cx9x family.
14.1.1 Physical Description
The ADC3 module, shown in Figure 14-1, consists of:
-
Fifteen analog input channels (AN0-AN14), eight (AN0-AN7) of which can be software-configured as digital inputs (E0-E7) if not needed as analog channels The ADC3 conversion block An ADC3 conversion rate selector An ADC3 input selector (INPUT) A +VREF input selector (+VREF) The ADDATA register, which contains the digital value of a completed conversion ADC3 module control registers
The input channels can be routed through either the channel selector or the positive voltage selector. The ADC3 converter then processes these signals and puts the result in the ADDATA register. The ADC3 interrupt circuit informs the rest of the system when a conversion is completed.
14-2
Analog-to-Digital Converter 3 (ACD3) Overview
Figure 14-1. Analog-to-Digital Converter 3 (ADC3) Block Diagram
External pin connections
Port E input ENA 0
Port E data AN 0
ADENA.0
ADIN.0
AN0
Port E input ENA 1 Port E data AN 1
3
2
1
0
SAMPLE START
CONVERT START
ADCTL.3 - 0
AD INPUT SELECT
ADCTL.6
ADCTL.7
ADENA.1 AN1
ADIN.1
1 0
ADPRI.1 - 0
AD RATE SELECTS Port E input ENA 5
Port E data AN 5
AD
ADENA.5 AN5
Port E input ENA 6
ADIN.5 ADDATA.7 - 0
ADC data register AD READY
Port E data AN 6
ADENA.6 AN6
Port E input ENA 7
ADIN.6
Port E data AN 7
ADENA.7 AN7 AN8 AN9
ADSTAT.2
AD PRIORITY
ADIN.7 ADPRI.6 Level 1 Int 0
5 4 1 Level 2 Int
ADCTL.5 - 4
REF VOLTS SELECT
AN14 VCC3 VSS3
AD INT FLAG
ADSTAT.1 ADSTAT.0
AD INT ENA
Analog-to-Digital Converter 3 (ADC3) Module
14-3
Analog-to-Digital Converter 3 (ADC3) Overview
14.1.2 Control Registers
The ADC3 control registers are located at addresses 1070h to 107Fh and occupy peripheral file frame 7, as shown in Table 14-1.
Table 14-1. ADC3 Memory Map
Peripheral File Location P070
Symbol
ADCTL
Name Analog Control Register
Description Controls the input selection, reference voltage selection, sample start, and conversion start. Indicates the converter and interrupt status. Contains the digital result of the last ADC3 conversion.
P071 P072 P073-P07C P07D
ADSTAT
Analog Status and Interrupt Register Analog Conversion Data Register Reserved
ADDATA
ADIN
Analog Port E Data Input Register
Contains digital input data when one or more of the AN0-AN7 pins are used as digital ports. Controls the function of the AN0-AN7 pins. Selects the interrupt priority level of the ADC3 interrupt and the conversion rate selects.
P07E P07F
ADENA
Analog Port E Input Enable Register Analog Interrupt Priority Register
ADPRI
14-4
ADC3 Operation
14.2 ADC3 Operation
The following subsections describe the functions and options of the ADC3 module.
14.2.1 Input/Output Pins
The ADC3 module contains 17 pins: AN0-AN14, VCC3, and VSS3. These pins are described below:
-
Fifteen (AN0-AN14) of the 17 pins are analog channels. Eight (AN0-AN7) of the 15 analog channels can be individually configured as general-purpose input pins (E0-E7) when not used as analog inputs. Two (AN6-AN7) of the fifteen analog channels are also available as the positive input voltage reference. This feature allows a weighted measurement or ratio of one channel to another. The analog voltage supply pins, VCC3 and VSS3, isolate the ADC3 module from digital switching noise that can be present on the other power supply pins. This isolation provides a more accurate conversion. To further reduce noise and produce a more accurate conversion, you should run the power to the VCC3 and VSS3 pins on separate conductors from the other power lines. Additionally, the power conductors to the VCC3 and VSS3 should be as short as possible, and the two lines should be properly decoupled. Use other standard noise-reduction techniques to help provide a more accurate conversion.
Note that you can select the VREF pin to be either VCC3 or one of the analog input channels AN6 to AN7. A VCC3 must provide power to the ADC3 module even if it does not provide the voltage reference. A channel configured as the +VREF for one conversion can be changed to an analog input channel for the next conversion.
14.2.2 Sampling Time
The application program controls the length of the sample time, which provides the flexibility to optimize the conversion process for both high- and lowimpedance sources. The program should wait 1 s for each kilohm of source output impedance or a minimum of 1 s for low-impedance sources.
Analog-to-Digital Converter 3 (ADC3) Module
14-5
ADC3 Operation
14.2.3 ADC3 Conversion
The digital result of the conversion process is given in the following formula: digital result = 255 x input voltage reference voltage
The number of SYSCLK cyles required to complete a conversion is programmable through the AD RATE SELECT0-1 bits (P07F.0-1). For example, the conversion process requires 164 SYSCLK cycles and results in a conversion time of 32.8 microseconds at a SYSCLK frequency of less than or equal 5 MHz and greater than 2.5 MHz (5 MHz SYSCLK > 2.5 MHz). A maximum of 27,600 conversions per second is possible at a SYSCLK frequency within the range above, including setting up the conversion, sampling, converting, and saving the results. In ratiometric conversions, the conversion value is a ratio of the VREF source to the analog input. As VREF is increased, the input voltage that is required in order to produce a certain conversion value changes; however, all conversion values keep the same relationship to VREF. That is, one half of VREF always results in the value 080h, regardless of the value of VREF (assuming that VREF is in the range of 2.5 to 5.5 volts above VSS3).
14-6
ADC3 Operation
Figure 14-2 shows an example of ratiometric conversion. In this example, the digital result of the conversion indicates the position of the potentiometer wiper, even if the battery loses voltage over time. The ADC3 conversion always gives the ratio of the resistor values on either side of the wiper, even if VREF drops from 5.0 to 2.5 volts.
Figure 14-2. Ratiometric Conversion Example
2.5-5 V +VREF
+ Battery - VSS3 Analog In
14.2.4 Interrupts
The ADC3 module sets the AD INT FLAG bit (ADSTAT.1) at the end of the conversion process. If both the AD INT FLAG and the AD INT ENA bit (ADSTAT.0) are set, then the module generates an interrupt request. This interrupt request can be asserted on either high-priority level 1 or the lower-priority level 2, depending on the AD PRIORITY bit (ADPRI.6). The program must clear the AD INT FLAG bit before exiting the interrupt service routine (ISR), or else the same interrupt will cause the CPU to enter the interrupt routine again. If the AD INT ENA bit is cleared without clearing the flag, the interrupt is reasserted when the AD INT ENA bit is again set.
Analog-to-Digital Converter 3 (ADC3) Module
14-7
ADC3 Operation
14.2.5 Programming Considerations
Follow these steps to obtain data from the ADC3: 1) Write to the two bits (AD RATE SELECT 1-0) on the ADPRI register (subsection 14.4.6 on page 14-16). 2) Write to the ADCTL register (subsection 14.4.1 on page 14-12) to: a) Select the analog channel (ADCTL.3- 0). b) Select the VREF source (ADCTL.5-4). c) Set the SAMPLE START bit to 1 (ADCTL.6) to begin sampling. 3) Wait for the sample time to elapse. The program should wait 1 s for each kilohm of source output impedance or a minimum of 1 s for low impedance sources. 4) When the sample time completes, set the CONVERT START bit (ADCTL.7) and leave the SAMPLE START bit (ADCTL.6) set. 5) Wait for either the interrupt flag to be set or the ADC3 interrupt to occur. 6) Read the conversion data register (ADDATA, subsection 14.4.3 on page 14-15). 7) Clear the interrupt flag bit (ADSTAT.1). Eighteen SYSCLK cycles after the program sets the CONVERT START bit, the ADC3 module clears both the SAMPLE START and CONVERT START bits to signify the end of the internal sampling phase. After these bits are cleared, the program can change the input channel without affecting the conversion process. The voltage reference source VREF should remain constant throughout the conversion. To stop a conversion in progress, set the SAMPLE START (ADCTL.6) bit to 1 anytime after the ADC3 clears this bit. For SYSCLK frequencies less than or equal to 5MHz and greater than 2.5MHz, the entire conversion process requires 164 SYSCLK cycles after the program sets the CONVERT START bit (ADCTL.7).
14-8
ADC3 Example Program
14.3 ADC3 Example Program
This example program samples and converts data from all 15 channels at 1.0 MHz SYSCLK frequency and stores the digital results into a table beginning at ATABLE. The routine stops interrupting the main program after it finishes all 15 channels. If the main program wants more recent data, it needs to execute only the code at RESTART, and the ADC3 routine will again sample and convert all 15 channels of data. The AD INT ENA bit (ADSTAT.0) is cleared by the ADC3 interrupt routine as a signal to the main program that all 15 channels have been processed. The address of the label ATOD must be placed into the interrupt vector table located at 7FECh and 7FEDh.
Analog-to-Digital Converter 3 (ADC3) Module
14-9
ADC3 Example Program
ADCTL ADSTAT ADDATA ADENA
.EQU .EQU .EQU .EQU .REG .REG MOV CALL
P070 P071 P072 P07E ADCHANL ATABLE,8 #0,ADENA RESTART
INIT ; ; ; ; ;
;
;ADC3 control register ;ADC3 status register ;ADC3 conversion results ;ADC3 input enable ;keeps current channel number ;8 byte table that stores ; channel data, LSB first ;all channels to ADC3 inputs ; (reset condition) ;start taking data
MAIN PROGRAM GOES HERE . CALL RESTART ;start taking more data . MORE MAIN PROGRAM ;initialize channel ;select the conversion rate of ; 44 SYSCLK cycles and ADC3 ; interrupt-request priority ; level 1 ;enable interrupts, clear ; any flag ;start sampling (approx. 2 s ; delay) ;start converting now; enter ; main program
; SUBROUTINE SECTION RESTART CLR ADCHANL MOV #002h,ADPRI
MOV MOV MOV RTS
;
#001h,ADSTAT #040h,ADCTL #0C0h,ADCTL
INTERRUPT ROUTINE FOR ANALOG TO DIGITAL CONVERTER3 PUSH A ;save registers PUSH B MOV ADCHANL,B ;get channel number MOV ADDATA,A ;get ADC3 conversion value MOV A,*ATABLE[B] ;store in a table according to ; channel number INC B ;point to next channel BTJZ #15,B,GOCNVRT ;stop when all channels sampled ;(bit3 =1) CLR ADCHANL ;reset the ADC3 channel MOV #0,ADSTAT ;turn off interrupt and ; clear flag JMP EXITA2D ;all 8 channels taken, enable ;set to 0 now
;
; ATOD
GOCNVRT MOV B,ADCHANL MOV #01h,ADSTAT OR #040h,B ;set up sample bit in value MOV B,ADCTL OR #080h,ADCTL
;
;store current ADC3 channel ;clear interrupt flag ;start sampling channel data ;start converting data ;Restore data
EXITA2D POP POP RTI
B A
14-10
ADC3 Control Registers
14.4 ADC3 Control Registers
The ADC3 module control registers occupy peripheral file frame 7, as shown in Figure 14-3. The bits shown in shaded boxes in Figure 14-3 are privilege mode bits; that is, they can be written only to in the privilege mode.
Figure 14-3. Peripheral File Frame 7: ADC3 Converter Control Registers
Designation ADCTL ADDR 1070h PF P070
Bit 7
CONVERT START (RW-0) --
Bit 6
SAMPLE START (RW-0) --
Bit 5
REF VOL SELECT1 (RW-0) --
Bit 4
REF VOL SELECT0 (RW-0) --
Bit 3
AD INPUT SELECT3 (RW-0) --
Bit 2
AD INPUT SELECT2 (RW-0) AD READY (R-0)
Bit 1
AD INPUT SELECT1 (RW-0) AD INT FLAG (RC-0)
Bit 0
AD INPUT SELECT0 (RW-0) AD INT ENA (RW-0)
ADSTAT
1071h
P071
ADDATA
1072h 1073h to 107Ch
P072 P073 to P07C P07D P07E P07F AD STEST (RP-0) AD PRIORITY (RP-0) AD ESPEN (RP-0)
A-to-D Conversion Data Register (R-0) Reserved Port E Data Input Register (R-0) Port E Input Enable Register (RW-0) -- -- -- AD RATESELECT1 (RW-0) AD RATESELECT0 (RW-0)
ADIN ADENA ADPRI
107Dh 107Eh 107Fh
Analog-to-Digital Converter 3 (ADC3) Module
14-11
ADC3 Control Registers
14.4.1 Analog Control Register (ADCTL)
The ADCTL register controls the input selection, reference voltage selection, sample start, and conversion start.
Analog Control Register (ADCTL) [Memory Address 1070h]
Bit #
P070
7
CONVERT START RW-0
6
SAMPLE START RW-0
5
REF VOLT SELECT1 RW-0
4
REF VOLT SELECT0 RW-0
3
AD INPUT SELECT3 RW-0
2
AD INPUT SELECT2 RW-0
1
AD INPUT SELECT1 RW-0
0
AD INPUT SELECT0 RW-0
R = Read, W = Write, -n = Value of the bit after the register is reset Bit 7 CONVERT START. Conversion Start.
Setting this bit starts the conversion. This bit is cleared by the ADC3 18 system clock cycles after the program sets the CONVERT START bit. Entering halt or standby mode clears this bit and aborts any conversion in progress. Bit 6 SAMPLE START. Sample Start. Setting this bit stops any ongoing conversion and starts sampling the selected input channel to begin a new conversion. This bit is cleared by the ADC3 module 18 system-clock cycles after the program sets the CONVERT START bit. Entering halt or standby mode clears this bit and aborts any sampling in progress. Bits 5-4 REF VOLT SELECT1-0. Reference Voltage (+VREF) Select Bits 1-0. These bits select the channel the ADC3 uses for the positive voltage reference. The REF VOLT SELECT bits must not change during the entire conversion.
REF VOLT SELECT1 0 0 1 REF VOLT SELECT0 0 1 0 +VREF Source VCC3 AN6 AN7
Pins AN0-AN5 and AN8-AN14 cannot be selected as positive voltage reference.
14-12
ADC3 Control Registers
Bits 3-0
AD INPUT SELECT3-0. Analog Input Channel Select Bits 3-0. These bits select the channel used for conversion. Channels should be changed only after the ADC3 has cleared the SAMPLE START and CONVERT START bits. Changing the channel while either the SAMPLE START bit or the CONVERT START bit is 1 invalidates the conversion in progress.
AD INPUT SELECT3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 AD INPUT SELECT2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 AD INPUT SELECT1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 AD INPUT SELECT0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 AD INPUT CHANNEL AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14
Analog-to-Digital Converter 3 (ADC3) Module
14-13
ADC3 Control Registers
14.4.2 Analog Status and Interrupt Register (ADSTAT)
The ADSTAT register indicates the converter and interrupt status.
Analog Status and Interrupt Register (ADSTAT) [Memory Address 1071h]
Bit #
P071
7
--
6
--
5
--
4
--
3
--
2
AD READY R-0
1
AD INT FLAG RC-0
0
AD INT ENA RW-0
R = Read, W = Write, C = Clear only, -n = Value of the bit after the register is reset
Bits 7-3 Bit 2
Reserved. Read data is indeterminate. AD READY. ADC3 Converter Ready. The ADC3 module sets this bit whenever a conversion is not in progress and the ADC3 is ready for a new conversion to start. Writing to this bit has no effect on its state. 0 = Conversion in process. 1 = Converter ready.
Bit 1
AD INT FLAG. ADC3 Interrupt Flag. The ADC3 module sets this bit at the end of an ADC3 conversion. If this bit is set while the AD INT ENA bit is set, an interrupt request is generated. Clearing this flag clears pending ADC3 interrupt requests. This bit is cleared by the system reset. Software cannot set this bit.
Bit 0
AD INT ENA. ADC3 Interrupt Enable. This bit controls the ADC3 module's ability to generate an interrupt. 0 = Disables ADC3 interrupt. 1 = Enables ADC3 interrupt.
14-14
ADC3 Control Registers
14.4.3 Analog Conversion Data Register (ADDATA)
The ADDATA register contains the digital result of the last ADC3 conversion.
Analog Conversion Data Register (ADDATA) [Memory Address 1072h]
Bit #
P072
7
DATA7 R-0
6
DATA6 R-0
5
DATA5 R-0
4
DATA4 R-0
3
DATA3 R-0
2
DATA2 R-0
1
DATA1 R-0
0
DATA0 R-0
R = Read, -n = Value of the bit after the register is reset
The ADC3 data is loaded into this register at the end of a conversion and remains until replaced by another conversion.
14.4.4 Analog Port E Data Input Register (ADIN)
The ADIN register contains digital input data when one or more of the AN0 through AN7 pins are used as digital ports.
Analog Port E Data Input Register (ADIN) [Memory Address 107Dh]
Bit #
P07D
7
PORT E DATA AN 7 R-0
6
PORT E DATA AN 6 R-0
5
PORT E DATA AN 5 R-0
4
PORT E DATA AN 4 R-0
3
PORT E DATA AN 3 R-0
2
PORT E DATA AN 2 R-0
1
PORT E DATA AN 1 R-0
0
PORT E DATA AN 0 R-0
R = Read, -n = Value of the bit after the register is reset
The ADIN register shows the data present at the AN0-AN7 pins when they are configured for general-purpose input instead of for ADC3 channels. A bit is configured as a general-purpose input if the corresponding bit of the port enable register is a 1. Pins configured as ADC3 channels are read as 0s. Writing to this address has no effect.
Analog-to-Digital Converter 3 (ADC3) Module
14-15
ADC3 Control Registers
14.4.5 Analog Port E Input Enable Register (ADENA)
The ADENA register controls the function of the AN0 through AN7 pins.
Analog Port E Data Input Enable Register (ADENA) [Memory Address 107Eh]
Bit #
P07E
7
PORT E INPUT ENA 7 RW-0
6
PORT E INPUT ENA 6 RW-0
5
PORT E INPUT ENA 5 RW-0
4
PORT E INPUT ENA 4 RW-0
3
PORT E INPUT ENA 3 RW-0
2
PORT E INPUT ENA 2 RW-0
1
PORT E INPUT ENA 1 RW-0
0
PORT E INPUT ENA 0 RW-0
R = Read, W = Write, -n = Value of the bit after the register is reset
The ADENA register individually configures the AN0-AN7 pins as either analog input channels or as general-purpose input pins. 0 = For pins AN1-AN7, the pin becomes an analog input or reference channel for the ADC3; for pin AN0, the pin becomes an analog input channel for the ADC3. When the bit is 0, the corresponding bit in the ADIN register reads as a 0. 1 = Enables the pin as a general-purpose input pin; its digital value can be read from the corresponding bit in the port E data input register.
14.4.6 Analog Interrupt Priority Register (ADPRI)
The ADPRI register selects the interrupt priority level of the ADC3 interrupt.
Analog Interrupt Priority Register (ADPRI) [Memory Address 107Fh]
Bit #
P07F
7
AD STEST RP-0
6
AD PRIORITY RP-0
5
AD ESPEN RP-0
4
--
3
--
2
--
1
AD RATE SELECT1
0
ADD RATE SELECT0
R = Read, P = Privilege write only, -n = Value of the bit after the register is reset
Bit 7 Bit 6
AD STEST. This bit must be cleared (0) to ensure proper operation. AD PRIORITY. ADC3 Interrupt Priority Select. This bit selects the priority level of the ADC3 interrupt. 0 = ADC3 interrupt is a higher priority (level 1) request. 1 = ADC3 interrupt is a lower priority (level 2) request.
14-16
ADC3 Control Registers
Bit 5
AD ESPEN. Emulator Suspend Enable. Normally, this bit has no effect. However, when you are using the XDS emulator to debug a program, this bit determines what happens to the ADC3 when the program is suspended by an action such as a hardware or software breakpoint. 0 = When the emulator is suspended, the ADC3 continues to work until the current conversion is complete. 1 = When the emulator is suspended, the ADC3 is frozen so that its state can be examined at the point that the emulator was suspended. The conversion data is indeterminate upon restart.
Bits 4-2 Bits 1-0
Reserved. Read data is indeterminate. AD RATE SELECT1-0 ADC3 Conversion Rate Select Bits 1-0. These bits determine the conversion rate of the ADC3 as a function of the system clock frequency. Note in Table 14-2 that only the default selection (0,0) provides full SYSCLK frequency range together with 8-bit precision. Other selections allow maintaining minimum conversion time at lower system clock rates.
Table 14-2.
Conversion Rate Selection
AD RATE SELECT1 AD RATE SELECT0 0 1 0 1
Conversion Time (number (n mber of system clock cycles) Max SYSCLK Frequency 164 84 44 24 5 MHz SYSCLK > 2.5 MHz 2.5 MHz SYSCLK > 1.25 MHz 1.25 MHz SYSCLK > 0.625 MHz 0.625 MHz SYSCLK 0.5 MHz
0 0 1 1
If selections different from (0,0) are used at SYSCLK frequencies higher than specified in the above table the 8-bit precision of the ADC3 is not guaranteed.
Analog-to-Digital Converter 3 (ADC3) Module
14-17
14-18
Running Title--Attribute Reference
Chapter 15
Programmable Acquisition and Control Timer (PACT)
This chapter discusses the architecture and programming of the programmable acquisition and control timer (PACT) module. Even if you have extensive experience with microcontroller timers, you should read this chapter to fully understand how to use the TMS370 PACT module. The chapter covers the following topics:
Topic
Page
15.1 PACT Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2 15.2 PACT Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5 15.3 Dual-Port RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-9 15.4 Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-12 15.5 Control and Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-15 15.6 Command/Definition Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-21 15.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-29 15.8 WD Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-31 15.9 Mini-Serial Communications Interface (SCI) . . . . . . . . . . . . . . . . . . . 15-32 15.10 PWM Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-33 15.11 PACT Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-36
Chapter Title--Attribute Reference
15-1
PACT Overview
15.1 PACT Overview
The PACT module acts as a timer coprocessor by gathering timing information on input signals and controlling output signals with little or no intervention by the CPU. The coprocessor nature of this module allows for levels of flexibility and power not found in traditional microcontroller timers. The PACT module is available in the TMS370Cx32 and TMS370Cx36 families.
15.1.1 Physical Description
The PACT module, shown in Figure 15-1, consists of:
-
Input capture functions on up to six input pins, four of which (CP3-CP6) may have a programmable prescaler Timer-driven outputs on eight pins Configurable timer overflow rates for different functions One 8-bit event counter driven by CP6 Timer capability of up to 20 bits Interaction between event counter and timer activity Register-based organization, allowing single-cycle accesses to parameters Eighteen independent interrupt vectors with two priority levels Integrated, configurable watchdog (WD) timer with selectable time-out period Mini-serial communications interface with independent setup of bit rate (baud) for receive and transmit lines
15-2
PACT Overview
Figure 15-1. PACT Block Diagram
PACT prescaled clock
External pin connections
20-bit timer/counter 8-bit event counter
Prescale WD timer Reset
CP1 CP2
Dedicated capture register 1 Dedicated capture register 2 Dedicated capture register 3 Dedicated capture register 4 3-bit prescaler
CP3 CP4 CP5 CP6
Mode
Circular buffer (32-bit captures)
External pin connections
Event only
Command/definition area OP1 Outputs Command analyzer and output controller OP8 Int level 1 Int level 2
SCIRXD
Mini-SCI
SCITXD
Programmable Acquisition and Control Timer (PACT)
15-3
PACT Overview
15.1.2 Control Registers
The PACT control registers are located at addresses 1040h to 104Fh and occupy peripheral file frame 4. The function of each register is shown in Table 15-1.
Table 15-1. PACT Peripheral Frame
Peripheral File Location P040
Symbol PACT SCR
Name Setup Control Register
Description Determines the time base for the PACT module, enables the command/definition area, and controls the default timer overflow Defines the starting address of the command/definition area and enables the interrupts for that area Defines the end address of the command/definition area Defines the address of the buffer pointer
P041 P042 P043 P044 P045 P046 P047 P048 P049 P04A P04B P04C P04D P04E P04F
CDSTART CDEND BUFPTR
Command/Definition Area Start Register Command/Definition Area End Register Buffer Pointer Register Reserved
SCICTLP RXBUFP TXBUFP OPSTATE CDFLAGS CPCTL1 CPCTL2 CPCTL3 CPPRE WDRST PACTPRI
PACT-SCI Control Register PACT-SCI RX Data Register PACT-SCI TX Data Register Output Pins 1-8 State Register Command/Definition Entry Flags Register Setup CP Control Register 1 Setup CP Control Register 2 Setup CP Control Register 3 CP Input Control Register WD Reset Key Global Function Control Register
Controls the functions of the mini-SCI Contains the data received by the SCI Contains the data to be transmitted by the SCI Contains information about the current state of the output pins Contains information about the command/definition interrupts Controls the functions of the CP1 and CP2 pins Controls the functions of the CP3 and CP4 pins Controls the functions of the CP5 and CP6 pins Controls input and output functions Location that is written to when serving the WD Controls the WD time-out rate, the PACT interrupt priority levels, and the PACT operating mode
The PACT module is controlled not only by the peripheral file but also by the defined areas of the dual-port RAM. Refer to Section 15.3 on page 15-9 for more information on the dual-port RAM.
15-4
PACT Operation
15.2 PACT Operation
The following subsections describe the functions and options of the PACT module.
15.2.1 Hardware Pins
The PACT module has 16 external hardware pins allocated to its functions. There are three groups of pins:
-
Input Pins. The input or capture pins are CP1 to CP6. The function of these pins depends on the mode selected:
Mode A CP1-2 CP3-6 CP6 Dedicated capture Circular buffer capture Event pin CP1-4 CP5-6 CP6 Mode B Dedicated capture Circular buffer capture Event pin
-
Output pins. There are eight output pins: OP1-OP8. SCI receive/transmit pins. The PACT module has two pins for the miniSCI: SCIRXD (receive data) and SCITXD (transmit data).
In the TMS370Cx32 devices, the input pins CP3, CP4, and CP5 are internally bonded with I/O pins D4, D6, and D7 respectively. In the TMS370Cx36 devices, the input pins CP1, CP4, CP5, and CP6 are internally bonded with I/O pins D5, D4, D7, and D6 respectively, giving you a software-governed choice of function. Output pins (OP1-8) are initialized to a logic low on reset.
15.2.2 Memory Organization
To use the PACT module, you must set up three distinct areas of memory:
-
128 bytes of dual-port RAM contain the capture registers, the circular buffer, and a command/definition area. Dual-port RAM is described in Section 15.3 on page 15-9. Peripheral file frame 4 contains the hardware registers used for initial setup. These registers are described in Section 15.11 on page 15-36. Three groups of interrupt vectors are available. To use interrupts, you must set up the interrupt vectors. Interrupts are described in Section 15.7 on page 15-29.
The memory map in Figure 15-2 is a typical implementation of the PACT module.
Programmable Acquisition and Control Timer (PACT)
15-5
PACT Operation
Figure 15-2. TMS370 Memory Map Highlighting PACT Areas of the 'Cx36 and 'Cx32
TMS370Cx36
256 bytes register (0000h-00FFh) 128 bytes dual ported (0180h-01FFh) 256 bytes standby RAM (0200h-02FFh) 0000h RAM (0000h-0FFFh) 0FFFh 1000h 10FFh 1100h 1FFFh 2000h
TMS370Cx32
128 bytes register (0000h-007Fh) 128 bytes dual ported (0080h-00FFh) Peripheral frame (1040h-104Fh)
Peripheral file frame Data EEPROM
Peripheral frame (1040h-104Fh)
Expansion
3FFFh 4000h
Internal program memory
PACT interrupt vectors (7F9Ch-7FBFh)
7F9Bh 7F9Ch 7FFFh 8000h
PACT interrupt vectors
. . .
PACT interrupt vectors (7F9Ch-7FBFh)
FFFFh
15-6
PACT Operation
15.2.3 Time Base
The time-base section of PACT is similar to that used in traditional timers. The microcontroller system clock is routed to a prescaler that feeds a hardware counter. The prescale section consists of a 4-bit prescaler and an optional divide-by-8 circuit, as shown in Figure 15-3. The hardware counter is 20 bits wide.
Figure 15-3. Prescaler Circuit
Divide by 8
System clock
Prescaler (4 bits)
PACT time base
The divide rate is the binary value of the 4-bit prescaler plus one except for the value zero which, by hardware, provides a divide rate of two. The five bits that control the prescaler are located in the PACTSCR register at address 1040h. Refer to subsection 15.11.1, on page 15-38, for more information.
PACT PRESCALE SELECT Bits 3210 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Divide Rate FAST MODE SELECT Bit Value =1 2 2 3 4 5 6 7 8 =0 16 16 24 32 40 48 56 64 PACT PRESCALE SELECT Bits 3210 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Divide Rate FAST MODE SELECT Bit Value =1 9 10 11 12 13 14 15 16 =0 72 80 88 96 104 112 120 128
15.2.4 Command/Definition File Format
All entries in the command/definition area are 32 bits in length. Normally, commands are executed sequentially starting with entry zero (0), the entry next to the circular buffer. Each entry requires a specified number of time slots (the command/definition descriptions in Section 15.6, on page 15-21, explain the number of time slots required for each command).
15.2.5 Available Time Slots
The number of time slots available to you, and thus the number of definitions/ commands allowed, is controlled by the crystal frequency and the resolution
Programmable Acquisition and Control Timer (PACT)
15-7
PACT Operation
required by PACT functions. Therefore, you must balance these factors to suit your application. The PACT prescaler value determines the number of slots available. The prescaler gives the ratioed crystal frequency against resolution achievable by the PACT. Table 15-2 defines the maximum number of time slots available for all prescaler options.
Table 15-2. Number of Time Slots Available for Each Prescale Setting
Divide Rate -- 2 3 4 5 6 7 8 9 10 Time Slots -- 2 5 9 12 15 19 21 25 29 Divide Rate 11 12 13 14 15 16 24 32 40 48 Time Slots 31 35 38 41 45 48 74 101 127 153 Divide Rate 56 64 72 80 88 96 104 112 120 128 Time Slots 179 205 231 257 283 309 336 362 389 415
If your application requires a prescaler value that does not provide sufficient time slots, you can use the STEP command to cut in half the resolution of all commands later in the command/definition area. The STEP command affects the second entry after the entry that contains the command. (An example of PACT.H commands is in Section I.3 in Appendix I on page I-5). For example, if 10 entries exist in the command file and entry 2 contains a STEP instruction, then commands 0-3 run at full resolution, but 4-9 run at half resolution. Note that this use of the STEP command affects all operations, including the clocking of virtual and offset timers. Repeated use of the STEP instruction within a command file is not necessary--the commands run at either full or half speed (no slower). Note: Consideraton Using STEP Command
When you use STEP, the end address of the command/definition area must be programmed as the next to last address that will be executed.
15-8
Dual-Port RAM
15.3 Dual-Port RAM
The PACT is a RAM-based module that occupies an area of the internal RAM. The size of the RAM is determined by the functions that you select, according to the end device. For the TMS370Cx32 devices, the dual-port RAM is located in the register file from 0080h to 00FFh. This gives the CPU maximum speed in accessing the registers in the register file when you use the register address mode. For the TMS370Cx36 devices, the dual-port RAM is located in the memory map from 0180h to 01FFh. The dual-port RAM contains the following major areas:
-
Command/definition area. The length of the command/definition area (described in Section 15.6 on page 15-21) is defined in the software. Four bits define the start, and five bits define the end of the command area. The two least significant bits (LSBs) are not defined, because this area must start and finish on a 32-bit boundary. The start address of the command area also defines the length of the circular buffer because the buffer resides between the last dedicated storage location and the start of the command area. For the TMS370Cx32 devices, all RAM at lower addresses than the end of the command area can be used for general purposes such as registers, stack, etc. However, since all of the RAM locations above the end (0080h-00FFh) are also within the register file, the data in these locations can be directly manipulated with normal register-based instructions. For the TMS370Cx36 devices, all RAM between 0180h and the end of the command area can be used for data memory storage, program instructions, or a general purpose register. However, all of the RAM locations above the end (0180h-01FFh) can be used only as data memory storage.
-
Circular buffer. The circular buffer is an area in memory that stores the value of a PACT timer when a capture request is made. As new values are captured, they are put into successive locations in the buffer. When the buffer is full, the oldest captures are replaced with newer captures. The length of the circular buffer is defined in the software. The circular buffer resides between the command/definition area and the capture registers.
-
Capture registers. One of the major differences between the PACT module and standard timers is the location of the 32-bit capture registers in dual-port RAM. These locations can be read from or written to by the CPU.
Programmable Acquisition and Control Timer (PACT)
15-9
Dual-Port RAM
They are automatically written to by PACT when the appropriate feature is enabled. The capture registers reside between the circular buffer and the timer and event counter images. For more information about the input capture pins, refer to Section 15.4 on page 15-12. The addresses 00FCh-00FFh (TMS370Cx32 devices) and 01FCh-01FFh (TMS370Cx36 devices) of the dual-port memory contain an image of the 20-bit default timer and an image of the 8-bit event counter. Since they are images or copies of the actual hardware registers, they can be overwritten by the application software. However, they are rewritten every time the PACT module receives another prescaled clock. The dual-port RAM is 128 bytes long as shown in Figure 15-4.
Figure 15-4. Dual-Port RAM Organization
Mode A 0x80h General-purpose RAM Command end Command/definition area Command start Circular buffer Circular buffer Command/definition area 0x80h General-purpose RAM Mode B
0xE8h 0xECh 0xF0h 0xF4h 0xF8h 0xFCh 0xF3h 0xF7h 0xFBh 0xFFh 0xF0h 0xF4h 0xF8h 0xFCh
EVT CNT EVT CNT EVT CNT EVT CNT EVT Image
Capture by CP4 Capture by CP3 Capture by CP2 Capture by CP1 20-bit timer image
0xEBh 0xEFh 0xF3h 0xF7h 0xFBh 0xFFh
EVT CNT EVT CNT EVT Image
Capture by CP2 Capture by CP1 20-bit timer image
For TMS370Cx32 devices, the dual-port RAM is located at addresses 0080h-00FFh. For TMS370Cx36 devices, the dual-port RAM is located at addresses 0180h-01FFh.
Mode A provides two, and Mode B provides four dedicated 32-bit storage locations, which follow a circular storage buffer. Modes A and B are described in Section 15.4 on page 15-12.
15-10
Dual-Port RAM
The PACT module uses memory starting from the highest address going to lower addresses. For the TMS370Cx32 devices, the highest address of the PACT module's dual-port RAM is 00FFh. For TMS370Cx36 devices, the highest address of the PACT module's dual-port RAM is 01FFh. The first 32-bit block always contains an image of the 20-bit default timer, a copy of the flag bits for capture pins 3 to 6, and an image of the 8-bit event counter. Thereafter, allocation depends on the mode selected.
Programmable Acquisition and Control Timer (PACT)
15-11
Inputs
15.4 Inputs
The PACT module has six input capture pins (CP1 through CP6) that cause data to be stored into fixed locations. Each location is defined by the pin that triggers the capture. When triggered directly from the pin, capture values are 32 bits long and consist of the 20-bit hardware timer, the 8-bit event counter, and four extra bits that identify the pin that caused the capture in the circular buffer:
Event counter
D31
Pin ID
D23 D19
20-bit default timer triggered by input pin CPx
D0
The pin ID is set according to which input caused the capture. Only one of these bits will be set:
Bit D20 = 1 D21 = 1 D22 = 1 D23 = 1 Transition on Pin CP3 CP4 CP5 CP6 Result Causes the capture Causes the capture Causes the capture Causes the capture
Each input capture pin has a rising edge select bit, a falling edge select bit, and an interrupt enable bit, along with a fourth bit that acts as a flag to cause an interrupt. Table 15-3 lists these bits for each of the pins; the bits are described in Section 15.11 on page 15-36.
Table 15-3. Bits That Control Functions on the Input Capture Pins
Pin CP1 CP2 CP3 CP4 CP5 CP6 Rising Edge Select Bit CP1 CAPT RISING EDGE (CPCTL1.1) CP2 CAPT RISING EDGE (CPCTL1.5) CP3 CAPT RISING EDGE (CPCTL2.1) CP4 CAPT RISING EDGE (CPCTL2.5) CP5 CAPT RISING EDGE (CPCTL3.1) CP6 CAPT RISING EDGE (CPCTL3.5) Falling Edge Select Bit CP1 CAPT FALLING EDGE (CPCTL1.0) CP2 CAPT FALLING EDGE (CPCTL1.4) CP3 CAPT FALLING EDGE (CPCTL2.0) CP4 CAPT FALLING EDGE (CPCTL2.4) CP5 CAPT FALLING EDGE (CPCTL3.0) CP6 CAPT FALLING EDGE (CPCTL3.4) Interrupt Enable Bit CP1 INT ENA (CPCTL1.3) CP2 INT ENA (CPCTL1.7) CP3 INT ENA (CPCTL2.3) CP4 INT ENA (CPCTL2.7) CP5 INT ENA (CPCTL3.3) CP6 INT ENA (CPCTL3.7) Interrupt Flag Bit CP1 INT FLAG (CPCTL1.2) CP2 INT FLAG (CPCTL1.6) CP3 INT FLAG (CPCTL2.2) CP4 INT FLAG (CPCTL2.6) CP5 INT FLAG (CPCTL3.2) CP6 INT FLAG (CPCTL3.6)
When you select the rising or falling edge, or both, the capture function for that pin is enabled, and the timer value captured is stored in the location that is determined by the mode of operation.
15-12
Inputs
Two operating modes are available for the PACT module: mode A and mode B. You can select between these modes according to the capture functions that you need (refer to Figure 15-5):
-
Mode A offers two dedicated capture locations (associated with pins CP1 and CP2) plus four other pins (CP3-CP6), each with a programmable prescaler to store 32-bit data in the circular buffer. The prescaler rate is the same for all of the four pins (CP3-CP6). Pin CP6 also clocks the 8-bit event counter. Mode B offers four dedicated capture locations (associated with pins CP1-CP4). Pins CP3-CP6 have a programmable prescaler. Pin CP5 can capture 32-bit data in the circular buffer when the software defined edge occurs. The remaining capture pin, CP6, clocks the 8-bit event counter and can capture 32-bit data in the circular buffer.
-
Figure 15-5. Input Capture Block Diagram
PACT prescaled clock
External pin connections
20-bit timer/counter 8-bit event counter
CP1 CP2
Dedicated capture register 1 Dedicated capture register 2 Dedicated capture register 3 Dedicated capture register 4
CP3 CP4 CP5 CP6 Event only 3-bit prescaler Circular buffer (32-bit captures)
Mode
Captures can be set to occur on the falling, rising, or both edges of the input signal. Capture pins CP3 through CP6 can be prescaled with a divide value from 1 to 8. Each of these four pins has its own edge counter, but the maximum count value (1- 8) before an actual capture occurs must be the same for all four pins.
Programmable Acquisition and Control Timer (PACT)
15-13
Inputs
Since it takes several system clock periods for the CPU to read a 20-bit timer capture value, an additional capture could occur while the original capture is being read. Your program can detect this situation by clearing the capture flag in the peripheral file before the read and then verifying that the flag has not been set again after the read is complete. If the flag was set again, the value read may be invalid and should be reread. The buffer pointer (BUFPTR register) is available to tell the program when the last capture value was stored. You can modify the buffer pointer under processor control. Note: Circular-Buffer Area Captures
The 16-bit captures in the circular buffer area are available when triggered by commands in the command/definition area. A 32-bit capture can overwrite the last 16-bit capture if the 16-bit capture is located at the two higher addresses (address bit1 = 1) of a 32-bit block.
15-14
Control and Outputs
15.5 Control and Outputs
The control and outputs section of PACT is, perhaps, the most unique and most powerful part of this timer. Figure 15-6 shows the output control section of the PACT block diagram.
-
The controller acts like a state machine and starts when it receives a rising edge from the PACT prescaled clock. The controller reads its commands (or state microcode) from the command definition part of the dual-port RAM. The 8-bit event counter and the 16 LSBs of the 20-bit default counter are also input into the controller for use in comparisons. The outputs from the controller set or clear the eight output pins (OP1-8). The prescaled clock from the PACT time base is used only to start the controller.
The controller steps through its commands, using the system clock phases for synchronization. The controller must step through all of the commands in the command/definition area before the next rising edge of the prescaled clock. The next prescaled clock increments the 20-bit default counter and restarts the whole process.
Figure 15-6. Output Control Section
PACT prescaled clock 20-bit timer/counter Command/defintion area
8-bit event counter
16
Crystal clock
Command analyzer and output controller
Outputs Int level 1 Int level 2
Programmable Acquisition and Control Timer (PACT)
15-15
Control and Outputs
15.5.1 Standard Compare Command
To use the controller, you should understand the commands that it can execute. All of the commands or definitions in the command/definition area are 32 bits long. The simplest command is the standard compare command. The standard compare command sets or clears an output pin whenever the timer/ counter is equal to a certain value. As shown in Figure 15-7, the standard compare command consists of the following:
-
A 16-bit compare value Three bits to select one of the eight output pins Bits to select what action to take Bits to distinguish this command from the others
For more information or actual bit definitions, refer to subsection 15.6.4 on page 15-25.
Figure 15-7. Standard Compare Command
20-bit timer/counter Command/definition area Standard compare command Action Pin Timer compare selection value (16 bits)
8-bit event counter
STD compare CMD STD compare CMD
16
Outputs OP1
Command analyzer and output controller
Int level 1 Int level 2
OP8
Actions
Pin select
Timer compare value
The standard compare command can:
15-16
Set or clear the chosen output pin when the counter matches the compare value, Execute the opposite action (clear or set) when the 16 LSBs of the counter are equal to zero, or Generate an interrupt when the compare value is reached.
Control and Outputs
Therefore, you can make a pulse-width modulated (PWM) output of limited usefulness using a standard compare command. Assume that you want a PWM output with an initial duty cycle of 75 percent. Using the standard compare command, conduct the following:
15.5.2 Virtual Timers
Set the timer compare value to 4000h (1/4 the overflow rate) Set the actions to cause an output pin to go high when the count is equal to the compare value, and then low again when the 16 LSBs of the counter are zero. Vary the duty cycle by changing the 16-bit compare value. Invert the signal by selecting clear on compare equal, as opposed to set on compare equal.
You cannot use this command to vary the period of the PWM.
You can vary the period of the PWM by using a virtual timer. Remember that the command/definition area is implemented in RAM. Figure 15-8 shows the virtual timer definition and its implementation. The virtual timer definition consists of the following:
-
16 bits that are read, incremented, and rewritten on each tic of the PACT clock. 13 bits that define a maximum value. When the virtual timer reaches this maximum value, it is reset to zero.
Figure 15-8. Virtual Timer Implementation
20-bit timer/counter Command/definition area STD compare CMD STD compare CMD virtual timer STD compare CMD 16 Virtual timer definition Max virtual timer VAL 9-bits Outputs OP1 Command analyzer and output controller Max VAL 3-bits Virtual timer value 16-bits
8-bit event counter
Int level 1 Int level 2
OP8
Maximum virtual timer value
Virtual timer value
Programmable Acquisition and Control Timer (PACT)
15-17
Control and Outputs
For more information about the actual bit definitions, refer to subsection 15.6.1 on page 15-22. The command/definition area in Figure 15-8 shows two standard compare commands, a virtual timer definition, and a third standard compare command. Assume that you are using a microcontroller with a 200-ns (5-MHz) internal system clock and that you are prescaling the PACT clock with divide by five so that each PACT clock tic is one microsecond.
-
The first two standard compare commands generate PWM signals of variable duty cycle with a period of 65 536 prescaled clock tics (65.536 ms). If you want the third PWM to have a period of one millisecond, set up the virtual timer with a maximum value of 1000. When the controller sees the timer definition, it increments the virtual timer and then uses the virtual timer value for future comparisons. The third standard compare command generates a PWM of variable duty cycle with a period of one millisecond.
You can use combinations of standard compare commands and virtual timers to create complex repeating waveforms. Multiple standard compare commands can be used on a single output pin to create multiple pulses of different duration. You can use virtual timers to provide periodic interrupts to the processor.
15.5.3 Double Event Compare Command
Actions can also be taken as determined by comparisons to the 8-bit event counter. Since all commands are 32 bits wide, the double event compare command actually defines two event compare values and the actions that can be performed based on each value. The actions that are allowed according to the event 1 compare value matching the event counter are as follows:
15-18
Setting or resetting the selected output pin (OP1-OP8), Generating an interrupt, or Generating a 32-bit capture into the circular buffer.
The actions that are allowed according to the event 2 compare value matching the event counter are as follows: Setting or resetting the selected output pin (OP1-OP8), Generating an interrupt, Generating a 32-bit capture into the circular buffer, or Resetting the 20-bit default timer.
Control and Outputs
Because of synchronization, these actions occur two or three prescaled clock cycles after the input edge that incremented the event counter. A block diagram of the double-event compare command is shown below. This diagram shows the information contained in the command. For more information or actual bit definitions, refer to subsection 15.6.5 on page 15-26.
Event 1 actions Event 2 actions Pin select Event 2 compare value Event 1 compare value
So far, you can manipulate output lines depending on time values or the number of external events. An additional virtual timer definition allows you to manipulate output lines according to a combination of the event counter and time.
15.5.4 Offset Timer Definition--Time From the Last Event
The offset timer definition--time from the last event--creates a 16-bit virtual timer that is cleared on each occurrence of an event on pin CP6. This definition also sets an event counter maximum, so that the event counter is reset after reaching this maximum value. The offset timer definition can perform the following actions:
-
Generate an interrupt when the maximum event count is reached, Store the 16-bit virtual timer in the circular buffer on each event, Store the 20-bit default timer and 8-bit event counter in the circular buffer when the maximum event count is reached, or Reset the 20-bit hardware default timer when the maximum event count is reached.
A block diagram of the offset timer definition is shown below. This diagram shows the information contained in the command. For more information or actual bit definitions, refer to subsection 15.6.2 on page 15-23.
Maximum event value Actions Virtual timer value
Programmable Acquisition and Control Timer (PACT)
15-19
Control and Outputs
15.5.5 Conditional Compare Command
A special compare command, conditional compare, has a timer compare value and an event compare value. Both of these values must match for the defined action to take place. Usually, a series of these commands follows an offset-timer definition time from the last event, and provides output pulses on different pins, based on the event count and an elapsed time from the event. The conditional compare command generates the following actions:
-
Generates an interrupt when both the following two conditions are met:
J J
The event compare value equals the event counter. The timer compare value equals the last defined timer.
Sets or clears one of seven output pins (OP1-OP7) when the following two conditions are met:
J J
The event compare value equals the event counter. The timer compare value equals the last defined timer.
The actions described above can be enabled on the event counter reaching the event compare value plus one, regardless of the timer compare value. This allows for when the next event occurs before the delay period (specified by the timer compare value ) is reached. A block diagram of the conditional compare command is shown below. This diagram shows the information contained in the command. For more information or actual bit definitions, refer to subsection 15.6.6 on page 15-28.
Event compare value Actions Pin select Timer compare value
15.5.6 Baud Rate Timer Definition
The last item that can be put into the command/definition area of the PACT module is a baud rate virtual timer. This virtual timer runs the serial communications port built into the PACT module. Set up the maximum timer value for one-quarter bit period of the desired bit rate. Separate timers can be defined for transmit and receive. For more information on the baud rate timer definition, see subsection 15.6.3 on page 15-24. For more information about the SCI, see subsection 15.9 on page 15-32.
One quarter bit rate value Virtual timer value
15-20
Command/Definition Area
15.6 Command/Definition Area
All commands/definitions are 32 bits long. They are stored in memory with the most significant byte (MSbyte) first. If byte 3 is stored at location N, then byte 0 would be at location N+3. The bits are referenced as D0-D31. This section summarizes the available commands and the number of time slots required for each command. Definitions Virtual timer definition Offset timer definition Baud rate timer definition Commands Standard Compare command Conditional Compare command Double Event Compare command Time Slots 2 2/3 2 Time Slots 1 1 1
Programmable Acquisition and Control Timer (PACT)
15-21
Command/Definition Area
15.6.1 Virtual Timer Definition
Max virtual timer value D31 D22 D19 0 D15 Virtual timer value 0 D0
Requires two time slots. D31-23 Sets the radical of the maximum value of the virtual timer. Used with D20-D22 to specify the maximum value of the virtual timer. The maximum virtual timer value is equal to the desired period minus 2. For example, if you want a timer with a period of 100 PACT prescaled clocks, set the maximum virtual timer value to 98. The virtual timer increments from 0 to 99 and is then reset to 0. Define a further three bits of the maximum value of the virtual timer. Either the MSBs (bits 15-13) of the maximum value if the range bit = 1, or the LSBs (bits 3-1) if the range bit = 0. The undefined bits of the maximum value for the virtual timer are set to 0. Range Bit Used in conjunction with D22-D20 to define the maximum value (see illustration below).
D22-20
D19
Maximum Value Format (D19=0)
0 0 0 D31-D23 = 9-bit radical D22 D21 D20 0
Maximum Value Format (D19=1)
D22 D21 D20 D31-D23 = 9-bit radical 0 0 0 0
D18
Enable--Active = 1 Enables the timer update, and stops or starts the timer.
D17
Interrupt on 0--Active = 1 Sets the interrupt flag when the virtual timer (D15-D1) overflows to zero.
D16 D15-1
This bit must be written as a 0 for this command to be valid. Virtual Timer Value These are the 15 MSBs of a 16-bit virtual timer. This timer is resident at this location, so any write to this address by the CPU modifies the timer value. Because of hardware limitations, the LSB of the virtual timer cannot be read from or written to by the CPU, but it is used by PACT commands such as the Standard Compare command.
D0
15-22
This bit must be written as a 0 for this definition to be valid.
Command/Definition Area
15.6.2 Offset Timer Definition--Time From Last Event
Maximum event counter value D31 0 D19 Virtual timer value 1 D0
Requires two time slots if bit D21 = 0; requires three time slots if bit D21 = 1. D31-24 Event Maximum Value Specifies a maximum for the event counter. Upon reaching this value, the event counter will be reset to zero by the next event on CP6. Interrupt on Event--Active = 1 Sets the interrupt flag when an event on pin CP6 occurs. Default Capture--Active = 1 Captures 32-bit data into the circular buffer when the event counter reaches the maximum value (D31-D24). Virtual Capture--Active = 1 Stores the 16-bit virtual offset timer (defined by this definition) in the circular buffer on every event on CP6 before it is cleared. Reset Default Timer--Active = 1 Clears the default timer when the event counter reaches the maximum value (D31-D24). This bit must be written as a 0 for this definition to be valid. Enable--Active = 1 Enables the timer update. Used to stop and start the timer. Interrupt on Maximum Event--Active = 1 Sets the interrupt flag when the event counter reaches the maximum value (D31-D24). Step--Active = 1 Allows lower resolution on the following commands in this definition area (see subsection 15.2.5, on page 15-7, for details on the use of this function). Virtual Timer Value These are the 15 MSBs of a 16-bit virtual timer. This timer is resident at this location, so any write to this address by the CPU modifies the timer value. Because of hardware limitations, the LSB of the virtual timer cannot be read from or written to by the CPU, but it is used by the PACT commands such as the standard compare command. This bit must be written as a 1 for this definition to be valid.
Programmable Acquisition and Control Timer (PACT)
15-23
D23
D22
D21
D20
D19 D18
D17
D16
D15-1
D0
Command/Definition Area
15.6.3 Baud Rate Timer Definition
Max virtual timer value D31 D22 D19 1 D15 Virtual timer value 0 D0
Requires two time slots. D31-23 Set the radical of the maximum value of the virtual timer. Used with D22-D20 to specify the maximum value of the virtual timer. When the virtual timer reaches the defined value, the next prescaler clock cycle causes the timer to be cleared. The maximum virtual timer value should be set to one quarter of the desired bit time minus 2. For more details, see Section 15.9 on page 15-32. Define a further three bits of the maximum value of the virtual timer. Either the MSBs (bits 13-15) of the maximum value if range bit = 1, or the LSBs (bits 3-1) if range bit = 0. The undefined bits of the maximum value for the virtual timer are set to 0. Range Bit Used in conjunction with D20-D22 (see the illustration below).
D22-20
D19
Maximum Value Format (D19 = 0)
0 0 0 D31-D23 = 9-bit radical D22 D21 D20 0
Maximum Value Format (D19 = 1)
D22 D21 D20 D31-D23 = 9-bit radical 0 0 0 0
D18
RXselect--Active = 1 Selects this timer definition to use for the receive baud-rate generator.
D17
TXselect--Active = 1 Selects this timer definition to use for the transmit baud-rate generator.
D16 D15-1
This bit must be written as a 1 for this definition to be valid. Baud Rate Timer These are the 15 MSBs of a 16-bit virtual timer used as the baud-rate generator. The timer is resident at this location, so any write to this address modifies its value.
D0
This bit must be written as a 0 for this definition to be valid.
15-24
Command/Definition Area
15.6.4 Standard Compare Command
Reserved D31 00 D24 D23 Pin select D20 D17 D15 Timer compare value D0
Requires one time slot. D31-D28 D27 Reserved. Enable Pin--Active = 1 Enables output pin actions on this command. D26 Interrupt on Reset--Active = 1 Sets the interrupt flag when the referred timer is reset to zero. D25 Reset Action Sets or resets the pin defined by D20-D18 when the referred timer is reset to zero. 0 = No action when the referred timer is zero. 1 = When the referred timer is zero, execute the opposite action. D24-23 D22 These bits must be both written as 0s for this definition to be valid. Step--Active = 1 Allows lower resolution on the following commands in this definition area (see subsection 15.2.5, on page 15-7, for details on the use of this function). D21 Compare Action--Set = 1, Clear = 0 Sets or resets the pin defined by D20-D18 when the compare value is matched by the referred timer. D20-18 Pin Selection Select an output pin whose state is modified when the compare value is matched. The pin number is the binary value of D20-D18 (20 = MSB,18 = LSB) plus one. D17 Interrupt on Compare--Active = 1 Sets the interrupt flag when the compare value is matched by the referred timer. D16 Next Command Is a Definition--Active = 1 Indicates that the following entry in the command/definition area is a definition. D15-0 Timer Compare Value These 16 bits provide a timer-compare value. The timer, to which this value is compared, is either the last virtual timer defined above this command or, if no virtual timer has been defined, the default timer.
Programmable Acquisition and Control Timer (PACT)
15-25
Command/Definition Area
15.6.5 Double Event Compare Command
10 D31 D24 D23 Pin select D20 D17 Event 2 compare value D15 Event 1 compare value D0
D8 D7
Requires one time slot. D31 D30 Reserved. Event 2 Default Timer Capture--Active = 1 Stores a 32-bit data capture in the circular buffer when event 2 occurs. D29 Event 1 Default Timer Capture--Active = 1 Stores a 32-bit data capture in the circular buffer when event 1 occurs. D28 Event 2 Default Timer Reset--Active = 1 Resets the default timer when event 2 occurs. D27 Enable pin--Active = 1 Enables the output pin actions for this command. D26 Interrupt on Compare 2--Active = 1 Sets the interrupt flag when event 2 occurs. D25 Compare Action 2--No Action = 0 Inverted Action = 1 Sets or resets the pin defined by pin selection when the event 2 compare value (D8-D15) is matched by the event counter. D24 D23 D22 This bit must be written as a 1 for this command to be valid. This bit must be written as a 0 for this command to be valid. Step--Active = 1 Allows lower resolution on the following commands (see subsection 15.2.5, on page 15-7, for details on the use of this function). D21 Compare Action 1--Set = 1, Clear = 0 Sets or resets the pin defined by pin selection when the event 1 compare value (D7-D0) is matched by the event counter. D20-18 Pin Selection Selects an output pin whose state is modified when the compare value is matched. The pin number is the binary value of D20-D18 (20 = MSB,18 = LSB) + 1 (OP1-OP8).
15-26
Command/Definition Area
D17
Interrupt on Compare 1--Active = 1 Sets the interrupt flag when the event 1 compare value is matched by the event counter.
D16
Next Command Is a Definition--Active = 1 Indicates that the following entry in the command/definition area is a definition.
D15-8
Event 2 Sets an 8-bit value that, when matched by the 8-bit event counter, causes the action defined by D25, D26, D28, and D30.
D7-0
Event 1 Sets an 8-bit value that, when matched by the 8-bit event counter, causes the action defined by D17, D21, and D29.
Programmable Acquisition and Control Timer (PACT)
15-27
Command/Definition Area
15.6.6 Conditional Compare Command
Event counter compare value D31 1 D23 Pin select D20 D17 D15 Timer compare value D0
Requires one time slot. D31-24 Event Compare Value Sets an 8-bit value that is compared with the 8-bit event counter. The actions selected by this command occur under either of the following conditions:
- The event compare value matches the value of the event counter, and the timer compare value matches the referred timer value, or - The same action active bit is set, and the event counter matches the event
compare value + 1. D23 D22 This bit must be written as a 1 for this command to be valid. Same Action--Active = 1 Indicates the same action as compare action when the event counter reaches the event compare value plus one. This allows an action on the next event if the next event occurs before the time value is reached. If Same Action = 0, then there will be no action on event compare + 1. Compare Action--Set = 1, Clear = 0 Sets or resets the pin defined by pin selection when both compare values are matched by the referred timer and the event counter.
D21
D20-18
Pin Selection Select an output pin whose state will be modified when the compare value is matched. The pin number is the binary value of D20-D18 (20 = MSB,18 = LSB) plus one, except the binary value 111, which disables any pin action. Therefore, OP8 is not available for this command. Interrupt on Compare--Active = 1 Sets the interrupt flag when the timer compare value (D0-D15) is matched by the referred timer, and the event compare value (D24-D31) is matched by the event counter. Next Command is a Definition Active = 1 Indicates that the following entry in the command/definition area is a definition. Timer Compare Value These 16 bits provide a timer compare value. The timer, to which this value is compared, is either the last virtual timer defined above this command or, if no virtual timer has been defined, the default timer. This is called the referred timer. The value that you write must be greater than one.
D17
D16 D15-0
15-28
Interrupts
15.7 Interrupts
This section discusses interrupts that are specific to the PACT module. There are three groups of interrupt vectors.
-
The first group is associated with the events on a particular capture pin. The second group is associated with the SCI interrupts, such as the receive buffer full. The third group of interrupts is associated with the absolute position of the command or definition within the RAM area.
The 18 vectors available for PACT functions are located immediately after the trap vectors in the TMS370 address space. Refer to the memory map in Figure 15-9.
Figure 15-9. Interrupt Vector Memory Map
7F9Ch PACT vectors 7FBFh 7FC0h Trap vectors 7FDFh 7FE0h Reserved for factory 7FEBh 7FECh Hardware interrupt vectors 7FFDh 7FFEh 7FFFh Reset vector
As is standard in the TMS370, two levels of priority (1 and 2) exist for each of the three groups of interrupts described above. These interrupt groups can be allocated to one of two interrupt levels:
-
A priority that determines the order in which multiple interrupts within a level are serviced (see Table 15-4). An order for servicing groups on the same level (see Table 5-2, page 5-5).
Interrupts are enabled either in peripheral frame 4 or within the command/definition line. The service routine must clear the flag associated with the interrupt to prevent multiple servicing of the same interrupt.
Programmable Acquisition and Control Timer (PACT)
15-29
Interrupts
Table 15-4. Interrupt Vector Sources
Module PACT (Group 2) PACT (Group 3) Vector Address 7F9Ch, 7F9Dh 7F9Eh, 7F9Fh 7FA0h, 7FA1h 7FA2h, 7FA3h 7FA4h, 7FA5h 7FA6h, 7FA7h 7FA8h, 7FA9h 7FAAh, 7FABh 7FACh, 7FADh 7FAEh, 7FAFh PACT (Group 1) 7FB0h, 7FB1h 7FB2h, 7FB3h 7FB4h, 7FB5h 7FB6h, 7FB7h 7FB8h, 7FB9h 7FBAh, 7FBBh 7FBCh, 7FBDh 7FBEh, 7FBFh 1 is the highest priority. Interrupt Source PACT SCI TXINT PACT SCI RXINT PACT Cmd/Def Entry 0 PACT Cmd/Def Entry 1 PACT Cmd/Def Entry 2 PACT Cmd/Def Entry 3 PACT Cmd/Def Entry 4 PACT Cmd/Def Entry 5 PACT Cmd/Def Entry 6 PACT Cmd/Def Entry 7 PACT Circular Buffer (Half/ Full) PACT CP6 Edge PACT CP5 Edge PACT CP4 Edge PACT CP3 Edge PACT CP2 Edge PACT CP1 Edge PACT Default Timer Overflow Interrupt Flag PACT TXRDY PACT RXRDY CMD/DEF INT 0 FLAG CMD/DEF INT 1 FLAG CMD/DEF INT 2 FLAG CMD/DEF INT 3 FLAG CMD/DEF INT 4 FLAG CMD/DEF INT 5 FLAG CMD/DEF INT 6 FLAG CMD/DEF INT 7 FLAG BUFFER HALF/FULL INT FLAG CP6 INT FLAG CP5 INT FLAG CP4 INT FLAG CP3 INT FLAG CP2 INT FLAG CP1 INT FLAG DEFTIM OVRFL INT FLAG System Interrupt PTXINT PRXINT CDINT0 CDINT1 CDINT2 CDINT3 CDINT4 CDINT5 CDINT6 CDINT7 BUFINT CP6INT CP5INT CP4INT CP3INT CP2INT CP1INT POVRFL INT Priority in Group 2 1 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
Notes: 1) CP1-6 interrupts are caused by the software edge(s) selected for that particular pin in peripheral frame 4. Also, the associated interrupt enable bit in frame 4 must be set for that particular pin. Interrupts set in a command/definition line relate to their position in that area. 2) The entry address is derived from bits 2, 3, and 4 of the address. If the command or definition is at address 006Ch, 006Dh, 006Eh, or 006Fh (32 bits), then 0110 11xx is the binary value of the address. The entry address comes from bits 4-3-2 = 011 = Entry 3. Thus, the vector associated with entry address 3 is used when this command or definition causes an interrupt. For command/definition areas that contain more than eight entries, the entry vectors become overlaid, and the program must determine the correct source. Entry 0 has the same vector as entry 8, so the command/definition at addresses 04Ch, 04Dh, 04Eh, or 04Fh has the same interrupt vector as the command/ definition located at addresses 06Ch, 06Dh, 06Eh, or 06Fh; both are entry 3.
15-30
WD Timer
15.8 WD Timer
At powerup, the WD timer is enabled with the shortest time-out period (bit 9 of default timer). A WD-originated reset is generated when a software-selected bit of the default timer toggles. Three options determine the WD time-out period and a disable WD code. These options are specified according to how bits 0 and 1 of the global function control register (PACTPRI) are configured:
PACT WD PRESCALE SELECT 1 (PACTPRI.1) 0 0 1 1 PACT WD PRESCALE SELECT 0 (PACTPRI.0) 0 1 0 1
Option Selected Reset when bit 9 of default timer toggles Reset when bit 15 of default timer toggles Reset when bit 19 of default timer toggles Disable WD
These bits are described in subsection 15.11.14, on page 15-59. They are available only in privilege mode immediately after powerup. Once a time-out period has been selected as shown above, the alternate key bytes, 55h (first) and AAh must be written to the WDRST register (peripheral frame 4, 104Eh) to avoid issuing a WD-originated reset. The only exception to this occurs when the default counter is cleared by the PACT module. In this case, a WD-originated reset occurs, unless the correct keyword (55h/AAh) has been written since the previous clear. The WD timer is stopped in standby mode and halt mode.
Programmable Acquisition and Control Timer (PACT)
15-31
Mini-Serial Communications Interface (SCI)
15.9 Mini-Serial Communications Interface (SCI)
The mini-SCI works as a simplified full duplex UART by transmitting 8-bit words with a fixed format of one start bit and one stop bit.
-
If parity transmission is required, the parity bit must be calculated by the CPU and placed in the transmit buffer as part of the 8-bit word. Parity reception is facilitated by the parity result bit. This bit allows the processor to check for parity errors by comparing the PACT PARITY bit (SCICTLP.5) against 0 or 1 for even or odd parity. Hence, there is no parity error bit to be checked by the processor. There is no overrun detection. The PACT SCI has a shift register and a buffer register. This gives the program a full data byte reception time to read the previous byte before it is overwritten.
-
During reception, the start bit is detected on the falling edge and then sampled again in the center of the bit to avoid false detection. All other bits are sampled once at their centers. If at least one stop bit is not detected when it is expected, the framing error flag (PACT FE bit, P045.3) is set. This bit remains set until cleared by reset, by SCI software reset, or by writing a zero to it. The bit rate (baud) is determined by setting the maximum virtual timer value to one quarter of the desired bit time minus 2. For example, if the system clock period is 200 ns and the prescale value is 5, then the PACT resolution is 1 s. If a baud of 9600 is desired, the maximum virtual timer value should be: Max Virtual Timer Value 1 + (Baud) (4) (PACT Resolution) * 1 + (9600) (4) (10 ) - 2 + 24
-6
-2
*Where PACT Resolution = SYSCLK x Prescale Value The software selectable bauds (RX and TX can be different) are set up as shown in subsection 15.6.3 on page 15-24. Receive and transmit operations can be stopped or started by using the control bits within the baud rate definition command. The data being received and transmitted is accessed in the same peripheral frame (4) as the control bits are. Received data is held at 1046h; transmitted data at 1047h.
15-32
PWM Example
15.10 PWM Example
The following three-part routine provides an example of how to set up a pulsewidth-modulated signal with the PACT module:
-
The first part defines the bytes that make up the command/definition area. The second part copies the command/definition area bytes from ROM to the dual-port RAM. The third part sets up the PACT peripheral file.
Refer to Example 15-1, on page 15-34, as you read the following subsections.
15.10.1 Defining the Command/Definition Area
The macro file PACT.H (Example 15-1, page 15-34) simplifies the task of setting up the command/definition area. (Appendix I of this manual further describes PACT.H macros.) Since this file is subject to change as improvements are found, TI recommends that you download the latest version of this file from the microcontroller bulletin board. To set up the PWM signal,
-
A virtual timer definition must establish the timer period. A standard compare command must follow to determine the period and the polarity of the signal. An additional standard compare command must be inserted at the beginning with only the D16 bit set. This is because the PACT command/definition area cannot start with a definition. Line 8 of the routine causes the bytes that will become the commands and definitions to be located in a separate section. In this example, this section starts at location 7800h. Line 10 is the dummy standard compare command. Line 11 defines the virtual timer. The period is set to 1000 s, and the virtual timer enabled. Note that the macro takes care of subtracting two from the maximum count value as it creates the proper byte sequence. Line 12 is the standard compare command that sets the period to 800 s or 80%, and selects output pin 1. The default value sets the pin high on a compare equal and opp_act is selected to cause the pin to go low when the timer is reset. Notice how multiple actions are concatenated with the | operator in this command.
Programmable Acquisition and Control Timer (PACT)
15-33
PWM Example
Example 15-1. Routine to Perform a PWM FOR 'X32
0001 0002 0003 0004 0005 0006 0007 0008 0009 0010 0001 0011 0001 0012 0001 0013 0014 0015 0016 0017 0018 0019 0020 0021 0022 0023 0024 0025 0026 0027 0028 0029 0030 0031 0032 0033 0034 0035 ;This is an example program to do PWM using the PACT module .include "PACT.H" ;MACRO DESCRIPTION ;stdcmp ,, ;virtmr ,, .sect "pact",7800h ;PACT instructions to do PWM table stdcmp 0,0,nxt_def # .byte 0,0,1,0 virtmr 1000,enable # .byte 0,0,52,31 stdcmp 800,op1,opp_act|enable # .byte 32,3,0,10 len .equ $-table .text cmd_st .equ 6000h 0EBh
;dummy cmd, next line = def ;period = 1000 uSec ;80% duty, pin 1
start mov #7,P04F ;copy PACT commands/def. into ram mov #len,b movw #(cmd_st-len+1),r3 loop mov table-1[b],a mov a,*r3 inc r3 djnz b,loop
;for 'x36 device, replace 0EBh with 1EBH ;disable the WD ;length of cmd/def area ;R2:R3 points to area
;set up the peripheral file mov #07,p04f ;set to mode B mov #cmd_st,p041 ;cmd/def start at 0ebh mov #(cmd_st-len+1),p042 ;cmd/def end = 0E0h ;set prescale to 5, 1 usec res, enable cmd/def area mov #034h,p040 ;PWM running without processor intervention idle .end
15.10.2 Copying the Command/Definition Area to Dual-Port RAM
Since the dual-port RAM must be initialized after powerup, and the initial values for the command/definition area were defined in nonvolatile memory; they must be copied from the nonvolatile memory to the dual-port RAM. Since the PACT module works through memory from high addresses to lower addresses, and the assembler works through memory from low addresses to higher addresses, this routine flips the memory table as it is copied into the dual-port RAM. This makes the table easier to read.
15-34
PWM Example
Two variables must be defined before this routine is used.
-
The first variable, cmd_st, is the start of the command/definition area (the largest address in that area). Its value is dependent on the mode used and on the size of the desired circular buffer. cmd_st is defined in line 16 of this routine (Example 15-1). The second variable, len, is defined in line 13 as the number of bytes in the command/ definition area.
15.10.3 Initializing the PACT Peripheral Frame
The last part of the PWM routine sets up the PACT peripheral frame. 1) Line 27 chooses the mode (Example 15-1). 2) Line 28 chooses the command/definition start, and line 29 chooses the command/definition end. 3) The timer resolution is set to one microsecond, and the command/definition area is enabled in line 31. This line causes the PWM signal to start. You should always verify that the PACT clock prescale value allows enough time slots for the entire command/definition area. In this example, four time slots are required--one for each standard compare command and two for the virtual timer definition. The prescale value of 5 provides 12 time slots, which is more than enough for this application.
Programmable Acquisition and Control Timer (PACT)
15-35
PACT Control Registers
15.11 PACT Control Registers
The PACT module is controlled and accessed through registers in peripheral frame 4. These registers are listed in Figure 15-10 and described in the following subsections. The bits shown in shaded boxes in Figure 15-10 are privilege mode bits; they can be written to only in the privilege mode. Note: Inadvertent Modification of an Interrupt Flag
Be careful using the AND, OR, XOR, CMPBIT, SBIT0, or SBIT1 instructions to modify any registers that contain status flags. The read/modify/write nature of these instructions can inadvertently clear an interrupt flag that was set between the read and the write cycles. If the state of the nonflag bits is known, use the MOV #iop8,Pd instruction. If the state of the non-flag bits is not known, use a sequence similar to the example shown below.
; Clearing an interrupt flag MOV P04n,A OR #flag_mask,A ; set all flag bits to one AND #desired_flag,A ; clear the desired flag bit MOV A,P04n
15-36
PACT Control Registers
Figure 15-10. Peripheral File Frame 4: PACT Control Registers
Designation ADDR PF Bit 7 DEFTIM OVRFL INT ENA (RW-0) CMD/DEF AREA INT ENA (RW-0) Bit 6 DEFTIM OVRFL INT FLAG (RC-0) Bit 5 CMD/DEF AREA ENA (RW-0) CMD/DEF AREA START BIT 5 (RW-0) CMD/DEF AREA END BIT 5 (RW-0) BUFFER POINTER BIT 5 (R-1) Bit 4 FAST MODE SELECT (RP-0) CMD/DEF AREA START BIT 4 (RW-0) CMD/DEF AREA END BIT 4 (RW-0) BUFFER POINTER BIT 4 (R-1) Bit 3 PACT PRESCALE SELECT 3 (RP-0) CMD/DEF AREA START BIT 3 (RW-0) CMD/DEF AREA END BIT 3 (RW-0) BUFFER POINTER BIT 3 (R-0) Reserved PACT RXRDY (RC-0) PACT RXDT7 (R-0) PACT TXDT7 (RW-0) PACT OP8 STATE (RW-0) CMD/DEF INT 7 FLAG (RC-0) CP2 INT ENA (RW-0) CP4 INT ENA (RW-0) CP6 INT ENA (RW-0) BUFFER HALF/FULL INT ENA (RW-0) PACT TXRDY (R-1) PACT RXDT6 (R-0) PACT TXDT6 (RW-0) PACT OP7 STATE (RW-0) CMD/DEF INT 6 FLAG (RC-0) CP2 INT FLAG (RC-0) CP4 INT FLAG (RC-0) CP6 INT FLAG (RC-0) BUFFER HALF/FULL INT FLAG (RC-0) PACT PARITY (R-0) PACT RXDT5 (R-0) PACT TXDT5 (RW-0) PACT OP6 STATE (RW-0) CMD/DEF INT 5 FLAG (RC-0) CP2 CAPT RISING EDGE (RW-0) CP4 CAPT RISING EDGE (RW-0) CP6 CAPT RISING EDGE (RW-0) INPUT CAPT PRESCALE SELECT 3 (RW-0) PACT FE (RC-0) PACT RXDT4 (R-0) PACT TXDT4 (RW-0) PACT OP5 STATE (RW-0) CMD/DEF INT 4 FLAG (RC-0) CP2 CAPT FALLING EDGE (RW-0) CP4 CAPT FALLING EDGE (RW-0) CP6 CAPT FALLING EDGE (RW-0) INPUT CAPT PRESCALE SELECT 2 (RW-0) PACT SCI RX INT ENA (RW-0) PACT RXDT3 (R-0) PACT TXDT3 (RW-0) PACT OP4 STATE (RW-0) CMD/DEF INT 3 FLAG (RC-0) CP1 INT ENA (RW-0) CP3 INT ENA (RW-0) CP5 INT ENA (RW-0) INPUT CAPT PRESCALE SELECT 1 (RW-0) PACT SCI TX INT ENA (RW-0) PACT RXDT2 (R-0) PACT TXDT2 (RW-0) PACT OP3 STATE (RW-0) CMD/DEF INT 2 FLAG (RC-0) CP1 INT FLAG (RC-0) CP3 INT FLAG (RC-0) CP5 INT FLAG (RC-0) CP6 EVENT ONLY (RW-0) -- PACT RXDT1 (R-0) PACT TXDT1 (RW-0) PACT OP2 STATE (RW-0) CMD/DEF INT 1 FLAG (RC-0) CP1 CAPT RISING EDGE (RW-0) CP3 CAPT RISING EDGE (RW-0) CP5 CAPT RISING EDGE (RW-0) EVENT COUNTER SW RESET (RW-0) PACT SCI SW RESET (RW-0) PACT RXDT0 (R-0) PACT TXDT0 (RW-0) PACT OP1 STATE (RW-0) CMD/DEF INT 0 FLAG (RC-0) CP1 CAPT FALLING EDGE (RW-0) CP3 CAPT FALLING EDGE (RW-0) CP5 CAPT FALLING EDGE (RW-0) OP SET/CLR SELECT (RW-0) Bit 2 PACT PRESCALE SELECT 2 (RP-0) CMD/DEF AREA START BIT 2 (RW-0) CMD/DEF AREA END BIT 2 (RW-0) BUFFER POINTER BIT 2 (R-0) Bit 1 PACT PRESCALE SELECT 1 (RP-0) Bit 0 PACT PRESCALE SELECT 0 (RP-0)
PACTSCR
1040h
P040
CDSTART
1041h
P041
--
--
--
CDEND
1042h
P042
--
CMD/DEF AREA END BIT 6 (RW-0) 1 (R-1)
--
--
BUFPTR
1043h
P043
1 (R-1)
BUFFER POINTER BIT 1 (R-0)
--
1044h SCICTLP 1045h
P044 P045
RXBUFP
1046h
P046
TXBUFP
1047h
P047
OPSTATE
1048h
P048
CDFLAGS
1049h
P049
CPCTL1
104Ah
P04A
CPCTL2
104Bh
P04B
CPCTL3
104Ch
P04C
CPPRE
104Dh
P04D
WDRST
104Eh
P04E PACT STEST (RP-0) PACT GROUP 1 PRIORITY (RP-0)
WD Reset Key PACT GROUP 2 PRIORITY (RP-0) PACT GROUP 3 PRIORITY (RP-0) PACT MODE SELECT (RP-0) PACT WD PRESCALE SELECT 1 (RP-0) PACT WD PRESCALE SELECT 0 (RP-0)
PACTPRI
104Fh
P04F
--
Programmable Acquisition and Control Timer (PACT)
15-37
PACT Control Registers
15.11.1 Setup Control Register (PACTSCR)
The PACTSCR register determines the time base for the PACT module, enables the command/definition area, and controls the default timer overflow.
Setup Control Register (PACTSCR) [Memory Address 1040h]
Bit #
P040
7
DEFTIM OVRFL INT ENA RW-0
6
DEFTIM OVRFL INT FLAG RC-0
5
CMD/DEF AREA ENA RW-0
4
FAST MODE SELECT RP-0
3
PACT PRESCALE SELECT3 RP-0
2
PACT PRESCALE SELECT2 RP-0
1
PACT PRESCALE SELECT1 RP-0
0
PACT PRESCALE SELECT0 RP-0
R = Read, W = Write, P = Privilege write only, C = Clear, -n = Value of the bit after the register is reset
Bit 7
DEFTIM OVRFL INT ENA. Default Timer Overflow Interrupt Enable. This bit controls the default timer overflow interrupting capability. 0 = Disables interrupt 1 = Enables interrupt
Bit 6
DEFTIM OVRFL INT FLAG. Default Timer Overflow Interrupt Flag. This bit indicates the status of the PACT default timer overflow interrupt. This bit is cleared by reset or when a zero is written to it; it is set by overflow. 0 = Default timer overflow interrupt inactive 1 = Default timer overflow interrupt pending
Bit 5
CMD/DEF AREA ENA. Command and Definition Area Enable. This bit determines if the command/definition area of the dual-port RAM is enabled. This allows the PACT module to use this area for commands and definitions. 0 = Command/definition area is ignored 1 = Enables the commands and definitions
15-38
PACT Control Registers
Bit 4
FAST MODE SELECT. This bit determines if the system clock is divided by 8 before entering into the 4-bit prescale. This bit, as well as the PACT PRESCALE SELECT 0-3 bits, determines the time base for the PACT module. The possible combinations are shown below.
Table 15-5. Bits Determining PACT-Module Time Base
Divide Rate PACT PRESCALE SELECTn Bits 3210 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 FAST MODE SELECT Bit Value =1 2 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 =0 16 16 24 32 40 40 56 64 72 82 88 96 104 112 120 128
Bits 3-0
PACT PRESCALE SELECT3-0. These four bits select a prescaler divide rate for the PACT module. The bits specify the divide of the system clock from /2 to /16, giving 15 possible choices. The actual divide rate is also determined by the value of the FAST MODE SELECT bit. The possible combinations for a FAST MODE SELECT bit in either 1 or 0 are shown in the right half of Table 15-5.
Programmable Acquisition and Control Timer (PACT)
15-39
PACT Control Registers
15.11.2 Command/Definition Area Start Register (CDSTART)
The CDSTART register defines the starting address of the command/definition area and enables the interrupts for that area.
Command/Definition Area Start Register (CDSTART) [Memory Address 1041h]
Bit #
P041
7
CMD/DEF AREA INT ENA RW-0
6
--
5
CMD/DEF AREA START BIT 5 RW-0
4
CMD/DEF AREA START BIT 4 RW-0
3
CMD/DEF AREA START BIT 3 RW-0
2
CMD/DEF AREA START BIT 2 RW-0
1
--
0
--
R = Read, W = Write, -n = Value of the bit after the register is reset
Bit 7
CMD/DEF AREA INT ENA. Command and Definition Area Interrupt Enable. This bit enables interrupts from the command/definition area. 0 = Disables interrupt 1 = Enables interrupt
Bit 6 Bits 5-2
Reserved. Read data is indeterminate. CMD/DEF AREA START BIT 5-2. Command and Definition Area Start Bits 5-2. These bits define the start address of the Command/Definition Area. There are 16 possible locations for this area to start. The address is the same if bits 7, 6, 1, and 0 of this register are set to 1. A table of the bits and their corresponding addresses is shown in Table 15-6.
Bits 1-0
Reserved. Read data is indeterminate.
15-40
PACT Control Registers
Table 15-6. Bits Defining the Command/Definition Area Start Addresses
CMD/DEF AREA START Bits 5 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 4 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 3 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 2 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CMD/DEF Area Start Addresses TMS370Cx36 Address 01C3h 01C7h 01CBh 01CFh 01D3h 01D7h 01DBh 01DFh 01E3h 01E7h 01EBh 01EFh 01F3h 01F7h 01FBh 01FFh TMS370Cx32 Address 00C3h 00C7h 00CBh 00CFh 00D3h 00D7h 00DBh 00DFh 00E3h 00E7h 00EBh 00EFh 00F3h 00F7h 00FBh 00FFh Register R0C3 R0C7 R0CB R0CF R0D3 R0D7 R0DB R0DF R0E3 R0E7 R0EB R0EF R0F3 R0F7 R0FB R0FF invalid invalid invalid Notes
Invalid in Mode B.
Programmable Acquisition and Control Timer (PACT)
15-41
PACT Control Registers
15.11.3 Command/Definition Area End Register (CDEND)
The CDEND register defines the end address of the command/definition area.
Command/Definition Area End Register (CDEND) [Memory Address 1042h]
Bit #
P042
7
--
6
CMD/DEF AREA END BIT 6 RW-0
5
CMD/DEF AREA END BIT 5 RW-0
4
CMD/DEF AREA END BIT 4 RW-0
3
CMD/DEF AREA END BIT 3 RW-0
2
CMD/DEF AREA END BIT 2 RW-0
1
--
0
--
R = Read, W = Write, -n = Value of the bit after the register is reset
Bit 7 Bits 6-2
Reserved. Read data is indeterminate. CMD/DEF AREA END BIT 6-2. Command/Definition Area End Bits 6-2. These bits define the end address of the command/definition area. There are 32 possible locations for the command/definition area end. The address is the same if bit 7 of this register is set to 1, and bit 1 and bit 0 are set to 0. Table 15-7 lists the bits and their corresponding addresses. Reserved. Read data is indeterminate.
Bits 1-0
15-42
PACT Control Registers
Table 15-7. Bits Defining the Command/Definition Area End Addresses
CMD/DEF Area End Addresses CMD/DEF AREA END BIT 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 5 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 4 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 3 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 2 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 TMS370Cx36 Address 0180h 0184h 0188h 018Ch 0190h 0194h 0198h 019Ch 01A0h 01A4h 01A8h 01ACh 01B0h 01B4h 01B8h 01BCh 01C0h 01C4h 01C8h 01CCh 01D0h 01D4h 01D8h 01DCh 01E0h 01E4h 01E8h 01ECh 01F0h 01F4h 01F8h 01FCh TMS370Cx32 Address 0080h 0084h 0088h 008Ch 0090h 0094h 0098h 009Ch 00A0h 00A4h 00A8h 00ACh 00B0h 00B4h 00B8h 00BCh 00C0h 00C4h 00C8h 00CCh 00D0h 00D4h 00D8h 00DCh 00E0h 00E4h 00E8h 00ECh 00F0h 00F4h 00F8h 00FCh Register R080h R084h R088h R08Ch R090h R094h R098h R09Ch R0A0h R0A4h R0A8h R0ACh R0B0h R0B4h R0B8h R0BCh R0C0h R0C4h R0C8h R0CCh R0D0h R0D4h R0D8h R0DCh R0E0h R0E4h R0E8h R0ECh R0F0h R0F4h R0F8h R0FCh
Programmable Acquisition and Control Timer (PACT)
15-43
PACT Control Registers
15.11.4 Buffer Pointer Register (BUFPTR)
The BUFPTR register defines the address of the buffer pointer.
Buffer Pointer Register (BUFPTR) [Memory Address 1043h]
Bit #
P043
7
1 R-1
6
1 R-1
5
BUFFER POINTER BIT 5 R-1
4
BUFFER POINTER BIT 4 R-1
3
BUFFER POINTER BIT 3 R-0
2
BUFFER POINTER BIT 2 R-0
1
BUFFER POINTER BIT 1 R-0
0
0 R-0
R = Read, -n = Value of the bit after the register is reset
Bits 7-6 Bits 5-1
Reserved. BUFFER POINTER BIT 5-1. These bits define the address of the buffer pointer that points to the next available address out of 32 possible locations in the circular buffer. These addresses are the same if bit 7 and bit 6 of this register are set to 1, and bit 0 is set to 0. A table of the bits and their corresponding addresses are listed in Table 15-8. Reserved.
Bit 0
15-44
PACT Control Registers
Table 15-8. Buffer Pointer Address Generation
Buffer Pointer Buffer Pointer Bits 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 3 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 TMS370Cx36 Address 01C0h 01C2h 01C4h 01C6h 01C8h 01CAh 01CCh 01CEh 01D0h 01D2h 01D4h 01D6h 01D8h 01DAh 01DCh 01DEh 01E0h 01E2h 01E4h 01E6h 01E8h 01EAh 01ECh 01EEh 01E0h 01F2h 01F4h 01F6h 01F8h 01FAh 01FCh 01FEh TMS370Cx32 Address 00C0h 00C2h 00C4h 00C6h 00C8h 00CAh 00CCh 00CEh 00D0h 00D2h 00D4h 00D6h 00D8h 00DAh 00DCh 00DEh 00E0h 00E2h 00E4h 00E6h 00E8h 00EAh 00ECh 00FEh 00F0h 00F2h 00F4h 00F6h 00F8h 00FAh 00FCh 00FEh Register R0C0h R0C2h R0C4h R0C6h R0C8h R0CAh R0CCh R0CEh R0D0h R0D2h R0D4h R0D6h R0D8h R0DAh R0DCh R0DEh R0E0h R0E2h R0E4h R0E6h R0E8h R0EAh R0ECh R0EEh R0F0h R0F2h R0F4h R0F6h R0F8h R0FAh R0FCh R0FEh
Programmable Acquisition and Control Timer (PACT)
15-45
PACT Control Registers
15.11.5 PACT-SCI Control Register (SCICTLP)
The SCICTLP register controls the functions of the mini-SCI.
PACT-SCI Control Register (SCICTLP) [Memory Address 1045h]
Bit #
P045
7
PACT RXRDY RC-0
6
PACT TXRDY R-1
5
PACT PARITY R-0
4
PACT FE RC-0
3
PACT SCI RX INT ENA RW-0
2
PACT SCI TX INT ENA RW-0
1
--
0
PACT SCI SW RESET RW-0
R = Read, W = Write, C = Clear, -n = Value of the bit after the register is reset
Bit 7
PACT RXRDY. PACT Receive Ready. This bit shows when the receive buffer is full. This bit is cleared by a system reset, by the PACT SCI software reset, when a zero is written to it, or when the SCI RX DATA register is read. 0 = Receive buffer is empty 1 = Receive buffer is full
Bit 6
PACT TXRDY. PACT Transmit Ready. This bit shows when the transmit buffer is empty. This bit is set by a system reset, by the PACT SCI software reset, or when the SCI TX DATA register has been shifted out. 0 = Transmit buffer is full 1 = Transmit buffer is empty
Bit 5
PACT PARITY. PACT Receive Data Parity Bit. This bit is set as the result of the incoming parity calculation. To perform a parity check on incoming data, this bit is compared to a 0 or 1 for even or odd parity respectively. 0 = Received data was even parity 1 = Received data was odd parity
Bit 4
PACT FE. PACT Framing Error. This flag bit shows the detection of a framing error. This bit remains set until cleared by a PACT SCI software reset, by a system reset, or by writing a zero to it. 0 = No framing error 1 = Framing error was detected
15-46
PACT Control Registers
Bit 3
PACT SCI RX INT ENA. PACT SCI Receive Interrupt Enable. This bit enables the interrupt to occur when the receive buffer is full. 0 = Does not generate an interrupt when the receive buffer is full 1 = Generates an interrupt when the receive buffer is full
Bit 2
PACT SCI TX INT ENA. PACT SCI Transmit Interrupt Enable. This bit enables the interrupt to occur when the transmit buffer is empty. 0 = Does not generate an interrupt when the transmit buffer is empty 1 = Generates an interrupt when the transmit buffer is empty
Bit 1 Bit 0
Reserved. Read data is indeterminate. PACT SCI SW RESET. PACT SCI Software Reset. When set, this bit puts the SCI into a software reset state so that the parameters of the SCI can be set up. This bit must be cleared to allow the SCI to function. 0 = SCI in operating mode 1 = SCI in software reset mode
Programmable Acquisition and Control Timer (PACT)
15-47
PACT Control Registers
15.11.6 PACT-SCI RX Data Register (RXBUFP)
This register contains the data received by the SCI.
PACT-SCI RX Data Register (RXBUFP) [Memory Address 1046h]
Bit #
P046
7
PACT RXDT7 R-0
6
PACT RXDT6 R-0
5
PACT RXDT5 R-0
4
PACT RXDT4 R-0
3
PACT RXDT3 R-0
2
PACT RXDT2 R-0
1
PACT RXDT1 R-0
0
PACT RXDT0 R-0
R = Read, -n = Value of the bit after the register is reset
Bits 7-0
PACT RXDT 7-0. PACT Receive Data 7-0.
15.11.7 PACT-SCI TX Data Register (TXBUFP)
This register contains the data to be transmitted by the SCI.
PACT-SCI TX Data Register (TXBUFP) [Memory Address 1047h]
Bit #
P047
7
PACT TXDT7 RW-0
6
PACT TXDT6 RW-0
5
PACT TXDT5 RW-0
4
PACT TXDT4 RW-0
3
PACT TXDT3 RW-0
2
PACT TXDT2 RW-0
1
PACT TXDT1 RW-0
0
PACT TXDT0 RW-0
R = Read, W = Write, -n = Value of the bit after the register is reset
Bits 7-0
PACT TXDT 7-0. PACT Transmit Data 7-0.
15-48
PACT Control Registers
15.11.8 Output Pins 1-8 State Register (OPSTATE)
The OPSTATE register contains information about the current state of the output pins.
Output Pin 1-8 State Register (OPSTATE) [Memory Address 1048h]
Bit #
P048
7
PACT OP8 STATE RW-0
6
PACT OP7 STATE RW-0
5
PACT OP6 STATE RW-0
4
PACT OP5 STATE RW-0
3
PACT OP4 STATE RW-0
2
PACT OP3 STATE RW-0
1
PACT OP2 STATE RW-0
0
PACT OP1 STATE RW-0
R = Read, W = Write, -n = Value of the bit after the register is reset
Bits 7-0
PACT OP8-1 STATE. PACT Output Pins 8-1 State Bits. These bits reflect the current state of the output pins OP8 to OP1. Each bit is the actual state of the corresponding pin. Writing a 1 to any bit in this register modifies the corresponding output pin as determined by the OP SET/CLR SELECT bit (P04D.0).
Bit OPx Write 1 1 0 OP SET/CLR SELECT 1 0 x Result PACT OPx STATE = 1 PACT OPx STATE = 0 PACT OPx STATE remains unchanged
Upon reset, all pins are initialized to the low state.
Example 15-2. Example 1, if OP SET/CLR SELECT = 1
11001011 OP STATE Register 11110000 Write to OP STATE Register ---------- 11111011 New value in OP STATE Register.
Example 15-3. Example 2, if OP SET/CLR SELECT = 0
11001011 OP STATE Register 11110000 Write to OP STATE Register ---------- 00001011 New value in OP STATE Register.
Programmable Acquisition and Control Timer (PACT)
15-49
PACT Control Registers
15.11.9 Command/Definition Entry Flags Register (CDFLAGS)
The CDFLAGS register contains information about the command/definition interrupts.
Command/Definition Entry Flags Register (CDFLAGS) [Memory Address 1049h]
Bit #
P049
7
CMD/DEF INT 7 FLAG RC-0
6
CMD/DEF INT 6 FLAG RC-0
5
CMD/DEF INT 5 FLAG RC-0
4
CMD/DEF INT 4 FLAG RC-0
3
CMD/DEF INT 3 FLAG RC-0
2
CMD/DEF INT 2 FLAG RC-0
1
CMD/DEF INT 1 FLAG RC-0
0
CMD/DEF INT 0 FLAG RC-0
R = Read, C = Clear, -n = Value of the bit after the register is reset
Bits 7-0
CMD/DEF INT 7-0 FLAG. Command/Definition Interrupt 7-0 Flag. These bits are the interrupt flags for the command/definition area. If an interrupt has been enabled in a 4-byte command or definition, then the appropriate bit in this register will be set when the interrupt conditions are met. The actual bit set is determined by the command or definition's entry address. The entry address is derived from bits 2, 3, and 4 of the address. If the command or definition is at address 006Ch, 006Dh, 006Eh, or 006Fh (32 bits), then 0110 11xx is the binary value of the address. The entry address comes from bits 4-3-2 = 011 = Entry 3. Thus, the flag associated with entry address 3 is used when this command or definition causes an interrupt. These flags are not affected by the CMD/DEF AREA INT ENA bit (CDSTART.7).
CMD/DEF INT FLAG Set CMD/DEF INT 0 FLAG CMD/DEF INT 1 FLAG CMD/DEF INT 2 FLAG CMD/DEF INT 3 FLAG CMD/DEF INT 4 FLAG CMD/DEF INT 5 FLAG CMD/DEF INT 6 FLAG CMD/DEF INT 7 FLAG Command or Definition Entry That Generated Interrupt Request (Entry Address >> 2) ENTRY mod 8 = 0 (Entry Address >> 2) ENTRY mod 8 = 1 (Entry Address >> 2) ENTRY mod 8 = 2 (Entry Address >> 2) ENTRY mod 8 = 3 (Entry Address >> 2) ENTRY mod 8 = 4 (Entry Address >> 2) ENTRY mod 8 = 5 (Entry Address >> 2) ENTRY mod 8 = 6 (Entry Address >> 2) ENTRY mod 8 = 7
15-50
PACT Control Registers
15.11.10 Setup CP Control Register 1 (CPCTL1)
The CPCTL1 register controls the functions of the CP1 and CP2 pins.
Setup CP Control Register 1 (CPCTL1) [Memory Address 104Ah]
Bit #
P04A
7
CP2 INT ENA RW-0
6
CP2 INT FLAG RC-0
5
CP2 CAPT RISING EDGE RW-0
4
CP2 CAPT FALLING EDGE RW-0
3
CP1 INT ENA RW-0
2
CP1 INT FLAG RC-0
1
CP1 CAPT RISING EDGE RW-0
0
CP1 CAPT FALLING EDGE RW-0
R = Read, W = Write, C = Clear, -n = Value of the bit after the register is reset
Bit 7
CP2 INT ENA. CP2 Interrupt Enable. If set, this bit enables the interrupt when the selected edge occurs on pin CP2. 0 = Disables interrupt 1 = Enables interrupt
Bit 6
CP2 INT FLAG. CP2 Interrupt Flag. This bit indicates that the selected edge has occurred on pin CP2. This bit must be cleared by the program during an interrupt routine when CP2 INT ENA is set. 0 = Capture interrupt from selected edge of CP2 inactive 1 = Capture interrupt from selected edge of CP2 pending
Bit 5
CP2 CAPT RISING EDGE. CP2 Capture Rising Edge. This bit selects the rising edge on pin CP2 to cause a timer capture. Table 15-9 describes all possible combinations.
Table 15-9. Rising/Falling Edge Capture Bits
CPx CAPT RISING EDGE 0 0 1 1 CPx CAPT FALLING EDGE 0 1 0 1 Capture on Selected Edges Disables captures Captures on falling edges only Captures on rising edges only Captures on both rising and falling edges
Bit 4
CP2 CAPT FALLING EDGE. CP2 Capture Falling Edge. This bit selects the falling edge on pin CP2 to cause a timer capture. Table 15-9 describes all possible combinations.
Programmable Acquisition and Control Timer (PACT)
15-51
PACT Control Registers
Bit 3
CP1 INT ENA. CP1 Interrupt Enable. If set, this bit enables the interrupt when the selected edge occurs on pin CP1. 0 = Disables interrupt 1 = Enables interrupt
Bit 2
CP1 INT FLAG. CP1 Interrupt Flag. This bit indicates that the selected edge has occurred on pin CP1. This bit must be cleared by the program during an interrupt routine when CP1 INT ENA is set. 0 = Capture interrupt from selected edge of CP1 inactive 1 = Capture interrupt from selected edge of CP1 pending
Bit 1
CP1 CAPT RISING EDGE. CP1 Capture Rising Edge. This bit selects the rising edge on pin CP1 to cause a timer capture. Table 15-9 describes all possible combinations.
Bit 0
CP1 CAPT FALLING EDGE. CP1 Capture Falling Edge. This bit selects the falling edge on pin CP1 to cause a timer capture. Table 15-9 describes all possible combinations.
15-52
PACT Control Registers
15.11.11 Setup CP Control Register 2 (CPCTL2)
The CPCTL2 register controls the functions of the CP3 and CP4 pins.
Setup CP Control Register 2 (CPCTL2) [Memory Address 104Bh]
Bit #
P04B
7
CP4 INT ENA RW-0
6
CP4 INT FLAG RC-0
5
CP4 CAPT RISING EDGE RW-0
4
CP4 CAPT FALLING EDGE RW-0
3
CP3 INT ENA RW-0
2
CP3 INT FLAG RC-0
1
CP3 CAPT RISING EDGE RW-0
0
CP3 CAPT FALLING EDGE RW-0
R = Read, W = Write, C = Clear, -n = Value of the bit after the register is reset
Bit 7
CP4 INT ENA. CP4 Interrupt Enable. If set, this bit enables the interrupt when the selected edge occurs on pin CP4. 0 = Disables interrupt 1 = Enables interrupt
Bit 6
CP4 INT FLAG. CP4 Interrupt Flag. This bit indicates that the selected edge has occurred on pin CP4. This bit must be cleared by the program during an interrupt routine when CP4 INT ENA is set. 0 = Capture interrupt from selected edge of CP4 inactive 1 = Capture interrupt from selected edge of CP4 pending
Bit 5
CP4 CAPT RISING EDGE. CP4 Capture Rising Edge. This bit selects the rising edge on pin CP4 to cause a timer capture. Table 15-10 describes all possible combinations.
Table 15-10. Rising/Falling Edge Capture Bits
CPx CAPT RISING EDGE 0 0 1 1 CPx CAPT FALLING EDGE 0 1 0 1 Capture on Selected Edges Disables captures Captures on falling edges only Captures on rising edges only Captures on both rising and falling edges
Bit 4
CP4 CAPT FALLING EDGE. CP4 Capture Falling Edge. This bit selects the falling edge on pin CP4 to cause a timer capture. Table 15-10 describes all possible combinations.See the table following the bit 1 description for all possible combinations.
Programmable Acquisition and Control Timer (PACT)
15-53
PACT Control Registers
Bit 3
CP3 INT ENA. CP3 Interrupt Enable. If set, this bit enables the interrupt when the selected edge occurs on pin CP3. 0 = Disables interrupt 1 = Enables interrupt
Bit 2
CP3 INT FLAG. CP3 Interrupt Flag. This bit indicates that the selected edge has occurred on pin CP3. This bit must be cleared by the program during an interrupt routine when CP3 INT ENA is set. 0 = Capture interrupt from selected edge of CP3 inactive 1 = Capture interrupt from selected edge of CP3 pending
Bit 1
CP3 CAPT RISING EDGE. CP3 Capture Rising Edge. This bit selects the rising edge on pin CP3 to cause a timer capture. Table 15-10 describes all possible combinations.
Bit 0
CP3 CAPT FALLING EDGE. CP3 Capture Falling Edge. This bit selects the falling edge on pin CP3 to cause a timer capture. Table 15-10 describes all possible combinations.
15-54
PACT Control Registers
15.11.12 Setup CP Control Register 3 (CPCTL3)
The CPCTL3 register controls the functions of the CP5 and CP6 pins.
Setup CP Control Register 3 (CPCTL3) [Memory Address 104Ch]
Bit #
P04C
7
CP6 INT ENA RW-0
6
CP6 INT FLAG RC-0
5
CP6 CAPT RISING EDGE RW-0
4
CP6 CAPT FALLING EDGE RW-0
3
CP5 INT ENA RW-0
2
CP5 INT FLAG RC-0
1
CP5 CAPT RISING EDGE RW-0
0
CP5 CAPT FALLING EDGE RW-0
R = Read, W = Write, C = Clear, -n = Value of the bit after the register is reset
Bit 7
CP6 INT ENA. CP6 Interrupt Enable. If set, this bit enables the interrupt when the selected edge occurs on pin CP6. 0 = Disables interrupt 1 = Enables interrupt
Bit 6
CP6 INT FLAG. CP6 Interrupt Flag. This bit indicates that the selected edge has occurred on pin CP6. This bit must be cleared by the program during an interrupt routine when CP6 INT ENA is set. 0 = Capture interrupt from selected edge of CP6 inactive 1 = Capture interrupt from selected edge of CP6 pending
Bit 5
CP6 CAPT RISING EDGE. CP6 Capture Rising Edge. This bit selects the rising edge on pin CP6 to cause a timer capture. Table 15-11 describes all possible combinations.
Table 15-11. Rising/Falling Edge Capture Bits
CPx CAPT RISING EDGE 0 0 1 1 CPx CAPT FALLING EDGE 0 1 0 1 Capture on Selected Edges Disables captures Captures on falling edges only Captures on rising edges only Captures on both rising and falling edges
Bit 4
CP6 CAPT FALLING EDGE. CP6 Capture Falling Edge. This bit selects the falling edge on pin CP6 to cause a timer capture. Table 15-11 describes all possible combinations.
Programmable Acquisition and Control Timer (PACT)
15-55
PACT Control Registers
Bit 3
CP5 INT ENA. CP5 Interrupt Enable. If set, this bit enables the interrupt when the selected edge occurs on pin CP5. 0 = Disables interrupt 1 = Enables interrupt
Bit 2
CP5 INT FLAG. CP5 Interrupt Flag. This bit indicates that the selected edge has occurred on pin CP5. This bit must be cleared by the program during an interrupt routine when CP5 INT ENA is set. 0 = Capture interrupt from selected edge of CP5 inactive 1 = Capture interrupt from selected edge of CP5 pending
Bit 1
CP5 CAPT RISING EDGE. CP5 Capture Rising Edge. This bit selects the rising edge on pin CP5 to cause a timer capture. Table 15-11 describes all possible combinations.
Bit 0
CP5 CAPT FALLING EDGE. CP5 Capture Falling Edge. This bit selects the falling edge on pin CP5 to cause a timer capture. Table 15-11 describes all possible combinations.
15-56
PACT Control Registers
15.11.13 CP Input Control Register (CPPRE)
The CPPRE register controls input and output functions.
CP Input Control Register (CPPRE) [Memory Address 104Dh]
Bit #
7
BUFFER HALF/FULL INT ENA RW-0
6
BUFFER HALF/FULL INT FLAG RC-0
5
INPUT CAPT PRESCALE SELECT3 RW-0
4
INPUT CAPT PRESCALE SELECT2 RW-0
3
INPUT CAPT PRESCALE SELECT1 RW-0
2
CP6 EVENT ONLY RW-0
1
EVENT COUNTER SW RESET RW-0
0
OP SET/CLR SELECT RW-0
P04D
R = Read, W = Write, C = Clear, -n = Value of the bit after the register is reset
Bit 7
BUFFER HALF/FULL INT ENA. Buffer Half/Full Interrupt Enable. This bit determines whether or not the circular buffer can generate an interrupt on the half full and full buffer boundaries. 0 = Disables interrupt 1 = Enables interrupt
Bit 6
BUFFER HALF/FULL INT FLAG. Buffer Half/Full Interrupt Flag. This bit is set when the circular buffer becomes half or completely full. It is cleared when a zero is written to this bit or during RESET. 0 = Interrupt inactive 1 = Interrupt pending
Bits 5-3
INPUT CAPT PRESCALE SELECT3-1. Input Capture Prescale Select 3-1. These bits set the prescaler rate for pins CP3 to CP6. The bits allow a divide rate of /1 to /8 as shown in the table below. The prescale rate does not affect the event counter.
INPUT CAPT PRESCALE SELECTx Bits 3 0 0 0 0 1 1 1 1 2 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1
Divide Rate /1 /2 /3 /4 /5 /6 /7 /8
Programmable Acquisition and Control Timer (PACT)
15-57
PACT Control Registers
Bit 2
CP6 EVENT ONLY. CP6 8-Bit Event Counter Input Only. This bit must be cleared to allow 32-bit captures triggered by CP6. This bit does not disable the 16-bit captures on event (CP6) when triggered by a command/ definition area command. 0 = CP6 increments event counter and causes 32-bit captures 1 = CP6 increments event counter only
Bit 1
EVENT COUNTER SW RESET. 8-Bit Event Counter Software Reset. This bit resets the 8-bit event counter. When set, the 8-bit counter is continuously cleared. This bit must be cleared to enable the event counter to operate. 0 = Event counter operating 1 = Event counter cleared
Bit 0
OP SET/CLR SELECT. Output Pin Set/Clear Write Function Select. This bit controls how the outputs OP1 to OP8 are set or cleared by software.
- When OP SET/CLR = 1, a write to P048 causes the output pins corre- When OP SET/CLR = 0, a write to P048 causes the output pins corre-
sponding to the locations that were written as 1 to be set in the high state. The output pins corresponding to the locations that were written as 0 remain unchanged.
sponding to the locations that were written as 1 to be set in the low state. The output pins corresponding to the locations that were written as 0 remain unchanged. Refer to the following table and to the examples in subsection 15.11.8 on page 15-49.
OPx WRITE Bit 1 1 0 OP SET/CLR SELECT Bit 1 0 x Result PACT OPx STATE = 1 PACT OPx STATE = 0 PACT OPx STATE remains unchanged
15-58
PACT Control Registers
15.11.14 Global Function Control Register (PACTPRI)
The PACTPRI register controls the WD time-out rate, the PACT interrupt priority levels, and the PACT operating mode.
Global Function Control Register (PACTPRI) [Memory Address 104Fh]
Bit #
P04F
7
PACT STEST RP-0
6
--
5
PACT GROUP 1 PRIORITY RP-0
4
PACT GROUP 2 PRIORITY RP-0
3
PACT GROUP 3 PRIORITY RP-0
2
PACT MODE SELECT RP-0
1
PACT WD PRESCALE SELECT1 RP-0
0
PACT WD PRESCALE SELECT0 RP-0
R = Read, P = Privileged write only, C = Clear, -n = Value of the bit after the register is reset
Bit 7
PACT STEST. This bit must be cleared to ensure proper operation.
Bit 6 Bit 5
Reserved. Read data is indeterminate PACT GROUP 1 PRIORITY. PACT Group 1 Priority Select. This bit assigns the interrupt priority level of the PACT group 1 interrupt vectors. 0 = PACT group 1 interrupts are level 1 (high-priority) requests. 1 = PACT group 1 interrupts are level 2 (low-priority) requests.
Bit 4
PACT GROUP 2 PRIORITY. PACT Group 2 Priority Select. This bit assigns the interrupt priority level of the PACT group 2 interrupt vectors. 0 = PACT group 2 interrupts are level 1 (high-priority) requests. 1 = PACT group 2 interrupts are level 2 (low-priority) requests.
Bit 3
PACT GROUP 3 PRIORITY. PACT Group 3 Priority Select. This bit assigns the interrupt priority level of the PACT group 3 interrupt vectors. 0 = PACT group 3 interrupts are level 1 (high-priority) requests. 1 = PACT group 3 interrupts are level 2 (low-priority) requests.
Bit 2
PACT MODE SELECT. PACT Mode Select. This bit selects the mode for the PACT module to operate in. 0 = PACT operates in mode A 1 = PACT operates in mode B
Bit 1-0
PACT WD PRESCALE SELECT1-0. PACT WD Prescale Select 1-0.
Programmable Acquisition and Control Timer (PACT)
15-59
PACT Control Registers
These bits select the WD time-out rate. You can write to these bits only during privilege mode (after reset).
PACT WD PRESCALE SELECT1 Bit 0 0 1 1 PACT WD PRESCALE SELECT0 Bit 0 1 0 1 Options WD reset on bit 9 of default timer WD reset on bit 15 of default timer WD reset on bit 19 of default timer Disable WD
15-60
Running Title--Attribute Reference
Chapter 16
Assembly Language Instruction Set
An assembly language instruction set is a symbolic language that presents binary machine code in a more readable form. The TMS370 family is supported by a 73-function instruction set that uses a wide variety of addressing modes. This chapter includes the following topics:
Topic
Page
16.1 Instruction Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2 16.2 Symbol Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3 16.3 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4 16.4 Instruction Set Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-23 16.5 Instruction Set Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-32
Chapter Title--Attribute Reference
16-1
Instruction Operation
16.1 Instruction Operation
The assembly language instruction set provides a convenient method of programming the CPU. Each TMS370 assembly language instruction converts directly to one machine operation and consists of the following elements:
-
A function mnemonic. The mnemonic specifies the type of CPU operation. Zero to three operands. The operands indicate where the CPU can find or store data during an instruction execution. The type and combination of operands determine the actual opcode(s) for an instruction. The MOV instruction, for example, has 27 different options, each with its own opcode.
A typical two-operand instruction is shown below:
Mnemonic ADD Source #9, Destination R3
The example above can be read as follows: add the value 9 to the contents of register number 3 and place the result back into register number 3. The destination serves as a second source as well as the final address of the result; moreover, registers can be directly manipulated without having to use intermediate registers. Note that this instruction form differs from the mnemonicdestination-source arrangement that some microprocessors use. The following example shows how the instruction above might appear in a complete program line.
Label XXXXX Instruction ADD Operands #9,R3 Comment ;comment
There should be at least one space between each entry type. The label and comment entries are optional. The 73 instructions are supported by 246 opcodes that provide flexible control of CPU program flow. Some instructions, such as CLRC and TEST A, share the same opcode to help you understand all of the functions of an opcode. Some instructions use 16-bit opcodes, depending on the type of instruction and/or the addressing mode used. The assembler constructs several bit manipulation instructions from other instructions to simplify writing the instructions and to enhance the readability of the program.
16-2
Symbol Definitions
16.2 Symbol Definitions
To understand the instructions described in this chapter, you must know what the symbols in the syntax descriptions represent. Table 16-1 lists the instruction set symbols.
Table 16-1. TMS370 Symbols Defined
Symbol A B C cnd d/D iop8 iop16 label LSB LSbyte MSB MSbyte N name PC PCN Definition Register A or R0 in register file Register B or R1 in register file Carry flag/no borrow flag Condition Destination operand (8-bit/16-bit) 8-bit immediate operand 16-bit immediate operand 16-bit label Least significant bit Least significant byte Most significant bit Most significant byte Sign flag Symbol-defined for a bit Program counter 16-bit address of next instruction (program counter next) Destination register in peripheral file (0 d 255) Register n of peripheral file (0 Symbol-defined peripheral bit Source register in peripheral file (0 s 255) 8-bit signed offset 16-bit signed offset Symbol Rd Rn Rname Rp Rpd Rps Rs s SP ST V XADDR Z (x) ((x)) <> Definition Destination register in register file (0 n 255) Register n of register file (0 n 255) Symbol-defined register bit Register pair Destination register pair Source register pair Source register in register file (0 s 255) Source operand Stack pointer Status register Overflow 16-bit address Zero flag Contents of memory at address x Contents of memory location designated by contents at address x Indicates an entry that must be typed in. For example, indicates that a label must be entered. The brackets themselves are not entered. Is assigned to Becomes equal to Immediate operand prefix Indirect addressing operand prefix Direct addressing operand prefix
Pd Pn Pname Ps off8 off16

# * &
n 255)
Assembly Language Instruction Set
16-3
Addressing Modes
16.3 Addressing Modes
Each TMS370 assembly language instruction includes from zero to three operands. Each operand has an addressing mode. The addressing mode specifies how the CPU calculates the address of the data needed by the instruction. The power of the TMS370 is enhanced by the large number of addressing modes available. The 18 addressing modes are divided into two classes:
-
Data Manipulation Program Flow
Table 16-2 shows the 18 addressing modes, each with a sample instruction and its execution. The subsections that follow describe these modes.
Table 16-2. Overview of Addressing Modes
Addressing Mode Data Manipulation: Implied Register Peripheral Immediate Stack Pointer Relative Direct Indexed Indirect Offset Indirect Program Flow: PC Relative Absolute Direct Absolute Indexed Absolute Indirect Absolute Offset Indirect Relative Direct Relative Indexed Relative Indirect Relative Offset Indirect JMP #offset8 BR 4567h BR *1234h[B] BR *R04 BR *2h[R04] JMPL #1234h JMPL *1234h[B] JMPL *R04 JMPL *12h[R04] PCN + offset8 (PC) 4567h (PC) 1234h + (B) (PC) (R03:R04) (PC) 2h + (R03:R04) (PC) PCN + 1234h (PC) PCN + 1234h + (B) (PC) PCN + (R03:R04) (PC) PCN + 12h + (R03:R04) (PC) LDSP MOV R05,R04 MOV P025,A ADD #23h,R03 MOV *2h[SP],A MOV A,&1234h MOV *1234h[B],A MOV *R04,A MOV *12h[R04],A (B) (SP) (0005h) (0004h) (1025h) (A) 23h + (0003h) (0003h) (2h + (SP)) (A) (A) (1234h) (1234h + (B)) (A) ((R03:R04)) (A) (12h + (R03:R04)) (A) Example Execution
A number of instructions use more than one addressing mode, and several instructions, such as MOV, are very versatile.
16-4
Addressing Modes
16.3.1 Data Manipulation Addressing Modes
Instructions using the data manipulation addressing modes deal with the register file, peripheral file, or a nearby destination. The data manipulation addressing modes are as follows:
-
Implied Register Peripheral Immediate Stack pointer relative
-
Direct Indexed Indirect Offset Indirect
Most of these modes can use any register as a source and/or destination, preventing the bottleneck found on other microprocessors that use only one or two registers. The direct, indexed, indirect, and offset indirect addressing modes always use Register A as the operand to generate a 16-bit address. These addressing modes are used only by the compare (CMP) and move (MOV) instructions.
Assembly Language Instruction Set
16-5
Addressing Modes
16.3.1.1 Implied Addressing Mode
In the implied addressing mode, the instruction type alone determines where the data is to be found. You do not have to specify the operands, because they are inherently specified in the instruction. For example, the LDSP (load stack pointer) instruction always copies the contents of register B to the stack pointer (SP). Neither the source nor the destination is explicitly stated; they are implied in the instruction itself. These are the instructions that use the implied addressing mode: CLRC RTS SETC EINT EINTL Clear the carry bit Return from subroutine Set carry Enable interrupts Enable low-level interrupts LDSP RTI STSP EINTH Load stack pointer Return from interrupt Store stack pointer Enable high-level interrupts
Figure 16-1 shows an example of the implied addressing mode.
Figure 16-1. Implied Addressing Mode
[(B) LDSP (SP)]
Register file Address (1) LDSP MOV (A) 0 (B) 1 2 25 34 (2) Stack Pointer 34
Program Address 7123h 7124h 7125h
Note:
Numbers in parentheses represent the order of execution.
16-6
Addressing Modes
16.3.1.2 Register Addressing Mode
The register file (RF) of the TMS370 consists of the first 128 or 256 bytes of memory (the number of bytes differs according to the device that you are using). In the register addressing mode, instructions use a one-byte value to specify an address (location) in the RF. Any location in the RF can be accessed in one memory cycle by instructions using this mode. Other addressing modes require two cycles to access the register file. In register file addressing, the operand is stated by Rn, where n is the 8-bit address number. The address number can be a decimal (0-255) or hexadecimal (0-0FF) number. Hexadecimal numbers require a leading zero, but no suffix. Registers R0 and R1 of the register file are also known as registers A and B and are referenced as such by most instructions to reduce the size of the program. For example, the instruction MOV A,B uses one byte of code, while the instruction MOV R3,R4 uses three bytes of code. Any register can be specified by a symbol that has been equated to that register. This is illustrated in the following example:
CAT DOG MOV .EQU .EQU MOV R16,R011 R16 R17 CAT,DOG ;Move contents of 0010h to 0011h ;Equate register 16 to symbol CAT ;Equate register 17 to symbol DOG ;Move contents of 0010h to 0011h
Note that the entry .EQU is an assembler directive, not an assembly language instruction. For more information on assembler directives, refer to the TMS370 Family Assembly Language Tools User's Guide. Figure 16-2 shows an example of the register addressing mode.
Figure 16-2. Register Addressing Mode
INC R023 [(Rn) + 1 (Rn)]
Program Address 7123h 7124h INC Rn 23 (1) Address 0022h 0023h 34 35 (2) (3) 34h + 1h 35h Data
Note:
Numbers in parentheses represent the order of execution.
Assembly Language Instruction Set
16-7
Addressing Modes
16.3.1.3 Peripheral Addressing Mode
The peripheral addressing mode is used for program control of the peripheral on-chip modules such as timers, interrupts, and I/O ports. Devices with bus expansion can address a small amount of external memory as peripheral file (PF) space. The PF of the TMS370 is allocated 256 bytes of memory. Each PF register is accessed by an 8-bit operand designated as Pn, with n being either a decimal (0-255) or hexadecimal (0-0FF) number. Hexadecimal numbers require a leading zero but no suffix. The CPU assumes the most significant byte of a peripheral address to be 010h. As described for register file addressing in subsection 16.3.1.2, the Pn designation, like the Rn designation, can be replaced with a symbol by using the equate (.EQU) assembler directive as shown in the example below.
CAT DOG MOV .EQU .EQU MOV R16,P020 R16 P32 CAT,DOG ;Move contents of 0010h to 1020h ;Equate register 16 to symbol CAT ;Equate peripheral file 32 to symbol DOG ;Move contents of 0010h to 1020h
The use of designated symbols is optional but is particularly suited for the register and peripheral addressing modes. Figure 16-3 shows an example of peripheral file addressing.
Figure 16-3. Peripheral Addressing Mode
MOV P025, A (A)] [(Ps)
Program Address 7120h 7121h 7122h 7123h MOV Ps, A 25 ADD (1) Address 1024h 1025h 1026h (2) 32 Address (A) 0 (B) 1 2 3 32 Peripheral register Register
Note:
Numbers in parentheses represent the order of execution.
16-8
Addressing Modes
16.3.1.4 Immediate Addressing Mode
The immediate addressing mode uses a constant value as the operand that immediately follows the function mnemonic. This mode allows nonchanging data to be incorporated into the instruction. The constant can be in the form of a decimal number, a hexadecimal number, or a symbolic label, but the constant is always preceded by the number sign (#). Note that hexadecimal numbers require both a leading numeric digit and the h suffix. Some examples of immediate addressing are as follows:
MOV MOV .EQU ADD #0Fh,A ;Store the value 15 in register A #(3*54),R022 ;Store the value 162 at location 022h 12 ;Equate 12 to symbol CNT #CNT,R34 ;Add the value 12 to register 34, place ; result in register 34.
CNT
Figure 16-4 illustrates an instruction using the immediate addressing mode.
Figure 16-4. Immediate Addressing Mode
ADD #11, R045 (Rd)] [#iop8 + (Rd)
Program Address 7123h 7124h 7125h ADD #iop8, Rd (1) 11 (2) 45 11h + 56h 67h Address (3) (4) R043 R044 R045 R046 12 34 56 67 Data
Note:
Numbers in parentheses represent the order of execution.
Assembly Language Instruction Set
16-9
Addressing Modes
16.3.1.5 Stack Pointer Relative Addressing Mode
The stack pointer relative addressing mode adds an 8-bit signed constant to the existing 8-bit contents of the stack pointer register. The result is truncated to an 8-bit address of the data. The second operand in the stack pointer relative mode is always register A. This addressing mode is useful in accessing arguments that are passed to a subroutine on the stack. You must ensure that the resulting address location is within the implemented register file, because overflows or underflows will execute without warning. Only the CMP and MOV instructions use this mode. An example of stack relative addressing is as follows:
MOV *-2h[SP], A
In this example, the value of -2 plus the stack pointer equals the address of the data to be moved to register A. Figure 16-5 illustrates this instruction operation.
Figure 16-5. Stack Pointer Relative Addressing Mode
MOV *-2h [SP], A [((SP) + off8) (A)]
Stack Pointer Program Address 7123h MOV *off8[SP],A 63h + -2h -2 7124h 61h ADD 7125h (1) XXX 7126h 63
(2)
Data Address 5Fh 60h 61h 62h 63h Address (A) 0 (B) 1 2 3
Register file 34
(3)
34
(4)
Note:
Numbers in parentheses represent the order of execution.
16-10
Addressing Modes
16.3.1.6 Direct Addressing Modes
Direct addressing mode instructions use an address as the operand. The 16-bit address is written as either a constant value or a label and immediately follows the opcode in the source code. The direct addressing mode acts on the address itself as shown in Figure 16-6.
Figure 16-6. Direct Addressing Mode
MOV &2233h, A [(label) (A)]
Data Program Address 7123h 7124h 7125h 7126h MOV & label, A 22 33 ADD (1) Address 2232h 2233h 2234h 2235h 12 34 56 78 (2) Address (A) 0 (B) 1 2 3 34 Register file
Note:
Numbers in parentheses represent the order of execution.
Assembly Language Instruction Set
16-11
Addressing Modes
16.3.1.7 Indexed Addressing Mode
The indexed addressing mode generates a 16-bit address by adding the unsigned contents of register B to a 16-bit unsigned constant. The assembly language statement for the indexed addressing modes contains the direct memory address written as a 16-bit value or a label, preceded by an asterisk (*) and followed by a B in brackets; for example, MOV *1234[B], or MOV *LABEL[B]. Note the following:
-
The MOV and CMP instructions can use indexed addressing to step easily through a small table or to pick out a particular array value.
Figure 16-7 illustrates how the object code produced by an instruction using this mode generates a 16-bit effective address.
Figure 16-7. Indexed Addressing Mode
MOV *2233h [B], A [(label + (B)) (A)]
Register file Address Program Address 7123h MOV *label[B],A 7124h 22 7125h 33 22 7126h (1) 2233h + 4h 2237h Address (3) 2235h 2236h 2237h 2238h (A) 0 (B) 1 2 (2) 78 4 (4)
Data
78
Note:
Numbers in parentheses represent the order of execution.
16-12
Addressing Modes
16.3.1.8 Indirect Addressing Mode
In indirect addressing modes, instructions use the contents of a register pair as the 16-bit address of the data. The indirect register file address is written as a register number (Rn) preceded by an asterisk (*) symbol. The LSbyte of the address is contained in Rn, and the MSbyte of the address is contained in the previous register (Rn-1). The TMS370 can use any register pair as an indirect register. Figure 16-8 shows how the indirect addressing mode uses the register pair in the calculation.
Figure 16-8. Indirect Addressing Mode
MOV *R099, A [((Rp -1: Rp))
Program Address 7123h 7124h 7125h 7126h Address R097 (1) R098 R099 R09A Register file Address 2231h 2232h 2233h (2) 2234h
(A)]
Data Address (A) 0 (B) 1 (3) 2 3 Register file
MOV *Rp,A 99 ADD
34
22 33
34
Note:
Numbers in parentheses represent the order of execution.
Assembly Language Instruction Set
16-13
Addressing Modes
16.3.1.9 Offset Indirect Addressing Mode
The offset indirect addressing mode is similar to the indirect addressing mode previously described. The offset indirect addressing mode generates a 16-bit address by adding an 8-bit signed offset to an address taken from a register pair. Offset indirect addressing is useful for stepping through tables or for finding a particular value in a table by using two values to generate the address. Figure 16-9 illustrates how the object code produced by an instruction using the offset indirect addressing mode generates a 16-bit effective address.
Figure 16-9. Offset Indirect Addressing Mode
MOV *2h[R099] , A [(off8 + (Rp - 1: Rp)) (A)]
Register file Address Address Program Register file Address (1) (2) R097 R098 R099 2h + 2233h 2235h (3) (4) 41 22 33 (A) 0 (B) 1 2 56 (5)
7121h MOV *off8 [Rp],A 7122h 2 7123h 99 7124h ADD
Data Address 2234h 2235h 2236h 62 56 78
Note:
Numbers in parentheses represent the order of execution.
16-14
Addressing Modes
16.3.2 Program Flow Addressing Modes
The program flow addressing modes provide a sophisticated method for stepping through tables, picking out array values, and generating addresses. These modes allow the program to access data from anywhere in the memory. Program flow addressing modes consist of the following nine types:
-
Absolute Direct Absolute Indexed Absolute Indirect Absolute Offset Indirect
-
PC Relative Relative Direct Relative Indexed Relative Indirect Relative Offset Indirect
There are two modes of program flow addressing; absolute addressing and relative addressing. Each mode is described below.
-
Program flow absolute addressing modes always use the PC (program counter) as the destination operand to store the generated 16-bit address. The program flow absolute addressing modes are used only by the branch (BR) and CALL instructions. The program flow relative addressing modes are similar to the program flow absolute addressing modes but include the additional step of combining the operand with the PCN value before placing the 16-bit address into the program counter. These modes are similar to the program counter relative mode. A 16-bit signed offset is used to calculate the succeeding instruction address. The succeeding instruction address is calculated at execution time by using the signed 16-bit offset according to the instruction's addressing mode. The program flow relative addressing modes are useful in relocatable code because their operation is based on the differences in the address position instead of on the addresses themselves. This makes the program flow relative addressing modes well suited for high-level languages that often use position-independent code. Program flow relative addressing is used by the CALLR and JMPL instructions.
Assembly Language Instruction Set
16-15
Addressing Modes
16.3.2.1
Program Counter Relative Addressing Mode
The program counter relative addressing mode adds an 8-bit signed offset to the address of the next instruction to produce the address of the succeeding instruction. The new address is placed in the program counter register. The range of the 8-bit offset is within 128 bytes before or 127 bytes after the instruction following the jump. When labels are used, the signed offset is automatically calculated by the assembler. Note that the PCN is the location (address) of the next instruction. Figure 16-10 illustrates object code generated by a jump instruction using the program counter relative mode.
Figure 16-10. Program Counter Relative Addressing Mode
JMPL #label [PCN + off8 (PC)]
Program Counter (off8) (PCN) 7123h + 5h 7128h (Label) off8 = Label - PCN (Precalculated by assembler) 7123 7128
Program Address 7121h 7122h 7123h 7124h 7125h 7126h 7127h 7128h 7129h JMP 5 ADD R3 R4 INC R4 CLR R8
16-16
Addressing Modes
16.3.2.2
Absolute and Relative Direct Addressing Modes
Absolute and relative direct addresssing mode instructions use an address as the operand. The 16-bit address is written as either a constant value or a label and immediately follows the opcode in the source code. The absolute direct addressing mode takes a label and places the value into the PC as shown in Figure 16-11.
Figure 16-11. Absolute Direct Addressing Mode
BR 4567h [label (PC)]
Program Counter 4567
Program Address 7123h 7124h 7125h 7126h BR label 45 67 ADD
The relative direct addressing mode (see Figure 16-12) adds the address of the next instruction to the 16-bit operand to produce the address of the succeeding instruction. If a label is used in the instruction, the assembler automatically calculates the offset to use as the operand.
Figure 16-12. Relative Direct Addressing Mode
JMPL #5432h [PCN + off16 (PC)]
Program Counter 9565
Program Address 4130h 4131h 4132h 4133h JMPL #off16 54 32 INC PCN
5432h + 4133h 9565h
Assembly Language Instruction Set
16-17
Addressing Modes
16.3.2.3
Absolute and Relative Indexed Addressing Modes
The absolute indexed addressing mode generates a 16-bit address by adding the unsigned contents of register B to a 16-bit unsigned constant. The 16-bit address is then placed into the PC. The assembly language statement for the absolute indexed addressing modes contains the direct memory address written as a 16-bit value or a label preceded by an asterisk (*) and followed by a B in brackets; for example, BR *1234[B] or BR *LABEL[B]. Note: Use of Indexed Addressing by BR and CALL Instructions
The CALL and BR instructions can use this mode to execute code according to a decision table and the value in register B. Figure 16-13 illustrates how the object code produced by an instruction using this mode generates a 16-bit effective address.
Figure 16-13. Absolute Indexed Addressing Mode
BR *1234h[B] [label + (B) (PC)]
Address Program Address 7123h 7124h 7125h 7126h BR *label[B] 12 34 (1) (2) 1234h + 5h 1239h (A) 0 (B) 1 2 5 Program Counter
Program Counter (3) 1239
Note:
Numbers in parentheses represent the order of execution.
16-18
Addressing Modes
The relative indexed addressing mode includes the operation described for the absolute indexed addressing mode with the following additional step: the address of the next instruction is added to the sum of register B and the signed 16-bit constant offset to produce the address of the next instruction. The relative indexed addressing mode is shown in Figure 16-14.
Figure 16-14. Relative Indexed Addressing Mode
JMPL *1236h [B] [label + (B) + PCN (PC)]
Register File 25 34 Program Counter 7126 8390
Program Address 7123h 7124h 7125h 7126h JMPL *label [B] (1) 12 36 PCN INC 1236h 34h + 7126h 8390h
Address (A) 0 (B) 1 (2) (3) (4)
Note:
Numbers in parentheses represent order of execution.
Assembly Language Instruction Set
16-19
Addressing Modes
16.3.2.4
Absolute and Relative Indirect Addressing Modes
In absolute indirect addressing mode, instructions use the contents of a register pair as the 16-bit address. The absolute and relative indirect register file address is written as a register number (Rn) preceded by an asterisk (*) symbol. The LSbyte of the address is contained in Rn, and the MSbyte of the address is contained in the previous register (Rn-1). The TMS370 can use any register pair as an absolute or relative indirect register. Figure 16-15 shows how the absolute indirect addressing mode uses the register pair in the calculation.
Figure 16-15. Absolute Indirect Addressing Mode
BR *R099 [(Rp - 1: Rp) (PC)]
Program Address Address 7123h 7124h 7125h BR *Rp 99 R097 R098 R099 R09A
Register File
Program Counter 4567
45 67
The relative indirect addressing mode (Figure 16-16) adds the address of the next instruction to the register pair contents before obtaining the destination address.
Figure 16-16. Relative Indirect Addressing Mode
JMPL *R099 [(Rp - 1: Rp) + PCN
Program Address Address 7123h 7124h 7125h JMPL*Rp 99 ADD (1) PCN R098 R099 Register File 10 24 (2) 1024h + 7125h 8149h (3) (4) Program Counter 7125 8149
(PC)]
Note:
Numbers in parentheses represent the order of execution.
16-20
Addressing Modes
16.3.2.5
Absolute and Relative Offset Indirect Addressing Modes
The absolute and relative offset indirect addressing modes are similar to the absolute and relative indirect addressing modes previously described. The absolute offset indirect addressing mode generates a 16-bit address by adding an 8-bit signed offset to an address taken from a register pair. The 16-bit address is then placed into the PC. Offset indirect addressing is useful for stepping through tables or for finding a particular value in a table by using two values to generate the address. Figure 16-17 illustrates how the object code produced by an instruction using the absolute offset indirect addressing mode generates a 16-bit effective address.
Figure 16-17. Absolute Offset Indirect Addressing Mode
BR *2h[R099] [off8 + (Rp -1: Rp) (PC)]
Register File Address BR *off8 [Rp] 2 99 ADD (1) (2) R097 R098 R099 2h + 4455h 4457h (3) (4) 41 44 55 Program Counter 4457
Program Address 7121h 7122h 7123h 7124h
Note:
Numbers in parentheses represent the order of execution.
Assembly Language Instruction Set
16-21
Addressing Modes
The relative offset indirect addressing mode adds the address of the next instruction with the sum of the 8-bit signed offset and the register pair before obtaining the destination address.
Figure 16-18. Relative Offset Indirect Addressing Mode
JMPL *56h [R0A] [PCN + off8 + (Rp -1: Rp)
Register File Address R08 R09 R0A 56h 1024h + 7126h 81A0h Note: 12 10 24
(PC)]
Program Counter 7126 81A0
Program Address 7123h JMPL *off8 [Rp] (1) 7124h 56 (2) 7125h 0A 7126h PCN INC
(3) (4) (5)
Numbers in parentheses represent the order of execution.
16.3.3 Additional Addressing Modes
In some cases, the operation of an instruction does not fit into any of the addressing modes previously described. Some modes illustrated by instructions such as MOVW #iop[B],Rpd provide unique capabilities for table addressing. Other modes illustrated by instructions like the LDST #iop8 give access to the status register bits (shown in Figure 16-19). The individual instruction description can be referenced for a list of that instruction's operations.
16.3.4 Status Register
Most of the instructions affect the bits in the status register. The status register is presented in Figure 16-19 as a quick reference to aid in programming.
Figure 16-19. Status Register (ST)
Status Register (ST)
Bit #
7
C RW-0
6
N RW-0
5
Z RW-0
4
V RW-0
3
IE2 RW-0
2
IE1 RW-0
1
--
0
--
R = Read, W = Write, -n = Value of the bit after the register is reset
16-22
Instruction Set Overview
16.4 Instruction Set Overview
The tables in this section list the instruction set, including pertinent characteristics and an opcode/instruction map. Table 16-3 lists all instruction formats, opcodes, byte lengths, cycles/instructions, operands, status bits affected, and an operational description.
Table 16-3. TMS370 Family Instruction Overview
Mnemonic and Operands ADC B,A Rs,A Rs,B Rs,Rd #iop8,A #iop8,B #iop8,Rd B,A Rs,A Rs,B Rs,Rd #iop8,A #iop8,B #iop8,Rd A,Pd B,A B,Pd Rs,A Rs,B Rs,Rd #iop8,A #iop8,B #iop8,Rd #iop8,Pd label *Rp *label[B] *off8[Rp] A,Pd,#off8 B,A,#off8 B,Pd,#off8 Rs,A,#off8 Rs,B,#off8 Rs,Rd,#off8 #iop8,A,#off8 #iop8,B,#off8 #iop8,Rd,#off8 #iop8,Pd,#off8 Opcode 69 19 39 49 29 59 79 68 18 38 48 28 58 78 83 63 93 13 33 43 23 53 73 A3 8C 9C AC F4 EC 86 66 96 16 36 46 26 56 76 A6 Bytes 1 2 2 3 2 2 3 1 2 2 3 2 2 3 2 1 2 2 2 3 2 2 3 3 3 2 3 4 3 2 3 3 3 4 3 3 4 4 Cycles (tc) 8 7 7 9 6 6 8 8 7 7 9 6 6 8 9 8 9 7 7 9 6 6 8 10 9 8 11 16 10 10 10 9 9 11 8 8 10 11 Status C N Z V xxxx Operation Description (s) + (d) + (C) (d) Add the source, destination, and carry bit together. Store at the destination address.
ADD
xxxx
(s) + (d) (d) Add the source and destination operands and store at the destination address.
AND
0xx0
(s) AND (d) (d) AND the source and destination operands together and store at the destination address.
BR
----
XADDR (PC) Branch to the destination address.
BTJO
0xx0
If (s) AND (d) 0, then PCN + off8 (PC). If the AND of the source and destination operands 0 (corresponding 1 bit), the PC will add the offset, and the jump will be taken.
Add two to the cycle count if a jump is taken. Status Values: 0 Status bit always cleared. 1 Status bit always set. x Status bit cleared or set on results. - Status bit not affected.
Assembly Language Instruction Set
16-23
Instruction Set Overview
Table 16-3. TMS370 Family Instruction Overview (Continued)
Mnemonic and Operands BTJZ A,Pd,#off8 B,A,#off8 B,Pd,#off8 Rs,A,#off8 Rs,B,#off8 Rs,Rd,#off8 #iop8,A,#off8 #iop8,B,#off8 #iop8,Rd,#off8 #iop8,Pd,#off8 label *Rp *label[B] *off8[Rp] #off16 label *Rp *off16[B] *label[B] *off8[Rp] A B Rd Opcode 87 67 97 17 37 47 27 57 77 A7 8E 9E AE F4 EE 8F 8F 9F AF AF F4 EF B5 C5 D5 B0 Bytes 3 2 3 3 3 4 3 3 4 4 3 2 3 4 3 3 2 3 3 4 1 1 2 1 Cycles (tc) 10 10 10 9 9 11 8 8 10 11 13 12 15 20 15 15 14 17 17 22 8 8 6 9 Status C N Z V 0xx0 Operation Description If (s) AND (not d) 0, then (PCN) + off8 (PC). If any 1 in the source corresponds to a 0 in the destination, the PC adds the offset, and the jump is taken.
CALL
----
Push PC MSbyte, PC LSbyte, XADDR (PC)
CALLR
----
Call relative Push PC MSbyte, PC LSbyte, PCN + (XADDR) (PC)
CLR
0010
0 (Rd) Clear the destination operand. 0 (C) Clear the carry bit. N and Z bits are set on the value in A. Compare; (d) - (s) computed. Set flags on the result of the source operand subtracted from the destination operand. Operands are not affected by operation.
CLRC
0xx0
CMP
*label,A *Rp,A *label[B],A *off8[Rp],A *off8[SP],A B,A Rs,A Rs,B Rs,Rd #iop8,A #iop8,B #iop8,Rd Rname Pname A B Rd
8D 9D AD F4 ED F3 6D 1D 3D 4D 2D 5D 7D 75 A5 BB CB DB
3 2 3 4 2 1 2 2 3 2 2 3 3 3 1 1 2
11 10 13 18 8 8 7 7 9 6 6 8 8 10 8 8 6
xxxx
CMPBIT COMPL
0xx0 xxx0
Complement bit; invert the bit 2s complement; 00h - (s) (d)
Add two to the cycle count if a jump is taken. Status Values: 0 1 x - Status bit always cleared. Status bit always set. Status bit cleared or set on results. Status bit not affected.
16-24
Instruction Set Overview
Table 16-3. TMS370 Family Instruction Overview (Continued)
Mnemonic and Operands DAC B,A Rs,A Rs,B Rs,Rd #iop8,A #iop8,B #iop8,Rd A B Rd Opcode 6E 1E 3E 4E 2E 5E 7E B2 C2 D2 F0 00 Rs,A F4 F8 Bytes 1 2 2 3 2 2 3 1 1 2 2 3 Cycles (tc) 10 9 9 11 8 8 10 8 8 6 6 55-63 14 DJNZ A,#off8 B,#off8 Rd,#off8 B,A Rs,A Rs,B Rs,Rd #iop8,A #iop8,B #iop8,Rd BA CA DA 6F 1F 3F 4F 2F 5F 7F F0 0C F0 04 2 2 3 1 2 2 3 2 2 3 2 2 10 10 8 10 9 9 11 8 8 10 6 6 Status C N Z V xxxx Operation Description (s) + (d) + (C) (d) (BCD) The source, destination, and carry bit are added, and the BCD sum is stored at the destination address.
DEC
xxxx
(d) - 1 (d) Decrement destination operand by 1. 0 (ST)(global interrupt enable bits) 0 IE1, 0 IE2. A:B/Rs A(= QUO),B(= REM) Integer divide, 16 by 8 bits. Overflow detected. (d) - 1 (d); If (d) 0, then PCN + off8 (PC). Decrement and jump if not 0. (d) - (s) - 1 + (C) (d) (BCD) The source operand is subtracted from the destination; this sum is then reduced by 1, and the carry bit is then added to it. The result is stored as a BCD number.
DINT DIV
0000 0xx0 1111 ----
DSB
xxxx
EINT EINTH
0000 0000
0Ch (ST)(global interrupt enable bit) 1 IE1, 1 IE2. 04h (ST)(high-priority global interrupt enable bit) 1 IE1, 0 IE2 08h (ST)(low-priority global interrupt enable bit) 0 IE1, 1 IE2 (PC) (PC) until interrupt (PC) + 1 (PC) after return from interrupt. Stops C execution until an interrupt. Entry to low-power modes. (d) + 1 (d) Increase the destination operand by 1. (Rp) + operand (Rp) Add 8-bit immediate operand to register pair.
EINTL IDLE
F0 08 F6
2 1
6 6
0000 ----
INC
A B Rd #iop8,Rp
B3 C3 D3 70
1 1 2 3
8 8 6 11
xxxx
INCW
xxxx
Add two to the cycle count if a jump is taken. Status Values: 0 1 x - Status bit always cleared. Status bit always set. Status bit cleared or set on results. Status bit not affected.
Assembly Language Instruction Set
16-25
Instruction Set Overview
Table 16-3. TMS370 Family Instruction Overview (Continued)
Mnemonic and Operands INV A B Rd Rname,#off8 Pname,#off8 Rname,#off8 Pname,#off8 off8 #off16 label *Rp *off16[B] *label[B] *off8[Rp] JC JEQ JG JGE JHS JL JLE JLO JN JNC JNE JNV JNZ JP JPZ JV JZ LDSP LDST #iop8 Opcode B4 C4 D4 77 A7 76 A6 00 89 89 99 A9 A9 F4 E9 03 02 0E 0D 0B 09 0A 0F 01 07 06 0C 06 04 05 08 02 FD F0 Bytes 1 1 2 4 4 4 4 2 3 3 2 3 3 4 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 2 Cycles (tc) 8 8 6 10 11 10 11 7 9 9 8 11 11 16 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 7 6 ---- xxxx Status C N Z V 0xx0 Operation Description NOT(d) (d) 1s complement the destination operand. Jump if bit = 0 This instruction may have as many as 8 operands. All operands must reference the same byte. Jump if bit = 1 PCN + off8 (PC) Jump unconditionally using an 8-bit offset. PCN + D (PC) Jump unconditionally using a 16-bit offset.
JBIT0
0xx0
JBIT1 JMP JMPL
0xx0 ---- ----
Jcnd
----
Conditional jump Carry Jump equal Greater than, signed Greater than or equal, signed Higher or same, unsigned Less than, signed Less than or equal, signed Lower value, unsigned Negative, signed No carry Jump not equal No overflow, signed Not zero Positive, signed Positive or zero, signed Overflow, signed Zero (B) (SP) Load stack pointer with contents of register B. (s) (ST) Load ST register.
Add two to the cycle count if a jump is taken. Status Values: 0 Status bit always cleared. 1 Status bit always set. x Status bit cleared or set on results. - Status bit not affected.
16-26
Instruction Set Overview
Table 16-3. TMS370 Family Instruction Overview (Continued)
Mnemonics and Operands MOV A,B A,Rd A,Pd A,&label A,*Rp A,*label[B] A,*off8[Rp] A,*off8[SP] Rs,A Rs,B &label,A *Rp,A *label[B],A *off8[Rp],A *off8[SP],A B,A B,Rd B,Pd Rs,Rd Rs,Pd Ps,A Ps,B Ps,Rd #iop8,A #iop8,B #iop8,Rd #iop8,Pd Rps,Rpd #iop16,Rpd #iop16[B],Rpd #off8[Rps],Rpd B,A Rs,A Rs,B Rs,Rd #iop8,A #iop8,B #iop8,Rd Opcode C0 D0 21 8B 9B AB F4 EB F2 12 32 8A 9A AA F4 EA F1 62 D1 51 42 71 80 91 A2 22 52 72 F7 98 88 A8 F4 E8 6C 1C 3C 4C 2C 5C 7C Bytes 1 2 2 3 2 3 4 2 2 2 3 2 3 4 2 1 2 2 3 3 2 2 3 2 2 3 3 3 4 4 5 1 2 2 3 2 2 3 1 Cycles (tc) 9 7 8 10 9 12 17 7 7 7 10 9 12 17 7 8 7 8 9 10 8 8 10 6 6 8 10 12 13 15 20 47 46 46 48 45 45 47 7 Status C N Z V 0xx0 Operation Description (s) (d) Replace the destination operand with the source operand.
MOVW
0xx0
(s) (Rpd-1:Rpd) Copy the source register word to the destination register pair. (s) x (d) (A:B) Multiply the source and destination operands; store the result in registers A (MSbyte) and B (LSbyte).
MPY
0xx0
NOP FF Status Values: 0 Status bit always cleared. 1 Status bit always set. x Status bit cleared or set on results. - Status bit not affected.
----
No operation
Assembly Language Instruction Set
16-27
Instruction Set Overview
Table 16-3. TMS370 Family Instruction Overview (Continued)
Mnemonic and Operands OR A,Pd B,A B,Pd Rs,A Rs,B Rs,Rd #iop8,A #iop8,B #iop8,Rd #iop8,Pd A B Rd ST A B Rs ST A B Rd A B Rd A B Rd A B Rd Opcode 84 64 94 14 34 44 24 54 74 A4 B9 C9 D9 FC B8 C8 D8 FB BE CE DE BF CF DF BC CC DC BD CD DD FA F9 B,A Rs,A Rs,B Rs,Rd #iop8,A #iop8,B #iop8,Rd Rname Pname Rname Pname 6B 1B 3B 4B 2B 5B 7B 73 A3 74 A4 Bytes 2 1 2 2 2 3 2 2 3 3 1 1 2 1 1 1 2 1 1 1 2 1 1 2 1 1 2 1 1 2 1 1 1 2 2 3 2 2 3 3 3 3 3 Cycles (tc) 9 8 9 7 7 9 6 6 8 10 9 9 7 8 9 9 7 8 8 8 6 8 8 6 8 8 6 8 8 6 12 9 8 7 7 9 6 6 8 8 10 8 10 Status C N Z V 0xx0 Operation Description (s) OR (d) (d) Logically OR the source and destination operands, and store the results at the destination address.
POP
0xx0 xxxx 0xx0 ---- xxx0
((SP)) (d) (SP) -1 (SP)
PUSH
(SP) + 1 (SP) (s) ((SP)) Copy the operand onto the stack. Copy the status register onto the stack. Bit(n) Bit(n + 1) Bit(7) Bit(0) and Carry Bit(n) Bit(n + 1) Carry Bit(0) Bit(7) Carry Bit(n + 1) Bit(n) Bit(0) Bit(7) and Carry Bit(n + 1) Bit(n) Carry Bit(7) Bit(0) Carry Pop PCL, PCH, POP ST Return from interrupt. Pop PCL, PCH (d) - (s) - 1 + (C) (d) Subtract with borrow. Destination minus source minus 1 plus carry; stored at the destination address.
RL
RLC
xxx0
RR
xxx0
RRC
xxx0
RTI RTS SBB
xxxx ---- xxxx
SBIT0 SBIT1
0xx0 0xx0
Set bit to 0 Set bit to 1
Status Values: 0 Status bit always cleared. 1 Status bit always set. x Status bit cleared or set on results. - Status bit not affected.
16-28
Instruction Set Overview
Table 16-3. TMS370 Family Instruction Overview (Concluded)
Mnemonic and Operands SETC STSP SUB B,A Rs,A Rs,B Rs,Rd #iop8,A #iop8,B #iop8,Rd A B Rd #n Opcode F8 FE 6A 1A 3A 4A 2A 5A 7A B7 C7 D7 EF-E0 Bytes 1 1 1 2 2 3 2 2 3 1 1 2 1 Cycles (tc) 7 8 8 7 7 9 6 6 8 11 11 9 14 Status C N Z V 1010 ---- xxxx Operation Description Axh (ST) Set the carry bit. IE1 and IE2 unchanged. (SP) (B) Copy the SP into register B. (d) - (s) (d) Store the destination operand minus the source operand into the destination.
SWAP
0xx0
s(7-4,3-0) d(3-0,7-4) Swap the operand's high and low nibbles. Vector n (PC), n = 0 15 = trap number Trap to subroutine; Push PCN Trap 0 = EF, Trap 15 = E0 Test; Set status bit according to the value in register A or B. (B) (Rn) (with Rn = A or B or Rd) Swap the contents of register B with (Rn). (s) XOR (d) (d) Logically exclusive OR the source and destination operands; store at the destination address.
TRAP
----
TST XCHB
A B A B Rd A,Pd B,A B,Pd Rs,A Rs,B Rs,Rd #iop8,A #iop8,B #iop8,Rd #iop8,Pd
B0 C6 B6 C6 D6 85 65 95 15 35 45 25 55 75 A5
1 1 1 1 2 2 1 2 2 2 3 2 2 3 3
9 10 10 10 8 9 8 9 7 7 9 6 6 8 10
0xx0 0xx0
XOR
0xx0
Status Values: 0 Status bit always cleared. 1 Status bit always set. x Status bit cleared or set on results. - Status bit not affected.
Table 16-4 provides an opcode-to-instruction cross-reference of all 73 instructions and 274 opcodes of the TMS370 instruction set. To check the instruction of a known opcode, locate the left (high) digit across the top or bottom of the table, then find the right (low) digit along the side of the table. The intersection contains the instruction mnemonic, operands, and byte/cycle peculiar to that opcode. Some opcodes, such as B0, are shared by two instructions, in which case, both mnemonics are shown with the byte/cycle count.
Assembly Language Instruction Set
16-29
Instruction Set Overview
16-30
Table 16-4. TMS370 Family Opcode/Instruction Map
MSN
0 0 JMP ra 2/7 JN ra 2/5 JZ ra 2/5 JC ra 2/5 JP ra 2/5 JPZ ra 2/5 JNZ ra 2/5 JNC ra 2/5 JV ra 2/5 JL ra 2/5 JLE ra 2/5 JHS ra 2/5 MOV Rs,A 2/7 AND Rs,A 2/7 OR Rs,A 2/7 XOR Rs,A 2/7 BTJO Rs,A,ra 3/9 BTJZ Rs,A,ra 3/9 ADD Rs,A 2/7 ADC Rs,A 2/7 SUB Rs,A 2/7 SBB Rs,A 2/7 MOV A,Pd 2/8 MOV #n,A 2/6 AND #n,A 2/6 OR #n,A 2/6 XOR #n,A 2/6 BTJO #n,A,ra 3/8 BTJZ #n,A,ra 3/8 ADD #n,A 2/6 ADC #n,A 2/6 SUB #n,A 2/6 SBB #n,A 2/6 MOV Rs,B 2/7 AND Rs,B 2/7 OR Rs,B 2/7 XOR Rs,B 2/7 BTJO Rs,B,ra 3/9 BTJZ Rs,B,ra 3/9 ADD Rs,B 2/7 ADC Rs,B 2/7 SUB Rs,B 2/7 SBB Rs,B 2/7 MOV Rs,Rd 3/9 AND Rs,Rd 3/9 OR Rs,Rd 3/9 XOR Rs,Rd 3/9 BTJO Rs,Rd,ra 4/11 BTJZ Rs,Rd,ra 4/11 ADD Rs,Rd 3/9 ADC Rs,Rd 3/9 SUB Rs,Rd 3/9 SBB Rs,Rd 3/9 MOV B,Pd 2/8 MOV #n,B 2/6 AND #n,B 2/6 OR #n,B 2/6 XOR #n,B 2/6 BTJO #n,B,ra 3/8 BTJZ #n,B,ra 3/8 ADD #n,B 2/6 ADC #n,B 2/6 SUB #n,B 2/6 SBB #n,B 2/6 MOV B,A 1/8 AND B,A 1/8 OR B,A 1/8 XOR B,A 1/8 BTJO B,A,ra 2/10 BTJZ B,A,ra 2/10 ADD B,A 1/8 ADC B,A 1/8 SUB B,A 1/8 SBB B,A 1/8 1 2 3 4 5 6 7 INCW #n,Rd 3/11 MOV Rs,Pd 3/10 MOV #n,Rd 3/8 AND #n,Rd 3/8 OR #n,Rd 3/8 XOR #n,Rd 3/8 BTJO #n,Rd,ra 4/10 BTJZ #n,Rd,ra 4/10 ADD #n,Rd 3/8 ADC #n,Rd 3/8 SUB #n,Rd 3/8 SBB #n,Rd 3/8 AND A,Pd 2/9 OR A,Pd 2/9 XOR A,Pd 2/9 BTJO A,Pd,ra 3/11 BTJZ A,Pd,ra 3/10 MOVW #16,Rd 4/13 JMPL lab 3/9 MOV &lab,A 3/10 MOV A,&lab 3/10 AND B,Pd 2/9 OR B,Pd 2/9 XOR B,Pd 2/9 BTJO B,Pd,ra 3/10 BTJZ B,Pd,ra 3/10 MOVW Rs,Rd 3/12 JMPL *Rd 2/8 MOV *Rs,A 2/9 MOV A,*Rp 2/9 8 MOV Ps,A 2/8 MOV Ps,B 2/7 MOV Ps,Rd 3/10 AND #n,Pd 3/10 OR #n,Pd 3/10 XOR #n,Pd 3/10 BTJO #n,Pd,ra 4/11 BTJZ #n,Pd,ra 4/11 MOVW #16[B],Rd 4/15 JMPL *lab[B] 3/11 MOV *lab[B],A 3/12 MOV A,*lab[B] 3/12 DEC A 1/8 INC A 1/8 INV A 1/8 CLR A 1/8 XCHB A 1/10 SWAP A 1/11 PUSH A 1/9 POP A 1/9 DJNZ A,ra 2/10 COMPL A 1/8 DEC B 1/8 INC B 1/8 INV B 1/8 CLR B 1/8 XCHB A / TST B 1/10 SWAP B 1/11 PUSH B 1/9 POP B 1/9 DJNZ B,ra 2/10 COMPL B 1/8 9 A B CLRC / TST A 1/9 C MOV A,B 1/9 D MOV A,Rd 2/7 MOV B,Rd 2/7 DEC Rn 2/6 INC Rn 2/6 INV Rn 2/6 CLR Rd 2/6 XCHB Rn 2/8 SWAP Rn 2/9 PUSH Rs 2/7 POP Rd 2/7 DJNZ Rn,ra 3/8 COMPL Rn 2/6 E TRAP 15 1/14 TRAP 14 1/14 TRAP 13 1/14 TRAP 12 1/14 TRAP 11 1/14 TRAP 10 1/14 TRAP 9 1/14 TRAP 8 1/14 TRAP 7 1/14 TRAP 6 1/14 TRAP 5 1/14 TRAP 4 1/14 IDLE 1/6 MOV #n,Pd 3/10 SETC 1/7 RTS 1/9 RTI 1/12 PUSH ST 1/8 F LDST n 2/6 MOV *n[SP],A 2/7 MOV *A,n[SP] 2/7 CMP *n[SP],A 2/8 extend inst,2 opcodes
1
2
3
4
L S N
5
6
7
8
9
A
B
All conditional jumps (opcodes 01-0F), BTJO, BTJZ, and DJNZ instructions use two additional cycles if the branch is taken. The BTJO, BTJZ, and DJNZ instructions have a relative address as the last operand. Abbreviations are explained on the next page of this table.
Table 16-4. TMS370 Family Opcode/Instruction Map (Concluded)
MSN
0 C JNV ra 2/5 JGE ra 2/5 JG ra 2/5 JLO ra 2/5 1 MPY Rs,A 2/46 CMP Rs,A 2/7 DAC Rs,A 2/9 DSB Rs,A 2/9 2 MPY #n,A 2/45 CMP #n,A 2/6 DAC #n,A 2/8 DSB #n,A 2/8 3 MPY Rs,B 2/46 CMP Rs,B 2/7 DAC Rs,B 2/9 DSB Rs,B 2/9 4 MPY Rs,Rd 3/48 CMP Rs,Rd 3/9 DAC Rs,Rd 3/11 DSB Rs,Rd 3/11 5 MPY #n,B 2/45 CMP #n,B 2/6 DAC #n,B 2/8 DSB #n,B 2/8 6 MPY B,A 1/47 CMP B,A 1/8 DAC B,A 1/10 DSB B,A 1/10 7 MPY #n,Rs 3/47 CMP #n,Rd 3/8 DAC #n,Rd 3/10 DSB #n,Rd 3/10 8 BR lab 3/9 CMP &lab,A 3/11 CALL lab 3/13 CALLR lab 3/15 9 BR *Rd 2/8 CMP *Rs,A 2/10 CALL *Rd 2/12 CALLR *Rd 2/14 A BR *lab[B] 3/11 CMP *lab[B],A 3/13 CALL *lab[B)] 3/15 CALLR *lab[B] 3/17 B RR A 1/8 RRC A 1/8 RL A 1/8 RLC A 1/8 C RR B 1/8 RRC B 1/8 RL B 1/8 RLC B 1/8 D RR Rn 2/6 RRC Rn 2/6 RL Rn 2/6 RLC Rn 2/6 E TRAP 3 1/14 TRAP 2 1/14 TRAP 1 1/14 TRAP 0 1/14 F POP ST 1/8 LDSP 1/7 STSP 1/8 NOP 1/7
L S N
D
E
F
Second byte of two-byte instructions (F4xx):
F4
8
MOVW *n[Rp] 4/15 JMPL *n[Rp] 4/16 MOV *n[Rp],A 4/17 MOV A,*n[Rp] 4/16 BR *n[Rp] 4/17 CMP *n[Rp],A 4/18 CALL *n[Rp] 4/20 CALLR *n[Rp] 4/22
DIV Rn,A 3/14-63
F4
9
F4
A
F4 * & # #16 lab n Pd Pn Ps ra Rd Rn Rp Rpd Rps Rs = = = = = = = = = = = = = = = = Indirect addressing operand prefix Direct addressing operand prefix Immediate operand Immediate 16-bit number 16-bit label Immediate 8-bit number Peripheral register containing destination type Peripheral register Peri heral Peripheral register containing source byte Relative address Register containing destination type g Register file Register pair Destination register pair Source register pair Register containing source byte
B
Assembly Language Instruction Set
16-31
F4
C
F4
D
F4
E
Instruction Set Overview
F4
F
All conditional jumps (opcodes 01-0F), BTJO, BTJZ, and DJNZ instructions use two additional cycles if the branch is taken. The BTJO, BTJZ, and DJNZ instructions have a relative address as the last operand.
Instruction Set Descriptions
16.5
Instruction Set Descriptions
The TMS370 instruction set contains 73 instructions that are supported by 246 opcodes. Each operation has an associated opcode. Some instructions, including those using the offset indirect addressing mode, have 16-bit (or dual) opcodes. Several bit manipulation instructions are constructed by the assembler out of other instructions to simplify writing the instructions and to enhance the readability of the program. The following pages contain the individual instruction descriptions. The instructions are in alphabetical order by mnemonic. Refer to Table 16-1 on page 16-3 for the symbol definitions that are used in the instruction descriptions. Refer to subsection 3.2.2, on page 3-5, on the status register for a defini tion of the status bits.
16-32
Add With Carry
ADC
Syntax Execution Options
ADC s, Rd (s) + (Rd) + (C) (Rd) inst ADC ADC ADC ADC ADC ADC ADC C Z N V operands B,A Rs,A Rs,B Rs,Rd #iop8,A #iop8,B #iop8,Rd bytes 1 2 2 3 2 2 3 cycles 8 7 7 9 6 6 8 opcode 69 19 39 49 29 59 79 operation (B)+(A)+(C) (A) (Rs)+(A)+(C) (A) (Rs)+(B)+(C) (B) (Rs)+(Rd)+(C) (Rd) iop8+(A)+(C) (A) iop8+(B)+(C) (B) iop8+(Rd)+(C) (Rd)
Status Bits Affected
Set to 1 on carryout of (s) + (Rd) + (C) Set on result Set on result (C XOR N) AND (source [bit 7] XNOR destination [bit 7])
Description
ADC adds the contents of the source, the destination register, and the carry bit and stores the result in the destination register. Adding a 0 to the destination register is equivalent to a conditional increment (increment on carry). You can use ADC for the multiprecision addition of signed or unsigned integers. For example, the 16-bit integer in register pair (R2,R3) can be added to the 16-bit integer in (A,B) as follows:
ADD R3,B ADC R2,A ; Low-order bytes added ; High-order bytes added
Examples
LABEL1
ADC R66,R117
; Adds the contents of ; register 66, register ; 117, and the carry bit, ; and stores the sum in ; register 117 ; Adds the contents of ; register B, register A, ; and the carry bit, and ; stores the sum in ; register A ; Adds #3Ch, contents of ; register 29, and the ; carry bit, and stores ; the sum in register 29
ADC
B,A
ADC #03Ch,R29
Assembly Language Instruction Set
16-33
ADD Add
Syntax Execution Options ADD s, Rd (s) + (Rd) (Rd) inst ADD ADD ADD ADD ADD ADD ADD C Z N V operands B,A Rs,A Rs,B Rs,Rd #iop8,A #iop8,B #iop8,Rd bytes 1 2 2 3 2 2 3 cycles 8 7 7 9 6 6 8 opcode 68 18 38 48 28 58 78 operation (B)+(A) (A) (Rs)+(A) (A) (Rs)+(B) (B) (Rs)+(Rd) (Rd) iop8+(A) (A) iop8+(B) (B) iop8+(Rd) (Rd)
Status Bits Affected
Set to 1 on carry-out of (s) + (Rd) Set on result Set on result (C XOR N) AND (Source [bit 7] XNOR Destination [bit 7])
Description
ADD adds the source value and destination register and stores the result in the destination register. You can use ADD for signed 2s complement or unsigned addition.
LABEL ADD B,A ; Adds the contents of ; registers B and A and ; stores the results in A ; Adds the contents of R7 ; and A and stores the ; results in A ; Adds the value of ; TOTAL to R13 and stores ; the result in R13
Examples
ADD R7,A
ADD #TOTAL,R13
16-34
Logical AND
AND
Syntax Execution Options
AND s, Rd (s) AND (Rd) (Rd) inst AND AND AND AND AND AND AND AND AND AND C N Z V operands A,Pd B,A B,Pd Rs,A Rs,B Rs,Rd #iop8,A #iop8,B #iop8,Rd #iop8,Pd bytes 2 1 2 2 2 3 2 2 3 3 cycles 9 8 9 7 7 9 6 6 8 10 opcode 83 63 93 13 33 43 23 53 73 A3 operation (A) AND (Pd) (Pd) (B) AND (A) (A) (B) AND (Pd) (Pd) (Rs) AND (A) (A) (Rs) AND (B) (B) (Rs) AND (Rd) (Rd) iop8 AND (A) (A) iop8 AND (B) (B) iop8 AND (Rd) (Rd) iop8 AND (Pd) (Pd)
Status Bits Affected
0 Set on result Set on result 0
Description
AND logically ANDs the two 8-bit source and destination operands. Each bit in the first operand is ANDed with the corresponding bit in the second operand. This is useful for clearing bits. If you need to clear a bit in the destination operand, put a 0 in the corresponding source bit. A 1 in a source bit will not change the corresponding destination bit.
LABEL AND #01h,R12 ; Clear all bits in R12 except ; bit 0, which remains ; unchanged ; AND the contents of R7 to A ; and store the contents in A ; AND contents of B to P025, ; store the contents in P025
Examples
AND
R7,A
AND
B,P025
Assembly Language Instruction Set
16-35
BR Branch
Syntax Execution Options BR XADDR XADDR (PC) inst BR BR BR BR None BR branches to any location in memory, including the on-chip RAM. BR supports the following four program flow absolute addressing modes: operands label *Rp *label[B] *off8[Rp] bytes 3 2 3 4 cycles 9 8 11 16 opcode 8C 9C AC F4 EC operation label (PC) (Rp-1:Rp) (PC) label+(B) (PC) (Rp-1:Rp)+off8 (PC)
Status Bits Affected Description
-
Direct Indirect Indexed Offset Indirect
The powerful concept of computed GOTOs is supported by the BR *Rp instruction. Additionally, an indexed branch instruction of the form BR *TABLE[B] is an efficient way to execute one of several actions on the basis of a control input; this is similar to the Pascal CASE statement. The program can branch to up to 128 different jump statements. You can use BR to transfer control on character inputs, error codes, etc. Examples
LABEL BR BR BR BR BR LABEL4 5432h *LABEL5[B] *1234h[B] *R12 ; (PC) LABEL4 ; (PC) 5432h ; (PC) LABEL5 + (B) ; (PC) 1234h + (B) ; (PC) (R11:R12) ; R12 = LSbyte ; (PC) 56 + (R9:R10) ; R10 = LSbyte
BR
*56[R10]
16-36
Bit Test and Jump if One
BTJO
Syntax Execution
BTJO s1,s2,off8 If (s1) AND (s2) 0, then PCN + off8 (PC), else PCN (PC)
Options
inst BTJO BTJO BTJO BTJO BTJO BTJO BTJO BTJO BTJO BTJO
operands A,Pd,#off8 B,A,#off8 B,Pd,#off8 Rs,A,#off8 Rs,B,#off8 Rs,Rd,#off8 #iop8,A,#off8 #iop8,B,#off8 #iop8,Rd,#off8 #iop8,Pd,#off8
bytes 3 2 3 3 3 4 3 3 4 4
cycles opcode jump if 10/12 86 (A) AND (Pd) 0 10/12 66 (B) AND (A) 0 10/12 96 (B) AND (Pd) 0 9/11 16 (Rs) AND (A) 0 9/11 36 (Rs) AND (B) 0 11/13 46 (Rs) AND (Rd) 0 8/10 26 iop8 AND (A) 0 8/10 56 iop8 AND (B) 0 10/12 76 iop8 AND (Rd) 0 11/13 A6 iop8 AND (Pd) 0
The number of cycles to the left of the slash are valid when the jump is not taken; the number of cycles to the right of the slash are valid when the jump is taken.
Status Bits Affected
C N Z V
0 Set on (s) AND (d) Set on (s) AND (d) 0
Description
BTJZ jumps if a bit in source operand s1 has a 1 and its corresponding bit position in s2 also has a 1 (refer to the table below -- jumps if any two corresponding bit positions in s1 and s2 are both 1). The s1 source operand can be used as a bit mask to test for one or more 1 bits in the specified register. The operands are not changed by this instruction. The table below contains examples wher jumps occur and don't occur.
s1 00000001 00000001 00000011 11110000 11110000 s2 xxxxxxx0 xxxxxxx1 xxxxxx00 1000xxxx 1001xxxx Jump? No Yes No Yes Yes
Examples
LABEL
BTJO #014,R4,#ISSET
; Jump to ISSET if R4 (bit 2) ; or R4 (bit 4) is a 1 ; Jump to LOOP if bit 0 ; of register A is a 1 ; Jump to START if any 1 bit ; of R113 corresponds to a ; 1 bit in R37
BTJO #01,A,#LOOP
BTJO R37,R113,#START
Assembly Language Instruction Set
16-37
BTJZ
Syntax
Bit Test and Jump if Zero
BTJZ s1,s2,off8 If (s1) AND NOT (s2) 0, then PCN + off8 (PC), else PCN (PC) inst BTJZ BTJZ BTJZ BTJZ BTJZ BTJZ BTJZ BTJZ BTJZ BTJZ operands A,Pd,#off8 B,A,#off8 B,Pd,#off8 Rd,A,#off8 Rd,B,#off8 Rs,Rd,#off8 #iop8,A,#off8 #iop8,B,#off8 #iop8,Rd,#off8 #iop8,Pd,#off8 bytes cycles opcode jump if 3 10/12 87 (A) AND NOT(Pd) 0 2 10/12 67 (B) AND NOT(A) 0 3 10/12 97 (B) AND NOT(Pd) 0 3 9/11 17 (Rd) AND NOT(A) 0 3 9/11 37 (Rd) AND NOT(B) 0 4 11/13 47 (Rs) AND NOT(Rd) 0 3 8/10 27 iop8 AND NOT (A) 0 3 8/10 57 iop8 AND NOT (B) 0 4 10/12 77 iop8 AND NOT (Rd) 0 4 11/13 A7 iop8 AND NOT (Pd) 0
Execution Options
The number of cycles to the left of the slash are valid when the jump is not taken; the number of cycles to the right of the slash are valid when the jump is taken. The instruction must have at least one 1 value bit in s1.
Status Bits Affected
C N Z V
0 Set on (s) AND NOT (Rd) Set on (s) AND NOT (Rd) 0
Description
BTJZ jumps if a bit in source operand s1 has a 1 and its corresponding bit position in s2 has a 0 (refer to the table below). The s1 source operand can be used as a bit mask to test for 0 bits in the specified register. The operands are not changed by this instruction. The jump is calculated starting from the opcode of the instruction immediately after the BTJZ.
s1 00000001 00000001 11000000 11110000 11110000 s2 xxxxxxx0 xxxxxxx1 11xxxxxx 0111xxxx 0110xxxx Jump? Yes No No Yes Yes
Examples
LABEL
BTJZ
A,P23,#ZERO
; If any 1 bit in reg. A ; corresponds to a 0 bit ; in P23, then jump to ZERO ; If reg. A contains any 0 ; bits, jump to NEXT ; If any 0 bits in R15 ; correspond to 1 bits ; in R7, jump to OUT
BTJZ #0FFh,A,#NEXT
BTJZ
R7,R15,#OUT
16-38
Call
CALL
Syntax Execution
CALL XADDR (SP) + 1 PCN MSbyte (SP) + 1 PCN LSbyte XADDR (SP) ((SP)) (SP) ((SP)) (PC)
(The stack contains the address of the instruction immediately following the CALL.) Options inst CALL CALL CALL CALL None CALL invokes a subroutine and pushes the PC contents on the stack. The operand indicates the starting address of the subroutine. The program flow addressing modes of the CALL instruction support the powerful transfer of control functions.
LABEL CALL CALL CALL CALL CALL LABEL4 5432h *LABEL5[B] *1234h[B] *R12 ; Push PC; (PC) LABEL4 ; Push PC; (PC) 5432h ; Push PC; (PC) LABEL5 + (B) ; Push PC; (PC) 1234h + (B) ; Push PC; (PC) (R11:R12) ; R12 = LSbyte ; Push PC; (PC) 56 + (R9:R10) ; R10 = LSbyte
operands label *label[B] *off8[Rp] *Rp
bytes 3 3 4 2
cycles 13 15 20 12
opcode 8E AE F4 EE 9E
operation label (PC) label+(B) (PC) (Rp-1:Rp)+off8 (PC) (Rp-1:Rp) (PC)
Status Bits Affected Description
Examples
CALL
*56[R10]
Assembly Language Instruction Set
16-39
CALLR
Syntax
Call Relative
CALLR XADDR (SP) + 1 PCN MSbyte (SP) + 1 PCN LSbyte XADDR + PCN
inst CALLR CALLR CALLR CALLR CALLR CALLR #off16 label *Rp *off16[B] *label[B] *off8[Rp]
Execution
(SP) ((SP)) (SP) ((SP)) (PC)
bytes cycles 3 3 2 3 3 4 15 15 14 17 17 22 opcode operation 8F 8F 9F AF AF F4 EF off16 + PCN (PC) off16 + PCN (PC) (Rp-1:Rp) + PCN (PC) off16 + (B)+ PCN (PC) off16 + (B) + PCN (PC) (Rp-1:Rp) + off8 + PCN (PC)
Options
operands
Status Bits Affected Description
None CALLR is similar to CALL, but it uses a value relative to the current program counter (PCN). The program flow relative addressing modes of the CALLR instruction support the powerful transfer of control functions. This is useful for relocatable code produced by linkers, compilers, or other high-level language structures. The assembler automatically calculates the correct offset value for the two modes by using labels in the operands.
Relative Direct Addressing: LABEL CALLR LABEL4 ; Push PC ; (PC) PCN + off16, ; off16 = LABEL4-PCN ; Push PC ; (PC) PCN + 5432h ; Push PC ; (PC) PCN + ; off16 +(B) ; off16=LABEL5 - PCN ; Push PC ; (PC) PCN + ; 1234h + (B) ; Push PC ; (PC) PCN + ; (R11:R12) ; R12=LSbyte ; Push PC ; (PC) PCN ; + 56 + (R9:R10) ; R10=LSbyte
Examples
CALLR #5432h Relative Indexed Addressing: CALLR *LABEL5[B]
CALLR *1234h[B] Relative Indirect Addressing: CALLR *R12
Relative Offset Indirect Addressing: CALLR *56[R10]
16-40
Clear
CLR
Syntax Execution Options
CLR Rd 0 (Rd) inst CLR CLR CLR C N Z V 0 0 1 0 operands A B Rd bytes 1 1 2 cycles 8 8 6 opcode B5 C5 D5 operation 0 (A) 0 (B) 0 (Rd)
Status Bits Affected
Description Examples
CLR clears or initializes to 0 any register, including registers A and B.
LABEL CLR CLR CLR B A R105 ; Clear register B ; Clear register A ; Clear register 105
Assembly Language Instruction Set
16-41
CLRC
Syntax
Clear the Carry Bit
CLRC Set status bits inst CLRC C N Z V operands none bytes 1 cycles 9 opcode B0
Execution Options
Status Bits Affected
0 Set on value of register A Set on value of register A 0
Description
CLRC clears the carry flag. This instruction may be required before an arithmetic or rotate instruction. The logical and move instructions typically clear the carry bit. The CLRC opcode is equivalent to the TST A opcode.
LABEL CLRC ; Clear the carry bit
Example
16-42
Compare
CMP
Syntax Execution Options
CMP s,d (d) - (s) computed but not stored inst operands Data Manipulation: CMP B,A CMP Rs,A CMP Rs,B CMP Rs,Rd CMP #iop8,A CMP #iop8,B CMP #iop8,Rd CMP &label,A CMP *label[B],A CMP *off8[Rp],A CMP *Rp,A CMP *off8[SP],A bytes 1 2 2 3 2 2 3 3 3 4 2 2 cycles 8 7 7 9 6 6 8 11 13 18 10 8 opcode operation 6D 1D 3D 4D 2D 5D 7D 8D AD F4 ED 9D F3 (A)-(B) (A)-(Rs) (B)-(Rs) (Rd)-(Rs) (A)-iop8 (B)-iop8 (Rd)-iop8 (A)-(label) (A)-(label+(B)) (A)-((Rp-1:Rp)+off8) (A)-((Rp-1:Rp)) (A)-((SP)+off8)
Note: Operations are computed but not stored. Status bits are set on results.
Status Bits Affected
C N Z V
1 if (d) (s) Sign of result 1 if (d) = (s) (C XOR N) AND (Source [bit 7] XOR Destination [bit 7])
Description
CMP compares the destination operand to the source operand and sets the status bits. The CMP instruction is usually used in conjunction with a jump instruction. Table 16-5 shows which jump instructions can be used on status conditions set by CMP execution. There are only seven possible outcomes of the status register after a compare instruction. The jump instructions JC and JHS are equivalent after a compare.
Assembly Language Instruction Set
16-43
CMP Compare
Table 16-5. Compare Instruction Examples--Status Bit Values
Operand Opcodes (s) (d) Status Bits CNZV JEQ/ JZ JNE/ JNZ
JGE
JG
JL
JLE
JLO
JHS
JC
JNC
JN
JP
JPZ
JV
JNV
FF 00 81 00 80 00 80 7F 00 7F 20 30 90 A0 7F 00 30 20 A0 90 7F 80 00 FF 00 81 00 80 7F 7F
Notes:
0000 0101 1000
1 1 1
1 1 1
0 0 0
0 0 0
1 1 0
0 0 1
0 0 1
1 1 0
0 1 0
1 0 1
0 0 0
1 0 1
1 1 1
0 1 0
1 0 1
0100
0
0
1
1
1
0
0
1
1
0
0
0
1
0
1
1001 1100
0 0
0 0
1 1
1 1
0 0
1 1
1 1
0 0
0 1
1 0
0 0
1 0
1 1
1 0
0 1
1010
1
0
0
1
0
1
1
0
0
0
1
1
0
0
1
1) Signed Jumps: JGE, JG, JL, JLE. Unsigned Jumps: JLO, JHS. Test Bits: JC, JNC, JN, JP, JEQ/JZ, JPZ, JNE/JNZ, JV, JNZ 2) 1 = jump was taken; 0 = jump was not taken
Examples
LABEL
CMP R13,R89
; Set status bits on ; result of R89 minus R13 ; Set status bits on result ; of (B) minus R39 ; Set status bits on result ; of (A) minus #03h ; Set status bits on result ; of (A) minus (TABLE + (B))
CMP R39,B
CMP #003h,A
CMP *TABLE[B],A
16-44
Complement Bit
CMPBIT
Syntax Execution Options
CMPBIT name NOT
inst operands bytes cycles opcode operation 3 3 8 10 75 A5 NOT (bit) (bit) Register bits NOT (bit) (bit) PF bits CMPBIT Rname CMPBIT Pname
Status Bits Affected
C N Z V
0 Set on result of (Mask XOR (s)) Set on result of (Mask XOR (s)) 0
Description
CMPBIT is an assembler-constructed instruction that conveniently complements the value of the named bit without having to specify a register or mask. This enhances the readability of the program. The CMPBIT instruction assembles to the instructions XOR #iop8,Rd or XOR #iop8,Pd. The name for the bit is defined by the .DBIT assembler directive.
INT1ENA .DBIT 7,P017 ; Interrupt 1 bit is now ; named INT1ENA ; Bit 4 of register 33 is now ; named TEST ; Invert the value of the TEST ; bit. ; Change the interrupt 1 ; enabled condition.
Examples
TEST
.DBIT
4,R33
LABEL
CMPBIT TEST
CMPBIT INT1ENA
Assembly Language Instruction Set
16-45
COMPL
Syntax Execution Options
2s Complement
COMPL Rd 0 - Rd Rd inst COMPL COMPL COMPL C N Z V operands A B Rd bytes 1 1 2 cycles 8 8 6 opcode BB CB DB operation NOT(A)+1 (A) NOT(B)+1 (B) NOT(Rd)+1 (Rd)
Status Bits Affected
Set on result Set on result Set on result 1 if 80h is the result; 0 otherwise
Description
COMPL provides a logical or 2s complement of the operand. This is the equivalent to an inversion of all the bits followed by an increment. The instruction is useful in doing arithmetic with signed numbers.
LABEL COMPL COMPL COMPL A B R82 ; Complement register A ; Complement register B ; Complement register 82
Examples
16-46
Decimal Add With Carry
DAC
Syntax Execution Options
DAC s,Rd (s) + (Rd) + (C) (Rd), produces a decimal result inst DAC DAC DAC DAC DAC DAC DAC C N Z V operands B,A Rs,A Rs,B Rs,Rd #iop8,A #iop8,B #iop8,Rd bytes 1 2 2 3 2 2 3 cycles 10 9 9 11 8 8 10 opcode 6E 1E 3E 4E 2E 5E 7E operation (B)+(A)+(C) (A) (Rs)+(A)+(C) (A) (Rs)+(B)+(C) (B) (Rs)+(Rd)+(C) (Rd) iop8+(A)+(C) (A) iop8+(B)+(C) (B) iop8+(Rd)+(C) (Rd)
Status Bits Affected
1 if value of (s) + (Rd) + C > 99 Set on result Set on result Undefined
Description
DAC adds bytes in binary-coded decimal (BCD) form. Each byte is assumed to contain two BCD digits. DAC is not defined for non-BCD operands. DAC with an immediate operand of zero value is equivalent to a conditional increment of the destination operand (increment destination on carry). The DAC instruction automatically performs a decimal adjust on the binary sum of (s) + (d) + C. The carry bit is added to facilitate adding multibyte BCD strings; therefore, the carry bit must be cleared before the first DAC instruction is executed.
Examples
LABEL
DAC #024h,A
; If register A contains 097h ; and C = 0,then the final result ; put into A is 021h and the carry ; bit is set ; Add the BCD value of R55, ; and the carry bit to the ; BCD value of R7 ; Add the carry bit to the ; BCD value in register B ; to register A
DAC
R55,R7
DAC
B,A
Assembly Language Instruction Set
16-47
DEC Decrement
Syntax Execution Options DEC Rd (Rd) - 1 (Rd) inst DEC DEC DEC C N Z V operands A B Rd bytes 1 1 2 cycles 8 8 6 opcode B2 C2 D2 operation (A)-1 (A) (B)-1 (B) (Rd)-1 (Rd)
Status Bits Affected
0 if (Rd) decrements from 00h to FFh; 1 otherwise Set on result Set on result 1 if (Rd) decrements from 80h to 7Fh; 0 otherwise
Description Examples
DEC subtracts 1 from any register. It is useful for counting and addressing byte arrays.
LABEL DEC R102 DEC A ; Decrement R102 by 1 ; Subtract 1 from the contents of ; register A ; Subtract 1 from the contents of ; register B
DEC
B
16-48
Disable Interrupts
DINT
Syntax Execution Options
DINT 0 (ST) inst DINT C 0 N 0 Z 0 V 0 IE1 0 IE2 0 DINT simultaneously disables all interrupts. Since the interrupt enable flags are stored in the status register, the POP ST or RETI instructions may re-enable interrupts, even though a DINT instruction has been executed. During the interrupt service, the interrupt enable bit is automatically cleared after the old status register value has been pushed onto the stack. The DINT instruction is equal to the LDST #00 instruction.
LABEL DINT ; Disable high- and low-level interrupts.
operands none
bytes 2
cycles 6
opcode F0 00
Status Bits Affected
Description
Example
Assembly Language Instruction Set
16-49
DIV Divide
Syntax Execution Options DIV Rs, A A:B/(Rs) A(=quo), B(=rem) inst DIV
Note:
operands Rs,A
bytes 3
cycles 55-63
opcode operation F4 F8 (A:B)/(Rs) Quotient A Remainder B
If overflow occurs, 14 cycles are used, and C,N,Z,V = 1
Status Bits Affected
C N Z V
0 Set on results (register A) Set on results (register A) 0
Description
DIV divides the 16-bit value in the A:B register pair by the 8-bit value in the specified register. The resulting 8-bit quotient is stored in A with the remainder stored in B (note these are 8-bit values maximum). Overflow conditions are checked before the DIV instruction is executed; if an overflow is detected, the operands are left unchanged, the status bits C,N,Z, and V are set to 1, and the instruction is aborted. Execution time varies from 55-63 cycles, depending on the operands, with an overflow condition taking only 14 cycles. The average execution time is 57 cycles.
LABEL DIV R10,A ;R10 is divided into the ;A:B register pair (A = MSbyte) ;Carry is 1 on overflow conditions
Example
JC OVERFLOW
The TMS370 Microcontroller Family Application Book (SPNA017) contains example routines to enhance capabilities of the DIV instruction such as providing a 16-bit quotient from the division of a 16-bit concatenated number by an 8-bit number.
16-50
Decrement Register and Jump if Not Zero
DJNZ
Syntax Execution Type Options
DJNZ Rn,off8 (Rn) - 1 (Rn) If (Rn) 0, then PCN + (off8) (PC), else PCN (PC) Single Operand
inst DJNZ DJNZ DJNZ operands A,#off8 B,#off8 Rd,#off8 bytes cycles opcode operation 2 2 3 10/12 10/12 8/10 BA CA DA (A)-1 (A), jump if (A) 0 (B)-1 (B), jump if (B) 0 (Rd)-1 (Rd), jump if (Rd) 0
The number of cycles to the left of the slash are valid when the jump is not taken; the number of cycles to the right of the slash are valid when the jump is taken.
Status Bits Affected Description
None DJNZ is used for loop control. It combines the DEC and the JNZ instructions, providing a faster and more compact instruction. DJNZ does not change the status bits.
LABEL DJNZ R15,THERE ; Decrement R15. If R15 0, ; jump to THERE ; Decrement A; if A 0, ; jump to AGAIN ; Decrement B; if B 0, ; jump to BACK
Examples
DJNZ
A,AGAIN
DJNZ
B,BACK
Assembly Language Instruction Set
16-51
DSB Decimal Subtract With Borrow
Syntax Execution Options DSB s,Rd (Rd) - (s) - 1 + (C) (Rd) (decimal result) inst DSB DSB DSB DSB DSB DSB DSB C N Z V operands bytes B,A 1 Rs,A 2 Rs,B 2 Rs,Rd 3 #iop8,A 2 #iop8,B 2 #iop8,Rd 3 cycles opcode operation 10 6F (A)-(B)-1+(C) (A) 9 1F (A)-(Rs)-1+(C) (A) 9 3F (B)-(Rs)-1+(C) (B) 11 4F (Rd)-(Rs)-1+(C) (Rd) 8 2F (A)-iop8-1+(C) (A) 8 5F (B)-iop8-1+(C) (B) 10 7F (Rd)-iop8-1+(C) (Rd)
Status Bits Affected
1 if no borrow required, 0 if borrow required Set on result Set on result Undefined
Description
DSB performs multiprecision BCD subtraction. The DSB instruction with an immediate operand of zero value is equivalent to a conditional decrement of the destination operand, depending on the carry bit. The carry bit functions as a no-borrow bit; if a no-borrow is required, the carry bit should be set to 1. You can accomplish this by executing the SETC instruction. The DSB instruction is undefined for non-BCD operands.
LABEL DSB R15,R76 ; R76 minus R15 minus 1 plus ; the carry bit is stored in R76 ; Register B minus register ; A minus 1 plus the carry ; bit is stored in ; register B ; R5 - 1 R5, if C = 0 ; R5 R5, if C = 1
Examples
DSB
A,B
DSB
#0,R5
16-52
Enable Interrupts
EINT
Syntax Execution Options
EINT 0Ch (ST) inst EINT C 0 N 0 Z 0 V 0 IE1 1 IE2 1 EINT simultaneously enables all global interrupts. Since the interrupt enable flags are stored in the status register, the POP ST or RTI instructions may disable interrupts, even though an EINT instruction has been executed. During the interrupt service, the interrupt enable bit is automatically cleared after the old status register value has been pushed onto the stack. Thus, the EINT instruction must be included inside the interrupt service routine to permit nested or multilevel interrupts. This instruction is equivalent to the LDST #00Ch instruction.
LABEL EINT ; All interrupts are enabled
operands none
bytes 2
cycles 6
opcode F0 0C
Status Bits Affected
Description
Example
Assembly Language Instruction Set
16-53
EINTH Enable High-Level Interrupts
Syntax Execution Options EINTH 04h (ST) inst EINTH C 0 N 0 Z 0 V 0 IE1 1 IE2 0 EINTH is similar to the EINT instruction but enables only high-level (1) interrupts and disables low-level interrupts. This assembles to the LDST #04h instruction.
LABEL EINTH ; All level 1 interrupts are enabled
operands none
bytes 2
cycles 6
opcode F0 04
Status Bits Affected
Description
Example
16-54
Enable Low-Level Interrupts
EINTL
Syntax Execution Options
EINTL 08h (ST) inst EINTL C 0 N 0 Z 0 V 0 IE1 0 IE2 1 EINTL is similar to the EINT instruction but enables only low-level (2) interrupts while disabling high-level interrupts. This assembles to the LDST #08h instruction.
LABEL EINTL ; All level 2 interrupts are enabled
operands none
bytes 2
cycles 6
opcode F0 08
Status Bits Affected
Description
Example
Assembly Language Instruction Set
16-55
IDLE Idle Until Interrupt
Syntax Execution Options IDLE (PC) + 1 (PC) after return from interrupt inst IDLE None The IDLE instruction causes the device to enter one of three modes: halt, standby, or idle. Two of these modes, halt and standby, use only a fraction of the normal operating power. operands none bytes 1 cycles 6 (minimum) opcode F6
Status Bits Affected Description
-
In standby mode, the on-chip oscillator and timer 1 module remain active. In halt mode, the oscillator is off, and the chip consumes the least amount of power.
If you execute an IDLE instruction when low-power modes are disabled through a programmable contact (mask-ROM devices only), the device will always enter the idle mode. Appropriate interrupts must be enabled before the device enters idle mode. For more information on the low-power or idle modes, refer to Section 4.2. Example
LABEL IDLE ; Enter idle mode and ; wait for interrupt
16-56
Increment
INC
Syntax Execution Options
INC Rd (Rd) + 1 (Rd) inst INC INC INC C N Z V operands A B Rd bytes 1 1 2 cycles 8 8 6 opcode B3 C3 D3 operation (A)+1 (A) (B)+1 (B) (Rd)+1 (Rd)
Status Bits Affected
1 if (Rd) incremented from FFh to 00h; 0 otherwise Set on result Set on result 1 if (Rd) incremented from 7Fh to 80h; 0 otherwise
Description Examples
INC increments the value of any register. It is useful for incrementing counters.
LABEL INC INC INC A B R43 ; Increment register A by 1 ; Increment register B by 1 ; Increment register 43 by 1
Assembly Language Instruction Set
16-57
INCW Increment Word
Syntax Execution Options INCW #iop8,Rp (Rp) + #iop8 (Rp) inst operands bytes cycles opcode operation INCW #iop8,Rp 3 11 70 iop8+(Rp-1:Rp) (Rp-1:Rp) iop8 = 8-bit immediate operand C N Z V Set to 1 on carry out of iop8 + (Rp) Set on result Set on MSbyte ( C XOR N ) AND (MSB iop8 XNOR MSB (Rd))
Status Bits Affected
Description
INCW increments the value of any register pair by the amount specified. The register pair can be incremented by as much as 127 or decremented by as much as 128. This instruction is useful for incrementing counters into large tables. The iop8 is sign-extended to perform 16-bit 2s-complement addition. The JC and JNC are commonly used after the INCW instruction for loop control.
LABEL INCW #1,R10 INCW #-1,R10 INCW #064h,R255 ; Increment R9:R10 by 1 ; Decrement register R9:R10 by 1 ; Increment register pair ; R254:R255 by #064h
Examples
16-58
Invert
INV
Syntax Execution Options
INV Rd NOT(Rd) (Rd) inst INV INV INV C N Z V operands A B Rd 0 Set on result Set on result 0 bytes 1 1 2 cycles 8 8 6 opcode B4 C4 D4 operation NOT(A) (A) NOT(B) (B) NOT(Rd) (Rd)
Status Bits Affected
Description
INV performs a 1s complement of the operand. A 1s complement inverts the value of every bit in the register. You can perform a 2s complement of the operand by following the INV instruction with an increment (INC) or by simply using the COMPL instruction.
LABEL INV A ; Invert register A (0s become 1s, ; 1s become 0s) ; Invert register B : Invert register 82
Examples
INV B INV R82
Assembly Language Instruction Set
16-59
JBIT0
Syntax
Jump If Bit = 0
JBIT0 name, #off8 If bit (name) = 0, then PCN + off8 (PC), else PCN PC inst JBIT0 JBIT0
Note:
Execution Options
operands Rname,#off8 Pname,#off8
bytes 4 4
cycles 10 11
opcode 77 A7
Add two cycles if jump is taken
Status Bits Affected
C N Z V
0 Set on (s) AND NOT (Rd) Set on (s) AND NOT (Rd) 0
Description
The JBIT0 is an assembler-constructed instruction that conveniently jumps to the label if the value of the named bit is zero. This enhances the readability of the program because the source does not have to specify both the register containing the bit and a mask. JBIT0 is assembled to BTJZ #iop8,Rd,label or BTJZ #iop8,Pd,label. The name for the bit is defined by the .DBIT assembler directive.
MCDATA ; ; ; ; .DBIT 4,R3 ; ; ; JBIT0 BIT4,#THERE ; ; ; JBIT0 MCDATA,#HERE ; ; .DBIT 2,P010 MC data in bit 2 of SCCR0 (P010) is now named MCDATA Bit 4 of register 3 is now named BIT4 Jump to THERE if bit 4 in register 3 is zero. Jump to HERE if the MC pin is zero
Examples
BIT4
16-60
Jump if Bit = 1
JBIT1
Syntax Execution Options
JBIT1 name, #off8 bit (name) = 1, then PCN + off8 (PC), else PCN (PC) inst JBIT1 JBIT1
Note:
operands Rname,#off8 Pname,#off8
bytes 4 4
cycles 10 11
opcode operation 76 register bits A6 peripheral bits
Add two cycles if jump is taken.
Status Bits Affected
C N Z V
0 Set on (s) AND (Rd) Set on (s) AND (Rd) 0
Description
The JBIT1 is an assembler-constructed instruction that conveniently jumps to the label if the value of the named bit is one. This instruction enhances the readability of the program because the source does not have to specify both the register containing the bit and a mask. This instruction assembles to BTJO #iop8,Rd,label or BTJO #iop8,Pd,label. The name for the bit is defined by the .DBIT assembler directive.
BUSYP .DBIT 7,P01C ; ; ; ; ; ; ; ; ; ; ; ; Busy bit in PEECTL (program EEPROM) is now named BUSYP Bit 0 of register 100 is now named BIT0 Jump to THERE if bit 0 in register 100 is a one. Jump to HERE if the program EEPROM is busy.
Examples
BIT0
.DBIT 0,R100
LABEL
JBIT1 BIT0, #THERE
JBIT1 BUSYP,#HERE
Assembly Language Instruction Set
16-61
Jcnd
Syntax
Jump on Condition
Jcnd #off8 If tested condition is true, (PCN) + off8 (PC), else PCN (PC) None The Jcnd instructions (listed in Table 16-6) are commonly used after a CMP instruction to branch according to the relative values of the operands tested. After MOV operations, a JZ or JNZ can be used to test whether the value moved was equal to zero; in this case, JN and JPZ are used to test the sign bit of the value moved. In addition, the program can check the overflow bit V after executing an arithmetic instruction with the JV or JNV instructions. All Jcnd instructions are two bytes in length and require five cycles to execute; however, if the jump is taken, the instruction requires seven cycles.
Execution Status Bits Affected Description
Table 16-6. Conditional-Jump Instructions
Instruction Jump if Carry Jump if No Carry Jump if Equal Jump if Not Equal Jump if Nonzero Jump if Zero Jump if Lower Jump if Higher or Same Mnemonic JC JNC JEQ JNE JNZ JZ
JLO JHS
Opcode 03 07 02 06 06 02
0F 0B
C 1 0 x x x x
0 -
N x x x x x x
x x
Z x x 1 0 0 1
0 -
V x x x x x x
x x
Operation
(C = 1) OR (Z = 1) --Signed Operation-- Z OR (N XOR V) = 0 N XOR V = 0 N XOR V = 1 Z OR (N XOR V) = 1
Jump if Greater Jump if Greater or Equal Jump if Less Jump if Less or Equal Jump if Negative Jump if Positive Jump if Positive or Zero Jump if No Overflow Jump if Overflow
JG JGE JL JLE JN JP JPZ JNV JV
0E 0D 09 0A 01 04 05 0C 08
x x x x x x x x x
- - - - 1 0 0 x x
- x x - x 0 x x x
- - - - x x x 0 1
Status Values: 0 Status bit always cleared. 1 Status bit always set. x Status bit cleared or set on results. - Status bit not affected.
16-62
Jump on Condition
Jcnd
These two-instruction jump sequences are used in place of the single conditional jumps for the numbers shown in the tables. ($ is the current PC value.)
Signed Number Jumps Condition ds Negative Positive Positive or 0 Notes: True JL JLE JEQ JGE JG JN JP JPZ False JGE JG JNE JL JLE JPZ Note 1 JN Unsigned Number Jumps Condition ds True JLO Note 2 JEQ JHS Note 3 False JHS Note 3 JNE JLO Note 2
1) JZ LABEL JN LABEL 2) JEQ LABEL JLO LABEL 3) JEQ $+4 JHS LABEL Status Bit Jumps
Bits C N Z V
True JC JN JZ JV
False JNC JPZ JNZ JNV
Examples
LABEL
JNC
TABLE
; If the carry bit is clear, ; jump to TABLE ; If the negative and zero flags ; are clear, jump to HERE ; If the zero flag is set, jump ; to NEXT
JP
HERE
JZ
NEXT
Assembly Language Instruction Set
16-63
JMP
Jump Unconditional
Syntax Execution Options
JMP #off8 PCN + off8 (PC) inst JMP None JMP jumps unconditionally to the address specified in the operand. The second byte of the JMP instruction contains the 8-bit relative address of the operand. The operand address must therefore be within -128 to +127 bytes of the location of the instruction following the JMP instruction. The assembler will indicate an error if the target address is beyond -128 to +127 bytes from the next instruction. For a longer jump, you can use the BR (branch) or the JMPL instruction.
LABEL JMP #THERE ; Load the PC with the address ; of THERE
operands #off8
bytes 2
cycles 7
opcode operation 00 PCN+off8 (PC)
Status Bits Affected Description
Example
16-64
Jump Long
JMPL
Syntax Execution Options
JMPL XADDR PCN + D (PC) inst JMPL JMPL JMPL JMPL JMPL JMPL None JMPL is similar to the the JMP instruction but generates a 16-bit (instead of 8-bit) signed offset to the program counter.
LABEL JMPL LABEL4 ; (PC) PCN + offset ; offset=LABEL4-PCN ; (PC) PCN + 5432h
operands bytes cycles opcode operation #off16 3 9 89 off16+PCN (PC) label 3 9 89 off16+PCN (PC) *Rp 2 8 99 (Rp-1:Rp)+PCN (PC) *off16[B] 3 11 A9 off16+(B) +PCN (PC) *label[B] 3 11 A9 off16+(B)+PCN (PC) *off8[Rp] 4 16 F4 E9 (Rp-1:Rp)+off8+PCN (PC)
Status Bits Affected Description Example
JMPL JMPL
#5432h
*LABEL5[B] ; (PC) PCN + off8 + (B) ; offset=LABEL5 - PCN *1234h[B] *R12 ; (PC) PCN + 1234h + (B) ; (PC) PCN + (R11:R12) ; R12=LSbyte ; (PC) PCN + 56 + (R9:R10) ; R10 = LSbyte ; (PC) PCN - 2 + (R9:R10) ; R10 = LSbyte
JMPL JMPL
JMPL
*56[R10]
JMPL
*-2[R10]
Assembly Language Instruction Set
16-65
LDSP Load Stack Pointer
Syntax Execution Options LDSP (B) (SP) inst LDSP None LDSP copies the contents of register B to the stack pointer (SP). Use LDSP to initialize the stack pointer.
MOV LABEL #080h,B LDSP ; Register B = SP value. ; ; Copy register B to the stack ; pointer.
operands none
bytes 1
cycles 7
opcode FD
Status Bits Affected Description Example
16-66
Load Status Register
LDST
Syntax Execution Options
LDST #iop8 (iop8) (ST) inst LDST operands #iop8 bytes 2 cycles 6 opcode operation F0 iop8 (ST)
Status Bits Affected
C Set on value loaded N Set on value loaded Z Set on value loaded V Set on value loaded IE1 Set on value loaded IE2 Set on value loaded The LDST copies the immediate value operand to the status register (ST). Any combination of bits can be loaded into the status register using this command. Some instructions such as EINT, EINTL, EINTH, DINT are assembled into this instruction. Status bits are defined in detail in subsection 3.2.2 on page 3-5.
LABEL LDST #08Ch ; Copy immediate value to ; the status register and ; set IE2 bit
Description
Example
Assembly Language Instruction Set
16-67
MOV
Syntax
Move
MOV s,d (s) (d) inst operands bytes cycles opcode operation 1 2 1 2 2 2 3 2 2 3 2 2 3 2 2 3 3 3 3 2 2 3 3 4 4 9 7 8 7 7 7 9 6 6 8 8 8 10 8 8 10 10 10 12 9 9 12 12 17 17 7 7 C0 D0 62 D1 12 32 42 22 52 72 21 51 71 80 91 A2 F7 8B 8A 9B 9A AB AA F4 EB F4 EA F2 F1 (A) (B) (A) (Rd) (B) (A) (B) (Rd) (Rs) (A) (Rs) (B) (Rs) (Rd) iop8 (A) iop8 (B) iop8 (Rd) (A) (Pd) (B) (Pd) (Rs) (Pd) (Ps) (A) (Ps) (B) (Ps) (Rd) iop8 (Pd) (A) (label) (label) (A) (A) ((Rp-1:Rp)) ((Rp-1:Rp)) (A) (A) (label+(B)) (label+(B)) (A) (A) (off8+(Rp-1:Rp)) (off8+(Rp-1:Rp)) (A) (A) (off8+(SP)) (off8+(SP)) (A)
Execution Options
Register: MOV A,B MOV A,Rd MOV B,A MOV B,Rd MOV Rs,A MOV Rs,B MOV Rs,Rd MOV #iop8,A MOV #iop8,B MOV #iop8,Rd Peripheral: MOV A,Pd MOV B,Pd MOV Rs,Pd MOV Ps,A MOV Ps,B MOV Ps,Rd MOV #iop8,Pd Direct: MOV A,*label MOV *label,A Indirect: MOV A,*Rp MOV *Rp,A Indexed: MOV A,*label[B] MOV *label[B],A Offset Indirect: MOV A,*off8[Rp] MOV *off8[Rp],A
Stack Pointer Relative: MOV A,*off8[SP] 2 MOV *off8[SP],A 2
16-68
Move
MOV
Status Bits Affected
C N Z V
0 Set on value loaded Set on value loaded 0
Description
MOV transfers values within the memory space. Immediate values can be loaded directly into the registers. In direct, indirect, indexed, offset indirect, and stack pointer relative addressing modes, the processor must use register A. A MOV instruction that uses register A or B as an operand requires fewer bytes. When the MOV Pn,Rn and MOV Rn,Pn instructions are assembled into machine code, their operands are reversed.
MOV A,B ; Move the contents of register ; A to register B ; Move the contents of register ; 32 to register 105 ; Move #010h to register 3
Examples
MOV
R32,R105
MOV MOV
#010h,R3
A,*LABEL[B] ; Move the contents of register A to the ; location LABEL+B A,*2Fh[R32] ; Move the contents of register A to the ; location 002Fh+(R31:R32) *ROF,A ; Use the contents of the register ; pair ROE:ROF as address. ; Move the contents of that ; address to register A ; Move the contents of the location at ; LABEL to register A
MOV
MOV
MOV
LABEL,A
Assembly Language Instruction Set
16-69
MOVW Move Word
Syntax Execution Options MOVW s,Rpd (s) (Rpd)
inst operands bytes 3 4 4 5 cycles 12 13 15 20 opcode operation 98 88 A8 F4 E8 (Rps-1:Rps) (Rpd-1:Rpd) iop16 (Rpd-1:Rpd) (B) + iop16 (Rpd-1:Rpd) (Rp-1:Rp)+iop8 (Rpd-1:Rpd) MOVW Rps,Rpd MOVW #iop16,Rpd MOVW #iop16[B],Rpd MOVW #off8[Rps],Rpd
Status Bits Affected
C N Z V
0 Set on MSbyte moved Set on MSbyte moved 0
Description
MOVW moves a 2-byte value to the register pair indicated by the destination register number. (Note that Rpd should be greater than 0.) The destination points to the LSbyte of the destination register pair. The source can be a 16-bit constant, another register pair, or an indexed address. For the indexed address, the source must be of the form "#ADDR[B]" where ADDR is a 16-bit constant or address. This 16-bit value is added (via 16-bit addition) to the contents of register B, and the result is placed in the destination register pair. This stores an indexed address into a register pair for use later in indirect addressing mode. This is not to be confused with the program flow addressing instruction *LABEL[B].
Examples
LABEL
MOVW MOVW
#1234h,R3 R5,R3
; 1234h (R2:R3) ; (R4:R5) (R2:R3) ; R5,R3 = LSbyte ; TAB + (B) (R2:R3) ; R3 = LSbyte ; 127 + (R199:R200) ; (R33:R34)
MOVW #TAB[B],R3
MOVW #127[R200],R34
MOVW #-128[R200],R34 ; (R199:R200) - 128 ; (R33:R34)
16-70
Multiply
MPY
Syntax Execution Options
MPY s,Rn (s) x (Rn) (A:B) Result always stored in A,B; A = MSbyte inst MPY MPY MPY MPY MPY MPY MPY C N Z V operands B,A Rs,A Rs,B Rs,Rd #iop8,A #iop8,B #iop8,Rd bytes 1 2 2 3 2 2 3 cycles 47 46 46 48 45 45 47 opcode 6C 1C 3C 4C 2C 5C 7C operation (A) X (B) (A:B) (A) X (Rs) (A:B) (B) X (Rs) (A:B) (Rd) X (Rs) (A:B) (A) X iop8 (A:B) (B) X iop8 (A:B) (Rd) X iop8 (A:B)
Status Bits Affected
0 Set on MSbyte of results (register A) Set on MSbyte of results (register A) 0
Description
MPY performs an 8-bit multiply for a general source and destination operand. The 16-bit result is placed in the A, B register pair with the most significant byte in A. Multiplying by a power of two is a convenient means of performing doublebyte shifts.
Examples
If a double-byte shift is three places or less, then it can be faster to use RLC or RRC instead of multiply. To shift a single byte, it is almost always faster to use RLC or RRC.
MPY R3,A ; Multiply (R3) with (A), store ; result in A, B register pair ; Multiply 32h with (B), store ; in register pair A, B ; Multiply (R12) with (R7) and ; store in A, B register pair
LABEL
MPY #032h,B
MPY
R12,R7
Assembly Language Instruction Set
16-71
NOP No Operation
Syntax Execution Options NOP (PC) + 1 (PC) inst NOP None NOP is useful as a pad instruction during program development to "patch out" unwanted or erroneous instructions or to leave room for code changes during development. It is also useful in software timing loops. NOP uses seven clock cycles.
LABEL NOP ; Use 7 cycles of time
operands none
bytes 1
cycles 7
opcode FF
Status Bits Affected Description
Example
16-72
Logical OR
OR
Syntax Execution Options
OR s,Rd (s) OR (Rd) (Rd) inst OR OR OR OR OR OR OR OR OR OR C N Z V operands A,Pd B,A B,Pd Rs,A Rs,B Rs,Rd #iop8,A #iop8,B #iop8,Rd #iop8,Pd 0 Set on result Set on result 0 bytes 2 1 2 2 2 3 2 2 3 3 cycles 9 8 9 7 7 9 6 6 8 10 opcode 84 64 94 14 34 44 24 54 74 A4 operation (A) OR (Pd) (Pd) (B) OR (A) (A) (B) OR (Pd) (Pd) (Rs) OR (A) (A) (Rs) OR (B) (B) (Rs) OR (Rd) (Rd) iop8 OR (A) (A) iop8 OR (B) (B) iop8 OR (Rd) (Rd) iop8 OR (Pd) (Pd)
Status Bits Affected
Description
OR logically ORs the two operands. The OR operation is used to set bits in a register. If a register needs a 1 in the destination, then a 1 is placed in the corresponding bit location in the source operand.
LABEL OR A,R12 ; OR register A with R12, ; store in R12 ; Set lower nibble of A to 1s, ; leave upper nibble unchanged ; OR (R8) with (B), store in B
Examples
OR
#00Fh,A
OR
R8,B
Assembly Language Instruction Set
16-73
POP Pop From Stack
Syntax Execution POP d ((SP)) (d) (SP) - 1 (SP) (Move value then decrement SP) inst operands
POP POP POP POP A B Rd ST
Options
bytes cycles
1 1 2 1 9 9 7 8
opcode operation
B9 C9 D9 FC ((SP)) (A); (SP) - 1 (SP) ((SP)) (B); (SP) - 1 (SP) ((SP)) (Rd); (SP) - 1 (SP) ((SP)) (ST); (SP) - 1 (SP)
Status Bits Affected
C N Z V
0 Set on value POPed Set on value POPed 0
Note: POP ST affects all status bits. Description POP pulls a value from the top of the stack. The stack can be used to save or to pass values between routines. POP ST can replace the status register with the contents on the stack. This 1-byte instruction is usually executed in conjunction with a previously performed PUSH ST instruction.
LABEL POP R32 POP ST ; Load R32 with value on top of stack ; Load status register with ; value on top of stack
Examples
16-74
Push on Stack
PUSH
Syntax Execution
PUSH s (SP) + 1 (SP) (s) ((SP)) (Increment SP then move value) inst
PUSH PUSH PUSH PUSH
Options
operand
A B Rs ST
bytes cycles opcode operation
1 1 2 1 9 9 7 8 B8 C8 D8 FB (SP) + 1 (SP); (A) ((SP)) (SP) + 1 (SP); (B) ((SP)) (SP) + 1 (SP); (Rs) ((SP)) (SP) + 1 (SP); (ST) ((SP))
Status Bits Affected
C N Z V
0 Set on value PUSHed Set on value PUSHed 0
Note: Status bits are unchanged for PUSH ST. Description PUSH places a value on the top of the stack. The stack is used to save or pass values between routines. The status register can be pushed on the stack with the statement PUSH ST. This 1-byte instruction is usually executed in conjunction with a subsequently performed POP ST instruction. Examples
LABEL PUSH PUSH A ST ; Move (A) to top of stack ; Move status to top of stack
Assembly Language Instruction Set
16-75
RL
Rotate Left
Syntax Execution Options
RL Rd Bit(n) Bit(n+1) Bit(7) Bit(0) and carry inst RL RL RL C N Z V operands A B Rd bytes 1 1 2 cycles 8 8 6 opcode BE CE DE
Status Bits Affected
Set to bit 7 of the original operand Set on result Set on result 0
Description
RL circularly shifts the destination contents one bit to the left. The MSB is shifted into the LSB; the carry bit is also set to the original MSB value.
MSB C 7 6 5 4 3 2 1 LSB 0
For example, if register B contains the value 93h, then RL changes the contents of B to 27h and sets the carry bit. Examples
LABEL RL R102 RL RL A B ; Circularly rotate reg. R102 left one bit ; Circularly rotate reg. A left one bit ; Circularly rotate reg. B left one bit
16-76
Rotate Left Through Carry
RLC
Syntax Execution
RLC Rd Bit(n) Bit(n+1) Carry Bit(0) Bit(7) Carry inst RLC RLC RLC C N Z V operands A B Rd bytes 1 1 2 cycles 8 8 6 opcode BF CF DF
Options
Status Bits Affected
Set to bit 7 of the original operand Set on result Set on result 0
Description
RLC circularly shifts the destination contents one bit to the left and through the carry. The original carry bit contents shift into the LSB, and the original MSB shifts into the carry bit.
MSB C 7 6 5 4 3 2 1 LSB 0
For example, if register B contains the value 93h and the carry bit is a zero, then the RLC instruction changes the operand value to 26h and the carry bit to one. Rotating left effectively multiplies the value by 2. Using multiple rotations, any power of 2 (2, 4, 8, 16,...) can be achieved. This type of multiplication can be faster than the MPY (multiply) instruction. This instruction is also useful in rotations where a value is contained in more than one byte (such as an address) or in multiplying a large multibyte number by 2. Take care to ensure that the carry bit is at the proper value. The SETC or CLRC instructions can be used to set up the correct value. Examples
LABEL RLC R72 ; Circular rotate reg. R72 left one bit ; with MSbit --> Carry bit ; Circular rotate reg. A left one bit ; with MSbit --> Carry bit ; Circular rotate reg. B left one bit ; with MSbit --> Carry bit
RLC
A
RLC
B
Assembly Language Instruction Set
16-77
RR Rotate Right
Syntax Execution Options RR Rd Bit(n+1) Bit(n) Bit(0) Bit (7) and carry inst RR RR RR C N Z V operands A B Rd bytes 1 1 2 cycles 8 8 6 opcode BC CC DC
Status Bits Affected
Set to bit 0 of the original value Set on result Set on result 0
Description
RR circularly shifts the destination contents one bit to the right. The LSB is shifted into the MSB, and the carry bit is also set to the original LSB value.
MSB C 7 6 5 4 3 2 1 LSB 0
For example, if register B contains the value 93h, then the RR B instruction changes the contents of B to C9h and sets the carry status bit. Examples
LABEL RR RR RR A B R56 ; Circular rotate right one bit the A reg. ; with LSbit --> Carry bit ; Circular rotate right one bit the B reg. ; with LSbit --> Carry bit ; Circular rotate right one bit register ; R56 with LSbit --> Carry bit
16-78
Rotate Right Through Carry
RRC
Syntax Execution
RRC Rd Bit(n+1) Bit(n) Carry Bit(7) Bit(0) Carry inst RRC RRC RRC C N Z V operands A B Rd bytes 1 1 2 cycles 8 8 6 opcode BD CD DD
Options
Status Bits Affected
Set to bit 0 of the original value Set on result Set on result 0
Description
RRC circularly shifts the destination contents one bit to the right through the carry. The carry bit contents shift into the MSB, and the LSB shifts into the carry bit.
MSB C 7 6 5 4 3 2 1 LSB 0
For example, if register B contains the value 93h and the carry bit is zero, then RRC changes the operand value to 49h and sets the carry bit. When the carry bit is 0, this instruction effectively divides the value by 2. A value of 80h becomes 40h. Repetitive use of this instruction can divide the value by any power of 2. Care must be taken to ensure the correct value in the carry bit. Examples
LABEL RRC R32 RRC A RRC B ; Rotate right R32; LSbit --> Carry and ; Carry bit to R32 MSbit ; Rotate right reg, A; LSbit --> Carry ; Carry bit to reg. A MSbit ; Rotate right reg. B; LSbit --> Carry ; Carry bit to reg. B MSbit
Assembly Language Instruction Set
16-79
RTI
Return From Interrupt
Syntax Execution
RTI ((SP)) (PC LSbyte) (SP) - 1 (SP) ((SP)) (PC MSbyte) (SP) - 1 (SP) ((SP)) (ST) (SP) - 1 (SP) inst RTI operands none bytes 1 cycles 12 opcode FA
Options
Status Bits Affected Description
Status register is loaded from the stack RTI is typically the last instruction executed in an interrupt service routine. RTI restores the status register to the state it was in immediately before the interrupt occurred and branches back to the program at the instruction boundary where the interrupt occurred. In an interrupt routine, there must be an equal number of POPs and PUSHs so that the stack pointer is pointing to the correct return address and not some other data.
LABEL RTI ; Return to main program from interrupt routine
Example
16-80
Return From Subroutine
RTS
Syntax Execution
RTS ((SP)) (PC LSbyte) (SP) - 1 (SP) ((SP)) (PC MSbyte) (SP) - 1 (SP) inst RTS None RTS is typically the last instruction executed in a subroutine. RTS branches to the location immediately following the subroutine call instruction. In the called subroutine, there must be an equal number of POPs and PUSHes so that the stack pointer is pointing to the return address and not some other data.
LABEL RTS ; Return to main program from subroutine
Options
operands none
bytes 1
cycles 9
opcode F9
Status Bits Affected Description
Example
Assembly Language Instruction Set
16-81
SBB Subtract With Borrow
Syntax Execution Options SBB s,Rd (Rd) - (s) - 1 + (C) (Rd) inst SBB SBB SBB SBB SBB SBB SBB C N Z V operands B,A Rs,A Rs,B Rs,Rd #iop8,A #iop8,B #iop8,Rd bytes cycles opcode operation 1 8 6B (A) - (B) - 1 + (C) (A) 2 7 1B (A) - (Rs) - 1 + (C) (A) 2 7 3B (B) - (Rs) - 1 + (C) (B) 3 9 4B (Rd) - (Rs) - 1 + (C) (Rd) 2 6 2B (A) - iop8 - 1 + (C) (A) 2 6 5B (B) - iop8 - 1 + (C) (B) 3 8 7B (Rd) - iop8 - 1 + (C) (Rd)
Status Bits Affected
Set to 1 if no borrow; 0 otherwise Set on result Set on result ((C XOR N) AND (Source[Bit 7] XOR Destination[Bit 7]))
Description
SBB performs multibyte 2s-complement subtraction. An SBB instruction with an immediate operand of zero value is equivalent to a conditional decrement of the destination operand, depending on the carry value. If (s) = 0 and (C) = 0, then (Rd) is decremented. A borrow operation occurs if the result is negative. In this case, the carry bit is set to 0. The carry bit acts as the no-borrow bit.
LABEL SBB #023h,B ; Subtract 23h from (B), sub; tract 1, add the carry bit ; and store in register B ; R20:R21 and R2:R3 contain 1 ; bit numbers. SUB subtracts ; the LSbyte, and the SBB will ; use the carry as a borrow ; during the subtract of ; the MSbyte.
Examples
SUB SBB
R3,R21 R2,R20
16-82
Set Bit to 0
SBIT0
Syntax Execution Options
SBIT0 name 0 inst operands bytes cycles opcode operation SBIT0 Rname 3 8 73 0 Register bits SBIT0 Pname 3 10 A3 0 Peripheral bits C N Z V 0 Set on result Set on result 0
Status Bits Affected
Description
SBIT0 is an assembler-constructed instruction that conveniently clears the value of the named bit without having to specify a register or mask. This enhances the readability of the program. This instruction assembles to the instructions AND #iop8,Rd or AND #iop8,Pd. The name for the bit is defined by the .DBIT assembler directive.
INT1ENA .DBIT 7,P01C ; The interrupt 1 enable ; bit is now named INT1ENA ; Bit 4 of register 33 ; is now named TEST ; Clears the value of the ; TEST bit ; Disables interrupt 1
Example
TEST
.DBIT 4,R33
LABEL
SBIT0 TEST
SBIT0 INT1ENA
Assembly Language Instruction Set
16-83
SBIT1
Syntax
Set Bit to 1
SBIT1 name 1 inst SBIT1 SBIT1 C N Z V operands Rname Pname bytes 3 3 cycles opcode operation 8 74 1 Register bits 10 A4 1 Peripheral bits
Execution Option
Status Bits Affected
0 Set on result Set on result 0
Description
SBIT1 is an assembler-constructed instruction that conveniently sets the value of the named bit without having to specify a register or mask. This enhances the readability of the program. This instruction assembles to the instructions OR #iop8,Rd or OR #iop8,Pd. The name for the bit is defined by the .DBIT assembler directive.
INT1ENA .DBIT 7,P01C ; The interrupt 1 enable bit ; is now named INT1ENA ; Bit 4 of register 33 is now ; named TEST ; Sets the value of the TEST ; bit to 1 ; Enables interrupt 1
Examples
TEST
.DBIT 4,R33
LABEL
SBIT1 TEST
SBIT1 INT1ENA
16-84
Set Carry
SETC
Syntax Execution Options
SETC 1 (C) inst SETC C N Z V 1 0 1 0 operands none bytes 1 cycles 7 opcode F8
Status Bits Affected
Description Example
SETC sets the carry flag. This instruction can be used before an arithmetic or rotate instruction. The IE1 and IE2 enable bits are not affected.
LABEL SETC ; Set the carry bit in the status register ; Status register = 0Axh ; Where X (lower nibble) is don't care
Assembly Language Instruction Set
16-85
STSP Store Stack Pointer
Syntax Execution Options STSP (SP) (B) inst STSP None STSP copies the contents of the stack pointer to register B. This instruction can test the stack size. The indexed addressing mode can reference operands on the stack after executing this instruction.
LABEL STSP ; Copy the contents of stack pointer ; to register B
operands none
bytes 1
cycles 8
opcode FE
Status Bits Affected Description
Example
16-86
Subtract
SUB
Syntax Execution Options
SUB s,Rd (Rd) - (s) (Rd) inst SUB SUB SUB SUB SUB SUB SUB C N Z V operands B,A Rs,A Rs,B Rs,Rd #iop8,A #iop8,B #iop8,Rd bytes 1 2 2 3 2 2 3 cycles 8 7 7 9 6 6 8 opcode 6A 1A 3A 4A 2A 5A 7A operation (A) - (B) (A) (A) - (Rs) (A) (B) - (Rs) (B) (Rd) - (Rs) (Rd) (A) - iop8 (A) (B) - iop8 (B) (Rd) - iop8 (Rd)
Status Bits Affected
Set to 1 if no borrow, otherwise set to 0 Set on result Set on result ((C XOR N) AND (Source[Bit 7] XOR Destination[Bit 7]))
Description Examples
SUB performs 2s-complement subtraction. The carry bit is set to 0 if a borrow is required. The carry bit acts as a no-borrow bit in this case.
LABEL SUB R19,B ; (B) minus (R19) is ; stored in B ; (A) minus 076h is stored ; in A ; (R9) minus (R4) is stored ; in R9
SUB
#076h,A
SUB
R4,R9
Assembly Language Instruction Set
16-87
SWAP Swap Nibbles
Syntax Execution Options SWAP Rd Bits (7,6,5,4 / 3,2,1,0) Bits (3,2,1,0 / 7,6,5,4) inst SWAP SWAP SWAP C N Z V operands A B Rd bytes 1 1 2 cycles 11 11 9 opcode B7 C7 D7
Status Bits Affected
Set to bit 4 of original register or bit 0 of result register Set on results Set on results 0
Description
SWAP exchanges the first four bits with the second four bits. This instruction is equivalent to four consecutive RL (rotate left) instructions. It is especially useful for packed BCD operations.
LABEL SWAP R45 SWAP SWAP A B ; Switch low and high nibbles of R45 ; Switch low and high nibbles of A ; Switch low and high nibbles of B
Examples
16-88
Trap to Subroutine
TRAP
Syntax Execution
TRAP #n where n = the trap number = 0 thru 15 (SP) + 1 (PC MSbyte) (SP) + 1 (PC LSbyte) (Entry vector) (SP) ((SP)) (SP) ((SP)) (PC) entry-vector MSbyte LSbyte 7FDEh 7FDFh 7FDCh 7FDDh 7FDAh 7FDBh 7FD8h 7FD9h 7FD6h 7FD7h 7FD4h 7FD5h 7FD2h 7FD3h 7FD0h 7FD1h 7FCEh 7FCFh 7FCCh 7FCDh 7FCAh 7FCBh 7FC8h 7FC9h 7FC6h 7FC7h 7FC4h 7FC5h 7FC2h 7FC3h 7FC0h 7FC1h
Options inst TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP TRAP Status Bits Affected Description None operands #0 #1 #2 #3 #4 #5 #6 #7 #8 #9 #10 #11 #12 #13 #14 #15 bytes 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 cycles 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 opcode EF EE ED EC EB EA E9 E8 E7 E6 E5 E4 E3 E2 E1 E0
Trap is a 1-byte subroutine call. The operand <#n> is a trap number that identifies a location in the trap vector table (addresses 07FC0h to 07FDFh in memory). The contents of the 2-byte vector location form a 16-bit trap vector to which a subroutine call is performed. When you invoke the same routine more than once, TRAP is a more efficient instruction than CALL because fewer bytes are needed. The subroutine addresses are stored like all other addresses in memory, with the least significant byte in the higher-addressed location, as indicated above.
LABEL TRAP #0 ; Execute subroutine at TRAPONE ; Define section starting ; at 7FC0h ; Define TRAPS 15 AND 14 ; subroutine entry points
Examples
.sect trap,07FC0h
.word TRAP15,TRAP14
Assembly Language Instruction Set
16-89
TST
Test, Set Flags From Register
Syntax Execution Options
TST {A | B} C,N,Z,V bits affected inst TST TST C N Z V operands A B bytes 1 1 cycles 9 10 opcode B0 C6
Status Bits Affected
0 Set or cleared based on operand Set or cleared based on operand 0
Description Examples
TST sets the status bits according to the value in register A or B. This allows conditional jumps on the value in the register.
LABEL TST A ; Check for zero and negative ; conditions in register A ; Check for zero and negative ; conditions in register B
TST
B
16-90
Exchange With Register B
XCHB
Syntax Execution Options
XCHB Rd (B) (Rd) inst XCHB XCHB XCHB C N Z V operands A B Rd bytes 1 1 2 cycles 10 10 8 opcode B6 C6 D6 operation (A) (B) (B) (B) (TST B) (Rd) (B)
Status Bits Affected
0 Set on original contents of B Set on original contents of B 0
Description
XCHB exchanges a register with register B without going through an intermediate location. The XCHB instruction with register B as the operand is equivalent to the TST B instruction.
LABEL XCHB A ; Exchange register B with ; register A ; Exchange register B with R3
Examples
XCHB
R3
Assembly Language Instruction Set
16-91
XOR Exclusive OR
Syntax Execution Options XOR s,d (s) XOR (d) (d) inst XOR XOR XOR XOR XOR XOR XOR XOR XOR XOR C N Z V operands A,Pd B,A B,Pd Rs,A Rs,B Rs,Rd #iop8,A #iop8,B #iop8,Rd #iop8,Pd bytes 2 1 2 2 2 3 2 2 3 3 cycles 9 8 9 7 7 9 6 6 8 10 opcode 85 65 95 15 35 45 25 55 75 A5 operation (A) XOR (Pd) (Pd) (B) XOR (A) (A) (B) XOR (Pd) (Pd) (Rs) XOR (A) (A) (Rs) XOR (B) (B) (Rs) XOR (Rd) (Rd) iop8 XOR (A) (A) iop8 XOR (B) (B) iop8 XOR (Rd) (Rd) iop8 XOR (Pd) (Pd)
Status Bits Affected
0 Set on result Set on result 0
Description
XOR performs a bit-wise exclusive OR operation on the operands. The XOR instruction can complement bits in the destination operand. This operation can also toggle a bit in a register. If the bit value in the destination must be the opposite from what it currently is, then the source should contain a 1 in that bit location.
LABEL XOR R98,R125 ; XOR (R98) with (R125), ; store in R125 ; Toggle bit 0 in R20 ; XOR (B) with (A), store ; in register A
Examples
XOR XOR
#01,R20 B,A
16-92
Running Title--Attribute Reference
Chapter 17
Development Support
This chapter discusses the key features of the TMS370 development tools. These tools are currently available for PC-DOS or MS-DOS (version 3.0 and up) systems. Some tools are also available for UNIX systems. For a detailed description of system components, refer to the documents listed in the preface. The topics in this chapter include:
Topic
Page
17.1 TMS370 Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2 17.2 The Assembler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4 17.3 The Linker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-5 17.4 Additional Software Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-7 17.5 The Optimizing C Compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-8 17.6 The C Source Debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-9 17.7 The XDS/22 System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-12 17.8 The CDT370 (Compact Development Tool) . . . . . . . . . . . . . . . . . . . . 17-18 17.9 The Design Kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-20 17.10 The Starter Kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-24 17.11 The Microcontroller Programmer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-25 17.12 Reprogrammable EPROM and OTP Devices . . . . . . . . . . . . . . . . . . . 17-26
Chapter Title--Attribute Reference
17-1
TMS370 Development Tools
17.1 TMS370 Development Tools
Texas Instruments provides extensive development support for the TMS370 family. This support includes:
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Assembly language tools, such as the assembler and linker, that convert assembly language into executable object code Additional software-support tools, such as an archiver and hex conversion utility An optimizing C compiler that supports high-level language programming and is a full implementation of the standard ANSI C language A C source debugger--an advanced software interface to the TMS370 XDS/22 emulator, CDT370, and design kit Development support tools that offer full-speed emulation for testing your object files:
J J J J
XDS/22 (extended development support system) that provides realtime breakpoint, trace, and timing functions to facilitate hardware and software integration during system development CDT370 (compact development tool) that supports realtime in-circuit emulation of the TMS370 family Design kit for evaluation of the TMS370 family Starter kit for programming and software simulation of the TMS370 family
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A software simulator TMS370 microcontroller programmer to program the programmable memory of any TMS370 device EPROM devices for prototype and small production runs
These development tools are designed to work with IBM-compatible PCs. Additionally, the TMS370C6xx and TMS370C7xx devices prototype and emulate masked-ROM parts and also act as a medium for submitting the program to TI for mask-ROM production.
17-2
TMS370 Development Tools
Figure 17-1 shows the software development flow. The shaded portion highlights the most common development path; the other portions are optional.
Figure 17-1. Software Development Flow
C source files Macro source files
C compiler
Archiver
Assembler source
Macro library Assembler
Archiver
COFF object files
Library-build utility
Library of object files
Runtimesupport library Linker Debugging tools Executable COFF file
Hex conversion utility
Emulator
EPROM programmer
Absolute lister
Cross-reference lister
TMS370
The emulator can be the XDS/22 or the CDT370. The design kit contains a simulator and EPROM/EEPROM programmer.
Development Support
17-3
The Assembler
17.2 The Assembler
The TMS370 assembler translates assembly language source files into machine language object files. Source files can contain instructions, assembler directives, and macro directives. The assembler directives control various aspects of the assembly process, such as the source listing format, symbol definition, conditional assembly blocks, macro library definition, and the way the machine code is placed into the TMS370 memory space. The format of the object files created by the assembler and linker is called common object file format (COFF). COFF encourages and facilitates modular programming. It allows the assembler to maintain a section program counter (SPC) for each section of object code generated. The SPC defines the virtual program-memory addresses assigned to the associated object code. The assembler uses the SPC while it builds the symbol table. The symbol tables contained in the COFF object files allow the C source debugger to provide you with symbolic debugging. The debugger also provides for direct referencing of any assembler label and arithmetic expressions involving assembler labels when the labels are part of the downloaded COFF object file. The TMS370 microcontroller programmer also uses COFF object files to form a PC memory image of the data loaded for programming.
17-4
The Linker
17.3 The Linker
The TMS370 linker creates executable modules by combining COFF object files. The concept of user-definable COFF sections is basic to the linker operation. The linker accepts several types of files as input:
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Relocatable COFF object files produced by the TMS370 assembler Command files Archive object libraries Output modules created by a previous linker run (referred to as partially linked files)
As the linker combines object files, it performs the following tasks: Allocates sections into the target system's configured memory Relocates symbols and sections to assign them to final addresses Resolves undefined external references between input files
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The linker supports a command language similar to C that controls memory configuration, section definition, and address binding. The language supports expression assignment and evaluation. It also provides two powerful directives, MEMORY and SECTIONS, that allow you to: Define a memory model that conforms to target system memory Combine object file sections Allocate sections into specific areas of memory Define overlayed memory structures Define or redefine global symbols at link time
Figure 17-2 shows the operation of the linker on two source code files. Each file has been assembled and contains four default sections and one named section. The various sections are arranged in the order dictated either by the linker's default method or by a user-supplied control file. The executable object module shows the combined sections, and the memory map indicates the location of the sections in memory.
Development Support
17-5
The Linker
Figure 17-2. Linker Output Generation
file1.obj .reg .bss .text .data Init (named section) Executable Object Module file1 (.reg) file2 (.reg) file1 (.bss) file2 (.bss) file1 (.text) file2 (.text) file1 (.data) file2.obj .reg .bss .text file2 (.data) Init Tables 02h Programmable registers (.reg)
Memory Map
Space for variables (.bss) 100h 2000h Executable code (.text) 3000h 7000h Initialized data (.data)
Init Tables
17-6
E EEEEEEEEEEEEEEEE EEEEE EEEEEEEEEEEEEEEE E E EEEEE EEEEEEEEEEEEEEEE E EEEEE EEEEEEEEEEEEEEEE EEEEEEEEEEEE
8000h .data Tables (named section)
Additional Software Support
17.4 Additional Software Support
Two additional software utilities are included with the TMS370 assembly language tools:
17.4.1 The Archiver
An archiver A hex conversion utility
The archiver provides file management by allowing a group of files to be collected into a single library. For example, macros can be collected by the archiver, then fetched by the assembler as directed by the source file. In addition, object modules can be collected into a library for convenient access by the linker. While not necessary for program development, the archiver can provide valuable organization in the building of the executable COFF object file.
17.4.2 The Hex Conversion Utility
The hex conversion utility converts a COFF object file into TI-tagged, ASCIIhex, Intel, Motorola-S, or Tektronix object format. The converted file can be downloaded to an EPROM programmer.
Development Support
17-7
The Optimizing C Compiler
17.5 The Optimizing C Compiler
The TMS370 optimizing C compiler translates the widely used ANSI C language directly into highly optimized assembly language, enhancing productivity by enabling you to program in C. C code is easier to prototype, debug, and benchmark than assembly language. Also, it produces information that is used by the debugger, which allows source-level debugging in both C and assembly. This shortens the development cycle for TMS370 applications. Key features of the C compiler include:
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Conformance with the ANSI C specification Highly efficient code--the C compiler incorporates state-of-the-art generic and target-specific optimizations ANSI standard runtime-support library A C shell program that facilitates one-step translation from C source to executable code ROM-able, relocatable, and re-entrant code (where declared) A source interlist utility that can interlist your original C source statements into assembly language output of the compiler A utility for building object libraries from source libraries Fast compilation to increase productivity
The following is a partial list of key optimizations used by the compiler: Performs control-flow graph simplification Allocates variables to registers Performs loop rotation Performs loop unrolling Performs loop optimizations expressions Eliminates dead code Simplifies expressions and statements Performs local copy/constant propagations Removes dead assignments Eliminates local common expressions Eliminates global common expressions Eliminates global dead assignments
17-8
The C Source Debugger
17.6 The C Source Debugger
The C source debugger is an advanced software interface that runs on IBMcompatible PCs and helps you to develop, test, and refine TMS370 C programs (compiled with the TMS370 optimizing ANSI C compiler) and assembly language programs. The debugger is the interface to the TMS370 in-circuit XDS/22 emulator, design kit, CDT370, and software simulator. The debugger has a standard screen appearance for the supported products, allowing you to move from one tool to the next without having to learn a new interface--only the new features. The C source debugger improves productivity by enabling you to debug a program in the language it was written in. You can choose to debug your programs in C, assembly language, or both. Also, the debugger is easy to learn and use. Its friendly window-, mouse-, and menu-oriented interface reduces learning time and eliminates the need to memorize complex commands. Figure 17-3 identifies several features of the debugger display.
Figure 17-3. The Basic Debugger Display
Pulldown menus Disassembly display
Load
Break
Watch
Memory
Color
MoDe
BTT
Run=F5
Step=F8
Next=F10
C source display
DISASSEMBLY 7185 88 c_int00: MOVW #02883h,R021 7189 98 MOVW R021,R01F 718c 52 MOV #022h,B 718e fd LDSP 718f 8e CALL 7199h 7192 8e CALL main 7195 8e CALL exit 7198 fa RTI 7199 88 MOVW #0723Ah,R0F 719d 00 JMP 71BFh 719f f4 MOV 3(R0F),A 71a3 FILE: sample1.c d0 MOV A,R0D } 71a5 0007 f4 MOV 2(R0F),A 71a9 0008 d0 MOV A,R0C call(newvalue) 71ab 0009 70 INCW #4,R0F int newvalue; 71ae 0010 00 JMP 71BAh { 71b0 0011 9a MOV @R0F,A 0012 static int value = 0; 0013 0014 switch (newvalue & 3) 0015 { 0016 case 0 : str.a = newvalue 0017 case 1 : str.b = newvalue 0018 case 2 : str.c = newvalue 0019 case 3 : xcall(newvalue); 0020 } 0021 COMMAND step MEMORY 0000 000c 0018 0024 0030 87 28 00 40 00
CALLS 2: call() 1: main() WATCH 1:str.a 0 2:F0 1.000000e 3:color GREEN
Function call traceback
CPU PC A B ST SP
7185 87 00 40 22
Natural-format data displays
DISP: astr[7] a 123 b 555 c 75 DISP: astr[7].f4 f1 3 [0] 0 f2 6 [1] 9 f3 0x0f [2] 7 f4 [...] [3] 54 ; break; [4] 3 + 1; return [5] 3 * 2; [6] 4 break; [7] 123 [8] 4 [9] 789
Interactive command entry and history window
>>>
00 81 00 00 00
cb 72 00 00 00
01 44 00 00 00
00 00 00 00 00
00 00 00 00 00
28 00 28 00 00
e5 00 87 00 00
00 00 28 00 00
00 00 8f 00 00
00 00 00 00 00
00 00 70 00 00
Scrolling data displays with on-screen, interactive editing
Development Support
17-9
The C Source Debugger
Key features of the C source debugger include:
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Multilevel debugging. The debugger allows you to debug both C and assembly language code. If you're debugging a C program, you can choose to view just the C source, the disassembly of the object code created from the C source, or both. You can also use the debugger as an assembly language debugger. Fully configurable, state-of-the-art, window-oriented interface. The C source debugger separates code, data, and commands into manageable portions. Use any of the default displays, or select the windows you want to display, size them, and move them where you want them. The debugger display is completely configurable, allowing you to create the interface that is suited for your use. Comprehensive data displays. You can easily create windows for displaying and editing the values of variables, arrays, structures, pointers-- any kind of data --in their natural format (float, int, char, enum, or pointer). You can even display entire linked lists (see Figure 17-4).
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Figure 17-4. Debugger Display
DISP: str a 123 b 0 c 75435 f1 3 f2 6 f3 0x0fa f4 [...] WATCH 1: str.a 0 2: F0 1.000000e 3: color GREEN
DISP: *str.f3 a 8327 b 666 DISP: *str.f3->f3 c 87 a 75 f1 45 b 3212 f2 27 c 782 f3 0x0f f4 [...] f1 7 f2 9 f3 0x0f f4 [...]
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On-screen editing. Change any data value displayed in any window-- just point the mouse, click, and type. Continuous update. The debugger continuously updates information on the screen, highlighting changed values. Powerful command set. The C source debugger supports a small, but powerful, command set that makes full use of C expressions. One debugger command performs actions that would require several commands in another system.
17-10
The C Source Debugger
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Flexible command entry. There are a variety of ways to enter commands. You can type commands or use a mouse, function keys, or the pulldown menus; choose the method that you like best. Variety of screen sizes. The debugger's default configuration is set up for a typical PC display, with 25 lines by 80 characters. If you use a sophisticated graphics card, you can take advantage of the debugger's additional screen sizes. A larger screen size allows you to display more information and provides you with more screen space for organizing the display-- bringing the benefits of workstation displays to your PC. All the standard features you expect in a world-class debugger. The debugger provides you with complete control over program execution with features like conditional execution and single-stepping (including singlestepping into or over function calls). You can set or clear a breakpoint with a click of the mouse or by typing commands. You can define a memory map that identifies the portions of target memory that the debugger can access. You can choose to load only the symbol table portion of an object file to work with systems that have code in ROM. The debugger can execute commands from a batch file, providing you with an easy method for entering often-used command sequences.
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Development Support
17-11
The XDS/22 System
17.7 The XDS/22 System
The XDS/22 system is a self-contained package that provides full-speed, incircuit emulation and debugging functions required for program development of the TMS370 family devices. These are key features of the XDS/22 emulation function:
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A 0.5- to 5-MHz SYSCLK full-speed in-circuit emulation of all TMS370 family members Realtime hardware breakpoint/trace/timing analysis capabilities Execution of programs from internal XDS/22 memory (64K byte) or target memory Support of both microcomputer and microprocessor modes Large trace buffer--2047 samples Full logic tracing with logic analyzer interface cable
The XDS/22 system set of boards consists of an emulator, communications board, and a breakpoint/trace/timing board. At the heart of the XDS/22 system is a special system emulator chip containing all of the peripheral modules and I/O line circuits that precisely duplicate the TMS370's logic and performance. You can use the internal XDS/22 memory to emulate on-chip ROM and/or external memory. The target cables that are necessary for using the XDS/22 are sold separately. See subsection 19.4.5, page 19-26, for ordering information. The XDS/22 is supported by a debugger, as described in Section 17.6, on page 17-9.
17-12
The XDS/22 System
17.7.1 Breakpoint, Trace, and Timing (BTT) Functions
Included with the XDS/22 emulation system is a separate board called the BTT board, which provides breakpoint, trace, and timing features. The BTT monitors the TMS370 CPU; when a preselected pattern of bus activity is detected, the BTT performs an action such as executing a hardware breakpoint or storing information in the trace buffer. The BTT supports these features:
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Full range of actions. The BTT functions allow you to set hardware breakpoints, count event occurrences, collect trace samples, jump to a BTT state, or start or stop timers. These actions occur when they are qualified--that is, when bus activity matches conditions that you have defined. Four separate states. The BTT supports four separate states, called state 0 through state 3. Each state can be associated with up to four actions. You can define actions for as many states as you need. By default, the BTT cycles through the states, beginning with state 0 and ending with the last state that you defined actions for. You can control this sequencing by jumping to another state or by using counters to loop through a sequence of states. To view information about specific states, add an action, delete an action, or access global settings, use the BTT Setup dialog box (see Figure 17-5).
Figure 17-5. BTT Setup Dialog Box
Current state
BTT Setup State 0
<>

Descriptions of actions defined for the current state
Action: BP/event addr = 7050 data = IGNORE cycles ALL extern IGNORE
Action: Trace addr = 7000 ...7FFF data = IGNORE cycles ALL extern IGNORE
State Mode
( ) Address only (*) address and data
Trace Mode
(*) Normal ( ) TRIX Event count [1 .......... ]

Development Support
17-13
The XDS/22 System
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Flexible qualification for actions. You can qualify actions according to address or data values (either singly or in relation to ranges) and to the memory-cycle type. You can combine these conditions; for example, you could qualify an action whenever a certain data value is accessed during an instruction acquisition cycle. You can define conditions or qualify actions by using a dialog box (refer to Figure 17-6).
Figure 17-6. Dialog Box for Defining Conditions
BP/Event action
Address qualifiers
(*)One point
Jump to [N/A] ( )In range ( )Outside range
( )Two points
addr1=[0x0000 ................................................................. ] addr2=[N/A ] mask [0x0000 ......... ]
Data qualifiers
(*)One point ( )Two points ( )In range ( )Outside range
data1=[0x00 .................................................................... ] data2=[N/A ] mask [0x00 ............ ] extern [0x00 ...................... ] mask [0x00 ....... ] Cycle [X] MR [X] MW [X] IAQ <>
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Informative trace reporting. The BTT can store up to 2047 trace samples in the trace buffer. You can display the trace samples and associated information by opening the Inspect window (see Figure 17-7).
Figure 17-7. Example of the Inspect Window
Inspect INDX ST 0000 0 0001 0 0002 0 0003 0L 0004 0 0005 0
Trace buffer
Point & range timer statistics
h m s ms 0:00:00.000 0:00:00.000 0:00:00.000 0:00:00.000 0:00:00.000 0:00:00.000
us 000 000 001 002 002 002
ns 400 800 200 200 600 800
EXTERNAL CYCLE 11111111 IAQ 11111111 MR 11111111 MR 11111111 IAQ 11111111 MR 11111111 MR
ADDR 7003 7004 7005 7000 7001 0007
DATA 8C 70 00 42 07 00
REVERSE ASM BR 7000h
MOV
R07,R08
T1 0:00:00.000 000 000
AVG1 0:00:00.000 000 000
T2 0:00:00.000 000 000
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External signal access. The BTT has eight external probes that can be connected to eight signals. You can qualify actions by looking for a particular pattern of activity on these probes. Additionally, the trace buffer reports the values that were on the signals when each trace sample was collected.
17-14
The XDS/22 System
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Complete timing analysis. The BTT supports two timers that you can start and stop on a variety of conditions. The BTT reports the total time for each of these timers; it also reports the average for one of the timers. Additionally, the BTT collects timing information that relates specifically to the samples in the trace buffer. External filing. Once you have defined a complex BTT setup, you may want to reuse the setup. The BTT allows you to save the setup to a file and then load it again for a later session. You can also save the contents of the trace buffer to a file for later use or to compare to another trace collection.
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Development Support
17-15
The XDS/22 System
17.7.2 XDS System Configuration Requirements
A functional XDS system configuration consists of the XDS system and the following user-supplied components:
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IBM-compatible PC, a serial communication port, and a 3-1/2-inch highdensity disk drive Windows version 3.1 or later Monitor (preferably color, to better highlight field and value changes)
Figure 17-8. Typical XDS System Configuration
PC XDS
Target system
17-16
The XDS/22 System
17.7.3 XDS System Operating Considerations
The emulation hardware of the XDS systems (XDS/22) generally exhibits the same characteristics as the actual TMS370 devices. There are, however, a few subtle differences that you should be aware of when building a prototype circuit for use with the XDS system.
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Mode control pin. To allow an XDS system to function without being attached to a target system, a 20-k pulldown resistor is connected to the mode control line in the XDS unit. This increases the minimum input current needed to drive this line high (II) from 100 A to 300 A. If you are using a pull-up resistor to put the device in the microprocessor mode, then its value should be no greater than 1 k. Reset. The XDS systems add an analog switch and a 51-k pull-up resistor to the reset line. This increases the current necessary to pull this line to a logic low from 10 A to 100 A. Clock in. The XDS systems cannot drive a crystal located on the target system. Therefore, either the crystal must be moved to socket Y1 of the emulator board, or an external clock signal must be connected to the XTAL2/CLKIN pin. The external clock signal must meet the VIH specifications for the XTAL2/CLKIN described in Chapter 18, Electrical Specifications and Timings.
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17.7.4 XDS Target Connectors
For additional or replacement XDS target connectors, contact the TI factory repair department.
Development Support
17-17
The CDT370 (Compact Development Tool)
17.8 The CDT370 (Compact Development Tool)
The CDT370 supports real-time in-circuit emulation of most of the TMS370 family of devices. It offers a low-cost, highly efficient route to TMS370 family development of software and hardware with the target system. The CDT370 contains a single board, called an emulator, which can be plugged into the expansion chassis of any IBM-compatible PC, or connected through the RS-232 serial communication link. Under Windows '95, it must be connected to an RS-232 serial communication link. Attached to the emulator is a target cable with the same pinout as the system's circuit board; the cable uses the same socket that would normally hold the TMS370 microcontroller. The CDT370 uses a debugger interface that is similar to that of the XDS/22 systems. With the CDT370, you can:
17-18
Program the EEPROM and EPROM contained within the TMS370 devices Inspect and modify memory locations Upload/download program and data memory Execute programs and software routines Use a large trace buffer with 2,048 samples Single-step executable instructions Use software breakpoints to halt program execution at selected addresses
The CDT package is shown in Figure 17-9, on page 17-19, and comes complete with: A CDT370 emulator board An assembler and linker The C source debugger
If the CDT is connected externally with an RS-232 cable, the following requirements must be supplied by the user: A 5 V, 3 A power supply A 9-pin RS-232 cable
The CDT370 (Compact Development Tool)
The cables that you need to use the CDT370 are sold separately. See subsection 19.4.6, page 19-26, for ordering information.
Figure 17-9. CDT370 Configuration
CDT370 includes assembler, linker, and debugger software
Plugs into any PCcompatible computer
Target cable CDT370 board
Target system
17.8.1 The CDT370 PACT (Compact Development Tool PACT)
The CDT370 PACT supports real-time in-circuit emulation for the 'x32, 'x36, and 'x9x family devices. The CDT370 PACT offers the same features and functionality as the CDT370.
17.8.2 The CDT370 Timer (Compact Development Tool Timer)
The CDT370 timer supports real-time in-circuit emulation for the 'x6x, 'x7x, and 'xBx family devices. The CDT370 timer offers the same features and functionality as the CDT370, but with the addition of a logic analyzer interface.
Development Support
17-19
The Design Kit
17.9 The Design Kit
The TMS370 design kit is a low-cost evaluation tool that lets you analyze the hardware and software capabilities of the TMS370 family by actually using the TMS370 devices. The kit consists of a TMS370 application board, assembler, linker, and debugger software. The design kit helps you quickly assess the feasibility of using a member of the TMS370 family for your applications. However, it can only be used to evaluate the TMS370Cx0x, TMS370Cx1x, and TMS370Cx5x (can evaluate neither TMS370Cx58 nor TMS370Cx59) devices. See subsection 19.4.2, on page 19-25, for ordering information. The design kit package allows you to:
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Upload and download code Access any register or memory location Read and modify memory locations Execute programs and software routines Single-step executable instructions Use software breakpoints to halt program execution at selected addresses Program the EEPROM and EPROM contained within the following device families: TMS370Cx0x, TMS370Cx1x, and TMS370Cx5x (except TMS370Cx58 and TMS370Cx59). For devices other than the TMS370Cx0x, TMS370Cx1x, and TMS370Cx5x devices, you must wire your own socket to the board. Use the assembler on a PC Use a wire-wrap prototyping area Use a patch assembler in the debugger mode Use a reverse assembler
17-20
The design kit includes: An assembler A C-source debugger An application board, also referred to as a design kit board (shown in Figure 17-10 on page 17-21 )
The Design Kit
Figure 17-10. Application Board (Design Kit Board)
Microprocessor/ microcomputer
Slave TMS370C010 Slave TMS370C010
100 uH
MC voltage adjustment 8v - 18v
TL497
Power
Caps
Xtal2
HD25X2
JP5
JP4 RAM or EPROM
Master EPROM
JP3
JP1 RAM/ EPROM
74HCT652
ACT11004 Master TMS370C050 RST/SW Xtal1 TLC4016 SW2
Slave TMS370C050 Xtal3
ACT11074
RS232
MAX232 ACT11074 ACT11244 ACT11374
ACT11244 74HCT138
ACT11374
Caps
ACT11074 ACT11244 ACT11374
74HCT138
ACT11244
ACT11374
Development Support
HD25X2
ACT11032
PAL16L8-15
ACT1108
HD25X2
17-21
The Design Kit
Requirements that you supply:
Debugger Mode
A 5 V, 500 mA power supply A 25-pin RS-232 cable (DB-25)
The design kit application board operates in one of three modes: Debugger mode TTY mode Isolated mode
The debugger mode is the standard TI programmer's interface. There are many advantages to using the debugger mode of operation:
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Multilevel debugging Powerful command set Window-oriented interface Comprehensive data displays On-screen editing Patch assembly Direct COFF download
To use the debugger mode of the design kit, the PC must meet the XDS system configuration requirements as discussed in subsection 17.7.2, on page 17-16. For more information on the debugger function, refer to Section 17.6.
TTY Mode
The TTY mode allows you to communicate using an ASCII serial protocol with equipment such as dumb terminals, PCs running terminal interface programs (for example, Crosstalk or Procomm), or computers that are not PC-compatible. This mode is most useful when you don't have access to a PC or if you need to do only simple operations or programming. The TTY mode has several two-letter commands that allow you to check the operation of an application board.
17-22
The Design Kit
Additionally, you can perform the following memory operations in the TTY mode; these operations aren't available in the debugger mode:
Isolated Mode
Run system tests Upload memory Verify memory Find bytes Move memory Compare memory Block program Directly read the analog pin Load on-chip EEPROM from on-board UVEPROM Use a computer in dumb terminal mode Reverse assemble with cycle times
After you have written and debugged a program for a slave, you can check the accuracy of that program by using the isolated mode. This mode turns off all debugger software and allows the slave device to run on its own.
Development Support
17-23
The Starter Kit
17.10 The Starter Kit
The TMS370 starter kit helps you to quickly assess the feasibility of using a member of the TMS370 family for your application. This low-cost programmer and simulation tool allows you to conduct software programming and simulations for the EEPROM and EPROM of the following families: TMS370Cx0x TMS370Cx4x TMS370CxAx TMS370Cx1x TMS370Cx5x (except '759) TMS370CxBx TMS370Cx2x TMS370Cx6x (except '769) TMS370Cx32 TMS370Cx7x
The starter kit package includes the following:
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TMS370 Assembler diskette and documentation TMS370 Simulator. Its capabilities include the following: Upload and download code Access any register or memory location Read and modify memory locations Execute programs and software routines Single-step executable instructions Use software breakpoints to halt program execution at selected addresses
J J J J J J
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Programming adapter board and programming software (shown in Figure 17-11)
Figure 17-11. Starter Kit
IC0
IC1 IC2
R P1 + P1 -
Reset
Xtal IC3 ICS OFF S1 POWER IC4
Requirements supplied by user:
17-24
A 5 V, 500 mA power supply A 9-pin RS-232 cable ZIF sockets
The Microcontroller Programmer
17.11 The Microcontroller Programmer
The TMS370 microcontroller programmer is an interactive, menu-driven system that provides a method of programming TMS370 family devices and EPROMs. The TMS370 microcontroller programmer system consists of a PDS (programmable device support) base unit, a microcontroller programmer top, and an IBM-compatible PC running microcontroller programmer software under MS/PC-DOS. The programmer top and PDS base unit are sold separately. Five types of tops are available for the packages listed below:
Type of Top 1 TMS370 Packages 28-Pin PDIP 40-Pin PDIP 40-Pin PSDIP 64-Pin PSDIP 28-Pin PLCC 44-Pin PLCC 68-Pin PLCC 44-Pin PLCC 40-Pin PSDIP 44-Pin PLCC 28-Pin PLCC/PDIP Devices Supported 'x1x 'x2x, 'x4x, 'x8x, and 'xAx 'x2x and 'x4x 'x5x, 'x7x, and 'xBx 'x0x and 'x1x 'x2x, 'x32, 'x4x, and 'x8x 'x5x, 'x6x, 'x7x, and 'xBx 'x36 'x9x 'x9x 'xCx
2
3 4 5
NOTE: Refer to subsection 19.4.4, on page 19-26, for ordering information. The programmer software provides both interactive and limited batch control with the following features:
-
Window-oriented screens with a menu-driven command structure Intermediate PC memory, which provides a storage area for downloading a file or for uploading from a device, which allows you to inspect and patch load data Relocatable programming capability, which allows source data bytes within a certain address range to be programmed at a specified address
Development Support
17-25
Reprogammable EPROM and OTP Devices
17.12 Reprogrammable EPROM and OTP Devices
In the TMS370 one-time programmable (OTP) and the SE370 reprogrammable EPROM devices, program ROM has been replaced by a programmable program memory, such as EPROM.
-
The TMS370 OTP devices are in plastic packages and can be programmed one time. The OTP device is an effective microcontroller to use for immediate production updates for other members of the TMS370 family or for low-volume production runs that cannot satisfy minimum volume or cycle times for low-cost mask-ROM devices. The SE370 reprogrammable EPROM devices are in windowed ceramic packages to allow reprogramming of the EPROM memory during the prototype development phase of design. This capability provides form factor preproduction parts with zero lead time for field testing and production qualifications, thereby reducing the overall time to market. This also supports applications with small production runs. You can program all TMS370 devices directly from the assembler or linker output file with the TMS370 microcontroller programmer. The application board can program the corresponding devices for which it demonstrates the capabilities.
-
Table 17-1, on page 17-27, shows the TMS370 ROM devices and their corresponding OTP devices and reprogrammable EPROM devices.
17-26
Reprogammable EPROM and OTP Devices
Table 17-1. OTP and Reprogrammable EPROM Support of ROM Devices
TMS370 ROM Device TMS370C002A TMS370C302A TMS370C010A TMS370C012A TMS370C310A TMS370C311A TMS370C312A TMS370C020A TMS370C320A TMS370C022A TMS370C322A TMS370C032A TMS370C036A TMS370C332A TMS370C040A TMS370C340A TMS370C042A TMS370C342A (See Note 1) TMS370C050A TMS370C350A TMS370C052A TMS370C352A TMS370C452A TMS370C353A TMS370C056A TMS370C356A TMS370C456A TMS370C058A TMS370C358A TMS370C059A TMS370C067A TMS370C068A TMS370C069A TMS370C077A TMS370C080 (See Note 2) TMS370C380A TMS370C090A TMS370C3A7A TMS370C0B6A TMS370C3C0A Notes: OTP EPROMs TMS370C702 TMS370C712A TMS370C712B Reprogrammable EPROMs SE370C702 SE370C712A SE370C712B
TMS370C722
SE370C722
TMS370C732A TMS370C736A TMS370C742A
SE370C732A SE370C736A SE370C742A
TMS370C756A TMS370C758A TMS370C758B TMS370C759A
SE370C756A SE370C758A SE370C758B SE370C759A
TMS370C768A TMS370C769A TMS370C777A TMS370C686A TMS370C792 (See Note 2) (See Note 2) TMS370C6C2A
SE370C768A SE370C769A SE370C777A SE370C686A SE370C792 (See Note 2) (See Note 2) SE370C6C2A
1) ROM-less devices (TMS370C15x, TMS370C25x) do not have EPROM devices. 2) For OTP EPROMs, the TMS370C758A and TMS370C758B are recommended. For reprogrammable EPROMS, the SE370C758A and SE370C758B are recommended. - For the TMS370C080 and TMS370C3A7 ROM devices, a converter socket is required in conjunction with the 'C758 EPROMS. - For the TMS370C0B6 device, refer to the TMS370CxBx Data Sheet (SPNS038) for pin-to-pin compatibility with the 'C758 EPROMs.
Development Support
17-27
17-28
Running Title--Attribute Reference
Chapter 18
Electrical Specifications and Timings
This chapter contains electrical and timing information for the TMS370 family devices. This information is presented according to device category.
Topic
18.1 18.2 18.3 18.4 18.5 18.6 18.7 18.8 18.9
Page
Timing Parameter Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2 Parameter Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2 Absolute Maximum Ratings for All TMS370 Devices . . . . . . . . . . . 18-3 External Crystal/Clock Connections and Typical Circuits for Loads and Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-4 General-Purpose Output Signal Timings . . . . . . . . . . . . . . . . . . . . . . 18-6 EPROM/EEPROM Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-7 TMS370Cx0xA and TMS370Cx0x Specifications . . . . . . . . . . . . . . . 18-8 TMS370Cx1xA and TMS370Cx1xB Specifications . . . . . . . . . . . . 18-12 TMS370Cx2xA and TMS370Cx2x Specifications . . . . . . . . . . . . . . 18-16
18.10 TMS370Cx32A Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-20 18.11 TMS370Cx36A Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-24 18.12 TMS370Cx4xA Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-29 18.13 TMS370Cx5xA and TMS370Cx5xB Specifications . . . . . . . . . . . . 18-34 18.14 TMS370Cx6xA Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-43 18.15 TMS370Cx7xA Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-51 18.16 TMS370Cx8xA Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-57 18.17 TMS370Cx9xA Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-62 18.18 TMS370CxAxA Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-68 18.19 TMS370CxBxA Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-73 18.20 TMS370CxCxA Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-79 18.21 SCI Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-84 18.22 SPI Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-86 18.23 Analog-to-Digital Converter 1 (ADC1) Module Specifications . . . . 18-89 18.24 Analog-to-Digital Converter 2 (ADC2) Module Specifications . . . . 18-92 18.25 Analog-to-Digital Converter 3 (ADC3) Module Specifications . . . . 18-94
Chapter Title--Attribute Reference
18-1
Timing Parameter Symbols / Parameter Measurements
18.1 Timing Parameter Symbols
Timing parameter symbols occur throughout this chapter. They were created in accordance with JEDEC standard 100A. To keep the symbols short, some of the signal names and other operational terms were abbreviated as follows: A AR B CI D E FE IE M PGM R Address Array mode Byte mode XTAL2/CLKIN Data EDS Final Initial Master mode Programming Read RXD S SC SCC SIMO SOMI SPC TXD W WT SCIRXD Slave mode SYSCLK SCICLK SPISIMO SPISOMI SPICLK SCITXD Write WAIT
Lowercase subscripts and their meanings are: c d f h Cycle time (period) Delay time Fall time Hold time r su v w Rise time Setup time Valid time Pulse duration (width)
The following additional letters are used with these meanings: H L High Low V Z Valid High impedance
18.2 Parameter Measurements
All timings are calculated between high and low measurement points as indicated in Figure 18-1.
Figure 18-1. Measurement Points for Timings
(a) XTAL2/CLKIN measurement points
0.8VCC V (High) 0.8 V (Low)
(b) General measurement points
2 V (High) 0.8 V (Low)
18-2
Absolute Maximum Ratings for All TMS370 Devices
18.3 Absolute Maximum Ratings for All TMS370 Devices
For all TMS370 devices, Table 18-1 provides the absolute maximum ratings over the operating free-air temperature range. This operating free-air temperature range is specified for your device in its respective section of this chapter. Stresses beyond those listed in Table 18-1 may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the recommended operating conditions for the specific device is not implied. Exposure to absolute-maximumrated conditions for extended periods may affect device reliability.
Table 18-1. Absolute Maximum Ratings Over Operating Free-Air Temperature Range (See Note 1)
Parameter Su ly Supply voltage range, VCC (see Note 1) range Input voltage range In ut All pins except MC ins exce t MC Input clamp current, IIK (VI < 0 V or VI > VCC) Output clamp current, IOK (VO < 0 V or VO > VCC) Continuous output current per buffer, IO (VO = 0 V to VCC) (see Note 2) Maximum supply current, ICC Maximum supply current, ISS Continuous power dissipation TMS370Cx0xA, TMS370Cx0x, TMS370Cx1xA, TMS370Cx1xB, TMS370CxCxA TMS370Cx32A TMS370Cx2xA, TMS370Cx2x, TMS370Cx36A, TMS370Cx4xA, TMS370Cx5xA, TMS370Cx5xB, TMS370Cx6xA, TMS370Cx7xA, TMS370Cx8xA, TMS370Cx9xA, TMS370CxAxA, TMS370CxBxA Storage temperature range, Tstg
Notes:
Maximum Rating
-0.6 -0 6 V to 7 V -0 6 V to 7 V -0.6 -0.6 -0 6 V to 14 V
"20 mA "20 mA "10 mA
170 mA -170 mA 500 mW
800 mW 1W
-65_C to 150_C
1) Unless otherwise noted, all voltage values are with respect to VSS (ground). 2) Electrical characteristics are specified with all output buffers loaded with the specified IO. Exceeding the specified IO in any buffer may affect the levels on other buffers.
Electrical Specifications and Timings
18-3
External Crystal/Clock Connections and Typical Circuits for Loads and Buffers
18.4 External Crystal/Clock Connections and Typical Circuits for Loads and Buffers
Figure 18-2 illustrates how to connect the crystal/ceramic resonator and the external clock signal. This figure is valid for all TMS370 family devices.
Figure 18-2. Recommended Crystal/Clock Connections
XTAL2/CLKIN
XTAL1
XTAL2/CLKIN
XTAL1 C3 (see Note 2)
C1 (see Note 2)
Crystal/Ceramic Resonator (see Note 1)
C2 (see Note 2)
External Clock Signal
Notes:
1) The crystal/ceramic resonator frequency is four times the reciprocal of the system clock period. 2) The values of C1 and C2 are typically 15 pF and the value of C3 is typically 50 pF. See the manufacturer's recommendations for ceramic resonators.
Figure 18-3 is an output load circuit that you can use for any TMS370 device.
Figure 18-3. Typical Output Load Circuit
Load Voltage
1.2 k
VO 20 pF
Case 1: VO = VOH = 2.4 V; Load Voltage = 0 V Case 2: VO = VOL = 0.4 V; Load Voltage = 2.1 V
Note: All measurements are made with the pin loading as shown unless otherwise noted. All measurements are made with XTAL2/CLKIN driven by an external square wave signal with a 50% duty cycle and rise and fall times less than 10 ns unless otherwise stated.
18-4
External Crystal/Clock Connections and Typical Circuits for Loads and Buffers
Figure 18-4. Typical Buffer Circuitry
VCC VCC
300 30 I/O 20
Pin data Output enable INT1
6 k
20
GND
GND
Electrical Specifications and Timings
18-5
General-Purpose Output Signal Timings
18.5 General-Purpose Output Signal Timings
Refer to Sections 18.1 and 18.2 for timing symbol definitions and parameter measurement points. The timings shown in this section are valid for all TMS370 family devices.
Table 18-2. General-Purpose Output Signal Timing Requirements
Parameter tr tf Rise time Fall time Min Nom 30 30 Max Unit ns ns
Figure 18-5. Switching Time Measurement Points
tr tf
18-6
EPROM/EEPROM Specifications
18.6 EPROM/EEPROM Specifications
Refer to Sections 18.1 and 18.2 for timing symbol definitions and parameter measurement points. The timings shown in this section are valid for all 'C702, 'C722, 'CxxxA, and 'CxxxB family devices except the 'C3xxA device.
Table 18-3. EEPROM Timing Requirements for Programming
Parameter tw(PGM)B tw(PGM)AR Pulse duration, programming signal to ensure valid data is stored (byte mode) Pulse duration, programming signal to ensure valid data is stored (array mode) Min 10 20 Max Unit ms ms
Table 18-4. Recommended EPROM Operating Conditions for Programming
Parameter VCC VPP IPP SYSCLK Supply voltage Supply voltage at MC pin Supply current at MC pin during programming (VPP = 13 V) System clock operating frequency Divide-by-4 clock Divide-by-1 clock 0.5 2 Min 4.75 13 Nom 5.5 13.2 30 Max 6 13.5 50 5 5 Unit V V mA MHz MHz
Table 18-5. EPROM Timing Requirements for Programming
Parameter tw(EPGM)
Note:
Min Pulse duration, programming signal (see Note) 0.40
Nom 0.50
Max 3
Unit ms
Programming pulse is active when both EXE (EPCTL.0) and VPPS (EPCTL.6) are set.
Note: The parameters VPP and tw(EPGM) for EPROM are different for the TMS370Cxxx devices (vs. the TMS370CxxxA or TMS370CxxxB devices). Refer to subsection A.9.3, Differences in EPROM Specifications, on page A-10.
Electrical Specifications and Timings
18-7
TMS370Cx0xA and TMS370Cx0x Specifications
18.7 TMS370Cx0xA and TMS370Cx0x Specifications
The tables in this section give specifications that apply to the devices in the TMS370Cx0xA and TMS370Cx0x categories. These devices include the TMS370C002A, TMS370C302A, TMS370C702, and SE370C702.
18.7.1 TMS370Cx0xA and TMS370Cx0x Electrical Specifications
Stresses beyond those listed in Table 18-1 may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the recommended operating conditions in Table 18-6 is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Table 18-6. Recommended Operating Conditions (See Note 1)
Parameter VCC Supply voltage (see Note 1) RAM data-retention supply voltage (see Note 2) VIL Low-level input voltage All pins except MC MC, normal operation VIH High-level input voltage All pins except MC, XTAL2 / CLKIN, and RESET XTAL2 / CLKIN RESET VMC MC (mode control) voltage EEPROM write-protect override (WPO) mode EPROM programming voltage (VPP) Microcomputer mode TA Operating free-air temperature L version A version T version
Notes:
Min 4.5 3 VSS VSS 2 0.8VCC 0.7VCC 11.7 13 VSS 0 -40 -40
Nom 5
Max 5.5 5.5 0.8 0.3 VCC VCC VCC
Unit V V V V V V V V V V C C C
12 13.2
13 13.5 0.3 70 85 105
1) Unless otherwise noted, all voltage values are with respect to VSS (ground). 2) RESET must be activated externally when VCC or SYSCLK is out of the recommended operating range.
18-8
TMS370Cx0xA and TMS370Cx0x Specifications
Table 18-7. Electrical Characteristics Over Recommended Operating Free-Air Temperature Range
Parameter VOL VOH II Low-level output voltage High-level output voltage Test Conditions IOL = 1.4 mA IOH = - 50 A IOH = - 2 mA Input current MC 0 V VI 0.3 V 0.3 V < VI 13 V 12 V VI 13 V (see Note 1) I / O pins IOL IOH ICC Low-level output current High-level output current 0 V VI VCC VOL = 0.4 V VOH = 0.9VCC VOH = 2.4 V Supply current (operating mode) OSC POWER bit = 0 (see Note 4) See Notes 2 and 3 SYSCLK = 5 MHz See Notes 2 and 3 SYSCLK = 3 MHz See Notes 2 and 3 SYSCLK = 0.5 MHz ICC Supply current (STANDBY mode) OSC POWER bit = 0 (see Note 5) See Notes 2 and 3 SYSCLK = 5 MHz See Notes 2 and 3 SYSCLK = 3 MHz See Notes 2 and 3 SYSCLK = 0.5 MHz ICC Supply current (STANDBY mode) OSC POWER bit = 1 (see Note 6) See Notes 2 and 3 SYSCLK = 3 MHz See Notes 2 and 3 SYSCLK = 0.5 MHz ICC Supply current (HALT mode) See Note 2 XTAL2 / CLKIN < 0.2 V 1.4 -50 -2 20 13 5 10 6.5 2 4.5 1.5 1 36 25 11 17 11 3.5 8.6 3.0 30 0.9VCC 2.4 10 650 50 10 Min Typ Max 0.4 Unit V V V A A mA A mA A mA mA mA mA mA mA mA mA mA A
Notes:
1) Input current IPP is a maximum of 50 mA only when EPROM is being programmed. 2) Single-chip mode, ports configured as inputs or as outputs with no load. All inputs 0.2 V or VCC - 0.2 V. 3) XTAL2/CLKIN is driven with an external square wave signal with 50% duty cycle and rise and fall times less than 10 ns. Current can be higher with a crystal oscillator. At 5-MHz SYSCLK, this extra current = 0.01 mA x (total load capacitance + crystal capacitance in pF). 4) Maximum operating current = 5.6 (SYSCLK) + 8 mA. 5) Maximum standby current = 3 (SYSCLK) + 2 mA (OSC POWER bit = 0). 6) Maximum standby current = 2.24 (SYSCLK) + 1.9 mA (OSC POWER bit = 1, only valid up to 3 MHz of SYSCLK).
Electrical Specifications and Timings
18-9
TMS370Cx0xA and TMS370Cx0x Specifications
18.7.2 TMS370Cx0xA and TMS370Cx0x Timings
Refer to Sections 18.1 and 18.2 (both on page 18-2) for timing symbol definitions and parameter measurement points.
Table 18-8. External Clocking Requirements for Divide-by-4 Clock (See Note 1)
No. 1 2 3 4 Parameter tw(Cl) tr(Cl) tf(CI) td(CIH-SCL) CLKIN SYSCLK
Notes:
Min Pulse duration, XTAL2/CLKIN (see Note 2) Rise time, XTAL2/CLKIN Fall time, XTAL2/CLKIN Delay time, XTAL2/CLKIN rise to SYSCLK fall Crystal operating frequency Internal system clock operating frequency (see Note 3) 2 0.5 20
Max
Unit ns
30 30 100 20 5
ns ns ns MHz MHz
1) For VIL and VIH, refer to recommended operating conditions in Table 18-6. 2) This pulse can be either a high pulse, as illustrated in Figure 18-6, which extends from the earliest valid high to the final valid high in an XTAL2/CLKIN cycle, or a low pulse, which extends from the earliest valid low to the final valid low in an XTAL2/CLKIN cycle. 3) SYSCLK = CLKIN/4
Figure 18-6. External Clock Timing for Divide-by-4 Clock
1 XTAL2/CLKIN 2 3 4 SYSCLK
18-10
TMS370Cx0xA and TMS370Cx0x Specifications
Table 18-9. External Clocking Requirements for Divide-by-1 Clock (PLL) (see Note 1)
No. 1 2 3 4 Parameter tw(Cl) tr(Cl) tf(CI) td(CIH-SCH) CLKIN SYSCLK
Notes:
Min Pulse duration, XTAL2/CLKIN (see Note 2) Rise time, XTAL2/CLKIN Fall time, XTAL2/CLKIN Delay time, XTAL2/CLKIN rise to SYSCLK rise Crystal operating frequency Internal system clock operating frequency (see Note 3) 2 2 20
Max
Unit ns
30 30 100 5 5
ns ns ns MHz MHz
1) For VIL and VIH, refer to recommended operating conditions in Table 18-6. 2) This pulse can be either a high pulse, as illustrated in Figure 18-7, which extends from the earliest valid high to the final valid high in an XTAL2/CLKIN cycle, or a low pulse, which extends from the earliest valid low to the final valid low in an XTAL2/CLKIN cycle. 3) SYSCLK = CLKIN/1
Figure 18-7. External Clock Timing for Divide-by-1 Clock
1 XTAL2/CLKIN 2 SYSCLK 3 4
Table 18-10. Switching Characteristics and Timing Requirements (See Note)
No. 5 Parameter tc Cycle time, SYSCLK Divide-by-4 clock Divide-by-1 clock 6 7
Note:
Min 200 200 0.5tc - 20 0.5tc
Max 2 000 500 0.5tc 0.5tc + 20
Unit ns ns ns ns
tw(SCL) tw(SCH)
Pulse duration, SYSCLK low Pulse duration, SYSCLK high
tc = system clock cycle time = 1 / SYSCLK
Figure 18-8. SYSCLK TIming
5 6 SYSCLK 7
Electrical Specifications and Timings
18-11
TMS370Cx1xA and TMS370Cx1xB Specifications
18.8 TMS370Cx1xA and TMS370Cx1xB Specifications
The tables in this section give specifications that apply to the devices in the TMS370Cx1xA and the TMS370Cx1xB categories. These devices include the TMS370C010A, TMS370C012A, TMS370C310A, TMS370C311A, TMS370C312A, TMS370C712A, TMS370C712B, SE370C712A, and SE370C712B.
18.8.1 TMS370Cx1xA and TMS370Cx1xB Electrical Specifications
Stresses beyond those listed in Table 18-1 may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the recommended operating conditions in Table 18-11 is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Table 18-11. Recommended Operating Conditions (See Note 1)
Parameter VCC Supply voltage (see Note 1) RAM data-retention supply voltage (see Note 2) VIL Low-level input voltage All pins except MC MC, normal operation VIH High-level input voltage All pins except MC, XTAL2 / CLKIN, and RESET XTAL2 / CLKIN RESET VMC MC (mode control) voltage EEPROM write-protect override (WPO) mode EPROM programming voltage (VPP) Microcomputer mode TA Operating free-air tempera- L version ture A version T version
Notes:
Min 4.5 3 VSS VSS 2 0.8VCC 0.7VCC 11.7 13 VSS 0 -40 -40
Nom 5
Max 5.5 5.5 0.8 0.3 VCC VCC VCC
Unit V V V V V V V V V V C C C
12 13.2
13 13.5 0.3 70 85 105
1) Unless otherwise noted, all voltage values are with respect to VSS (ground). 2) RESET must be externally activated when VCC or SYSCLK is not within the recommended operating range.
18-12
TMS370Cx1xA and TMS370Cx1xB Specifications
Table 18-12. Electrical Characteristics Over Recommended Operating Free-Air Temperature Range
Parameter VOL VOH II Low-level output voltage High-level output voltage Test Conditions IOL = 1.4 mA IOH = - 50 A IOH = - 2 mA Input current MC 0 V VI 0.3 V 0.3 V < VI 13 V 12 V VI 13 V (see Note 1) I / O pins IOL IOH ICC Low-level output current High-level output current 0 V VI VCC VOL = 0.4 V VOH = 0.9VCC VOH = 2.4 V Supply current (operating mode) OSC POWER bit = 0 (see Note 4) See Notes 2 and 3 SYSCLK = 5 MHz See Notes 2 and 3 SYSCLK = 3 MHz See Notes 2 and 3 SYSCLK = 0.5 MHz ICC Supply current (STANDBY mode) OSC POWER bit = 0 (see Note 5) See Notes 2 and 3 SYSCLK = 5 MHz See Notes 2 and 3 SYSCLK = 3 MHz See Notes 2 and 3 SYSCLK = 0.5 MHz ICC Supply current (STANDBY mode) OSC POWER bit = 1 (see Note 6) See Notes 2 and 3 SYSCLK = 3 MHz See Notes 2 and 3 SYSCLK = 0.5 MHz ICC Supply current (HALT mode) See Note 2 XTAL2 / CLKIN < 0.2 V 1.4 -50 -2 20 13 5 10 6.5 2 4.5 1.5 1 36 25 11 17 11 3.5 8.6 3.0 30 0.9VCC 2.4 10 650 50 10 Min Typ Max 0.4 Unit V V V A A mA A mA A mA mA mA mA mA mA mA mA mA A
Notes:
1) Input current IPP is a maximum of 50 mA only when EPROM is being programmed. 2) Single-chip mode, ports configured as inputs or as outputs with no load. All inputs 0.2 V or VCC - 0.2 V. 3) XTAL2/CLKIN is driven with an external square wave signal with 50% duty cycle and rise and fall times less than 10 ns. Current can be higher with a crystal oscillator. At 5-MHz SYSCLK, this extra current = 0.01 mA x (total load capacitance + crystal capacitance in pF). 4) Maximum operating current = 5.6(SYSCLK) + 8 mA. 5) Maximum standby current = 3(SYSCLK) + 2 mA (OSC POWER bit = 0). 6) Maximum standby current = 2.24(SYSCLK) + 1.9 mA (OSC POWER bit = 1; valid only up to 3-MHz SYSCLK).
Electrical Specifications and Timings
18-13
TMS370Cx1xA and TMS370Cx1xB Specifications
18.8.2 TMS370Cx1xA and TMS370Cx1xB Timings
Refer to Sections 18.1 and 18.2 (both on page 18-2) for timing symbol definitions and parameter measurement points.
Table 18-13. External Clocking Requirements for Divide-by-4 Clock (See Note 1)
No. 1 2 3 4 Parameter tw(Cl) tr(Cl) tf(CI) td(CIH-SCL) CLKIN SYSCLK
Notes:
Min Pulse duration, XTAL2/CLKIN (see Note 2) Rise time, XTAL2/CLKIN Fall time, XTAL2/CLKIN Delay time, XTAL2/CLKIN rise to SYSCLK fall Crystal operating frequency Internal system clock operating frequency (see Note 3) 2 0.5 20
Max
Unit ns
30 30 100 20 5
ns ns ns MHz MHz
1) For VIL and VIH, refer to recommended operating conditions in Table 18-11. 2) This pulse may be either a high pulse, as illustrated in Figure 18-9, which extends from the earliest valid high to the final valid high in an XTAL2/CLKIN cycle or a low pulse, which extends from the earliest valid low to the final valid low in an XTAL2/CLKIN cycle. 3) SYSCLK = CLKIN/4
Figure 18-9. External Clock Timing for Divide-by-4 Clock
1 XTAL2/CLKIN 2 3 4 SYSCLK
18-14
TMS370Cx1xA and TMS370Cx1xB Specifications
Table 18-14. External Clocking Requirements for Divide-by-1 Clock (PLL) (see Note 1)
No. 1 2 3 4 Parameter tw(Cl) tr(Cl) tf(CI) td(CIH-SCH) CLKIN SYSCLK
Notes:
Min Pulse duration, XTAL2/CLKIN (see Note 2) Rise time, XTAL2/CLKIN Fall time, XTAL2/CLKIN Delay time, XTAL2/CLKIN rise to SYSCLK rise Crystal operating frequency Internal system clock operating frequency (see Note 3) 2 2 20
Max
Unit ns
30 30 100 5 5
ns ns ns MHz MHz
1) For VIL and VIH, refer to recommended operating conditions in Table 18-11. 2) This pulse may be either a high pulse, as illustrated in Figure 18-10, which extends from the earliest valid high to the final valid high in an XTAL2/CLKIN cycle or a low pulse, which extends from the earliest valid low to the final valid low in an XTAL2/CLKIN cycle. 3) SYSCLK = CLKIN/1
Figure 18-10. External Clock Timing for Divide-by-1 Clock
1 XTAL2/CLKIN 2 SYSCLK 3 4
Table 18-15. Switching Characteristics and Timing Requirements (see Note)
No. 5 Parameter tc Cycle time, SYSCLK Divide-by-4 clock Divide-by-1 clock 6 7
Note:
Min 200 200 0.5tc - 20 0.5tc
Max 2000 500 0.5tc 0.5tc + 20
Unit ns ns ns ns
tw(SCL) tw(SCH)
Pulse duration, SYSCLK low Pulse duration, SYSCLK high
tc = system clock cycle time = 1 / SYSCLK
Figure 18-11. SYSCLK Timing
5 6 SYSCLK 7
Electrical Specifications and Timings
18-15
TMS370Cx2xA and TMS370Cx2x Specifications
18.9 TMS370Cx2xA and TMS370Cx2x Specifications
The tables in this section give specifications that apply to the devices in the TMS370Cx2xA TMS370Cx2x categories. These devices include the TMS370C020A, TMS370C022A, TMS370C320A, TMS370C322A, TMS370C722, and SE370C722.
18.9.1 TMS370Cx2xA and TMS370Cx2x Electrical Specifications
Stresses beyond those listed in Table 18-1 may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the recommended operating conditions in Table 18-16 is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Table 18-16. Recommended Operating Conditions (See Note 1)
Parameter VCC Supply voltage RAM data-retention supply voltage (see Note 2) VIL Low-level input voltage All pins except MC MC, normal operation VIH High-level input voltage All pins except MC, XTAL2 / CLKIN, and RESET XTAL2 / CLKIN RESET VMC MC (mode control) voltage EEPROM write-protect override (WPO) mode EPROM programming voltage (VPP) Microcomputer mode TA Operating free-air temperature L version A version T version
Notes:
Min 4.5 3 VSS VSS 2 0.8VCC 0.7VCC 11.7 13 VSS 0 -40 -40
Nom 5
Max 5.5 5.5 0.8 0.3 VCC VCC VCC
Unit V V V V V V V V V V C C C
12 13.2
13 13.5 0.3 70 85 105
1) Unless otherwise noted, all voltages are with respect to VSS (ground). 2) RESET must be externally activated when VCC or SYSCLK is out of the recommended operating range.
18-16
TMS370Cx2xA and TMS370Cx2x Specifications
Table 18-17. Electrical Characteristics Over Recommended Operating Free-Air Temperature Range
Parameter VOL VOH II Low-level output voltage High-level output voltage Input current MC Test Conditions IOL = 1.4 mA IOH = - 50 A IOH = - 2 mA 0 V < VI 0.3 V 0.3 V < VI 13 V 12 V VI 13 V (see Note 1) I / O pins IOL IOH ICC Low-level output current High-level output current Supply current (operating mode) OSC POWER bit = 0 (see Note 4) 0 V VI VCC VOL = 0.4 V VOH = 0.9VCC VOH = 2.4 V See Notes 2 and 3 SYSCLK = 5 MHz See Notes 2 and 3 SYSCLK = 3 MHz See Notes 2 and 3 SYSCLK = 0.5 MHz ICC Supply current (STANDBY mode) OSC POWER bit = 0 (see Note 5) See Notes 2 and 3 SYSCLK = 5 MHz See Notes 2 and 3 SYSCLK = 3 MHz See Notes 2 and 3 SYSCLK = 0.5 MHz ICC Supply current (STANDBY mode) OSC POWER bit = 1 (see Note 6) See Notes 2 and 3 SYSCLK = 3 MHz See Notes 2 and 3 SYSCLK = 0.5 MHz ICC Supply current (HALT mode) See Note 2 XTAL2 / CLKIN < 0.2 V 1.4 -50 -2 30 20 7 10 8 2 6 2 2 45 30 11 17 11 3.5 8.6 3.0 30 0.9VCC 2.4 10 650 50 10 Min Typ Max 0.4 Unit V V V A A mA A mA A mA mA mA mA mA mA mA mA mA A
Notes:
1) Input current IPP is a maximum of 50 mA only when EPROM is being programmed. 2) Single-chip mode, ports configured as inputs or as outputs with no load. All inputs 0.2 V or VCC - 0.2 V. 3) XTAL2/CLKIN is driven with an external square wave signal with 50% duty cycle and rise and fall times less than 10 ns. Current can be higher with a crystal oscillator. At 5-MHz SYSCLK, this extra current = 0.01 mA x (total load capacitance + crystal capacitance in pF). 4) Maximum operating current = 7.6(SYSCLK) + 7 mA. 5) Maximum standby current = 3(SYSCLK) + 2 mA (OSC POWER bit = 0). 6) Maximum standby current = 2.24(SYSCLK) + 1.9 mA (OSC POWER bit = 1; valid only up to 3-MHz SYSCLK).
Electrical Specifications and Timings
18-17
TMS370Cx2xA and TMS370Cx2x Specifications
18.9.2 TMS370Cx2xA and TMS370Cx2x Timings
Refer to Sections 18.1 and 18.2 (both on page 18-2) for timing symbol definitions and parameter measurement points.
Table 18-18. External Clocking Requirements for Divide-by-4 Clock (See Note 1)
No. 1 2 3 4 Parameter tw(Cl) tr(Cl) tf(CI) td(CIH-SCL) CLKIN SYSCLK
Notes:
Min Pulse duration, XTAL2/CLKIN (see Note 2) Rise time, XTAL2/CLKIN Fall time, XTAL2/CLKIN Delay time, XTAL2/CLKIN rise to SYSCLK fall Crystal operating frequency Internal system clock operating frequency (see Note 3) 2 0.5 20
Max
Unit ns
30 30 100 20 5
ns ns ns MHz MHz
1) For VIL and VIH, refer to recommended operating conditions in Table 18-16. 2) This pulse may be either a high pulse, as illustrated in Figure 18-12, which extends from the earliest valid high to the final valid high in an XTAL2/CLKIN cycle, or a low pulse, which extends from the earliest valid low to the final valid low in an XTAL2/CLKIN cycle. 3) SYSCLK = CLKIN/4
Figure 18-12. External Clock Timing for Divide-by-4 Clock
1 XTAL2/CLKIN 2 3 4 SYSCLK
18-18
TMS370Cx2xA and TMS370Cx2x Specifications
Table 18-19. External Clocking Requirements for Divide-by-1 Clock (PLL) (See Note 1)
No. 1 2 3 4 Parameter tw(Cl) tr(Cl) tf(CI) td(CIH-SCH) CLKIN SYSCLK
Notes:
Min Pulse duration, XTAL2/CLKIN (see Note 2) Rise time, XTAL2/CLKIN Fall time, XTAL2/CLKIN Delay time, XTAL2/CLKIN rise to SYSCLK rise Crystal operating frequency Internal system clock operating frequency (see Note 3) 2 2 20
Max
Unit ns
30 30 100 5 5
ns ns ns MHz MHz
1) For VIL and VIH, refer to recommended operating conditions in Table 18-16. 2) This pulse can be either a high pulse, as illustrated in Figure 18-13, which extends from the earliest valid high to the final valid high in an XTAL2/CLKIN cycle, or a low pulse, which extends from the earliest valid low to the final valid low in an XTAL2/CLKIN cycle. 3) SYSCLK = CLKIN/1
Figure 18-13. External Clock Timing for Divide-by-1 Clock
1 XTAL2/CLKIN 2 SYSCLK 3 4
Table 18-20. Switching Characteristics and Timing Requirements (See Note)
No. 5 Parameter tc Cycle time, SYSCLK Divide-by-4 clock Divide-by-1 clock 6 7
Note:
Min 200 200 0.5tc - 20 0.5tc
Max 2000 500 0.5tc 0.5tc + 20
Unit ns
tw(SCL) tw(SCH)
Pulse duration, SYSCLK low Pulse duration, SYSCLK high
ns ns
tc = system-clock cycle time = 1 / SYSCLK
Figure 18-14. SYSCLK Timing
5 6 SYSCLK 7
Electrical Specifications and Timings
18-19
TMS370Cx32A Specifications
18.10 TMS370Cx32A Specifications
The tables in this section give specifications that apply to the devices in the TMS370Cx32A category. These devices include the TMS370C032A, TMS370C332A, TMS370C732A, and SE370C732A.
18.10.1 TMS370Cx32A Electrical Specifications
Stresses beyond those listed in Table 18-1 may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the recommended operating conditions in Table 18-21 is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Table 18-21. Recommended Operating Conditions (See Note 1)
Parameter VCC1 Supply voltage RAM data-retention supply voltage (see Note 2) VCC3 Analog supply voltage VSS3 Analog supply ground VIL Low-level input voltage All pins except MC MC, normal operation VIH High-level input voltage All pins except MC, XTAL2 / CLKIN, and RESET XTAL2 / CLKIN RESET VMC MC (mode control) voltage EEPROM write-protect override (WPO) mode EPROM programming voltage (VPP) Microcomputer mode TA Operating free-air temperature L version A version T version
Notes:
Min 4.5 3 4.5 -0.3 VSS1 VSS1 2 0.8VCC1 0.7VCC1 11.7 13 VSS1 0 -40 -40
Nom 5
Max 5.5 5.5
Unit V V V V V V
5 0
5.5 0.3 0.8 0.3
VCC1 V VCC1 V VCC1 V 12 13.2 13 13.5 0.3 70 85 105 V V V C C C
1) Unless otherwise noted, all voltage values are with respect to VSS1. 2) RESET must be externally activated when VCC1 or SYSCLK is not within the recommended operating range.
18-20
TMS370Cx32A Specifications
Table 18-22. Electrical Characteristics Over Recommended Operating Free-Air Temperature Range
Parameter VOL VOH Low-level output voltage High-level output voltage Test Conditions IOL = 1.4 mA IOH = - 50 A IOH = - 2 mA II Input current MC 0 V VI 0.3 V 0.3 V < VI 13 V 12 V VI 13 V (see Note 1) I / O pins IOL IOH Low-level output current High-level output current 0 V VI VCC1 VOL = 0.4 V VOH = 0.9VCC1 VOH = 2.4 V ICC1 Supply current (operating mode) OSC POWER bit = 0 See Notes 2 and 3 SYSCLK = 5 MHz See Notes 2 and 3 SYSCLK = 3 MHz See Notes 2 and 3 SYSCLK = 0.5 MHz ICC1 Supply current (STANDBY mode) OSC POWER bit = 0 See Notes 2 and 3 SYSCLK = 5 MHz See Notes 2 and 3 SYSCLK = 3 MHz See Notes 2 and 3 SYSCLK = 0.5 MHz ICC1 Supply current (STANDBY mode) OSC POWER bit = 1 See Notes 2 and 3 SYSCLK = 3 MHz See Notes 2 and 3 SYSCLK = 0.5 MHz ICC1
Notes:
Min
Typ
Max 0.4
Unit V V V
0.9VCC 2.4 10 650 50 10 1.4 -50 -2 35 25 10 12 8 3 6 2 15 45 35 14 17 13 4 8.6 3.0 40
A A mA A mA A mA mA mA mA mA mA mA mA mA A
Supply current (HALT mode)
See Note 2 XTAL2/CLKIN < 0.2 V
1) Input current IPP is a maximum of 50 mA only when EPROM is being programmed. 2) Single-chip mode, ports configured as inputs or as outputs with no load. All inputs 0.2 V or VCC1 - 0.2 V. 3) XTAL2/CLKIN is driven with an external square wave signal with 50% duty cycle and rise and fall times less than 10 ns. Current can be higher with a crystal oscillator. At 5-MHz SYSCLK, this extra current = 0.01 mA x (total load capacitance + crystal capacitance in pF).
Electrical Specifications and Timings
18-21
TMS370Cx32A Specifications
18.10.2 TMS370Cx32A Timings
Refer to Sections 18.1 and 18.2 (both on page 18-2) for timing symbol definitions and parameter measurement points.
Table 18-23. External Clocking Requirements For Divide-by-4 Clock (See Note 1)
No. 1 2 3 4 Parameter tw(Cl) tr(Cl) tf(CI) td(CIH-SCL) CLKIN SYSCLK
Notes:
Min Pulse duration, XTAL2/CLKIN (see Note 2) Rise time, XTAL2/CLKIN Fall time, XTAL2/CLKIN Delay time, XTAL2/CLKIN rise to SYSCLK fall Crystal operating frequency Internal system clock operating frequency (see Note 3) 2 0.5 20
Max
Unit ns
30 30 100 20 5
ns ns ns MHz MHz
1) For VIL and VIH, refer to recommended operating conditions in Table 18-21. 2) This pulse may be either a high pulse, as illustrated in Figure 18-15, which extends from the earliest valid high to the final valid high in an XTAL2/CLKIN cycle or a low pulse, which extends from the earliest valid low to the final valid low in an XTAL2/CLKIN cycle. 3) SYSCLK = CLKIN/4
Figure 18-15. External Clock Timing for Divide-by-4 Clock
1 XTAL2/CLKIN 2 3 4 SYSCLK
18-22
TMS370Cx32A Specifications
Table 18-24. External Clocking Requirements for Divide-by-1 Clock (PLL) (See Note 1)
No. 1 2 3 4 Parameter tw(Cl) tr(Cl) tf(CI) td(CIH-SCH) CLKIN SYSCLK
Notes:
Min Pulse duration, XTAL2/CLKIN (see Note 2) Rise time, XTAL2/CLKIN Fall time, XTAL2/CLKIN Delay time, XTAL2/CLKIN rise to SYSCLK rise Crystal operating frequency Internal system clock operating frequency (see Note 3) 2 2 20
Max
Unit ns
30 30 100 5 5
ns ns ns MHz MHz
1) For VIL and VIH, refer to recommended operating conditions in Table 18-21. 2) This pulse can be either a high pulse, as illustrated in Figure 18-16, which extends from the earliest valid high to the final valid high in an XTAL2/CLKIN cycle or a low pulse, which extends from the earliest valid low to the final valid low in an XTAL2/CLKIN cycle. 3) SYSCLK = CLKIN/1
Figure 18-16. External Clock Timing for Divide-by-1 Clock
1 XTAL2/CLKIN 2 SYSCLK 3 4
Table 18-25. Switching Characteristics and Timing Requirements (See Note)
No. 5 Parameter tc Cycle time, SYSCLK Divide-by-4 clock Divide-by-1 clock 6 7
Note:
Min 200 200 0.5tc-20 0.5tc
Max 2000 500 0.5tc 0.5tc + 20
Unit ns
tw(SCL) tw(SCH)
Pulse duration, SYSCLK low Pulse duration, SYSCLK high
ns ns
tc = system clock cycle time = 1 / SYSCLK
Figure 18-17. SYSCLK Timing
5 6 SYSCLK 7
Electrical Specifications and Timings
18-23
TMS370Cx36A Specifications
18.11 TMS370Cx36A Specifications
The tables in this section give specifications that apply to the devices in the TMS370Cx36A category. These devices include the TMS370C036A, TMS370C736A, and SE370C736A.
18.11.1 TMS370Cx36A Electrical Specifications
Stresses beyond those listed in Table 18-1 may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the recommended operating conditions in Table 18-26 is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
18-24
TMS370Cx36A Specifications
Table 18-26. Recommended Operating Conditions (See Note 1)
Parameter VCC1 Supply voltage RAM data-retention supply voltage (see Note 2) VCCSTBY VCCSTBY VCC3 VSS3 VIL Standby RAM supply voltage Standby RAM data retention supply voltage (see Note 2) Analog supply voltage Analog supply ground Low-level input voltage High-level input voltage All pins except MC MC, normal operation VIH All pins except MC, XTAL2 / CLKIN, and RESET XTAL2 / CLKIN RESET VMC MC (mode control) voltage EEPROM write-protect override (WPO) mode EPROM programming voltage (VPP) Microcomputer mode TA Operating free-air temperature L version A version T version
Notes:
Min 4.5 3 4.5 3 4.5 -0.3 VSS1 VSS1 2 0.8VCC1 0.7VCC1 11.7 13 VSS1 0 -40 -40
Nom 5
Max 5.5 5.5
Unit V V V V V V V V
5
5.5 5.5
5 0
5.5 0.3 0.8 0.3
VCC1 V VCC1 V VCC1 V 12 13.2 13 13.5 0.3 70 85 105 V V V C C C
1) Unless otherwise noted, all voltage values are with respect to VSS1. 2) RESET must be externally activated when VCC1 or SYSCLK is not within the recommended operating range.
Electrical Specifications and Timings
18-25
TMS370Cx36A Specifications
Table 18-27. Electrical Characteristics Over Recommended Operating Free-Air Temperature Range
Parameter VOL VOH Low-level output voltage, all outputs High-level output voltage All outputs except PACT outputs PACT outputs All outputs II Input current MC pin Test Conditions IOL = 1.4 mA IOH = - 50 A 0.9VCC1 Min Typ Max 0.4 Unit V V
IOH = - 50 A IOH = - 2 mA 0 V < VI < 0.3 V 0.3 V < VI < VCC1 - 0.3 V VCC1 - 0.3 < VI < VCC1 + 0.3 V VCC1 + 0.3 V < VI < 13 V
0.7VCC1 2.4 10 50 10 650 10 1.4 -50 -2 36 7 45 12
V V A A A A A mA A mA mA mA
I / O pins IOL IOH Low-level output current, all outputs High-level output current, all outputs Supply current (operating mode) OSC POWER bit = 0 Supply current (STANDBY mode) OSC POWER bit = 0 Supply current (HALT mode) ICCSTBY Standby RAM supply current (operating mode) OSC POWER bit = 0
0 V < VI < VCC1 VOL = 0.4 V VOH = 0.9 VCC1 VOH = 2.4 V
ICC1
See Notes 1 and 2 SYSCLK = 5 MHz See Notes 1 and 2 SYSCLK = 5 MHz See Notes 1 and 2 XTAL2/CLKIN < 0.2 V SYSCLK = 5 MHz VCCSTBY = 4.5 V
5 1
30 1.5
A mA
Notes:
1) Single-chip mode, ports configured as inputs or as outputs with no load. All inputs 0.2 V or VCC1 - 0.2 V. 2) XTAL2/CLKIN is driven with an external square wave signal with 50% duty cycle and rise and fall times less than 10 ns. Current can be higher with a crystal oscillator. At 5-MHz SYSCLK, this extra current = 0.01 mA x (total load capacitance + crystal capacitance in pF).
18-26
TMS370Cx36A Specifications
18.11.2 TMS370Cx36A Timings
Refer to Sections 18.1 and 18.2 (both on page 18-2) for timing symbol definitions and parameter measurement points.
Table 18-28. External Clocking Requirements for Divide-by-4 Clock (See Note 1)
No. 1 2 3 4 Parameter tw(Cl) tr(Cl) tf(CI) td(CIH-SCL) CLKIN SYSCLK
Notes:
Min Pulse duration, XTAL2/CLKIN (see Note 2) Rise time, XTAL2/CLKIN Fall time, XTAL2/CLKIN Delay time, XTAL2/CLKIN rise to SYSCLK fall Crystal operating frequency Internal system clock operating frequency (see Note 3) 2 0.5 20
Max
Unit ns
30 30 100 20 5
ns ns ns MHz MHz
1) For VIL and VIH, refer to recommended operating conditions in Table 18-26. 2) This pulse may be either a high pulse, as illustrated in Figure 18-18, which extends from the earliest valid high to the final valid high in an XTAL2/CLKIN cycle or a low pulse, which extends from the earliest valid low to the final valid low in an XTAL2/CLKIN cycle. 3) SYSCLK = CLKIN/4
Figure 18-18. External Clock Timing for Divide-by-4 Clock
1 XTAL2/CLKIN 2 3 4 SYSCLK
Electrical Specifications and Timings
18-27
TMS370Cx36A Specifications
Table 18-29. External Clocking Requirements For Divide-by-1 Clock (PLL) (See Note 1)
No. 1 2 3 4 Parameter tw(Cl) tr(Cl) tf(CI) td(CIH-SCH) CLKIN SYSCLK
Notes:
Min Pulse duration, XTAL2/CLKIN (see Note 2) Rise time, XTAL2/CLKIN Fall time, XTAL2/CLKIN Delay time, XTAL2/CLKIN rise to SYSCLK rise Crystal operating frequency Internal system clock operating frequency (see Note 3) 2 2 20
Max
Unit ns
30 30 100 5 5
ns ns ns MHz MHz
1) For VIL and VIH, refer to recommended operating conditions in Table 18-26. 2) This pulse can be either a high pulse, as illustrated in Figure 18-19, which extends from the earliest valid high to the final valid high in an XTAL2/CLKIN cycle or a low pulse, which extends from the earliest valid low to the final valid low in an XTAL2/CLKIN cycle. 3) SYSCLK = CLKIN/1
Figure 18-19. External Clock Timing for Divide-by-1 Clock
1 XTAL2/CLKIN 2 SYSCLK 3 4
Table 18-30. Switching Characteristics and Timing Requirements (See Note)
No. 5 Parameter tc Cycle time, SYSCLK Divide-by-4 clock Divide-by-1 clock 6 7
Note:
Min 200 200 0.5tc-20 0.5tc
Max 2000 500 0.5tc 0.5tc + 20
Unit ns ns ns ns
tw(SCL) tw(SCH)
Pulse duration, SYSCLK low Pulse duration, SYSCLK high
tc = system clock cycle time = 1 / SYSCLK
Figure 18-20. SYSCLK Timing
5 6 SYSCLK 7
18-28
TMS370Cx4xA Specifications
18.12 TMS370Cx4xA Specifications
The tables in this section give specifications that apply to the devices in the TMS370Cx4xA category. These devices include the TMS370C040A, TMS370C042A, TMS370C340A, TMS370C342A, TMS370C742A, and SE370C742A.
18.12.1 TMS370Cx4xA Electrical Specifications
Stresses beyond those listed in Table 18-1 may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the recommended operating conditions in Table 18-31 is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Electrical Specifications and Timings
18-29
TMS370Cx4xA Specifications
Table 18-31. Recommended Operating Conditions (See Note 1)
Parameter VCC Supply voltage RAM data-retention supply voltage (see Note 2) VCC3 Analog supply voltage VSS3 Analog supply ground VIL Low-level input voltage All pins except MC MC, normal operation VIH High-level input voltage All pins except MC, XTAL2/CLKIN, and RESET XTAL2/CLKIN RESET VMC MC (mode control) volt- EEPROM write-protect override age (WPO) mode Microcomputer mode EPROM programming voltage (VPP) TA Operating free-air temperature L version A version T version
Notes:
Min 4.5 3 4.5 -0.3 VSS VSS 2 0.8VCC 0.7VCC 11.7 VSS 13 0 -40 -40
Nom 5
Max 5.5 5.5
Unit V V V V V V V V V V V V C C C
5 0
5.5 0.3 0.8 0.3 VCC VCC VCC
12
13 0.3
13.2
13.5 70 85 105
1) Unless otherwise noted, all voltage values are with respect to VSS (ground). 2) RESET must be externally activated when VCC or SYSCLK is out of the recommended operating range.
18-30
TMS370Cx4xA Specifications
Table 18-32. Electrical Characteristics Over Recommended Operating Free-Air Temperature Range
Parameter VOL VOH II Low-level digital output voltage High-level output voltage Test Conditions IOL = 1.4 mA IOH = - 50 A IOH = - 2 mA Input current MC 0 V < VI 0.3 V 0.3 V < VI 13 V 12 V VI 13 V (see Note 6) I/O pins IOL IOH ICC Low-level output current High-level output current 0 V VI VCC VOL = 0.4 V VOH = 0.9VCC VOH = 2.4 V Supply current (operating mode) See Notes 1 and 2 OSC POWER bit = 0 (see Note 3) SYSCLK = 5 MHz See Notes 1 and 2 SYSCLK = 3 MHz See Notes 1 and 2 SYSCLK = 0.5 MHz ICC Supply current (STANDBY mode) See Notes 1 and 2 OSC POWER bit = 0 (see Note 4) SYSCLK = 5 MHz See Notes 1 and 2 SYSCLK = 3 MHz See Notes 1 and 2 SYSCLK = 0.5 MHz ICC Supply current (STANDBY mode) See Notes 1 and 2 OSC POWER bit = 1 (see Note 5) SYSCLK = 3 MHz See Notes 1 and 2 SYSCLK = 0.5 MHz ICC Supply current (HALT mode) See Note 1 XTALK2/CLKIN < 0.2 V 1.4 -50 -2 30 20 7 10 8 2 6 2 2 45 30 11 17 11 3.5 8.6 3.0 30 0.9VCC 2.4 10 650 50 10 Min Typ Max 0.4 Unit V V V A A mA A mA A mA mA mA mA mA mA mA mA mA A
Notes:
1) Microcontroller single-chip mode, ports configured as inputs or as outputs with no load. All inputs 0.2 V or VCC - 0.2 V. 2) XTAL2/CLKIN is driven with an external square wave signal with 50% duty cycle and rise and fall times less than 10 ns. Current can be higher with a crystal oscillator. At 5-MHz SYSCLK this extra current = 0.01 mA x (total load capacitance + crystal capacitance in pF). 3) Maximum operating current = 7.6(SYSCLK) + 7 mA. 4) Maximum standby current = 3(SYSCLK) + 2 mA (OSC POWER bit = 0.) 5) Maximum standby current = 2.24(SYSCLK) + 1.9 mA (OSC POWER bit = 1; valid only up to 3-MHz SYSCLK.) 6) Input current IPP is a maximum of 50 mA only when an EPROM is being programmed.
Electrical Specifications and Timings
18-31
TMS370Cx4xA Specifications
18.12.2 TMS370Cx4xA Timings
Refer to Sections 18.1 and 18.2 (both on page 18-2) for timing symbol definitions and parameter measurement points.
Table 18-33. External Clocking Requirements for Divide-by-4 Clock (See Note 1)
No. 1 2 3 4 Parameter tw(Cl) tr(Cl) tf(CI) td(CIH-SCL) CLKIN SYSCLK
Notes:
Min Pulse duration, XTAL2/CLKIN (see Note 2) Rise time, XTAL2/CLKIN Fall time, XTAL2/CLKIN Delay time, XTAL2/CLKIN rise to SYSCLK fall Crystal operating frequency Internal system clock operating frequency (see Note 3) 2 0.5 20
Max
Unit ns
30 30 100 20 5
ns ns ns MHz MHz
1) For VIL and VIH, refer to recommended operating conditions in Table 18-31. 2) This pulse can be either a high pulse, as illustrated in Figure 18-21, which extends from the earliest valid high to the final valid high in an XTAL2/CLKIN cycle or a low pulse, which extends from the earliest valid low to the final valid low in an XTAL2/CLKIN cycle. 3) SYSCLK = CLKIN/4
Figure 18-21. External Clock Timing for Divide-by-4 Clock
1 XTAL2/CLKIN 2 3 4 SYSCLK
18-32
TMS370Cx4xA Specifications
Table 18-34. External Clocking Requirements for Divide-by-1 Clock (PLL) (See Note 1)
No. 1 2 3 4 Parameter tw(Cl) tr(Cl) tf(CI) td(CIH-SCH) CLKIN SYSCLK
Notes:
Min Pulse duration, XTAL2/CLKIN (see Note 2) Rise time, XTAL2/CLKIN Fall time, XTAL2/CLKIN Delay time, XTAL2/CLKIN rise to SYSCLK rise Crystal operating frequency Internal system clock operating frequency (see Note 3) 2 2 20
Max
Unit ns
30 30 100 5 5
ns ns ns MHz MHz
1) For VIL and VIH, refer to recommended operating conditions in Table 18-31. 2) This pulse can be either a high pulse, as illustrated in Figure 18-22, which extends from the earliest valid high to the final valid high in an XTAL2/CLKIN cycle or a low pulse, which extends from the earliest valid low to the final valid low in an XTAL2/CLKIN cycle. 3) SYSCLK = CLKIN/1
Figure 18-22. External Clock Timing for Divide-by-1 Clock
1 XTAL2/CLKIN 2 SYSCLK 3 4
Table 18-35. Switching Characteristics and Timing Requirements (See Note)
No. 5 Parameter tc Cycle time, SYSCLK Divide-by-4 clock Divide-by-1 clock 6 7
Note:
Min 200 200 0.5tc - 20 0.5tc
Max 2 000 500 0.5tc 0.5tc + 20
Unit ns ns ns ns
tw(SCL) tw(SCH)
Pulse duration, SYSCLK low Pulse duration, SYSCLK high
tc = system-clock cycle time = 1/SYSCLK.
Figure 18-23. SYSCLK Timing
5 6 SYSCLK 7
Electrical Specifications and Timings
18-33
TMS370Cx5xA and TMS370Cx5xB Specifications
18.13 TMS370Cx5xA and TMS370Cx5xB Specifications
The tables in this section give specifications that apply to the devices in the TMS370Cx5xA and TMS370Cx5xB categories. These devices include the following: TMS370C050A TMS370C052A TMS370C056A TMS370C456A TMS370C358A SE370758B Note: Some electrical specifications and timings differ for TMS370Cx5x devices. Refer to Appendix A. TMS370C150A TMS370C352A TMS370C156A TMS370C756A TMS370C758A TMS370C059A TMS370C250A TMS370C452A TMS370C256A SE370C756A TMS370C758B, TMS370C759A TMS370C350A TMS370C353A TMS370C356A TMS370C058A SE370C758A SE370C759A
18.13.1 TMS370Cx5xA and TMS370Cx5xB Electrical Specifications
Stresses beyond those listed in Table 18-1 may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the recommended operating conditions in Table 18-36 is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
18-34
TMS370Cx5xA and TMS370Cx5xB Specifications
Table 18-36. Recommended Operating Conditions (See Note 1)
Parameter VCC1 Supply voltage RAM data-retention supply voltage (see Note 2) VCC2 Digital I/O supply voltage VCC3 Analog supply voltage VSS2 Digital I/O supply ground VSS3 Analog supply ground VIL VIH Low-level input voltage l High-level input voltage All pins except MC MC, normal operation All pins except MC, XTAL2 / CLKIN, and RESET MC (non-WPO mode) XTAL2 / CLKIN RESET VMC MC (mode control) voltage (see N ( Note 3) ) EEPROM write-protect override (WPO) mode EPROM programming voltage (VPP) Microprocessor mode Microcomputer mode TA Operating freeair temperature i L version A version T version
Notes:
Min 4.5 3 4.5 4.5 -0.3 -0.3 VSS1 VSS1 2 VCC1 - 0.3 0.8VCC1 0.7VCC1 11.7 13 VCC1 - 0.3 VSS1 0 -40 -40
Nom 5
Max 5.5 5.5
Unit V V V V V V V V V V V V V V V V C C C
5 5 0 0
5.5 5.5 0.3 0.3 0.8 0.3 VCC1 VCC1 + 0.3 VCC1 VCC1
12 13.2
13 13.5 VCC1 + 0.3 0.3 70 85 105
1) Unless otherwise noted, all voltage values are with respect to VSS1. 2) RESET must be externally activated when VCC1 or SYSCLK is not within the recommended operating range. 3) The basic microcomputer and microprocessor operating modes are selected by the voltage level applied to the dedicated MC pin two system-clock cycles (2tc) before RESET goes inactive (high). The WPO mode can be selected any time a sufficient voltage is present on MC.
You cannot use the internal connectors between pins (e.g., the connector between VSS1 and VSS2) for a jumper from one side of the chip to another.
Electrical Specifications and Timings
18-35
TMS370Cx5xA and TMS370Cx5xB Specifications
Table 18-37. Electrical Characteristics Over Recommended Operating Free-Air Temperature Range
Parameter VOL VOH Low-level output voltage (see Note 1) High-level output voltage Test Conditions IOL = 1.4 mA IOH = - 50 A IOH = - 2 mA II Input current MC 0 V < VI 0.3 V 0.3 V < VI < VCC1 - 0.3 V VCC1 - 0.3 V VI VCC1 + 0.3 V VCC1 + 0.3 V < VI 13 V 12 V VI 13 V (see Note 2) I / O pins IOL IOH Low-level output current (see Note 1) High-level output current 0 V VI VCC1 VOL = 0.4 V VOH = 0.9VCC1 VOH = 2.4 V ICC1 Supply current (operating mode) OSC POWER bit = 0 (see Note 5) TMS370Cx50A TMS370Cx52A TMS370Cx53A TMS370Cx56A TMS370Cx58A TMS370Cx58B See Notes 3 and 4 SYSCLK = 5 MHz 1.4 -50 -2 30 35 45 56 0.9VCC 2.4 10 50 10 650 50 10 Min Typ Max 0.4 Unit V V V A A A A mA A mA A mA mA mA
TMS370Cx59 operates only up to 3-MHz SYSCLK. Notes: 1) In prior versions of the TMS370 family, IOL was equal to 2 mA for ports A, B, C, and D and RESET. 2) Input current IPP is a maximum of 50 mA only when EPROM is being programmed. 3) Single-chip mode, ports configured as inputs or as outputs with no load. All inputs 0.2 V or VCC1 - 0.2 V. 4) XTAL2/CLKIN is driven with an external square wave signal with 50% duty cycle and rise and fall times less than 10 ns. Current can be higher with a crystal oscillator. At 5-MHz SYSCLK, this extra current = 0.01 mA x (total load capacitance + crystal capacitance in pF). 5) Maximum operating current for TMS370Cx50A and TMS370Cx52A = 7.6(SYSCLK) + 7 mA. Maximum operating current for the 'Cx53A, 'Cx56A, 'Cx58A, and 'Cx58B = 10(SYSCLK) + 5.8 mA. 6) Maximum standby current for the 'Cx5xA and 'Cx5xB = 3(SYSCLK) + 2 mA (OSC POWER bit = 0). 7) Maximum standby current for the 'Cx5xA and 'Cx5xB = 2.24(SYSCLK) + 1.9 mA (OSC POWER bit = 1; valid only up to 3-MHz SYSCLK.)
18-36
TMS370Cx5xA and TMS370Cx5xB Specifications
Table 18-37. Electrical Characteristics Over Recommended Operating Free-Air Temperature Range (Continued)
Parameter ICC1 Supply current (operating mode) OSC POWER bit = 0 (see Note 5) TMS370Cx50A TMS370Cx52A TMS370Cx53A TMS370Cx56A TMS370Cx58A TMS370Cx58B TMS370Cx59A ICC1 Supply current (operating mode) OSC POWER bit = 0 (see Note 5) TMS370Cx50A TMS370Cx52A TMS370Cx53A TMS370Cx56A TMS370Cx58A TMS370Cx58B TMS370Cx59A ICC1 Supply current (STANDBY mode) OSC POWER bit = 0 (see Note 6) See Notes 3 and 4 SYSCLK = 5 MHz See Notes 3 and 4 SYSCLK = 3 MHz See Notes 3 and 4 SYSCLK = 0.5 MHz ICC1 Supply current (STANDBY mode) OSC POWER bit = 1 (see Note 7) See Notes 3 and 4 SYSCLK = 3 MHz See Notes 3 and 4 SYSCLK = 0.5 MHz ICC1 Supply current (HALT mode) See Note 3 XTAL2 / CLKIN < 0.2 V See Notes 3 and 4 SYSCLK = 0.5 MHz Test Conditions See Notes 3 and 4 SYSCLK = 3 MHz Min Typ Max 20 25 30 36 Unit mA mA
46 5 13
55 11 18
mA mA mA
22 12 8 2.5 6 2 2
28 17 11 3.5 8.6 3 30
mA mA mA mA mA mA A
TMS370Cx59A operates only up to 3-MHz SYSCLK. Notes: 1) 2) 3) 4) I then prior versions of the TMS370 family, IOL was equal to 2 mA for ports A, B, C, and D and RESET. Input current IPP is a maximum of 50 mA only when EPROM is being programmed. Single-chip mode, ports configured as inputs or as outputs with no load. All inputs 0.2 V or VCC1 - 0.2 V. XTAL2/CLKIN is driven with an external square wave signal with 50% duty cycle and rise and fall times less than 10 ns. Current can be higher with a crystal oscillator. At 5-MHz SYSCLK, this extra current = 0.01 mA x (total load capacitance + crystal capacitance in pF). 5) Maximum operating current for the 'Cx50A and 'Cx52A = 7.6(SYSCLK) + 7 mA. Maximum operating current for the 'Cx53A, 'Cx56A, 'Cx58A and 'Cx58B = 10(SYSCLK) + 5.8 mA. 6) Maximum standby current for the 'Cx5xA and 'Cx5xB = 3(SYSCLK) + 2 mA (OSC POWER bit = 0). 7) Maximum standby current for the 'Cx5xA and 'Cx5xB = 2.24(SYSCLK) + 1.9 mA (OSC POWER bit = 1; valid only up to 3-MHz SYSCLK.)
Electrical Specifications and Timings
18-37
TMS370Cx5xA and TMS370Cx5xB Specifications
18.13.2 TMS370Cx5xA and TMS370Cx5xB Timings
Refer to Sections 18.1 and 18.2 (both on page 18-2) for timing symbol definitions and parameter measurement points.
Table 18-38. External Clocking Requirements for Divide-by-4 Clock (See Note 1)
No. 1 2 3 4 Parameter tw(Cl) tr(Cl) tf(CI) td(CIH-SCL) CLKIN SYSCLK
Notes:
Min Pulse duration, XTAL2/CLKIN (see Note 2) Rise time, XTAL2/CLKIN Fall time, XTAL2/CLKIN Delay time, XTAL2/CLKIN rise to SYSCLK fall Crystal operating frequency (see Note 3) Internal system clock operating frequency (see Notes 4 and 5) 2 0.5 20
Max
Unit ns
30 30 100 20 5
ns ns ns MHz MHz
1) For VIL and VIH, refer to recommended operating conditions in Table 18-36. 2) This pulse can be either a high pulse, as illustrated in Figure 18-24, which extends from the earliest valid high to the final valid high in an XTAL2/CLKIN cycle, or a low pulse, which extends from the earliest valid low to the final valid low in an XTAL2/CLKIN cycle. 3) TMS370Cx59A operates up to 12-MHz CLKIN. 4) TMS370Cx59A operates up to 3-MHz SYSCLK. 5) SYSCLK = CLKIN/4
Figure 18-24. External Clock Timing for Divide-by-4 Clock
1 XTAL2/CLKIN 2 3 4 SYSCLK
18-38
TMS370Cx5xA and TMS370Cx5xB Specifications
Table 18-39. External Clocking Requirements for Divide-by-1 Clock (PLL) (see Note 1)
No. 1 2 3 4 Parameter tw(Cl) tr(Cl) tf(CI) td(CIH-SCH) CLKIN SYSCLK
Notes:
Min Pulse duration, XTAL2/CLKIN (see Note 2) Rise time, XTAL2/CLKIN Fall time, XTAL2/CLKIN Delay time, XTAL2/CLKIN rise to SYSCLK rise Crystal operating frequency (see Note 3) Internal system clock operating frequency (see Notes 4 and 5) 2 2 20
Max
Unit ns
30 30 100 5 5
ns ns ns MHz MHz
1) For VIL and VIH, refer to recommended operating conditions in Table 18-36. 2) This pulse can be either a high pulse, as illustrated in Figure 18-25, which extends from the earliest valid high to the final valid high in an XTAL2/CLKIN cycle, or a low pulse, which extends from the earliest valid low to the final valid low in an XTAL2/CLKIN cycle. 3) TMS370Cx59A operates up to 3-MHz CLKIN (for the divide-by-1 clock option). 4) TMS370Cx59A operates up to 3-MHz SYSCLK. 5) SYSCLK = CLKIN/1
Figure 18-25. External Clock Timing for Divide-by-1 Clock
1 XTAL2/CLKIN 2 3 4 SYSCLK
Electrical Specifications and Timings
18-39
TMS370Cx5xA and TMS370Cx5xB Specifications
Table 18-40. Switching Characteristics and Timing Requirements for External Read and Write (See Note 1)
No. 5 Parameter tc tw(SCL) tw(SCH) td(SCL-A) tv(A) tsu(D) th(EH-A) th(EH-D)W td(DZ-EL) td(EH-D) td(EL-DV)R th(EH-D)R Cycle time, SYSCLK Divide-by-4 clock Min 200 Max 2 000 500 0.5tc 0.5tc + 20 0.25tc + 75 0.5tc - 90 0.75tc - 80 See Note 2 0.5tc - 60 0.75tc + 15 0.25tc - 35 1.25tc - 40 Unit ns ns ns ns ns ns ns ns ns ns ns tc - 95 ns See Note 2 0 0.25tc + 70 See Note 3 0 0.5tc - 60 ns ns ns ns
Divide-by-1 clock (PLL) 200 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Pulse duration, SYSCLK low Pulse duration, SYSCLK high Delay time, SYSCLK low to address, R / W, and OCF valid Valid time, address valid to EDS, CSE1, CSE2, CSH1, CSH2, CSH3, and CSPF low Setup time, write data to EDS high Hold time, address, R / W, and OCF from EDS, CSE1, CSE2, CSH1, CSH2, CSH3, and CSPF high Hold time, write data from EDS high Delay time, data bus high impedance to EDS low (read cycle) Delay time, EDS high to data bus enable (read cycle) Delay time, EDS low to read data valid Hold time, read from EDS high 0.5tc - 25 0.5tc
tsu(WT-SCH) Setup time, WAIT to SYSCLK high th(SCH-WT) td(EL-WTV) tw td(AV-DV)R td(AV-WTV) td(AV-EH) Hold time, WAIT time from SYSCLK high Delay time, EDS low to WAIT valid Pulse duration, EDS, CSE1, CSE2, CSH1, CSH2, CSH3, and CSPF low Delay time, address valid to read data valid Delay time, address valid to WAIT valid Delay time, address valid to EDS high (end of write)
tc - 80 tc + 40 ns See Note 2 See Note 2 1.5tc - 115 ns See Note 2 tc - 115 1.5tc - 85 See Note 2 ns ns
Notes:
1) tc = system-clock cycle time = 1 / SYSCLK 2) If wait states, PFWait, or the autowait feature is used, add tc to this value for each wait state invoked. 3) If the autowait feature is enabled, the WAIT input can assume a "don't care" condition until the third cycle of the access. The WAIT signal must be synchronized with the high pulse of the SYSCLK signal while still conforming to the minimum setup time.
18-40
TMS370Cx5xA and TMS370Cx5xB Specifications
Figure 18-26. External Read Timing
7 5 6 SYSCLK 8 ADDRESS 11 EDS, CSE1, CSE2, CSH1, CSH2, CSH3, CSPF 20 9 21 13 15 DATA '370 Drives Data Read Data Drive 19 22 17 18 WAIT Read Data Valid '370 Drives Data Read Data Disable 14 16
R/W
OCF
Electrical Specifications and Timings
18-41
TMS370Cx5xA and TMS370Cx5xB Specifications
Figure 18-27. External Write Timing
7 5 6 SYSCLK 8 ADDRESS 11 20 EDS, CSE1, CSE2, CSH1, CSH2, CSH3, CSPF 9 10 23 12 DATA 19 22 17 18 WAIT
R/W
18-42
TMS370Cx6xA Specifications
18.14 TMS370Cx6xA Specifications
The tables in this section give specifications that apply to the devices in the TMS370Cx6xA category. These devices include the TMS370C067A, TMS370C068A, TMS370C069A, TMS370C768A, TMS370C769A, SE370C768A, and SE370C769A.
18.14.1 TMS370Cx6xA Electrical Specifications
Stresses beyond those listed in Table 18-1 may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the recommended operating conditions in Table 18-41 is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Electrical Specifications and Timings
18-43
TMS370Cx6xA Specifications
Table 18-41. Recommended Operating Conditions (See Note 1)
Parameter VCC1 Supply voltage RAM data-retention supply voltage (see Note 2) VCC2 Digital I/O supply voltage VCC3 Analog supply voltage VSS2 Digital I/O supply ground VSS3 Analog supply ground VIL Low-level input voltage High-level input voltage All pins except MC MC, normal operation All pins except MC, XTAL2 / CLKIN, and RESET MC (non-WPO mode) XTAL2 / CLKIN RESET VMC MC (mode control) voltage (see Note 3) EEPROM write-protect override (WPO) mode EPROM programming voltage (VPP) Microprocessor mode Microcomputer mode TA Operating free-air temperature L version A version T version
Notes:
Min 4.5 3 4.5 4.5 -0.3 -0.3 VSS1 VSS1 2 VCC1 - 0.3 0.8VCC1 0.7VCC1 11.7 13 VCC1 - 0.3 VSS1 0 -40 -40
Nom 5
Max 5.5 5.5
Unit V V V V V V V V V
5 5 0 0
5.5 5.5 0.3 0.3 0.8 0.3 VCC1
VIH
VCC1 + 0.3 V VCC1 VCC1 12 13.2 13 13.5 V V V V
VCC1 + 0.3 V 0.3 70 85 105 V C C C
1) Unless otherwise noted, all voltage values are with respect to VSS1. 2) RESET must be externally activated when VCC1 or SYSCLK is out of the recommended operating range. 3) The basic microcomputer and microprocessor operating modes are selected by the voltage level applied to the dedicated MC pin two system-clock cycles (2tc) before RESET goes inactive (high). The WPO mode can be selected any time a sufficient voltage is present on MC.
You cannot use the internal connections between pins (for example, the connection between VSS1 and VSS2) for a jumper from one side of the chip to the other.
18-44
TMS370Cx6xA Specifications
Table 18-42. Electrical Characteristics Over Recommended Operating Free-Air Temperature Range
Parameter VOL VOH II Low-level output voltage High-level output voltage Input current MC Test Conditions IOL = 1.4 mA IOH = - 50 A IOH = - 2 mA 0 V < VI 0.3 V 0.3 V < VI < VCC1 - 0.3 V VCC1- 0.3 V VI VCC1 + 0.3 V VCC1 + 0.3 V < VI 13 V 12 V VI 13 V (see Note 1) 0 V VI VCC1 VOL = 0.4 V VOH = 0.9VCC1 VOH = 2.4 V See Notes 2 and 3 SYSCLK = 5 MHz See Notes 2 and 3 SYSCLK = 3 MHz See Notes 2 and 3 SYSCLK = 0.5 MHz See Notes 2 and 3 SYSCLK = 5 MHz See Notes 2 and 3 SYSCLK = 3 MHz See Notes 2 and 3 SYSCLK = 0.5 MHz See Notes 2 and 3 SYSCLK = 3 MHz See Notes 2 and 3 SYSCLK = 0.5 MHz See Note 2 XTAL2 / CLKIN < 0.2 V 1.4 -50 -2 35 25 46 13 22 12 8 2.5 6 2 2 56 36 55 18 28 17 11 3.5 8.6 3 30 0.9VCC1 2.4 10 50 10 650 50 10 Min Typ Max Unit 0.4 V V V A A A A mA A mA A mA mA mA mA mA mA mA mA mA mA mA A
I / O pins IOL IOH ICC1 Low-level output current High-level output current Supply current (operating mode) OSC POWER bit = 0 ( (see Note 4) ) 'Cx67A, 'Cx68A 'Cx67A, 'Cx68A 'Cx69A 'Cx67A, 'Cx68A 'Cx69A ICC1 Supply current (STANDBY mode) OSC POWER bit = 0 (see Note 5)
ICC1
Supply current (STANDBY mode) OSC POWER bit = 1 (see Note 6)
ICC1
Supply current (HALT mode)
TMS370Cx69A operates only up to 3 MHz SYSLCK. Notes: 1) Input current IPP is a maximum of 50 mA only when EPROM is being programmed. 2) Single-chip mode, ports configured as inputs or as outputs with no load. All inputs 0.2 V or VCC1 - 0.2 V. 3) XTAL2/CLKIN is driven with an external square wave signal with 50% duty cycle and rise and fall times less than 10 ns. Current can be higher with a crystal oscillator. At 5-MHz SYSCLK, this extra current = 0.01 mA x (total load capacitance + crystal capacitance in pF). 4) Maximum operating current = 10(SYSCLK) + 5.8 mA. 5) Maximum standby current = 3(SYSCLK) + 2 mA (OSC POWER bit = 0). 6) Maximum standby current = 2.24(SYSCLK) + 1.9 mA (OSC POWER bit = 1; valid only up to 3-MHz SYSCLK).
Electrical Specifications and Timings
18-45
TMS370Cx6xA Specifications
18.14.2 TMS370Cx6xA Timings
Refer to Sections 18.1 and 18.2 (both on page 18-2) for timing symbol definitions and parameter measurement points.
Table 18-43. External Clocking Requirements for Divide-by-4 Clock (see Note 1)
No. 1 2 3 4 Parameter tw(Cl) tr(Cl) tf(CI) td(CIH-SCL) CLKIN SYSCLK
Notes:
Min Pulse duration, XTAL2/CLKIN (see Note 2) Rise time, XTAL2/CLKIN Fall time, XTAL2/CLKIN Delay time, XTAL2/CLKIN rise to SYSCLK fall Crystal operating frequency (see note 3) Internal system clock operating frequency (see Notes 4 and 5) 2 0.5 20
Max
Unit ns
30 30 100 20 5
ns ns ns MHz MHz
1) For VIL and VIH, refer to recommended operating conditions table in Table 18-41. 2) This pulse can be either a high pulse, as illustrated in Figure 18-28, which extends from the earliest valid high to the final valid high in an XTAL2/CLKIN cycle, or a low pulse, which extends from the earliest valid low to the final valid low in an XTAL2/CLKIN cycle. 3) TMS370Cx69A operates up to 12 MHz CLKIN. 4) TMS370Cx69A operates up to 3 MHz SYSCLK. 5) SYSCLK = CLKIN/4
Figure 18-28. External Clock Timing for Divide-by-4 Clock
1 XTAL2/CLKIN 2 3 4 SYSCLK
18-46
TMS370Cx6xA Specifications
Table 18-44. External Clocking Requirements for Divide-by-1 Clock (PLL)(See Note 1)
No. 1 2 3 4 Parameter tw(Cl) tr(Cl) tf(CI) td(CIH-SCH) CLKIN SYSCLK
Notes:
Min Pulse duration, XTAL2/CLKIN (see Note 2) Rise time, XTAL2/CLKIN Fall time, XTAL2/CLKIN Delay time, XTAL2/CLKIN rise to SYSCLK rise Crystal operating frequency (see Note 3) Internal system clock operating frequency (see Notes 4 and 5) 2 2 20
Max
Unit ns
30 30 100 5 5
ns ns ns MHz MHz
1) For VIL and VIH, refer to recommended operating conditions in Table 18-41. 2) This pulse can be either a high pulse, as illustrated in Figure 18-29, which extends from the earliest valid high to the final valid high in an XTAL2/CLKIN cycle, or a low pulse, which extends from the earliest valid low to the final valid low in an XTAL2/CLKIN cycle. 3) TMS370Cx69A operates up to 3-MHz CLKIN (for the divide-by-1 clock option). 4) TMS370Cx69A operates up to 3 MHz SYSCLK. 5) SYSCLK = CLKIN/1
Figure 18-29. External Clock Timing for Divide-by-1 Clock
1 XTAL2/CLKIN 2 3 4 SYSCLK
Electrical Specifications and Timings
18-47
TMS370Cx6xA Specifications
Table 18-45. Switching Characteristics and Timing Requirements for External Read and Write (See Note 1)
No. 5 Parameter tc tw(SCL) tw(SCH) td(SCL-A) tv(A) tsu(D) th(EH-A) th(EH-D)W td(DZ-EL) td(EH-D) td(EL-DV)R th(EH-D)R Cycle time, SYSCLK Divide-by-4 clock Min 200 0.5tc - 25 0.5tc Divide-by-1 clock (PLL) 200 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Pulse duration, SYSCLK low Pulse duration, SYSCLK high Delay time, SYSCLK low to address, R / W, and OCF valid Valid time, address valid to EDS, CSE1, CSH1, and CSPF low Setup time, write data to EDS high Hold time, address, R / W, and OCF from EDS, CSE1, CSH1, and CSPF high Hold time, write data time from EDS high Delay time, data bus high impedance to EDS low (read cycle) Delay time, EDS high to data bus enable (read cycle) Delay time, EDS low to read data valid Hold time, read from EDS high 0 0.25tc + 70 See Note 3 0 0.5tc - 60 tc - 80 See Note 2 tc + 40 See Note 2 1.5tc - 115 See Note 2 tc - 115 1.5tc - 85 See Note 2 0.5tc - 90 0.75tc - 80 See Note 2 0.5tc - 60 0.75tc + 15 0.25tc - 35 1.25tc - 40 tc - 95 See Note 2 Max 2 000 500 0.5tc 0.5tc + 20 0.25tc + 75 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tsu(WT-SCH) Setup time, WAIT to SYSCLK high th(SCH-WT) td(EL-WTV) tw td(AV-DV)R td(AV-WTV) td(AV-EH) Hold time, WAIT from SYSCLK high Delay time, EDS low to WAIT valid Pulse duration, EDS, CSE1, CSH1, and CSPF low Delay time, address valid to read data valid Delay time, address valid to WAIT valid Delay time, address valid to EDS high (end of write)
Notes:
1) tc = system clock cycle time = 1 / SYSCLK 2) If wait states, PFWait, or the autowait feature is used, add tc to this value for each wait state invoked. 3) If the autowait feature is enabled, the WAIT input can assume a "don't care" condition until the third cycle of the access. The WAIT signal must be synchronized with the high pulse of the SYSCLK signal while still conforming to the minimum setup time.
18-48
TMS370Cx6xA Specifications
Figure 18-30. External Read Timing
7 5 6 SYSCLK 8 ADDRESS 11 EDS, CSE1, CSH1, CSPF 9 21 13 15 DATA '370 Drives Data Read Data Drive 19 22 17 18 WAIT Read Data Valid 16 20 14
'370 Drives Data Read Data Disable
R/W
OCF
Electrical Specifications and Timings
18-49
TMS370Cx6xA Specifications
Figure 18-31. External Write Timing
7 5 6 SYSCLK 8 ADDRESS 11 EDS, CSE1, CSH1, CSPF 9 10 23 12 DATA 19 22 17 18 WAIT 20
R/W
18-50
TMS370Cx7xA Specifications
18.15 TMS370Cx7xA Specifications
The tables in this section give specifications that apply to the devices in the TMS370Cx7xA category. These devices include the TMS370C077A, TMS370C777A, and SE370C777A.
18.15.1 TMS370Cx7xA Electrical Specifications
Stresses beyond those listed in Table 18-1 may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the recommended operating conditions in Table 18-46 is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Electrical Specifications and Timings
18-51
TMS370Cx7xA Specifications
Table 18-46. Recommended Operating Conditions (See Note 1)
Parameter VCC1 Supply voltage RAM data-retention supply voltage (see Note 2) VCC2 Digital I/O supply voltage VCC3 Analog supply voltage VSS2 Digital I/O supply ground VSS3 Analog supply ground VIL Low-level input voltage lt High-level input voltage All pins except MC MC, normal operation All pins except MC, XTAL2 / CLKIN, and RESET MC (non-WPO mode) XTAL2 / CLKIN RESET VMC MC (mode control) voltage (see N t 3) ( Note EEPROM write-protect override (WPO) mode EPROM programming voltage (VPP) Microprocessor mode Microcomputer mode TA Operating freeair t i temperature t L version A version T version
Notes:
Min 4.5 3 4.5 4.5 -0.3 -0.3 VSS1 VSS1 2 VCC1 - 0.3 0.8VCC1 0.7VCC1 11.7 13 VCC1 - 0.3 VSS1 0 -40 -40
Nom 5
Max 5.5 5.5
Unit V V V V V V V V V V V V V V V V C C C
5 5 0 0
5.5 5.5 0.3 0.3 0.8 0.3 VCC1 VCC1 + 0.3 VCC1 VCC1
VIH
12 13.2
13 13.5 VCC1 + 0.3 0.3 70 85 105
1) Unless otherwise noted, all voltage values are with respect to VSS1. 2) RESET must be activated externally when VCC1 or SYSCLK is out of the recommended operating range. 3) The basic microcomputer and microprocessor operating modes are selected by the voltage level applied to the dedicated MC pin two system clock cycles (2tc) before RESET goes inactive (high). The WPO mode can be selected any time a sufficient voltage is present on MC.
You cannot use the internal connections between pins (for example, the connection between VSS1 and VSS2) for a jumper from one side of the chip to the other.
18-52
TMS370Cx7xA Specifications
Table 18-47. Electrical Characteristics Over Recommended Operating Free-Air Temperature Range
Parameter VOL VOH II Low-level output voltage High-level output voltage Input current MC Test Conditions IOL = 1.4 mA IOH = - 50 A IOH = - 2 mA 0 V < VI 0.3 V 0.3 V < VI < VCC1 - 0.3 V VCC1 - 0.3 V VI VCC1 + 0.3 V VCC1 + 0.3 V < VI 13 V 12 V VI 13 V (see Note 1) I / O pins IOL IOH ICC Low-level output current High-level output current Supply current (operating mode) OSC POWER bit = 0 (see Note 4) 0 V VI VCC1 VOL = 0.4 V VOH = 0.9VCC1 VOH = 2.4 V See Notes 2 and 3 SYSCLK = 5 MHz See Notes 2 and 3 SYSCLK = 3 MHz See Notes 2 and 3 SYSCLK = 0.5 MHz ICC Supply current (STANDBY mode) OSC POWER bi = 0 ( N bit (see Note 5) See Notes 2 and 3 SYSCLK = 5 MHz See Notes 2 and 3 SYSCLK = 3 MHz See Notes 2 and 3 SYSCLK = 0.5 MHz ICC Supply current (STANDBY mode) OSC POWER bi = 1 ( N bit (see Note 6) Supply current (HALT mode) See Notes 2 and 3 SYSCLK = 3 MHz See Notes 2 and 3 SYSCLK = 0.5 MHz See Note 2 XTAL2 / CLKIN < 0.2 V 1.4 -50 -2 35 25 13 12 8 2.5 6 2 2 56 36 18 17 11 3.5 8.6 3 30 A mA mA 0.9VCC1 2.4 10 50 10 650 50 10 mA A mA A mA mA A Min Typ Max 0.4 Unit V V
ICC
Notes:
1) Input current IPP is a maximum of 50 mA only when EPROM is being programmed. 2) Single-chip mode, ports configured as inputs or as outputs with no load. All inputs 0.2 V or VCC1 - 0.2 V. 3) XTAL2/CLKIN is driven with an external square wave signal with 50% duty cycle and rise and fall times less than 10 ns. Current can be higher with a crystal oscillator. At 5 MHz SYSCLK, this extra current = 0.01 mA x (total load capacitance + crystal capacitance in pF). 4) Maximum operating current = 10(SYSCLK) + 5.8 mA. 5) Maximum standby current = 3(SYSCLK) + 2 mA (OSC POWER bit = 0). 6) Maximum standby current = 2.24(SYSCLK) + 1.9 mA (OSC POWER bit =1; valid only up to 3-MHz SYSCLK).
Electrical Specifications and Timings
18-53
TMS370Cx7xA Specifications
18.15.2 TMS370Cx7xA Timings
Refer to Sections18.1 and 18.2 (page 18-2) for timing symbol definitions and parameter measurement points.
Table 18-48. External Clocking Requirements for Divide-by-4 Clock (See Note 1)
No. 1 2 3 4 Parameter tw(Cl) tr(Cl) tf(CI) td(CIH-SCL) CLKIN SYSCLK
Notes:
Min Pulse duration, XTAL2/CLKIN (see Note 2) Rise time, XTAL2/CLKIN Fall time, XTAL2/CLKIN Delay time, XTAL2/CLKIN rise to SYSCLK fall Crystal operating frequency Internal system clock operating frequency (see Note 3) 2 0.5 20
Max
Unit ns
30 30 100 20 5
ns ns ns MHz MHz
1) For VIL and VIH, refer to recommended operating conditions in Table 18-46. 2) This pulse can be either a high pulse, as illustrated in Figure 18-32, which extends from the earliest valid high to the final valid high in an XTAL2/CLKIN cycle, or a low pulse, which extends from the earliest valid low to the final valid low in an XTAL2/CLKIN cycle. 3) SYSCLK = CLKIN/4
Figure 18-32. External Clock Timing for Divide-by-4 Clock
1 XTAL2/CLKIN 2 3 4 SYSCLK
18-54
TMS370Cx7xA Specifications
Table 18-49. External Clocking Requirements for Divide-by-1 Clock (PLL)(see Note 1)
No. 1 2 3 4 Parameter tw(Cl) tr(Cl) tf(CI) td(CIH-SCH) CLKIN SYSCLK
Notes:
Min Pulse duration, XTAL2/CLKIN (see Note 2) Rise time, XTAL2/CLKIN Fall time, XTAL2/CLKIN Delay time, XTAL2/CLKIN rise to SYSCLK rise Crystal operating frequency Internal system clock operating frequency (see Note 3) 2 2 20
Max
Unit ns
30 30 100 5 5
ns ns ns MHz MHz
1) For VIL and VIH, refer to recommended operating conditions in Table 18-46. 2) This pulse can be either a high pulse, as illustrated in Figure 18-33, which extends from the earliest valid high to the final valid high in an XTAL2/CLKIN cycle, or a low pulse, which extends from the earliest valid low to the final valid low in an XTAL2/CLKIN cycle. 3) SYSCLK = CLKIN/1
Figure 18-33. External Clock Timing for Divide-by-1 Clock
1 XTAL2/CLKIN 2 3 4 SYSCLK
Electrical Specifications and Timings
18-55
TMS370Cx7xA Specifications
Table 18-50. Switching Characteristics and TIming Requirements (See Note)
No. 5 Parameter tc tw(SCL) tw(SCH) Cycle time, SYSCLK Divide-by-4 clock Min 200 0.5tc - 25 0.5tc Divide-by-1 clock (PLL) 200 6 7
Note:
Max 2 000 500 0.5tc 0.5tc + 20
Unit ns ns ns ns
Pulse duration, SYSCLK low Pulse duration, SYSCLK high
tc = system clock cycle time = 1 / SYSCLK
Figure 18-34. SYSCLK Timing
7 5 6 SYSCLK
18-56
TMS370Cx8xA Specifications
18.16 TMS370Cx8xA Specifications
The tables in this section give specifications that apply to the devices in the TMS370Cx8xA category. These devices include the TMS370C080A, TMS370C380A, TMS370C686A, and SE370C686A.
18.16.1 TMS370Cx8xA Electrical Specifications
Stresses beyond those listed in Table 18-1 may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the recommended operating conditions in Table 18-51 is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Table 18-51. Recommended Operating Conditions (See Note 1)
Parameter VCC Supply voltage RAM data-retention supply voltage (see Note 2) VIL Low-level input voltage All pins except MC MC, normal operation VIH High-level input voltage All pins except MC, XTAL2 / CLKIN, and RESET XTAL2 / CLKIN RESET VMC MC (mode control) voltage EEPROM write-protect override (WPO) mode EPROM programming voltage (VPP) Microcomputer mode TA Operating free-air temperature L version A version T version
Notes:
Min 4.5 3 VSS VSS 2 0.8VCC 0.7VCC 11.7 13 VSS 0 -40 -40
Nom 5
Max 5.5 5.5 0.8 0.3 VCC VCC VCC
Unit V V V V V V V V V V C C C
12 13.2
13 13.5 0.3 70 85 105
1) Unless otherwise noted, all voltage values are with respect to VSS (ground). 2) RESET must be externally activated when VCC or SYSCLK is not within the recommended operating range.
Electrical Specifications and Timings
18-57
TMS370Cx8xA Specifications
Table 18-52. Electrical Characteristics Over Recommended Operating Free-Air Temperature Range
Parameter VOL VOH II Low-level output voltage High-level output voltage Input current MC Test Conditions IOL = 1.4 mA IOH = - 50 A IOH = - 2 mA 0 V < VI 0.3 V 0.3 V < VI 13 V 12 V VI 13 V (see Note 1) I / O pins IOL IOH ICC Low-level output current High-level output current Supply current (operating mode) OSC POWER bit = 0 (see Note 4) 0 V VI VCC VOL = 0.4 V VOH = 0.9VCC VOH = 2.4 V See Notes 2 and 3 SYSCLK = 5 MHz See Notes 2 and 3 SYSCLK = 3 MHz See Notes 2 and 3 SYSCLK = 0.5 MHz ICC Supply current (STANDBY mode) OSC POWER bit = 0 (see Note 5) See Notes 2 and 3 SYSCLK = 5 MHz See Notes 2 and 3 SYSCLK = 3 MHz See Notes 2 and 3 SYSCLK = 0.5 MHz ICC Supply current (STANDBY mode) OSC POWER bit = 1 (see Note 6) See Notes 2 and 3 SYSCLK = 3 MHz See Notes 2 and 3 SYSCLK = 0.5 MHz ICC Supply current (HALT mode) See Note 2 XTAL2 / CLKIN < 0.2 V 1.4 -50 -2 30 20 7 10 8 2 6 2 2 45 30 11 17 11 3.5 8.6 3.0 30 0.9VCC 2.4 10 650 50 10 Min Typ Max 0.4 Unit V V V A A mA A mA A mA mA mA mA mA mA mA mA mA A
Notes:
1) Input current IPP is a maximum of 50 mA only when EPROM is being programmed. 2) Single-chip mode, ports configured as inputs or as outputs with no load. All inputs 0.2 V or VCC - 0.2 V. 3) XTAL2/CLKIN is driven with an external square wave signal with 50% duty cycle and rise and fall times less than 10 ns. Current can be higher with a crystal oscillator. At 5-MHz SYSCLK, this extra current = 0.01 mA x (total load capacitance + crystal capacitance in pF). 4) Maximum operating current = 7.6(SYSCLK) + 7 mA. 5) Maximum standby current = 3(SYSCLK) + 2 mA (OSC POWER bit = 0). 6) Maximum standby current = 2.24(SYSCLK) + 1.9 mA (OSC POWER bit = 1; valid only up to 3-MHz SYSCLK).
18-58
TMS370Cx8xA Specifications
18.16.2 TMS370Cx8xA Timings
Refer to Section 18.1 and Section 18.2 (both on page 18-2) for timing symbol definitions and parameter measurement points.
Table 18-53. External Clocking Requirements for Divide-by-4 Clock (See Note 1)
No. 1 2 3 4 Parameter tw(Cl) tr(Cl) tf(CI) td(CIH-SCL) CLKIN SYSCLK
Notes:
Min Pulse duration, XTAL2/CLKIN (see Note 2) Rise time, XTAL2/CLKIN Fall time, XTAL2/CLKIN Delay time, XTAL2/CLKIN rise to SYSCLK fall Crystal operating frequency Internal system clock operating frequency (see Note 3) 2 0.5 20
Max
Unit ns
30 30 100 20 5
ns ns ns MHz MHz
1) For VIL and VIH, refer to recommended operating conditions in Table 18-51. 2) This pulse may be either a high pulse, as illustrated in Figure 18-35, which extends from the earliest valid high to the final valid high in an XTAL2/CLKIN cycle or a low pulse, which extends from the earliest valid low to the final valid low in an XTAL2/CLKIN cycle. 3) SYSCLK = CLKIN/4
Figure 18-35. External Clock Timing for Divide-by-4 Clock
1 XTAL2/CLKIN 2 3 4 SYSCLK
Electrical Specifications and Timings
18-59
TMS370Cx8xA Specifications
Table 18-54. External Clocking Requirements for Divide-by-1 Clock (PLL) (See Note 1)
No. 1 2 3 4 Parameter tw(Cl) tr(Cl) tf(CI) td(CIH-SCH) CLKIN SYSCLK
Notes:
Min Pulse duration, XTAL2/CLKIN (see Note 2) Rise time, XTAL2/CLKIN Fall time, XTAL2/CLKIN Delay time, XTAL2/CLKIN rise to SYSCLK rise Crystal operating frequency Internal system clock operating frequency (see Note 3) 2 2 20
Max
Unit ns
30 30 100 5 5
ns ns ns MHz MHz
1) For VIL and VIH, refer to recommended operating conditions in Table 18-51. 2) This pulse can be either a high pulse, as illustrated in Figure 18-36, which extends from the earliest valid high to the final valid high in an XTAL2/CLKIN cycle or a low pulse, which extends from the earliest valid low to the final valid low in an XTAL2/CLKIN cycle. 3) SYSCLK = CLKIN/1
Figure 18-36. External Clock Timing for Divide-by-1 Clock
1 XTAL2/CLKIN 2 SYSCLK 3 4
18-60
TMS370Cx8xA Specifications
Table 18-55. Switching Characteristics and Timing Requirements (See Note)
No. 5 Parameter tc Cycle time, SYSCLK Divide-by-4 clock Divide-by-1 clock 6 7
Note:
Min 200 200 0.5tc - 20 0.5tc
Max 2000 500 0.5tc 0.5tc + 20
Unit ns ns ns ns
tw(SCL) tw(SCH)
Pulse duration, SYSCLK low Pulse duration, SYSCLK high
tc = system-clock cycle time = 1 / SYSCLK
Figure 18-37. SYSCLK Timing
5 6 SYSCLK 7
Electrical Specifications and Timings
18-61
TMS370Cx9xA Specifications
18.17 TMS370Cx9xA Specifications
The tables in this section give specifications that apply to the devices in the TMS370Cx9xA category. These devices include the TMS370C090A, TMS370C792A, and SE370C792A.
18.17.1 TMS370Cx9xA Electrical Specifications
Stresses beyond those listed in Table 18-1 may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the recommended operating conditions in Table 18-56 is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
18-62
TMS370Cx9xA Specifications
Table 18-56. Recommended Operating Conditions (See Note 1)
Parameter VCC Supply voltage RAM data-retention supply voltage (see Note 2) VCC3 Analog supply voltage VSS3 Analog supply ground VIL Low-level input voltage All pins except MC MC, normal operation VIH High-level input voltage All pins except MC, XTAL2 / CLKIN, and RESET XTAL2 / CLKIN RESET VMC MC (mode control) voltage EEPROM write-protect override (WPO) mode EPROM programming voltage (VPP) Microcomputer mode TA Operating free-air temperature L version A version T version
Notes:
Min 4.5 3 3 - 0.3 VSS VSS 2 0.8VCC 0.7VCC 11.7 13 VSS 0 -40 -40
Nom 5
Max 5.5 5.5 5.5
Unit V V V V V V V V V V V V C C C
0
0.3 0.8 0.3 VCC VCC VCC
12 13.2
13 13.5 0.3 70 85 105
1) Unless otherwise noted, all voltage values are with respect to VSS (ground). 2) RESET must be externally activated when VCC or SYSCLK is out of the recommended operating range.
Electrical Specifications and Timings
18-63
TMS370Cx9xA Specifications
Table 18-57. Electrical Characteristics Over Recommended Operating Free-Air Temperature Range
Parameter VOL VOH II Low-level output voltage High-level output voltage Test Conditions IOL = 1.4 mA IOH = - 50 A IOH = - 2 mA Input current MC 0 V < VI 0.3 V 0.3 V < VI 13 V 12 V VI 13 V (see Note 1) I / O pins IOL IOH ICC Low-level output current High-level output current 0 V VI VCC VOL = 0.4 V VOH = 0.9VCC VOH = 2.4 V Supply current (operating mode) y g OSC POWER bit = 0 (see Note 4) See Notes 2 and 3 SYSCLK = 5 MHz See Notes 2 and 3 SYSCLK = 3 MHz See Notes 2 and 3 SYSCLK = 0.5 MHz ICC Supply current (STANDBY mode) OSC POWER bit = 0 ( ) (see N Note 5) See Notes 2 and 3 SYSCLK = 5 MHz See Notes 2 and 3 SYSCLK = 3 MHz See Notes 2 and 3 SYSCLK = 0.5 MHz ICC Supply current (STANDBY mode) OSC POWER bit = 1 ( ) (see N Note 6) See Notes 2 and 3 SYSCLK = 3 MHz See Notes 2 and 3 SYSCLK = 0.5 MHz See Note 2 XTAL2 / CLKIN < 0.2 V 1.4 -50 -2 30 20 7 10 8 2 6 2 2 45 30 11 17 11 3.5 8.6 3 30 0.9VCC 2.4 10 650 50 10 Min Typ Max 0.4 Unit V V V A A mA A mA A mA mA mA mA mA mA mA mA mA A
ICC
Notes:
Supply current (HALT mode)
1) Input current IPP is a maximum of 50 mA only when EPROM is being programmed. 2) Single-chip mode, ports configured as inputs or as outputs with no load. All inputs 0.2 V or VCC - 0.2 V. 3) XTAL2/CLKIN is driven with an external square wave signal with 50% duty cycle and rise and fall times less than 10 ns. Current can be higher with a crystal oscillator. At 5-MHz SYSCLK, this extra current = 0.01 mA x (total load capacitance + crystal capacitance in pF). 4) Maximum operating current = 7.6(SYSCLK) + 7 mA. 5) Maximum standby current = 3(SYSCLK) + 2 mA (OSC POWER bit = 0). 6) Maximum standby current = 2.24(SYSCLK) + 1.9 mA (OSC POWER bit =1; valid only up to 3-MHz SYSCLK).
18-64
TMS370Cx9xA Specifications
18.17.2 TMS370Cx9xA Timings
Refer to Section 18.1 and Section 18.2 (both on page 18-2) for timing symbol definitions and parameter measurement points.
Table 18-58. External Clocking Requirements for Divide-by-4 Clock (See Note 1)
No. 1 2 3 4 Parameter tw(Cl) tr(Cl) tf(CI) td(CIH-SCL) CLKIN SYSCLK
Notes:
Min Pulse duration, XTAL2/CLKIN (see Note 2) Rise time, XTAL2/CLKIN Fall time, XTAL2/CLKIN Delay time, XTAL2/CLKIN rise to SYSCLK fall Crystal operating frequency Internal system clock operating frequency (see Note 3) 2 0.5 20
Max
Unit ns
30 30 100 20 5
ns ns ns MHz MHz
1) For VIL and VIH, refer to recommended operating conditions in Table 18-56. 2) This pulse can be either a high pulse, as illustrated in Figure 18-38, which extends from the earliest valid high to the final valid high in an XTAL2/CLKIN cycle or a low pulse, which extends from the earliest valid low to the final valid low in an XTAL2/CLKIN cycle. 3) SYSCLK = CLKIN/4
Figure 18-38. External Clock Timing for Divide-by-4 Clock
1 XTAL2/CLKIN 2 3 4 SYSCLK
Electrical Specifications and Timings
18-65
TMS370Cx9xA Specifications
Table 18-59. External Clocking Requirements for Divide-by-1 Clock (PLL) (See Note 1)
No. 1 2 3 4 Parameter tw(Cl) tr(Cl) tf(CI) td(CIH-SCH) CLKIN SYSCLK
Notes:
Min Pulse duration, XTAL2/CLKIN (see Note 2) Rise time, XTAL2/CLKIN Fall time, XTAL2/CLKIN Delay time, XTAL2/CLKIN rise to SYSCLK rise Crystal operating frequency Internal system clock operating frequency (see Note 3) 2 2 20
Max
Unit ns
30 30 100 5 5
ns ns ns MHz MHz
1) For VIL and VIH, refer to recommended operating conditions in Table 18-56. 2) This pulse can be either a high pulse, as illustrated in Figure 18-39, which extends from the earliest valid high to the final valid high in an XTAL2/CLKIN cycle or a low pulse, which extends from the earliest valid low to the final valid low in an XTAL2/CLKIN cycle. 3) SYSCLK = CLKIN/1
Figure 18-39. External Clock Timing for Divide-by-1 Clock
1 XTAL2/CLKIN 2 3 4 SYSCLK
18-66
TMS370Cx9xA Specifications
Table 18-60. Switching Characteristics and Timing Requirements (See Note)
No. 5 Parameter tc Cycle time, SYSCLK Divide-by-4 clock Divide-by-1 clock (PLL) 6 7
Note:
Min 200 200
Max 2 000 500
Unit ns ns ns
tw(SCL) tw(SCH)
Pulse duration, SYSCLK low Pulse duration, SYSCLK high
0.5tc - 20 0.5tc 0.5tc
0.5tc + 20 ns
tc = system-clock cycle time = 1 / SYSCLK
Figure 18-40. SYSCLK Timing
5 6
SYSCLK
7
Electrical Specifications and Timings
18-67
TMS370CxAxA Specifications
18.18 TMS370CxAxA Specifications
The tables in this section give specifications that apply to the devices in the TMS370CxAxA category. These devices include the TMS370C3A7A.
18.18.1 TMS370CxAxA Electrical Specifications
Stresses beyond those listed in Table 18-1 may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the recommended operating conditions in Table 18-61 is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Table 18-61. Recommended Operating Conditions (See Note 1)
Parameter VCC Supply voltage RAM data-retention supply voltage (see Note 2) VIL Low-level input voltage All pins except MC MC, normal operation VIH High-level input voltage All pins except MC, XTAL2 / CLKIN, and RESET XTAL2 / CLKIN RESET VMC TA MC (mode control) voltage Operating free-air temperature Microcomputer mode L version A version T version
Notes:
Min 4.5 3 VSS VSS 2 0.8VCC 0.7VCC VSS 0 -40 -40
Nom 5
Max 5.5 5.5 0.8 0.3 VCC VCC VCC 0.3 70 85 105
Unit V V V V V V V V C C C
1) Unless otherwise noted, all voltage values are with respect to VSS (ground). 2) RESET must be activated externally when VCC or SYSCLK is out of the recommended operating range.
18-68
TMS370CxAxA Specifications
Table 18-62. Electrical Characteristics Over Recommended Operating Free-Air Temperature Range
Parameter VOL VOH Low-level output voltage High-level output voltage Test Conditions IOL = 1.4 mA IOH = - 50 A IOH = - 2 mA II Input current
MC
Min
Typ
Max 0.4
Unit V V V
0.9VCC 2.4 10 650 10 1.4 -50 -2 30 20 7 10 8 2 6 2 2 45 30 11 17 11 3.5 8.6 3.0 30
0 V < VI 0.3 V 0.3 V < VI 13 V
A A A mA A mA mA mA mA mA mA mA mA mA A
I / O pins
0 V VI VCC VOL = 0.4 V VOH = 0.9VCC VOH = 2.4 V
IOL IOH
Low-level output current High-level output current
ICC
Supply current (operating mode) OSC POWER bit = 0 (see Note 3)
See Notes 2 and 3 SYSCLK = 5 MHz See Notes 2 and 3 SYSCLK = 3 MHz See Notes 2 and 3 SYSCLK = 0.5 MHz
ICC
Supply current (STANDBY mode) OSC POWER bit = 0 (see Note 4)
See Notes 2 and 3 SYSCLK = 5 MHz See Notes 2 and 3 SYSCLK = 3 MHz See Notes 2 and 3 SYSCLK = 0.5 MHz
ICC
Supply current (STANDBY mode) OSC POWER bit = 1 (see Note 5)
See Notes 2 and 3 SYSCLK = 3 MHz See Notes 2 and 3 SYSCLK = 0.5 MHz
ICC
Notes:
Supply current (HALT mode)
See Note 1 XTAL2 / CLKIN < 0.2 V
1) Single-chip mode, ports configured as inputs or as outputs with no load. All inputs 0.2 V or VCC - 0.2 V. 2) XTAL2/CLKIN is driven with an external square wave signal with 50% duty cycle and rise and fall times less than 10 ns. Current can be higher with a crystal oscillator. At 5-MHz SYSCLK, this extra current = 0.01 mA x (total load capacitance + crystal capacitance in pF). 3) Maximum operating current = 7.6(SYSCLK) + 7 mA. 4) Maximum standby current = 3(SYSCLK) + 2 mA (OSC POWER bit = 0). 5) Maximum standby current = 2.24(SYSCLK) + 1.9 mA (OSC POWER bit = 1; valid only up to 3-MHz SYSCLK).
Electrical Specifications and Timings
18-69
TMS370CxAxA Specifications
18.18.2 TMS370CxAxA Timings
Refer to Section 18.1 and Section 18.2 (both on page 18-2) for timing symbol definitions and parameter measurement points.
Table 18-63. External Clocking Requirements for Divide-by-4 Clock (see Note 1)
No. 1 2 3 4 Parameter tw(Cl) tr(Cl) tf(CI) td(CIH-SCL) CLKIN SYSCLK
Notes:
Min Pulse duration, XTAL2/CLKIN (see Note 2) Rise time, XTAL2/CLKIN Fall time, XTAL2/CLKIN Delay time, XTAL2/CLKIN rise to SYSCLK fall Crystal operating frequency Internal system clock operating frequency (see Note 3) 2 0.5 20
Max
Unit ns
30 30 100 20 5
ns ns ns MHz MHz
1) For VIL and VIH, refer to recommended operating conditions in Table 18-61. 2) This pulse can be either a high pulse, as illustrated in Figure 18-41, which extends from the earliest valid high to the final valid high in an XTAL2/CLKIN cycle, or a low pulse, which extends from the earliest valid low to the final valid low in an XTAL2/CLKIN cycle. 3) SYSCLK = CLKIN/4
Figure 18-41. External Clock Timing for Divide-by-4 Clock
1 XTAL2/CLKIN 2 3 4 SYSCLK
18-70
TMS370CxAxA Specifications
Table 18-64. External Clocking Requirements for Divide-by-1 Clock (PLL) (See Note 1)
No. 1 2 3 4 Parameter tw(Cl) tr(Cl) tf(CI) td(CIH-SCH) CLKIN SYSCLK
Notes:
Min Pulse duration, XTAL2/CLKIN (see Note 2) Rise time, XTAL2/CLKIN Fall time, XTAL2/CLKIN Delay time, XTAL2/CLKIN rise to SYSCLK rise Crystal operating frequency Internal system clock operating frequency (see Note 3) 2 2 20
Max
Unit ns
30 30 100 5 5
ns ns ns MHz MHz
1) For VIL and VIH, refer to recommended operating conditions in Table 18-61. 2) This pulse can be either a high pulse, as illustrated in Figure 18-42, which extends from the earliest valid high to the final valid high in an XTAL2/CLKIN cycle, or a low pulse, which extends from the earliest valid low to the final valid low in an XTAL2/CLKIN cycle. 3) SYSCLK = CLKIN/1
Figure 18-42. External Clock Timing for Divide-by-1 Clock
1 XTAL2/CLKIN 2 SYSCLK 3 4
Electrical Specifications and Timings
18-71
TMS370CxAxA Specifications
Table 18-65. Switching Characteristics and Timing Requirements (See Note)
No. 5 Parameter tc Cycle time, SYSCLK Divide-by-4 clock Divide-by-1 clock (PLL) 6 7
Note:
Min 200 200 0.5tc - 20 0.5tc
Max 2 000 500 0.5tc 0.5tc + 20
Unit ns ns ns ns
tw(SCL) tw(SCH)
Pulse duration, SYSCLK low Pulse duration, SYSCLK high
tc = system-clock cycle time = 1 / SYSCLK
Figure 18-43. SYSCLK Timing
5 6 SYSCLK 7
18-72
TMS370CxBxA Specifications
18.19 TMS370CxBxA Specifications
The tables in this section give specifications that apply to the devices in the TMS370CxBxA category. These devices include the TMS370C0B6A.
18.19.1 TMS370CxBxA Electrical Specifications
Stresses beyond those listed in Table 18-1 may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the recommended operating conditions in Table 18-66 is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Electrical Specifications and Timings
18-73
TMS370CxBxA Specifications
Table 18-66. Recommended Operating Conditions (See Note 1)
Parameter VCC1 Supply voltage RAM data-retention supply voltage (see Note 2) VCC2 Digital I/O supply voltage VCC3 Analog supply voltage VSS2 Digital I/O supply ground VSS3 Analog supply ground VIL Low-level input voltage High-level input voltage All pins except MC MC, normal operation VIH All pins except MC, XTAL2 / CLKIN, and RESET MC (non-WPO mode) XTAL2 / CLKIN RESET VMC MC (mode control) voltage (see Note 3) EEPROM write-protect override (WPO) mode Microprocessor mode Microcomputer mode TA Operating freeair temperature L version A version T version
Notes:
Min 4.5 3 4.5 4.5 - 0.3 - 0.3 VSS1 VSS1 2 VCC1 - 0.3 0.8VCC1 0.7VCC1 11.7 VCC1 - 0.3 VSS1 0 -40 -40
Nom 5
Max 5.5 5.5
Unit V V V V V V V V V
5 5 0 0
5.5 5.5 0.3 0.3 0.8 0.3 VCC1
VCC1 + 0.3 V VCC1 VCC1 12 13 VCC1 + 0.3 0.3 70 85 105 V V V V V C C C
1) Unless otherwise noted, all voltage values are with respect to VSS1. 2) RESET must be externally activated when VCC1 or SYSCLK is out of the recommended operating range. 3) The basic microcomputer and microprocessor operating modes are selected by the voltage level applied to the dedicated MC pin two system clock cycles (2tc) before RESET goes inactive (high). The WPO mode can be selected any time a sufficient voltage is present on MC.
You cannot use the internal connections between pins (for example, the connection between VSS1 and VSS2) for a jumper from one side of the chip to the other.
18-74
TMS370CxBxA Specifications
Table 18-67. Electrical Characteristics Over Recommended Operating Free-Air Temperature Range
Parameter VOL VOH II Low-level output voltage High-level output voltage Input current MC Test Conditions IOL = 1.4 mA IOH = - 50 A IOH = - 2 mA 0 V < VI 0.3 V 0.3 V < VI < VCC1 - 0.3 V VCC1 - 0.3 V VI VCC1 + 0.3 V VCC1 + 0.3 V < VI 13 V I / O pins IOL IOH ICC Low-level output current High-level output current Supply current (operating mode), OSC POWER bit = 0 (see Note 3) 0 V VI VCC1 VOL = 0.4 V VOH = 0.9VCC1 VOH = 2.4 V See Notes 1 and 2 SYSCLK = 5 MHz See Notes 1 and 2 SYSCLK = 3 MHz See Notes 1 and 2 SYSCLK = 0.5 MHz ICC Supply current (STANDBY mode), OSC POWER bit = 0 (see N ( Note 4) ) See Notes 1 and 2 SYSCLK = 5 MHz See Notes 1 and 2 SYSCLK = 3 MHz See Notes 1 and 2 SYSCLK = 0.5 MHz ICC Supply current (STANDBY mode), OSC POWER bit = 1 ( ) (see N Note 5) Supply current (HALT mode) See Notes 1 and 2 SYSCLK = 3 MHz See Notes 1 and 2 SYSCLK = 0.5 MHz See Note 1 XTAL2 / CLKIN < 0.2 V 1.4 -50 -2 35 25 13 12 8 2.5 6 2
2
Min 0.9VCC1 2.4
Typ
Max 0.4
Unit V V V
10 50 10 650 10
A A A A A mA A mA
56 36 18 17 11 3.5 8.6 3
30
mA mA mA mA mA mA mA mA A
ICC
Notes:
1) Single-chip mode, ports configured as inputs or as outputs with no load. All inputs 0.2 V or VCC1 - 0.2 V. 2) XTAL2/CLKIN is driven with an external square wave signal with 50% duty cycle and rise and fall times less than 10 ns. Current can be higher with a crystal oscillator. At 5-MHz SYSCLK, this extra current = 0.01 mA x (total load capacitance + crystal capacitance in pF). 3) Maximum operating current = 10(SYSCLK) + 5.8 mA. 4) Maximum standby current = 3(SYSCLK) + 2 mA (OSC POWER bit = 0). 5) Maximum standby current = 2.24(SYSCLK) + 1.9 mA (OSC POWER bit =1; valid only up to 3-MHz SYSCLK).
Electrical Specifications and Timings
18-75
TMS370CxBxA Specifications
18.19.2 TMS370CxBxA Timings
Refer to Sections 18.1 and 18.2 (both on page 18-2) for timing symbol definitions and parameter measurement information.
Table 18-68. External Clocking Requirements for Divide-by-4 Clock (See Note 1)
No. 1 2 3 4 Parameter tw(Cl) tr(Cl) tf(CI) td(CIH-SCL) CLKIN SYSCLK
Notes:
Min Pulse duration, XTAL2/CLKIN (see Note 2) Rise time, XTAL2/CLKIN Fall time, XTAL2/CLKIN Delay time, XTAL2/CLKIN rise to SYSCLK fall Crystal operating frequency Internal system clock operating frequency (see Note 3) 2 0.5 20
Max
Unit ns
30 30 100 20 5
ns ns ns MHz MHz
1) For VIL and VIH, refer to recommended operating conditions in Table 18-66. 2) This pulse can be either a high pulse, as illustrated in Figure 18-44, which extends from the earliest valid high to the final valid high in an XTAL2/CLKIN cycle, or a low pulse, which extends from the earliest valid low to the final valid low in an XTAL2/CLKIN cycle. 3) SYSCLK = CLKIN/4
Figure 18-44. External Clock Timing for Divide-by-4 Clock
1 XTAL2/CLKIN 2 3 4 SYSCLK
18-76
TMS370CxBxA Specifications
Table 18-69. External Clocking Requirements for Divide-by-1 Clock (PLL) (See Note 1)
No. 1 2 3 4 Parameter tw(Cl) tr(Cl) tf(CI) td(CIH-SCH) CLKIN SYSCLK
Notes:
Min Pulse duration, XTAL2/CLKIN (see Note 2) Rise time, XTAL2/CLKIN Fall time, XTAL2/CLKIN Delay time, XTAL2/CLKIN rise to SYSCLK rise Crystal operating frequency Internal system clock operating frequency (see Note 3) 2 2 20
Max
Unit ns
30 30 100 5 5
ns ns ns MHz MHz
1) For VIL and VIH, refer to recommended operating conditions in Table 18-66. 2) This pulse can be either a high pulse, as illustrated in Figure 18-45, which extends from the earliest valid high to the final valid high in an XTAL2/CLKIN cycle, or a low pulse, which extends from the earliest valid low to the final valid low in an XTAL2/CLKIN cycle. 3) SYSCLK = CLKIN/1
Figure 18-45. External Clock Timing for Divide-by-1 Clock
1 XTAL2/CLKIN 2 3 4 SYSCLK
Electrical Specifications and Timings
18-77
TMS370CxBxA Specifications
Table 18-70. Switching Characteristics and Timing Requirements (See Note)
No. 5 Parameter tc tw(SCL) tw(SCH) Cycle time, SYSCLK Divide-by-4 clock Divide-by-1 clock (PLL) 6 7
Note:
Min 200 200 0.5tc - 25 0.5tc
Max 2 000 500 0.5tc 0.5tc + 20
Unit ns ns ns ns
Pulse duration, SYSCLK low Pulse duration, SYSCLK high
tc = system clock cycle time = 1 / SYSCLK
Figure 18-46. SYSCLK Timing
7 5 6 SYSCLK
18-78
TMS370CxCxA Specifications
18.20 TMS370CxCxA Specifications
The tables in this section give specifications that apply to the devices in the TMS370CxCxA category. These devices include the TMS370C3C0A, TMS370C6C2A and SE370C6C2A.
18.20.1 TMS370CxCxA Electrical Specifications
Stresses beyond those listed in Table 18-1 may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the recommended operating conditions in Table 18-71 is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Table 18-71. Recommended Operating Conditions (See Note 1)
Parameter VCC Supply voltage RAM data-retention supply voltage (see Note 2) VIL Low-level input voltage All pins except MC MC, normal operation VIH High-level input voltage All pins except MC, XTAL2 / CLKIN, and RESET XTAL2 / CLKIN RESET VMC MC (mode control) voltage EPROM programming voltage (VPP) Microcomputer mode TA Operating free-air temperature L version A version T version
Notes:
Min 4.5 3 VSS VSS 2 0.8VCC 0.7VCC 13 VSS 0 -40 -40
Nom 5
Max 5.5 5.5 0.8 0.3 VCC VCC VCC
Unit V V V V V V V V V C C C
13.2
13.5 0.3 70 85 105
1) Unless otherwise noted, all voltage values are with respect to VSS (ground). 2) RESET must be activated externally when VCC or SYSCLK is out of the recommended operating range.
Electrical Specifications and Timings
18-79
TMS370CxCxA Specifications
Table 18-72. Electrical Characteristics Over Recommended Operating Free-Air Temperature Range
Parameter VOL VOH II Low-level output voltage High-level output voltage Input current MC Test Conditions IOL = 1.4 mA IOH = - 50 A IOH = - 2 mA 0 V VI 0.3 V 0.3 V < VI 13 V 12 V VI 13 V (see Note 1) I / O pins IOL IOH ICC Low-level output current High-level output current Supply current (operating mode) OSC POWER bit = 0 (see Note 4) 0 V VI VCC VOL = 0.4 V VOH = 0.9VCC VOH = 2.4 V See Notes 2 and 3 SYSCLK = 5 MHz See Notes 2 and 3 SYSCLK = 3 MHz See Notes 2 and 3 SYSCLK = 0.5 MHz ICC Supply current (STANDBY mode) OSC POWER bit = 0 (see Note 5) See Notes 2 and 3 SYSCLK = 5 MHz See Notes 2 and 3 SYSCLK = 3 MHz See Notes 2 and 3 SYSCLK = 0.5 MHz ICC Supply current (STANDBY mode) OSC POWER bit = 1 (see Note 6) See Notes 2 and 3 SYSCLK = 3 MHz See Notes 2 and 3 SYSCLK = 0.5 MHz ICC
Notes:
Min
Typ
Max 0.4
Unit V V V
0.9VCC 2.4 10 650 50 10 1.4 -50 -2 20 13 5 10 6.5 2 4.5 1.5 1 36 25 11 17 11 3.5 8.6 3.0 30
A A mA A mA A mA mA mA mA mA mA mA mA mA A
Supply current (HALT mode)
See Note 2 XTAL2 / CLKIN < 0.2 V
1) Input current IPP is a maximum of 50 mA only when EPROM is being programmed. 2) Single-chip mode, ports configured as inputs or as outputs with no load. All inputs 0.2 V or VCC - 0.2 V. 3) XTAL2/CLKIN is driven with an external square wave signal with 50% duty cycle and rise and fall times less than 10 ns. Current can be higher with a crystal oscillator. At 5 MHz SYSCLK, this extra current = 0.01 mA x (total load capacitance + crystal capacitance in pF). 4) Maximum operating current = 5.6(SYSCLK) + 8 mA. 5) Maximum standby current = 3(SYSCLK) + 2 mA (OSC POWER bit = 0). 6) Maximum standby current = 2.24(SYSCLK) + 1.9 mA (OSC POWER bit = 1; valid only up to 3-MHz SYSCLK).
18-80
TMS370CxCxA Specifications
18.20.2 TMS370CxCxA Timings
Refer to Sections 18.1 and 18.2 (both on page 18-2)) for timing symbol definitions and parameter measurement points.
Table 18-73. External Clocking Requirements for Divide-by-4 Clock (See Note 1)
No. 1 2 3 4 Parameter tw(Cl) tr(Cl) tf(CI) td(CIH-SCL) CLKIN SYSCLK
Notes:
Min Pulse duration, XTAL2/CLKIN (see Note 2) Rise time, XTAL2/CLKIN Fall time, XTAL2/CLKIN Delay time, XTAL2/CLKIN rise to SYSCLK fall Crystal operating frequency Internal system clock operating frequency (see Note 3) 2 0.5 20
Max
Unit ns
30 30 100 20 5
ns
ns ns MHz MHz
1) For VIL and VIH, refer to recommended operating conditions in Table 18-71. 2) This pulse can be either a high pulse, as illustrated in Figure 18-47, which extends from the earliest valid high to the final valid high in an XTAL2/CLKIN cycle, or a low pulse, which extends from the earliest valid low to the final valid low in an XTAL2/CLKIN cycle. 3) SYSCLK = CLKIN/4
Figure 18-47. External Clock Timing for Divide-by-4 Clock
1 XTAL2/CLKIN 2 3 4 SYSCLK
Electrical Specifications and Timings
18-81
TMS370CxCxA Specifications
Table 18-74. External Clocking Requirements for Divide-by-1 Clock (PLL) (See Note 1)
No. 1 2 3 4 Parameter tw(Cl) tr(Cl) tf(CI) td(CIH-SCH) CLKIN SYSCLK
Notes:
Min Pulse duration, XTAL2/CLKIN (see Note 2) Rise time, XTAL2/CLKIN Fall time, XTAL2/CLKIN Delay time, XTAL2/CLKIN rise to SYSCLK rise Crystal operating frequency Internal system clock operating frequency (see Note 3) 2 2 20
Max
Unit ns
30
30
ns ns ns MHz MHz
100 5 5
1) For VIL and VIH, refer to recommended operating conditions in Table 18-71. 2) This pulse can be either a high pulse, as illustrated in Figure 18-48, which extends from the earliest valid high to the final valid high in an XTAL2/CLKIN cycle, or a low pulse, which extends from the earliest valid low to the final valid low in an XTAL2/CLKIN cycle. 3) SYSCLK = CLKIN/1
Figure 18-48. External Clock Timing for Divide-by-1 Clock
1 XTAL2/CLKIN 2 SYSCLK 3 4
18-82
TMS370CxCxA Specifications
Table 18-75. Switching Characteristics and Timing Requirements (See Note)
No. 5 Parameter tc Cycle time, SYSCLK Divide-by-4 clock Divide-by-1 clock (PLL) 6 7
Note:
Min 200 200 0.5tc - 20 0.5tc
Max 2 000 500 0.5tc 0.5tc + 20
Unit ns ns ns ns
tw(SCL) tw(SCH)
Pulse duration, SYSCLK low Pulse duration, SYSCLK high
tc = system clock cycle time = 1 / SYSCLK
Figure 18-49. SYSCLK Timing
5 6 SYSCLK 7
Electrical Specifications and Timings
18-83
SCI Timings
18.21 SCI Timings
This section contains timing tables and figures for devices that have the serial communications interface (SCI) module. Note: Parameter Difference
The td(SCCL-TXDV) parameter differs for TMS370Cxxx devices. Refer to subsection A.9.2 on page A-9.
Table 18-76. SCI Isosynchronous Mode Timing Characteristics and Requirements for Internal Clock (See Note)
No. 24 25 26 27 28 29 30 Parameter tc(SCC) tw(SCCL) tw(SCCH) td(SCCL-TXDV) tv(SCCH-TXD) tsu(RXD-SCCH) tv(SCCH-RXD) Cycle time, SCICLK Pulse duration, SCICLK low Pulse duration, SCICLK high Delay time, SCITXD valid after SCICLK low Valid time, SCITXD data valid after SCICLK high Setup time, SCIRXD to SCICLK high Valid time, SCIRXD data valid after SCICLK high Min 2tc tc - 45 tc - 45 -50 tw(SCCH) - 50 0.25 tc + 145 0 Max 131 072tc Unit ns
0.5tc(SCC) + 45 ns 0.5tc(SCC) + 45 ns 60 ns ns ns ns
Note:
tc = system clock cycle time = 1 / SYSCLK
Figure 18-50. SCI Isosynchronous Mode Timing for Internal Clock
24 26 25 SCICLK 28 27 SCITXD 29 30 SCIRXD Data Valid Data Valid
18-84
SCI Timings
Table 18-77. SCI Isosynchronous Mode Timing Characteristics and Requirements for External Clock (See Note)
No. 31 32 33 34 35 36 37
Note:
Parameter tc(SCC) tw(SCCL) tw(SCCH) td(SCCL-TXDV) tv(SCCH-TXD) tsu(RXD-SCCH) tv(SCCH-RXD) Cycle time, SCICLK Pulse duration, SCICLK low Pulse duration, SCICLK high Delay time, SCITXD valid after SCICLK low Valid time, SCITXD data valid after SCICLK high Setup time, SCIRXD to SCICLK high Valid time, SCIRXD data after SCICLK high
Min 10tc 4.25tc + 120 tc + 120
Max
Unit ns ns ns
4.25tc + 145 ns tw(SCCH) 40 2tC ns ns ns
tc = system clock cycle time = 1 / SYSCLK
Figure 18-51. SCI Isosynchronous Mode Timing for External Clock
31 33 32 SCICLK 35 34 SCITXD 36 37 SCIRXD Data Valid Data Valid
Electrical Specifications and Timings
18-85
SPI Timings
18.22 SPI Timings
This section contains timing tables and diagrams for the devices that have the serial peripheral interface (SPI) module in the following categories: TMS370Cx1x, TMS370Cx2x, TMS370Cx36, TMS370Cx5x, and TMS370Cx6x. Note: Electrical/Timing Specification Differences
Some SPI electrical specifications and timings differ for TMS370Cxxx devices. Refer to subsection A.9.2 on page A-9.
Table 18-78. SPI Master Mode External Timing Characteristics and Requirements (See Note)
No. 38 39 40 41 42 43 44 Parameter tc(SPC)M tw(SPCL)M tw(SPCH)M td(SPCL-SIMOV)M tv(SPCH-SIMO)M tsu(SOMI-SPCH)M tv(SPCH-SOMI)M Cycle time, SPICLK Pulse duration, SPICLK low Pulse duration, SPICLK high Delay time, SPISIMO valid after SPICLK low (polarity = 1) Valid time, SPISIMO after SPICLK high (polarity =1) Setup time, SPISOMI to SPICLK high (polarity = 1) Valid time, SPISOMI after SPICLK high (polarity = 1) Min 2tc tc - 45 tc - 55 - 65 tw(SPCH) - 50 0.25 tc + 150 0 Max 256tc 0.5tc(SPC) + 45 0.5tc(SPC) + 45 50 Unit ns ns ns ns ns ns ns
Note:
tc = system clock cycle time = 1 / SYSCLK
18-86
SPI Timings
Figure 18-52. SPI Master Mode External Clock Timing
38 40 39 SPICLK 41 SPISIMO 43 44 SPISOMI Data Valid Data Valid 42
Note:
In this figure, polarity = 1. SPICLK is inverted when polarity = 0.
Electrical Specifications and Timings
18-87
SPI Timings
Table 18-79. SPI Slave Mode External Timing Characteristics and Requirements (See Note)
No. 45 46 47 48 49 50 51 tc(SPC)S tw(SPCL)S tw(SPCH)S Cycle time, SPICLK Pulse duration, SPICLK low Pulse duration, SPICLK high Min 8tc 4tc - 45 4tc - 45 Max Unit ns 0.5tc(SPC)S + 45 ns 0.5tc(SPC)S + 45 ns 3.25tc + 130 tw(SPCH)S 0 3tc + 100 ns ns ns ns
td(SPCL-SOMIV)S Delay time, SPISOMI valid after SPICLK low (polarity = 1) tv(SPCH-SOMI)S Valid time, SPISOMI after SPICLK high (polarity =1)
tsu(SIMO-SPCH)S Setup time, SPISIMO to SPICLK high (polarity = 1) tv(SPCH-SIMO)S Valid time, SPISIMO after SPICLK high (polarity = 1)
Note:
tc = system clock cycle time = 1 / SYSCLK
Figure 18-53. SPI Mode Slave External Timing
45 47 46 SPICLK 48 SPISIMO 50 51 SPISOMI
Notes:
49 Data Valid
Data Valid
1) In this figure, polarity = 1. SPICLK is inverted when polarity = 0. 2) As a slave, the SPICLK pin is used as the input for the serial clock, which is supplied from the network master.
18-88
Analog-to-Digital Converter 1 (ADC1) Module Specifications
18.23 Analog-to-Digital Converter 1 (ADC1) Module Specifications
This section contains specifications for the devices that have the analog-todigital converter 1 (ADC1) module in the following categories: TMS370Cx32, TMS370Cx36, TMS370Cx4x, TMS370Cx5x, TMS370Cx6x, TMS370Cx7x and TMS370CxBx. The ADC1 module has a separate power bus for its analog circuitry. These pins are referred to as VCC3 and VSS3. The purpose is to enhance ADC1 performance by preventing digital switching noise of the logic circuitry that may be present on VSS and VCC from coupling into the ADC1 analog stage. All ADC1 specifications are given with respect to VSS3 unless otherwise noted.
Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-bits (256 values) Monotonic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Yes Output conversion code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 00h to FFh (00h for VI VSS3; FFh for VI Vref) Conversion time (excluding sample time) . . . . . . . . . . . . . . . . . . . . . . . 164 tc (where tc = system clock cycle time)
Table 18-80. Recommended Operating Conditions
Parameter VCC3 Analog supply voltage Min 4.5 VCC - 0.3 VSS3 Analog ground Vref Non-VCC3 reference (see Note) Analog input for conversion
Note:
Nom 5
Max 5.5 VCC + 0.3 VSS + 0.3
Unit V V V V V
VSS - 0.3 2.5 VSS3 VCC3
VCC3 + 0.1 Vref
Vref must be stable, within 1/2 LSB of the required resolution, during the entire conversion time. VCC = VCC1 and VSS = VSS1 for 'x32, 'x36, 'x5x, 'x6x, 'x7x, and 'xBx devices.
Electrical Specifications and Timings
18-89
Analog-to-Digital Converter 1 (ADC1) Module Specifications
Table 18-81. ADC1 Electrical Characteristics Over Recommended Operating Free-Air Temperature Range
Parameter Absolute accuracy (see Note 1) Differential/integral linearity error (see Notes 1 and 2) ICC3 Analog supply current Test Conditions VCC3 = 5.5 V, Vref = 5.1 V VCC3 = 5.5 V, Vref = 5.1 V Converting Nonconverting II Iref Zref Input current, AN0 - AN7 input charge current Source impedance of Vref SYSCLK 3 MHz 3 MHz < SYSCLK 5 MHz
Notes:
Min
Max 1.5 0.9 2 5 2 1 24 10
Unit LSB LSB mA A A mA k k
0 V VI 5.5 V
1) Absolute resolution = 20 mV. At Vref = 5 V, this is one LSB. As Vref decreases, LSB size decreases. Therefore, the absolute accuracy and differential/integral linearity errors in terms of LSBs increase. 2) Excluding quantization error of 1/2 LSB
The ADC1 module allows complete freedom in design of the sources for the analog inputs. The period of the sample time is user-defined so that high-impedance sources can be accommodated without penalty to low-impedance sources. The sample period begins when the SAMPLE START bit of the ADC1 control register (ADCTL.6) is set to 1. The end of the signal sample period occurs when the conversion bit (CONVERT START, ADCTL.7) is set to 1. After a hold time, the converter resets the SAMPLE START and CONVERT START bits, signaling that a conversion has started and that the analog signal can be removed.
18-90
Analog-to-Digital Converter 1 (ADC1) Module Specifications
Table 18-82. Analog Timing Requirements
Parameter tsu(S) th(AN) tw(S)
Note:
Min 0 18tc 1
Max
Unit ns ns s/k
Setup time, analog to sample command Hold time, analog input from start of conversion Pulse duration, sample time per kilohm of source impedance (see Note)
The value given is valid for a signal with a source impedance > 1 k. If the source impedance is < 1 k, use a minimum sampling time of 1 s.
Figure 18-54. Analog Timing
Analog Stable Analog In tsu(S) Sample Start th(AN) tw(S) Convert Start
Electrical Specifications and Timings
18-91
Analog-to-Digital Converter 2 (ADC2) Module Specifications
18.24 Analog-to-Digital Converter 2 (ADC2) Module Specifications
This section contains specifications for the TMS370CxCx device category, which has the analog-to-digital converter 2 (ADC2) module. ADC2 shares the VCC power bus for its analog and digital circuitry. All ADC2 specifications are given with respect to VSS unless otherwise noted. Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-bits (256 values) Monotonic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Yes Output conversion code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 00h to FFh (00h for VI VSS ; FFh for VI Vref) Conversion time (excluding sample time) . . . . . . . . . . . . . . . . . . . . . . . 164 tc (where tc = system clock cycle time)
Table 18-83. Recommended Operating Conditions
Parameter VCC Vref Analog supply voltage Non-VCC reference (see Note) Analog input for conversion
Note:
Min 4.5 2.5 VSS
Nom 5 VCC
Max 5.5 VCC + 0.1 Vref
Unit V V V
Vref must be stable, within 1/2 LSB of the required resolution during the entire conversion time.
Table 18-84. ADC2 Electrical Characteristics Over Recommended Operating Free-Air Temperature Range
Parameter Absolute accuracy (see Note 1) Differential/integral linearity error (see Notes 1 and 2) ICC Analog supply current Test Conditions VCC = 5.5 V, Vref = 5.1 V VCC = 5.5 V, Vref = 5.1 V Converting Nonconverting II Iref Zref Input current, AN0-AN3 Input charge current Source impedance of Vref SYSCLK 3 MHz 3 MHz < SYSCLK 5 MHz
Notes:
Min
Max +1.5
Unit LSB LSB mA A A mA k k
0.9
2 5 2 1 24 10
0 V VI 5.5 V
1) Absolute resolution = 20 mV. At Vref = 5 V, this is 1 LSB. As Vref decreases, LSB size decreases and thus absolute accuracy and differential / integral linearity errors in terms of LSBs increases. 2) Excluding quantization error of 1/2 LSB
18-92
Analog-to-Digital Converter 2 (ADC2) Module Specifications
The ADC2 module allows complete freedom in design of the sources for the analog inputs. The period of the sample time is user-defined so that high-impedance sources can be accommodated without penalty to low-impedance sources. The sample period begins when the SAMPLE START bit of the ADC2 control register (ADCTL.6) is set to 1. The end of the signal sample period occurs when the conversion bit (CONVERT START, ADCTL.7) is set to 1. After a hold time, the converter resets the SAMPLE START and CONVERT START bits, signaling that a conversion has started and the analog signal can be removed.
Table 18-85. Analog Timing Requirements
Parameter tsu(S) th(AN) tw(S)
Note:
Min 0 18tc 1
Max
Unit ns ns s/k
Setup time, analog input to sample command Hold time, analog input from start of conversion Pulse duration, sample time per kilohm of source impedance (see Note)
The value given is valid for a signal with a source impedance > 1 k. If the source impedance is < 1 k, use a minimum sampling time of 1 s.
Figure 18-55. Analog Timing
Analog Stable Analog In
tsu(S) Sample Start th(AN) tw(S) Convert Start
Electrical Specifications and Timings
18-93
Analog-to-Digital Converter 3 (ADC3) Module Specifications
18.25 Analog-to-Digital Converter 3 (ADC3) Module Specifications
This section contains specifications for the TMS370Cx9x device category, which has the analog-to-digital converter 3 (ADC3) module. The ADC3 module has a separate power bus for its analog circuitry. These pins are referred to as VCC3 and VSS3. The purpose is to enhance ADC3 performance by preventing digital switching noise of the logic circuitry that may be present on VSS and VCC from coupling into the ADC3 analog stage. All ADC3 specifications are given with respect to VSS3 unless otherwise noted.
Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-bits (256 values) Monotonic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Yes Output conversion code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 00h to FFh (00h for VI VSS3 ; FFh for VI Vref) Conversion time (excluding sample time) . . . . . . . . . . . . . . . . . . . . . . . 164 tc (where tc = system clock cycle time)
Table 18-86. Recommended Operating Conditions
Parameter VCC3 Analog supply voltage Min 4.5 VCC - 0.3 VSS3 Analog input ground Vref Non-VCC3 reference (see Note) Analog input for conversion
Note:
Nom 5
Max 5.5 VCC + 0.3 VSS + 0.3
Unit V V V V V
VSS - 0.3 2.5 VSS3 VCC3
VCC3 + 0.1 Vref
Vref must be stable, within 1/2 LSB of the required resolution during the entire conversion time.
18-94
Analog-to-Digital Converter 3 (ADC3) Module Specifications
Table 18-87. ADC3 Electrical Characteristics Over Recommended Operating Free-Air Temperature Range
Parameter Absolute accuracy (see Note 1) Differential/integral linearity error (see Notes 1 and 2) ICC3 Analog supply current Test Conditions VCC3 = 5.5 V, Vref = 5.1 V VCC3 = 5.5 V , Vref = 5.1 V Converting Nonconverting II Iref Zref Input current, AN0 - AN14 Input charge current Source impedance of Vref SYSCLK 3 MHz 3 MHz < SYSCLK 5 MHz
Notes:
Min
Max 1.5 0.9 2 5 2 1 24 10
Unit LSB LSB mA A A mA k k
0 V VI 5.5 V
1) Absolute resolution = 20 mV. At Vref = 5 V, this is 1 LSB. As Vref decreases, LSB size decreases; therefore, the absolute accuracy and differential/integral linearity errors in terms of LSBs increase. 2) Excluding quantization error of 1/2 LSB
The ADC3 module allows complete freedom in design of the sources for the analog inputs. The period of the sample time is user-defined so that high-impedance sources can be accommodated without penalty to low-impedance sources. The sample period begins when the SAMPLE START bit of the ADC3 control register (ADCTL.6) is set to 1. The end of the signal sample period occurs when the conversion bit (CONVERT START, ADCTL.7) is set to 1. After a hold time, the converter resets the SAMPLE START and CONVERT START bits, signaling that a conversion has started and the analog signal can be removed.
Electrical Specifications and Timings
18-95
Analog-to-Digital Converter 3 (ADC3) Module Specifications
Table 18-88. Analog Timing Requirements
Parameter tsu(S) th(AN) tw(C) tw(S) Setup time, analog to sample command Hold time, analog input from start of conversion (see Note 2) Conversion time (see Note 2) Pulse duration, sample time per kilohm of source impedance (see Note 1) Min 0 (N+2)tc (10N + 4)tc 1 Max Unit ns ns ns s / k
Notes:
1) The value given is valid for a signal with a source impedance > 1 k. If the source impedance is < 1 k, use a minimum sampling time of 1s. 2) N = 16, 8, 4, or 2 upon selected conversion rate.
Figure 18-56. Analog Timing
Analog In Stable Analog In tsu(S) Sample Time tsu(S)
th(AN)
tw(S) Convert Time
tw(C)
18-96
Running Title--Attribute Reference
Chapter 19
Customer Information
This chapter includes general information on mask-ROM prototyping, TMS370 physical characteristics, and parts ordering.
Topic
Page
19.1 Mask-ROM Prototype and Production Flow . . . . . . . . . . . . . . . . . . . . 19-2 19.2 Mechanical Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-6 19.3 TMS370 Family Numbering and Symbol Conventions . . . . . . . . . . 19-16 19.4 Ordering Information for Development Support Tools . . . . . . . . . . 19-25
Chapter Title--Attribute Reference
19-1
Mask-ROM Prototype and Production Flow
19.1 Mask-ROM Prototype and Production Flow
The TMS370 family includes many mask-ROM microcontrollers. The ROM is manufactured containing your application code. The custom-programmed nature of these devices requires a standard, defined interface between you and the factory during production. The prototype and production flow is described in the following steps. 1) Customer-required information. For TI to accept the receipt of your ROM algorithm, you must follow these steps: a) Complete and submit a new code release form (NCRF--available from a TI Field Sales Office and shown in Example 19-1, page 19-5) describing the custom features of the device (for example, customer information, prototype and production quantities and dates, any exceptions to standard electrical specifications, part numbers and symbols, package type, etc.). b) If you requested nonstandard specifications on the NCRF, submit a copy of the description of the microcontroller that includes the functional description and electrical specifications (including absolute maximum ratings, recommended operating conditions, and timing values). TI will then respond to the requested specification changes. c) When you have developed and verified your code with the development system, submit the object file in one of the following formats: Intel Hex, TI-Tagged, or COFF (generated by TMS370 development system). Acceptable media include the following:
J J J J
Modem transfer: PC-to-PC via Xmodem, Ymodem, or Zmodem protocol or Microstuf's CROSSTALK XVI protocol DOS-formatted 3-1/2-inch high-density disk EPROM devices (currently TMS27C256, and TMS27C512) supported: TMS27C128,
TMS370 EPROM devices (OTP and reprogrammable--refer to Table 17-1 on page 17-27)
Send the completed NCRF, purchase order, customer specification (if required), and ROM code to the local representative or to the nearest field sales office. 2) TI performs ROM receipt. Code review and ROM receipt is performed on your code, and a unique manufacturing ROM code number (such as R1501234FN) is assigned to your algorithm. All future correspondence should indicate this number. During the ROM receipt procedure, TI:
-
Reads the ROM code information.
19-2
Mask-ROM Prototype and Production Flow
Notes:
Processes the ROM code information, including writing identification information into the reserved locations. Reproduces your ROM object code on the media that you requested on the NCRF. (Note: You must provide the EPROM device if that is the type of media that you have requested on the NCRF.) Returns the processed code and the original code for your verification.
-
All TMS370 family devices contain mask-ROM space reserved for TI use only. This space includes addresses 7FE0h through 7FEBh. This reserved area should not be used in your software algorithm, nor should it be used during mask-ROM/firmware development. The reserved location contents are changed only by TI. Data EEPROM locations are not programmed in the standard production flow.
3) Customer ROM receipt approval. Verify that the ROM code received and processed by TI is correct and that no information was misinterpreted in the transfer. Next, return an algorithm approval form (available from the field sales office) to verify the correct ROM receipt or resubmit the code for processing. This written verification constitutes the contractual agreement for creating the custom mask and manufacturing the ROM verification prototype units. 4) TI orders masks; manufactures and ships 25 prototypes. TI generates the prototype photomasks and processes, manufactures, and tests 25 microcontroller prototypes containing your ROM pattern. TI then ships the prototypes to you for ROM code verification; these microcontroller devices have been made using the custom mask but are for the purposes of ROM verification only. 5) Customer prototype approval. Verify the operation of these prototypes in the system and respond with written approval or disapproval. Written approval constitutes the contractual agreement to initiate volume microcontroller production using the verified prototype ROM code. 6) Customer release to production. With your algorithm approval, the ROM code is released to production. TI begins shipping production devices (with production lead time) according to your final specification and order requirements.
Customer Information
19-3
Mask-ROM Prototype and Production Flow
Figure 19-1 illustrates the standard of prototype/production.
Figure 19-1. Prototype and Production Flow
Customer submits ROM code Customer submits NCRF & PO Customer submits microcontroller spec (if required)
TI performs ROM receipts
TI evaluates spec exceptions; returns Print Evaluation and Acceptance Form (PEAF)
No
Customer No ROM receipt approval ? Yes TI orders masks; manufactures and ships 25 prototypes
No
Customer No prototype approval ? Yes Customer release to production
TI ships production devices
Two lead times are quoted in reference to the preceding flow. For the latest lead times, contact the nearest TI field sales office.
19-4
Prototype lead time is the elapsed time from the receipt of written ROM receipt verification to the delivery of 25 prototype devices. Production lead time is the elapsed time from the receipt of written customer prototype approval to delivery of production devices.
Example 19-1 shows a sample new code release form.
Mask-ROM Prototype and Production Flow
Example 19-1. New Code Release Form
NEW CODE RELEASE FORM TEXAS INSTRUMENTS TMS370 MICROCONTROLLER PRODUCTS DATE:
To release a new customer algorithm to TI incorporated into a TMS370 family microcontroller, complete this form and submit with the following information: 1. A ROM description in object form on Floppy Disk, Modem XFR, or EPROM (Verification file will be returned via same media) 2. An attached specification if not using TI standard specification as incorporated in TI's applicable device data book. Company Name: Street Address: Street Address: City: Customer Part Number: Customer Application: TMS370 Device: TI Customer ROM Number: (provided by Texas Instruments) OSCILLATOR FREQUENCY MIN [] External Drive (CLKIN) [] Crystal [] Ceramic Resonator TYP MAX
CONTACT OPTIONS FOR THE 'A' VERSION TMS370 MICROCONTROLLERS
Contact Mr./Ms.: Phone: ( State Zip
)
Ext.:
Customer Purchase Order Number: Customer Print Number *Yes: # No: (Std. spec to be followed) *If Yes: Customer must provide "print" to TI w/NCRF for approval before ROM code processing starts.
Low Power Modes [] Enabled [] Disabled
Watchdog counter [] Standard [] Hard Enabled [] Simple Counter
Clock Type [] Standard (/4) [] PLL (/1)
[] Supply Voltage MIN: (std range: 4.5V to 5.5V)
MAX:
NOTE: Non 'A' version ROM devices of the TMS370 microcontrollers will have the "Low power modes Enabled", "Divide-by-4" Clock, and "Standard" Watchdog options. See the TMS370 Family User's Guide (literature number SPNU127) or the TMS370 Family Data Manual (literature number SPNS014B). PACKAGE TYPE [] 'N' 28-pin PDIP [] "FN" 44-pin PLCC [] "FN" 28-pin PLCC [] "FN" 68-pin PLCC [] "N" 40-pin PDIP [] "NM" 64-pin PSDIP [] "NJ" 40-pin PSDIP (formerly known as N2) BUS EXPANSION [] YES [] NO
TEMPERATURE RANGE [] 'L': 0C to 70C (standard) [] 'A': -40C to 85C [] 'T': -40C to 105C SYMBOLIZATION [] TI standard symbolization [] TI standard w/customer part number [] Customer symbolization (per attached spec, subject to approval)
NON-STANDARD SPECIFICATIONS: ALL NON-STANDARDS SPECIFICATIONS MUST BE APPROVED BY THE TI ENGINEERING STAFF: If the customer requires expedited production material (i.e., product which must be started in process prior to prototype approval and full production release) and non-standard spec issues are not resolved to the satisfaction of both the customer and TI in time for a scheduled shipment, the specification parameters in question will be processed/tested to the standard TI spec. Any such devices which are shipped without conformance to a mutually approved spec, will be identified by a 'P' in the symbolization preceding the TI part number. RELEASE AUTHORIZATION: This document, including any referenced attachments, is and will be the controlling document for all orders placed for this TI custom device. Any changes must be in writing and mutually agreed to by both the customer and TI. The prototype cycletime commences when this document is signed off and the verification code is approved by the customer. 1. Customer: Date: 2. TI: Field Sales: Marketing: Prod. Eng.: Proto. Release:
Customer Information
19-5
Mechanical Package Information
19.2 Mechanical Package Information
The TMS370 microcontroller family devices are assembled in six package types according to the type of material and outline used for the package. These package types are:
-
Plastic dual-in-line package (PDIP) Plastic shrink dual-in-line package (PSDIP) Plastic leaded chip carrier (PLCC) Ceramic dual-in-line package (CDIP) Ceramic shrink dual-in-line package (CSDIP) Ceramic leaded chip carrier (CLCC)
Package types are designated by the suffix on the ROM code number for devices manufactured with your ROM code (for example, R1501234FN) and by the suffix of the standard device number for devices with EPROM. Table 19-1 indicates the package type, suffix indicator, and family members supported on that package type. The various package types are shown in Figure 19-2 through Figure 19-9 as listed below:
Figure 19-2 19-3 19-4 19-5 19-6 19-7 19-8 19-9 Title Plastic Dual-In-Line Package (N Suffix) 40-Pin Plastic Shrink Dual-In-Line Package (NJ Suffix) 64-Pin Plastic Shrink Dual-In-Line Package, 70-mil Pin Spacing (NM Suffix) Plastic-Leaded Chip Carrier Package (FN Suffix) Ceramic Shrink (Side-Braze) Dual-In-Line Package (JD Suffix) 40-Pin Ceramic Shrink (Side-Braze) Dual-In-Line Package (JC Suffix) 64-Pin Ceramic Shrink Dual-In-Line Package (JN Suffix) Ceramic-J-Leaded Chip Carrier Package (FZ Suffix) Page 19-8 19-9 19-10 19-11 19-12 19-13 19-14 19-15
19-6
Mechanical Package Information
Table 19-1.
Package Type
Package Types and Associated Family Members
Suffix Indicator N JD FN FZ N NJ JD JC FN FZ NM JN FN FZ Family Members TMS370Cx1x and TMS370CxCx SE370C712 and SE370C6C2 TMS370Cx0x, TMS370Cx1x, and TMS370CxCx SE370C702, SE370C712, and SE370C6C2 TMS370Cx2x, TMS370Cx4x, TMS370C080, and TMS370C3A7 TMS370Cx2x, TMS370Cx4x, and TMS370Cx9x SE370C722 and SE370C742 SE370C722, SE370C742, and SE370C792 TMS370Cx2x, TMS370Cx3x, TMS370Cx4x, TMS370Cx8x, and TMS370Cx9x SE370C722, SE370C732, SE370C736, SE370C742, SE370C686, and SE370C792 TMS370Cx5x, TMS370Cx7x, and TMS370C0B6 SE370C756, SE370C758, SE370C759, and SE370C777 TMS370Cx5x, TMS370Cx6x, TMS370Cx7x, and TMS370C0B6 SE370C756, SE370C758, SE370C759, SE370C768, SE370C769, and SE370C777
28-pin plastic DIP (100-mil pin spacing) 28-pin ceramic DIP (100-mil pin spacing) 28-pin PLCC (50-mil pin spacing) 28-pin CLCC (50-mil pin spacing) 40-pin plastic DIP (100-mil pin spacing) 40-pin plastic shrink DIP (70-mil pin spacing) 40-pin ceramic DIP (100-mil pin spacing) 40-pin ceramic shrink DIP (70-mil pin spacing) 44-pin PLCC (50-mil pin spacing) 44-pin CLCC (50-mil pin spacing) 64-pin plastic shrink DIP (70-mil pin spacing) 64-pin ceramic shrink DIP (70-mil pin spacing) 68-pin PLCC (50-mil pin spacing) 68-pin CLCC (50-mil pin spacing)
The NJ designator for the 40-pin plastic shrink DIP package was formerly known as N2. The mechanical drawing of the NJ is identical to the N2 package and did not need to be requalified.
Customer Information
19-7
Mechanical Package Information
Figure 19-2. Plastic Dual-In-Line Package (N Suffix)
N (R-PDIP-T**)
A 24 13
Plastic Dual-In-Line Package
24 pin device shown
0.560 (14,22) 0.520 (13,21)
1 0.060 (1,52) typ
12 0.200 (5,08) max 0.020 (0,51) min 0.610 (15,49) 0.590 (14,99)
Seating plane
0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.010 (0,25)
M
0.125 (3,18) min 0.010 (0,25) nom
0- 15
PIns Dim A Max A MIN
24
28
32
40
48
52
1.270 1.450 1.650 2.090 2.450 2.650 (32,26) (36,83) (41,91) (53,09) (62,23) (67,31) 1.230 1.410 1.610 2.040 2.390 2.590 (31,24) (35,81) (40,89) (51,82) (60,71) (65,79)
Unshaded values are part of the applicable TMS370 families.
Notes:
1) All linear dimensions are in inches (millimeters). 2) Falls within JEDEC MS-011 3) Falls within JEDEC MS-015 (32 pin only) 4) This drawing is subject to change without notice.
19-8
Mechanical Package Information
Figure 19-3. 40-Pin Plastic Shrink Dual-In-Line Package (NJ Suffix)
NJ (R-PDIP-T**)
A 40 21 Pins 40 1.425 (36,20) 54 2.031 (51,60)
Plastic Shrink Dual-In-Line Package
40 pin device shown
Dim 0.560 (14,22) max
A Max
Unshaded values are part of the applicable TMS370 families. 1 0.048 (1,216) 0.032 (0,816) 0.200 (5,08) max 0.020 (0,51) min 0.600 (15,24) 20
Seating plane
0.070 (1,78) 0.022 (0,56) 0.014 (0,36) 0.010 (0,25)
M
0.125 (3,18) MIN
0- 15 0.010 (0,25) nom
Notes:
1) Each pin centerline is located within 0,26 (0.010) of its true longitudinal position. 2) All linear dimensions are in inches (millimeters). 3) This drawing is subject to change without notice.
Customer Information
19-9
Mechanical Package Information
Figure 19-4. 64-Pin Plastic Shrink Dual-In-Line Package, 70-mil Pin Spacing (NM Suffix)
NM (R-PDIP-T64)
2.280 (57,91) max 64 33
Plastic Shrink Dual-In-Line Package
0.680 (17,27) 0.670 (17,02)
1 0.048 (1,216) 0.032 (0,816)
32
0.222 (5,64) max 0.020 (0,51) min 0.760 (19,30) 0.740 (18,80)
Seating plane
0.070 (1,78) 0.022 (0,56) 0.014 (0,36) 0.010 (0,25)
M
0.125 (3,18) min
0- 15 0.010 (0,25) nom
Notes:
1) All linear dimensions are in inches (millimeters). 2) This drawing is subject to change without notice.
19-10
Mechanical Package Information
Figure 19-5. Plastic-Leaded Chip Carrier Package (FN Suffix)
FN (S-PQCC-J**) Plastic J-Leaded Chip Carrier
20 pin device shown Seating plane 0.004 (0,10) D D1 3 1 19 0.032 (0,81) 0.026 (0,66) 4 18 D2 / E2 0.180 (4,57) max 0.120 (3,05) 0.090 (2,29) 0.020 (0,51) min
E
E1 D2 / E2 8 14
9
13
0.050 (1,27) 0.008 (0,20) nom
0.021 (0,53) 0.013 (0,33) 0.007 (0,18) M
D/E No. of Pins 20 28 44 52 68 84 Min 0.385 (9,78) Max 0.395 (10,03) Min
D1 / E1 Max 0.356 (9,04) Min
D2 / E2 Max 0.169 (4,29) 0.219 (5,56) 0.319 (8,10) 0.369 (9,37)
0.350 (8,89)
0.141 (3,58) 0.191 (4,85)
0.485 (12,32) 0.495 (12,57) 0.450 (11,43) 0.456 (11,58)
0.685 (17,40) 0.695 (17,65) 0.650 (16,51) 0.656 (16,66) 0.291 (7,39) 0.785 (19,94) 0.795 (20,19) 0.750 (19,05) 0.756 (19,20) 0.341 (8,66)
0.985 (25,02) 0.995 (25,27) 0.950 (24,13) 0.958 (24,33) 0.441 (11,20) 0.469 (11,91) 1.185 (30,10) 1.195 (30,35) 1.150 (29,21) 1.158 (29,41) 0.541 (13,74) 0.569 (14,45)
Unshaded values are part of the applicable TMS370 families.
Notes:
1) All linear dimensions are in inches (millimeters). 2) Falls within JEDEC MS-018 3) This drawing is subject to change without notice.
Customer Information
19-11
Mechanical Package Information
Figure 19-6. Ceramic (Side-Braze) Dual-In-Line Package (JD Suffix)
JD (R-CDIP-T**)
A 24 13
Ceramic Side-Braze Dual-In-Line Package
24 pin device shown
0.590 (15,00) typ Pins Dim A Max 1 0.065 (1,65) 0.045 (1,14) 12
24
28
40
48
52
1.250 1.450 2.050 2.435 2.650 (31,75) (36,83) (52,07) (61,85) (67,31)
Unshaded values are part of the applicable TMS370 families.
0.075 (1,91) max 4 places
0.175 (4,45) 0.140 (3,56)
0.620 (15,75) 0.590 (14,99)
Seating plane 0.020 (0,51) min 0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.125 (3,18) min 0- 15 0.012 (0,30) 0.008 (0,20)
Notes:
1) All linear dimensions are in inches (millimeters). 2) This package can be hermetically sealed with a metal lid. 3) The terminals are gold plated. 4) This drawing is subject to change without notice.
19-12
Mechanical Package Information
Figure 19-7. 40-Pin Ceramic Shrink (Side-Braze) Dual-In-Line Package (JC Suffix)
JC (R-CDIP-T40) Ceramic Side-Braze Dual-In-Line Package
1.414 (35,92) 1.386 (35,20) 40 21
0.600 (15,24) 0.580 (14,73)
1
20 0.032 (0,81) typ
0.093 (2,38) 0.077 (1,96)
0.060 (1,52) 0.040 (1,02) Seating plane
0.610 (15,49) 0.590 (14,99)
0.020 (0,51) 0.016 (0,41) 0.070 (1,78) 1.335 (33,91) 1.325 (33,66)
0.175 (4,46) typ
0.012 (0,31) 0.009 (0,23)
Notes:
1) All linear dimensions are in inches (millimeters). 2) This package can be hermetically sealed with a metal lid. 3) The terminals are gold plated. 4) This drawing is subject to change without notice.
Customer Information
19-13
Mechanical Package Information
Figure 19-8. 64-Pin Ceramic Shrink Dual-In-Line Package (JN Suffix)
JN (R-CDIP-T64)
2.424 (61,57) 2.376 (60,35) 64 33
Ceramic Dual-In-Line Package
0.750 (19,05) 0.730 (18,54)
1 0.040 (1,02) typ
32
0.094 (2,39) 0.078 (1,98) 0.060 (1,52) 0.040 (1,02) Seating plane 0.088 (2,24) 0.072 (1,83) 0.020 (0,51) 0.016 (0,41) 0.070 (1,78) See Note 3 2.178 (55,32) 2.162 (54,91) 0.175 (4,45) typ 0.012 (0,31) 0.009 (0,23) 0.760 (19,30) 0.740 (18,80)
Notes:
1) All linear dimensions are in inches (millimeters). 2) Each pin centerline located within 0.010 (0,26) of it true longitudinal position. 3) This drawing is subject to change without notice.
19-14
Mechanical Package Information
Figure 19-9. Ceramic-J-Leaded Chip Carrier Package (FZ Suffix)
FZ (S-CQCC-J**) J-Leaded Ceramic Chip Carrier
28 lead device shown 0.040 (1,02)
45
A B 4 1 26
Seating Plane 0.180 (4,57) 0.155 (3,94) 0.140 (3,55) 0.120 (3,05)
0.050 (1,27)
5
25
A
B
0.032 (0,81) 0.026 (0,66)
C (at Seating Plane) 0.020 (0,51) 0.014 (0,36)
11
19
12
18
0.025 (0,64) R TYP
0.040 (1,02) MIN 0.120 (3,05) 0.090 (2,29)
JEDEC OUTLINE MO-087AA MO-087AB MO-087AC MO-087AD
NO. OF PINS** 28 44 52 68 MIN 0.485 (12,32) 0.685 (17,40) 0.785 (19,94) 0.985 (25,02)
A MAX 0.495 (12,57) 0.695 (17,65) 0.795 (20,19) 0.995 (25,27) MIN 0.430 (10,92) 0.630 (16,00) 0.730 (18,54) 0.930 (23,62)
B MAX 0.455 (11,56) 0.655 (16,64) 0.765 (19,43) 0.955 (24,26) MIN 0.410 (10,41) 0.610 (15,49) 0.680 (17,28) 0.910 (23,11)
C MAX 0.430 (10,92) 0.630 (16,00) 0.740 (18,79) 0.930 (23,62)
Notes:
1) All linear dimensions are in inches (millimeters). 2) This package can be hermetically sealed with a ceramic lid using glass frit. 3) This drawing is subject to change without notice.
Customer Information
19-15
TMS370 Family Numbering and Symbol Conventions
19.3 TMS370 Family Numbering and Symbol Conventions
All TMS370 devices are marked with information as to the type, package, copyright date(s), place of manufacture, and manufacturing data.
19.3.1 Production Device Prefix Designators
To help you identify the development stage of a product, Texas Instruments assigns a prefix designator: TMX, TMP, or TMS. These prefixes represent the evolutionary stages of product development from engineering prototypes through fully qualified production devices. Figure 19-10 depicts this evolutionary development flowchart.
Figure 19-10. Development Flowchart
TMXxxxx
Experimental devices that may not be representative of the final device's electrical specifications and have not completed reliability verification.
TMPxxxx
Devices that conform to the electrical specifications but have not completed quality and reliability verification. Fully qualified production devices. Production devices shipped by TI have the TMS designator signifying that they have demonstrated the high standards of Texas Instruments quality and reliability.
TMSxxxx
-
TMX devices are shipped against the following disclaimer:
J J J
Experimental product and its reliability has not been characterized. Product is sold "as is." Product is not warranted to be exemplary of final production version if or when released by Texas Instruments.
-
TMP devices are shipped against the following disclaimer:
J J
Customer understands that the product purchased here under has not been fully characterized and the expectation of reliability cannot be defined; therefore, Texas Instruments standard warranty refers only to the device's specifications. No warranty of merchantability or fitness is expressed or implied.
19-16
TMS devices have been fully characterized and the quality and reliability of the device has been fully demonstrated. Texas Instruments standard warranty applies.
TMS370 Family Numbering and Symbol Conventions
19.3.2 Support Device Prefix Designators
The SE prefix designation is given to the system evaluator devices that are used for prototyping purposes. This designation applies only to the prototype members of the TMS370 family (SE370C702, SE370C712, SE370C722, SE370C732, SE370C736, SE370C742, SE370C756, SE370C758, SE370C759, SE370C768, SE370C769, SE370C777, SE370C686, SE370C792, and SE370C6C2). SE devices are shipped against the following disclaimer:
Development products are intended for internal evaluation purposes only.
19.3.3 Device Numbering Conventions
Figure 19-11 illustrates the numbering and symbol nomenclature for the TMS370 family.
19.3.4 Device Symbols
Table 19-2 lists the graphic and letter designators for the symbolization.
Customer Information
19-17
TMS370 Family Numbering and Symbol Conventions
Figure 19-11. TMS370 Family Number and Symbol Nomenclature
TMS 370 C 7 1 2 A FN T
Prefix TMS TMP TMX SE Qualified Preproduction Experimental/Prototype System evaluator (reprogrammable) Temperature Range L 0 to 70 degrees C A -40 to 85 degrees C T -40 to 105 degrees C Package Type Pkg No. Pins Type CDIP 28/40 CLCC 28/44/68 CSDIP 40 CSDIP 64 PDIP 28/40 PLCC 28/44/68 PSDIP 40 PSDIP 64
Family
Microcontroller
Technology
CMOS
TI Code JD FZ JC JN N FN NJ NM
Memory Type No. Type 0 ROM and EEPROM 1 ROMless 2 ROMless and EEPROM 3 ROM 4 Secured-memory ROM and EEPROM 6 EPROM 7 EPROM and EEPROM Base Product: External No. Mem T1 0 1 2 3 4 5 6 7 8 9 A B C
Contact Options For ROM: A Clock, power mode, and watchdog selected at ROM code
For ROMless A Standard watchdog and /4 OSC, low-power enable For EPROM: A Standard watchdog and /4 OSC, low-power enable
B Hard watchdog and /1 PLL, low-power enable
Extra T2A T2B SCI SPI ADC PIO PACT Pins SCI1 28 28 SCI1 40/44 ADC1 44 SCI1 ADC1 40/44 SCI1 ADC1 64/68 SCI1 ADC1 68 ADC1 64/68 40/44 ADC3 40/44 SCI1 40 ADC1 64/68 SCI2 ADC2 28
None: Standard watchdog and /4 OSC, low-power enable Program Memory Size No. Size 0 4K 1 2K 2 8K 3 12K 6 16K 7 24K 8 32K 9 48K
Extra peripheral I/O For base product no. 3: TMS370Cx32 has no SPI; TMS370Cx36 has SPI. NJ package was formerly designated as N2.
19-18
TMS370 Family Numbering and Symbol Conventions
Table 19-2. Symbolization Designators
Letter Designator and Name Description This is the standard TI signature. 12345678901 Example
a) b)
Texas Instruments trademark
Optional customer part You can specify a one-line number that will appear number on your mask-ROM device:
-
28-pin PLCC: you can have 11 characters. 44-pin PLCC: you can have 12 characters. 68-pin PLCC: you can have 15 characters. 64-pin PSDIP: you can have 21 characters. 28- or 40-pin PDIP or 40-pin PSDIP: you can have 23 characters. R1x00xxxN
c)
Customer's ROM code On mask-ROM devices, you will find up to a ten-digit and package type number that TI assigns. This number is unique to the device that you ordered. Standard number device part This is the TMS- part number on OTP devices.
d) e) f)
TMS370CxxxxNT SE370CxxxxFZT WAYYWW
Evaluation device part This is the SE- evaluation part number on repronumber grammable EPROM devices. Tracking mark and date This six-character code denotes the date and place code of the device assembly. W stands for the wafer fabrication plant, A represents the device revision, and YY and WW stand for the year and week the device was assembled. TI microcode copyright ROM code copyright Lot code EIA code If your device has only one copyright date, it is that of the TI microcode. If your device has more than one copyright date, the second copyright date is that of the ROM code. This eight-digit number designates the wafer lot. This code is an alternate to the TI signature. It denotes that the device is a TI device. You must use either the EIA code or the TI trademark on your custom-programmed devices. This is the TI site at which the part was assembled. This designation may appear on the backside of the part. This seven-character code denotes the year, month, assembly lot , and assembly site code place of the device assembly. YM stands for year and month, LLLL represents the assembly lot, and W stands for the assembly site code.
g) h) i) j)
E1986TI E1995TI
12345678 980
k)
Assembly site
Philippines
l)
Lot trace code
YMLLLLW
m)
Wafer fab lot and die W represents wafer fab lot and A represents the die revision revision.
WA
Customer Information
19-19
TMS370 Family Numbering and Symbol Conventions
19.3.5 Symbolization by Device
The device symbolization of the TMS370 family members can be divided into two main categories:
-
On Page devices with factory-programmed mask-ROM devices with user-programmed memory: - OTP (one-time programmable) EPROM - reprogrammable EPROM 19-20 19-22 19-23
TMS370 family members with mask-ROM
Family members with mask-ROM are custom-programmed devices in which the ROM is mask programmed according to your application code. These devices follow the prototyping and production flow outlined in Section 19.1. Since they are semicustom devices, they receive a unique ROM code identification number. Figure 19-12 through Figure 19-18 illustrate typical labels for mask-ROM devices. Refer to Table 19-2, for the key to the lettered designators.
Figure 19-12. Typical Symbolization for 28-pin PLCC Mask-ROM Devices
Line 1: Line 2: Line 3: Line 4: Line 5: (b) (c) R1x00xxxFN (g) (c)1986TI (l) 48ADUXW (m) WF
Figure 19-13. Typical Symbolization for 44-pin PLCC Mask-ROM Devices
Line 1: Line 2: Line 3: Line 4: Line 5: (b) (g) (c)1986TI (c) R1x00xxxFN (l) 48ADUXW (m) WA
Figure 19-14. Typical Symbolization for 68-pin PLCC Mask-ROM Devices
Line 1: Line 2: Line 3: Line 4: (b) (g) (c)1986TI (c) R1x00xxxFN (m) WA (l) 48ADUXW
19-20
TMS370 Family Numbering and Symbol Conventions
Figure 19-15. Typical Symbolization for 28-pin PDIP Mask-ROM Devices
Line 1: Line 2: Line 3: Line 4: (g) (c)1986TI (i) 12345678 (b) (c) R1x00xxxN (h) (c)1995TI (k) USA (f) WAYYWW
Figure 19-16. Typical Symbolization for 40-pin PDIP Mask-ROM Devices
Line 1: Line 2: Line 3: Line 4: (g) (c)1986TI (i) 12345678 (b) (c) R1x00xxxN (h) (c)1995TI (k) USA (f) WAYYWW
Figure 19-17. Typical Symbolization for 40-pin PSDIP Mask-ROM Devices
Line 1: Line 2: Line 3: Line 4: (g) (c)1986TI (b) (c) R1x00xxxNJ (h) (c)1995TI (m) WA
(l) YMLLLLW
Figure 19-18. Typical Symbolization for 64-pin PSDIP Mask-ROM Devices
Line 1: Line 2: Line 3: Line 4: (g) (c)1986TI (i) 12345678 (b) (c) R1x00xxxNM (h) (c)1995TI (f) WAYYWW
Customer Information
19-21
TMS370 Family Numbering and Symbol Conventions
TMS370 family members with program EPROM (OTP)
Family members with program EPROM (OTP) are standard device types and have a standard identification. The TMS370 family members with program EPROM include the TMS370C6xx and TMS370C7xx. Figure 19-19 through Figure 19-23 illustrate typical labels for OTP devices. Refer to Table 19-2, on page 19-19, for the key to the lettered designators.
Figure 19-19. Typical Symbolization for 28-pin PLCC Program EPROM Devices (OTP)
Line 1: Line 2: Line 3: Line 4: Line 5: (d) TMS (d) 370CxxxxFNT (g) (c)1986TI (I) 59ADUXW (m) WF
Figure 19-20. Typical Symbolization for 44-pin PLCC Program EPROM Devices (OTP)
Line 1: Line 2: Line 3: Line 4: (g) (c)1986TI (d) TMS370CxxxxFNT (I) 59ADUXW (m) WF
Figure 19-21. Typical Symbolization for 68-pin PLCC Program EPROM Devices (OTP)
Line 1: Line 2: Line 3: (g) (c)1986TI (d) TMS370CxxxxFNT (m) WA (I) 59ADUXW
Figure 19-22. Typical Symbolization for 28-pin PDIP Program EPROM Devices (OTP)
Line 1: Line 2: Line 3: Line 4: (d) TMS370CxxxxNT (f) WAYYWW (g) (c)1986TI (k) USA
(i) 12345678
Figure 19-23. Typical Symbolization for 40-pin PDIP Program EPROM Devices (OTP)
Line 1: Line 2: Line 3: Line 4: (d) TMS370CxxxxNT (f) WAYYWW (g) (c)1986TI (k) USA
(i) 12345678
Figure 19-24. Typical Symbolization for 40-pin PSDIP EPROM Devices (OTP)
Line 1: Line 2: Line 3: (d) TMS370CxxxxNJT (g) (c)1986TI (m) WA
(l) YMLLLLW
19-22
TMS370 Family Numbering and Symbol Conventions
Figure 19-25. Typical Symbolization for 64-pin PSDIP Reprogrammable EPROM Devices
Line 1: Line 2: Line 3: (g) (c)1986TI (m) WA (d) TMS370CxxxxNMT (f) WAYYWW
TMS370 family members with reprogrammable EPROM
Family members with reprogrammable EPROM are standard device types and have a standard identification. The TMS370 family members with program EPROM include the SE370Cxxxx. Figure 19-26 through Figure 19-30 illustrate typical labels for reprogrammable EPROM devices. Refer to Table 19-2, on page 19-19, for the key to the lettered designators.
Figure 19-26. Typical Symbolization for 28-pin and 40-pin CDIP Reprogrammable EPROM Devices
Line 1: Line 2: Line 3: Line 4: Line 5: (e) SE (e) 370CxxxxJDT (f) WAYYWW (g) (c)1986TI (i) 12345678 (j) 980
(k) USA
Figure 19-27. Typical Symbolization for 40-pin CSDIP Reprogrammable EPROM Devices
Line 1: Line 2: Line 3: Line 4: Line 5: (e) SE (e) 370CxxxxJCT (f) WAYYWW (g) (c)1986TI (i) 12345678 (j) 980
(k) USA
Figure 19-28. Typical Symbolization for 64-pin CSDIP Reprogrammable EPROM Devices
Line 1: Line 2: Line 3: Line 4: Line 5: (e) SE (e) 370CxxxxJNT (f) WAYYWW (g) (c)1986TI (i) 12345678
(k) USA
Customer Information
19-23
TMS370 Family Numbering and Symbol Conventions
Figure 19-29. Typical Symbolization for 44-pin and 68-pin CLCC Reprogrammable EPROM Devices
Line 1: Line 2: Line 3: Line 4: Line 5: Line 6: Line 7: Line 8: Line 8: (e) SE370CxxxxFZT (j) 980 (i) 4 (f) W (i) 2 (f) A (i) 6 (f) Y (i) 9 (f) Y (i) 0 (f) W (i) 2 (i) 3 (k) USA (g) (c)1986TI
Figure 19-30. Typical Symbolization for 28-pin CLCC Reprogrammable EPROM Devices
Line 1: Line 2: Line 3: Line 4: Line 5: Line 6: (e) SE (e) 370CxxxxFZT (j) 980 (f) WAYYWW (i) 12345678 (g) (c)1986TI (k) USA
19-24
Ordering Information for Development Support Tools
19.4 Ordering Information for Development Support Tools
The following development tools are available from TI.
19.4.1 TMS370 Macro Assembler, Linker, C Compiler, and Utilities
These software packages include all of the utilities required for developing object code for the TMS370 devices. Part Number TMDS3740850-02 TMDS3740855-02 TMDS3740555-09 Description Assembler/Linker (DOS version) C Compiler with Assembler/Linker (DOS version) C Compiler with Assembler/Linker (Sun and HP700 versions)
19.4.2 TMS370 Design Kit
The TMS370 design kit contains the necessary software and hardware for you to evaluate TMS370Cx0x, TMS370Cx1x, and TMS370Cx5x devices. Part Number TMDS3770110 Description TMS370 Design Kit
19.4.3 TMS370 Starter Kit
The TMS370 starter kit contains the necessary software and hardware for you to evaluate TMS370Cx0x, TMS370Cx1x, TMS370Cx2x, TMS370Cx32, TMS370Cx4x, TMS370Cx5x, TMS370Cx6x, TMS370Cx7x, TMS370CxAx, and TMS370CxBx devices; an Assembler diskette is included in the kit. Part Number TMDS37000 Description TMS370 Starter Kit
Customer Information
19-25
Ordering Information for Development Support Tools
19.4.4 TMS370 Microcontroller Programmer
With the TMS370 microcontroller programmer, you can program the TMS370 prototype devices. Each programmer comes with the necessary cables and control software for interfacing with a PC. Part Number TMDS3760500A TMDS3780510A TMDS3780511A TMDS3780512A TMDS3780513A TMDS3780514A Description TMS370 Programmer Base Unit (requires top) TMS370 Single-Unit 28- , 44- , and 68-pin PLCC (adapter top only) TMS370 Single-Unit 28- and 40-pin DIP, and 40- and 64-pin PSDIP (adapter top only) TMS370 Single-Unit 44-pin PLCC for TMS370Cx36 (adapter top only) TMS370 Single-Unit 44-pin PLCC/40-pin SDIP for TMS370Cx9x (adapter top only) TMS370 Single-Unit 28-pin PLCC/DIP for TMS370CxCx (adapter top only)
19.4.5 TMS370 XDS Systems
The XDS system provides software debugging and overall evaluation of a TMS370-based system. The XDS comes complete with necessary cables and the debugging program (not available in Europe). Part Number TMDS3762210 TMDS3788828 TMDS3788844 TMDS3788868 Description TMS370 XDS/22 Emulator--110 VAC (target cables sold separately) 28-pin DIP/PLCC Target Cable ('x1x) 40-pin DIP/SDIP, 44-pin PLCC Target Cable ('x2x and 'x4x) 64-pin SDIP, 68-pin PLCC Target Cable ('x5x)
19.4.6 TMS370 Compact Development Tool
The CDT370 includes a debugger, an assembler/linker, and the CDT board. Part Number EDSCDT370 Description TMS370 Compact Development Tool for 'Cx0x, 'Cx1x, 'Cx2x, 'Cx4x, 'Cx5x, 'Cx8x, 'CxAx, and 'CxCx (target cables sold separately) TMS370 Compact Development Tool timer for 'Cx6x, 'Cx7x, and 'CxBx (target cables sold separately) TMS370 Compact Development Tool PACT for 'Cx32, 'Cx36, and 'Cx9x (target cables sold separately)
EDSCDT37T EDSCDT37P
19-26
Ordering Information for Development Support Tools
28-pin PLCC Target Cable ('Cx0x devices) 28-pin DIP Target Cable ('Cx1x devices) 28-pin PLCC Target Cable ('Cx1x devices) 40-pin DIP Target Cable ('Cx2x devices) 40-pin SDIP Target Cable ('Cx2x devices) 44-pin PLCC Target Cable ('Cx2x devices) 44-pin PLCC Target Cable ('Cx32 devices) 44-pin PLCC Target Cable ('Cx36 devices) 40-pin SDIP Target Cable ('Cx4x devices) 40-pin DIP Target Cable ('Cx4x devices) 44-pin PLCC Target Cable ('Cx4x devices) 68-pin PLCC Target Cable ('Cx5x, 'Cx6x, 'Cx7x, and 'CxBx) EDSTRG64SDIL 64-pin SDIP Target Cable ('Cx5x, 'Cx7x, and 'CxBx) EDSTRG40DIL8X 40-pin DIP Target Cable ('Cx8x devices) EDSTRG44PLCC8X 44-pin PLCC Target Cable ('Cx8x devices) EDSTRG40SDIL05 40-pin SDIP Target Cable ('Cx9x devices) EDSTRG44PLCC05 44-pin PLCC Target Cable ('Cx9x devices) EDSTRG40DILAX 40-pin DIP Target Cable ('CxAx devices) EDSTRG28DILCX 28-pin DIP Target Cable ('CxCx devices) EDSTRG28PLCCCX 28-pin PLCC Target Cable ('CxCx devices)
EDSTRG28PLCC02 EDSTRG28DIL EDSTRG28PLCC EDSTRG40DILX EDSTRG40SDILX EDSTRG44PLCCX EDSTRG44PLCC32 EDSTRG44PLCC36 EDSTRG40SDIL EDSTRG40DIL EDSTRG44PLCC EDSTRG68PLCC
19.4.7 TMS370 Converter Socket
The 40-pin TMS370C080 and TMS370C3A7 ROM devices rely on the 68-pin TMS370C758 device (with 32K EPROM) with a converter socket for field testing or software development. Part Number TMDS37788OTP Description Converter socket
19.4.8 XDS Target Connectors
For additional or replacement XDS target connectors, contact the TI factory repair department.
Customer Information
19-27
19-28
Running Title--Attribute Reference
Appendix A Appendix A
Differences Among the TMS370CxxxA, TMS370C7xxB, and TMS370Cxxx Devices (Contact Options)
The TMS370 family of microcontroller devices have been revised to include features that enhance performance and enable new application technologies. The specifications and descriptions included in this manual apply to the TMS370CxxxA and TMS370C7xxB devices. This appendix describes how the TMS370CxxxA and TMS370C7xxB devices differ from the TMS370Cxxx devices:
Topic
A.1 A.2 A.3 A.4 A.5 A.6 A.7 A.8 A.9
Page
Watchdog (WD) Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2 Clock Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-3 Low-Power and Idle Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-4 Timer 1 Control Register 2 (T1CTL2) Bits . . . . . . . . . . . . . . . . . . . . . . . A-5 System Control and Configuration Register 2 (SCCR2) Bits . . . . . . A-5 AP Bit in the DEECTL Register (DEECTL.2) . . . . . . . . . . . . . . . . . . . . . A-6 Program EPROM Control Register (EPCTLx) . . . . . . . . . . . . . . . . . . . . A-7 VCC1 and VCC2 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-7 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-8
A.10 Summary of Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-11
Chapter Title--Attribute Reference
A-1
Watchdog (WD) Options
A.1 Watchdog (WD) Options
As described in Section 7.7, on page 7-21, you can configure the WD timer for the TMS370CxxxA devices as one of three mask options to accommodate various applications:
-
A standard WD for ROMless, EPROM, and mask-ROM devices. This option lets you configure the WD timer as a non-WD or as a WD. A hard WD for mask-ROM devices. In this configuration, you can operate the WD timer only as a WD, providing additional system integrity. A simple counter for mask-ROM devices. In this configuration, you can use the WD timer as an event counter, a pulse accumulator, or an interval timer (similar to the non-WD mode in the standard WD configuration).
These WD options are summarized in Table A-1.
Table A-1. WD Option Summary for TMS370CxxxA Devices
Standard WD Option WD OVRFL TAP SEL bit and WD INPUT SELECT0-2 bits WD Mode Once the WD OVRFL RST ENA is set, these bit values can be changed only after any system reset. Non-WD Mode These bits can be changed at any time, as long as WD OVRFL RST ENA is not set. Hard WD These WD bit values can be changed at any time, even if WD OVRFL RST ENA bit is set. However, the WD INPUT SELECT2 bit is not available. No Simple Counter Once the WD OVRFL RST ENA is set, these bit values can be changed only after any system reset.
Generates an interrupt when the WD counter overflows Generates a system reset WD OVRFL RST ENA bit
No
Yes (If enabled) No Select to be a nonWD. If bit = 0, WD counter does not initiate reset upon overflow.
Yes (If enabled) No If bit = 0, WD bits and WD OVRFL TAP SELECT are not locked. If bit = 1, WD bits and WD OVRFL TAP SELECT are locked.
Yes Select to be a WD. If bit = 1, WD counter does initiate a reset upon overflow. This bit is cleared by any system reset.
Yes This bit is ignored.
INT1 operation during low-power modes Available WD clock resources
Controlled by INT1 ENABLE bit (INT1.0) and INT1 NMI bit (SCCR2.1). 8 options: - No clock - Event - Pulse accumulator - SYSCLK - 4 prescalers All devices
Controlled by INT1 ENABLE bit (INT1.0) and INT1 NMI bit (SCCR2.1). 8 options: - No clock - Event - Pulse accumulator - SYSCLK - 4 prescalers All devices
Automatically enabled as an NMI upon entry to a low-power mode. 4 options: - SYSCLK/4 - SYSCLK/16 - SYSCLK/64 - SYSCLK/256 Mask-ROM devices
Controlled by INT1 ENABLE bit (INT1.0) and INT1 NMI bit (SCCR2.1). 8 options: - No clock - Event - Pulse accumulator - SYSCLK - 4 prescalers Mask-ROM devices
Available devices
A-2
Watchdog (WD) Options/Clock Options
For the TMS370C7xxA devices (EPROM only), the only WD option is the standard WD (refer to Table A-3 on page A-4). For the TMS370C7xxB devices (EPROM only), the only WD option is the hard WD mode (refer to Table A-3). For the TMS370Cxxx devices (ROMless, mask-ROM, and EPROM), the only WD option is the standard WD. In this mode, you can set the WD OVRFL RST ENA bit (T1CTL2.7) to configure the WD timer as a WD, or clear the WD OVRFL RST ENA bit to configure the WD timer as a non-WD (refer to Table A-3).
A.2 Clock Options
For the TMS370CxxxA devices, the clock options are ROMless, ROM, and EPROM dependent. Clock options for ROM devices are configured through a programmable contact during manufacture. These clock options are summarized in Table A-2. (Refer to Table A-3, on page A-4.)
Table A-2. Clock Option Summary for TMS370CxxxA Devices
Option SYSCLK range Available Devices Divide-by-4 (Standard Oscillator) 0.5 MHz to 5 MHz All devices Divide-by-1 (Phase-Locked Loop) 2 MHz to 5MHz Mask-ROM devices
For the TMS370C7xxB devices (EPROM only), the only clock option is the divide-by-1 (PLL). (Refer to Table A-3). For the TMS370Cxxx devices (ROMless, mask-ROM, and EPROM), the only clock option is the divide-by-4 (standard oscillator). (Refer to Table A-3).
Differences Among the TMS370CxxxA, TMS370C7xxB, and TMS370Cxxx Devices (Contact Options)
A-3
Low-Power and Idle Modes
A.3 Low-Power and Idle Modes
For the TMS370CxxxA devices (ROMless, mask-ROM, and EPROM), there are two low-power modes (halt and standby) and an idle mode. Bits 6 and 7 of SCCR2 select the halt, standby, or idle modes. For mask-ROM devices, lowpower modes can be disabled permanently through a programmable contact at the time when the mask is manufactured. Low-power modes for EPROM and ROMless devices can be disabled or enabled through software only and cannot be disabled permanently through a mask option. Refer to Section 4.2, page 4-7 for more information about the low-power and idle modes. For the TMS370C7xxB (EPROM only) and TMS370Cxxx (ROMless, maskROM, and EPROM) devices, the low-power modes cannot be disabled permanently. (Refer to Table A-3).
Table A-3. Summary for TMS370CxxxA, TMS370C7xxB, and TMS370Cxxx Devices
OPTIONS WD, Clock, & Low-power L Mode Original Rev. TMS370C6xx TMS370C7xx SE370C6xx SE370C7xx Yes EPROM Revision A TMS370C6xxA TMS370C7xxA SE370C6xxA SE370C7xxA Yes Yes Revision B TMS370C7xxB SE370C7xxB Original Rev. TMS370C0xx TMS370C3xx ROM Revision A TMS370C0xxA TMS370C3xxA TMS370C4xxA ROMLESS Original Rev. TMS370C1xx TMS370C2xx Revision A TMS370C1xxA TMS370C2xxA
Standard WD Hard WD Simple Counter Divide-by-1 Divide-by-4 Low-power mode
Yes
Selected through contact option ti
Yes
Yes
Yes Yes Software configurable Yes Software configurable Software configurable Yes Software configurable
Selected through contact option Contact option enable/disable
Yes Software configurable
Yes Software configurable
Low-power mode can be enabled or disabled through software. Refer to Table 4-3, on page 4-7, for the powerdown/idle control bits. Standard WD, hard WD, and simple counter options are available for ROM with revision A. One of these options must be specified when the devices are ordered. Divide-by-1 and divide-by-4 options are avilable for ROM with revision A. One of these options must be specified when the devices are ordered. When ordering a device, low power must be specified to be enabled or disabled permanently through a programmable contact.
A-4
Timer 1 Control Register 2 (T1CTL2) Bits/System Control and Configuration Register 2 (SCCR2) Bits
A.4 Timer 1 Control Register 2 (T1CTL2) Bits
Two of the T1CTL2 bits (register T1CTL2 shown in subsection 7.9.2 on page 7-34) operate differently according to which WD contact option you are using:
-
WD OVRFL INT FLAG bit (T1CTL2.5): For the TMS370CxxxA and TMS370C7xxB devices, this bit is set if the last reset is initiated by the WD counter. This bit is cleared by writing a zero to it or by any system reset that is not initiated by the WD counter; it is not cleared following a WD-initiated reset. WD resets can occur, regardless of the status of this flag. For the TMS370Cxxx devices, the bit indicates the status of the WD overflow interrupt. If the WD OVRFL RST ENA bit = 1, this bit is cleared by writing a zero to it or by a power cycle. If the WD OVRFL RST ENA bit = 0, this bit is cleared by any system reset. Once a WD reset has occurred and if the flag is not cleared, any subsequent WD-generated reset will not reset the system.
-
WD OVRFL RST ENA bit (T1CTL2.7): For the TMS370CxxxA and TMS370C7xxB devices, this bit is cleared by any system reset (for example, a power-up reset, an oscillator fault, or a reinitialized incorrect value to the WD timer). For the TMS370Cxxx devices, only a power-up reset can clear this bit.
A.5 System Control and Configuration Register 2 (SCCR2) Bits
Two of the SCCR2 bits (SCCR2 register shown in subsection 4.3.3 on page 4-16) operate differently according to which device you're using:
-
Bit SCCR2.2:
J J
For the TMS370CxxxA and TMS370C7xxxB devices, this bit is reserved; writing a zero or a one to this bit has no effect. For the TMS370Cxxx device, this is the OSC FLT DISABLE bit (oscillator fault disable). You must clear (zero) this bit to ensure proper operation. (Note, this bit is shown reserved -- without a name -- in the register figure in subsection 4.3.3 on page 4-16).
-
Bit SCCR2.5:
J
For the TMS370CxxxA and TMS370C7xxB devices, this bit is reserved; writing a zero or a one to this bit has no effect. When the system detects an oscillator fault, the device generates a system reset, regardless of the status of this bit.
A-5
Differences Among the TMS370CxxxA, TMS370C7xxB, and TMS370Cxxx Devices (Contact Options)
System Control and Configuration Register 2 (SCCR2) Bits/AP Bit in the DEECTL Register (DEECTL.2)
J
For the TMS370Cxxx devices, this bit is the OSC FLT RST ENA bit (oscillator failt reset enable). It determines whether or not a system reset is generated when an oscillator fault is detected. 0 = A reset will not be generated if an oscillator fault is detected. An external hardware reset is required to restart the program. 1 = A reset is generated when an oscillator fault is detected if bit SCCR.2 is cleared. (Note, this bit is shown reserved -- without a name -- in the register figure in subsection 4.3.3 on page 4-16).
A.6 AP Bit in the DEECTL Register (DEECTL.2)
The AP (array program) bit in the Data EEPROM Control Register (DEECTL, Section 6.2.2 on page 6-4) operates differently depending on which device you are using:
-
TMS370CxxxA and TMS370C7xxB devices with a single or multiple 256-bye array: In a single programming cycle, the AP bit programs the entire array space with the value specified by the W1W0 bit. However, the device must be in the WPO mode for the array to be programmed. Moreover, there is no write protection during WPO mode; the write protection register (WPR, described in subsection 6.2.1 on page 6-3) is considered a normal data location within the data EEPROM array during this time. If the device is not in the WPO mode, the AP bit has no effect on the programming operation, and a single byte is programmed. TMS370Cxxx devices with multiple 256-byte arrays: In this case, the AP bit operates like that described for the TMS370CxxxA and TMS370C7xxB devices above. TMS370Cxxx devices with a single 256-byte array: In this case, the AP bit programs the entire array in a single programming cycle with the value specified by the W1W0 bit (Section 18.6, EPROM/EEPROM Specifications, on page 18-7 contains EPROM/EEPROM timings). Blocks that are protected in the WPR register are not programmed. If BLK0 is unprotected and bit W1W0 is zero, this function clears the WPR. Any array locations previously protected then lose their protection, but their contents are not altered during the current programming cycle.
-
A-6
Program EPROM Control Register (EPCTLx) / VCC1 and VCC2 Pins
A.7 Program EPROM Control Register (EPCTLx)
The EPCTLx register (subsection 6.4.2 on page 6-12) operates differently depending on the TMS370C758 device:
-
TMS370C758A and TMS370C758B devices: The first 16K-byte array is controlled by register EPCTLL, located at address 101Eh (P01E), and the second 16K-byte array is controlled by register EPCTLM, located at address 101Ch (P01C). See Table A-4. TMS370C758 devices: In comparison to the 'C758A and 'C758B devices described above, control registers EPCTLL and EPCTLM are switched as shown in Table A-4. The first 16K-byte array is controlled by EPCTLM (at address 101Ch, P01C), and the second 16K-byte array is controlled by EPCTLL (at address 101Eh, P01E).
Table A-4.
EPROM Memory Map for TMS370C758 Devices
TMSC70C758A and TMS370C758B TMS370C758 32K bytes First 16K (2000h-5FFFh) EPCTLM (P01C) Second 16K (6000h-9FFFh) EPCTLL (P01E)
EPROM size Mapped memory Control registers First 16K (2000h-5FFFh) EPCTLL (P01E)
32K bytes Second 16K (6000h-9FFFh) EPCTLM (P01C)
A.8 VCC1 and VCC2 Pins
The VCC1 and VCC2 pins are internally connected on the TMS370CxxxA and TMS370C7xxxB devices. For the TMS370Cxxx devices, these pins are not internally connected.
Remember, when using a TMS370CxxxA device, you cannot use the internal connections between pins (for example, the connection between VSS1 and VSS2) for a jumper from one side of the chip to the other.
Differences Among the TMS370CxxxA, TMS370C7xxB, and TMS370Cxxx Devices (Contact Options)
A-7
Electrical Specifications
A.9 Electrical Specifications
This section describes the differences among the TMS370Cx5xA devices and TMS370Cx5x devices, both in terms of electrical specifications and SCI and SPI specifications.
A.9.1 Differences for TMS370Cx5x Devices
Table A-5 summarizes the differences in electrical specifications.
Table A-5. Switching Characteristics and Timing Requirements for External Read and Write
TMS370Cx5xA and TMS370Cx5xB Devices Parameter tc SYSCLK (system clock) cycle time Divide-by-4 clock Divide-by-1 (PLL) tw(SCL) tw(SCH) td(SCL-A) tv(A) tsu(D) th(EH-A) SYSCLK low pulse duration SYSCLK high pulse duration Delay time, SYSCLK low to address R/W, and OCF valid Address valid to EDS, CSE1, CSE2, CSH1, CSH2, CSH3, and CSPF low Write data setup time to EDS high Address, R/W, and OCF hold time from EDS,CSE1, CSE2, CSH1, CSH2, CSH3, and CSPF high Write data hold time from EDS high Delay time, data bus high impedance to EDS low (read cycle) Delay time, EDS high to data bus enable (read cycle) Delay time, EDS low to read data valid Read data hold time from EDS high WAIT setup time to SYSCLK high WAIT hold time from SYSCLK high 0 0.25 tc + 70 0 0.5 tc - 90 0.75 tc - 80 0.5 tc - 60 Min 200 200 0.5 tc - 25 0.5 tc Max 2000 500 0.5 tc 0.5 tc + 20 0.25 tc + 75 0.5 tc - 50 0.75 tc - 40 0.5 tc - 40 TMS370Cx5x Devices Min 200 Not available 0.5 tc - 20 0.5 tc Max 2000 Not available 0.5 tc 0.5 tc + 20 0.25 tc + 40 Unit ns ns ns ns ns ns ns ns
th(EH-D)W td(DZ-EL) td(EH-D) td(EL-DV)R th(EH-D)R tsu(WT-SCH) th(SCH-WT)
0.75 tc + 15 0.25 tc - 35 1.25 tc - 40 tc - 95
0.75 tc + 15 0.25 tc - 30 1.25 tc - 40 tc - 65 0 0.25 tc + 75 0
ns ns ns ns ns ns ns
td(EL-WTV) Delay time, EDS low to WAIT valid 0.5 tc - 60 0.5 tc - 70 ns tc = system clock cycle time = 1/SYSCLK. If wait states, PFWait, or the autowait feature is used, add one SYSCLK cycle (tc) to this value for each wait state invoked. If the autowait feature is enabled, the WAIT input may assume a "don't care" condition until the third cycle of the access. The WAIT signal must be synchronized with the high pulse of the SYSCLK signal while still conforming to the minimum setup time.
A-8
Electrical Specifications
Table A-5. Switching Characteristics and Timing Requirements for External Read and Write (Continued)
TMS370Cx5xA and TMS370Cx5xB Devices Parameter tw td(AV-DV)R td(AV-WTV) td(AV-EH) Pulse duration, EDS, CSE1, CSE2, CSH1, CSH2, CSH3, and CSPF low Delay time, address valid to read data valid Delay time, address valid to WAIT valid Delay time, address valid to EDS high (end of write) 1.5 tc - 85 Min tc - 80 Max tc + 40 1.5 tc - 115 tc - 115 1.5 tc - 40 TMS370Cx5x Devices Min tc - 40 Max tc + 40 1.5 tc - 75 tc - 85 Unit ns ns ns ns
tc = system clock cycle time = 1/SYSCLK. If wait states, PFWait, or the autowait feature is used, add one SYSCLK cycle (tc) to this value for each wait state invoked. If the autowait feature is enabled, the WAIT input may assume a "don't care" condition until the third cycle of the access. The WAIT signal must be synchronized with the high pulse of the SYSCLK signal while still conforming to the minimum setup time.
Table A-6. IOL (Low-Level Output Current)
Parameter VOL Low-level output voltage (port A, B, C, D, and RESET) Test Conditions IOL = 1.4 mA for TMS370Cx5xA and TMS370Cx5xB IOL = 2.0 mA for TMS370Cx5x Min Typ Max 0.4 Unit V
A.9.2 Differences in SCI1 and SPI Specifications
The differences in SCI1 and SPI electrical specifications among the TMS370CxxxA, TMS370C7xxB, and TMS370Cxxx devices are summarized in this subsection.
Table A-7. SCI1 Isosynchronous Mode Timing Characteristics for Internal Clock
TMS370CxxxA and TMS370C7xxB Parameter td(SCCL-TXDV) Delay time, SCITXD valid after SCICLK low Min - 50 Max 60 TMS370Cxxx Min - 50 Max 50 ns Unit
Table A-8. SPI External Timing Characteristics and Requirements
TMS370CxxxA and TMS370C7xxB Parameter tw(SPCH)M td(SPCL-SIMOV)M td(SPCL-SOMIV)S SPICLK high pulse duration Delay time, SPISIMO valid after SPICLK low (polarity = 1) Delay time, SPISOMI valid after SPICLK low (polarity = 1) Min tc - 55 -65 Max 0.5 tc(SPC) + 45 50 3.25 tc + 130 Min tc - 45 -50 TMS370Cxxx Max 0.5 tc(SPC) + 45 50 3.25 tc + 125 ns ns ns Unit
Differences Among the TMS370CxxxA, TMS370C7xxB, and TMS370Cxxx Devices (Contact Options)
A-9
Electrical Specifications
A.9.3 Differences in EPROM Specifications
The differences in EPROM electrical specifications among the TMS370CxxxA, TMS370CxxxB, and TMS370xxx devices are summarized in Table A-9 and Table A-10.
Table A-9. Recommended EPROM Operating Conditions for Programming
TMS370CxxxA and TMS370CxxxB Parameter VPP Supply voltage at MC pin Min 13 Nom 13.2 Max 13.5
TMS370Cxxx Min 12 Nom 12.5 Max 13 Unit V
Table A-10. Recommended EPROM Timing Requirements for Programming
TMS370CxxxA and TMS370CxxxB Parameter tw(EPGM) Programming signal pulse duration Min 0.40 Nom 0.50 Max 3
TMS370Cxxx Min 0.95 Nom 2 Max 30 Unit ms
A-10
Summary of Differences
A.10 Summary of Differences
The differences among the TMS370CxxxA, TMS370C7xxB, TMS370Cxxx devices are summarized in Table A-11. and
Table A-11.
Summary of Differences Among the TMS370Cxxx, TMS370CxxxA, and TMS370C7xxB Devices
TMS370Cxxx ROMless, Mask-ROM, and EPROM TMS370CxxxA ROMless andMask-ROM
Options Standard WD option (WD and non-WD modes) Hard WD option Simple counter option Value of WD OVRFL RST ENA Bit (T1CTL2.7) Value of WD OVRFL INT FLAG Bit (T1CTL2.5)
TMS370CxxxA EPROM
TMS370C7xxB EPROM
n
Cleared by powerup reset only Once a WD reset has occurred and the bit remains set (1), a subsequent WD reset will not reset the system. Determines whether or not a system reset is generated when an oscillator fault is detected Must be cleared to ensure proper operation Not internally connected Software configurable
n n n
Cleared by any system reset If a WD reset has occurred, it must be cleared by the software in order to determine the source of resets that follow. Reserved bit (value has no effect)
n
Cleared by any system reset If a WD reset has occurred, it must be cleared by the software in order to determine the source of resets that follow. Reserved bit (value has no effect)
n
Cleared by any system reset If a WD reset has occurred, it must be cleared by the software in order to determine the source of resets that follow. Reserved bit (value has no effect)
Value of OSC FLT RST ENA Bit (SCCR2.5)
Value of OSC FLT DISABLE Bit (SCCR2.2) VCC1 and VCC2 pins Method of enabling lowpower mode
Reserved bit (value has no effect) Internally connected Programmable contact when mask is manufactured
Reserved bit (value has no effect) Internally connected Software configurable
Reserved bit (value has no effect) Internally connected Software configurable
Differences Among the TMS370CxxxA, TMS370C7xxB, and TMS370Cxxx Devices (Contact Options)
A-11
Summary of Differences
Table A-11. Summary of Differences Among the TMS370Cxxx, TMS370CxxxA, and TMS370C7xxB Devices(Continued)
TMS370Cxxx ROMless, Mask-ROM, and EPROM If set, programs the entire array with the value specified by the W1W0 bit. 1) For multiple 256-byte arrays, must be in the WPO mode for the array to be programmed; otherwise this bit has no effect on the programming operation, and a single bit is programmed. 2) For a single 256-byte array, blocks that are protected in the WPR register are not programmed. TMS370CxxxA ROMless andMask-ROM If set, programs the entire array with the value specified by the W1W0 bit. For single or multiple 256-byte arrays, must be in the WPO mode for the array to be programmed; otherwise this bit has no effect on the programming operation, and a single bit is programmed.
Options Value of AP Bit (DEECTL.2)
TMS370CxxxA EPROM If set, programs the entire array with the value specified by the W1W0 bit. For single or multiple 256-byte arrays, must be in the WPO mode for the array to be programmed; otherwise this bit has no effect on the programming operation, and a single bit is programmed.
TMS370C7xxB EPROM If set, programs the entire array with the value specified by the W1W0 bit. For single or multiple 256-byte arrays, must be in the WPO mode for the array to be programmed; otherwise this bit has no effect on the programming operation, and a single bit is programmed.
A-12
Running Title--Attribute Reference
Appendix B Appendix A
Peripheral File Memory Map
This appendix summarizes the peripheral file (PF) and control bit information. Each PF register is presented as a row of bit representations. The register designation (for example, SCCR0), memory map address, and the PF hex address (for example, P010) are to the left of each register. The registers described in this appendix are as follows:
Topic
B.1 B.2 B.3 B.4 B.5 B.6 B.7 B.8 B.9
Page
Read/Write Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2 Peripheral File Frame 1: System Configuration Registers . . . . . . . . B-3 Peripheral File Frame 2: Digital Port Control Registers . . . . . . . . . . . B-4 Peripheral File Frame 3: SPI Control Registers . . . . . . . . . . . . . . . . . . B-5 Peripheral File Frame 4: Timer 1 (T1) Control Registers . . . . . . . . . . B-6 Peripheral File Frame 4: PACT Control Registers . . . . . . . . . . . . . . . . B-7 Peripheral File Frame 5: SCI1 Control Registers . . . . . . . . . . . . . . . . . B-8 Peripheral File Frame 5: SCI2 Control Registers . . . . . . . . . . . . . . . . . B-9 Peripheral File Frame 6: Timer 2A (T2A) Control Registers . . . . . . B-10
B.10 Peripheral File Frame 7: ADC1 Control Registers . . . . . . . . . . . . . . . B-11 B.11 Peripheral File Frame 7: ADC2 Control Registers . . . . . . . . . . . . . . . B-12 B.12 Peripheral File Frame 7: ADC3 Control Registers . . . . . . . . . . . . . . . B-13 B.13 Peripheral File Frame 8: Timer 2B (T2B) Control Registers . . . . . . B-14
Chapter Title--Attribute Reference
B-1
Read/Write Definitions
B.1 Read/Write Definitions
The read/write accessibility of each bit is indicated in parentheses below each bit symbol, with the following definitions: R W P C S -0 -1 -* = = = = = = = = Read Write Write in privilege mode only Clear only Set only Cleared when the register is reset Set when the register is reset This bit exhibits a special behavior during or after a reset; see the description for this bit in the appropriate section
The shaded boxes in the tables denote privilege mode bits; that is, these bits can be written to only in the privilege mode.
B-2
Peripheral File Frame 1: System Configuration Registers
B.2 Peripheral File Frame 1: System Configuration Registers
Designation SCCR0 ADDR 1010h PF P010 Bit 7 COLD START (RW-*) -- SCCR2 1012h P012 HALT/ STANDBY (RP-0) Bit 6 OSC POWER (RP-0) -- PWRDWN/ IDLE (RP-0) Bit 5 PF AUTOWAIT (RP-0) -- Bit 4 OSC FLT FLAG (RW-0) AUTOWAIT DISABLE (RP-0) BUS STEST (RP-0) Bit 3 MC PIN WPO (R-0) -- CPU STEST (RP-1) Bit 2 MC PIN DATA (R-*) MEMORY DISABLE (RP-*) -- Bit 1 -- Bit 0 P/C MODE (R-*) -- PRIVILEGE DISABLE (RS-0)
SCCR1
1011h
P011
-- INT1 NMI (RP-0)
--
1013h EPCTLH 1014h 1015h to 1016h INT1 1017h
P013 P014 P015 to P016 P017 INT1 FLAG (RC-0) INT2 FLAG (RC-0) INT3 FLAG (RC-0) BUSY (R-*) INT1 PIN DATA (R-0) INT2 PIN DATA (R-0) INT3 PIN DATA (R-0) -- -- -- BUSY (R-0) VPPS (RW-0) -- --
Reserved -- -- W0 (RW-0) EXE (RW-0)
Reserved INT1 POLARITY (RW-0) INT2 POLARITY (RW-0) INT3 POLARITY (RW-0) AP (RW-0) INT1 PRIORITY (RW-0) INT2 PRIORITY (RW-0) INT3 PRIORITY (RW-0) W1W0 (RW-0) INT1 ENABLE (RW-0) INT2 ENABLE (RW-0) INT3 ENABLE (RW-0) EXE (RW-0)
-- INT2 DATA OUT (RW-0) INT3 DATA OUT (RW-0) -- Reserved
INT2
1018h
P018
--
INT2 DATA DIR (RW-0) INT3 DATA DIR (RW-0) --
INT3
1019h
P019
--
DEECTL
101Ah 101Bh
P01A P01B P01C P01D P01E P01F
--
EPCTLM
101Ch 101Dh
BUSY (R-0)
VPPS (RW-0)
--
-- Reserved
--
--
W0 (RW-0)
EXE (RW-0)
EPCTLL
101Eh 101Fh
BUSY (R-0)
VPPS (RW-0)
--
-- Reserved
--
--
W0 (RW-0)
EXE (RW-0)
Note:
Shaded boxes can be written to in the privilege mode.
For more information about these registers and control bits, refer to the following sections:
-
SCCR0, SCCR1, and SCCR2: Section 4.3, page 4-13 INT1, INT2, and INT3: Section 5.2, page 5-12 DEECTL: subsection 6.2.2, page 6-4 EPCTLL, EPCTLM, and EPCTLH: subsection 6.4.2, page 6-12
Peripheral File Memory Map
B-3
Peripheral File Frame 2: Digital Port Control Registers
B.3 Peripheral File Frame 2: Digital Port Control Registers
Designation APORT1 APORT2 ADATA ADIR BPORT1 BPORT2 BDATA BDIR CPORT1 CPORT2 CDATA CDIR DPORT1 DPORT2 DDATA DDIR ADDR 1020h 1021h 1022h 1023h 1024h 1025h 1026h 1027h 1028h 1029h 102Ah 102Bh 102Ch 102Dh 102Eh 102Fh 1030h to 1035h GDATA GDIR 1036h 1037h 1038h to 1039h HDATA HDIR 103Ah 103Bh PF P020 P021 P022 P023 P024 P025 P026 P027 P028 P029 P02A P02B P02C P02D P02E P02F P030 to P035 P036 P037 P038 to P039 P03A P03B Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reserved Port A Control Register 2 Port A Data Port A Direction Reserved Port B Control Register 2 Port B Data Port B Direction Reserved Port C Control Register 2 Port C Data Port C Direction Port D Control Register 1 Port D Control Register 2 Port D Data Port D Direction Reserved Port G Data Port G Direction Reserved Port H Data Port H Direction
Reserved Reserved
For more information about these registers and control bits, refer to Section 4.4 on page 4-18.
B-4
Peripheral File Frame 3: SPI Control Registers
B.4 Peripheral File Frame 3: SPI Control Registers
Designation SPICCR ADDR 1030h PF P030 Bit 7 SPI SW RESET (RW-0) RECEIVER OVERRUN (R-0) Bit 6 CLOCK POLARITY (RW-0) SPI INT FLAG (R-0) Bit 5 SPI BIT RATE2 (RW-0) -- Bit 4 SPI BIT RATE1 (RW-0) -- Bit 3 SPI BIT RATE0 (RW-0) -- Bit 2 SPI CHAR2 (RW-0) MASTER/ SLAVE (RW-0) Bit 1 SPI CHAR1 (RW-0) TALK (RW-0) Bit 0 SPI CHAR0 (RW-0) SPI INT ENA (RW-0)
SPICTL
1031h
P031
1032h to 1036h SPIBUF 1037h 1038h SPIDAT 1039h 103Ah to 103Ch SPIPC1 103Dh
P032 to P036 P037 P038 P039 P03A to P03C P03D -- -- SPISIMO DATA OUT (RW-0) SPI PRIORITY (RP-0) -- SPISIMO FUNCTION (RW-0) SPI ESPEN (RP-0) -- SPISIMO DATA DIR (RW-0) -- SPICLK DATA IN (R-0) SPISOMI DATA IN (R-0) -- SPICLK DATA OUT (RW-0) SPISOMI DATA OUT (RW-0) -- SPICLK FUNCTION (RW-0) SPISOMI FUNCTION (RW-0) -- SPICLK DATA DIR (RW-0) SPISOMI DATA DIR (RW-0) -- Reserved SDAT7 (RW-0) SDAT6 (RW-0) SDAT5 (RW-0) RCVD7 (R-0) RCVD6 (R-0) RCVD5 (R-0) RCVD4 (R-0) RCVD3 (R-0) RCVD2 (R-0) RCVD1 (R-0) RCVD0 (R-0) Reserved
Reserved SDAT4 (RW-0) SDAT3 (RW-0) SDAT2 (RW-0) SDAT1 (RW-0) SDAT0 (RW-0)
SPIPC2
103Eh
P03E
SPISIMO DATA IN (R-0) SPI STEST (RP-0)
SPIPRI
103Fh
P03F
Note:
Shaded boxes can be written to in the privilege mode.
For more information about these registers and control bits, refer to Section 11.9 on page 11-13.
Peripheral File Memory Map
B-5
Peripheral File Frame 4: Timer 1 (T1) Control Registers
B.5 Peripheral File Frame 4: Timer 1 (T1) Control Registers
Designation T1CNTR T1CNTR T1C T1C T1CC T1CC WDCNTR WDCNTR WDRST T1CTL1 ADDR 1040h 1041h 1042h 1043h 1044h 1045h 1046h 1047h 1048h 1049h PF P040 P041 P042 P043 P044 P045 P046 P047 P048 P049 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 7 WD OVRFL TAP SEL (RP-0) WD OVRFL RST ENA (RS-0) WD INPUT SELECT2 (RP-0) WD INPUT SELECT1 (RP-0) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 0 T1 INPUT SELECT2 (RW-0) T1 INPUT SELECT1 (RW-0) T1 INPUT SELECT0 (RW-0) T1 SW RESET (S-0) T1 Counter MSbyte T1 Counter LSbyte Compare Register MSbyte Compare Register LSbyte Capture/Compare Register MSbyte Capture/Compare Register LSbyte Watchdog Counter MSbyte Watchdog Counter LSbyte Watchdog Reset Key WD INPUT SELECT0 (RP-0) T1 OVRFL INT ENA (RW-0)
T1CTL2
104Ah
P04A
T1CTL3
104Bh
P04B
T1CTL4
104Ch
P04C
T1PC1
104Dh
P04D -- -- T1PWM DATA OUT (RW-0) T1 PRIORITY (RP-0) -- T1PWM FUNCTION (RW-0) -- -- T1PWM DATA DIR (RW-0) --
T1PC2
104Eh
P04E
T1PRI
104Fh
P04F
Once the WD OVRFL RST ENA bit is set, these bits cannot be changed until a reset; this applies only to the standard watchdog (WD) and to the simple counter. In the hard WD, these bits can be modified at any time; the WD INPUT SELECT2 bit is ignored. Note: Shaded boxes can be written to in the privilege mode.
B-6
IIII IIII I IIII I I IIII I IIIIIIIII IIIIIIIIIIII I II I IIIIIIIIIIII
WD OVRFL INT ENA (RW-0) WD OVRFL INT FLAG (RC-*) T1EDGE INT FLAG (RC-0) T1C2 INT FLAG (RC-0) T1C1 INT FLAG (RC-0) -- T1EDGE INT FLAG (RC-0) -- T1C1 INT FLAG (RC-0) -- T1 MODE = 0 (RW-0) T1C1 OUT ENA (RW-0) T1C2 OUT ENA (RW-0) T1C1 RST ENA (RW-0) T1 MODE = 1 (RW-0) T1C1 OUT ENA (RW-0) -- T1C1 RST ENA (RW-0) T1PWM DATA IN (R-0) T1 STEST (RP-0)
--
T1 OVRFL INT FLAG (RC-0)
--
--
Dual Compare Mode T1EDGE INT ENA (RW-0) T1C2 INT ENA (RW-0) T1C1 INT ENA (RW-0)
--
Capture / Compare Mode T1EDGE INT ENA (RW-0) T1C1 INT ENA (RW-0)
--
--
Dual Compare Mode T1CR OUT ENA (RW-0) T1EDGE POLARITY (RW-0) T1CR RST ENA (RW-0) T1EDGE DET ENA (RW-0)
Capture / Compare Mode -- T1EDGE POLARITY (RW-0) T1EVT DATA OUT (RW-0) T1IC/CR DATA OUT (RW-0) -- -- T1EDGE DET ENA (RW-0) T1EVT DATA DIR (RW-0) T1IC/CR DATA DIR (RW-0) --
T1EVT DATA IN (R-0) T1IC/CR DATA IN (R-0) --
T1EVT FUNCTION (RW-0) T1IC/CR FUNCTION (RW-0) --
For more information about these registers and control bits, refer to Section 7.9 on page 7-30.
Peripheral File Frame 4: PACT Control Registers
B.6 Peripheral File Frame 4: PACT Control Registers
Designation
ADDR
PF
Bit 7 DEFTIM OVRFL INT ENA (RW-0) CMD/DEF AREA INT ENA (RW-0)
Bit 6 DEFTIM OVRFL INT FLAG (RC-0)
Bit 5 CMD/DEF AREA ENA (RW-0) CMD/DEF AREA START BIT 5 (RW-0) CMD/DEF AREA END BIT 5 (RW-0) BUFFER POINTER BIT 5 (R-1)
Bit 4 FAST MODE SELECT (RP-0) CMD/DEF AREA START BIT 4 (RW-0) CMD/DEF AREA END BIT 4 (RW-0) BUFFER POINTER BIT 4 (R-1)
Bit 3 PACT PRESCALE SELECT 3 (RP-0) CMD/DEF AREA START BIT 3 (RW-0) CMD/DEF AREA END BIT 3 (RW-0) BUFFER POINTER BIT 3 (R-0)
Bit 2 PACT PRESCALE SELECT 2 (RP-0) CMD/DEF AREA START BIT 2 (RW-0) CMD/DEF AREA END BIT 2 (RW-0) BUFFER POINTER BIT 2 (R-0)
Bit 1 PACT PRESCALE SELECT 1 (RP-0)
Bit 0 PACT PRESCALE SELECT 0 (RP-0)
PACTSCR
1040h
P040
CDSTART
1041h
P041
--
--
--
CDEND
1042h
P042
--
CMD/DEF AREA END BIT 6 (RW-0) 1 (R-1)
--
--
BUFPTR
1043h
P043
1 (R-1)
BUFFER POINTER BIT 1 (R-0)
--
1044h SCICTLP 1045h
P044 P045 PACT RXRDY (RC-0) PACT RXDT7 (R-0) PACT TXDT7 (RW-0) PACT OP8 STATE (RW-0) CMD/DEF INT 7 FLAG (RC-0) CP2 INT ENA (RW-0) CP4 INT ENA (RW-0) CP6 INT ENA (RW-0) BUFFER HALF/FULL INT ENA (RW-0) PACT TXRDY (R-1) PACT RXDT6 (R-0) PACT TXDT6 (RW-0) PACT OP7 STATE (RW-0) CMD/DEF INT 6 FLAG (RC-0) CP2 INT FLAG (RC-0) CP4 INT FLAG (RC-0) CP6 INT FLAG (RC-0) BUFFER HALF/FULL INT FLAG (RC-0) PACT PARITY (R-0) PACT RXDT5 (R-0) PACT TXDT5 (RW-0) PACT OP6 STATE (RW-0) CMD/DEF INT 5 FLAG (RC-0) CP2 CAPT RISING EDGE (RW-0) CP4 CAPT RISING EDGE (RW-0) CP6 CAPT RISING EDGE (RW-0) INPUT CAPT PRESCALE SELECT 3 (RW-0) PACT FE (RC-0) PACT RXDT4 (R-0) PACT TXDT4 (RW-0)
Reserved PACT SCI RX INT ENA (RW-0) PACT RXDT3 (R-0) PACT TXDT3 (RW-0) PACT OP4 STATE (RW-0) CMD/DEF INT 3 FLAG (RC-0) CP1 INT ENA (RW-0) CP3 INT ENA (RW-0) CP5 INT ENA (RW-0) INPUT CAPT PRESCALE SELECT 1 (RW-0) PACT SCI TX INT ENA (RW-0) PACT RXDT2 (R-0) PACT TXDT2 (RW-0) PACT OP3 STATE (RW-0) CMD/DEF INT 2 FLAG (RC-0) CP1 INT FLAG (RC-0) CP3 INT FLAG (RC-0) CP5 INT FLAG (RC-0) CP6 EVENT ONLY (RW-0) -- PACT RXDT1 (R-0) PACT TXDT1 (RW-0) PACT OP2 STATE (RW-0) CMD/DEF INT 1 FLAG (RC-0) CP1 CAPT RISING EDGE (RW-0) CP3 CAPT RISING EDGE (RW-0) CP5 CAPT RISING EDGE (RW-0) EVENT COUNTER SW RESET (RW-0) PACT SCI SW RESET (RW-0) PACT RXDT0 (R-0) PACT TXDT0 (RW-0) PACT OP1 STATE (RW-0) CMD/DEF INT 0 FLAG (RC-0) CP1 CAPT FALLING EDGE (RW-0) CP3 CAPT FALLING EDGE (RW-0) CP5 CAPT FALLING EDGE (RW-0) OP SET/CLR SELECT (RW-0)
RXBUFP
1046h
P046
TXBUFP
1047h
P047
OPSTATE
1048h
P048
PACT OP5 STATE (RW-0) CMD/DEF INT 4 FLAG (RC-0) CP2 CAPT FALLING EDGE (RW-0) CP4 CAPT FALLING EDGE (RW-0) CP6 CAPT FALLING EDGE (RW-0) INPUT CAPT PRESCALE SELECT 2 (RW-0)
CDFLAGS
1049h
P049
CPCTL1
104Ah
P04A
CPCTL2
104Bh
P04B
CPCTL3
104Ch
P04C
CPPRE
104Dh
P04D
WDRST
104Eh
P04E PACT STEST (RP-0) PACT GROUP 1 PRIORITY (RP-0)
WD Reset Key PACT GROUP 2 PRIORITY (RP-0) PACT GROUP 3 PRIORITY (RP-0) PACT MODE SELECT (RP-0) PACT WD PRESCALE SELECT 1 (RP-0) PACT WD PRESCALE SELECT 0 (RP-0)
PACTPRI
104Fh
P04F
--
Note:
Shaded boxes can be written to in the privilege mode.
For more information about these registers and control bits, refer to Section 15.11 on page 15-36.
Peripheral File Memory Map
B-7
Peripheral File Frame 5: SCI1 Control Registers
B.7 Peripheral File Frame 5: SCI1 Control Registers
Designation SCICCR ADDR 1050h PF P050 Bit 7 STOP BITS (RW-0) Bit 6 EVEN/ODD PARITY (RW-0) -- BAUDE (RW-0) BAUD6 (RW-0) TX EMPTY (R-1) RXRDY (R-0) Bit 5 PARITY ENABLE (RW-0) SCI SW RESET (RW-0) BAUDD (RW-0) BAUD5 (RW-0) -- BRKDT (R-0) Bit 4 ASYNC/ ISOSYNC (RW-0) CLOCK (RW-0) BAUDC (RW-0) BAUD4 (RW-0) -- FE (R-0) Reserved RXDT7 (R-0) RXDT6 (R-0) RXDT5 (R-0) RXDT4 (R-0) RXDT3 (R-0) RXDT2 (R-0) RXDT1 (R-0) RXDT0 (R-0) Bit 3 ADDRESS/ IDLE WUP (RW-0) TXWAKE (RS-0) BAUDB (RW-0) BAUD3 (RW-0) -- OE (R-0) Bit 2 SCI CHAR2 (RW-0) SLEEP (RW-0) BAUDA (RW-0) BAUD2 (RW-0) -- PE (R-0) Bit 1 SCI CHAR1 (RW-0) TXENA (RW-0) BAUD9 (RW-0) BAUD1 (RW-0) -- RXWAKE (R-0) Bit 0 SCI CHAR0 (RW-0) RXENA (RW-0) BAUD8 (RW-0) BAUD0 (LSB) (RW-0) SCI TX INT ENA (RW-0) SCI RX INT ENA (RW-0)
SCICTL
1051h
P051 --
BAUD MSB
1052h
P052
BAUDF (MSB) (RW-0) BAUD7 (RW-0) TXRDY (R-1) RX ERROR (R-0)
BAUD LSB
1053h
P053
TXCTL
1054h
P054
RXCTL
1055h
P055
1056h RXBUF 1057h 1058h TXBUF 1059h 105Ah to 105Ch SCIPC1 105Dh
P056 P057 P058 P059 P05A to P05C P05D -- -- SCITXD DATA OUT (RW-0) SCITX PRIORITY (RP-0) -- SCITXD FUNCTION (RW-0) SCIRX PRIORITY (RP-0) -- TXDT7 (RW-0) TXDT6 (RW-0) TXDT5 (RW-0)
Reserved TXDT4 (RW-0) TXDT3 (RW-0) TXDT2 (RW-0) TXDT1 (RW-0) TXDT0 (RW-0)
Reserved
SCICLK DATA IN (R-0) SCIRXD DATA IN (R-0) --
SCICLK DATA OUT (RW-0) SCIRXD DATA OUT (RW-0) --
SCICLK FUNCTION (RW-0) SCIRXD FUNCTION (RW-0) --
SCICLK DATA DIR (RW-0) SCIRXD DATA DIR (RW-0) --
SCIPC2
105Eh
P05E
SCITXD DATA IN (R-0) SCI STEST (RP-0)
SCITXD DATA DIR (RW-0) SCI ESPEN (RP-0)
SCIPRI
105Fh
P05F
Note:
Shaded boxes can be written to in the privilege mode.
For more information about these registers and control bits, refer to Section 9.8 on page 9-21.
B-8
Peripheral File Frame 5: SCI2 Control Registers
B.8 Peripheral File Frame 5: SCI2 Control Registers
Designation SCICCR ADDR 1050h PF P050 Bit 7 STOP BITS (RW-0) Bit 6 EVEN/ODD PARITY (RW-0) -- BAUDE (RW-0) BAUD6 (RW-0) TX EMPTY (R-1) RXRDY (R-0) Bit 5 PARITY ENABLE (RW-0) SCI SW RESET (RW-0) BAUDD (RW-0) BAUD5 (RW-0) -- BRKDT (R-0) Bit 4 ASYNC ENABLE (RW-0) CLOCK ENABLE (RW-0) BAUDC (RW-0) BAUD4 (RW-0) -- FE (R-0) Reserved RXDT7 (R-0) RXDT6 (R-0) RXDT5 (R-0) RXDT4 (R-0) RXDT3 (R-0) RXDT2 (R-0) RXDT1 (R-0) RXDT0 (R-0) Bit 3 ADDRESS/ IDLE WUP (RW-0) TXWAKE (RS-0) BAUDB (RW-0) BAUD3 (RW-0) -- OE (R-0) Bit 2 SCI CHAR2 (RW-0) SLEEP (RW-0) BAUDA (RW-0) BAUD2 (RW-0) -- PE (R-0) Bit 1 SCI CHAR1 (RW-0) TXENA (RW-0) BAUD9 (RW-0) BAUD1 (RW-0) -- RXWAKE (R-0) Bit 0 SCI CHAR0 (RW-0) RXENA (RW-0) BAUD8 (RW-0) BAUD0 (LSB) (RW-0) SCI TX INT ENA (RW-0) SCI RX INT ENA (RW-0)
SCICTL
1051h
P051 --
BAUD MSB
1052h
P052
BAUDF (MSB) (RW-0) BAUD7 (RW-0) TXRDY (R-1) RX ERROR (R-0)
BAUD LSB
1053h
P053
TXCTL
1054h
P054
RXCTL
1055h
P055
1056h RXBUF 1057h 1058h TXBUF 1059h 105Ah to 105Dh SCIPC2 105Eh
P056 P057 P058 P059 P05A to P05D P05E SCITXD DATA IN (R-0) SCI STEST (RP-0) SCITXD DATA OUT (RW-0) SCITX PRIORITY (RP-0) SCITXD FUNCTION (RW-0) SCIRX PRIORITY (RP-0) TXDT7 (RW-0) TXDT6 (RW-0) TXDT5 (RW-0)
Reserved TXDT4 (RW-0) TXDT3 (RW-0) TXDT2 (RW-0) TXDT1 (RW-0) TXDT0 (RW-0)
Reserved
SCITXD DATA DIR (RW-0) SCI ESPEN (RP-0)
SCIRXD DATA IN (R-0) --
SCIRXD DATA OUT (RW-0) --
SCIRXD FUNCTION (RW-0) --
SCIRXD DATA DIR (RW-0) --
SCIPRI
105Fh
P05F
Note:
Shaded boxes can be written to in the privilege mode.
For more information about these registers and control bits, refer to Section 10.8 on page 10-17.
Peripheral File Memory Map
B-9
Peripheral File Frame 6: Timer 2A (T2A) Control Registers
B.9 Peripheral File Frame 6: Timer 2A (T2A) Control Registers
Designation T2ACNTR T2ACNTR T2AC T2AC T2ACC T2ACC T2AIC T2AIC T2ACTL1 ADDR 1060h 1061h 1062h 1063h 1064h 1065h 1066h 1067h 106Ah PF P060 P061 P062 P063 P064 P065 P066 P067 P06A -- -- -- Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 T2A INPUT SELECT1 (RW-0) T2A INPUT SELECT0 (RW-0) T2A SW RESET (S-0)
T2A Counter MSbyte T2A Counter LSbyte Compare Register MSbyte Compare Register LSbyte Capture/Compare Register MSbyte Capture/Compare Register LSbyte Capture Register 2 MSbyte Capture Register 2 LSbyte T2A OVRFL INT ENA (RW-0) T2A OVRFL INT FLAG (RC-0)
Dual Compare Mode T2ACTL2 106Bh P06B T2AEDGE1 INT FLAG (RC-0) T2AC2 INT FLAG (RC-0) T2AC1 INT FLAG (RC-0) -- -- T2AEDGE1 INT ENA (RW-0) T2AC2 INT ENA (RW-0) T2AC1 INT ENA (RW-0)
Dual Capture Mode T2AEDGE1 INT FLAG (RC-0) T2AEDGE2 INT FLAG (RC-0) T2AC1 INT FLAG (RC-0) -- -- T2AEDGE1 INT ENA (RW-0) T2AEDGE2 INT ENA (RW-0) T2AC1 INT ENA (RW-0)
Dual Compare Mode T2ACTL3 106Ch P06C T2A MODE= 0 (RW-0) T2AC1 OUT ENA (RW-0) T2AC2 OUT ENA (RW-0) T2AC1 RST ENA (RW-0) T2AEDGE1 OUT ENA (RW-0) T2AEDGE1 POLARITY (RW-0) T2AEDGE1 RST ENA (RW-0) T2AEDGE1 DET ENA (RW-0)
Dual Capture Mode T2A MODE= 1 (RW-0) -- -- T2AC1 RST ENA (RW-0) T2AEDGE2 POLARITY (RW-0) T2AEDGE1 POLARITY (RW-0) T2AEDGE2 DET ENA (RW-0) T2EDGE1 DET ENA (RW-0)
T2APC1
106Dh
P06D -- --
T2AIC2/PWM
--
T2AIC2/PWM
--
T2AIC2/PWM
T2AEVT DATA IN (R-0) T2AIC1/CR DATA IN (R-0) --
T2AEVT DATA OUT (RW-0) T2AIC1/CR DATA OUT (RW-0) --
T2AEVT FUNCTION (RW-0) T2AIC1/CR FUNCTION (RW-0) --
T2AEVT DATA DIR (RW-0) T2AIC1/CR DATA DIR (RW-0) --
T2APC2
106Eh
P06E
T2AIC2/PWM
DATA IN (R-0) T2APRI 106Fh P06F T2A STEST (RP-0)
DATA OUT (RW-0) T2A PRIORITY (RP-0)
FUNCTION (RW-0) --
DATA DIR (RW-0) --
Note:
Shaded boxes can be written to in the privilege mode.
For more information about these registers and control bits, refer to Section 8.8 on page 8-17.
B-10
Peripheral File Frame 7: ADC1 Control Registers
B.10 Peripheral File Frame 7: ADC1 Control Registers
Designation ADCTL ADDR 1070h PF P070 Bit 7 CONVERT START (RW-0) -- ADDATA 1072h 1073h to 107Ch ADIN ADENA ADPRI 107Dh 107Eh 107Fh P072 P073 to P07C P07D P07E P07F AD STEST (RP-0) AD PRIORITY (RP-0) Bit 6 SAMPLE START (RW-0) -- Bit 5 REF VOLT SELECT2 (RW-0) -- Bit 4 REF VOLT SELECT1 (RW-0) -- Bit 3 REF VOLT SELECT0 (RW-0) -- Bit 2 AD INPUT SELECT2 (RW-0) AD READY (R-0) Bit 1 AD INPUT SELECT1 (RW-0) AD INT FLAG (RC-0) Bit 0 AD INPUT SELECT0 (RW-0) AD INT ENA (RW-0)
ADSTAT
1071h
P071
A-to-D Conversion Data Register (R-0) Reserved Port E Data Input Register (R-0) Port E Data Input Enable Register (RW-0) AD ESPEN (RP-0) -- -- -- -- --
Note:
Shaded boxes can be written to in the privilege mode.
For more information about these registers and control bits, refer to Section 12.3 on page 12-9.
Peripheral File Memory Map
B-11
Peripheral File Frame 7: ADC2 Control Registers
B.11
Designation ADCTL
Peripheral File Frame 7: ADC2 Control Registers
ADDR 1070h PF P070 Bit 7 CONVERT START (RW-0) -- Bit 6 SAMPLE START (RW-0) -- Bit 5 -- Bit 4 REF VOLT SELECT1 (RW-0) -- Bit 3 REF VOLT SELECT0 (RW-0) -- Bit 2 -- AD READY (R-0) Bit 1 AD INPUT SELECT1 (RW-0) AD INT FLAG (RC-0) Bit 0 AD INPUT SELECT0 (RW-0) AD INT ENA (RW-0)
ADSTAT
1071h
P071 --
ADDATA
1072h 1073h to 107Ch
P072 P073 to P07C P07D P07E P07F -- -- AD STEST (RP-0) -- -- AD PRIORITY (RP-0) -- -- AD ESPEN (RP-0)
A-to-D Conversion Data Register (R-0) Reserved -- -- -- -- Port E Data Input Register (R-0) Port E Data Input Enable Register (RW-0) -- -- --
ADIN ADENA ADPRI
107Dh 107Eh 107Fh
Note:
Shaded boxes can be written to in the privilege mode.
For more information about these registers and control bits, refer to Section 13.4 on page 13-10.
B-12
Peripheral File Frame 7: ADC3 Control Registers
B.12
Designation ADCTL
Peripheral File Frame 7: ADC3 Control Registers
ADDR 1070h PF P070 Bit 7 CONVERT START (RW-0) -- Bit 6 SAMPLE START (RW-0) -- Bit 5 REF VOLT SELECT1 (RW-0) -- Bit 4 REF VOLT SELECT0 (RW-0) -- Bit 3 AD INPUT SELECT3 (RW-0) -- Bit 2 AD INPUT SELECT2 (RW-0) AD READY (R-0) Bit 1 AD INPUT SELECT1 (RW-0) AD INT FLAG (RC-0) Bit 0 AD INPUT SELECT0 (RW-0) AD INT ENA (RW-0)
ADSTAT
1071h
P071
ADDATA
1072h 1073h to 107Ch
P072 P073 to P07C P07D P07E P07F AD STEST (RP-0) AD PRIORITY (RP-0)
A-to-D Conversion Data Register (R-0) Reserved Port E Data Input Register (R-0) Port E Data Input Enable Register (RW-0) AD ESPEN (RP-0) -- -- -- AD RATE SELECT1 (RW-0) AD RATE SELECT0 (RW-0)
ADIN ADENA ADPRI
107Dh 107Eh 107Fh
Note:
Shaded boxes can be written to in the privilege mode.
For more information about these registers and control bits, refer to Section 14.4 on page 14-11.
Peripheral File Memory Map
B-13
Peripheral File Frame 8: Timer 2B (T2B) Control Registers
B.13
Designation T2BCNTR T2BCNTR T2BC T2BC T2BCC T2BCC T2BIC T2BIC T2BCTL1
Peripheral File Frame 8: Timer 2B (T2B) Control Registers
ADDR 1080h 1081h 1082h 1083h 1084h 1085h 1086h 1087h 108Ah PF P080 P081 P082 P083 P084 P085 P086 P087 P08A -- -- -- Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 T2B INPUT SELECT1 (RW-0) T2B INPUT SELECT0 (RW-0) T2B SW RESET (S-0)
T2B Counter MSbyte T2B Counter LSbyte Compare Register MSbyte Compare Register LSbyte Capture/Compare Register MSbyte Capture/Compare Register LSbyte Capture Register 2 MSbyte Capture Register 2 LSbyte T2B OVRFL INT ENA (RW-0) T2B OVRFL INT FLAG (RC-0)
Dual Compare Mode T2BCTL2 108Bh P08B T2BEDGE1 INT FLAG (RC-0) T2BC2 INT FLAG (RC-0) T2BC1 INT FLAG (RC-0) -- -- T2BEDGE1 INT ENA (RW-0) T2BC2 INT ENA (RW-0) T2BC1 INT ENA (RW-0)
Dual Capture Mode T2BEDGE1 INT FLAG (RC-0) T2BEDGE2 INT FLAG (RC-0) T2BC1 INT FLAG (RC-0) -- -- T2BEDGE1 INT ENA (RW-0) T2BEDGE2 INT ENA (RW-0) T2BC1 INT ENA (RW-0)
Dual Compare Mode T2BCTL3 108Ch P08C T2B MODE= 0 (RW-0) T2BC1 OUT ENA (RW-0) T2BC2 OUT ENA (RW-0) T2BC1 RST ENA (RW-0) T2BEDGE1 OUT ENA (RW-0) T2BEDGE1 POLARITY (RW-0) T2BEDGE1 RST ENA (RW-0) T2BEDGE1 DET ENA (RW-0)
Dual Capture Mode T2B MODE= 1 (RW-0) -- -- T2BC1 RST ENA (RW-0) T2BEDGE2 POLARITY (RW-0) T2BEDGE1 POLARITY (RW-0) T2BEDGE2 DET ENA (RW-0) T2BEDGE1 DET ENA (RW-0)
T2BPC1
108Dh
P08D -- --
T2BIC2/PWM
--
T2BIC2/PWM
--
T2BIC2/PWM
T2BEVT DATA IN (R-0) T2BIC1/CR DATA IN (R-0) --
T2BEVT DATA OUT (RW-0) T2BIC1/CR DATA OUT (RW-0) --
T2BEVT FUNCTION (RW-0) T2BIC1/CR FUNCTION (RW-0) --
T2BEVT DATA DIR (RW-0) T2BIC1/CR DATA DIR (RW-0) --
T2BPC2
108Eh
P08E
T2BIC2/PWM
DATA IN (R-0) T2BPRI 108Fh P08F T2B STEST (RP-0)
DATA OUT (RW-0) T2B PRIORITY (RP-0)
FUNCTION (RW-0) --
DATA DIR (RW-0) --
Note:
Shaded boxes can be written to in the privilege mode.
For more information about these registers and control bits, refer to Section 8.8 on page 8-17.
B-14
Running Title--Attribute Reference
Appendix C Appendix A
Block Diagrams
This appendix summarizes the block diagrams of the major circuits.
Topic
C.1 C.2 C.3 C.4 C.5 C.6 C.7 C.8 C.9
Page
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-2 Timer 1 (T1) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-4 Timer 2n (T2n) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-8 Serial Communications Interface 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-10 Serial Communications Interface 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-11 Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-12 Analog-to-Digital Converter 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-13 Analog-to-Digital Converter 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-14 Analog-to-Digital Converter 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-15
Chapter Title--Attribute Reference
C-1
Interrupts
C.1 Interrupts
The block diagram for interrupt 1 is shown in Figure C-1. This interrupt is controlled by the SCCR2 (P012) and INT1 (P017) registers. The control bits for these registers are shown in Section B.2, page B-3.
Figure C-1. Interrupt 1 Block Diagram
P017.0 Enable Wake-up P017.6
External pin connection
NMI
Pin Data 1 1 = Rising D
CLR 1 Q 0
P012.1 NMI enable P017.0 Enable ST Level 2 Int request Level 1 Int request
INT 1 0 = Falling P017.2 Polarity
IE2 1 0
CLR
Write Read INT flag P017.7
Priority Select P017.1 Other Level 2 interrupts Other Level 1 interrupts
IE1
ST Status register Global interrupts Enable bits
This bit is ignored if you are using the hard watchdog option.
C-2
Interrupts
The block diagram for interrupts 2 and 3 is shown in Figure C-2. These interrupts are controlled by the INT2 (P018) and INT3 (P019) registers. The control bits for these registers are shown in Section B.2, page B-3.
Figure C-2. Interrupts 2 and 3 Block Diagram
External pin connection
P018.6 P019.6 Input pin data 1 0
P018.3 P019.3 Data out
Other Level 2 interrupts Other Level 1 interrupts P018.0 P019.0 Enable IE2 ST
Wake-up
INT
(Int 2 or 3 pin)
1 1 = Rising
D Q
1 0 IE1 ST Priority select
Level 2 Int request Level 1 Int request
Data dir P018.4 P019.4
0 = Falling Polarity P018.2 P019.2
CLR
Write Read INT flag P018.7 P019.7
P018.1 P019.1
Status register Global interrupts Enable bits
Block Diagrams
C-3
Timer 1 (T1) Module
C.2 Timer 1 (T1) Module
The prescaler for the T1 module is shown in Figure C-3. The prescaler is controlled by the T1CTL1 register, located at P049 in peripheral file frame 4. The control bits for this register are shown in Section B.5, page B-6. The T1 WD timer is shown in Figure C-4 (a) through (c). The WD timer is controlled by the following registers:
-
WDCNTR (P046 and P047) WDRST (P048) T1CTL1 (P049) T1CTL2 (P04A)
The control bits for these registers are shown in Section B.5, page B-6.
Figure C-3. T1 System Clock Prescaler Block Diagram
Event
Accumulation General-purpose counter clock Frequency (SYSCLK)
External pin connection
4
16
64
256 T1 Select
Prescaler WD Select 4 16 64 256
T1EVT
SYNC WD counter clock
Accumulation Event Note:
For the hard WD option, the 8-bit prescaler provides four possible clock sources by dividing the system clock by 4, 16, 64, or 256.
C-4
Timer 1 (T1) Module
Figure C-4. WD Timer Block Diagrams
(a) Standard WD
WDCNTR.15-0
16-bit WD counter Reset WD OVRFL INT FLAG
T1CTL2.6
Interrupt WD OVRFL INT ENA
T1CTL2.5
Clock prescaler WD reset key
T1CTL1.7 WD OVRFL TAP SEL T1CTL2.7
System reset WD OVRFL RST ENA
WDRST.7-0
(b) Hard WD
WDCNTR.15-0
16-bit WD counter Reset WD OVRFL INT FLAG T1CTL2.5
Clock prescaler WD reset key
T1CTL1.7 WD OVRFL TAP SEL
System reset
WDRST.7-0
(c) Simple Counter
WDCNTR.15-0
16-bit WD counter Reset WD OVFL INT FLAG
T1CTL2.6
Interrupt WD OVRFL INT ENA
T1CTL2.5
T1CTL1.7
Clock prescaler WD reset key WD OVRFL TAP SEL
WDRST.7-0
Block Diagrams
C-5
Timer 1 (T1) Module
The T1 module has two operating modes:
-
Dual compare mode is shown in Figure C-5 Capture/compare mode is shown in Figure C-6
For a summary of the T1 module control registers and bits, refer to Section B.5, page B-6.
Figure C-5. T1: Dual Compare Mode Block Diagram
T1CC.15-0
16-bit LSB capture/compare register MSB T1C2 INT FLAG
Prescaler clock source
T1CTL3.6 T1CTL3.1 T1C2 INT ENA
Output enable
T1CNTR.15-0
LSB MSB 16-bit counter Reset T1C1 RST ENA
Compare= 16 Compare=
T1CTL4.5
T1C2 OUT ENA Toggle 1 Level 2 Int
External pin connection
T1PC2.7-4
T1PWM
T1C1 INT FLAG T1CTL3.5
T1CTL4.6
T1C1 OUT ENA
T1C.15-0
16-bit LSB compare register MSB
T1CTL3.0 T1C1 INT ENA
T1CTL4.3
T1CR OUT ENA
External pin connection
T1CTL2.0 T1 SW RESET
T1CTL4.4
T1PC2.3-0
T1IC/CR
T1CTL4.1 T1CR RST ENA
Edge select
T1 OVRFL INT FLAG T1CTL2.3
T1CTL2.4 T1 OVRFL INT ENA
T1EDGE INT FLAG
T1 PRIORITY T1PRI.6 Level 1 Int 0
T1CTL4.0 T1EDGE DET ENA T1CTL4.2 T1EDGE POLARITY
T1CTL3.7 T1CTL3.2 T1EDGE INT ENA
Note:
The annotations on this diagram identify the register and the bit(s) in the peripheral frame. For example, the actual address of T1CTL2.0 is 104Ah, bit 0, in the T1CTL2 register.
C-6
Timer 1 (T1) Module
Figure C-6. T1: Capture/Compare Mode Block Diagram
T1CC.15-0
Toggle LSB 16-bit capture/compare MSB register T1C1 OUT ENA
External pin connection
T1PC2.7-4
T1PWM
Prescaler clock source
T1CTL4.6
T1CNTR.15-0
LSB MSB 16-bit counter 16 T1C1 INT FLAG Compare= Reset
T1 PRIORITY
T1CTL3.5 T1CTL3.0
T1C.15-0
T1 SW RESET T1C1 T1CTL2.0 RST ENA 16-bit LSB compare register MSB
T1C1 INT ENA
T1 OVRFL INT FLAG
T1CTL4.4
External pin connection
T1CTL2.3 T1CTL2.4
T1 OVRFL INT ENA T1EDGE DET ENA T1EDGE INT FLAG
T1PC2.3-0
T1IC/CR Edge select
T1CTL3.7 T1CTL4.0 T1CTL3.2 T1CTL4.2
T1EDGE POLARITY T1EDGE INT ENA
Block Diagrams
IIII
Level 1 Int 0 1 Level 2 Int
T1PRI.6
C-7
Timer 2n (T2n) Module
C.3 Timer 2n (T2n) Module
The T2n module has two operating modes:
-
Dual compare mode is shown in Figure C-7 Dual capture mode is shown in Figure C-8
For a summary of the T2n module control registers and bits, refer to Section B.9, page B-10.
Figure C-7. T2n: Dual Compare Mode Block Diagram
T2nCC.15-0
16-bit LSB capture/compare register MSB T2nC2 INT FLAG
Clock source
Output enable
T2nCTL2.6 T2nCNTR.15-0
LSB MSB 16-Bit counter Reset T2nC1 RST ENA T2nCTL3.4 Compare= 16 Compare=
T2nCTL3.5
T2nC2 OUT ENA External pin connection
T2nCTL2.1 T2nC2 INT ENA
T2nC1 INT FLAG T2nCTL2.5
Toggle
T2nCTL3.6
T2nC1 OUT ENA
T2nPC2.7-4
T2nIC2/ PWM
T2nC.15-0
16-bit LSB compare register MSB
T2nCTL2.0 T2nC1 INT ENA
T2nCTL3.3
T2nEDGE1 OUT ENA
External pin connection
T2nCTL1.0 T2n SW RESET
T2n OVRFL INT FLAG
T2nPC2.3-0
T2nIC1/ CR
T2nCTL3.1 T2nEDGE1 RST ENA
Edge 1 select
T2nCTL1.3 T2nCTL1.4
T2n OVRFL INT ENA T2nEDGE1 INT FLAG T2n PRIORITY
T2nCTL3.0 T2nEDGE1 DET ENA T2nCTL3.2
T2nEDGE1 POLARITY
T2nPRI.6 Level 1 Int 0
1 Level 2 Int
T2nCTL2.7 T2nCTL2.2 T2nEDGE1 INT ENA
Note:
The annotations on the diagram identify the register and the bit (s) in the peripheral frame. For example, the actual address of T2nCTL2.0 is 106Bh (n=A) or 108Bh (n=B), bit 0, in the T2nCTL2 register.
C-8
Timer 2n (T2n) Module
Figure C-8. T2n: Dual Capture Mode Block Diagram
T2nCC.15-0
16-bit LSB capture/compare register 1 MSB
T2nIC.15-0
16-bit capture register 2 LSB MSB
Clock source
T2nCNTR.15-0
LSB MSB 16-bit counter 16 T2nC1 INT FLAG T2nCTL2.5
T2n PRIORITY T2nPRI.6 Level 1 Int 0 1 Level 2 Int
Compare = Reset
T2nCTL2.0 T2nC.15-0
External pin connections T2n SW RESET T2nCTL1.0 T2nC1 RST ENA 16-bit compare register LSB MSB T2nC1 INT ENA T2n OVRFL INT FLAG T2nCTL1.3
T2nCTL1.4 T2nCTL3.4 T2nCTL3.0 T2nEDGE1 DET ENA
Edge1 select T2n OVRFL INT ENA T2nEDGE1 INT FLAG T2nCTL2.7
T2nPC2.3-0
T2nIC1/CR
T2nCTL3.2 T2nEDGE1 POLARITY T2nCTL3.1 T2nEDGE2 DET ENA
T2nCTL2.2 T2nEDGE1 INT ENA
T2nPC2.7-4
T2nIC2/PWM Edge 2 select
T2nEDGE2 INT FLAG T2nCTL2.6
T2nCTL3.3
T2nEDGE2 POLARITY
T2nCTL2.1
T2nEDGE2 INT ENA
Block Diagrams
C-9
Serial Communications Interface 1
C.4 Serial Communications Interface 1
The block diagram for the SCI1 module is shown in Figure C-9. For a summary of the SCI1 control registers and bits, refer to Section B.7, page B-8.
Figure C-9. SCI1 Block Diagram - Three Pin Configuration
Frame format and mode PARITY EVEN/ ODD ENABLE TXWAKE SCICTL.3 1 WUT 8 TX EMPTY TXCTL.6 TXENA
TXBUF.7 - 0
Transmit data buffer reg. SCI TX Interrupt SCI TX TXRDY INT ENA TXCTL.7
SCITX PRIORITY SCIPRI.6 Level 1 Int
0 1
SCICCR.6 SCICCR.5
TXCTL.0
Level 2 Int
External pin connections
SCIPC2.7 - 4
SCITXD SCITXD
BAUD MSB. 7 - 0
Baud rate MSbyte reg.
TXSHF Reg. CLOCK
SCICTL.1 SCIPC1.3 - 0
SYSCLK
SCICTL.4 BAUD LSB. 7 - 0
Baud rate LSbyte reg. RXSHF reg. RXWAKE RXCTL.1 RXENA RX ERROR SCIRXD SCIRX PRIORITY SCIPRI.5 Level 1 Int
0 1
SCICLK
SCIPC2.3 - 0
SCIRXD
SCI RX interrupt RXRDY RXCTL.6 BRKDT RXCTL.5 SCI RX INT ENA
SCICTL.0
8
RXCTL.7
ERR
RXCTL.4-2
FE OE PE Receive data buffer reg.
RXCTL.0
Level 2 Int
RXBUF.7 - 0
Note: SCI1 registers are described in detail in Section 9.8.1 beginning on page 9-22.
C-10
Serial Communications Interface 2
C.5 Serial Communications Interface 2
The block diagram for the SCI2 module is shown in Figure C-10. For a summary of the SCI2 control register and bits, refer to section B.8, on page B-9.
Figure C-10. SCI2 Block Diagram
Frame format and mode PARITY EVEN/ ODD ENABLE TXWAKE SCICTL.3 1 WUT 8 TX EMPTY TXCTL.6 TXENA
TXBUF.7 - 0
Transmit data buffer reg. SCI TX Interrupt SCI TX TXRDY INT ENA TXCTL.7
SCITX PRIORITY SCIPRI.6 Level 1 Int
0 1
SCICCR.6 SCICCR.5
TXCTL.0
Level 2 Int
External pin connections
SCIPC2.7 - 4
SCITXD SCITXD
BAUD MSB. 7 - 0
Baud rate MSbyte reg.
TXSHF Reg. CLOCK ENA
SCICTL.1
SYSCLK
SCICTL.4 BAUD LSB. 7 - 0
Baud rate LSbyte reg. RXSHF reg. RXWAKE RXCTL.1 RXENA RX ERROR SCIRXD SCIRX PRIORITY SCIPRI.5 Level 1 Int
0 1
SCIPC2.3 - 0
SCIRXD
SCI RX interrupt RXRDY RXCTL.6 BRKDT RXCTL.5 SCI RX INT ENA
SCICTL.0
8
RXCTL.7
ERR
RXCTL.4-2
FE OE PE Receive data buffer reg.
RXCTL.0
Level 2 Int
RXBUF.7 - 0
Block Diagrams
C-11
Serial Peripheral Interface
C.6 Serial Peripheral Interface
The block diagram for the SPI module is shown in Figure C-11. For a summary of the SPI control registers and bits, refer to Section B.4, page B-5.
Figure C-11. SPI Block Diagram
SPIBUF.7-0
SPIBUF buffer register RECEIVER OVERRUN
SPICTL.7
SPIPRI.6
8 SPI INT FLAG
SPICTL.0
LeveI 1 INT 0 1
SPICTL.6
SPIINT ENA
External pin connections
Level 2 INT
SPIDAT data register
SPIPC2.7-4
SPISIMO
SPIDAT.7-0
SPICTL.1 SPIPC2.3-0
TALK SPISOMI
State control
SPI CHAR
SPICCR.2-0
2 System Clock 1 0
MASTER/SLAVE
SPICTL.2 SPIPC1.3-0
SPICCR.5-3
5 4 3
SPICCR.6
CLOCK POLARITY
SPICLK
SPI BIT RATE The diagram is shown in slave mode.
C-12
Analog-to-Digital Converter 1
C.7 Analog-to-Digital Converter 1
The block diagram for the ADC1 module is shown in Figure C-12. For a summary of the ADC1 registers and bits, refer to Section B.10, on page B-11.
Figure C-12. ADC1 Block Diagram
External pin connections
Port E input ENA 0
Port E data AN 0
ADENA.0
AN0
Port E input ENA 1
ADIN.0
2
1
0
SAMPLE START
CONVERT START
ADCTL.2 - 0
Port E data AN 1 AD INPUT SELECT
ADCTL.6
ADCTL.7
ADENA.1
AN1 Port E input ENA 2
ADIN.1
ADENA.2 AN2
Port E input ENA 3
Port E data AN 2
ADIN.2
ADENA.3 AN3
Port E input ENA 4
Port E data AN 3 ADIN.3
AD
ADENA.4 AN4
Port E input ENA 5
Port E data AN 4 ADIN.4
ADDATA.7 - 0
ADC data register AD READY
ADENA.5 AN5
Port E input ENA 6
Port E data AN 5 ADIN.5
ADSTAT.2
AD PRIORITY
Port E data AN 6
ADENA.6 AN6
Port E input ENA 7
ADIN.6
5
4
3
ADPRI.6 Level 1 Int 0
1 Level 2 Int
ADCTL.5 - 3
Port E data AN 7 REF VOLTS SELECT
ADENA.7 AN7 VCC3 VSS3
ADIN.7
AD INT FLAG
ADSTAT.1 ADSTAT.0
AD INT ENA These pins are not implemented in the TMS370Cx4x 40-pin device.
Block Diagrams
C-13
Analog-to-Digital Converter 2
C.8 Analog-to-Digital Converter 2
The block diagram for the ADC2 module is shown in Figure C-13. For a summary of the ADC2 control registers and bits, refer to Section B.11, page B-12.
Figure C-13. ADC2 Block Diagram
External pin connections
Port E input ENA 0
Port E data AN 0
ADENA.0 AN0
Port E input ENA 1
ADIN.0
1
0
SAMPLE START
CONVERT START
ADCTL.1- 0
Port E data AN 1 AD INPUT SELECT
ADCTL.6
ADCTL.7
ADENA.1 AN1
Port E input ENA 2
ADIN.1
Port E data AN 2
ADENA.2 AN2
Port E input ENA 3
ADIN.2
Port E data AN 3
AD
ADENA.3 AN3
ADIN.3 ADDATA.7 - 0
ADC data register 4 3 AD READY
ADCTL.4 - 3
REF VOLTS SELECT
ADSTAT.2
AD PRIORITY
VCC VSS
ADPRI.6 Level 1 Int 0
1 Level 2 Int
AD INT FLAG
ADSTAT.1 ADSTAT.0
AD INT ENA
C-14
Analog-to-Digital Converter 3
C.9 Analog-to-Digital Converter 3
The block diagram for the ADC3 module is shown in Figure C-14. For a summary of the ADC3 control registers and bits, refer to B.12, page B-13.
Figure C-14. ADC3 Block Diagram
External pin connections
Port E input ENA 0
Port E data AN 0
ADENA.0
ADIN.0
AN0
Port E input ENA 1 Port E data AN 1
3
2
1
0
SAMPLE START
CONVERT START
ADCTL.3 - 0
AD INPUT SELECT
ADCTL.6
ADCTL.7
ADENA.1 AN1
ADIN.1
1 0
ADPRI.1 - 0
AD RATE SELECTS Port E input ENA 5
Port E data AN 5
AD
ADENA.5 AN5
Port E input ENA 6
ADIN.5 ADDATA.7 - 0
ADC data register AD READY
Port E data AN 6
ADENA.6 AN6
Port E input ENA 7
ADIN.6
Port E data AN 7
ADENA.7 AN7 AN8 AN9
ADSTAT.2
AD PRIORITY
ADIN.7 ADPRI.6 Level 1 Int 0
5 4 1 Level 2 Int
ADCTL.5 - 4
REF VOLTS SELECT
AN14 VCC3 VSS3
AD INT FLAG
ADSTAT.1 ADSTAT.0
AD INT ENA
Block Diagrams
C-15
C-16
Running Title--Attribute Reference
Appendix D Appendix A
ASCII Character Set
The TMS370 assembler recognizes the following ASCII characters.
ASCII Character Set (7-Bit Code) Least significant i ifi t nibble (LSN) 0 1 2 3 4 5 6 7 8 9 A B C D E F
Note:
Most significant nibble (MSN) 0
(0)
1
(16)
2
(32)
3
(48)
4
(64)
5
(80)
6
(96)
7
(112)
NUL SOH STX ETX EOT ENQ ACK BEL BS HT LF VT FF CR SO SI
DLE DC1 DC2 DC3 DC4 NAK SYN ETB CAN EM SUB ESC FS GS RS US
SP ! " # $ % & ' ( ) * + , - . /
0 1 2 3 4 5 6 7 8 9 : ; < = > ?
@ A B C D E F G H I J K L M N O
P Q R S T U V W X Y Z [ \ ] _
' a b c d e f g h i j k l m n o
p q r s t u v w x y z { | } DEL
To obtain the decimal value, concatenate the decimal MSN to the decimal LSN. For example, a capital A = 4116.
Chapter Title--Attribute Reference
D-1
D-2
Running Title--Attribute Reference
Appendix E Appendix A
Opcode/Instruction Cross-Reference
Table E-1 provides an opcode-to-instruction cross-reference of all 73 mnemonics and 274 opcodes of the TMS370 instruction set. To check the instruction of a known opcode, locate the left (high) digit across the top of the table, then find the right (low) digit along the side of the table. The intersection contains the instruction mnemonic, operands, and byte/cycle peculiar to that opcode. Some opcodes, such as B0, are shared by two instructions, in which case both mnemonics are shown along with the byte/cycles count.
Chapter Title--Attribute Reference
E-1
E-2
Opcode/Instruction Map
Table E-1. TMS370 Family Opcode/Instruction Map
MSN
0 0 JMP ra 2/7 JN ra 2/5 JZ ra 2/5 JC ra 2/5 JP ra 2/5 JPZ ra 2/5 JNZ ra 2/5 JNC ra 2/5 JV ra 2/5 JL ra 2/5 JLE ra 2/5 JHS ra 2/5 MOV Rs,A 2/7 AND Rs,A 2/7 OR Rs,A 2/7 XOR Rs,A 2/7 BTJO Rs,A,ra 3/9 BTJZ Rs,A,ra 3/9 ADD Rs,A 2/7 ADC Rs,A 2/7 SUB Rs,A 2/7 SBB Rs,A 2/7 MOV A,Pd 2/8 MOV #n,A 2/6 AND #n,A 2/6 OR #n,A 2/6 XOR #n,A 2/6 BTJO #n,A,ra 3/8 BTJZ #n,A,ra 3/8 ADD #n,A 2/6 ADC #n,A 2/6 SUB #n,A 2/6 SBB #n,A 2/6 MOV Rs,B 2/7 AND Rs,B 2/7 OR Rs,B 2/7 XOR Rs,B 2/7 BTJO Rs,B,ra 3/9 BTJZ Rs,B,ra 3/9 ADD Rs,B 2/7 ADC Rs,B 2/7 SUB Rs,B 2/7 SBB Rs,B 2/7 MOV Rs,Rd 3/9 AND Rs,Rd 3/9 OR Rs,Rd 3/9 XOR Rs,Rd 3/9 BTJO Rs,Rd,ra 4/11 BTJZ Rs,Rd,ra 4/11 ADD Rs,Rd 3/9 ADC Rs,Rd 3/9 SUB Rs,Rd 3/9 SBB Rs,Rd 3/9 MOV B,Pd 2/8 MOV #n,B 2/6 AND #n,B 2/6 OR #n,B 2/6 XOR #n,B 2/6 BTJO #n,B,ra 3/8 BTJZ #n,B,ra 3/8 ADD #n,B 2/6 ADC #n,B 2/6 SUB #n,B 2/6 SBB #n,B 2/6 MOV B,A 1/8 AND B,A 1/8 OR B,A 1/8 XOR B,A 1/8 BTJO B,A,ra 2/10 BTJZ B,A,ra 2/10 ADD B,A 1/8 ADC B,A 1/8 SUB B,A 1/8 SBB B,A 1/8 1 2 3 4 5 6 7 INCW #n,Rd 3/11 MOV Rs,Pd 3/10 MOV #n,Rd 3/8 AND #n,Rd 3/8 OR #n,Rd 3/8 XOR #n,Rd 3/8 BTJO #n,Rd,ra 4/10 BTJZ #n,Rd,ra 4/10 ADD #n,Rd 3/8 ADC #n,Rd 3/8 SUB #n,Rd 3/8 SBB #n,Rd 3/8 AND A,Pd 2/9 OR A,Pd 2/9 XOR A,Pd 2/9 BTJO A,Pd,ra 3/11 BTJZ A,Pd,ra 3/10 MOVW #16,Rd 4/13 JMPL lab 3/9 MOV &lab,A 3/10 MOV A,&lab 3/10 AND B,Pd 2/9 OR B,Pd 2/9 XOR B,Pd 2/9 BTJO B,Pd,ra 3/10 BTJZ B,Pd,ra 3/10 MOVW Rs,Rd 3/12 JMPL *Rd 2/8 MOV *Rs,A 2/9 MOV A,*Rp 2/9 8 MOV Ps,A 2/8 MOV Ps,B 2/7 MOV Ps,Rd 3/10 AND #n,Pd 3/10 OR #n,Pd 3/10 XOR #n,Pd 3/10 BTJO #n,Pd,ra 4/11 BTJZ #n,Pd,ra 4/11 MOVW #16[B],Rd 4/15 JMPL *lab[B] 3/11 MOV *lab[B],A 3/12 MOV A,*lab[B] 3/12 DEC A 1/8 INC A 1/8 INV A 1/8 CLR A 1/8 XCHB A 1/10 SWAP A 1/11 PUSH A 1/9 POP A 1/9 DJNZ A,ra 2/10 COMPL A 1/8 DEC B 1/8 INC B 1/8 INV B 1/8 CLR B 1/8 XCHB A / TST B 1/10 SWAP B 1/11 PUSH B 1/9 POP B 1/9 DJNZ B,ra 2/10 COMPL B 1/8 9 A B CLRC / TST A 1/9 C MOV A,B 1/9 D MOV A,Rd 2/7 MOV B,Rd 2/7 DEC Rn 2/6 INC Rn 2/6 INV Rn 2/6 CLR Rd 2/6 XCHB Rn 2/8 SWAP Rn 2/9 PUSH Rs 2/7 POP Rd 2/7 DJNZ Rn,ra 3/8 COMPL Rn 2/6 E TRAP 15 1/14 TRAP 14 1/14 TRAP 13 1/14 TRAP 12 1/14 TRAP 11 1/14 TRAP 10 1/14 TRAP 9 1/14 TRAP 8 1/14 TRAP 7 1/14 TRAP 6 1/14 TRAP 5 1/14 TRAP 4 1/14 IDLE 1/6 MOV #n,Pd 3/10 SETC 1/7 RTS 1/9 RTI 1/12 PUSH ST 1/8 F LDST n 2/6 MOV *n[SP],A 2/7 MOV *A,n[SP] 2/7 CMP *n[SP],A 2/8 extend inst,2 opcodes
Opcode/Instruction Cross-Reference
L S N
1
2
3
4
5
6
7
8
9
A
B
All conditional jumps (opcodes 01-0F), BTJO, BTJZ, and DJNZ instructions use two additional cycles if the branch is taken. The BTJO, BTJZ, and DJNZ instructions have a relative address as the last operand. Abbreviations are listed on the next page of this table.
Table E-1. TMS370 Family Opcode/Instruction Map (Concluded)
MSN
0 C JNV ra 2/5 JGE ra 2/5 JG ra 2/5 JLO ra 2/5 1 MPY Rs,A 2/46 CMP Rs,A 2/7 DAC Rs,A 2/9 DSB Rs,A 2/9 2 MPY #n,A 2/45 CMP #n,A 2/6 DAC #n,A 2/8 DSB #n,A 2/8 3 MPY Rs,B 2/46 CMP Rs,B 2/7 DAC Rs,B 2/9 DSB Rs,B 2/9 4 MPY Rs,Rd 3/48 CMP Rs,Rd 3/9 DAC Rs,Rd 3/11 DSB Rs,Rd 3/11 5 MPY #n,B 2/45 CMP #n,B 2/6 DAC #n,B 2/8 DSB #n,B 2/8 6 MPY B,A 1/47 CMP B,A 1/8 DAC B,A 1/10 DSB B,A 1/10 7 MPY #n,Rs 3/47 CMP #n,Rd 3/8 DAC #n,Rd 3/10 DSB #n,Rd 3/10 8 BR lab 3/9 CMP &lab,A 3/11 CALL lab 3/13 CALLR lab 3/15 9 BR *Rd 2/8 CMP *Rs,A 2/10 CALL *Rd 2/12 CALLR *Rd 2/14 A BR *lab[B] 3/11 CMP *lab[B],A 3/13 CALL *lab[B)] 3/15 CALLR *lab[B] 3/17 B RR A 1/8 RRC A 1/8 RL A 1/8 RLC A 1/8 C RR B 1/8 RRC B 1/8 RL B 1/8 RLC B 1/8 D RR Rn 2/6 RRC Rn 2/6 RL Rn 2/6 RLC Rn 2/6 E TRAP 3 1/14 TRAP 2 1/14 TRAP 1 1/14 TRAP 0 1/14 F POP ST 1/8 LDSP 1/7 STSP 1/8 NOP 1/7
L S N
D
E
F
Second byte of two-byte instructions (F4xx):
F4
8
MOVW *n[Rp] 4/15 JMPL *n[Rp] 4/16 MOV *n[Rp],A 4/17 MOV A,*n[Rp] 4/16 BR *n[Rp] 4/17 CMP *n[Rp],A 4/18 CALL *n[Rp] 4/20
DIV Rn,A 3/14-63
F4
9
F4
A
Opcode/Instruction Cross-Reference
E-3
F4 * & # #16 lab n Pd Pn Ps ra Rd Rn Rp Rpd Rps Rs = = = = = = = = = = = = = = = = Indirect addressing operand prefix Direct addressing operand prefix Immediate operand Immediate 16-bit number 16-bit label Immediate 8-bit number Peripheral register containing destination type Peripheral register Peri heral Peripheral register containing source byte Relative address Register containing destination type g Register file Register pair Destination register pair Source register pair Register containing source byte
B
F4
C
F4
D
F4
E
Opcode/Instruction Map
F4
F
CALLR *n[Rp] 4/22
All conditional jumps (opcodes 01-0F), BTJO, BTJZ, and DJNZ instructions use two additional cycles if the branch is taken. The BTJO, BTJZ, and DJNZ instructions have a relative address as the last operand.
E-4
Running Title--Attribute Reference
Appendix F Appendix A
Instruction/Opcode Cross-Reference and Bus Activity Table
This appendix contains both an instruction-to-opcode cross-reference and an instruction bus activity table. The bus activity table specifies the cycle-by-cycle actions of a given instruction.
Topic
F.1 F.2
Page
Instruction/Opcode Cross-Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . F-2 Bus Activity Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F-6
Chapter Title--Attribute Reference
F-1
Instruction / Opcode Cross-Reference
F.1 Instruction/Opcode Cross-Reference
Table F-1 provides an instruction-to-opcode cross-reference of all 73 mnemonics and 274 opcodes of the TMS370 instruction set. The columns are grouped according to addressing modes.
F-2
Table F-1. TMS370 Family Instruction/Opcode Set
Data Manipulation Rd 69 68 63
8C
Program Flow B, Rd # || A, Pd Ps, A B, Pd Ps, B #n, Pd
Other
A 19 18 13 AC 9C EC 23 33 53 43 73 83 93 A3 28 38 58 48 78 29 39 59 49 79
B
A,B
B,A
Rs, A
#n, A
Rs, B
#n, B
Rs, Rd
#n, Rd
A, Rd
k
U O
h
v
ADC
ADD
AND
BR 66 67 8E 9E AE 17 27 37 57 47 77 87 A7 97 EE 16 26 36 56 46 76 86 A6 96
BTJO
BTJZ
CALL
CALLR D5
8F
9F
AF
EF
CLR
B5
C5
CLRC 6D 1D 2D 3D 5D 4D 7D
8D AD 9D ED
B0 F3 75,A5 DB 6E D2 F0 00 F4 F8 DA 6F 1F 2F 3F 5F 4F 7F
F0 0C
CMP
CMPBIT
COMPL 1E 2E 3E 5E 4E 7E
BB
CB
DAC
DEC
B2
C2
DINT
DIV
DJNZ
BA
CA
DSB
EINT
EINTH
F0 04 F0 08 F6 D3 D4 77,A7
EINTL
IDLE
INC
B3
C3
INV
B4
C4
JBIT0
Instruction / Opcode Cross-Reference and Bus Activity Table
#Absolute direct {label (PC)} ||Absolute indexed {label + (B) (PC)}
Direct {(label) (A)} Indexed {(label + (B)) (A)} Indirect {(Rn - 1:Rn) (A)} Offset indirect {(b + (Rn - 1:Rn)) (A)}
Instruction/Opcode Cross-Reference
Rel. direct {PCN + label (PC)} URel. indexed {PCN + label + (B) (A)} kAbsolute indirect {(Rn - 1:Rn) (PC)} ORel. indirect {PCN + (Rn - 1:Rn) (PC)} hAbsolute offset indirect {b + (Rn - 1:Rn) (PC)} vRel. off. indirect {PCN + b + (Rn - 1:Rn) (PC)} Unless otherwise indicated, includes instructions that do not qualify as a data manipulation or program flow addressing mode.
The MOV instruction also includes the following options and their opcodes: Rn,Pn {71}; Pn,Rn {A2}; A,label(B) {AB}; A,n(SP) {F2}; A,n(Rn) {F4 EB}; label,A {8A}; n(SP),A {F1}
The SBIT0 instruction consists of the following options and their opcodes: Rname {73}; Pname {A3} The SBIT1 instruction consists of the following options and their opcodes: Rname {74}; Pname {A4} The TRAP instruction consists of 16 options using operands 0 through 15 with opcodes EFh through E0h, respectively
F-3
Instruction/Opcode Cross-Reference
F-4
Data Manipulation Rd A,B B,A Rs, A 76,A6 00 89 A9 99 E9 03 02 0E 0D 0B 09 0A 0F 01 07 06 0C 04 05 08 FD F0 C0 62 12 22 32 52 42 72 D0 D1 21 80 51 91 F7 8B 88 6C 1C 2C 3C 5C 4C 7C FF 64 D9 D8 14 24 34 54 44 74 84 94 A4 FC FB
AA
Table F-1. TMS370 Family Instruction/Opcode Set (Continued)
Program Flow B, Rd # || A, Pd Ps, A B, Pd Ps, B #n, Pd Other
A
B
#n, A
Rs, B
#n, B
Rs, Rd
#n, Rd
A, Rd
k
U
h
O v
JBIT1
JMP
JMPL
JC
JEQ/JZ
JG
JGE
JHS
JL
JLE
JLO
JN
JNC
JNE/ JNZ
JNV
JP
JPZ
JV
LDSP
LDST 9A A8 98
EA
MOV
E8
MOVW
MPY
NOP
OR
POP
B9
C9
PUSH
B8
C8
Direct {(label) (A)} Indexed {(label + (B)) (A)} Indirect {(Rn - 1:Rn) (A)} Offset indirect {(b + (Rn - 1:Rn)) (A)}
Rel. direct {PCN + label (PC)} URel. indexed {PCN + label + (B) (A)} kAbsolute indirect {(Rn - 1:Rn) (PC)} ORel. indirect {PCN + (Rn - 1:Rn) (PC)} hAbsolute offset indirect {b + (Rn - 1:Rn) (PC)} vRel. off. indirect {PCN + b + (Rn - 1:Rn) (PC)} Unless otherwise indicated, includes instructions that do not qualify as a data manipulation or program flow addressing mode. #Absolute direct {label (PC)} ||Absolute indexed {label + (B) (PC)}
The MOV instruction also includes the following options and their opcodes: Rn,Pn {71}; Pn,Rn {A2}; A,label(B) {AB}; A,n(SP) {F2}; A,n(Rn) {F4 EB}; label,A {8A}; n(SP),A {F1}
The SBIT0 instruction consists of the following options and their opcodes: Rname {73}; Pname {A3} The SBIT1 instruction consists of the following options and their opcodes: Rname {74}; Pname {A4} The TRAP instruction consists of 16 options using operands 0 through 15 with opcodes EFh through E0h, respectively
Table F-1. TMS370 Family Instruction/Opcode Set (Continued)
Data Manipulation Rd DE DF DC DD FA F9 6B 1B 2B 3B 5B 4B 7B A,B B,A Rs, A # || #n, A Rs, B #n, B Rs, Rd #n, Rd A, Rd B, Rd A, Pd Ps, A B, Pd Ps, B #n, Pd Program Flow Other
A
B
k
U O v
h
RL
BE
CE
RLC
BF
CF
RR
BC
CC
RRC
BD
CD
RTI
RTS
SBB
SBIT0

F8 FE 6A D7 1A 2A 3A 5A 4A 7A
SBIT1
SETC
STSP
SUB
SWAP
B7
C7
TRAP
D6 65 15 25 35 55 45 75 85 95 A5
TST
B0
C6
XCHB
B6
C6
XOR
Direct {(label) (A)} Indexed {(label + (B)) (A)} Indirect {(Rn - 1:Rn) (A)} Offset indirect {(b + (Rn - 1:Rn)) (A)}
Rel. direct {PCN + label (PC)} URel. indexed {PCN + label + (B) (A)} kAbsolute indirect {(Rn - 1:Rn) (PC)} ORel. indirect {PCN + (Rn - 1:Rn) (PC)} hAbsolute offset indirect {b + (Rn - 1:Rn) (PC)} vRel. off. indirect {PCN + b + (Rn - 1:Rn) (PC)} Unless otherwise indicated, includes instructions that do not qualify as a data manipulation or program flow addressing mode. #Absolute direct {label (PC)} ||Absolute indexed {label + (B) (PC)}
Instruction / Opcode Cross-Reference and Bus Activity Table
The MOV instruction also includes the following options and their opcodes: Rn,Pn {71}; Pn,Rn {A2}; A,label(B) {AB}; A,n(SP) {F2}; A,n(Rn) {F4 EB}; label,A {8A}; n(SP),A {F1}
Instruction/Opcode Cross-Reference
The SBIT0 instruction consists of the following options and their opcodes: Rname {73}; Pname {A3} The SBIT1 instruction consists of the following options and their opcodes: Rname {74}; Pname {A4} The TRAP instruction consists of 16 options using operands 0 through 15 with opcodes EFh through E0h, respectively
F-5
Bus Activity Table
F.2 Bus Activity Table
The TMS370 family employs a microcoded instruction set. Each instruction is broken down into microcode states, and a miniprogram is executed for the instruction using these states. Each microcode state lasts for one internal clock cycle and includes provisions for conditional jumps, branching, and control of internal CPU operations. To increase efficiency and variety, each instruction can use sections of common microcode states (similar to subroutines). Table F-2 and Table F-3 explain the abbreviations used, while Table F-4 provides a cycle-by-cycle accounting for each of the 274 instruction and operand combinations for the TMS370 family microcontrollers. Each line in Table F-4 consists of the opcode value, the mnemonic and operands, and a summary of all the cycles. Table F-4 gives the minimum time for each instruction by showing the number of internal states. Each state lasts for four CLKIN or crystal periods, so each state represents 200 ns for a crystal running at 5 MHz SYSCLK. This time may increase if the application uses the autowait mode, peripheral autowait mode, or wait pin. The wait modes affect only the "<<" cycles that access external memory. The instructions are typically expressed in this format: OPCODE INSTR O1[,O2][,O3] Operands are always read in increasing address order. This distinction is especially important for the MOV Rs,Pd and the MOV Ps,Rd instructions, in which the operands are in reversed address order. A and B are implied operands and do not require additional bytes. The operand symbols used in Table F-4 are as follows:
* & # #16n lab n Pd Pn Ps ra Rd Rn Rp Rpd Rps Rs F-6 = = = = = = = = = = = = = = = = Indirect addressing operand prefix Direct addressing operand prefix Immediate operand Immediate 16-bit number 16-bit label Immediate 8-bit number Peripheral register containing destination byte Peripheral register Peripheral register containing source byte Relative address (8-bit immediate offset value) Register containing destination byte Register file Register pair Destination register pair Source register pair Register containing source byte
Bus Activity Table
The two-letter abbreviations used in each line are divided into two groups.
-
The first group (shown in Table F-2) generates valid external bus cycles when accessing external memory. The second group (shown in Table F-3) operates only internally and does not generate valid bus cycles, because internal memory accesses do not give valid external bus cycles.
Table F-2. Possible Bus Cycles
Name OC PO On PF Pr Pw Lr Lw Vr << Opcode read Pseudo-operand read Operand n read Prefix byte Peripheral read Peripheral write Long read Long write Vector read Continuation Long Long Long Long Long Long Type Long Long Long Description Opcode fetch, OCF, active during this cycle. Operand is read then discarded, and PC does not advance. Operand usually becomes an opcode on next instruction cycle. Read instruction's operands (n=operand order in instruction). First byte of a two-byte opcode. OCF is active during this cycle and not during next OC cycle. Always 0F4h. Read of 1000h-10FFh. The external reads are affected by PF autowait. Write to 1000h-10FFh. The external writes are affected by PF autowait. General long read, range of 0-0FFFFh. General long write, range of 0-0FFFFh. Reads vectors in trap table (7FC0h-7FDFh). Finish memory access, nominal one cycle. If external memory is accessed using autowait, PF autowait, or external wait signals, it could require two or more cycles. Only cycle type affected by wait modes.
Table F-3. Internal Cycles
Name IC RJ SH SP Sr Ar Br Rr Aw Bw Internal cycle Relative jump Stack push Stack pop Stack read Register A read Register B read Register read Register A write Register B write Type Other Other Other Other Other Description Indeterminate internal operation Add these if jump is taken; takes two cycles, so they always come in pairs. (SP)+1 -> (SP); n -> ((SP)) ((SP)) -> n ; (SP)-1 -> (SP) ((SP)) usually dummy cycle
Register 1-cycle register accesses Register 1-cycle register accesses Register 1-cycle register accesses Register 1-cycle register accesses Register 1-cycle register accesses Register 1-cycle register accesses
Rw Register write
Instruction / Opcode Cross-Reference and Bus Activity Table
F-7
Bus Activity Table
F-8
7 Rr Ar Aw Bw << Rr Rw Aw Rr Pw << << Rw IC Rr Rr RJ RJ RJ RJ RJ RJ RJ RJ RJ RJ RJ RJ IC IC IC Rr 12 RJ RJ RJ IC IC << RJ RJ RJ RJ RJ RJ << << Rw Pw Aw Pw Rw Rw Rr Ar Aw Bw << Rw Aw 8 9 10 . . . . . . . . . 11 12 13 14 16 17 18 19 21 22 IC 2 << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << 2 Pr Rr << Ar << Aw Bw << IC IC Br O1 O2 O2 Pr Rr << Ar << IC IC << O2 O2 Pr Rr << Ar << IC IC << IC IC Br O1 7 Rr IC IC IC << << << << IC IC IC IC O2 O2 Rr << << << IC IC IC IC O2 O2 Rr SH IC IC << 8 IC IC O2 RJ RJ IC O3 O2 O1 O2 << << IC RJ RJ IC O3 O2 O1 O2 << << IC IC SH IC O2 9 << RJ RJ RJ RJ RJ RJ << IC SH SH Rr 11 RJ IC SH IC 13 IC IC 14 SH 16 IC 17 SH 18 IC 19 . . . . . . << . . . . . . . . . IC << RJ RJ O3 << << << << RJ RJ O3 RJ RJ O3 << << << << RJ RJ O3 SH IC IC << 10 21 22 3 O1 O1 O1 PO O1 O1 O1 O1 O1 O1 PO O1 O1 O1 O1 O1 O1 O1 O1 PO O1 O1 O1 O1 O1 O1 O1 OC O1 O1 O1 O1 O1 PO O1 O1 O1 O1 O1 O1 O1 O1 O1 PO O1 O1 O1 O1 O1 O1 O1 OC 3 4 << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << 4 5 Ar Br O2 Br Rr Rr Rr Ar Br O2 Br Rr Rr Rr Ar Br O2 O2 Ar Br Br Rr Rr Rr Rr O2 O2 IC Ar Br O2 O2 Ar Br Br Rr Rr Rr Ar Br O2 O2 Ar Br Br Rr Rr Rr Rr O2 O2 IC 5 6 Aw Bw << IC Ar Br O2 Aw Bw << IC Ar Br O2 Aw Bw << << Pr IC Pr Ar Br O2 Rr << << IC IC IC << << Pr IC Pr Ar Br O2 IC IC << << Pr IC Pr Ar Br O2 Rr << << IC 6 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . IC . . . . . . . . . . . . . . . . . . . . . . IC IC 15 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IC 20
Table F-4. Bus Activity Table
Code Instruction 1 29 ADC #n,A OC 59 ADC #n,B OC 79 ADC #n,Rd OC 69 ADC B,A OC 19 ADC Rs,A OC 39 ADC Rs,B OC 49 ADC Rs,Rd OC 28 ADD #n,A OC 58 ADD #n,B OC 78 ADD #n,Rd OC 68 ADD B,A OC 18 ADD Rs,A OC 38 ADD Rs,B OC 48 ADD Rs,Rd OC 23 AND #n,A OC 53 AND #n,B OC A3 AND #n,Pd OC 73 AND #n,Rd OC 83 AND A,Pd OC 63 AND B,A OC 93 AND B,Pd OC 13 AND Rs,A OC 33 AND Rs,B OC 43 AND Rs,Rd OC 9C BR *Rp OC 8C BR lab OC AC BR *lab[B] OC F4 EC BR *n[Rp] PF 26 BTJO #n,A,#ra OC 56 BTJO #n,B,#ra OC A6 BTJO #n,Pd,#ra OC 76 BTJO #n,Rd,#ra OC 86 BTJO A,Pd,#ra OC 66 BTJO B,A,#ra OC 96 BTJO B,Pd,#ra OC 16 BTJO Rs,A,#ra OC 36 BTJO Rs,B,#ra OC 46 BTJO Rs,Rd,#ra OC 27 BTJZ #n,A,#ra OC 57 BTJZ #n,B,#ra OC A7 BTJZ #n,Pd,#ra OC 77 BTJZ #n,Rd,#ra OC 87 BTJZ A,Pd,#ra OC 67 BTJZ B,A,#ra OC 97 BTJZ B,Pd,#ra OC 17 BTJZ Rs,A,#ra OC 37 BTJZ Rs,B,#ra OC 47 BTJZ Rs,Rd,#ra OC 9E CALL *Rp OC 8E CALL lab OC AE CALL *lab[B] OC F4 EE CALL *n[Rp] PF code Instruction 1
Table F-4. Bus Activity Table (Continued)
9 IC IC IC IC IC O2 IC 7 IC IC IC Br Br O1 IC IC IC Rr Ar IC Aw 8 IC IC IC IC IC << Aw Bw 11 IC SH SH IC IC Rr 12 SH IC IC IC IC Rr 13 IC SH SH SH SH IC 14 IC IC IC IC IC IC 22
Ar IC << O2 Rr IC IC IC Pw << IC Rr Ar IC
Rr Lr Ar Br IC O1 IC IC << Pr Rr IC IC Rr << Rw Aw Bw
IC << IC IC Lr <<
Code 9F 8F 8F AF AF F4 EF B5 C5 D5 B0 F3 2D 5D 7D 9D 6D AD 8D F4 ED 1D 3D 4D A5 75 BB CB DB 2E 5E 7E 6E 1E 3E 4E B2 C2 D2 F4 F0 F8 F4 F8 IC IC Rr Ar IC IC << IC IC IC IC Aw Bw IC Rw IC O1 O1 << << Aw Bw << Aw Bw IC IC IC IC Rr 8 9 O1 O1 RJ IC IC Aw Bw IC Ar Ar Br Br RJ RJ IC IC RJ RJ IC IC IC Aw Aw Bw IC IC IC IC Rr Aw Bw
Instruction CALLR *Rp CALLR #16n CALLR lab CALLR *16n[B] CALLR *lab[B] CALLR *n[Rp] CLR A CLR B CLR Rd CLRC CMP *n[SP],A CMP #n,A CMP #n,B CMP #n,Rp CMP *Rp,A CMP B,A CMP *lab[B],A CMP &lab,A CMP *n[Rp],A CMP Rs,A CMP Rs,B CMP Rs,Rd CMPBIT Pname CMPBIT Rname COMPL A COMPL B COMPL Rd DAC #n,A DAC #n,B DAC #n,Rd DAC B,A DAC Rs,A DAC Rs,B DAC Rs,Rd DEC A DEC B DEC Rd DINT DIV Rs,A DIV Rs,A
1 OC OC OC OC OC PF OC OC OC OC OC OC OC OC OC OC OC OC PF OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC PF PF
2 << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << <<
3 O1 O1 O1 O1 O1 OC PO PO O1 PO O1 O1 O1 O1 O1 PO O1 O1 OC O1 O1 O1 O1 O1 PO PO O1 O1 O1 O1 PO O1 O1 O1 PO PO O1 PO OC OC
4 << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << <<
5 Rr O2 O2 O2 O2 IC Ar Br Rr Ar IC Ar Br O2 Rr Br O2 O2 IC Rr Rr Rr O2 O2 Ar Br Rr Ar Br O2 Br Rr Rr Rr Ar Br Rr Sr IC IC
6 Rr << << << << IC IC IC Rw IC RJ IC IC << Rr IC << << IC Ar Br O2 << << IC IC Rw IC IC << IC Ar Br O2 IC IC Rw Br IC IC
Instruction / Opcode Cross-Reference and Bus Activity Table
Rw 11 12 13 14 OC OC OC OC OC OC OC OC OC OC OC OC 1 << << << << << << << << << << << << 2 PO PO O1 O1 O1 O1 PO O1 O1 O1 PO PO 3 << << << << << << << << << << << << 4 Ar Br Rr Ar Br O2 Br Rr Rr Rr Sr Sr 5 IC IC Rw IC IC << IC Ar Br O2 Br Br 6 IC IC O2 IC IC Rr Ar IC IC << IC IC 7
Bus Activity Table
F-9
BA DJNZ A,#ra CA DJNZ B,#ra DA DJNZ Rd,#ra 2F DSB #n,A 5F DSB #n,B 7F DSB #n,Rd 6F DSB B,A 1F DSB Rs,A 3F DSB Rs,B 4F DSB Rs,Rd F00C EINT F004 EINTH code Instruction
10 SH IC IC IC IC << . . . . . . . . IC . Lr Ar << . . . << . . . . . . Rw Aw . . IC . . . . Rr Rr . << << RJ . . Rw Aw . . IC . . 10 22
15 16 17 18 19 20 21 . . IC . IC . SH IC IC . SH IC IC . IC IC IC SH IC SH IC . . . . . . (same as TST A instruction) . . . . . . . . . . . . . . . . Lr << Ar IC . . . . . . . (same as XOR #n,Pd instruction) (same as XOR #n,Rn instruction) . . . . . . . . . . . . . . . . . . . . . . . . . (same as LDST 00h instruction) overflow condition . [Bw IC IC IC Aw] ....IC . Repeat Block 55-63 cycles . . . . . . . . . . . . . . . . . . . . (same as LDST 0Ch instruction) (same as LDST 04h instruction) 15 16 17 18 19 20 21
Bus Activity Table
F-10
7 IC IC IC Rr IC IC RJ RJ << IC << IC IC IC IC IC IC << IC IC IC IC O2 IC IC Rr Rr IC IC Pr Rr Pr Rr RJ RJ IC IC IC Br Br O1 IC Rw Aw Pw Aw << Bw Lw IC O2 Lw Rr << Rr IC IC O3 IC O3 << RJ << RJ RJ RJ RJ RJ Rw Aw Bw IC Rw Aw Bw 8 9 10 . . . . . Rr . . 11 12 13 14 IC Rw << Lw Ar Ar IC << << IC Aw << IC << O2 IC << Rr Aw Rr IC IC IC Lr << Aw Bw << 1 OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC PF OC OC OC OC OC OC OC OC OC OC OC OC OC PF OC OC OC OC OC OC OC PF OC OC OC OC OC OC OC OC OC PF 1 << Rr Lr Ar IC IC Br O1 Pw Rw Ar Pw Rw Br IC O1 << << Pr Aw Bw Rr << Br IC O1 7 IC Rr IC O3 << 8 Pw Rw IC << O2 9 << Rw Rr 11 IC IC Rr 12 Rw Rw IC 13 IC IC 14 O3 << O3 << . . . . . IC IC << . . . . . . << . . . . << Ar << . . . . . Lr Aw << . . Rw . . << . O3 IC << 10 2 << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << 2 3 PO PO PO PO O1 O1 PO PO O1 O1 O1 O1 O1 O1 O1 O1 O1 O1 O1 O1 OC PO O1 O1 O1 O1 O1 O1 O1 O1 O1 PO O1 O1 OC O1 O1 PO O1 O1 O1 O1 OC O1 O1 O2r O1 O1 O2p O1 O1 O1 OC 3 4 << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << 4 5 Sr IC Ar Br Rr O2 Ar Br Rr O2 O2 O2 O2 IC IC Rr O2 O2 O2 O2 IC Sr IC IC IC Ar Br IC O2 Rr Rr Br O2 O2 IC Ar Rr Br Br Rr O2 O2 IC Ar Br O1p Rr Rr O1r Rr O2 O2 IC 5 6 Br IC IC IC Rw << IC IC Rw << << << << RJ RJ Rr << << << << IC Br IC Ar Rr Aw Bw O2 << Rr Rr IC << << IC IC Ar IC IC Br << << IC Pr Pr << Ar Br << O2 << << IC 6 15 16 17 18 19 20 (same as LDST 08h instruction) (usually exited by interrupt) . . . . . . . . . . . . . . (same as BTJZ #n,Pd,ra instruction) (same as BTJZ #n,Rn,ra instruction) (same as BTJO #n,Pd,ra instruction) (same as BTJO #n,Rn,ra instruction) . . . . . . . . . . . . . . IC IC . . . . . . . . . . . . . . . . . . . . . . . . . . Ar LW << . . . . . . . . . . . . . . . LR << Aw . . . . . operand order is reversed during assembly . . . . operand order is reversed during assembly . . Rw . . . O3 << IC RW IC RW 15 16 17 18 19 20 21
Table F-4. Bus Activity Table (Continued)
Code Instruction F008 EINTL F6 IDLE B3 INC A C3 INC B D3 INC Rd 70 INCW #n,Rp B4 INV A C4 INV B D4 INV Rd A7 JBIT0 Pname,#ra 77 JBIT0 Rname,#ra A6 JBIT1 Pname,#ra 76 JBIT1 Rname,#ra 01-0F Jcnd #ra 00 JMP #ra 99 JMPL *Rp 89 JMPL #16n 89 JMPL lab A9 JMPL *16n[B] A9 JMPL *lab[B] F4 E9 JMPL *n[Rp] FD LDSP F0 LDST #n F2 MOV A,*n[SP] F1 MOV *n[SP],A 22 MOV #n,A 52 MOV #n,B F7 MOV #n,Pd 72 MOV #n,Rd 9A MOV *Rp,A 9B MOV A,*Rp C0 MOV A,B 8B MOV A,&lab AB MOV A,*lab[B] F4 EB MOV A,*n[Rpd] 21 MOV A,Pd D0 MOV A,Rd 62 MOV B,A 51 MOV B,Pd D1 MOV B,Rd AA MOV *lab[B],A 8A MOV &lab,A F4 EA MOV *n[Rp],A 80 MOV Ps,A 91 MOV Ps,B A2 MOV Ps,Rd 12 MOV Rs,A 32 MOV Rs,B 71 MOV Rs,Pd 42 MOV Rs,Rd A8 MOVW #16n[B],Rpd 88 MOVW #16n,Rpd E8 MOVW #n[Rp],Rpd code Instruction
Table F-4. Bus Activity Table (Continued)
19 20 . 21 22
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 20 21
Instruction / Opcode Cross-Reference and Bus Activity Table
Code Instruction 98 MOVW Rps,Rpd 2C MPY #n,A 5C MPY #n,B 7C MPY #n,Rd 6C MPY B,A 1C MPY Rs,A 3C MPY Rs,B 4C MPY Rs,Rd FF NOP 24 OR #n,A 54 OR #n,B A4 OR #n,Pd 74 OR #n,Rd 84 OR A,Pd 64 OR B,A 94 OR B,Pd 14 OR Rs,A 34 OR Rs,B 44 OR Rs,Rd B9 POP A C9 POP B D9 POP Rd FC POP ST B8 PUSH A C8 PUSH B D8 PUSH Rs FB PUSH ST BE RL A CE RL B DE RL Rd BF RLC A CF RLC B DF RLC Rd BC RR A CC RR B DC RR Rd BD RRC A CD RRC B DD RRC Rd FA RTI F9 RTS 2B SBB #n,A 5B SBB #n,B 7B SBB #n,Rd 6B SBB B,A 1B SBB Rs,A 3B SBB Rs,B 4B SBB Rs,Rd A3 SBIT0 Pname 73 SBIT0 Rname code Instruction
1 OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC 1
2 << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << 2
3 O1 O1 O1 O1 PO O1 O1 O1 PO O1 O1 O1 O1 O1 PO O1 O1 O1 O1 PO PO O1 PO PO PO O1 PO PO PO O1 PO PO O1 PO PO O1 PO PO O1 PO PO O1 O1 O1 PO O1 O1 O1 O1 O1 3
4 << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << 4
5 6 7 8 9 10 11 12 13 14 15 16 17 18 Rr Rr O2 << IC Rw IC Rw . Ar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 cycles total Br . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 cycles total O2 << Rr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 cycles total Br IC Ar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 cycles total Rr Ar Br IC IC Br Bw IC Aw . . . . . . 46 cycles total Rr Br . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 cycles total Rr O2 << Rr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . 48 cycles total Sr Br IC . . Ar Aw . . Br Bw . . O2 << Pr << Pw << . O2 << Rr Rw . . Ar Pr << Pw << . . Br IC Ar Aw . . Br Pr << Pw << . . Rr Ar Aw . . Rr Br Bw . . Rr O2 << Rr Rw . . Ar IC IC SP Aw . . Br IC IC SP Bw . . Rr SP Rw . . SP Br IC IC . . Ar IC IC IC SH . . Br IC IC IC SH . . Rr IC SH . . Sr Br IC SH . . Ar IC IC Aw . . Br IC IC Bw . . Rr Rw . . Ar IC IC Aw . . Br IC IC Bw . . Rr Rw . . Ar IC IC Aw . . Br IC IC Bw . . Rr Rw . . Ar IC IC Aw . . Br IC IC Bw . . Rr Rw . . SP Br IC SP SP IC IC IC (PCl,PCm, ST) SP Br IC SP IC . (PCl, PCm ) Ar Aw . . Br Bw . . O2 << Rr Rw . . Br IC Ar Aw . . Rr Ar Aw . . Rr Br Bw . . Rr O2 << Rr Rw . . O2 << Pr << Pw << (same as AND #n,Pd) O2 << Rr Rw . (same as AND #n,Rn) 5 6 7 8 9 10 11 12 13 14 15 16 17 18
Bus Activity Table
F-11
Bus Activity Table
F-12
Table F-4. Bus Activity Table (Continued)
Code Instruction A4 SBIT1 Pname 74 SBIT1 Rname F8 SETC FE STSP 2A SUB #n,A 5A SUB #n,B 7A SUB #n,Rd 6A SUB B,A 1A SUB Rs,A 3A SUB Rs,B 4A SUB Rs,Rd B7 SWAP A C7 SWAP B D7 SWAP Rd EF-E0 TRAP #n B0 TST A C6 TST B B6 XCHB A C6 XCHB B D6 XCHB Rd 25 XOR #n,A 55 XOR #n,B A5 XOR #n,Pd 75 XOR #n,Rd 85 XOR A,Pd 65 XOR B,A 95 XOR B,Pd 15 XOR Rs,A 35 XOR Rs,B 45 XOR Rs,Rd code Instruction 1 OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC 1 2 << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << 2 3 O1 O1 PO PO O1 O1 O1 PO O1 O1 O1 PO PO O1 PO PO PO PO PO O1 O1 O1 O1 O1 O1 PO O1 O1 O1 O1 3 4 << << << << << << << << << << << << << << << << << << << << << << << << << << << << << << 4 5 O2 O2 Sr Sr Ar Br O2 Br Rr Rr Rr Ar Br Rr IC Ar Br Ar Br Rr Ar Br O2 O2 Ar Br Br Rr Rr Rr 5 6 << << Br Br Aw Bw << IC Ar Br O2 IC IC IC IC IC IC IC IC Br Aw Bw << << Pr IC Pr Ar Br O2 6 7 Pr Rr IC IC Rr Ar Aw Bw << IC IC IC IC IC IC IC IC Bw Pr Rr << Ar << Aw Bw << 7 8 << Rw Bw Rw Aw Rr IC IC IC IC Ar Br Br Br Rw << Rw Pw Aw Pw Rr 8 Rw IC IC Rw SH Aw Bw Bw Bw 9 Pw 10 << . . . . . . . . . . IC IC . Vr . Bw Aw Bw . . . << . . . . . . . 10 11 12 13 14 15 16 17 18 (same as OR #n,Pd) (same as OR #n,Rn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 16 17 18 19 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 21 22
Aw Bw << SH Vr <<
Pw << << Rw 9
11
12
13
14
19
21
22
The instructions in Table F-4 have the following general characteristics:
-
Opcodes and operands are executed in the same order as in the written instruction. (except MOV Rs,Pd and MOV Ps,Rd). All register pairs are accessed least significant byte first then most significant byte. (n then, n-1). Calls push PCH then PCL. All external writes occur on the last cycle of the instruction. All instructions make at least one operand fetch, even if not needed. The PC does not advance; it treats the pseudo-operand as an opcode on the next opcode fetch. Identified by PO. MPY performs register A,B accesses and internal cycles for the number of cycles shown. DIV execution time depends on the values divided but ranges from 55-63 cycles--fourteen cycles if overflow is detected. Overflow is detected if divisor <= dividend MSB.
Running Title--Attribute Reference
Appendix G Appendix A
Device Pinouts
This appendix provides pinouts for the following individual device categories:
Page
Figure G-1: TMS370Cx0x devices Figure G-2: TMS370Cx1x devices Figure G-3: TMS370Cx2x devices Figure G-4: TMS370Cx32 devices Figure G-5: TMS370Cx36 devices Figure G-6: TMS370Cx4x devices Figure G-7: TMS370Cx5x devices Figure G-8: TMS370Cx6x devices Figure G-9: TMS370Cx7x devices Figure G-10: TMS370Cx8x devices Figure G-11: TMS370Cx9x devices Figure G-12: TMS370CxAx devices Figure G-13: TMS370CxBx devices Figure G-14: TMS370CxCx devices For individual pin descriptions, refer to Chapter 2.
G-2 G-2 G-3 G-4 G-5 G-6 G-7 G-8 G-9 G-10 G-10 G-11 G-12 G-13
Chapter Title--Attribute Reference
G-1
Device Pinouts
Figure G-1. Pinouts for TMS370Cx0x Devices (Top View)
VCC A7 D7 D6 D3 RESET D4
4 3
XTAL2/CLKIN 5 XTAL1 6 A6 7 A5 8 A4 9 A3 10 A2 11
2 1 28 27 26 25 24 23 22 21 20
19 12 13 14 15 16 17 18
SCITXD SPICLK SCIRXD T1IC/CR T1PWM T1EVT MC
Figure G-2. Pinouts for TMS370Cx1x Devices (Top View)
VCC A7 D7 D6 D3 RESET D4
D6 D7 A7 VCC XTAL2/CLKIN
XTAL1
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VSS A1 A0 D5 INT1 INT2 INT3 A. 28-Pin PLCC (FN) B. 28-Pin CLCC (FZ) D3 RESET 4 3 2 1 28 27 26 D4 25 XTAL2/CLKIN 5 SPISOMI 24 6 XTAL1 SPICLK 23 7 A6 SPISIMO 22 8 A5 T1IC/CR 21 9 A4 T1PWM 20 10 A3 T1EVT 19 11 A2 MC 12 13 14 15 16 17 18 INT3 INT2 INT1 D5 VSS A1 A0 D5 INT1 INT2 INT3 C. 28-Pin PLCC (FN) D. 28-Pin CLCC (FZ)
A6 A5 A4 A3 A2 VSS A1 A0
SPISOMI SPICLK SPISIMO T1IC/CR T1PWM T1EVT MC
A. 28-Pin PDIP (N) B. 28-Pin CDIP (JD)
G-2
Device Pinouts
Figure G-3. Pinouts for TMS370Cx2x Devices (Top View)
B2 B3 B4 C0 RESET INT1 INT2 INT3 VCC A7 A6 VSS A5 A4 A3 A2 A1 A0 D7 D4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 B1 B0 SCITXD SCIRXD SCICLK D5 MC XTAL2/CLKIN XTAL1 T1IC/CR T1PWM T1EVT SPISOMI SPISIMO SPICLK B7 B6 B5 D6 D3 RESET C0 B4 B3 B2 B1 B0 SCITXD SCIRXD SCICLK D5 6 5 4 3 2 1 44 43 42 41 40 39 7 38 8 37 9 36 10 35 11 34 12 33 13 32 14 31 15 30 16 29 17 18 19 20 21 22 23 24 25 26 27 28 A2 A1 A0 D7 D4 D3 D6 NC B5 B6 B7
INT1 INT2 INT3 VCC NC A7 A6 VSS A5 A4 A3
MC XTAL2/CLKIN XTAL1 T1IC/CR T1PWM T1EVT NC SPISOMI SPISIMO SPICLK NC
A. 40-Pin PDIP (N) B. 40-Pin CDIP (JD) C. 40-Pin PSDIP (NJ) formerly known as N2 D. 40-Pin CSDIP (JC)
E. 44-Pin PLCC (FN) F. 44-Pin CLCC (FZ)
Device Pinouts
G-3
Device Pinouts
Figure G-4. Pinouts for TMS370Cx32 Devices (Top View)
RESET OP8 OP7 OP6 OP5 OP4 OP3 OP2 OP1 SCITXD CP1 6 5 4 3 2 1 44 43 42 41 40
INT1 INT2 INT3 VCC1 VCC3 A7 A6 VSS1 A5 A4 A3
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
39 38 37 36 35 34 33 32 31 30 29
MC XTAL2/CLKIN XTAL1 CP2 SCIRXD CP6 AN7 AN6 AN5 AN4 VSS3
G-4
A2 A1 A0 D7/CP5 D4/CP3 D3 D6/CP4 AN0 AN1 AN2 AN3
A. 44-Pin PLCC (FN) B. 44-Pin CLCC (FZ)
Device Pinouts
Figure G-5. Pinouts for TMS370Cx36 Devices (Top View)
AN2 AN1 AN0 VSS3 VCC3 VCC1 XTAL1 XTAL2/CLKIN AN3 AN4 AN5 AN6 AN7 D6/CP6 D7/CP5 D4/CP4 D5/CP1 OP1/CP3 OP2/CP2 7 8 9 10 11 12 13 14 15 16 17 VSS1 SCIRXD SCITXD OP3 OP4 OP5 OP6 OP7 OP8 D3 INT1 18 19 20 21 22 23 24 25 26 27 28
VCCSTBY
6 5 4 3 2 1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
A7 A6
A5 A4 A3 A2 A1 A0 MC RESET SPICLK SPISOMI SPISIMO
A. 44-Pin PLCC (FN) B. 44-Pin CLCC (FZ)
Device Pinouts
G-5
Device Pinouts
Figure G-6. Pinouts for TMS370Cx4x Devices (Top View)
B2 T2AEVT T2AIC2/PWM T2AIC1/CR RESET INT1 INT2 INT3 VCC A7 A6 VSS A5 A4 A3 A2 A1 A0 D7 D4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 B1 B0 SCITXD SCIRXD SCICLK D5 MC XTALK2/CLKIN XTAL1 T1IC/CR T1PWM T1EVT AN7 AN6 VCC3 VSS3 AN3 AN2 D6 D3 RESET T2AIC1/CR T2AIC2/PWM T2AEVT B2 B1 B0 SCITXD SCIRXD SCICLK D5 6 5 4 3 2 1 44 43 42 41 40 39 7 38 8 37 9 36 10 35 11 34 12 33 13 32 14 31 15 30 16 29 17 18 19 20 21 22 23 24 25 26 27 28 A2 A1 A0 D7 D4 D3 D6 AN0 AN1 AN2 AN3
INT1 INT2 INT3 VCC VCC3 A7 A6 VSS A5 A4 A3
MC XTAL2/CLKIN XTAL1 T1IC/CR T1PWM T1EVT AN7 AN6 AN5 AN4 VSS3
A. 40-Pin PDIP (N) B. 40-Pin CDIP (JD) C. 40-Pin PSDIP (NJ) formerly known as N2 D. 40-Pin CSDIP (JC)
E. 44-Pin PLCC (FN) F. 44-Pin CLCC (FZ)
G-6
Device Pinouts
Figure G-7. Pinouts for TMS370Cx5x Devices (Top View)
B5 B6 B7 C0 MC C1 C2 VSS1 C3 C4 C5 C6 C7 AN0 A0 A1 A2 A3 A4 A5 A6 A7 T2AEVT T2AIC2/PWM T2AIC1/CR SCICLK SCIRXD SCITXD XTAL2/CLKIN XTAL1 VCC1 VCC3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
D1/CSH3 D3/SYSCLK D4/R/W D6/CSH1/EDS D7/CSE1/WAIT RESET INT1 INT2 INT3 SPISOMI SPISIMO SPICLK T1IC/CR T1PWM AN7 T1EVT VSS1 AN6 AN5 AN4 AN3 AN2 AN1 VSS3
9
8
7
6
5
4
3
2
1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45
C3 C4 C5 C6 C7 VCC2 VSS2 A0 A1 A2 A3 A4 A5 A6 A7 T2AEVT
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
V CC1 D1/CSH3 D2/CSH2 D3/SYSCLK D4/R/W D5/CSPF D6/CSH1/EDS D7/CSE1/WAIT RESET INT1 INT2 INT3 SPISOMI SPISIMO SPICLK T1IC/CR T1PWM T1EVT AN7
V SS1 C2 C1 MC
C0 B7 B6 B5
T2AIC2/PWM
44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
XTAL2/CLKIN XTAL1 V CC1 V CC3
V SS3 AN0 AN1 AN2
B4 B3 B2 B1
B0 D0/CSE2/OCF VSS1 VCC1
A. 64-Pin PSDIP (NM) B. 64-Pin CSDIP (JN)
T2AIC1/CR SCICLK SCIRXD SCITXD
C. 68-Pin PLCC (FN) D. 68-Pin CLCC (FZ)
Device Pinouts
AN3 AN4 AN5 AN6
B0 D0/CSE2/OCF V CC2 V SS2
B4 B3 B2 B1
G-7
Device Pinouts
Figure G-8. Pinouts for TMS370Cx6x Devices (Top View)
B0 T2BIC1/CR V CC2 V SS2 V CC1
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
V SS1 C2 C1
MC C0 B7 B6
6 5 4 3
9
8
7
C3 C4 C5 C6 C7 VCC2 VSS2 A0 A1 A2 A3 A4 A5 A6 A7 T2AEVT T2AIC2/PWM
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
B5 B4 B3 B2 B1
2
1 68 67 66 65 64 63 62 61
T2BIC2/PWM T2BEVT D3/SYSCLK D4/R/W D5/CSPF D6/CSH1/EDS D7/CSE1/WAIT RESET INT1 INT2 INT3 SPISOMI SPISIMO SPICLK T1IC/CR T1PWM T1EVT
SCITXD XTAL2/CLKIN XTAL1 V CC1
V CC3 V SS3 AN0 AN1 AN2
AN3 AN4 AN5 AN6
T2AIC1/CR SCICLK SCIRXD
A. 68-Pin PLCC (FN) B. 68-Pin CLCC (FZ)
G-8
AN7
Device Pinouts
Figure G-9. Pinouts for TMS370Cx7x Devices (Top View)
B5 B6 B7 C0 MC C1 C2 VSS1 C3 C4 C5 C6 C7 AN0 A0 A1 A2 A3 A4 A5 A6 A7 T2AEVT T2AIC2/PWM T2AIC1/CR G0 G1 G2 XTAL2/CLKIN XTAL1 VCC1 VCC3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
D1/CSH3 D3/SYSCLK D4/R/W D6/CSH1/EDS D7/CSE1/WAIT RESET INT1 INT2 INT3 G5 G4 G3 T1IC/CR T1PWM AN7 T1EVT VSS1 AN6 AN5 AN4 AN3 AN2 AN1 VSS3
9
8
7
6
5
4
3
2
1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45
C3 C4 C5 C6 C7 VCC2 VSS2 A0 A1 A2 A3 A4 A5 A6 A7 T2AEVT
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
V CC1 D1/CSH3 D2/CSH2 D3/SYSCLK D4/R/W D5/CSPF D6/CSH1/EDS D7/CSE1/WAIT RESET INT1 INT2 INT3 G5 G4 G3 T1IC/CR T1PWM T1EVT AN7
V SS1 C2 C1 MC
C0 B7 B6 B5
T2AIC2/PWM
44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
T2AIC1/CR G0 G1 G2
XTAL2/CLKIN XTAL1 V CC1 V CC3
V SS3
AN0 AN1 AN2
B4 B3 B2 B1
B0 D0/CSE2/OCF VSS1 VCC1
A. 64-Pin PSDIP (NM) B. 64-Pin CSDIP (JN)
C. 68-Pin PLCC (FN) D. 68-Pin CLCC (FZ)
Device Pinouts
AN3 AN4 AN5 AN6
B0 D0/CSE2/OCF V CC2 V SS2
B4 B3 B2 B1
G-9
Device Pinouts
Figure G-10. Pinouts for TMS370Cx8x Devices (Top View)
C2 C3 C4 C5 RESET INT1 INT2 INT3 NC Vcc A7 A6 A5 A4 A3 A2 A1 A0 D7 D4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 C1 C0 B0 B1 B2 B3 MC XTAL2/CLKIN XTAL1 B7 B6 B5 B4 Vss T1IC/CR T1PWM T1EVT D5 D6 D3 RESET C5 C4 C3 C2 C1 C0 B0 B1 B2 B3 6 5 4 3 2 1 44 43 42 41 40 39 7 38 8 37 9 36 10 35 11 34 12 33 13 32 14 31 15 30 16 29 17 18 19 20 21 22 23 24 25 26 27 28 A2 A1 A0 D7 D4 D3 D6 D5 T1EVT T1PWM T1IC/CR
INT1 INT2 INT3 VCC NC A7 A6 VSS A5 A4 A3
MC XTAL2/CLKIN XTAL1 B7 B6 B5 NC B4 C7 C6 NC
A. 40-Pin PDIP (N)
B. 44-Pin PLCC (FN) C. 44-Pin CLCC (FZ)
Figure G-11. Pinouts for TMS370Cx9x Devices (Top View)
A3 A4 A5 A6 A7 RESET INT1 VCC VCC3 VSS3 AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 A2 A1 A0 T1EVT T1PWM MC T1IC/CR XTAL2/CLKIN XTAL1 VSS D7 D5 D4 D6 D3 AN14 AN13 AN12 AN11 AN10 A7 A6 A5 A4 A3 NC A2 A1 A0 T1EVT T1PWM 6 5 4 3 2 1 44 43 42 41 40 39 7 38 8 37 9 36 10 35 11 34 12 33 13 32 14 31 15 30 16 29 17 18 19 20 21 22 23 24 25 26 27 28 AN5 AN6 AN7 AN8 AN9 NC AN10 AN11 AN12 AN13 AN14
RESET INT1 VCC VCC3 VSS3 AN0 AN1 AN2 AN3 AN4 NC
MC T1IC/CR XTAL2/CLKIN NC XTAL1 VSS D7 D5 D4 D6 D3
A. 40-Pin PSDIP (NJ) formerly known as N2 B. 40-Pin CSDIP (JC)
C. 44-Pin PLCC (FN) D. 44-Pin CLCC (FZ)
G-10
Device Pinouts
Figure G-12. Pinouts for TMS370CxAx Devices (Top View)
B2 T2AEVT T2AIC2/PWM T2AIC1/CR RESET INT1 INT2 INT3 VCC A7 A6 VSS A5 A4 A3 A2 A1 A0 D7 D4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 B1 B0 SCITXD SCIRXD SCICLK D5 MC XTAL2/CLKIN XTAL1 T1IC/CR T1PWM T1EVT C0 B7 B6 B5 B4 B3 D6 D3
A. 40-Pin PDIP (N)
Device Pinouts
G-11
Device Pinouts
Figure G-13. Pinouts for TMS370CxBx Devices (Top View)
B5 B6 B7 C0 MC C1 C2 VSS1 C3 C4 C5 C6 C7 AN0 A0 A1 A2 A3 A4 A5 A6 A7 G0 G1 G2 G3 G4 G5 XTAL2/CLKIN XTAL1 VCC1 VCC3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
D1/CSH3 D3/SYSCLK D4/R/W D6/CSH1/EDS D7/CSE1/WAIT RESET INT1 INT2 INT3 H0 G7 G6 T1IC/CR T1PWM AN7 T1EVT VSS1 AN6 AN5 AN4 AN3 AN2 AN1 VSS3
9
8
7
6
5
4
3
2
1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45
C3 C4 C5 C6 C7 VCC2 VSS2 A0 A1 A2 A3 A4 A5 A6 A7 G0 G1
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
V CC1 D1/CSH3 D2/CSH2 D3/SYSCLK D4/R/W D5/CSPF D6/CSH1/EDS D7/CSE1/WAIT RESET INT1 INT2 INT3 H0 G7 G6 T1IC/CR T1PWM T1EVT AN7
V SS1 C2 C1 MC
C0 B7 B6 B5
44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
G2 G3 G4 G5
XTAL2/CLKIN XTAL1 V CC1 V CC3
V SS3 AN0 AN1 AN2
B4 B3 B2 B1
B0 D0/CSE2/OCF VSS1 VCC1
A. 64-Pin PSDIP (NM)
B. 68-Pin PLCC (FN)
G-12
AN3 AN4 AN5 AN6
B0 D0/CSE2/OCF V CC2 V SS2
B4 B3 B2 B1
Device Pinouts
Figure G-14. Pinouts for TMS370CxCx Devices (Top View)
A7 D6 D3 VCC VSS RESET D4
VCC D3 D6 A7 XTAL2/CLKIN
XTAL1
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
A6 A5 A4 A3 A2 D7 A1 A0
VSS RESET 4 3 2 1 28 27 26 D4 25 XTAL2/CLKIN 5 AN3 24 6 XTAL1 AN2 23 7 A6 AN1 22 8 A5 AN0 21 9 A4 SCITXD 20 10 A3 SCIRXD 19 11 A2 MC 12 13 14 15 16 17 18 T1IC/CR T1PWM T1EVT INT1 D7 A1 A0 INT1 T1EVT T1PWM T1IC/CR
AN3 AN2 AN1 AN0 SCITXD SCIRXD MC
A. 28-Pin PDIP (N) B. 28-Pin CDIP (JD)
C. 28-Pin PLCC (FN) D. 28-Pin CLCC (FZ)
Device Pinouts
G-13
G-14
Running Title--Attribute Reference
Appendix H Appendix A
PLCC-to-PGA Socket Pinouts
This appendix shows the pinouts for the standard PLCC-to-PGA sockets that are commonly used in prototype and production applications. You can use these pinouts when you wirewrap your breadboard with a socket. These diagrams make constructing, debugging, and troubleshooting with the TMS370 family quicker and easier. The figures shown in this appendix are for sockets that correspond to the following package types:
Page
28-pin PLCC/CLCC
28-Pin PGA Pinout TMS370Cx0x Device PGA Pinout TMS370Cx1x Device PGA Pinout TMS370CxCx Device PGA Pinout
44-pin PLCC/CLCC
H-2 H-3 H-4 H-5
44-Pin PGA Pinout TMS370Cx2x Device PGA Pinout TMS370Cx32 Device PGA Pinout TMS370Cx36 Device PGA Pinout TMS370Cx4x Device PGA Pinout TMS370Cx8x Device PGA Pinout TMS370Cx9x Device PGA Pinout
68-pin PLCC/CLCC
H-6 H-7 H-8 H-9 H-10 H-11 H-12
68-Pin PGA Pinout TMS370Cx5x Device PGA Pinout TMS370Cx6x Device PGA Pinout TMS370Cx7x Device PGA Pinout TMS370CxBx Device PGA Pinout
H-13 H-14 H-15 H-16 H-17
Chapter Title--Attribute Reference
H-1
PLCC-to-PGA Socket Pinouts
Figure H-1. 28-Pin PGA Pinout
26
28
2
4
25
27
1
3
6
5
23
24
8
7
21
22
10
9
19
20
17
15
13
11
18
16
14
12
Bottom View
H-2
PLCC-to-PGA Socket Pinouts
Figure H-2. TMS370Cx0x Device PGA Pinout
D4
D3
D7
VCC
TXD
RST
D6
A7
XTAL1
XTAL2
RXD
SCICLK
A5
A6
T1PWM
T1IC
A3
A4
MC
T1EVT
INT2
D5
A1
A2
INT3
INT1
A0
VSS
Bottom View
PLCC-to-PGA Socket Pinouts
H-3
PLCC-to-PGA Socket Pinouts
Figure H-3. TMS370Cx1x Device PGA Pinout
D4
D3
D7
VCC
SOMI
RST
D6
A7
XTAL1
XTAL2
SIMO
SPICLK
A5
A6
T1PWM
T1IC
A3
A4
MC
T1EVT
INT2
D5
A1
A2
INT3
INT1
A0
VSS
Bottom View
H-4
PLCC-to-PGA Socket Pinouts
Figure H-4. TMS370CxCx Device PGA Pinout
D4
VSS
D3
A7
AN3
RST
VCC
D6
XTAL1
XTAL2
AN1
AN2
A5
A6
TXD
AN0
A3
A4
MC
RXD
T1PWM
INT1
A1
A2
T1IC
T1EVT
A0
D7
Bottom View
PLCC-to-PGA Socket Pinouts
H-5
PLCC-to-PGA Socket Pinouts
Figure H-5. 44-Pin PGA Pinout
40
42
44
2
4
6
39
41
43
1
3
5
8
7
37
38
10
9
35
36
12
11
33
34
14
13
31
32
16
15
29
30
27
25
23
21
19
17
28
26
24
22
20
18
Bottom View
H-6
PLCC-to-PGA Socket Pinouts
Figure H-6. TMS370Cx2x Device PGA Pinout
D5
RXD
B0
B2
B4
RST
MC
SCICLK
TXD
B1
B3
C0
INT2
INT1
XTAL1
XTAL2
VCC
INT3
T1PWM
T1IC
A7
NC
NC
T1EVT
VSS
A6
SIMO
SOMI
A4
A5
NC
SPICLK
B6
NC
D3
D7
A1
A3
B7
B5
D6
D4
A0
A2
Bottom View
PLCC-to-PGA Socket Pinouts
H-7
PLCC-to-PGA Socket Pinouts
Figure H-7. TMS370Cx32 Device PGA Pinout
CP1
OP1
OP3
OP5
OP7
RST
MC
TXD
OP2
OP4
OP6
OP8
INT2
INT1
XTAL1
XTAL2
VCC1
INT3
RXD
CP2
A7
VCC3
AN7
CP6
VSS1
A6
AN5
AN6
A4
A5
VSS3
AN4
AN2
AN0
D3
CP5
A1
A3
AN3
AN1
CP4
CP3
A0
A2
Bottom View
H-8
PLCC-to-PGA Socket Pinouts
Figure H-8. TMS370Cx36 Device PGA Pinout
A6
VCCSTBY
XTAL1
VCC3
AN0
AN2
A5
A7
XTAL2
VCC1
VSS3
AN1
AN4
AN3
A3
A4
AN6
AN5
A1
A2
D6/CP6
AN7
MC
A0
D4/CP4
D7/CP5
SPICLK
RST
OP1/CP3
D5/CP1
SIMO
SOMI
D3
OP7
OP5
OP3
RXD
OP2/CP2
INT1
OP8
OP6
OP4
TXD
VSS1
Bottom View
PLCC-to-PGA Socket Pinouts
H-9
PLCC-to-PGA Socket Pinouts
Figure H-9. TMS370Cx4x Device PGA Pinout
D5
RXD
B0
B2
T2AIC2
RST
MC
SCICLK
TXD
B1
T2AEVT
T2AIC1
INT2
INT1
XTAL1
XTAL2
VCC
INT3
T1PWM
T1IC
A7
VCC3
AN7
T1EVT
VSS
A6
AN5
AN6
A4
A5
VSS3
AN4
AN2
AN0
D3
D7
A1
A3
AN3
AN1
D6
D4
A0
A2
Bottom View
H-10
PLCC-to-PGA Socket Pinouts
Figure H-10. TMS370Cx8x Device PGA Pinout
B3
B1
C0
C2
C4
RST
MC
B2
B0
C1
C3
C5
INT2
INT1
XTAL1
XTAL2
VCC
INT3
B6
B7
A7
NC
NC
B5
VSS
A6
C7
B4
A4
A5
NC
C6
T1PWM
D5
D3
D7
A1
A3
T1IC
T1EVT
D6
D4
A0
A2
Bottom View
PLCC-to-PGA Socket Pinouts
H-11
PLCC-to-PGA Socket Pinouts
Figure H-11. TMS370Cx9x Device PGA Pinout
T1PWM
A0
A2
A3
A5
A7
MC
T1EVT
A1
NC
A4
A6
INT1
RST
XTAL2
T1IC
VCC3
VCC
XTAL1
NC
AN0
VSS3
D7
VSS
AN2
AN1
D4
D5
AN4
AN3
D3
D6
AN13
AN11
NC
AN8
AN6
NC
AN14
AN12
AN10
AN9
AN7
AN5
Bottom View
H-12
PLCC-to-PGA Socket Pinouts
Figure H-12. 68-Pin PGA Pinout
61
63
65
67
1
3
5
7
9
60
62
64
66
68
2
4
6
8
11
10
58
59
13
12
56
57
15
14
54
55
17
16
52
53
19
18
50
51
21
20
48
49
23
22
46
47
25
24
44
45
42
40
38
36
34
32
30
28
26
43
41
39
37
35
33
31
29
27
Bottom View
PLCC-to-PGA Socket Pinouts
H-13
PLCC-to-PGA Socket Pinouts
Figure H-13. TMS370Cx5x Device PGA Pinout
VCC1
VCC2
B0
B2
B4
B6
C0
C1
VSS1
D1
VSS2
D0
B1
B3
B5
B7
MC
C2
C4
C3
D3
D2
C6
C5
D5
D4
VCC2
C7
D7
D6
A0
VSS2
INT1
RST
A2
A1
INT3
INT2
A4
A3
SIMO
SOMI
A6
A5
T1IC
SPICLK
T2AEVT
A7
T1EVT
T1PWM
AN6
AN4
AN2
AN0
VCC3
XTAL1
TXD
SCICLK
T2AIC2
AN7
AN5
AN3
AN1
VSS3
VCC1
XTAL2
RXD
T2AIC1
Bottom View
H-14
PLCC-to-PGA Socket Pinouts
Figure H-14. TMS370Cx6x Device PGA Pinout
VCC1
VCC2
B0
B2
B4
B6
C0
C1
VSS1
T2BIC2
VSS2
T2BIC1
B1
B3
B5
B7
MC
C2
C4
C3
D3
T2BEVT
C6
C5
D5
D4
VCC2
C7
D7
D6
A0
VSS2
INT1
RST
A2
A1
INT3
INT2
A4
A3
SIMO
SOMI
A6
A5
T1IC
SPICLK
T2AEVT
A7
T1EVT
T1PWM
AN6
AN4
AN2
AN0
VCC3
XTAL1
TXD
SCICLK
T2AIC2
AN7
AN5
AN3
AN1
VSS3
VCC1
XTAL2
RXD
T2AIC1
Bottom View
PLCC-to-PGA Socket Pinouts
H-15
PLCC-to-PGA Socket Pinouts
Figure H-15. TMS370Cx7x Device PGA Pinout
VCC1
VCC2
B0
B2
B4
B6
C0
C1
VSS1
D1
VSS2
D0
B1
B3
B5
B7
MC
C2
C4
C3
D3
D2
C6
C5
D5
D4
VCC2
C7
D7
D6
A0
VSS2
INT1
RST
A2
A1
INT3
INT2
A4
A3
G4
G5
A6
A5
T1IC
G3
T2AEVT
A7
T1EVT
T1PWM
AN6
AN4
AN2
AN0
VCC3
XTAL1
G2
G0
T2AIC2
AN7
AN5
AN3
AN1
VSS3
VCC1
XTAL2
G1
T2AIC1
Bottom View
H-16
PLCC-to-PGA Socket Pinouts
Figure H-16. TMS370CxBx Device PGA Pinout
VCC1
VCC2
B0
B2
B4
B6
C0
C1
VSS1
D1
VSS2
D0
B1
B3
B5
B7
MC
C2
C4
C3
D3
D2
C6
C5
D5
D4
VCC2
C7
D7
D6
A0
VSS2
INT1
RST
A2
A1
INT3
INT2
A4
A3
G7
H0
A6
A5
T1IC
G6
G0
A7
T1EVT
T1PWM
AN6
AN4
AN2
AN0
VCC3
XTAL1
G5
G3
G1
AN7
AN5
AN3
AN1
VSS3
VCC1
XTAL2
G4
G2
Bottom View
PLCC-to-PGA Socket Pinouts
H-17
H-18
Running Title--Attribute Reference
Appendix IA Appendix
PACT.H MACROS
The macros defined in the PACT.H file make it easier to define the initial values for the PACT command/definition area. You can obtain the latest version of this file from the microcontroller bulletin board. This appendix describes how to use these macros.
Topic
I.1 I.2 I.3
Page
General Comments About Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-2 Comments About Specific Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-4 PACT.H Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-5
Chapter Title--Attribute Reference
I-1
General Comments About Macros
I.1
General Comments About Macros
The following subsections discuss generalities about macros including how to address commands and definitions in dual-port RAM, how to define output pins, and how to define actions.
I.1.1
Addressing Commands and Definitions in Dual-Port RAM
The initial value of the command/definition area is usually defined in program memory and then copied to dual-port RAM during the initialization routine. If the values in a command or definition are to be read from or written to while the PACT module is running, the runtime location of that command or definition must be known. Each of the six macros allows for an optional parameter (a register label) that, if passed as a symbol, equates the symbol to the register containing the least significant byte of the command or definition. For example, you can use the MOVW instruction with the register label parameter to change the compare value of a standard compare command from its initial value of 80h to 100h.
stdcmp
movw
80h,op2,enable|opp_act,pwm1len ;if the command ;looks like this
#100h,pwm1len ;this modifies ;the compare value
Often, the code that reads from or writes to the command/definition area is in a separate file from the code that initializes this area. You can make references to specific commands or definitions by declaring the register label parameter as .globreg. Bytes other than the least significant byte in a command or definition can be referenced as offsets from the least significant byte. Likewise, individual bits can be referenced according to the definition of the least significant byte. For example, the byte containing the output pin value of the standard compare command and the bit that enables that command can be referenced in this way:
.globreg pwm1len pwm1pin .equ pwm1len-2 pwm1en .dbit 3,pwm1len-3 ;PWM 1 compare value ;PWM 1 output pin byte ;PWM 1 enable bit
The assembler requires that you declare the global register symbols used in equates are .globreg before using them. You can do this by creating a file that has all of the .globreg symbols at the top, followed by the equates and the bit definitions. This file then can be included at the beginning of the file that defines the command/definition area and again at the beginning of each file that references that area. Using this technique, you have only to reassemble the module that defines the command/definition area. If this area changes, modules that reference specific commands or definitions are corrected at link time. Before the macro is invoked, define the symbols cmd.stand table, so that the macros calculate the final destination of the command or definition.
I-2
General Comments About Macros
I.1.2
Defining Output Pins
The symbols OP1 through OP8 are defined in the PACT.H file to make it easier to read the output pin selected for a specific command. You can use the numbers one through eight or any previously defined symbol that equates to a value in this range. The macros automatically subtract one and then shift the bits into their proper place for the requested command.
I.1.3
Defining Actions
Twenty-three possible actions are equated to numeric values at the beginning of the PACT.H file. The commands and definitions, for which each action is valid, are shown in the comment section beside the equate statement. The | operator concatenates multiple actions. The numeric value assigned to each action is valid only when used in the macro expansion. These symbols should not be used to set or clear the action bits while the PACT module is running.
PACT.H Macros
I-3
Comments About Specific Macros
I.2
Comments About Specific Macros
This section provides specific information about the following commands and definitions:
I.2.1
Standard compare command Conditional compare command Virtual timer definition Baud timer definition
Standard Compare Command
It is not necessary to specify the compare value or the output pin if the enable action is not specified. For example, you can use the standard compare command as a dummy command so that a definition may follow as shown below.
stdcmp ,,nxt_def ;dummy command, next line is a definition
I.2.2
Conditional Compare Command
The time compare value that is passed to this macro is reduced by two before it is encoded into the command. This allows the value that is passed to the macro to more accurately reflect the time delay until the specified actions occur. The time compare value must be greater than or equal to two.
I.2.3
Virtual Timer Definition
The virtual timer period value passed to the macro is reduced by two so that the desired period is achieved. This value must be able to be represented in the maximum value format described in subsection 15.5.2 on page 15-17, Virtual Timers. If you want to have the macro truncate the value to fit into the maximum value format without generating an error, comment out the appropriate error lines in the PACT.H file. The initial timer value is optional; if it is used, it must be an even number.
I.2.4
Baud Timer Definition
The maximum count value for this definition is derived by the equation given in 15.9 on page 15-32. The value obtained must then meet the maximum value format, or an error will be generated. The initial timer value is optional; if it is used, it must be an even number.
I-4
PACT.H Macros
I.3
PACT.H Macros
This section describes a file that contains macro definitions for all PACT commands.
Example I-1. Macro Definitions
;This file contains macro definitions for all PACT commands and definitions. ;All the actions desired in each of the commands/definitions must be passed ;in the macro as they are defined in the following equate table. All the ;actions are passed as one parameter in the macro. These actions are ;concatenated by '|' to form one parameter. These actions can be defined in ;any order. ; ;NOTE: If an action, which is not a valid action for a particular command ; or definition, is used in that command, incorrect assembly may occur ; without flagging an error. ; ;If you want to use different action names, the equate table must be ;modified. ; ; Version 1.00 ;OUTPUT PINS op1 .EQU 1 op2 .EQU 2 op3 .EQU 3 op4 .EQU 4 op5 .EQU 5 op6 .EQU 6 op7 .EQU 7 op8 .EQU 8
PACT.H Macros
I-5
PACT.H Macros
Example I-1. Macro Definitions (Continued)
; ACTIONS VTD BRD OTD SCC CCC DEC clr_pin .EQU 0 ; x x Default condition clr_evt1 .EQU 0 ; x Default condition nxt_def .EQU 1 ; x x x Next entry is a def int_cmp .EQU 2 ; x x Interrupt on compare = int_evt1 .EQU 2 ; x Interrupt on event 1 int_trst .EQU 4 ; x x Interrupt on timer = 0 enable .EQU 8 ; x x x x Enable timer or pin rst_def_tmr .EQU 10h ; x Reset def tmr on evt max rst_def_ev2 .EQU 10h ; x Reset def tmr on evt 2 set_pin .EQU 20h ; x x Set output pin on = set_evt1 .EQU 20h ; x Set output pin on evt1 step .EQU 40h ; x x x Go to half resolution int_evt .EQU 80h ; x Interrupt on each event int_max_evt .EQU 100h; x Interrupt on max event opp_act .EQU 200h; x xOpp action on timer rst int_evt2 .EQU 400h; x Int on event 2 tx .EQU 800h; x Use as TX bit rate rx .EQU 1000h; x Use as RX bit rate vir_cap .EQU 2000h; x Cap virt timer each evt cap_def_ev1 .EQU 2000h; x Cap def timer on event 1 def_cap .EQU 4000h; x Cap def timer on evt max cap_def_ev2 .EQU 4000h; x Cap def timer on event 2 evt_plus1 .EQU 8000h; x Action on event plus 1
I-6
PACT.H Macros
Example I-1. Macro Definitions (Continued)
;STANDARD COMPARE COMMAND ; stdcmp ,,, ; compare value: 16-bit timer compare value ; pin: Output pin selection. (D18-D20) ; Possible actions:enable,set_pin,clr_pin,int_cmp,step, ; nxt_def,int_trst,opp_act ; register label: a symbol to be equated to the register containing the ; least significant byte of this command
.MACRO cmpval,pin,actions,lab .var b1,b2,b3,b4 .if ((pin.v<1)|(pin.v>8))&((actions.v&enable)=enable) ** ERROR, pin selection is illegal ** .endif .if (actions.v&0FD90h)!=0 ** ERROR, illegal action specified ** .endif .asg cmpval.v&0FFh,b1.v .asg (cmpval.v>>8)&0FFh,b2.v .if (pin.v<1)|(pin.v>8) .asg 1,pin.v .endif .asg pin.v-1,pin.v .asg actions.v&63h|pin.v<<2,b3.v .asg actions.v&0Ch|actions.v>>8&2h,b4.v .byte b1.v,b2.v,b3.v,b4.v .if lab.l!=0 .asg cmd_st-$+table+4,b1.v :lab: .equ r:b1.v: .endif .ENDM
STDCMP
;CONDITIONAL COMPARE COMMAND ; CONCMP ,,,, ; ; ; event compare value: 8-bit value compared to the event counter ; time compare value: 16-bit value compared to the referred timer ; pin: Output pin (only pin 1-7 are valid) ; Possible actions: nxt_def,int_cmp,set_pin,clr_pin,evt_plus1 ; register label: a symbol to be equated to the register containing the ; least significant byte of this command
PACT.H Macros
I-7
PACT.H Macros
Example I-1. Macro Definitions (Continued)
CONCMP .MACRO evcmpval,cmpval,pin,actions,lab .var b1,b2,b3,b4 .if (cmpval.v=0)|(cmpval.v=1) ** ERROR, compare value must be greater than 1 ** .endif .asg cmpval.v-2,cmpval.v .if (pin.v>7)|(pin.v<0) ** ERROR, pin selection is illegal ** .endif .if (actions.v&07FDCh)!=0 ** ERROR, illegal action specified ** .endif .if (evcmpval.v>255)|(evcmpval.v<0) ** ERROR, Event counter compare value out of range ** .endif .asg cmpval.v&0FFh,b1.v .asg (cmpval.v>>8)&0FFh,b2.v .if pin.v=0 .asg 7,pin.v .else .asg pin.v-1,pin.v .endif .asg 80h|actions.v&23h|pin.v<<2|actions.v>>9&40h,b3.v .asg evcmpval.v,b4.v .byte b1.v,b2.v,b3.v,b4.v .if lab.l!=0 .asg cmd_st-$+table+4,b1.v :lab: .equ r:b1.v: .endif .ENDM ;DOUBLE EVENT COMMAND ; DEVCMP ,,,, ; ; ; event value 1: 8-bit value compared to the event counter ; event value 2: 8-bit value compared to the event counter ; pin: Output pin ; Possible actions: nxt_def,int_evt1,set_pin,clr_pin,step,opp_act,int_evt2 ; rst_def_ev2,cap_def_ev1,cap_def_ev2,enable, ; register label: a symbol to be equated to the register containing the ; least significant byte of this command
.MACRO e1cmpval,e2cmpval,pin,actions,lab .var b1,b2,b3,b4 .if (e1cmpval.v>255)|(e1cmpval.v<0) ** ERROR, Event compare 1 value out of range ** .endif
DEVCMP
I-8
PACT.H Macros
Example I-1. Macro Definitions (Continued)
.if (e2cmpval.v>255)|(e2cmpval.v<0) ** ERROR, Event compare 2 value out of range ** .endif .asg e1cmpval.v,b1.v .asg e2cmpval.v,b2.v .if (pin.v<1)|(pin.v>8) .asg 1,pin.v ** ERROR, pin selection is illegal ** .endif .asg pin.v-1,pin.v .if (actions.v&09984h)!=0 ** ERROR, illegal action specified ** .endif .asg actions.v&063h|pin.v<<2,b3.v .asg actions.v&18h|actions.v>>8&66h|1,b4.v .byte b1.v,b2.v,b3.v,b4.v .if lab.l!=0 .asg cmd_st-$+table+4,b1.v :lab: .equ r:b1.v: .endif .ENDM
;VIRTUAL TIMER DEFINITION ; virtmr ,,, ; ; period: The period of the virtual timer, the maximum count plus 1 ; Possible actions: enable,int_trst ; initial timer value: 16-bit virtual timer initial value. ; register label: a symbol to be equated to the register containing the ; least significant byte of this definition
.MACRO period,actions,tmrval,lab .var b1,b2,b3,b4 .if (period.v=0)|(period.v=1) ** Error, Max Timer value must be greater than 2 ** .endif .if (actions.v&0FFF3h)!=0 ** ERROR, illegal action specified ** .endif .asg period.v-2,period.v .asg tmrval.v&0FEh,b1.v .asg (tmrval.v>>8)&0FFh,b2.v .if ((period.v>>8)&0FFh) > 1Fh .asg (period.v>>9)&70h|(period.v<<3)&80h|08h,b3.v .if (period.v&0Fh)!=0 ** ERROR, Max. Timer value truncated in last 4 bits ** .endif .else
VIRTMR
PACT.H Macros
I-9
PACT.H Macros
Example I-1. Macro Definitions (Continued)
.asg (period.v<<3)&0F0h|(actions.v&0Ch)>>1,b3.v .if period.v&01h!=0 ** ERROR, Max. Timer value truncated in last bit ** .endif .endif .if tmrval.v&01h!=0 ** ERROR, Timer value truncated in last bit ** .endif .asg b3.v|(actions.v&0Ch)>>1,b3.v .asg (period.v>>5)&0FFh,b4.v .byte b1.v,b2.v,b3.v,b4.v .if lab.l!=0 .asg cmd_st-$+table+4,b1.v :lab: .equ r:b1.v: .endif .ENDM
;BAUD TIMER DEFINITION ; BRTMR ,,, ; ; maximum count: number that determines the baud rate ; initial timer value: 16-bit virtual timer initial value ; Possible actions: RX,TX ; register label: a symbol to be equated to the register containing the ; least significant byte of this definition
BRTMR
** ERROR,
** ERROR,
** ERROR,
** ERROR,
.MACRO maxcount,actions,tmrval,lab .var b1,b2,b3,b4 .if ((actions.v&0E7FFh)!=0) illegal action specified ** .endif .asg tmrval.v&0FEh,b1.v .asg (tmrval.v>>8)&0FFh,b2.v .if ((maxcount.v>>8)&0FFh) > 1Fh .asg (maxcount.v>>9)&70h|(maxcount.v<<3)&80h|08h,b3.v .if maxcount.v&0Fh!=0 Max. Timer value truncated in last 4 bits ** .endif .else .asg (maxcount.v<<3)&0F0h,b3.v .if maxcount.v&01h!=0 Max. Timer value truncated in last bit ** .endif .endif .if tmrval.v&01h!=0 Timer value truncated in last bit ** .endif .asg (maxcount.v>>5)&0FFh,b4.v
I-10
PACT.H Macros
Example I-1. Macro Definitions (Continued)
.asg b3.v|((actions.v&1800h)>>10)|1,b3.v .byte b1.v,b2.v,b3.v,b4.v .iflab.l!=0 .asg cmd_st-$+table+4,b1.v :lab: .equ r:b1.v: .endif .ENDM
;OFFSET TIMER DEFINITION ; OFSTMR ,,, ; ; max event count: The maximum value the event counter may reach before ; being reset. ; Possible actions: step,int_max_evt,enable,rst_def_tmr, ; vir_cap,def_cap,int_evt ; initial value: 16-bit initial timer value ; register label: a symbol to be equated to the register containing the ; least significant byte of this definition
OFSTMR .MACRO maxcount,actions,tmrval,lab .var b1,b2,b3,b4 .if(maxcount.v>255)|(maxcount.v<0) ** ERROR, Maximum event value out of range ** .endif .if((actions.v&09E27h)!=0) ** ERROR, illegal action specified ** .endif .asg (tmrval.v&0FFh|1),b1.v .asg (tmrval.v>>8)&0FFh,b2.v .asg (actions.v&090h)|((actions.v&8)>>1)|(actions.v&40h)>>6,b3.v .asg b3.v|((actions.v&100h)>>7)|((actions.v>>8)&60h),b3.v .asg maxcount.v&0FFh,b4.v .byte b1.v,b2.v,b3.v,b4.v .iflab.l!=0 .asg cmd_st-$+table+4,b1.v :lab: .equ r:b1.v: .endif .ENDM
PACT.H Macros
I-11
I-12
Glossary
Appendix J Appendix A
Glossary
A
absolute addressing mode: An addressing mode in which code or operands produce the actual address. addressing mode: The method by which an instruction calculates the location of its required data. analog-to-digital converter (ADC): An 8-bit successive-approximation converter with internal sample-and-hold circuitry. Also designated as ADC1 (8-channels except the 40-pin TMS370Cx4x devices which have only 4 channels), ADC2 (4-channels), and ADC3 (15-channels). ANSI C: A version of the C programming language that conforms to the C standards defined by the American National Standards Institute. archiver: A software program that allows you to collect several individual files into a single file called an archive library. The archiver also allows you to add, delete, extract, or replace members of the archive library. assembler: A software program that creates a machine-language program from a source file containing assembly language instructions, directives, and macro directives. The assembler substitutes absolute operation codes for symbolic operation codes, and absolute or relocatable addresses for symbolic addresses. assembly language: A symbolic language that describes the binary machine code in a more readable form. Each of the 73 unique instructions of the TMS370 family converts to one machine operation. asynchronous communications mode: An SCI mode that needs no synchronizing clock. This format consists of a start bit followed by data bits, an optional parity bit, and a stop bit. This format is commonly used with RS-232-C communications and PC serial ports.
Glossary
J-1
Glossary
B
baud: The communication speed for serial ports; equivalent to bits per second. BCD: Binary coded decimal. Each 4-bit nibble expresses a digit from 0-9 and usually packs two digits to a byte, giving a range of 0-99. breakpoint, trace, and timing (BTT) features: A set of features supported by the BTT board (included with the XDS/22 emulation system). These features allow you to set hardware breakpoints, collect trace samples, and perform timing analysis. buffer pointer: A 5-bit register in the PACT module peripheral frame that points to the next available location in the circular capture buffer. byte: A sequence of 8 adjacent bits operated upon as a unit.
C
C: A high-level, general-purpose programming language that is useful for writing compilers and operating systems and for programming microprocessors. C compiler: A program that translates C source statements into assembly language source statements. capture register: A timer 2 register that is loaded with the 16-bit counter value on the occurrence of an external input transition. Either edge of the external input can be configured to trigger the capture. chip select: For some blocks of the TMS370 memory map, the most significant bits of the address are pre-decoded to activate chip-select signals. These chip-select signals allow the TMS370 to access external addresses with a minimum of external logic and to perform memory bank selection under software control. circular buffer: A variable length area in the PACT module dual-port RAM that stores the value of a PACT timer when a capture request is made. As new values are captured, they are put into successive locations in the buffer. When the buffer is full, the oldest captures are replaced with newer captures. code conversion utility: A software program that translates a COFF object file into one of several standard ASCII hexadecimal formats suitable for loading into an EPROM programmer.
J-2
Glossary
COFF: Common Object File Format. An implementation of the object file format of the same name developed by AT&T. The TMS370 compiler, assembler, and linker use and generate COFF files. command/definition area: A variable length area in the PACT module dualport RAM that is used to define the actions taken by the PACT module. comment: A source statement (or portion of a source statement) that documents or improves the readability of a source file. Comments are not compiled, assembled, or linked; they have no effect on the object file. CDT370: A low-cost code-development tool that is external to the target system and provides direct control over the TMS370 processor that is on the target system. compare register: A timer 1 or timer 2 register that contains a value that is compared to the counter value. The compare function triggers when the counter matches the contents of the compare register. constant: A value that does not change during execution.
CPU: An 8-bit register-oriented processor with a status register, program counter, and stack pointer. The TMS370 CPU uses the register file, accessed in one bus cycle, as working registers.
D
debugger: A window-oriented software interface that helps you to debug '370 programs running on an emulator, CDT370, or design kit. dedicated capture registers: An area in the PACT module dual-port RAM that stores the value of the default timer at the time of a specified edge on one of the PACT input capture pins. Unlike the circular buffer, the location of the dedicated capture register does not change. default timer (also hardware timer): A 20-bit hardware counter in the PACT module that is incremented by the PACT prescaled clock. design kit: A low-cost tool that allows you to analyze the hardware and software capabilities of the TMS370 family. dual-port RAM: An area in RAM that can be read from and written to by both the TMS370 CPU and the PACT module.
Glossary
J-3
Glossary
E
edge detection: A type of circuitry that senses an active pulse transition on a given timer input and provides appropriate output transitions to the rest of the module. The active transition can be configured to be low-to-high or high-to-low. EEPROM: Electrically erasable programmable read-only memory. Memory that can be programmed and erased under direct program control. EPROM: Erasable programmable read-only memory. Memory that can be programmed under direct program control.
G
gang programmer: An interactive, menu-driven system that provides programming support for on-chip EEPROM or EPROM of the TMS370 microcontrollers in a production environment.
H
halt mode: An operating mode that reduces operating power by stopping the internal clock, which stops processing in all the modules. This is the lowest-power mode in which all register contents are preserved.
I
idle mode: An operating mode in which the CPU stops processing and waits for the next interrupt. It is not a low-power mode. immediate operand: An operand whose actual constant value is specified in the instruction and placed after the opcode in the machine code. index: An 8-bit unsigned number added to a base address to give a final address. instruction: The basic unit of programming that causes the execution of one operation; consists of an opcode and operands, along with optional labels and comments. interrupt: A signal to the CPU that stops the flow of a program and forces the CPU to execute instructions at an address corresponding to the source of the interrupt. When the interrupt is finished, the CPU resumes execution at the point where it was interrupted.
J-4
Glossary
isosynchronous communications mode: An SCI mode in which data transmission is synchronized by a clock signal (SCICLK) common to both the sender and receiver. The format is identical to the asynchronous mode and consists of a start bit, data bits, an optional parity bit, and a stop bit. The term "isochronous" is interchangeable with isosynchronous.
L
label: A symbol that begins in column 1 of a source statement and corresponds to the address of that statement. linker: A software tool that combines object files to form an object module that can be allocated into system memory and executed by the devices. low-power mode: An operating mode that reduces operating power by reducing or stopping the activity of various modules. There are two lowpower modes: halt and standby. LSB: Least significant bit. LSbyte: Least significant byte.
M
machine code: The actual bytes read by the CPU during an instruction execution; usually read by a programmer as hexadecimal bytes. MC pin: Mode control pin. The pin that determines the operating mode of the TMS370 device, depending on the voltage applied to the pin. Twelve volts on the MC pin after reset places the processor in the write-protection override (WPO) mode. memory map: A description of the addresses of the various sections and features of the TMS370 processor. The map depends on the operating mode. microcomputer mode with external expansion: An operating mode in which the address, control, and data memory extend off-chip to access external memory or peripherals. microcomputer single-chip mode: An operating mode in which the device uses only on-chip memory. microcontroller programmer: An interactive, menu-driven system that provides a method of programming TMS370 family devices and EPROMs directly or through an XDS.
Glossary
J-5
Glossary
microprocessor mode with internal program memory: An operating mode in which the on-chip program memory is available to the processor. microprocessor mode without internal program memory: An operating mode in which the on-chip program memory is not available to the processor. The processor must have external memory. mini-SCI: The mini-UART function available in the PACT module. mnemonic: A symbol that represents the opcode part of an assembly language instruction. MSB: Most significant bit. MSbyte: Most significant byte. multiprocessor communications: An SCI format option that enables one processor to efficiently send blocks of data to other processors on the same serial link.
N
NCRF: New Code Release Form. A form that provides TI with information on the custom features of the device (e.g., prototype and production quantities and dates, exceptions to standard electrical specifications, part numbers, symbology, package type, etc.). nested interrupts: The ability of an interrupt to suspend the service routine of a prior interrupt. Nested interrupts are implemented in TMS370 devices by executing an interrupt service routine that uses the EINT, EINTL, or EINTH instructions to set the global interrupt enable bits in the status register. New Code Release Form: See NCRF. nonmaskable interrupt (NMI): An interrupt that causes the processor to execute the NMI routine. On TMS370 devices, INT1 can be configured as an NMI. NRZ (nonreturn to zero) format: A communication format in which the inactive state is a logic state.
J-6
Glossary
O
offset: A signed value that is added to the base operand to give the final address. opcode: Operation code. The first byte of the machine code that describes to the CPU the type of operation and combination of operands. Some TMS370 instructions use 16-bit opcodes. operand: The part of an instruction that tells the programmer where the CPU will fetch or store data. OTP: One-time programmable. A memory that can be programmed only once (compared to an EPROM that is erasable and can be reprogrammed).
P
PACT: Programmable acquisition and control timer module. A timer coprocessor module for the TMS370 microcontroller family. peripheral file (PF): The 128 or 256 bytes of memory, starting at 1000h, that contain the registers that control the on-board peripherals and system configuration. peripheral file frames: A set of sixteen contiguous peripheral file registers, usually related by function. PPM: Pulse-position modulation. A serial signal in which the information is contained in the frequency of a signal with a constant pulse width. By using the timer compare features, a TMS370 device can output a PPM signal with a constant duty cycle without any program intervention. prescaler: A circuit that slows the rate of a clocking source to the counter. The timer 1 prescaler can slow the clocking source by a factor of 4, 16, 64, or 256. privilege mode: A mode immediately following reset in which the program can alter the privileged registers and bits. Once the privilege mode is disabled, these registers cannot be changed before another reset. This mode does not affect the EEPROM or the watchdog registers. program counter (PC): A CPU register that identifies the current statement in the program. prototyping device: A device used before mask-ROM devices are available that has identical functions, pinout, size, and timings to those of the actual device. Programmable memory such as EEPROM or EPROM is used in place of the masked ROM.
Glossary
J-7
Glossary
pulse accumulation: A timer 1 or timer 2 mode that keeps a cumulative count of SYSCLK pulses gated by the T1EVT or T2EVT signal. PWM: Pulse-width modulation. A serial signal in which the information is contained in the width of a pulse of a constant frequency signal. By using the timer compare features, a TMS370 device can output a PWM signal with a constant duty cycle without any program intervention.
R
RAM: Random access memory. ratiometric conversion: An analog-to-digital conversion in which the conversion value is a ratio of the VREF source to the analog input. As VREF is increased, the input voltage needed to give a certain conversion value changes; however, all conversion values keep the same relationship to VREF. referred timer: The timer that a PACT command uses for time comparisons. This is the last timer defined in the PACT command/definition area before the command was encountered, or if no timer has been defined, it is the least significant 16 bits of the hardware timer. register file (RF): The first 128 or 256 bytes of memory that can be accessed by the majority of the instructions. relative addressing mode: An operating mode in which operands and code produce an absolute address at some distance from the current location. RESET pin: A pin that, when held low, starts hardware initialization and insures an orderly software startup. If the MC pin is low when the RESET signal returns high, then the processor enters the microcomputer mode. If the MC pin is high when the RESET signal returns high, then it enters the microprocessor mode. ROM security: Inhibits the reading of the ROM data using any programmer.
S
serial communications interface (SCI): SCI is referred to as SCI1 or SCI2. SCI1 is a built-in serial interface that can be programmed to be asynchronous or isosynchronous. SCI2 is also a built-in serial interface that can only be programmed to be asynchronous. Many timing, data format, and protocol factors are programmable and controlled by the SCI module in operation.
J-8
Glossary
serial peripheral interface (SPI): A built-in serial interface that facilitates communication between networked master and slave CPUs. As in the SCI, the SPI is set up by software; from then on, the CPU takes no part in timing, data format, or protocol. signed integer: tegers. A number system used to express positive and negative in-
stack: The part of the register file used as last-in, first-out memory for temporary variable storage. The stack is used during interrupts and calls to store the current program status. The area occupied by the stack is determined by the stack pointer and by the application program. stack pointer (SP): An 8-bit CPU register that points to the last entry or top of the stack. The SP is automatically incremented before data is pushed onto the stack and decremented after data is popped from the stack. standby mode: A power reduction mode in which the CPU stops processing, but the on-chip oscillator remains active. Timers remain active and can cause the CPU to exit the standby mode. status register (ST): A CPU register that monitors the operation of the instructions and contains the global interrupt enable bits. symbolic debugging: The ability of a software tool to retain symbolic information so that it can be used by a debugging tool such as an XDS/22, a design kit, or a CDT370. symbol table: A portion of a COFF object file that contains information about the symbols that are defined and used by the file.
T
time slots: The internal cycles in which the PACT module can make a 32-bit access to the dual-port RAM. Each command or definition requires one, two, or three time slots. The number of time slots available is a function of the PACT prescaled clock and the frequency of access to the dual-port RAM by the CPU.
U
unsigned integer: A number system used to express positive integers.
Glossary
J-9
Glossary
V
virtual timer: An entry in the PACT command/definition area that creates an independent time base that is incremented by the PACT prescaled clock and cleared upon reaching a maximum value that is set by this definition.
W
WAIT pin: The pin that allows an external device to cause the processor to wait an indefinite number of clock cycles. When the wait line is released, the processor resynchronizes with the rising edge of the clockout signal and continues with the program. wait states, automatic: Extra clock cycles inserted automatically on every external memory access to accommodate peripherals or expansion memory with slower access time than the TMS370 processor. These wait states are governed by two control bits: PF AUTOWAIT (SCCR0.5) and AUTOWAIT DISABLE (SCCR1.4). watchdog timer: A timer option that can be programmed to generate an interrupt when it times out. This function serves as a hardware monitor over the software to prevent a "lost" program and is available in both the timer 1 and PACT modules. If timer 1 does not need a watchdog, this timer can be used as a general-purpose timer. write protect override (WPO): The only mode in which a TMS370 device can modify the on-board EEPROM. The WPO mode is entered when external circuitry applies 12 volts to the MC pin after the device has been reset into one of its normal operating modes.
X
XDS/22: A code-development tool that is external to the target system and provides direct control over the TMS370 processor that is on the target system.
J-10
Index
Index
16-bit register access 7-30, 8-17 28-pin PGA pinout H-2 TMS370Cx1x H-3, H-4, H-5 44-pin PGA pinout H-6 TMS370Cx2x H-7 TMS370Cx3x H-8, H-9 TMS370Cx4x H-10 to H-12 68-pin PGA pinout H-13 TMS370Cx5x H-14 to H-16, H-17 AD INPUT SELECT0-2 bits (ADCTL register) 12-13, 13-12, 14-13 AD INT ENA bit (ADSTAT register) 12-7, 12-14, 13-6, 13-13, 14-7, 14-14 AD INT FLAG bit (ADSTAT register) 12-7, 12-14, 13-6, 13-13, 14-7, 14-14 AD PRIORITY bit (ADPRI register) 12-7, 12-17, 13-6, 13-15, 14-7, 14-16 AD READY bit (ADSTAT register) 12-14, 13-13, 14-14 AD STEST bit (ADPRI register) 12-17, 13-15, 14-16 adapter board (programming) 17-24 ADC (add with carry) instruction 16-33 V bit setting (in ST) 3-6 ADC1 converter module block diagram 12-3 control registers 12-11 to 12-17 ADCTL (analog control) 12-12 to 12-13 ADDATA (analog conversion data) 12-15 ADENA (analog port E input enable) 12-16 ADIN (analog port E data input) 12-15 ADPRI (analog interrupt priority) 12-17, 14-16 ADSTAT (analog status and interrupt) 12-14 overview 12-4 conversion process 12-6, 14-6 digital result 12-6, 12-15, 14-6 example program 12-9 to 12-10 I/O pins 12-5, 14-5 AN0-AN7, 12-5, 12-15 VCC3 , 12-5 VSS3 , 12-5 interrupts 12-7, 14-7 disabling 12-14 enabling 12-14 memory map 12-4 obtaining data 12-8, 14-8 operation 12-5 to 12-8
A
A (R0) register 3-10 during reset sequence 5-20 value during reset 3-11 A/D converter module See also ADC 1, ADC 2, ADC 3 converter module headings block diagram C-13 control registers B-11, B-12, B-13 conversion process, during low-power modes 4-8 description 1-12 interrupts priority level 5-5 vector sources 5-6 selecting, conversion channel 12-13, 13-12, 14-13 timings 18-89 to 18-96 abbreviations, v absolute maximum electrical ratings 18-3 access time EEPROM 3-13, 6-2 program EPROM 3-15 register file 3-11 ACLOCK ENABLE bit (SCICTL register) 10-21 AD ESPEN bit (ADPRI register) 12-17, 13-15, 14-17
Index-1
Index
ADC1 converter module (continued) overview 12-2 to 12-4 physical description 12-2 to 12-3 programming considerations 12-8, 14-8 ratiometric conversion 12-6, 14-6 description 12-6, 14-6 example 12-7 sampling time 12-6, 14-5 selecting positive voltage source 12-12 priority level 12-17, 14-16 starting the conversion 12-12 ADC2 converter module block diagram 13-3 control registers 13-10 to 13-15 ADCTL (analog control) 13-11 to 13-12 ADDATA (analog conversion data) 13-13 ADENA (analog port E input enable) 13-14 ADIN (analog port E data input) 13-14 ADPRI (analog interrupt priority) 13-15 ADSTAT (analog status and interrupt) 13-13 overview 13-4 conversion process 13-5 digital result 13-5, 13-13 example program 13-8 to 13-9 I/O pins 13-5 AN0-AN7, 13-14 interrupts 13-6 disabling 13-13 enabling 13-13 memory map 13-4 obtaining data 13-7 operation 13-5 to 13-7 overview 13-2 to 13-4 physical description 13-2 to 13-3 programming considerations 13-7 ratiometric conversion 13-5 description 13-5 example 13-6 sampling time 13-5 selecting positive voltage source 13-11 priority level 13-15 starting the conversion 13-11 ADC3 converter module block diagram 14-3 control registers 14-11 to 14-17 ADCTL (analog control) 14-12 to 14-13 ADDATA (analog conversion data) 14-15 ADENA (analog port E input enable) 14-16 Index-2
ADC3 converter module (continued) ADIN (analog port E data input) 14-15 ADSTAT (analog status and interrupt) 14-14 overview 14-4 digital result 14-15 example program 14-9 to 14-10 I/O pins, AN0-AN7, 14-15 interrupts disabling 14-14 enabling 14-14 memory map 14-4 operation 14-5 to 14-8 overview 14-2 to 14-4 physical description 14-2 to 14-3 ratiometric conversion, example 14-7 selecting, positive voltage source 14-12 starting the conversion 14-12 ADCTL (analog control) register 12-12 to 12-13, 13-11 to 13-12, 14-12 to 14-13 AD INPUT SELECT0-2 bits 12-13, 13-12, 14-13 CONVERT START bit 12-8, 12-12, 13-7, 13-11, 14-8, 14-12 REF VOLT SELECT0-2 bits 12-12, 13-11, 14-12 SAMPLE START bit 12-8, 13-7, 13-11, 14-8, 14-12 ADD instruction 16-34 V bit setting (in ST) 3-6 ADDATA (analog conversion data) register 12-15, 13-13, 14-15 DATA0-7 bits 12-15, 13-13, 14-15 addition instructions ADC 16-33 ADD 16-34 DAC 16-47 INC 16-57 INCW 16-58 address memory, during microcomputer mode 3-19 ADDRESS/IDLE WUP bit (SCICCR register) 9-8, 9-23, 10-7, 10-19 addressing modes 16-4 to 16-22 additional 16-22 extended 16-15 to 16-22 absolute 16-15
direct 16-11 indexed 16-12 indirect 16-13 offset indirect 16-14
Index
addressing modes (continued) overview 16-4 relative 16-15
direct 16-11 indexed 16-19 indirect 16-20 offset indirect 16-22
general 16-5 to 16-14 immediate 16-9 implied 16-6 overview 16-4 peripheral 16-8 register 16-7 stack pointer relative
assembler 17-4 ordering information 19-25 symbolic debugging 17-4 assembly language instructions addressing modes 16-4 to 16-22 alphabetical summary 16-33 to 16-92 bus activity table F-6 to F-12
bus cycles F-7 internal cycles F-7
cross-reference
instruction/opcode F-2 to F-3 opcode/instruction 16-30 to 16-31, E-1 to E-3
16-10
ADENA (analog port E input enable) register 12-16, 13-14, 14-16 PORT E INPUT ENA0-7 bits 12-16, 13-14, 14-16 ADIN (analog port E data input) register 12-15, 13-14, 14-15 PORT E DATA AN0-7 bits 12-15, 13-14, 14-15 ADPRI (analog interrupt priority) register 12-17, 13-15, 14-16 AD ESPEN bit 12-17, 13-15, 14-17 AD PRIORITY bit 12-7, 12-17, 13-6, 13-15, 14-7, 14-16 AD STEST bit 12-17, 13-15, 14-16 ADSTAT (analog status and interrupt) register 12-14, 13-13, 14-14 AD INT ENA bit 12-7, 12-14, 13-6, 13-13, 14-7, 14-14 AD INT FLAG bit 12-7, 12-14, 13-6, 13-13, 14-7, 14-14 AD READY bit 12-14, 13-13, 14-14 amplitude detector AN0-AN7 pins 4-4 12-5
operation 16-2 overview 16-23 to 16-29 symbol definitions 16-3 tools 17-2 ASYNC ENABLE bit (SCICCR register) 10-18 ASYNC/ISOSYNC bit (SCICCR register) 9-12, 9-22 asynchronous mode 1-11 AUTOWAIT DISABLE bit (SCCR1 register) 4-5 to 4-8, 4-15
B
B (R1) register 3-10 during reset sequence 5-20 exchanging value with another register 16-91 value during reset 3-11 BAUD LSB and BAUD MSB (baud select) registers 9-27, 10-22 BAUD0-7 bits 9-27, 10-22 BAUD8-F bits 9-27, 10-22 BAUD0-7 bits (BAUD LSB register) 9-27, 10-22 BAUD8-F bits (BAUD MSB register) 9-27, 10-22 block diagram 1-21 A/D converter module C-13 ADC1 converter module 12-3 ADC2 converter module 13-3 ADC3 converter module 14-3 hard watchdog 7-25, C-5 interrupt 1, 5-10, C-2 interrupts 2 and 3, 5-11, C-3 PACT module 15-3 SCI module C-10 SCI1 module 9-4 SCI2 module 10-3 SPI module 11-3, C-12 standard watchdog 7-23, C-5
analog-to-digital converter. See A/D converter module AND (logical AND) instruction AP bit (DEECTL register) application board 17-21 6-5 16-35
applications for the TMS370, 1-2 architecture overview 1-7 to 1-12, 3-2 to 3-3 summary of components (by device) archiver 17-2, 17-7 D-1 ASCII table
1-12
Index-3
Index
block diagram (continued) summary of major circuits C-1 to C-15 timer 1 module 7-4 capture/compare mode 7-14, C-7 clock prescaler 7-16, C-4 dual compare mode 7-11, C-6 timer 2 module 8-3 clock sources 8-14 dual capture mode 8-12, C-9 dual compare mode 8-11, C-8 TMS370Cx0x 1-21 TMS370Cx1x 1-22 TMS370Cx2x 1-23 TMS370Cx32, 1-24 TMS370Cx36, 1-25 TMS370Cx4x 1-26 TMS370Cx5x 1-27 TMS370Cx6x 1-28 TMS370Cx7x 1-29 TMS370Cx8x 1-30 TMS370Cx9x 1-31 TMS370CxA 1-32 TMS370CxB 1-33 TMS370CxC 1-34 watchdog simple counter 7-27, C-5 watchdog timer 7-22 BR (branch) instruction 16-36 9-15, 9-29, 10-12, 16-37 16-38 BRKDT bit (RXCTL register) 10-24
BUS STEST bit (SCCR2 register) 4-17 BUSY bit (DEECTL register) 6-4, 6-9 BUSY bit (EPCTL register) 6-12
C
C bit (ST register) 3-5 C compiler. See compiler C source debugger. See debugger CALL instruction 16-39 CALLR (call relative) instruction 16-40 carry bit (C) 3-5 clearing using CLRC 3-7, 16-42 setting using SETC 3-7, 16-85 CDEND (command/definition area end) register 15-42 to 15-43 CMD/DEF AREA END BIT 2-6 bits 15-42 CDFLAGS (command/definition entry flags) register 15-50 CMD/DEF INT 0-7 FLAG bits 15-50 CDIP 19-6, 19-12 CDSTART (command/definition area start) register 15-40 to 15-41 CMD/DEF AREA INT ENA bit 15-40 CMD/DEF AREA START BIT 2-5 bits 15-40 CDT370, 17-2 CDT370 development tool 17-18 capabilities 17-18 hardware 17-18, 17-19 ordering information 19-26 character sets D-1 circuitry buffer 18-5 clock 18-4 constructing with expansion memory 4-6 crystal 18-4 output load 18-4 reset 5-20 to 5-22 with low-voltage detection 5-22 to 5-23 CLCC 19-6, 19-15 CLKOUT signal, definition 4-24 CLOCK bit (SCICTL register) 9-12, 9-16, 9-25, 10-13 clock options, device differences A-3 CLOCK POLARITY bit (SPICCR register) 11-10, 11-14 clock/crystal connections 18-4
BTJO (bit test and jump if one) instruction BTJZ (bit test and jump if zero) instruction BTT (breakpoint trace and timing) buffer circuit, typical 18-5 BUFFER HALF/FULL INT ENA bit (CPPRE register) 15-57 BUFFER HALF/FULL INT FLAG bit (CPPRE register) 15-57 BUFFER POINTER BIT 1-5 bits (BUFPTR register) 15-44 17-13
BUFPTR (buffer pointer) register 15-14 to 15-15, 15-44 to 15-45 BUFFER POINTER BIT 1-5 bits 15-44 bus activity table F-6 to F-12 bus cycles F-7 internal cycles F-7 Index-4
Index
CLR (clear) instruction 16-41 CLRC (clear the carry bit) instruction 16-42 clearing the C bit of ST 3-7 CMD/DEF AREA ENA bit (PACTSCR register) 15-38 CMD/DEF AREA END BIT 2-6 bits (CDEND register) 15-42 CMD/DEF AREA INT ENA bit (CDSTART register) 15-40 CMD/DEF AREA START BIT 2-5 bits (CDSTART register) 15-40 CMD/DEF INT 0-7 FLAG bits (CDFLAGS register) 15-50 CMP (compare) instruction 16-43 to 16-44 status bit values 16-44 V bit setting (in ST) 3-6 CMPBIT (complement bit) instruction 16-45 code conversion utility 17-2, 17-7 COFF 17-4 COLD START bit 4-13 COLD START bit (SCCR0 register) 4-13 as source of reset 5-19 determining source of reset 4-5 command/definition area, file format 15-7 compare instructions CMP 16-43 to 16-44 CMPBIT 16-45 COMPL 16-46 compiler 17-2, 17-8 key features 17-8 optimizations 17-8 ordering information 19-25 COMPL (2s-complement) instruction 16-46 condition flags (C, N, Z, V) 3-6 conditional-jump instuctions, list 16-62 connectors, XDS/22, 17-17 contact options 19-18 CONVERT START bit (ADCTL register) 12-8, 12-12, 13-7, 13-11, 14-8, 14-12 converter socket 17-27, 19-27 CP1 CAPT FALLING EDGE bit (CPCTL1 register) 15-12, 15-52 CP1 CAPT RISING EDGE bit (CPCTL1 register) 15-12, 15-52 CP1 INT ENA bit (CPCTL1 register) 15-12, 15-52 CP1 INT FLAG bit (CPCTL1 register) 15-12, 15-52
CP1-CP6 pins 15-5, 15-12 to 15-14 CP2 CAPT FALLING EDGE bit (CPCTL1 register) 15-12, 15-51 CP2 CAPT RISING EDGE bit (CPCTL1 register) 15-12, 15-51 CP2 INT ENA bit (CPCTL1 register) 15-12, 15-51 CP2 INT FLAG bit (CPCTL1 register) 15-12, 15-51 CP3 CAPT FALLING EDGE bit (CPCTL2 register) 15-12, 15-54 CP3 CAPT RISING EDGE bit (CPCTL2 register) 15-12, 15-54 CP3 INT ENA bit (CPCTL2 register) 15-12, 15-54 CP3 INT FLAG bit (CPCTL2 register) 15-12, 15-54 CP4 CAPT FALLING EDGE bit (CPCTL2 register) 15-12, 15-53 CP4 CAPT RISING EDGE bit (CPCTL2 register) 15-12, 15-53 CP4 INT ENA bit (CPCTL2 register) 15-12, 15-53 CP4 INT FLAG bit (CPCTL2 register) 15-12, 15-53 CP5 CAPT FALLING EDGE bit (CPCTL3 register) 15-12, 15-56 CP5 CAPT RISING EDGE bit (CPCTL3 register) 15-12, 15-56 CP5 INT ENA bit (CPCTL3 register) 15-12, 15-56 CP5 INT FLAG bit (CPCTL3 register) 15-12, 15-56 CP6 CAPT FALLING EDGE bit (CPCTL3 register) 15-12, 15-55 CP6 CAPT RISING EDGE bit (CPCTL3 register) 15-12, 15-55 CP6 EVENT ONLY bit (CPPRE register) 15-58 CP6 INT ENA bit (CPCTL3 register) 15-12, 15-55 CP6 INT FLAG bit (CPCTL3 register) 15-12, 15-55 CPCTL1 (set-up CP control 1) register 15-51 to 15-52 CP1 CAPT FALLING EDGE bit 15-12, 15-52 CP1 CAPT RISING EDGE bit 15-12, 15-52 CP1 INT ENA bit 15-12, 15-52 CP1 INT FLAG bit 15-12, 15-52 CP2 CAPT FALLING EDGE bit 15-12, 15-51 CP2 CAPT RISING EDGE bit 15-12, 15-51 CP2 INT ENA bit 15-12, 15-51 CP2 INT FLAG bit 15-12, 15-51 CPCTL2 (set-up CP control 2) register 15-53 to 15-54 CP3 CAPT FALLING EDGE bit 15-12, 15-54 CP3 CAPT RISING EDGE bit 15-12, 15-54 CP3 INT ENA bit 15-12, 15-54
Index-5
Index
CPCTL2 (set-up CP control 2) register (continued) CP3 INT FLAG bit 15-12, 15-54 CP4 CAPT FALLING EDGE bit 15-12, 15-53 CP4 CAPT RISING EDGE bit 15-12, 15-53 CP4 INT ENA bit 15-12, 15-53 CP4 INT FLAG bit 15-12, 15-53 CPCTL3 (set-up CP control 3) register 15-55 to 15-56 CP5 CAPT FALLING EDGE bit 15-12, 15-56 CP5 CAPT RISING EDGE bit 15-12, 15-56 CP5 INT ENA bit 15-12, 15-56 CP5 INT FLAG bit 15-12, 15-56 CP6 CAPT FALLING EDGE bit 15-12, 15-55 CP6 CAPT RISING EDGE bit 15-12, 15-55 CP6 INT ENA bit 15-12, 15-55 CP6 INT FLAG bit 15-12, 15-55 CPPRE (CP input control) register 15-57 to 15-58 BUFFER HALF/FULL INT ENA bit 15-57 BUFFER HALF/FULL INT FLAG bit 15-57 CP6 EVENT ONLY bit 15-58 EVENT COUNTER SW RESET bit 15-58 INPUT CAPT PRESCALE SELECT1-3 bits 15-57 OP SET/CLR SELECT bit 15-58 CPU accessing program EPROM 6-10 description 1-7 memory map 3-3 overview 3-2 to 3-3 registers 3-4 to 3-7 PC 3-7 SP 3-4 to 3-5 ST 3-5 to 3-7 value during low-power modes 4-8 CPU STEST bit (SCCR2 register) crystal/clock connections CSDIP CSE1 signal, definition CSE2 signal, definition CSH1 signal, definition CSH2 signal, definition CSPF signal, definition 18-4 19-6, 19-13, 19-14 4-24 4-24 4-24 4-24 4-24 4-17
data EEPROM 3-13 to 3-14, 6-2 to 6-9 access time 3-13, 6-2 control registers 6-3 to 6-5
DEECTL 3-14, 6-2, 6-4 to 6-5, 6-6 to 6-9, B-3 WPR 6-2, 6-3 to 6-4, 6-6 to 6-9
definition 3-2 description 1-7 entering a low-power mode 6-7 finding voltage status 6-4, 6-9 loading a data byte 6-6
example 6-8
preventing data corruption 6-9 programming 3-14, 6-2, 6-6 to 6-9
calculating loop delay 6-9 devices with multiple 256-byte arrays 6-5 devices with single 256-byte array 6-5 example 6-7 to 6-9 initiating 6-6, 6-8
reading 6-2
after voltage is stabilized 6-9
write protection 3-13, 6-2, 6-3 to 6-4
overriding 6-4 programming example 6-4
memory, during microcomputer mode DATA BUS signal, definition data sheets, part numbers, vii DATA0-7 bits (ADDATA register) 14-15 4-24
3-19
12-15, 13-13,
debugger 17-2, 17-9 to 17-11 basic display 17-9 breakpoint, trace, and timing functions 17-13 to 17-17 key features 17-13 to 17-17 key features 17-10 to 17-12 symbolic debugging 17-4 DEC (decrement) instruction V bit setting (in ST) 3-6 16-48 3-12 3-14,
decimal designator (peripheral file)
DEECTL (data EEPROM control) register 6-2, 6-4 to 6-5, 6-6 to 6-9 AP bit 6-5 BUSY bit 6-4, 6-9 EXE bit 6-5, 6-6, 6-8 W1W0 bit 6-5, 6-6, 6-8 DEFTIM OVRFL INT ENA bit (PACTSCR register) 15-38 16-47 DEFTIM OVRFL INT FLAG bit (PACTSCR register) 15-38
D
DAC (decimal add with carry) instruction Index-6
Index
design kit 17-2, 17-20 to 17-23 board (illustrated) 17-21 capabilities 17-20 operating modes debugger 17-22 isolated 17-23 TTY 17-22 ordering information 19-25 development tools 17-1 to 17-27 ordering information 19-25 to 19-27 overview 17-2 to 17-3 software development flow 17-3 summary 1-3 devices description, detailed 1-13 listing by families 1-4 overview 1-1 to 1-13 packages 1-13 part numbers 1-13 differences between 'xxxA, 'xxxB, and xxx devices A-1 DINT (disable interrupts) instruction 16-49 direct addressing modes 16-11 DIV (divide) instruction 16-50 V bit setting (in ST) 3-6 DJNZ (decrement register and jump if not zero) instruction 16-51 documentation, related, vii DSB (decimal subtract with borrow) instruction 16-52 dual-port RAM 3-8 to 3-11 contents during low-power modes 4-8 contents during reset 5-20
EINT (enable interrupts) instruction nesting interrupts 5-18 EINTH (enable high-level interrupts) instruction 16-54 nesting interrupts 5-18 EINTL (enable low-level interrupts) instruction 16-55 nesting interrupts 5-18
16-53
electrical specifications 18-1 to 18-52 absolute maximum ratings 18-3 TMS370Cx0xA & 'x0x 18-8 to 18-9 TMS370Cx1xA & 'x1xB 18-12 to 18-13 TMS370Cx2xA & 'x2x 18-16 to 18-17 TMS370Cx32A 18-20 to 18-21 TMS370Cx36A 18-24 to 18-26 TMS370Cx4xA 18-29 to 18-31 TMS370Cx5x, differences A-8 TMS370Cx5xA & 'x5xB 18-34 to 18-37 TMS370Cx6xA 18-43 to 18-45 TMS370Cx7xA 18-51 to 18-53 TMS370Cx8xA 18-57 to 18-58 TMS370Cx9xA 18-62 to 18-64 TMS370CxAxA 18-68 to 18-69 TMS370CxBxA 18-73 to 18-75 TMS370CxCxA 18-79 to 18-80 emulation. See XDS/22 EPCTL (program EPROM control) register BUSY bit 6-12 EXE bit 6-12, 6-13 VPPS bit 6-12, 6-13, 6-15 W0 bit 6-12 EPROM description 1-8 program 3-15, 6-10 to 6-15 programming operating conditions 18-7 timing requirements 18-7 EPROM devices 17-27 17-27 9-22, EPROM devices (list) 6-12
E
edge detection, overview timer 2, 8-2 timer1, 7-2 EDS pin activating 3-23, 3-24, 3-26 definition 4-24 EEPROM 6-2 to 6-9 data 3-13 to 3-14 description 1-7 ensuring integrity of contents timing requirements 18-7
EVEN/ODD PARITY bit (SCICCR register) 10-18 event counter 7-18, 8-15 EVENT COUNTER SW RESET bit (CPPRE register) 15-58 EXE bit (DEECTL register) 5-22 to 5-23 EXE bit (EPCTL register) extended addressing mode 6-5, 6-6, 6-8 6-12, 6-13 16-15 to 16-22
Index-7
Index
F
families of TMS370 devices 1-4 FAST MODE SELECT bit (PACTSCR register) 15-39 calculating the divide rate 15-7 FE bit (RXCTL register) 9-30, 10-25 features of TMS370 family 1-5 frequency detector 4-4 function A expansion signals 3-22 external memory expansion 3-17, 3-19 to 3-22 function B accessing external memory chips 3-17, 3-23 during reset in microprocessor mode 3-25 expansion signals 3-23 function mnemonic, definition 16-2
G
general addressing mode 16-5 to 16-14
H
HALT/STANDBY bit (SCCR2 register) 4-16, 7-29 help, hotline number, ix hex conversion utility 17-7 hexadecimal designator (P0) hotline number, ix 3-12 4-7 to 4-8,
I
I/O configuration 4-18 to 4-30 effect of memory operation mode 4-29 to 4-30 pins 4-18 to 4-30 by device 4-20 port control registers 4-21 to 4-22, B-4 set-up 4-23 to 4-24
example 4-27 to 4-29
system interface example I/O ports bits per port 1-9 description 1-8 Index-8
4-30
IDLE (idle until interrupt) instruction 4-7, 11-9, 16-56 exiting halt mode 4-9 exiting standby mode 4-9 idle mode 4-7 to 4-12 control bits 4-7 entering 4-16 IE1 bit (ST register) 3-6, 4-8, 5-3, 5-9, 7-26 while servicing an interrupt 5-18 IE2 bit (ST register) 3-6, 4-8, 5-3, 5-9, 7-26 while servicing an interrupt 5-18 immediate addressing mode 16-9 implied addressing mode 16-6 INC (increment) instruction 16-57 V bit setting (in ST) 3-6 INCW (increment word) instruction 16-58 V bit setting (in ST) 3-6 indexed addressing modes 16-12 indirect addressing modes 16-13 INPUT CAPT PRESCALE SELECT1-3 bits (CPPRE register) 15-57 instruction addressing modes 16-4 to 16-22 alphabetical summary 16-33 to 16-92 bus activity table F-6 to F-12 bus cycles F-7 internal cycles F-7 cross-reference instruction/opcode F-2 to F-3 opcode/instruction 16-30 to 16-31, E-1 to E-3 operation 16-2 overview 16-23 to 16-29 symbol definitions 16-3 INT1 (interrupt 1 control) register 5-12 INT1 ENABLE bit 4-8, 5-9, 5-13, 7-26 INT1 FLAG bit 5-12 INT1 PIN DATA bit 5-12 INT1 POLARITY bit 5-12 INT1 PRIORITY bit 4-8, 5-9, 5-13, 7-26 INT1 ENABLE bit (INT1 register) 4-8, 5-9, 5-13, 7-26 INT1 FLAG bit (INT1 register) 5-12 INT1 NMI bit (SCCR2 register) 4-8, 4-17, 5-9, 7-26 INT1 pin, during hard watchdog 4-8, 5-9, 7-26 INT1 PIN DATA bit (INT1 register) 5-12 INT1 POLARITY bit (INT1 register) 5-12
Index
INT1 PRIORITY bit (INT1 register) 7-26
4-8, 5-9, 5-13,
INT2 (interrupt 2 control) register 5-14 to 5-15 INT2 DATA DIR bit 5-14 INT2 DATA OUT bit 5-14 INT2 ENABLE bit 5-15 INT2 FLAG bit 5-14 INT2 PIN DATA bit 5-14 INT2 POLARITY bit 4-10, 5-15 INT2 PRIORITY bit 5-15 INT2 DATA DIR bit (INT2 register) INT2 DATA OUT bit (INT2 register) INT2 ENABLE bit (INT2 register) INT2 FLAG bit (INT2 register) INT2 PIN DATA bit (INT2 register) INT2 POLARITY bit (INT2 register) INT2 PRIORITY bit (INT2 register) INT3 (interrupt 3 control) register INT3 DATA DIR bit 5-16 INT3 DATA OUT bit 5-16 INT3 ENABLE bit 5-17 INT3 FLAG bit 5-16 INT3 PIN DATA bit 5-16 INT3 POLARITY bit 5-17 INT3 PRIORITY bit 5-17 INT3 DATA DIR bit (INT3 register) INT3 DATA OUT bit (INT3 register) INT3 ENABLE bit (INT3 register) INT3 FLAG bit (INT3 register) INT3 PIN DATA bit (INT3 register) INT3 POLARITY bit (INT3 register) INT3 PRIORITY bit (INT3 register) 5-16 5-16 5-17 5-17 5-14 5-14 4-10, 5-15 5-15 5-16 to 5-17 5-14 5-14 5-15
interrupts (continued) enabling 5-3 EINT instruction 16-53 EINTH instruction 16-54 EINTL instruction 16-55 exiting a low-power mode 5-11 exiting halt mode 4-10 considerations 4-10 to 4-12 correct method 4-11 incorrect method 4-11 exiting standby mode 4-9 external 5-8 to 5-11 configuring 5-9 functions of bits 5-10 interrupt 1, setting as maskable or NMI 4-17 memory map 5-9 nested routines 5-18 NMI caution while using 5-9 INT1 during hard watchdog 4-8, 5-9, 7-26 programming INT1, 5-9 purpose 5-9 PACT 15-5 to 15-6, 15-29 to 15-30 pins INT1, 5-8 to 5-11
determining interrupt priority 5-13 determining transition direction 5-12 finding current condition 5-12 generating an interrupt 5-13
5-16 5-16 5-17
INT2, 5-8 to 5-11
determining interrupt priority 5-15 determining transition direction 5-15 finding current condition 5-14 generating an interrupt 5-15
INT3, 5-8 to 5-11
determining interrupt priority 5-17 determining transition direction 5-17 finding current condition 5-16 generating an interrupt 5-17
interrupts 5-2 to 5-11 ADC1 conversion module 12-7, 14-7 ADC2 conversion module 13-6 block diagram 5-4 interrupt 1, 5-10, C-2 interrupts 2 and 3, 5-11, C-3 context switch routine 5-7 control registers 5-12 to 5-17, B-3 INT1 (interrupt 1 control) 5-12 INT2 (interrupt 2 control) 5-14 to 5-15 INT3 (interrupt 3 control) 5-16 to 5-17 disabling 5-3 DINT instruction 16-49 enable bits 3-6
priority levels 5-3 to 5-8 by module 5-5 level 1, 5-3 to 5-4 level 2, 5-3 to 5-4 routine description 5-2 RTI instruction 16-80 SCI1, 9-15 SCI2, 10-12 servicing multiple 5-18 SPI 11-9 timer 1, 7-20 overview 7-3
Index-9
Index
interrupts (continued) timer 2, 8-16 overview 8-2 vector sources 5-2, 5-6 to 5-7 INV (invert) instruction isosynchronous mode 16-59 1-11
low-power modes (continued) halt 4-9, 7-29, 8-17 definition 4-7 entering 4-9, 4-16 exiting 4-10 when using interrupts to exit
4-10 to 4-12
correct method of exiting 4-11 incorrect method of exiting 4-11
J
JBIT0 (jump if bit = 0) instruction JBIT1 (jump if bit = 1) instruction 16-60 16-61 16-62 to 16-63 16-64 Jcnd (jump on condition) instruction JMP (jump unconditional) instruction JMPL (jump long) instruction jump instructions BTJO 16-37 BTJZ 16-38 DJNZ 16-51 JBIT0, 16-60 JBIT1, 16-61 Jcnd 16-62 to 16-63 JMP 16-64 JMPL 16-65 jump-conditional instructions, list 16-62 16-65
information retained 4-8 standby 4-8 to 4-9, 7-29, 8-17 definition 4-7 entering 4-8, 4-16 exiting 4-9 while programming data EEPROM
6-7
M
manuals, TMS370, vii mask-ROM numbering conventions 19-20 to 19-28 prototyping production flow 19-2 to 19-5 MASTER/SLAVE bit (SPICTL register) 11-16 11-6, 11-11,
L
LDSP (load stack pointer) instruction loading the SP 3-4 LDST (load status register) instruction modifying ST value 3-6 linker 17-5 to 17-6 directives 17-5 input files 17-5 ordering information output 17-6 tasks 17-5 logical AND 16-35 4-24 16-66 16-67
MC pin overriding EPROM write protection 6-15 providing voltage for programming EPROMs 6-11, 6-14 selecting memory operating mode 3-16 microcomputer single-chip 3-17 microcomputer with external expansion microprocessor with internal program memory 3-27 microprocessor without internal memory 3-26 writing to EPROM 3-15 MC PIN DATA bit (SCCR0 register) 4-14 4-14 MC PIN WPO bit (SCCR0 register) mechanical data 19-6 to 19-15
3-24
19-25
LOW ADDR/HI ADDR signal, definition low-power modes 4-7 to 4-12 control bits 4-7 definition 4-7 entering 4-16, 11-9 differences A-4 exiting 5-11 Index-10
memory data EEPROM 3-13 to 3-14, 6-2 to 6-9 expansion 3-19 to 3-24 operating modes 3-16 to 3-29 See also operating modes, memory peripheral file 3-11 to 3-13 program 3-14 to 3-15 EPROM 6-10 to 6-15 register file 3-8 to 3-11 reserved 3-14, 3-15
Index
memory (continued) size device options 1-13 part nomenclature 19-18 type (nomenclature) 19-18 MEMORY directive 17-5 3-26, MEMORY DISABLE bit (SCCR1 register) 4-15 memory map 3-8 to 3-15 ADC1 converter module 12-4 ADC2 converter module 13-4 ADC3 converter module 14-4 available locations 3-3 illustration 3-9 interrupts 5-9 PACT 15-4 peripheral file summary B-1 to B-14 SCI1 module 9-6 SCI2 module 10-5 SPI module 11-4 timer 1, 7-5 timer 2, 8-5 watchdog timer 7-5 microcomputer mode effect on I/O ports 4-29 to 4-30 function A expansion signals 3-22 function B expansion signals 3-23 programming port D 3-17, 3-19 to 3-24 selecting 4-14 single-chip 3-17 to 3-18 diagram 3-18 memory map 3-18 selecting 3-17 with external expansion 3-19 to 3-24 selecting 3-24 microcontroller programmer 17-25 microprocessor mode effect on I/O ports 4-29 for ROM-less devices 3-15 programming port D 3-25 selecting 4-14 with internal program memory 3-26 to 3-28 diagram 3-28 selecting 3-27 without internal memory 3-24 to 3-26 diagram 3-25 to 3-26 selecting 3-26 MOV (move) instruction 16-68 to 16-69
move instructions MOV 16-68 to 16-69 MOVW 16-70 MOVW (move word) instruction 16-70 mP/mC MODE bit (SCCR0 register) 4-14 MPY (multiply) instruction 16-71 multiprocessor modes, overview 9-3, 10-2
N
N bit (ST register) 3-5 NCRF (new code release form) 19-2 diagram 19-4 negative bit (N) 3-5 new code release form (NCRF) 19-2 diagram 19-4 nonreturn to zero format 9-7, 10-6 NOP (no operation) instruction 16-72 NRZ (nonreturn to zero) format 9-7, 10-6 numbering conventions 19-16 to 19-24
O
OCF signal, definition 4-25 OE bit (RXCTL register) 9-30, 10-25 offset, calculation 16-10 offset indirect addressing modes 16-14 to 16-15 one-time programmables list 17-27 OP SET/CLR SELECT bit (CPPRE register) 15-58 OP1-OP8 pins 15-5, 15-15 opcode instruction/opcode cross-reference F-2 to F-3 opcode/instruction cross-reference 16-30 to 16-31, E-1 to E-3 operand, definition 16-2 operating modes, memory device applicability 3-16 for device families 3-16 selecting 3-16 summary 3-28 to 3-29 OPSTATE (output pins 1-8 state) register 15-49 PACT OP1-8 bits 15-49 optimizing C compiler. See compiler OR (logical OR) instruction 16-73
Index-11
Index
ordering information 19-1 to 19-27 development tools 19-25 to 19-27 mechanical data 19-6 to 19-15 numbering conventions 19-16 to 19-24 prototyping device production flow 19-2 to 19-5 OSC FLT DISABLE bit (SCCR2 register) OSC FLT FLAG bit (SCCR0 register) as source of reset 5-19 determining source of reset 4-5 OSC POWER bit (SCCR0 register) oscillator 4-4 amplitude detector 4-4 as reset source 5-19 detection 4-14 frequency detector 4-4 power reduction 4-13 purpose 4-5 OTP (one-time programmable) devices OTP devices 17-26 numbering conventions OTP list 17-27 18-4 3-6 output load circuit, typical overflow bit (V) 17-27 A-5 4-14
PACT (continued) Double Event Compare
15-18 to 15-19
bit definitions 15-26 to 15-28 block diagram 15-19 components 15-18 uses 15-18 to 15-19
required time slots 15-21 Standard Compare 15-16 to 15-17
bit definitions 15-25 block diagram 15-16 components 15-16 creating PWM 15-17 macro I-4 uses 15-16 to 15-17
OSC FLT RST ENA bit (SCCR2 register)
A-5
4-12, 4-13
controller 15-15 to 15-20 block diagram 15-15 event counter as input 15-15 outputs 15-15 definitions addressing I-2 baud rate timer definition 15-20
bit definitions 15-24 block diagram 15-20 macro I-4 uses 15-20
19-22, 19-23
offset timer definition-time from last event 15-19
bit definitions 15-23 block diagram 15-19 uses 15-19
P
package types 19-18 packaging 19-6 to 19-15 device descriptions 1-13 PACT 15-1 to 15-54 block diagram 15-3 circular buffer 15-9 address of buffer pointer 15-44 location in RAM 15-10 command/definition area 15-9, 15-21 to 15-28 determining ending address 15-42 determining starting address 15-40 enabling 15-38 location in RAM 15-10 commands addressing I-2 Conditional Compare 15-20
bit definitions 15-28 block diagram 15-20 macro I-4 uses 15-20
required time slots 15-21 virtual timer definition 15-17 to 15-18
bit definitions 15-22 block diagram 15-17 components 15-17 macro I-4 uses 15-18
description 1-10, 1-11 dual-port RAM 15-5 to 15-6, 15-9 to 15-11 major areas 15-9 memory map 15-10 event counter 15-11 exiting standby mode 4-9 hardware pins 15-5 input
controlling functions 15-51 to 15-56 CP1-CP6, 15-5, 15-12 to 15-14
output
determining state 15-49 OP1-OP8, 15-5, 15-15
outputs, defining I-3
Index-12
Index
PACT (continued) SCI receive/transmit
RX 15-5 TX 15-5
input captures 15-12 to 15-14 block diagram 15-13 interrupts 15-5 to 15-6, 15-29 to 15-30 enabling 15-38, 15-40, 15-47 memory map 15-29 priority level 5-5 priority levels 15-29 sources 15-30 types 15-29 vector sources 5-6 macros I-1 to I-11 memory organization memory map 15-4, 15-6 overview 15-5 to 15-6 mini-SCI 15-32 calculating baud 15-32 operating modes 15-10 mode A 15-13 mode B 15-13 operation 15-5 to 15-8 outputs 15-15 to 15-20 block diagram 15-15 overview 15-2 to 15-4 PACT.H macros I-1 to I-11 physical description 15-2 to 15-3 prescaler 15-7 calculating the divide rate 15-7, 15-39 determining the number of time slots 15-7 to 15-8 effect on controller 15-15 pulse width modulated (PWM) signal 15-33 to 15-35 copying the command/definition area to RAM 15-34 defining the command/definition area 15-33 to 15-34 example 15-34 initializing the PACT peripheral frame 15-35 registers 15-36 to 15-60, B-7 BUFPTR (buffer pointer) 15-14 to 15-15, 15-44 to 15-45 capture 15-9
location in RAM 15-10
PACT (continued) CDSTART (command/definition area start) 15-40 to 15-41 CPCTL1 (set-up CP control 1) 15-51 to 15-52 CPCTL2 (set-up CP control 2) 15-53 to 15-54 CPCTL3 (set-up CP control 3) 15-55 to 15-56 CPPRE (CP input control) 15-57 to 15-58 OPSTATE (output pins 1-8 state) 15-49 overview 15-4 PACTPRI (global function control) 15-59 to 15-60 PACTSCR (set-up control) 15-38 to 15-39 RXBUFP (PACT-SCI RX data) 15-48 SCICTLP (PACT-SCI control) 15-46 to 15-47 TXBUFP (PACT-SCI TX data) 15-48 time base 15-7 time slots 15-7 to 15-8 available number 15-8 number required for commands and definitions 15-21 timers baud rate timer 15-20
block diagram 15-20 uses 15-20
default timer 15-11
finding status 15-38
offset timer 15-19
block diagram 15-19 uses 15-19
virtual timer 15-17 to 15-18
block diagram 15-17 components 15-17 uses 15-18
CDEND (command/definition area end) 15-42 to 15-43 CDFLAGS (command/definition entry flags) 15-50
watchdog timer 15-31 PACT FE bit (SCICTLP register) 15-32, 15-46 PACT GROUP 2 PRIORITY bit (PACTPRI register) 15-59 PACT GROUP 3 PRIORITY bit (PACTPRI register) 15-59 PACT MODE SELECT bit (PACTPRI register) 15-59 PACT OP1-8 bits (OPSTATE register) 15-49 PACT PARITY bit (SCICTLP register) 15-32, 15-46 PACT PRESCALE SELECT0-3 bits (PACTSCR register) 15-39 calculating the divide rate 15-7 PACT RXDT0-7 bits (RXBUFP register) 15-48
Index-13
Index
PACT RXRDY bit (SCICTLP register)
15-46
PACT SCI RX INT ENA bit (SCICTLP register) 15-47 PACT SCI SW RESET bit (SCICTLP register) 15-47 PACT SCI TX INT ENA bit (SCICTLP register) 15-47 PACT STEST bit (PACTPRI register) PACT TXRDY bit (SCICTLP register) 15-59 15-48 15-46 PACT TXDT0-7 bits (TXBUFP register)
peripheral file (continued) frames 3-11 to 3-13 frame 1, B-3
memory map 5-9 overview 4-2 register descriptions 4-13 to 4-17, 5-12 to 5-17, 6-4 to 6-5, 6-12
frame 2, 4-21 to 4-22, B-4
register descriptions 4-21 to 4-22
frame 3, B-5
memory map 11-4 register descriptions 11-13 to 11-22
PACT WD PRESCALE SELECT0-1 bits (PACTPRI register) 15-31, 15-59 PACT.H macros I-1 to I-11 PACTPRI (global function control) register 15-59 to 15-60 PACT GROUP 2 PRIORITY bit 15-59 PACT GROUP 3 PRIORITY bit 15-59 PACT MODE SELECT bit 15-59 PACT STEST bit 15-59 PACT WD PRESCALE SELECT0-1 bits 15-59
frame 4, 15-5 to 15-6, B-6, B-7
memory map 7-5, 15-4 register descriptions 7-30 to 7-43, 15-36 to 15-60
frame 5, B-8, B-9
memory map 9-6, 10-5 register descriptions 9-21 to 9-35, 10-17 to 10-29
frame 6, B-10, B-14
15-31,
memory map 8-5 register descriptions 8-17 to 8-29
frame 7, B-11, B-12, B-13
memory map 12-4, 13-4, 14-4 register descriptions 12-11 to 12-17, 13-10 to 13-15, 14-11 to 14-17
PACTSCR (set-up control) register 15-38 to 15-39 CMD/DEF AREA ENA bit 15-38 DEFTIM OVRFL INT ENA bit 15-38 DEFTIM OVRFL INT FLAG bit 15-38 FAST MODE SELECT bit 15-39 calculating the divide rate 15-7 PACT PRESCALE SELECT0-3 bits 15-39 calculating the divide rate 15-7 PARITY ENABLE bit (SCICCR register) 10-18 part numbers breakdown by fields 19-18 device description 1-13 device symbolization 19-19 prefix definition 19-18 PCH register PCL register PDIP 3-7 3-7 9-30, 10-25 16-8 9-22,
hexadecimal designator 3-12 memory map B-1 to B-14 peripheral addressing mode 16-8 PF AUTOWAIT bit (SCCR0 register) 4-14 pins and signals ADC1 pins 12-5, 14-5 ADC2 pins 13-5 AN0-AN7, 12-5 CLKOUT, definition 4-24 CP1-CP6, 15-5, 15-12 to 15-14 CSE1, definition 4-24 CSE2, definition 4-24 CSH1, definition 4-24 CSH2, definition 4-24 CSPF, definition 4-24 DATA BUS, definition 4-24 descriptions, list of devices 1-13 EDS 4-15 activating 3-23, 3-24, 3-26 definition 4-24 INT1, 5-8 to 5-11 INT2, 5-8 to 5-11 INT3, 5-8 to 5-11 4-5 to 4-8,
19-6, 19-8
PE bit (RXCTL register)
peripheral addressing mode peripheral file 3-11 to 3-13 adding wait states 4-14 address map 3-13 decimal designator 3-12 definition 3-2 Index-14
Index
pins and signals (continued) LOW ADDR/HI ADDR, definition 4-24 MC finding voltage status 4-14 overriding write protection 4-14 selecting the memory operating mode
3-16
microcomputer single-chip 3-17 microcomputer with external expansion 3-24 microprocessor with internal program memory 3-27 microprocessor without internal memory 3-26
OCF, definition 4-25 OP1-OP8, 15-5, 15-15 pin descriptions 2-1 to 2-39 pinouts TMS370Cx0x 2-2 TMS370Cx1x 2-4, G-2, G-13 TMS370Cx2x 2-6, G-3, G-10, G-11 TMS370Cx32, 2-8 TMS370Cx36, 2-11 TMS370Cx3x G-4, G-5 TMS370Cx4x 2-14, G-6 TMS370Cx5x 2-16, G-7, G-8, G-9, G-12 TMS370Cx6x 2-20 TMS370Cx7x 2-24 TMS370Cx8x 2-27 TMS370Cx9x 2-30 TMS370CxA 2-33 TMS370CxB 2-35 TMS370CxC 2-38 PLCC to PGA sockets H-1 to H-17 RESET 5-19 selecting the memory operating mode 3-16
microcomputer single-chip 3-17 microcomputer with external expansion 3-24 microprocessor with internal program memory 3-27 microprocessor without internal memory 3-26
R/W, definition 4-24 RX 15-5 SCICLK 9-12, 9-13, 9-16 to 9-17, 10-13 to 10-14 control register 9-32 frequency formula 9-27, 10-22 selecting source 9-25 SCIRXD 9-5, 9-14, 10-4, 10-10 control register 9-33, 10-27 SCITXD 9-5, 9-14, 10-3, 10-11 control register 9-33 to 9-34, 10-27 to 10-28
pins and signals (continued) SPICLK 11-2, 11-5, 11-6 to 11-7, 11-11 control register 11-19 selecting polarity 11-14 SPISIMO 11-2, 11-6 to 11-7 control register 11-20 to 11-21 SPISOMI 11-2, 11-6 control register 11-20 T1EVT, definition 7-3 T1IC/CR, definition 7-3 T1PWM, definition 7-3 T2EVT, definition 8-3 T2IC1/CR, definition 8-3 T2IC2/PWM, definition 8-3 TX 15-5 VCC3, 12-5 VREF 12-6, 13-5, 14-5 VSS3, 12-5 WAIT 4-5 to 4-8 definition 4-25 WPO 3-15, 3-16, 4-14 PLCC 19-6, 19-11 POP (pop from stack) instruction 16-74 port A as external memory 3-19, 3-25 control registers 4-21 to 4-22 dedicated pins 4-18 to 4-30 port B as external memory 3-19, 3-25 control registers 4-21 to 4-22 dedicated pins 4-18 to 4-30 port C as external memory 3-19, 3-25 control registers 4-21 to 4-22 dedicated pins 4-18 to 4-30 port D as external memory 3-19 chip-select and enable functions 3-19 to 3-24 control registers 4-21 to 4-22 dedicated pins 4-18 to 4-30 function A expansion signals 3-22 function B expansion signals 3-23 programming using microcomputer mode 3-17, 3-19 to 3-24 programming using microprocessor mode 3-25 PORT E DATA AN0-7 bits (ADIN register) 12-15, 13-14, 14-15 PORT E INPUT ENA0-7 bits (ADENA register) 12-16, 13-14, 14-16
Index-15
Index
ports as external memory 3-19 bits per port 1-9 control registers 4-21 to 4-22, B-4 description (by device) 1-8 to 1-9 value during low-power modes 4-8 prescaler, overview 7-2 4-2,
PRIVILEGE DISABLE bit (SCCR2 register) 4-17 privilege mode 4-2 to 4-3 entering 4-2 exiting 4-2, 4-17 privilege bits changing after leaving privilege mode listing 4-3 product description characteristics 1-13 web address, ix production lead time, definition 19-4
4-3
program EPROM 3-15, 6-10 to 6-15 access time 3-15 control register, overview B-3 DEECTL register 6-12 description 1-8 entering reserved mode 6-14 finding voltage status 6-12 preparing for programming 6-11 programming 6-13 to 6-14
flowchart 6-14 initiating 6-13 preventing 6-14 voltage required 6-14
program counter (continued) PCL (program counter low) 3-7 value during low-power modes 4-8 value during reset 3-7 programmer gang, ordering information 19-26 microcontroller 17-2 features 17-25 ordering information 19-26 programmer top 17-25 programming design kit use 17-20 devices supported 17-27 EPROM devices 17-27 microcontroller programmer 17-25 OTPs (one-time programmables) 17-27 programming adapter board 17-24 prototyping area 17-21 prototyping device numbering conventions 19-20 to 19-28 production flow 19-2 to 19-5 prototyping lead time, definition 19-4 pulse accumulation 7-18, 8-15 PUSH (push on stack) instruction 16-75 PWRDWN/IDLE bit (SCCR2 register) 4-7 to 4-8, 4-16, 7-29, 8-17
R
RAM, description 1-7 RCVD0-7 bits (SPIBUF register) 11-18 RECEIVER OVERRUN bit (SPICTL register) 11-16 REF VOLT SELECT0-2 bits (ADCTL register) 12-12, 13-11, 14-12 register addressing mode 16-7 register file 3-8 to 3-11 access time 3-11 accessing 3-11 address map 3-10 definition 3-2 description 1-7 memory map 3-3 partitioning 3-10 register addressing mode 16-7 registers A (R0) 3-10 A/D control registers B-11, B-12, B-13 11-9,
reading 6-11 write protecting 6-15 memory 3-14 to 3-15 disabling 4-15 enabling 4-15 for ROM-less devices 3-15 map 3-3 vector address map 3-14 ROM 3-15
program counter (PC) 3-7 definition 3-2 during context switch routine 5-8 during interrupt routine 5-2 during reset sequence 5-20 PCH (program counter high) 3-7 Index-16
Index
registers (continued) ADATA, ADIR 4-21 to 4-22 ADC1 control registers 12-11 to 12-17 ADC2 control registers 13-10 to 13-15 ADC3 control registers 14-11 to 14-17 ADCTL 12-12 to 12-13, 13-11 to 13-12, 14-12 to 14-13 ADDATA 12-15, 13-13, 14-15 ADENA 12-16, 13-14, 14-16 ADIN 12-15, 13-14, 14-15 ADPRI 12-17, 13-15, 14-16 ADSTAT 12-14, 13-13, 14-14 APORT1, APORT2, 4-21 to 4-22 B (R1) 3-10 BAUD LSB 9-27, 10-22 BAUD MSB 9-27, 10-22 BDATA, BDIR 4-21 to 4-22 BPORT1, BPORT2, 4-21 to 4-22 BUFPTR 15-14 to 15-15, 15-44 to 15-45 CDATA, CDIR 4-21 to 4-22 CDEND 15-42 to 15-43 CDFLAGS 15-50 CDSTART 15-40 to 15-41 CPCTL1, 15-51 to 15-52 CPCTL2, 15-53 to 15-54 CPCTL3, 15-55 to 15-56 CPORT1, CPORT2, 4-21 to 4-22 CPPRE 15-57 to 15-58 CPU registers 3-4 to 3-7 overview 3-2 DDATA, DDIR 4-21 to 4-22 DEECTL 3-14, 6-2, 6-4 to 6-5, 6-6 to 6-9, B-3 DPORT1, DPORT2, 4-21 to 4-22 EPCTL 6-12, B-3 INT1, 5-12 INT2, 5-14 to 5-15 INT3, 5-16 to 5-17 interrupt control registers 5-12 to 5-17, B-3 OPSTATE 15-49 PACT control registers 15-36 to 15-60, B-7 PACTPRI 15-59 to 15-60 PACTSCR 15-38 to 15-39 PC 3-7 port control registers 4-21 to 4-22, B-4 reading 16-bit registers 7-30, 8-17 RXBUF 9-5, 9-15, 9-31, 10-4, 10-12, 10-26 RXBUFP 15-48 RXCTL 9-29 to 9-30, 10-24 to 10-25 RXSHF 9-5, 10-4 SCCR0, 4-13 to 4-14
registers (continued) SCCR1, 4-15 SCCR2, 4-16 to 4-17 SCI control registers B-8, B-9 SCI1 control registers 9-21 to 9-35 SCI2 control registers 10-17 to 10-29 SCICCR 9-22 to 9-23, 10-18 to 10-19 SCICTL 9-24 to 9-26, 10-20 to 10-21 SCICTLP 15-46 to 15-47 SCIPC1, 9-32 SCIPC2, 9-33 to 9-34, 10-27 to 10-28 SCIPRI 9-35, 10-29 SP 3-4 to 3-5 SPI control registers 11-13 to 11-22, B-5 SPIBUF 11-18 clearing interrupt flag 11-9 definition 11-2 during data transmission 11-6 formatting 11-8 SPICCR 11-14 to 11-15 SPICTL 11-16 to 11-17 SPIDAT 11-18 definition 11-2 during data transmission 11-6 to 11-7 formatting 11-8 to 11-9 initialization 11-11 to 11-12 SPIPC1, 11-19 SPIPC2, 11-20 to 11-21 SPIPRI 11-22 ST 3-5 to 3-7 system configuration and control 4-2, 4-13 to 4-17, B-3 T1CTL1, 7-32 to 7-33 T1CTL2, 7-34 to 7-35 T1CTL3, 7-36 to 7-37 T1CTL4, 7-38 to 7-39 T1PC1, 7-40 T1PC2, 7-41 to 7-42 T1PRI 7-43 T2CTL1, 8-19 T2CTL2, 8-20 to 8-22 T2CTL3, 8-23 to 8-25 T2PC1, 8-26 T2PC2, 8-27 to 8-28 T2PRI 8-29 timer 1 control registers 7-30 to 7-43, B-6 timer 2 control registers 8-17 to 8-29, B-10, B-14 TXBUF 9-5, 9-9, 9-10, 9-15, 9-31, 10-3, 10-8, 10-9, 10-12, 10-26
Index-17
Index
registers (continued) TXBUFP 15-48 TXCTL 9-28, 10-23 TXSHF 9-5, 9-9, 9-10, 9-15, 10-3, 10-8, 10-9, 10-12 value during low-power modes 4-8 watchdog timer control registers 7-30 to 7-35, B-6 WPR 6-2, 6-3 to 6-4, 6-6 to 6-9 reprogrammable EPROMs 17-26 numbering conventions 19-23 reset 5-19 to 5-23 circuit simple 5-20 to 5-22 with low-voltage detection 5-22 to 5-23 exiting halt mode 4-10 exiting standby mode 4-9 finding cause 4-13 generating by the hard watchdog 7-25 by the standard watchdog 7-23 initializing the SPI 11-11 PC value 3-7 register A value 3-11 register B value 3-11 resetting timer 1 counter 7-6, 7-13 resetting timer 2 counter 8-6 selecting the memory operating mode 3-16 sequence 5-20 number of cycles 5-20 sources 5-19 SP value 3-4 vectors 3-14, 5-2 RESET pin as reset source 5-19 during oscillator fault 5-20 during watchdog overflow 5-20 entering reserved mode 6-14 reset circuit simple 5-20 to 5-22 with low-voltage detection 5-22 to 5-23 selecting memory operation mode 3-16 microcomputer single-chip 3-17 microcomputer with external expansion 3-24 microprocessor with internal program memory 3-27 microprocessor without internal memory 3-26 RL (rotate left) instruction 16-76 RLC (rotate left through carry) instruction 16-77 Index-18
ROM, program 3-15 rotate instructions RL 16-76 RLC 16-77 RR 16-78 RRC 16-79 RR (rotate right) instruction 16-78 RRC (rotate right through carry) instruction 16-79 RTI (return from interrupt) instruction 16-80 function at end of interrupt routine 5-2 restoring ST value 3-6 RTS (return from subroutine) instruction 16-81 R/W signal, definition 4-24 RX ERROR bit (RXCTL register) 9-29, 10-24 RX pin 15-5 RXBUF (SCI receiver data buffer) register 9-15, 9-31, 10-4, 10-12, 10-26 RXDT0-7 bits 9-31, 10-26 RXBUF (SCI1 receiver data buffer) register 9-5 RXBUFP (PACT-SCI RX data) register 15-48 PACT RXDT0-7 bits 15-48 RXCTL (SCI receiver interrupt control and status) register 9-29 to 9-30, 10-24 to 10-25 BRKDT bit 9-15, 9-29, 10-12, 10-24 FE bit 9-30, 10-25 OE bit 9-30, 10-25 PE bit 9-30, 10-25 RX ERROR bit 9-29, 10-24 RXRDY bit 9-8, 9-15, 9-29, 10-7, 10-12, 10-24 RXWAKE bit 9-30, 10-25 SCI RX INT ENA bit 9-15, 9-30, 10-12, 10-25 RXDT0-7 bits (RXBUF register) 9-31, 10-26 RXENA bit (SCICTL register) 9-26, 10-21 RXRDY bit (RXCTL register) 9-8, 9-15, 9-29, 10-7, 10-12, 10-24 RXSHF register 9-5, 10-4 RXWAKE bit (RXCTL register) 9-30, 10-25
S
SAMPLE START bit (ADCTL register) 12-8, 12-12, 13-7, 13-11, 14-8, 14-12 SBB (subtract with borrow) instruction 16-82 V bit setting (in ST) 3-6 SBIT0 (set bit to 0) instruction 16-83 SBIT1 (set bit to 1) instruction 16-84
Index
SCCR0 (system control and configuration 0) register 4-13 to 4-14 COLD START bit 4-13 as source of reset 5-19 determining source of reset 4-5 MC PIN DATA bit 4-14 MC PIN WPO bit 4-14 mP/mC MODE bit 4-14 OSC FLT FLAG bit 4-14 as source of reset 5-19 determining source of reset 4-5 OSC POWER bit 4-12, 4-13 overview of bits 4-2 PF AUTOWAIT bit 4-5 to 4-8, 4-14 SCCR1 (system control and configuration 1) register 4-15 AUTOWAIT DISABLE bit 4-5 to 4-8, 4-15 MEMORY DISABLE bit 3-26, 4-15 overview of bits 4-2 SCCR2 (system control and configuration 2) register 4-16 to 4-17 BUS STEST bit 4-17 CPU STEST bit 4-17 differences in bits A-5 HALT/STANDBY bit 4-7 to 4-8, 4-16, 7-29 INT1 NMI bit 4-8, 4-17, 5-9, 7-26 OSC FLT DISABLE bit A-5 OSC FLT RST ENA bit A-5 overview of bits 4-2 PRIVILEGE DISABLE bit 4-2, 4-17 PWRDWN/IDLE bit 4-7 to 4-8, 4-16, 7-29, 8-17 SCI See also SCI1 or SCI2 for individual modules asynchronous mode baud formula 9-16 to 9-17, 9-27 description 9-12 selecting (ASYNC/ISOSYNC bit) 9-22 single-line communication 9-12, 10-10 two-line communication 9-12, 10-10 block diagram C-10 clock sources frequency formula 9-27 selecting (SCI1 function) 9-25 communications modes, selecting (ASYNC/ISOSYNC bit) 9-22 control registers B-8, B-9 data format parity 9-22, 10-18 selecting character length 9-23, 10-19 selecting number of stop bits 9-22, 10-18
SCI (continued) description 1-11 for the PACT module 15-32 interrupts disabling 9-28, 9-30, 10-25 enabling 9-28, 9-30, 10-25 priority level 5-5 sequence of events 10-7 to 10-8 vector sources 5-6 isosynchronous mode baud formula 9-16, 9-27 description 9-13 selecting (ASYNC/ISOSYNC bit) 9-22 three-line communication 9-13 two-line communication 9-13 multiprocessor communications idle line mode, sending a block start signal 10-8, 10-9 interrupt sequence 10-7 to 10-8 selecting mode 9-23, 10-7, 10-19 pins SCICLK
control register 9-32 frequency formula 9-27 selecting source 9-25
SCIRXD 9-14, 10-10
control register 9-33 exiting halt mode 4-10 exiting standby mode 4-9
SCITXD, control register 9-33 to 9-34 receiving data, during low-power modes 4-8 reset 9-24, 10-20 affected bits 9-24 timings 18-84 to 18-85 differences A-9 to A-10 transmitting data, during low-power modes 4-8 WUT flag 10-8, 10-9
SCI CHAR0-2 bits (SCICCR register) SCI ESPEN bit (SCIPRI register) SCI RX INT ENA bit (RXCTL register) 10-12, 10-25 SCI RX PRIORITY bit (SCIPRI register) 9-35, 10-12, 10-29 SCI STEST bit (SCIPRI register) SCI SW RESET bit (SCICTL register) SCI TX INT ENA bit (TXCTL register) 10-12, 10-23 SCI TX PRIORITY bit (SCIPRI register) 9-35, 10-12, 10-29 9-23, 10-19 9-15, 9-30, 9-15, 9-35, 10-29
9-35, 10-29 9-24, 10-20 9-15, 9-28, 9-15,
Index-19
Index
SCI1 9-1 architecture 9-5 asynchronous mode 9-12 baud formula 9-16 to 9-17 bit rates 9-2 communication format 9-12 definition 9-5 single-line communication 9-12 two-line communication 9-12 bit rates 9-2 block diagram 9-4 clock sources 9-16 to 9-17 bit rates (baud) 9-16 to 9-17 serial clock rates 9-16 to 9-17 communications modes 9-12 to 9-14 overview 9-5 receiver signals 9-13 to 9-14 transmitter signals 9-14 control registers 9-21 to 9-35 BAUD LSB and BAUD MSB (baud select) 9-27 overview 9-6 RXBUF (SCI receiver data buffer) 9-31 RXCTL (SCI receiver interrupt control and status) 9-29 to 9-30 SCICCR (SCI communication control) 9-22 to 9-23 SCICTL (SCI control) 9-24 to 9-26 SCIPC1 (SCI port control 1) register 9-32 SCIPC2 (SCI port control 2) register 9-33 to 9-34 SCIPRI (SCI priority control) register 9-35 TXBUF (SCI transmitter data buffer) 9-31 TXCTL (SCI transmitter interrupt control and status) 9-28 data format 9-7 components 9-7 illustration 9-7 programming 9-7 error detection flags, overview 9-2 initialization examples 9-18 to 9-20 RS-232-C 9-18 RS-232-C multiprocessor mode 9-19 to 9-20 interrupts 9-15 generating during multiprocessor communications 9-8 sequence of events 9-8 to 9-9 isosynchronous mode 9-13 baud formula 9-16 bit rates 9-2 Index-20
SCI1 (continued) communication format 9-13 definition 9-5 three-line communication 9-13 two-line communication 9-13 memory map 9-6 multiprocessor communications 9-8 to 9-11 address bit mode 9-8, 9-10
data format 9-7 format 9-11
generating an interrupt 9-8 idle line mode 9-8, 9-9 to 9-10
data format 9-7 format 9-9 sending a block start signal 9-9, 9-10
interrupt sequence 9-8 to 9-9 overview 9-5 to 9-6 selecting mode 9-8 overview 9-2 to 9-6 physical description 9-2 to 9-4 pins SCICLK 9-12, 9-13, 9-16 to 9-17 SCIRXD 9-5 SCITXD 9-5, 9-14 receiver, overview 9-5 transmitter, overview 9-5 WUT flag 9-9, 9-10
SCI2 10-1 to 10-29 architecture 10-3 to 10-4 asynchronous mode 10-10 block diagram 10-3 clock sources 10-13 frequency formula 10-22 communications modes overview 10-4 receiver signals 10-10 transmitter signals 10-10 control registers 10-17 to 10-29 BAUD LSB and BAUD MSB (baud select) 10-22 overview 10-4 RXBUF (SCI receiver data buffer) 10-26 RXCTL (SCI receiver interrupt control and status) 10-24 to 10-25 SCICCR (SCI communication control) 10-18 to 10-19 SCICTL (SCI control) 10-20 to 10-21 SCIPC2 (SCI port control 2) register 10-27 to 10-28 SCIPRI (SCI priority control) register 10-29
Index
SCI2 (continued) TXBUF (SCI transmitter data buffer) 10-26 TXCTL (SCI transmitter interrupt control and status) 10-23 data format 10-6 components 10-6 illustration 10-6 programming 10-6 error detection flags, overview 10-2 initialization examples 10-14 to 10-16 RS-232-C 10-14 RS-232-C multiprocessor mode 10-15 to 10-16 interrupts 10-12 disabling 10-23 enabling 10-23 generating during multiprocessor communications 10-7 memory map 10-5 multiprocessor communications 10-7 to 10-9 address bit mode 10-7, 10-9
data format 10-6 format 10-9
SCICCR (SCI1/SCI2 communication control) register ADDRESS/IDLE WUP bit 9-8, 10-7 ASYNC/ISOSYNC bit (SCI1 only) 9-12 programming the data format 9-7, 10-6 SCICLK DATA DIR bit (SCIPC1 register) SCICLK DATA IN bit (SCIPC1 register) 9-32 9-17, 9-32 9-32 9-12,
SCICLK DATA OUT bit (SCIPC1 register) SCICLK FUNCTION bit (SCIPC1 register) 9-16, 9-32
SCICTL (SCI control) register 9-24 to 9-26, 10-20 to 10-21 CLOCK bit 9-25, 10-13 CLOCK ENABLE bit 10-21 RXENA bit 9-26, 10-21 SCI SW RESET bit 9-24, 10-20 SLEEP bit 9-25, 10-7, 10-9, 10-21 TXENA bit 9-25, 10-21 TXWAKE bit 9-25, 10-7, 10-8, 10-9, 10-21 double-buffered WUT flag 10-8 SCICTL (SCI1 control) register SLEEP bit 9-8, 9-9, 9-10 TXWAKE bit 9-9, 9-10 double-buffered WUT flag
generating an interrupt 10-7 idle line mode 10-7, 10-8 to 10-9
data format 10-6 format 10-8
9-9
overview 10-4 overview 10-2 to 10-5 physical description 10-2 to 10-3 pins SCICLK 10-13
frequency formula 10-22
SCICTL (SCI1/SCI2 control) register CLOCK bit (SCI1 only) 9-12, 9-16 SLEEP bit 10-8 TXWAKE bit 9-8, 10-7 SCICTLP (PACT-SCI control) register 15-46 to 15-47 PACT FE bit 15-32, 15-46 PACT PARITY bit 15-32, 15-46 PACT RXRDY bit 15-46 PACT SCI RX INT ENA bit 15-47 PACT SCI SW RESET bit 15-47 PACT SCI TX INT ENA bit 15-47 PACT TXRDY bit 15-46 SCIPC1 (SCI port control 1) register 9-32 SCICLK DATA DIR bit 9-32 SCICLK DATA IN bit 9-17, 9-32 SCICLK DATA OUT bit 9-32 SCICLK FUNCTION bit 9-16, 9-32 SCIPC1 (SCI1 port control 1) register, SCICLK FUNCTION bit 9-12
SCIRXD 10-4
control register 10-27
SCITXD 10-3, 10-11
control register 10-27 to 10-28
receiver, overview 10-4 reset, affected bits 10-20 transmitter, overview 10-3 SCICCR (SCI communication control) register 9-22 to 9-23, 10-18 to 10-19 ADDRESS/IDLE WUP bit 9-23, 10-7, 10-19 ASYNC ENABLE bit 10-18 ASYNC/ISOSYNC bit 9-22 EVEN/ODD PARITY bit 9-22, 10-18 PARITY ENABLE bit 9-22, 10-18 SCI CHAR0-2 bits 9-23, 10-19 STOP BITS bit 9-22, 10-18
Index-21
Index
SCIPC2 (SCI port control 2) register 9-33 to 9-34, 10-27 to 10-28 SCIRXD DATA DIR bit 9-34, 10-28 SCIRXD DATA IN bit 9-33, 10-27 SCIRXD DATA OUT bit 9-33, 10-27 SCIRXD FUNCTION bit 9-34, 10-28 SCITXD DATA DIR bit 9-33, 10-27 SCITXD DATA IN bit 9-33, 10-27 SCITXD DATA OUT bit 9-33, 10-27 SCITXD FUNCTION bit 9-33, 10-27 SCIPRI (SCI priority control) register 9-35, 10-29 SCI ESPEN bit 9-35, 10-29 SCI RX PRIORITY bit 9-15, 9-35, 10-12, 10-29 SCI STEST bit 9-35, 10-29 SCI TX PRIORITY bit 9-15, 9-35, 10-12, 10-29 SCIRXD DATA DIR bit (SCIPC2 register) 10-28 SCIRXD DATA IN bit (SCIPC2 register) 10-27 9-34, 9-33, 9-33, 9-34, 9-33, 9-33, 9-33, 9-33,
SPI 11-1 to 11-22 block diagram 11-3, C-12 clock sources 11-10 bit rates (baud) 11-10
selecting 11-15
SCIRXD DATA OUT bit (SCIPC2 register) 10-27 SCIRXD FUNCTION bit (SCIPC2 register) 10-28 SCITXD DATA DIR bit (SCIPC2 register) 10-27 SCITXD DATA IN bit (SCIPC2 register) 10-27
in master mode 11-10 in slave mode 11-10 communications 11-5 disabling transmissions 11-16 enabling transmissions 11-16 control registers 11-13 to 11-22, B-5 overview 11-4 port control registers 11-19 to 11-21 SPIBUF (serial input buffer) 11-18 SPICCR (SPI configuration control) 11-14 to 11-15 SPICTL (SPI operation control) 11-16 to 11-17 SPIDAT (serial data) 11-18 SPIPC1 (SPI port control 1) 11-19 SPIPC2 (SPI port control 2) 11-20 to 11-21 SPIPRI (SPI interrupt priority control) 11-22 data format 11-8 character length 11-8
selecting 11-15
SCITXD DATA OUT bit (SCIPC2 register) 10-27 SCITXD FUNCTION bit (SCIPC2 register) 10-27 SDAT0-7 bits (SPIDAT register) SDIP 19-6, 19-9, 19-10 17-4 17-5 section program counter (SPC) SECTIONS directive 11-18
serial peripheral interface. See SPI SETC (set carry) instruction 16-85 setting the C bit of ST 3-7 simulator 17-24 single-line communication 9-12, 10-10 9-8, 9-9, 9-10, 9-25, SLEEP bit (SCICTL register) 10-7, 10-8, 10-9, 10-21 socket, converter 19-27 17-3 17-4 software development flow
components 11-8 illustration 11-8 description 1-12 example 11-12 initialization 11-11 changing configuration 11-11 interrupts 11-9 disabling 11-17 enabling 11-17 priority level 5-5 master/slave connection 11-5 memory map 11-4 operating modes 11-6 to 11-7 master 11-6
clock source 11-10 communications 11-5
selecting 11-16 slave 11-6 to 11-7
clock source 11-10 communications 11-5
overview 11-2 to 11-4 physical description 11-2 to 11-3 pins SPICLK 11-2, 11-5, 11-6 to 11-7, 11-11
control register 11-19 selecting polarity 11-14
SPC (section program counter) Index-22
Index
SPI (continued) SPISIMO 11-2, 11-6 to 11-7
control register 11-20 to 11-22
SPISOMI 11-2, 11-6
control register 11-20
receiving data, during low-power modes 4-8 reset 11-14 timings 18-86 to 18-88 differences A-9 to A-10 transmitting data, during low-power modes 4-8 SPI BIT RATE0-2 bits (SPICCR register) 11-10, 11-15 SPI CHAR0-2 bits (SPICCR register) SPI ESPEN bit (SPIPRI register) SPI INT ENA bit (SPICTL register) 11-17 SPI INT FLAG bit (SPICTL register) 11-16 SPI PRIORITY bit (SPIPRI register) SPI STEST bit (SPIPRI register) SPI SW RESET bit (SPICCR register) 11-14 SPIBUF (serial input buffer) register clearing interrupt flag 11-9 definition 11-2 during data transmission 11-6 formatting 11-8 RCVD0-7 bits 11-18 11-22 11-6, 11-9, 11-6, 11-9, 11-9, 11-22 11-9, 11-11, 11-18 11-6,
SPIDAT (serial data) register 11-18 definition 11-2 during data transmission 11-6 to 11-7 formatting 11-8 to 11-9 initialization 11-11 to 11-12 SDAT0-7 bits 11-18 SPIPC1 (SPI port control 1) register SPICLK DATA DIR bit 11-19 SPICLK DATA IN bit 11-19 SPICLK DATA OUT bit 11-19 SPICLK FUNCTION bit 11-19 SPIPC2 (SPI port control 2) register SPISIMO DATA DIR bit 11-20 SPISIMO DATA IN bit 11-20 SPISIMO DATA OUT bit 11-20 SPISIMO FUNCTION bit 11-20 SPISOMI DATA DIR bit 11-21 SPISOMI DATA IN bit 11-20 SPISOMI DATA OUT bit 11-20 SPISOMI FUNCTION bit 11-21 11-19
11-20 to 11-21
11-8, 11-15
11-22
SPIPRI (SPI interrupt priority control) register 11-22 SPI ESPEN bit 11-22 SPI PRIORITY bit 11-9, 11-22 SPI STEST bit 11-22 SPISIMO DATA DIR bit (SPIPC2 register) SPISIMO DATA IN bit (SPIPC2 register) SPISIMO DATA OUT bit (SPIPC2 register) SPISIMO FUNCTION bit (SPIPC2 register) SPISOMI DATA DIR bit (SPIPC2 register) SPISOMI DATA IN bit (SPIPC2 register) SPISOMI DATA OUT bit (SPIPC2 register) SPISOMI FUNCTION bit (SPIPC2 register) stack definition 3-4 function during interrupt routine POP instruction 16-74 PUSH instruction 16-75 11-20 11-20 11-20 11-20 11-21 11-20 11-20 11-21
SPICCR (SPI configuration control) register 11-14 to 11-15 CLOCK POLARITY bit 11-10, 11-14 SPI BIT RATE0-2 bits 11-6, 11-10, 11-15 SPI CHAR0-2 bits 11-8, 11-15 SPI SW RESET bit 11-9, 11-11, 11-14 SPICLK DATA DIR bit (SPIPC1 register) SPICLK DATA IN bit (SPIPC1 register) SPICLK DATA OUT bit (SPIPC1 register) SPICLK FUNCTION bit (SPIPC1 register) SPICTL (SPI operation control) register 11-16 to 11-17 MASTER/SLAVE bit 11-6, 11-11, 11-16 RECEIVER OVERRUN bit 11-9, 11-16 SPI INT ENA bit 11-6, 11-9, 11-17 SPI INT FLAG bit 11-6, 11-9, 11-16 TALK bit 11-7, 11-11, 11-16 11-19 11-19 11-19 11-19
5-2
stack pointer (SP) accessing the register file 3-11 definition 3-2 description 3-4 to 3-5 during context switch routine 5-8 during reset sequence 5-20 example 3-4 limits 3-5 loading using LDSP 3-4, 16-66
Index-23
Index
stack pointer (SP) (continued) partitioning the register file 3-10 storing using STSP 16-86 value during low-power modes 4-8 value during reset 3-4 stack pointer relative addressing mode starter kit 17-24 ordering information 19-25 16-10
system configuration 4-2 to 4-17 automatic wait states 4-5 to 4-8 control registers 4-2, 4-13 to 4-17, B-3 SCCR0 (system control and configuration 0) 4-13 to 4-14
overview of bits 4-2
SCCR1 (system control and configuration 1) 4-15
overview of bits 4-2
status register (ST) 3-5 to 3-7 bit definitions 3-5, 16-22 changing value using LDST 3-6, 16-67 clearing C bit using CLRC 3-7 definition 3-2 diagram 3-3, 3-5 during context switch routine 5-8 during interrupt routine 5-2 during reset sequence 5-20 restoring value using RTI 3-6 setting C bit using SETC 3-7 value during interrupt 3-6 value during low-power modes 4-8 STOP BITS bit (SCICCR register) SUB (subtract) instruction 16-87 V bit setting (in ST) 3-6 subroutine instructions CALL 16-39 CALLR 16-40 RTS 16-81 TRAP 16-89 subtraction instructions DEC 16-48 DSB 16-52 SBB 16-82 SUB 16-87 supply voltage supervisor symbol conventions general, v timing parameters 5-22 to 5-23 16-88 SWAP (swap nibbles) instruction 9-22, 10-18 16-86 STSP (store stack pointer) instruction
SCCR2 (system control and configuration 2) 4-16 to 4-17
overview of bits 4-2
oscillator
4-4
T
T1 INPUT SELECT0-2 bits (T1CTL1 register) 7-33 T1 MODE bit (T1CTL4 register) 7-10, 7-38 T1 OVRFL INT ENA bit (T1CTL2 register) 7-6, 7-13, 7-20, 7-35 T1 OVRFL INT FLAG bit (T1CTL2 register) 7-6, 7-13, 7-35 T1 PRIORITY bit (T1PRI register) 7-43 T1 STEST bit (T1PRI register) 7-43 T1 SW RESET bit (T1CTL2 register) 7-6, 7-13, 7-35 T1C1 INT ENA bit (T1CTL3 register) 7-7, 7-10, 7-20, 7-37 T1C1 INT FLAG bit (T1CTL3 register) 7-7, 7-8, 7-10, 7-11, 7-36 T1C1 OUT ENA bit (T1CTL4 register) 7-7, 7-10, 7-38 T1C1 RST ENA bit (T1CTL4 register) 7-7, 7-10, 7-39 T1C2 INT ENA bit (T1CTL3 register) 7-8, 7-11, 7-20, 7-37 T1C2 INT FLAG bit (T1CTL3 register) 7-36 T1C2 OUT ENA bit (T1CTL4 register) 7-8, 7-11, 7-38 T1CR OUT ENA bit (T1CTL4 register) 7-39 T1CR RST ENA bit (T1CTL4 register) 7-15, 7-39 T1CTL1 (timer 1 control 1) register 7-32 to 7-33 T1 INPUT SELECT0-2 bits 7-33 WD INPUT SELECT0-2 bits 7-25, 7-27 WD OVRFL TAP SEL bit 7-17, 7-23, 7-25, 7-27, 7-32
18-2 17-4
symbol tables in object files
symbols, device markings members with mask-ROM 19-17 members with program EPROM (OTP) 19-22 members with reprogrammable EPROM 19-23 SYSCLK Index-24 7-17, 7-18, 8-14
Index
T1CTL2 (timer 1 control 2) register 7-34 to 7-35 caution when modifying 7-35 differences in bits A-5 T1 OVRFL INT ENA bit 7-6, 7-13, 7-20, 7-35 T1 OVRFL INT FLAG bit 7-6, 7-13, 7-35 T1 SW RESET bit 7-6, 7-13, 7-35 WD contact option A-5 WD OVRFL INT ENA bit 7-34 WD OVRFL INT FLAG bit 7-24, 7-26, 7-35 as source of reset 5-19 device differences A-5 WD OVRFL RST ENA bit 7-23, 7-27, 7-34 device differences A-5 T1CTL3 (timer 1 control 3) register 7-36 to 7-37 caution when modifying 7-37 T1C1 INT ENA bit 7-7, 7-10, 7-20, 7-37 T1C1 INT FLAG bit 7-7, 7-8, 7-10, 7-11, 7-36 T1C2 INT ENA bit 7-8, 7-11, 7-20, 7-37 T1C2 INT FLAG bit 7-36 T1EDGE INT ENA bit 7-14, 7-20, 7-37 T1EDGE INT FLAG bit 7-9, 7-12, 7-14, 7-15, 7-36 T1CTL4 (timer 1 control 4) register 7-38 to 7-39 T1 MODE bit 7-10, 7-38 T1C1 OUT ENA bit 7-7, 7-10, 7-38 T1C1 RST ENA bit 7-7, 7-10, 7-39 T1C2 OUT ENA bit 7-8, 7-11, 7-38 T1CR OUT ENA bit 7-39 T1CR RST ENA bit 7-15, 7-39 T1EDGE DET ENA bit 7-12, 7-14, 7-15, 7-39 T1EDGE POLARITY bit 7-6, 7-12, 7-14, 7-15, 7-39 T1EDGE DET ENA bit (T1CTL4 register) 7-12, 7-14, 7-15, 7-39 T1EDGE INT ENA bit (T1CTL3 register) 7-14, 7-20, 7-37 T1EDGE INT FLAG bit (T1CTL3 register) 7-9, 7-12, 7-14, 7-15, 7-36 T1EDGE POLARITY bit (T1CTL4 register) 7-6, 7-12, 7-14, 7-15, 7-39 T1EVT DATA DIR bit (T1PC1 register) 7-40 T1EVT DATA IN bit (T1PC1 register) 7-40 T1EVT DATA OUT bit (T1PC1 register) 7-40 T1EVT FUNCTION bit (T1PC1 register) 7-40 T1IC/CR DATA DIR bit (T1PC2 register) 7-42 T1IC/CR DATA FUNCTION bit (T1PC2 register) 7-42 T1IC/CR DATA IN bit (T1PC2 register) 7-41
T1IC/CR DATA OUT bit (T1PC2 register) T1PC1 (timer 1 port control 1) register T1EVT DATA DIR bit 7-40 T1EVT DATA IN bit 7-40 T1EVT DATA OUT bit 7-40 T1EVT FUNCTION bit 7-40
7-42
7-40
T1PC2 (timer 1 port control 2) register 7-41 to 7-42 T1IC/CR DATA DIR bit 7-42 T1IC/CR DATA FUNCTION bit 7-42 T1IC/CR DATA IN bit 7-41 T1IC/CR DATA OUT bit 7-42 T1PWM DATA DIR bit 7-41 T1PWM DATA FUNCTION bit 7-41 T1PWM DATA IN bit 7-41 T1PWM DATA OUT bit 7-41 T1PRI (timer 1 interrupt priority control) register 7-43 T1 PRIORITY bit 7-43 T1 STEST bit 7-43 T1PWM DATA DIR bit (T1PC2 register) 7-41 T1PWM DATA FUNCTION bit (T1PC2 register) 7-41 T1PWM DATA IN bit (T1PC2 register) 7-41 7-41 T1PWM DATA OUT bit (T1PC2 register)
T2 INPUT SELECT0-1 bits (T2CTL1 register) 8-14 T2 MODE bit (T2CTL3 register) 8-10 8-6, 8-6 T2 OVRFL INT ENA bit (T2CTL1 register) 8-16 T2 OVRFL INT FLAG bit (T2CTL1 register) T2 PRIORITY bit (T2PRI register) 8-29 8-6, 8-19 8-6, 8-16 8-6 8-6, 8-23 8-6 8-8, 8-9, 8-21 8-8 8-9 8-16 T2 SW RESET bit (T2CTL1 register) T2C1 INT ENA bit (T2CTL2 register) T2C1 INT FLAG bit (T2CTL2 register) T2C1 OUT ENA bit (T2CTL3 register) T2C1 RST ENA bit (T2CTL3 register) T2C2 INT ENA bit (T2CTL2 register) T2C2 INT FLAG bit (T2CTL2 register) T2C2 OUT ENA bit (T2CTL3 register) T2CC2 INT ENA bit (T2CTL2 register)
T2CTL1 (timer 2 control 1) register 8-19 T2 INPUT SELECT0-1 bits 8-14 T2 OVRFL INT ENA bit 8-6, 8-16 T2 OVRFL INT FLAG bit 8-6 T2 SW RESET bit 8-6, 8-19
Index-25
Index
T2CTL2 (timer 2 control 2) register 8-20 to 8-22 caution when modifying 8-20 T2C1 INT ENA bit 8-6, 8-16 T2C1 INT FLAG bit 8-6 T2C2 INT ENA bit 8-8, 8-9, 8-21 T2C2 INT FLAG bit 8-8 T2CC2 INT ENA bit 8-16 T2EDGE1 INT ENA bit 8-9, 8-16 T2EDGE1 INT FLAG bit 8-9, 8-13, 8-20 T2EDGE2 INT ENA bit 8-16 T2EDGE2 INT FLAG bit 8-8, 8-13 T2CTL3 (timer 2 control 3) register 8-23 to 8-25 T2 MODE bit 8-10 T2C1 OUT ENA bit 8-6, 8-23 T2C1 RST ENA bit 8-6 T2C2 OUT ENA bit 8-9 T2EDGE1 DET ENA bit 8-9, 8-13, 8-16 T2EDGE1 OUT ENA bit 8-13 T2EDGE1 POLARITY bit 8-6, 8-13 T2EDGE1 RST ENA bit 8-13 T2EDGE2 DET ENA bit 8-16 T2EDGE2 POLARITY bit 8-13 T2EDGE1 DET ENA bit (T2CTL3 register) 8-9, 8-13, 8-16 T2EDGE1 INT ENA bit (T2CTL2 register) 8-9, 8-16 T2EDGE1 INT FLAG bit (T2CTL2 register) 8-9, 8-13, 8-20 T2EDGE1 OUT ENA bit (T2CTL3 register) 8-13 T2EDGE1 POLARITY bit (T2CTL3 register) 8-6, 8-13 T2EDGE1 RST ENA bit (T2CTL3 register) 8-13 T2EDGE2 DET ENA bit (T2CTL3 register) 8-16 T2EDGE2 INT ENA bit (T2CTL2 register) 8-16 T2EDGE2 INT FLAG bit (T2CTL2 register) 8-8, 8-13 T2EDGE2 POLARITY bit (T2CTL3 register) 8-13 T2PC1 (timer 2 port control 1) register 8-26 T2PC2 (timer 2 port control 2) register 8-27 to 8-28 T2PRI (timer 2 interrupt priority control) register 8-29 T2 PRIORITY bit 8-29 TALK bit (SPICTL register) 11-7, 11-11, 11-16 temperature ranges by device type 1-5, 1-13 defined 1-5, 19-18 three-line communication 9-13 Index-26
timer PACT, description 1-10, 1-11 watchdog, description 1-10 timer 1 block diagram 7-4 capabilities 7-2 clock 7-13, 7-16 to 7-19 counter duration 7-17 counter resolution 7-17 delays during compare equal 7-7 event counter mode 7-18 external clock input 7-17 pulse accumulator mode 7-18 selecting source 7-33 sources 7-16 counter (T1CNTR) 7-6 clock input 7-13 generating a rollover interrupt 7-6, 7-13 initialization 7-6 resetting 7-6, 7-13
during compare equal 7-6, 7-7, 7-10, 7-13 using the T1IC/CR pin 7-12
description 1-9 edge detection 7-12, 7-15 during capture/compare mode 7-15 during dual compare mode 7-15 generating an interrupt 7-12 overview 7-2 toggling the T1PWM pin 7-12 exiting standby mode 4-9 interrupts 7-20 clearing flags 7-20 control register 7-43 disabling 7-35
compare register interrupts 7-37
enabling 7-35
compare register interrupts 7-37
finding status 7-35 generating
by edge detection 7-12 during compare equal 7-7, 7-8, 7-10 with the T1IC/CR pin 7-12
overview 7-3 priority level 5-5 low-power modes 7-29 halt 7-29 standby 7-29 memory map 7-5
Index
timer 1 (continued) operating modes 7-10 to 7-14 capture/compare 7-13
block diagram 7-14, C-7 components 7-13 edge detection 7-15 function of capture/compare register 7-9 overview 7-4
timer 1 (continued)
resetting counter when equal 7-6, 7-7, 7-10, 7-13 sample registers values 7-8
dual compare 7-10 to 7-13
block diagram 7-11, C-6 components 7-10 edge detection 7-12, 7-15 function of capture/compare register 7-8 overview 7-4 PWM applications 7-12
overview 7-2, 7-5 T1CTL1 (timer 1 control 1) 7-32 to 7-33 T1CTL2 (timer 1 control 2) 7-34 to 7-35 T1CTL3 (timer 1 control 3) 7-36 to 7-37 T1CTL4 (timer 1 control 4) 7-38 to 7-39 T1PC1 (timer 1 port control 1) 7-40 T1PC2 (timer 1 port control 2) 7-41 to 7-42 T1PRI (timer 1 interrupt priority control) 7-43 reset sources 7-6, 7-13 watchdog counter overflow rates 7-18
timer 2 8-1 to 8-29 block diagram 8-3 capabilities 8-2 clock 8-14 to 8-15 block diagram 8-14 counter duration 8-14 counter resolution 8-14 event counter mode 8-15 pulse accumulator mode 8-15 sources 8-14 control registers B-10, B-14 counter (T2CNTR) 8-6 generating a rollover interrupt 8-6 initialization 8-6 resetting 8-6
during compare equal 8-6, 8-13
overview 7-4 selecting 7-10, 7-38 overview 7-2 to 7-5 pins definitions 7-4 overview 7-3 T1EVT 7-13, 7-17, 7-18
control register 7-40 overview 7-3
T1IC/CR
control register 7-41 to 7-42 determining transition direction 7-39 edge detection 7-15 generating an interrupt 7-12, 7-37 overview 7-3 resetting the counter 7-6, 7-12 toggling the T1PWM pin 7-12
T1PWM 7-15
control register 7-41 to 7-42 during compare equal 7-7, 7-8, 7-10, 7-11 overview 7-3 toggling 7-12
prescaler 7-16 to 7-19 block diagram 7-16, C-4 clock sources 7-16 overview 7-2 pulse accumulation 7-19 PWM applications, toggling the T1PWM pin 7-12 registers 7-30 to 7-43, B-6 capture/compare 7-8
during capture/compare mode 7-9 during dual compare mode 7-8
compare 7-6 to 7-8
clock delays 7-7 formula for registers values 7-7 initialization value 7-7
description 1-10 edge detection 8-13 during dual capture mode 8-13 during dual compare mode 8-13 overview 8-2 interrupts 8-16 clearing flags 8-16 control register 8-29 generating, during compare equal overview 8-2 priority level 5-5 vector sources 5-6 low-power modes 8-17 major components 8-6 to 8-9 memory map 8-5 operating modes 8-10 to 8-12 dual capture 8-11 to 8-13
block diagram 8-12, C-9 components 8-11
8-6, 8-9
Index-27
Index
timer 2 (continued)
edge detection 8-13 function of capture/compare register 8-9 overview 8-4
dual compare 8-10 to 8-11
block diagram 8-11, C-8 components 8-10 edge detection 8-13 function of capture/compare register 8-8 overview 8-4
overview 8-4 selecting 8-10 overview 8-2 to 8-5 pins definitions 8-4 overview 8-3 T2EVT 8-15
control register 8-26 overview 8-3
timings (continued) TMS370Cx2xA & 'x2x 18-18 to 18-19 TMS370Cx32A 18-22 to 18-23 TMS370Cx36A 18-27 to 18-28 TMS370Cx4xA 18-32 to 18-33 TMS370Cx5x, differences A-8 TMS370Cx5xA & 'x5xB 18-38 to 18-50 TMS370Cx6xA 18-46 TMS370Cx7xA 18-54 TMS370Cx8xA 18-59 TMS370Cx9xA 18-65 TMS370CxAxA 18-70 TMS370CxBxA 18-76 TMS370CxCxA 18-81 TMP prefix TMS prefix 19-16 19-16
T2IC1/CR 8-9, 8-12, 8-13
control register 8-27 to 8-28 overview 8-3 resetting the counter 8-6
T2IC2/PWM 8-12, 8-13
control register 8-27 to 8-28 during compare equal 8-6, 8-9 overview 8-3
registers 8-17 to 8-29 capture 8-7 to 8-8 capture/compare 8-8
during dual capture mode 8-9 during dual compare mode 8-8
compare 8-6 to 8-7
formula for registers values 8-7 resetting counter when equal 8-6, 8-13 sample registers values 8-7
overview 8-2, 8-4 T2CTL1 (timer 2 control 1) 8-19 T2CTL2 (timer 2 control 2) 8-20 to 8-22 T2CTL3 (timer 2 control 3) 8-23 to 8-25 T2PC1 (timer 2 port control 1) 8-26 T2PC2 (timer 2 port control 2) 8-27 to 8-28 T2PRI (timer 2 interrupt priority control) 8-29 reset sources 8-6
timings 18-1 to 18-52 EEPROM programming 18-7 EPROM programming 18-7 output signals 18-6 parameter measurements 18-2 parameter symbols 18-2 TMS370Cx0xA & 'x0x 18-10 to 18-11 TMS370Cx1xA & 'x1xB 18-14 to 18-15 Index-28
TMS370 family applications 1-2 architecture overview 1-7 to 1-12, 3-2 to 3-3 categories 1-4 description 1-1 development tools 17-1 to 17-27 ordering information 19-25 to 19-27 software development flow 17-3 differences A-1 to A-12 summary A-11 documentation, vii key features 1-5 numbering conventions 19-16 to 19-24 ordering information 19-1 to 19-27 development tools 19-25 to 19-27 mechanical data 19-6 to 19-15 prototyping device production flow 19-2 to 19-5 overview 1-1 to 1-12 packaging 19-6 to 19-15 pinouts and pin descriptions 2-1 to 2-39 summary of components (by device) 1-12 TMS370Cx0x electrical specifications 18-8 to 18-9 pinouts 2-2 timings ('x0xA & 'x0x) 18-10 to 18-11 TMS370Cx1x available pins 4-18 electrical specifications ('x1xA & 'x1xB) 18-12 to 18-13 PGA pinout H-3, H-4, H-5 pinouts 2-4, G-2, G-13 timings ('x1xA & 'x1xB) 18-14 to 18-15
Index
TMS370Cx2x available pins 4-18 electrical specifications ('x2xA & 'x2x) 18-16 to 18-17 PGA pinout H-7 pinouts 2-6, G-3, G-10, G-11 timings ('x2xA & 'x2x) 18-18 to 18-19 TMS370Cx32, pinout TMS370Cx36, pinout 2-8 2-11
TMS370Cx3x available pins 4-18 electrical specifications ('x32A) 18-20 to 18-21 electrical specifications ('x36A) 18-24 to 18-26 PGA pinout H-8, H-9 pinout G-4, G-5 timings ('x32A) 18-22 to 18-23 timings ('x36A) 18-27 to 18-28 TMS370Cx4x available pins 4-18 electrical specifications ('x4xA) 18-29 to 18-31 PGA pinout H-10, H-11, H-12 pinouts 2-14, G-6 timings ('x4xA) 18-32 to 18-33 TMS370Cx5x available pins 4-18 electrical specifications, differences A-8 electrical specifications ('x5xA & 'x5xB) 18-34 to 18-37 PGA pinout H-14, H-15, H-16, H-17 pinouts 2-16, G-7, G-8, G-9, G-12 timings, differences A-8 timings ('x5xA & 'x5x) 18-38 to 18-50 TMS370Cx6x available pins 4-18 electrical specifications ('x6xA) pinouts 2-20 timings ('x6xA) 18-46 TMS370Cx7x available pins 4-19 electrical specifications ('x7xA) pinouts 2-24 timings ('x7xA) 18-54 TMS370Cx8x available pins 4-19 electrical specifications ('x8xA) pinouts 2-27 timings ('x8xA) 18-59
18-43 to 18-45
18-51 to 18-53
18-57 to 18-58
TMS370Cx9x available pins 4-19 electrical specifications ('x9xA) 18-62 to 18-64 pinouts 2-30 timings ('x9xA) 18-65 TMS370CxAx available pins 4-19 electrical specifications ('xAxA) 18-68 to 18-69 pinouts 2-33 timings ('xAxA) 18-70 TMS370CxBx available pins 4-19 electrical specifications ('xBxA) 18-73 to 18-75 pinouts 2-35 timings ('xBxA) 18-76 TMS370CxCx available pins 4-19 electrical specifications ('xCxA) 18-79 to 18-80 pinouts 2-38 timings ('xCxA) 18-81 TMX prefix 19-16 top for programmer 17-25 trademarks, viii TRAP (trap to subroutine) instruction 16-89 trap vectors 3-14 TST (test, set flags from register) instruction 16-90 two-line communication 9-12, 9-13, 10-10 TX EMPTY bit (TXCTL register) 9-28, 10-23 TX pin 15-5 TXBUF (SCI transmitter data buffer) register 9-15, 9-31, 10-3, 10-8, 10-9, 10-12, 10-26 finding status 9-28, 10-23 TXDT0-7 bits 9-31, 10-26 TXBUF (SCI1 transmitter data buffer) register 9-5, 9-9, 9-10 TXBUFP (PACT-SCI TX data) register 15-48 PACT TXDT0-7 bits 15-48 TXCTL (SCI transmitter interrupt control and status) register 9-28, 10-23 SCI TX INT ENA bit 9-15, 9-28, 10-12, 10-23 TX EMPTY bit 9-28, 10-23 TXRDY bit 9-15, 9-28, 10-12, 10-23 TXDT0-7 bits (TXBUF register) 9-31, 10-26 TXENA bit (SCICTL register) 9-25, 10-21 TXRDY bit (TXCTL register) 9-15, 9-28, 10-12, 10-23 TXSHF register 9-5, 9-9, 9-10, 9-15, 10-3, 10-8, 10-9, 10-12
Index-29
Index
TXWAKE bit (SCICTL register) 9-8, 9-9, 9-10, 9-25, 10-7, 10-8, 10-9, 10-21 double-buffered WUT flag 9-9, 10-8
V
V bit (ST register) VCC3 pin 12-5 3-6 A-7 VCC1 and VCC2 pins, differences
VPPS bit (EPCTL register) 6-12, 6-13, 6-15 writing to EPROM 3-15 VREF pin VSS3 pin 12-6, 13-5, 14-5 12-5
W
W0 bit (EPCTL register) WAIT pin 4-5 to 4-8 definition 4-25 wait states 4-5 to 4-8 adding external memory access wait states 4-15 adding PF wait states 4-14 watchdog timer 7-21 to 7-28 as event counter 7-27 as interval timer 7-27 as pulse accumulator 7-27 block diagram 7-22 configurations selecting 7-32 summary 7-28, A-2 description 1-10 device differences A-2 to A-3 for the PACT module 15-31 hard watchdog 7-21, 7-25 to 7-26 additional system integrity 7-25 affect on INT1 pin 4-8, 5-9, 7-26 block diagram 7-25, C-5 generating a reset 7-25 summary 7-28, A-2 interrupts disabling 7-34 enabling 7-34 finding status 7-35 Index-30 6-12 6-5, 6-6, 6-8 W1W0 bit (DEECTL register)
watchdog timer (continued) low-power modes 7-29 during 4-8 entering 7-26 exiting 7-26 halt 7-29 standby 7-29 memory map 7-5 overflow rates 7-18, 7-23 overview 7-2, 7-21 registers 7-30 to 7-35, B-6 T1CTL1 (timer 1 control 1) 7-32 to 7-33 T1CTL2 (timer 1 control 2) 7-34 to 7-35 reset key (WDRST) 7-26, 7-27, 15-31 determining source of reset 4-5 reinitializing the watchdog counter 7-24 simple counter 7-21, 7-27 block diagram 7-27, C-5 summary 7-28, A-2 standard watchdog 7-21, 7-23 to 7-25 block diagram 7-23, C-5 generating a reset 7-23 initialization example 7-24 nonwatchdog mode 7-25 to 7-26 selecting 7-23 summary 7-28, A-2 watchdog mode 7-23 to 7-24 timeout as reset source 5-19 WD contact option A-5
WD INPUT SELECT0-2 bits (T1CTL1 register) 7-25, 7-27 WD OVRFL INT ENA bit (T1CTL2 register) WD OVRFL INT FLAG bit (T1CTL2 register) 7-26, 7-35 as source of reset 5-19 device differences A-5 WD OVRFL RST ENA bit (T1CTL2 register) 7-27, 7-34 device differences A-5 WD OVRFL TAP SEL bit (T1CTL1 register) 7-23, 7-25, 7-27, 7-32 7-34 7-24,
7-23,
7-17,
WDRST (watchdog reset) register, determining source of reset 4-5 WPR (write protection) register 3-13, 6-2, 6-3 to 6-4, 6-6 to 6-9 memory map 6-3 programming example 6-4
Index
write protect override 3-15, 3-16 write protection override 6-4 WUT flag 9-9, 9-10, 10-8, 10-9
X
XCHB (exchange with register B) instruction 16-91 XDS/22, 17-2, 17-12 to 17-17 breakpoint, trace, and timing functions 17-13 to 17-17 key features 17-13 to 17-17 breakpoints A/D converter module actions 12-17, 13-15, 14-17 SCI module actions 9-35, 10-29 SPI module actions 11-22
configuration requirements 17-16 hardware 17-12 key features 17-12 operating considerations 17-17 ordering information 19-26 target connectors 17-17 XOR (exclusive OR) instruction 16-92
Z
Z bit (ST register) zero bit (Z) 3-5 3-5
Index-31
Index-32
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