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SPARC V7.0
Instruction Set
for Embedded Real time 32-bit Computer (ERC32) for SPACE Applications
SPARC V7.0 Instruction Set
1. Assembly Language Syntax
The notations given in this section are taken from Sun's SPARC Assembler and are used to describe the suggested assembly language syntax for the instruction definitions given in Section 6.2. Understanding the use of type fonts is crucial to understanding the assembly language syntax in the instruction definitions. Items in typewriter font are literals, to be entered exactly as they appear. Items in italic font are metasymbols that are to be replaced by numeric or symbolic values when actual assembly language code is written. For example, asi would be replaced by a number in the range of 0 to 255 (the value of the bits in the binary instruction), or by a symbol that has been bound to such a number. Subscripts on metasymbols further identify the placement of the operand in the generated binary instruction. For example, regrs2 is a reg (i.e., register name) whose binary value will end up in the rs2 field of the resulting instruction.
1.1. Register Names
reg A reg is an integer unit register. It can have a value of: %0 through %31 all integer registers %g0 through %g7 global registers--same as %0 through %7 %o0 through %o7 out registers--same as %8 through %15 %l0 through %l7 local registers--same as %16 through %23 %i0 through %i7 in registers--same as %24 through %31 Subscripts further identify the placement of the operand in the binary instruction as one of the following: --rs1 field regrs1 --rs2 field regrs2 --rd field regrd freg A freg is a floating-point register. It can have a value from %f0 through %f31. Subscripts further identify the placement of the operand in the binary instruction as one of the following: --rs1 field fregrs1 --rs2 field fregrs2 --rd field fregrd creg A creg is a coprocessor register. It can have a value from %c0 through %c31. Subscripts further identify the placement of the operand in the binary instruction as one of the following: --rs1 field cregrs1 --rs2 field cregrs2 --rd field cregrd
1.2. Special Symbol Names
Certain special symbols need to be written exactly as they appear in the syntax table. These appear in typewriter font, and are preceded by a percent sign (%). The percent sign is part of the symbol name; it must appear as part of the literal value.
MATRA MHS Rev. A (10/09/96)
1
SPARC V7.0
The symbol names are: %psr Processor State Register %wim Window Invalid Mask register %tbr Trap Base Register %y Y register %fsr Floating-point State Register %csr Coprocessor State Register %fq Floating-point Queue %cq Coprocessor Queue %hi Unary operator that extracts high 22 bits of its operand %lo Unary operator that extracts low 10 bits of its operand
1.3. Values
Some instructions use operands comprising values as follows: simm13--A signed immediate constant that fits in 13 bits const22--A constant that fits in 22 bits asi--An alternate address space identifier (0 to 255)
1.4. Label
A label is a sequence of characters comprised of alphabetic letters (a-z, A-Z (upper and lower case distinct)), underscore ( _ ), dollar sign ($), period (.), and decimal digits (0-9), but which does not begin with a decimal digit. Some instructions offer a choice of operands. These are grouped as follows: regaddr: reg rs1 reg rs1 + reg rs2 address: reg rs1 reg rs1 + reg rs2 reg rs1 + simm13 reg rs1 - simm13 simm13 simm13 + reg rs1 reg_or_imm: reg rs2 simm13
1.5. Instruction Mnemonics
Figure 1.1 illustrates the mnemonics used to describe the SPARC instruction set. Note that some combinations possible in Figure 1.1 do not correspond to valid instructions (such as store signed or floating-point convert extended to extended). Refer to the instruction summary on page 6-6 for a list of valid SPARC instructions.
2
MATRA MHS Rev. A (10/09/96)
SPARC V7.0
Data Transfer
Signed Unsigned LoaD STore Byte Halfword word Double word Floating point Coprocessor normal Alternate
single Double
register Status Register Queue
atomic SWAP word
atomic Load Store Unsigned Byte
Integer Operations
AND OR XOR ADD SUB normal Not normal set CC Shift Left Right Logical Arithmetic
normal eXtended Y PSR WIM TBR
normal set CC
Tagged
ADD SUB
set CC
normal Trap oVerflow
ReaD WRite
MULtiply Step set CC SETHI SAVE RESTORE
Floating Point Operations
Fp convert Integer Single Double eXtended TO Integer Single Double eXtended Fp Fp MOVe NEGate ABSolute Single
ADD SUBtract MULtiply DIVide SQuare RooT CoMPare CoMPare and Exception
Single Double eXtended
Control Transfer
Branch Integer CC Floating point CC Coprocessor CC normal Anull delay instruction JuMP and Link RETurn from Trap CALL Trap on Integer CC
Figure 1.1. SPARC Instruction Mnemonic Summary
MATRA MHS Rev. A (10/09/96)
3
SPARC V7.0
2. Definitions
This section provides a detailed definition for each CY7C601 instruction. Each definition includes: the instruction operation; suggested assembly language syntax; a description of the salient features, restrictions and trap conditions; a list of synchronous or floating-point\coprocessor traps which can occur as a consequence of executing the instruction; and the instruction format and op codes. Instructions are defined in alphabetical order with the instruction mnemonic shown in large bold type at the top of the page for easy reference. The instruction set summary that precedes the definitions, (Table 1.2), groups the instructions by type. Table 1.1 identifies the abbreviations and symbols used in the instruction definitions. An example of how some of the description notations are used is given below in Figure 1.2. Register names, labels and other aspects of the syntax used in these instructions are described in the previous section.
Brackets indicate data located at address specified by contents Contents of source register 1 Sign-extended immediate 13-bit field of instruction
Load data into destination register rd
LDD
Operation : r[rd] r[rd + 1] Assembler Syntax :
Load Doubleword
Contents of source register 2
LDD
[r[rs1] + (r[rs2] or sign_extend(simm13))] [(r[rs1] + (r[rs2] or sign_extend(simm13))) + 4]
An example of this instruction would be :
ldd [address], regrd
ldd [%g1 + 4], %6
which would add the contents of global register g1 to signed immediate value (4) to determine the load address. The resulting address is used to fetch and load doubleword data into the destination registers 6 and 7.
Description :
The LDD instruction moves a doubleword from memory into a destination register pair, r[rd] and r[rd+1]. The effective memory address is derived by summing the contents of r[rs1] and either the Figure 1.2. Instruction Description Table 1.1. Instruction Description Notations
Symbol a AND, OR XOR, etc. asr_reg c ccc CONCAT cond
Description Instruction field that controls instruction annulling during control transfers AND, OR, XOR, etc operators Any implemented ASR (Ancillary State ) The icc carry bit The coprocessor condition code field of the CCSR Concatenate Instruction field that selects the condition code test for branches
4
MATRA MHS Rev. A (10/09/96)
SPARC V7.0
Symbol creg CWP disp22 disp30 EC EF ET i icc imm22 n not nPC opc operand2 PC pS PSR r[15] rd r[rd] r[rd]<31> [r[rs1] + r[rs2]] rs1 rs2 S shcnt sign_extend(simm13) Symbol TBR tt uf Description Communication Coprocessor Register : can be %ccsr, %ccfr, %ccpr, %cccrc PSR`s Current Window Pointer field Instruction field that contains the 22-bit sign-extended displacement for branches Instruction field that contains the 30-bit word displacement for calls PSR`s Enable Coprocessor bit PSR`s Enable FPU bit PSR`s Enable Traps bit Instruction field that selects rs2 or sign_extend(simm13) as the second operand The integer condition code field of the PSR Instruction field that contains the 22-bit constant used by SETHI The icc negative bit Logical complement operator next Program Counter Instruction field that specifies the count for Coprocessor-operate instructions Either r[rs2] or sign_extend(simm13) Program Counter PSR`s previous Supervisor bit Processor State Register A directly addressed register (could be floating-point or coprocessor) Instruction field that specifies the destination register (except for store) Depending on context, the integer register (or its contents) specified by the instruction field, e.g. , rd, rs1, rs2 <> are used to specify bit fields of a particular register or I/O signal The contents of the address specified by r[rs1] + r[rs2] Instruction field that specifies the source 1 register Instruction field that specifies the source 2 register PSR`s Supervisor bit Instruction field that specifies the count for shift instructions Instruction field that contains the 13-bit, sign-extended immediate value Description Trap Base Register TBR`s trap type field Floating-point exception : underflow
MATRA MHS Rev. A (10/09/96)
5
SPARC V7.0
Symbol v WIM Y z x / <-7FFFFFF H + Description The icc overflow bit Window Invalid Mask register Y Register The icc zero bit Subtract Multiply Divide Replaced by Hexadecimal number representation Add
6
MATRA MHS Rev. A (10/09/96)
SPARC V7.0
Table 1.2. Instruction Set Summary
Name LDSB(LDSBA*) LDSH(LDSHA*) LDUB(LDUBA*) LDUH(LDUHA*) LD(LDA*) LDD(LDDA*) LDF LDDF LDFSR LDC LDDC LDCSR STB(STBA*) STH(STHA*) ST(STA*) STD(STDA*) STF STDF STFSR STDFQ* STC STDC STCSR STDCQ* LDSTUB(LDSTUBA*) SWAP(SWAPA*) ADD(ADDcc) ADDX(ADDXcc) TADDcc(TADDccTV) SUB(SUBcc) SUBX(SUBXcc) TSUBcc(TSUBccTV) MULScc AND(ANDcc) ANDN(ANDNcc) OR(ORcc) ORN(ORNcc) XOR(XORcc) XNOR(XNORcc) SLL SRL SRA SETHI SAVE RESTORE Bicc FBicc CBccc CALL JMPL RETT Ticc RDY RDPSR* RDWIM* RDTBR* WRY WRPSR* WRWIM* WRTBR* UNIMP IFLUSH FPop CPop
* privileged instruction
Operation (from Alternate Space) Load Signed Byte (from Alternate Space) Load Signed Halfword Load Unsigned Byte (from Alternate Space) Load Unsigned Halfword (from Alternate Space) Load Word (from Alternate Space) Load Doubleword (from Alternate Space) Load Floating Point Load Double Floating Point Load Floating Point State Register Load Coprocessor Load Double Coprocessor Load Coprocessor State Register Store Byte (into Alternate Space) Store Halfword (into Alternate Space) Store Word (into Alternate Space) Store Doubleword (into Alternate Space) Store Floating Point Store Double Floating Point Store Floating Point State Register Store Double Floating Point Queue Store Coprocessor Store Double Coprocessor Store Coprocessor State Register Store Double Coprocessor Queue Atomic Load/Store Unsigned Byte (in Alternate Space) Swap r Register with Memory (in Alternate Space) Add (and modify icc) Add with Carry (and modify icc) Tagged Add and modify icc (and Trap on overflow) Subtract (and modify icc) Subtract with Carry (and modify icc) Tagged Subtract and modify icc (and Trap on overflow) Multiply Step and modify icc And (and modify icc) And Not (and modify icc) Inclusive Or (and modify icc) Inclusive Or Not (and modify icc) Exclusive Or (and modify icc) Exclusive Nor (and modify icc) Shift Left Logical Shift Right Logical Shift Right Arithmetic Set High 22 Bits of r Register Save caller's window Restore caller's window Branch on Integer Condition Codes Branch on Floating Point Condition Codes Branch on Coprocessor Condition Codes Call Jump and Link Return from Trap Trap on Integer Condition Codes Read Y Register Read Processor State Register Read Window Invalid Mask Read Trap Base Register Write Y Register Write Processor State Register Write Window Invalid Mask Write Trap Base Register Unimplemented Instruction Instruction Cache Flush Floating Point Unit Operations Coprocessor Operations
Cycles 2 2 2 2 2 3 2 3 2 2 3 2 3 3 3 4 3 4 3 4 3 4 3 4 4 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1** 1** 1** 1** 2** 2** 1 (4 if Taken) 1 1 1 1 1 1 1 1 1 1 1 to Launch 1 to Launch
FP (CP) Ops
Read/Write Control Registers
Control Transfer
Arithmetic/Logical/Shift
Load and Store Instructions
** assuming delay slot is filled with useful instruction
MATRA MHS Rev. A (10/09/96)
7
SPARC V7.0
ADD
Operation: Assembler Syntax: Description: r[rd] add regrs1 , reg_or_imm, regrd
Add
r[rs1] + (r[rs2] or sign extnd(simm13))
ADD
The ADD instruction adds the contents of the register named in the rs1 field ,r[rs1], to either the contents of r[rs2] if the instruction's i bit equals zero, or to the 13-bit, sign-extended immediate operand contained in the instruction if i equals one. The result is placed in the register specified in the rd field. none
Traps: Format:
31 30 29
25 24
19 18
14
13
12
54
0
10
31 30 29
rd
000000
25 24 19 18
rs1
14
i=0
13 12
ignored
rs2
0
10
rd
000000
rs1
i=1
simm13
8
MATRA MHS Rev. A (10/09/96)
SPARC V7.0
ADDcc
Operation: r[rd] n z v c r[rd]<31>
Add and modify icc
r[rs1] + operand2, where operand2 = (r[rs2] or sign extnd(simm13)) if r[rd] =0 then 1, else 0 (r[rs1]<31> AND operand2<31> AND not r[rd]<31>) OR (not r[rs1]<31> AND not operand2<31> AND r[rd]<31>) (r[rs1]<31> AND operand2<31>) OR (not r[rd]<31> AND (r[rs1]<31> OR operand2<31>))
ADDcc
Assembler Syntax: Description:
addcc regrs1 , reg_or_imm, regrd ADDcc adds the contents of r[rs1] to either the contents of r[rs2] if the instruction's i bit equals zero, or to a 13-bit, sign-extended immediate operand if i equals one. The result is placed in the register specified in the rd field. In addition, ADDcc modifies all the integer condition codes in the manner described above. none
Traps: Format:
31 30 29
25 24
19 18
14
13
12
54
0
10
31 30 29
rd
010000
25 24 19 18
rs1
14
i=0
13 12
ignored
rs2
0
10
rd
010000
rs1
i=1
simm13
MATRA MHS Rev. A (10/09/96)
9
SPARC V7.0
ADDX
Operation: Assembler Syntax: Description: r[rd] addx regrs1 , reg_or_imm, regrd
Add with Carry
r[rs1] + (r[rs2] or sign extnd(simm13)) + c
ADDX
ADDX adds the contents of r[rs1] to either the contents of r[rs2] if the instruction's i bit equals zero, or to a 13-bit, sign-extended immediate operand if i equals one. It then adds the PSR's carry bit (c) to that result. The final result is placed in the register specified in the rd field. none
Traps: Format:
31 30 29
25 24
19 18
14
13
12
54
0
10
31 30 29
rd
001000
25 24 19 18
rs1
14
i=0
13 12
ignored
rs2
0
10
rd
001000
rs1
i=1
simm13
10
MATRA MHS Rev. A (10/09/96)
SPARC V7.0
ADDXcc
Operation: r[rd] n z v c r[rd]<31>
Add with Carry and modify icc
ADDXcc
r[rs1] + operand2 + c, where operand2 = (r[rs2] or sign extnd(simm13)) if r[rd] =0 then 1, else 0 (r[rs1]<31> AND operand2<31> AND not r[rd]<31>) OR (not r[rs1]<31> AND not operand2<31> AND r[rd]<31>) (r[rs1]<31> AND operand2<31>) OR (not r[rd]<31> AND (r[rs1]<31> OR operand2<31>))
Assembler Syntax: Description:
addxcc regrs1 , reg_or_imm, regrd ADDXcc adds the contents of r[rs1] to either the contents of r[rs2] if the instruction's i bit equals zero, or to a 13-bit, sign-extended immediate operand if i equals one. It then adds the PSR's carry bit (c) to that result. The final result is placed in the register specified in the rd field. ADDXcc also modifies all the integer condition codes in the manner described above. none
Traps: Format:
31 30 29
25 24
19 18
14
13
12
54
0
10
31 30 29
rd
011000
25 24 19 18
rs1
14
i=0
13 12
ignored
rs2
0
10
rd
011000
rs1
i=1
simm13
MATRA MHS Rev. A (10/09/96)
11
SPARC V7.0
AND
Operation: Assembler Syntax: Description: r[rd] and regrs1 , reg_or_imm, regrd
And
r[rs1] AND (r[rs2] or sign extnd(simm13))
AND
This instruction does a bitwise logical AND of the contents of register r[rs1] with either the contents of r[rs2] (if if bit field i=0) or the 13-bit, sign-extended immediate value contained in the instruction (if if bit field i=1). The result is stored in register r[rd]. none
Traps: Format:
31 30 29
25 24
19 18
14
13
12
54
0
10
31 30 29
rd
000001
25 24 19 18
rs1
14
i=0
13 12
ignored
rs2
0
10
rd
000001
rs1
i=1
simm13
12
MATRA MHS Rev. A (10/09/96)
SPARC V7.0
ANDcc
Operation: r[rd] n z v c Assembler Syntax: Description: r[rd]<31> if r[rd] =0 then 1, else 0 0 0
And and modify icc
r[rs1] AND (r[rs2] or sign extnd(simm13))
ANDcc
andcc regrs1 , reg_or_imm, regrd This instruction does a bitwise logical AND of the contents of register r[rs1] with either the contents of r[rs2] (if if bit field i=0) or the 13-bit, sign-extended immediate value contained in the instruction (if if bit field i=1). The result is stored in register r[rd]. ANDcc also modifies all the integer condition codes in the manner described above. none
Traps: Format:
31 30 29
25 24
19 18
14
13
12
54
0
10
31 30 29
rd
010001
25 24 19 18
rs1
14
i=0
13 12
ignored
rs2
0
10
rd
010001
rs1
i=1
simm13
MATRA MHS Rev. A (10/09/96)
13
SPARC V7.0
ANDN
Operation: Assembler Syntax: Description: r[rd] andn regrs1 , reg_or_imm, regrd
And Not
r[rs1] AND (r[rs2] or sign extnd(simm13))
ANDN
ANDN does a bitwise logical AND of the contents of register r[rs1] with the logical compliment (not) of either r[rs2] (if if bit field i=0) or the 13-bit, sign-extended immediate value contained in the instruction (if if bit field i=1). The result is stored in register r[rd]. none
Traps: Format:
31 30 29
25 24
19 18
14
13
12
54
0
10
31 30 29
rd
000101
25 24 19 18
rs1
14
i=0
13 12
ignored
rs2
0
10
rd
000101
rs1
i=1
simm13
14
MATRA MHS Rev. A (10/09/96)
SPARC V7.0
ANDNcc
Operation: r[rd] n z v c Assembler Syntax: Description: r[rd]<31> if r[rd] =0 then 1, else 0 0 0
And Not and modify icc
r[rs1] AND (r[rs2] or sign extnd(simm13))
ANDNcc
andncc regrs1 , reg_or_imm, regrd ANDNcc does a bitwise logical AND of the contents of register r[rs1] with the logical compliment (not) of either r[rs2] (if bit field i=0) or the 13-bit, sign-extended immediate value contained in the instruction (if bit field i=1). The result is stored in register r[rd]. ANDNcc also modifies all the integer condition codes in the manner described above. none
Traps: Format:
31 30 29
25 24
19 18
14
13
12
54
0
10
31 30 29
rd
010101
25 24 19 18
rs1
14
i=0
13 12
ignored
rs2
0
10
rd
010101
rs1
i=1
simm13
MATRA MHS Rev. A (10/09/96)
15
SPARC V7.0
Bicc
Operation: PC nPC If condition true then nPC else nPC Assembler Syntax:
Integer Conditional Branch
Bicc
PC + (sign extnd(disp22) x 4)
nPC + 4
ba{,a} bn{,a} bne{,a} be{,a} bg{,a} ble{,a} bge{,a} bl{,a} bgu{,a} bleu{,a} bcc{,a} bcs{,a} bpos{,a} bneg{,a} bvc{,a} bvs{,a}
label label label label label label label label label label label label label label label label
synonym: bnz synonym: bz
synonym: bgeu synonym: blu
Note: The instruction's annul bit field, a, is set by appending ,a" after the branch name. If it is not appended, the a field is automatically reset. ,a" is shown in braces because it is optional. Description: The Bicc instructions (except for BA and BN) evaluate specific integer condition code combinations (from the PSR's icc field) based on the branch type as specified by the value in the instruction's cond field. If the specified combination of condition codes evaluates as true, the branch is taken, causing a delayed, PC-relative control transfer to the address (PC + 4) + (sign extnd(disp22) x 4). If the condition codes evaluate as false, the branch is not taken. Refer to Section NO TAG for additional information on control transfer instructions. If the branch is not taken, the annul bit field (a) is checked. If a is set, the instruction immediate ly following the branch instruction (the delay instruction) is not executed (i.e., it is annulled). If the annul field is zero, the delay instruction is executed. If the branch is taken, the annul field is ignored, and the delay instruction is executed. See Section NO TAG regarding delay branch instructions. Branch Never (BN) executes like a NOP, except it obeys the annul field with respect to its delay instruction. Branch Always (BA), because it always branches regardless of the condition codes, would nor mally ignore the annul field. Instead, it follows the same annul field rules: if a=1, the delay instruction is annulled; if a=0, the delay instruction is executed. The delay instruction following a Bicc (other than BA) should not be a delayed control transfer instruction. The results of following a Bicc with another delayed control transfer instruction are implementation dependent and therefore unpredictable. Traps: 16 none MATRA MHS Rev. A (10/09/96)
SPARC V7.0
Mnemonic BN BE BLE BL BLEU BCS BNEG BVS BA BNE BG BGE BGU BCC BPOS BVC Format:
31 30 29 28 25 24 22 21 0
Cond. 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Branch Never
Operation No test z Branch on Equal Branch on Less or Equal Branch on Less Branch on Less or Equal, Unsigned Branch on Carry Set (Less than, Unsigned) Branch on Negative Branch on oVerflow Set Branch Always Branch on Not Equal Branch on Greater Branch on Greater or Equal Branch on Greater, Unsigned Branch on Carry Clear (Greater than or Equal, Unsigned) Branch on Positive Branch on oVerflow Clear
icc Test
z OR (n XOR v) n XOR v c OR z c n v No test not z not(z OR (n XOR v)) not(n XOR v) not(c OR z) not c not n not v
00
a
cond.
010
disp22
MATRA MHS Rev. A (10/09/96)
17
SPARC V7.0
CALL
Operation: r[15] PC nPC Assembler Syntax: Description: PC nPC PC + (disp30 x 4)
Call
CALL
call label The CALL instruction causes a delayed, unconditional, PC-relative control transfer to the address (PC + 4) + (disp30 x 4). The CALL instruction does not have an annul bit, therefore the delay slot instruction following the CALL instruction is always executed (See Section NO TAG). CALL first writes its return address (PC) into the outs register, r[15], and then adds 4 to the PC. The 32-bit displacement which is added to the new PC is formed by appending two low-order zeros to the 30-bit word displacement contained in the instruction. Consequently, the target address can be anywhere in the CY7C601's user or supervisor address space. If the instruction following a CALL uses register r[15] as a source operand, hardware interlocks add a one cycle delay. Programming note: a register indirect CALL can be constructed using a JMPL instruction with rd set to 15.
Traps: Format:
none
31 30
29
0
01
disp30
18
MATRA MHS Rev. A (10/09/96)
SPARC V7.0
CBccc
Operation: PC nPC else nPC Assembler Syntax:
Coprocessor Conditional Branch
CBccc
If condition true then nPC nPC + 4
PC + (sign extnd(disp22) x 4)
cba{,a} cbn{,a} cb3{,a} cb2{,a} cb23{,a} cb1{,a} cb13{,a} cb12{,a} cb123{,a} cb0{,a} cb03{,a} cb02{,a} cb023{,a} cb01{,a} cb013{,a} cb012{,a}
label label label label label label label label label label label label label label label label
Note: The instruction's annul bit field, a, is set by appending ,a" after the branch name. If it is not appended, the a field is automatically reset. ,a" is shown in braces because it is optional. Description: The CBccc instructions (except for CBA and CBN) evaluate specific coprocessor condition code combinations (from the CCC<1:0> inputs) based on the branch type as specified by the value in the instruction's cond field. If the specified combination of condition codes evaluates as true, the branch is taken, causing a delayed, PC-relative control transfer to the address (PC + 4) + (sign extnd(disp22) x 4). If the condition codes evaluate as false, the branch is not taken. See Section NO TAG regarding control transfer instructions. If the branch is not taken, the annul bit field (a) is checked. If a is set, the instruction immediate ly following the branch instruction (the delay instruction) is not executed (i.e., it is annulled). If the annul field is zero, the delay instruction is executed. If the branch is taken, the annul field is ignored, and the delay instruction is executed. See Section NO TAG regarding delayed branch ing. Branch Never (CBN) executes like a NOP, except it obeys the annul field with respect to its delay instruction. Branch Always (CBA), because it always branches regardless of the condition codes, would nor mally ignore the annul field. Instead, it follows the same annul field rules: if a=1, the delay instruction is annulled; if a=0, the delay instruction is executed. To prevent misapplication of the condition codes, a non coprocessor instruction must immedi ately precede a CBccc instruction. A CBccc instruction generates a cp_disabled trap (and does not branch or annul) if the PSR's EC bit is reset or if no coprocessor is present. MATRA MHS Rev. A (10/09/96) 19
SPARC V7.0
Traps: cp_disabled cp_exception Mnemonic CBN CB123 CB12 CB13 CB1 CB23 CB2 CB3 CBA CB0 CB03 CB02 CB023 CB01 CB013 CB012 Format:
31 30 29 28 25 24 22 21 0
cond. 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
CCC<1:0> test Never 1 or 2 or 3 1 or 2 1 or 3 1 2 or 3 2 3 Always 0 0 or 3 0 or 2 0 or 2 or 3 0 or 1 0 or 1 or 3 0 or 1 or 2
00
a
cond.
111
disp22
20
MATRA MHS Rev. A (10/09/96)
SPARC V7.0
CPop
Operation: Assembler Syntax: Description: Unspecified
Coprocessor Operate
Dependent on Coprocessor implementation
CPop
CPop1 and CPop2 are the instruction formats for coprocessor operate instructions. The op3 field for CPop1 is 110110; for CPop2 it's 110111. The coprocessor operations themselves are encoded in the opc field and are dependent on the coprocessor implementation. Note that this does not include load/ store coprocessor instructions, which fall into the integer unit's load/store instruction category. All CPop instructions take all operands from, and return all results to, the coprocessor's regis ters. The data types supported, how the operands are aligned, and whether a CPop generates a cp_exception trap are Coprocessor dependent. A CPop instruction causes a cp_disabled trap if the PSR's EC bit is reset or if no coprocessor is present.
Traps:
cp_disabled cp_exception
Format:
31 30 29 25 24 19 18 14 13 54 0
10
31 30 29
rd
110110
25 24 19 18
rs1
14 13
opc
54
rs2
0
10
rd
110111
rs1
opc
rs2
MATRA MHS Rev. A (10/09/96)
21
SPARC V7.0
FABSs
Operation: Assembler Syntax: Description: f[rd]s
Absolute Value Single (FPU Instruction Only)
f[rs2]s AND 7FFFFFFF H
FABSs
fabss fregrs2 , fregrd The FABSs instruction clears the sign bit of the word in f[rs2] and places the result in f[rd]. It does not round. Since rs2 can be either an even or odd register, FABSs can also operate on the high order words of double and extended operands, which accomplishes sign bit clear for these data types.
Traps:
fp_disabled fp_exception*
Format:
31 30 29 25 24 19 18 14 13 54 0
10
rd
110100
ignored
000001001
rs2
* NOTE: An attempt to execute any FP instruction will cause a pending FP exception to be recognized by the integer unit.
22
MATRA MHS Rev. A (10/09/96)
SPARC V7.0
FADDd
Operation: Assembler Syntax: Description: f[rd]d f[rs1]d + f[rs2]d
Add Double (FPU Instruction Only)
FADDd
faddd fregrs1 , fregrs2 , fregrd The FADDd instruction adds the contents of f[rs1] CONCAT f[rs1+1] to the contents of f[rs2] CONCAT f[rs2+1] as specified by the ANSI/IEEE 754-1985 standard and places the results in f[rd] and f[rd+1]. fp_disabled fp_exception (of, uf, nv, nx)
Traps:
Format:
31 30 29 25 24 19 18 14 13 54 0
10
rd
110100
rs1
001000010
rs2
MATRA MHS Rev. A (10/09/96)
23
SPARC V7.0
FADDs
Operation: Assembler Syntax: Description: f[rd]s f[rs1]s + f[rs2]s
Add Single (FPU Instruction Only)
FADDs
fadds fregrs1 , fregrs2 , fregrd The FADDs instruction adds the contents of f[rs1] to the contents of f[rs2] as specified by the ANSI/ IEEE 754-1985 standard and places the results in f[rd]. fp_disabled fp_exception (of, uf, nv, nx)
Traps:
Format:
31 30 29 25 24 19 18 14 13 54 0
10
rd
110100
rs1
001000001
rs2
24
MATRA MHS Rev. A (10/09/96)
SPARC V7.0
FADDx
Operation: Assembler Syntax: Description: f[rd]x f[rs1]x + f[rs2]x
Add Extended (FPU Instruction Only)
FADDx
faddx fregrs1 , fregrs2 , fregrd The FADDx instruction adds the contents of f[rs1] CONCAT f[rs1+1] CONCAT f[rs1+2] to the contents of f[rs2] CONCAT f[rs2+1] CONCAT f[rs2+2] as specified by the ANSI/IEEE 754-1985 standard and places the results in f[rd], f[rd+1], and f[rd+2]. fp_disabled fp_exception (of, uf, nv, nx)
Traps:
Format:
31 30 29 25 24 19 18 14 13 54 0
10
rd
110100
rs1
001000011
rs2
MATRA MHS Rev. A (10/09/96)
25
SPARC V7.0
FBfcc
Operation: PC nPC else nPC Assembler Syntax:
Floating-Point Conditional Branch
FBfcc
If condition true then nPC nPC + 4
PC + (sign extnd(disp22) x 4)
fba{,a} fbn{,a} fbu{,a} fbg{,a} fbug{,a} fbl{,a} fbul{,a} fblg{,a} fbne{,a} fbe{,a} fbue{,a} fbge{,a} fbuge{,a} fble{,a} fbule{,a} fbo{,a}
label label label label label label label label label label label label label label label label
synonym: fbnz synonym: fbz
Note: The instruction's annul bit field, a, is set by appending ,a" after the branch name. If it is not appended, the a field is automatically reset. ,a" is shown in braces because it is optional. Description: The FBfcc instructions (except for FBA and FBN) evaluate specific floating-point condition code combinations (from the FCC<1:0> inputs) based on the branch type, as specified by the value in the instruction's cond field. If the specified combination of condition codes evaluates as true, the branch is taken, causing a delayed, PC-relative control transfer to the address (PC + 4) + (sign extnd(disp22) x 4). If the condition codes evaluate as false, the branch is not taken. See Section NO TAG for additional information on control transfer instructions. If the branch is not taken, the annul bit field (a) is checked. If a is set, the instruction immediate ly following the branch instruction (the delay instruction) is not executed (i.e., it is annulled). If the annul field is zero, the delay instruction is executed. If the branch is taken, the annul field is ignored, and the delay instruction is executed. See Section NO TAG regarding delayed branch instructions. Branch Never (FBN) executes like a NOP, except it obeys the annul field with respect to its delay instruction. Branch Always (FBA), because it always branches regardless of the condition codes, would nor mally ignore the annul field. Instead, it follows the same annul field rules: if a=1, the delay instruction is annulled; if a=0, the delay instruction is executed. To prevent misapplication of the condition codes, a non-floating point instruction must im mediately precede an FBfcc instruction. An FBfcc instruction generates an fp_disabled trap (and does not branch or annul) if the PSR's EF bit is reset or if no Floating Point Unit is present. 26 MATRA MHS Rev. A (10/09/96)
SPARC V7.0
Traps: fp_disabled fp_exception* Mnemonic FBN FBNE FBLG FBUL FBL FBUG FBG FBU FBA FBE FBUE FBGE FBUGE FBLE FBULE FBO Format:
31 30 29 28 25 24 22 21 0
Cond. 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Branch Never
Operation Branch on Not Equal Branch on Less or Greater Branch on Unordered or Less Branch on Less Branch on Unordered or Greater Branch on Greater Branch on Unordered Branch Always Branch on Equal Branch on Unordered or Equal Branch on Greater or Equal Branch on Unordered or Greater or Equal Branch on Less or Equal Branch on Unordered or Less or Equal Branch on Ordered
fcc Test no test U or L or G L or G U or L L U or G G U no test E U or E G or E U or G or E L or E U or L or E L or G or E
00
a
cond.
110
disp22
* NOTE: An attempt to execute any FP instruction will cause a pending FP exception to be recognized by the integer unit.
MATRA MHS Rev. A (10/09/96)
27
SPARC V7.0
FCMPd
Operation: Assembler Syntax: Description: fcc
Compare Double (FPU Instruction Only)
f[rs1]d COMPARE f[rs2]d
FCMPd
fcmpd fregrs1 , fregrs2 FCMPd subtracts the contents of f[rs2] CONCAT f[rs2+1] from the contents of f[rs1] CONCAT f[rs1+1] following the ANSI/IEEE 754-1985 standard. The result is evaluated, the FSR's fcc bits are set accordingly, and then the result is discarded. The codes are set as follows: fcc 0 1 2 3 relation fs1 = fs2 fs1 < fs2 fs1 > fs2 fs1 ? fs2 (unordered)
In this table, fs1 stands for the contents of f[rs1], f[rs1+1] and fs2 represents the contents of f[rs2], f[rs2+1]. Compare instructions are used to set up the floating point condition codes for a subsequent FBfcc instruction. However, to prevent misapplication of the condition codes, at least one non-floating point instruction must be executed between an FCMP and a subsequent FBfcc instruction. FCMPd causes an invalid exception (nv) if either operand is a signaling NaN. Traps: fp_disabled fp_exception (nv)
Format:
31 30 29 25 24 19 18 14 13 54 0
10
ignored
110101
rs1
001010010
rs2
28
MATRA MHS Rev. A (10/09/96)
SPARC V7.0
FCMPEd
Operation: Assembler Syntax: Description: fcc
Compare Double and Exception if Unordered (FPU Instruction Only)
f[rs1]d COMPARE f[rs2]d
FCMPEd
fcmped freg rs1 , fregrs2 FCMPEd subtracts the contents of f[rs2] CONCAT f[rs2+1] from the contents of f[rs1] CONCAT f[rs1+1] following the ANSI/IEEE 754-1985 standard. The result is evaluated, the FSR's fcc bits are set accordingly, and then the result is discarded. The codes are set as follows: fcc 0 1 2 3 Relation fs1 = fs2 fs1 < fs2 fs1 > fs2 fs1 ? fs2 (unordered)
In this table, fs1 stands for the contents of f[rs1], f[rs1+1] and fs2 represents the contents of f[rs2], f[rs2+1]. Compare instructions are used to set up the floating point condition codes for a subsequent FBfcc instruction. However, to prevent misapplication of the condition codes, at least one non-floating point instruction must be executed between an FCMP and a subsequent FBfcc instruction. FCMPEd causes an invalid exception (nv) if either operand is a signaling or quiet NaN. Traps: fp_disabled fp_exception (nv)
Format:
31 30 29 25 24 19 18 14 13 54 0
10
ignored
110101
rs1
001010110
rs2
MATRA MHS Rev. A (10/09/96)
29
SPARC V7.0
FCMPEs
Operation: Assembler Syntax: Description: fcc
Compare Single and Exception if Unordered (FPU Instruction Only)
f[rs1]s COMPARE f[rs2]s
FCMPEs
fcmpes fregrs1 , fregrs2 FCMPEs subtracts the contents of f[rs2] from the contents of f[rs1] following the ANSI/IEEE 754-1985 standard. The result is evaluated, the FSR's fcc bits are set accordingly, and then the result is discarded. The codes are set as follows: fcc 0 1 2 3 Relation fs1 = fs2 fs1 < fs2 fs1 > fs2 fs1 ? fs2 (unordered)
In this table, fs1 stands for the contents of f[rs1] and fs2 represents the contents of f[rs2]. Compare instructions are used to set up the floating point condition codes for a subsequent FBfcc instruction. However, to prevent misapplication of the condition codes, at least one non-floating point instruction must be executed between an FCMP and a subsequent FBfcc instruction. FCMPEs causes an invalid exception (nv) if either operand is a signaling or quiet NaN. Traps: fp_disabled fp_exception (nv)
Format:
31 30 29 25 24 19 18 14 13 54 0
10
ignored
110101
rs1
001010101
rs2
30
MATRA MHS Rev. A (10/09/96)
SPARC V7.0
FCMPEx x
Operation: Assembler Syntax: Description: fcc
Compare Extended and Exception if Unordered
FCMPE
(FPU Instruction Only)
f[rs1]x COMPARE f[rs2]x
fcmpex freg rs1 , fregrs2 FCMPEx subtracts the contents of f[rs2] CONCAT f[rs2+1] CONCAT f[rs2+2] from the contents of f[rs1] CONCAT f[rs1+1] CONCAT f[rs1+2] following the ANSI/IEEE 754-1985 standard. The result is evaluated, the FSR's fcc bits are set accordingly, and then the result is discarded. The codes are set as follows: fcc 0 1 2 3 Relation fs1 = fs2 fs1 < fs2 fs1 > fs2 fs1 ? fs2 (unordered)
In this table, fs1 stands for the contents of f[rs1], f[rs1+1], f[rs1+2] and fs2 represents the con tents of f[rs2], f[rs2+1], f[rs2+2]. Compare instructions are used to set up the floating point condition codes for a subsequent FBfcc instruction. However, to prevent misapplication of the condition codes, at least one non floating point instruction must be executed between an FCMP and a subsequent FBfcc instruc tion. FCMPEx causes an invalid exception (nv) if either operand is a signaling or quiet NaN. Traps: fp_disabled fp_exception (nv)
Format:
31 30 29 25 24 19 18 14 13 54 0
10
ignored
110101
rs1
001010111
rs2
MATRA MHS Rev. A (10/09/96)
31
SPARC V7.0
FCMPs
Operation: Assembler Syntax: Description: fcc
Compare Single (FPU Instruction Only)
f[rs1]s COMPARE f[rs2]s
FCMPs
fcmps fregrs1 , fregrs2 FCMPs subtracts the contents of f[rs2] from the contents of f[rs1] following the ANSI/IEEE 754-1985 standard. The result is evaluated, the FSR's fcc bits are set accordingly, and then the result is discarded. The codes are set as follows: fcc 0 1 2 3 Relation fs1 = fs2 fs1 < fs2 fs1 > fs2 fs1 ? fs2 (unordered)
In this table, fs1 stands for the contents of f[rs1] and fs2 represents the contents of f[rs2]. Compare instructions are used to set up the floating point condition codes for a subsequent FBfcc instruction. However, to prevent misapplication of the condition codes, at least one non floating point instruction must be executed between an FCMP and a subsequent FBfcc instruc tion. FCMPs causes an invalid exception (nv) if either operand is a signaling NaN. Traps: fp_disabled fp_exception (nv)
Format:
31 30 29 25 24 19 18 14 13 54 0
10
ignored
110101
rs1
001010001
rs2
32
MATRA MHS Rev. A (10/09/96)
SPARC V7.0
FCMPx
Operation: Assembler Syntax: Description: fcc
Compare Extended (FPU Instruction Only)
f[rs1]x COMPARE f[rs2]x
FCMPx
fcmpx fregrs1 , fregrs2 FCMPx subtracts the contents of f[rs2] CONCAT f[rs2+1] CONCAT f[rs2+2] from the contents of f[rs1] CONCAT f[rs1+1] CONCAT f[rs1+2] following the ANSI/IEEE 754-1985 standard. The result is evaluated, the FSR's fcc bits are set accordingly, and then the result is discarded. The codes are set as follows: fcc 0 1 2 3 fs1 = fs2 fs1 < fs2 fs1 > fs2 fs1 ? fs2 (unordered) Relation
In this table, fs1 stands for the contents of f[rs1], f[rs1+1], f[rs1+2] and fs2 represents the con tents of f[rs2], f[rs2+1], f[rs2+2]. Compare instructions are used to set up the floating point condition codes for a subsequent FBfcc instruction. However, to prevent misapplication of the condition codes, at least one non-floating point instruction must be executed between an FCMP and a subsequent FBfcc instruction. FCMPx causes an invalid exception (nv) if either operand is a signaling NaN. Traps: fp_disabled fp_exception (nv)
Format:
31 30 29 25 24 19 18 14 13 54 0
10
ignored
110101
rs1
001010011
rs2
MATRA MHS Rev. A (10/09/96)
33
SPARC V7.0
FDIVd
Operation: Assembler Syntax: Description: f[rd]d f[rs1]d / f[rs2]d
Divide Double (FPU Instruction Only)
FDIVd
fdivd fregrs1 , fregrs2 , fregrd The FDIVd instruction divides the contents of f[rs1] CONCAT f[rs1+1] by the contents of f[rs2] CONCAT f[rs2+1] as specified by the ANSI/IEEE 754-1985 standard and places the results in f[rd] and f[rd+1]. fp_disabled fp_exception (of, uf, dz, nv, nx)
Traps:
Format:
31 30 29 25 24 19 18 14 13 54 0
10
rd
110100
rs1
001001110
rs2
34
MATRA MHS Rev. A (10/09/96)
SPARC V7.0
FDIVs
Operation: Assembler Syntax: Description: f[rd]s f[rs1]s / f[rs2]s
Divide Single (FPU Instruction Only)
FDIVs
fdivs fregrs1 , fregrs2 , fregrd The FDIVs instruction divides the contents of f[rs1] by the contents of f[rs2] as specified by the ANSI/IEEE 754-1985 standard and places the results in f[rd]. fp_disabled fp_exception (of, uf, dz, nv, nx)
Traps:
Format:
31 30 29 25 24 19 18 14 13 54 0
10
rd
110100
rs1
001001101
rs2
MATRA MHS Rev. A (10/09/96)
35
SPARC V7.0
FDIVx
Operation: Assembler Syntax: Description: f[rd]x f[rs1]x / f[rs2]x
Divide Extended (FPU Instruction Only)
FDIVx
fdivx fregrs1 , fregrs2 , fregrd The FDIVx instruction divides the contents of f[rs1] CONCAT f[rs1+1] CONCAT f[rs1+2] by the contents of f[rs2] CONCAT f[rs2+1] CONCAT f[rs2+2] as specified by the ANSI/IEEE 754-1985 standard and places the results in f[rd], f[rd+1], and f[rd+2]. fp_disabled fp_exception (of, uf, dz, nv, nx)
Traps:
Format:
31 30 29 25 24 19 18 14 13 54 0
10
rd
110100
rs1
001001111
rs2
36
MATRA MHS Rev. A (10/09/96)
SPARC V7.0
FdTOi
Operation: Assembler Syntax: Description: f[rd]i f[rs2]d
Convert Double to Integer (FPU Instruction Only)
FdTOi
fdtoi fregrs2 , fregrd FdTOi converts the floating-point double contents of f[rs2] CONCAT f[rs2+1] to a 32-bit, signed integer by rounding toward zero as specified by the ANSI/IEEE 754-1985 standard. The result is placed in f[rd]. The rounding direction field (RD) of the FSR is ignored. fp_disabled fp_exception (nv, nx)
Traps:
Format:
31 30 29 25 24 19 18 14 13 54 0
10
rd
110100
ignored
011010010
rs2
MATRA MHS Rev. A (10/09/96)
37
SPARC V7.0
FdTOs
Operation: Assembler Syntax: Description: f[rd]s f[rs2]d
Convert Double to Single (FPU Instruction Only)
FdTOs
fdtos fregrs2 , fregrd FdTOs converts the floating-point double contents of f[rs2] CONCAT f[rs2+1] to a single-precision, floating-point format as specified by the ANSI/IEEE 754-1985 standard. The result is placed in f[rd]. Rounding is performed according to the rounding direction field (RD) of the FSR. fp_disabled fp_exception (of, uf, nv, nx)
Traps:
Format:
31 30 29 25 24 19 18 14 13 54 0
10
rd
110100
ignored
011000110
rs2
38
MATRA MHS Rev. A (10/09/96)
SPARC V7.0
FdTOx
Operation: Assembler Syntax: Description: f[rd]x f[rs2]d
Convert Double to Extended (FPU Instruction Only)
FdTOx
fdtox fregrs2 , fregrd FdTOx converts the floating-point double contents of f[rs2] CONCAT f[rs2+1] to an extended-precision, floating-point format as specified by the ANSI/IEEE 754-1985 standard. The result is placed in f[rd], f[rd+1], and f[rd+2]. Rounding is performed according to the rounding direction (RD) and rounding precision (RP) fields of the FSR. fp_disabled fp_exception (nv)
Traps:
Format:
31 30 29 25 24 19 18 14 13 54 0
10
rd
110100
ignored
011001110
rs2
MATRA MHS Rev. A (10/09/96)
39
SPARC V7.0
FiTOd
Operation: Assembler Syntax: Description: f[rd]d f[rs2]i
Convert Integer to Double (FPU Instruction Only)
FiTOd
fitod fregrs2 , fregrd FiTOd converts the 32-bit, signed integer contents of f[rs2] to a floating-point, double-precision format as specified by the ANSI/IEEE 754-1985 standard. The result is placed in f[rd] and f[rd+1]. fp_disabled fp_exception*
Traps:
Format:
31 30 29 25 24 19 18 14 13 54 0
10
rd
110100
ignored
011001000
rs2
* NOTE: An attempt to execute any FP instruction will cause a pending FP exception to be recognized by the integer unit.
40
MATRA MHS Rev. A (10/09/96)
SPARC V7.0
FiTOs
Operation: Assembler Syntax: Description: f[rd]s f[rs2]i
Convert Integer to Single (FPU Instruction Only)
FiTOs
fitos fregrs2 , fregrd FiTOs converts the 32-bit, signed integer contents of f[rs2] to a floating-point, single-precision format as specified by the ANSI/IEEE 754-1985 standard. The result is placed in f[rd]. Rounding is performed according to the rounding direction field, RD. fp_disabled fp_exception (nx)
Traps:
Format:
31 30 29 25 24 19 18 14 13 54 0
10
rd
110100
ignored
011000100
rs2
MATRA MHS Rev. A (10/09/96)
41
SPARC V7.0
FiTOx
Operation: Assembler Syntax: Description: f[rd]x f[rs2]i
Convert Integer to Extended (FPU Instruction Only)
FiTOx
fitox fregrs2 , fregrd FiTOx converts the 32-bit, signed integer contents of f[rs2] to an extended-precision, floating-point format as specified by the ANSI/IEEE 754-1985 standard. The result is placed in f[rd], f[rd+1], and f[rd+2]. fp_disabled fp_exception*
Traps:
Format:
31 30 29 25 24 19 18 14 13 54 0
10
rd
110100
ignored
011001100
rs2
* NOTE: An attempt to execute any FP instruction will cause a pending FP exception to be recognized by the integer unit.
42
MATRA MHS Rev. A (10/09/96)
SPARC V7.0
FMOVs
Operation: Assembler Syntax: Description: f[rd]s f[rs2]s
Move (FPU Instruction Only)
FMOVs
fmovs fregrs2 , fregrd The FMOVs instruction moves the word content of register f[rs2] to the register f[rd]. Multiple FMOVs's are required to transfer multiple-precision numbers between f registers. fp_disabled fp_exception*
Traps:
Format:
31 30 29 25 24 19 18 14 13 54 0
10
rd
110100
ignored
000000001
rs2
* NOTE: An attempt to execute any FP instruction will cause a pending FP exception to be recognized by the integer unit.
MATRA MHS Rev. A (10/09/96)
43
SPARC V7.0
FMULd
Operation: Assembler Syntax: Description: f[rd]d f[rs1]d x f[rs2]d
Multiply Double (FPU Instruction Only)
FMULd
fmuld fregrs1 , fregrs2 , fregrd The FMULd instruction multiplies the contents of f[rs1] CONCAT f[rs1+1] by the contents of f[rs2] CONCAT f[rs2+1] as specified by the ANSI/IEEE 754-1985 standard and places the results in f[rd] and f[rd+1]. fp_disabled fp_exception (of, uf, nv, nx)
Traps:
Format:
31 30 29 25 24 19 18 14 13 54 0
10
rd
110100
rs1
001001010
rs2
44
MATRA MHS Rev. A (10/09/96)
SPARC V7.0
FMULs
Operation: Assembler Syntax: Description: f[rd]s f[rs1]s x ([rs2]s
Multiply Single (FPU Instruction Only)
FMULs
fmuls fregrs1 , fregrs2 , fregrd The FMULs instruction multiplies the contents of f[rs1] by the contents of f[rs2] as specified by the ANSI/IEEE 754-1985 standard and places the results in f[rd]. fp_disabled fp_exception (of, uf, nv, nx)
Traps:
Format:
31 30 29 25 24 19 18 14 13 54 0
10
rd
110100
rs1
001001001
rs2
MATRA MHS Rev. A (10/09/96)
45
SPARC V7.0
FMULx
Operation: Assembler Syntax: Description: f[rd]x f[rs1]x x f[rs2]x
Multiply Extended (FPU Instruction Only)
FMULx
fmulx fregrs1 , fregrs2 , fregrd The FMULx instruction multiplies the contents of f[rs1] CONCAT f[rs1+1] CONCAT f[rs1+2] by the contents of f[rs2] CONCAT f[rs2+1] CONCAT f[rs2+2] as specified by the ANSI/IEEE 754-1985 standard and places the results in f[rd], f[rd+1], and f[rd+2]. fp_disabled fp_exception (of, uf, nv, nx)
Traps:
Format:
31 30 29 25 24 19 18 14 13 54 0
10
rd
110100
rs1
001001011
rs2
46
MATRA MHS Rev. A (10/09/96)
SPARC V7.0
FNEGs
Operation: Assembler Syntax: Description: f[rd]s f[rs2]s XOR 80000000 H
Negate (FPU Instruction Only)
FNEGs
fnegs fregrs2 , fregrd The FNEGs instruction complements the sign bit of the word in f[rs2] and places the result in f[rd]. It does not round. Since this FPop can address both even and odd f registers, FNEGs can also operate on the high order words of double and extended operands, which accomplishes sign bit negation for these data types.
Traps:
fp_disabled fp_exception*
Format:
31 30 29 25 24 19 18 14 13 54 0
10
rd
110100
ignored
000000101
rs2
* NOTE: An attempt to execute any FP instruction will cause a pending FP exception to be recognized by the integer unit.
MATRA MHS Rev. A (10/09/96)
47
SPARC V7.0
FSQRTd
Operation: Assembler Syntax: Description: f[rd]d SQRT f[rs2]d
Square Root Double (FPU Instruction Only)
FSQRTd
fsqrtd fregrs2 , fregrd FSQRTd generates the square root of the floating-point double contents of f[rs2] CONCAT f[rs2+1] as specified by the ANSI/IEEE 754-1985 standard. The result is placed in f[rd] and f[rd+1]. Rounding is performed according to the rounding direction field (RD) of the FSR. fp_disabled fp_exception (nv, nx)
Traps:
Format:
31 30 29 25 24 19 18 14 13 54 0
10
rd
110100
ignored
000101010
rs2
48
MATRA MHS Rev. A (10/09/96)
SPARC V7.0
FSQRTs
Operation: Assembler Syntax: Description: f[rd]s SQRT f[rs2]s
Square Root Single (FPU Instruction Only)
FSQRTs
fsqrts fregrs2 , fregrd FSQRTs generates the square root of the floating-point single contents of f[rs2] as specified by the ANSI/IEEE 754-1985 standard. The result is placed in f[rd]. Rounding is performed according to the rounding direction field (RD) of the FSR. fp_disabled fp_exception (nv, nx)
Traps:
Format:
31 30 29 25 24 19 18 14 13 54 0
10
rd
110100
ignored
000101001
rs2
MATRA MHS Rev. A (10/09/96)
49
SPARC V7.0
FSQRTx
Operation: Assembler Syntax: Description: f[rd]x SQRT f[rs2]x
Square Root Extended (FPU Instruction Only)
FSQRTx
fsqrtx fregrs2 , fregrd FSQRTx generates the square root of the floating-point extended contents of f[rs2] CONCAT f[rs2+1] CONCAT f[rs2+2] as specified by the ANSI/IEEE 754-1985 standard. The result is placed in f[rd], f[rd+1], and f[rd+2]. Rounding is performed according to the rounding direction (RD) and rounding precision (RP) fields of the FSR. fp_disabled fp_exception (nv, nx)
Traps:
Format:
31 30 29 25 24 19 18 14 13 54 0
10
rd
110100
ignored
000101011
rs2
50
MATRA MHS Rev. A (10/09/96)
SPARC V7.0
FsTOd
Operation: Assembler Syntax: Description: f[rd]d f[rs2]s
Convert Single to Double (FPU Instruction Only)
FsTOd
fstod fregrs2 , fregrd FsTOd converts the floating-point single contents of f[rs2] to a double-precision, floating-point format as specified by the ANSI/IEEE 754-1985 standard. The result is placed in f[rd] and f[rd+1]. Rounding is performed according to the rounding direction field (RD) of the FSR. fp_disabled fp_exception (nv)
Traps:
Format:
31 30 29 25 24 19 18 14 13 54 0
10
rd
110100
ignored
011001001
rs2
MATRA MHS Rev. A (10/09/96)
51
SPARC V7.0
FsTOi
Operation: Assembler Syntax: Description: f[rd]i f[rs2]s
Convert Single to Integer (FPU Instruction Only)
FsTOi
fstoi fregrs2 , fregrd FsTOi converts the floating-point single contents of f[rs2] to a 32-bit, signed integer by rounding toward zero as specified by the ANSI/IEEE 754-1985 standard. The result is placed in f[rd]. The rounding field (RD) of the FSR is ignored. fp_disabled fp_exception (nv, nx)
Traps:
Format:
31 30 29 25 24 19 18 14 13 54 0
10
rd
110100
ignored
011010001
rs2
52
MATRA MHS Rev. A (10/09/96)
SPARC V7.0
FsTOx
Operation: Assembler Syntax: Description: f[rd]x f[rs2]s
Convert Single to Extended (FPU Instruction Only)
FsTOx
fstox fregrs2 , fregrd FsTOx converts the floating-point single contents of f[rs2] to an extended-precision, floating-point format as specified by the ANSI/IEEE 754-1985 standard. The result is placed in f[rd], f[rd+1], and f[rd+2]. Rounding is performed according to the rounding direction (RD) and rounding precision (RP) fields of the FSR. fp_disabled fp_exception (nv)
Traps:
Format:
31 30 29 25 24 19 18 14 13 54 0
10
rd
110100
ignored
011001101
rs2
MATRA MHS Rev. A (10/09/96)
53
SPARC V7.0
FSUBd
Operation: Assembler Syntax: Description: f[rd]d f[rs1]d - f[rs2]d
Subtract Double (FPU Instruction Only)
FSUBd
fsubd fregrs1 , fregrs2 , fregrd The FSUBd instruction subtracts the contents of f[rs2] CONCAT f[rs2+1] from the contents of f[rs1] CONCAT f[rs1+1] as specified by the ANSI/IEEE 754-1985 standard and places the results in f[rd] and f[rd+1]. fp_disabled fp_exception (of, uf, nx, nv)
Traps:
Format:
31 30 29 25 24 19 18 14 13 54 0
10
rd
110100
rs1
001000110
rs2
54
MATRA MHS Rev. A (10/09/96)
SPARC V7.0
FSUBs
Operation: Assembler Syntax: Description: f[rd]s f[rs1]s - f[rs2]s
Subtract Single (FPU Instruction Only)
FSUBs
fsubs fregrs1 , fregrs2 , fregrd The FSUBs instruction subtracts the contents of f[rs2] from the contents of f[rs1] as specified by the ANSI/IEEE 754-1985 standard and places the results in f[rd]. fp_disabled fp_exception (of, uf, nx, nv)
Traps:
Format:
31 30 29 25 24 19 18 14 13 54 0
10
rd
110100
rs1
001000101
rs2
MATRA MHS Rev. A (10/09/96)
55
SPARC V7.0
FSUBx
Operation: Assembler Syntax: Description: f[rd]x f[rs1]x - f[rs2]x
Subtract Extended (FPU Instruction Only)
FSUBx
fsubx fregrs1 , fregrs2 , fregrd The FSUBx instruction subtracts the contents of f[rs2] CONCAT f[rs2+1] CONCAT f[rs2+2] from the contents of f[rs1] CONCAT f[rs1+1] CONCAT f[rs1+2] as specified by the ANSI/IEEE 754-1985 standard and places the results in f[rd], f[rd+1], and f[rd+2]. fp_disabled fp_exception (of, uf, nv, nx)
Traps:
Format:
31 30 29 25 24 19 18 14 13 54 0
10
rd
110100
rs1
001000111
rs2
56
MATRA MHS Rev. A (10/09/96)
SPARC V7.0
FxTOd
Operation: Assembler Syntax: Description: f[rd]d f[rs2]x
Convert Extended to Double (FPU Instruction Only)
FxTOd
fxtod fregrs2 , fregrd FxTOd converts the floating-point extended contents of f[rs2] CONCAT f[rs2+1] CONCAT f[rs2+2] to a double-precision, floating-point format as specified by the ANSI/IEEE 754-1985 standard. The result is placed in f[rd] and f[rd+1]. Rounding is performed according to the rounding direction (RD) field of the FSR. fp_disabled fp_exception (of, uf, nv, nx)
Traps:
Format:
31 30 29 25 24 19 18 14 13 54 0
10
rd
110100
ignored
011001011
rs2
MATRA MHS Rev. A (10/09/96)
57
SPARC V7.0
FxTOi
Operation: Assembler Syntax: Description: f[rd]i f[rs2]x
Convert Extended to Integer (FPU Instruction Only)
FxTOi
fxtoi fregrs2 , fregrd FxTOi converts the floating-point extended contents of f[rs2] CONCAT f[rs2+1] CONCAT f[rs2+2] to a 32-bit, signed integer by rounding toward zero as specified by the ANSI/IEEE 754-1985 standard. The result is placed in f[rd]. The rounding field (RD) of the FSR is ignored. fp_disabled fp_exception (nv, nx)
Traps:
Format:
31 30 29 25 24 19 18 14 13 54 0
10
rd
110100
ignored
011010011
rs2
58
MATRA MHS Rev. A (10/09/96)
SPARC V7.0
FxTOs
Operation: Assembler Syntax: Description: f[rd]s f[rs2]x
Convert Extended to Single (FPU Instruction Only)
FxTOs
fxtos fregrs2 , fregrd FxTOs converts the floating-point extended contents of f[rs2] CONCAT f[rs2+1] CONCAT f[rs2+2] to a single-precision, floating-point format as specified by the ANSI/IEEE 754-1985 standard. The result is placed in f[rd]. Rounding is performed according to the rounding direction (RD) field of the FSR. fp_disabled fp_exception (of, uf, nv, nx)
Traps:
Format:
31 30 29 25 24 19 18 14 13 54 0
10
rd
110100
ignored
011000111
rs2
MATRA MHS Rev. A (10/09/96)
59
SPARC V7.0
IFLUSH
Operation: Assembler Syntax: Description: FLUSH iflush address
Instruction Cache Flush
[r[rs1] + (r[rs2] or sign extnd(simm13))]
IFLUSH
The IFLUSH instruction causes a word to be flushed from an instruction cache which may be internal to the processor. The word to be flushed is at the address specified by the contents of r[rs1] plus either the contents of r[rs2] if the instruction's i bit equals zero, or the 13-bit, sign-extended immediate operand contained in the instruction if i equals one. Since there is no internal instruction cache in the current CY7C600 family, the result of execut ing an IFLUSH instruction is dependent on the state of the input signal, Instruction Cache Flush Trap (IFT). If IFT = 1, IFLUSH executes as a NOP, with no side effects. If IFT = 0, execution of IFLUSH causes an illegal_instruction trap.
Traps: Format:
illegal_instruction
31 30 29
25 24
19 18
14
13
12
54
0
10
ignored
111011
25 24 19 18
rs1
14
i=0
13 12
ignored
rs2
0
31 30 29
10
ignored
111011
rs1
i=1
simm13
60
MATRA MHS Rev. A (10/09/96)
SPARC V7.0
JMPL
Operation: r[rd] PC nPC Assembler Syntax: Description: PC nPC
Jump and Link
JMPL
r[rs1] + (r[rs2] or sign extnd(simm13))
jmpl address, regrd JMPL first provides linkage by saving its return address into the register specified in the rd field. It then causes a register-indirect, delayed control transfer to an address specified by the sum of the contents of r[rs1] and either the contents of r[rs2] if the instruction's i bit equals zero, or the 13-bit, signextended immediate operand contained in the instruction if i equals one. If either of the low order two bits of the jump address is nonzero, a memory_ad dress_not_aligned trap is generated. Programming note: A register indirect CALL can be constructed using a JMPL instruction with rd set to 15. JMPL can also be used to return from a CALL. In this case, rd is set to 0 and the return (jump) address would be equal to r[31] + 8.
Traps: Format:
memory_address_not_aligned
31 30 29
25 24
19 18
14
13
12
54
0
10
31 30 29
rd
111000
25 24 19 18
rs1
14
i=0
13 12
ignored
rs2
0
10
rd
111000
rs1
i=1
simm13
MATRA MHS Rev. A (10/09/96)
61
SPARC V7.0
LD
Operation: Assembler Syntax: Description: r[rd] ld [address], regrd
Load Word
[r[rs1] + (r[rs2] or sign extnd(simm13))]
LD
The LD instruction moves a word from memory into the destination register, r[rd]. The effective memory address is derived by summing the contents of r[rs1] and either the contents of r[rs2] if the instruction's i bit equals zero, or the 13-bit, sign-extended immediate operand contained in the instruction if i equals one. If LD takes a trap, the contents of the destination register remain unchanged. If the instruction following an integer load uses the load's r[rd] register as a source operand, hardware interlocks add one or more delay cycles to the following instruction depending upon the memory subsystem. Programming note: If rs1 is set to 0 and i is set to 1, any location in the lowest or highest 4 kbytes of an address space can be accessed without setting up a register.
Traps:
memory_address_not_aligned data_access_exception
Format:
31 30 29 25 24 19 18 14 13 12 54 0
11
31 30 29
rd
000000
25 24 19 18
rs1
14
i=0
13 12
ignored
rs2
0
11
rd
000000
rs1
i=1
simm13
62
MATRA MHS Rev. A (10/09/96)
SPARC V7.0
LDA
Operation: address space r[rd] Assembler Syntax: Description: asi
Load Word from Alternate space (Privileged Instruction)
LDA
[r[rs1] + r[rs2]]
lda [regaddr] asi, regrd The LDA instruction moves a word from memory into the destination register, r[rd]. The effective memory address is a combination of the address space value given in the asi field and the address derived by summing the contents of r[rs1] and r[rs2]. If LDA takes a trap, the contents of the destination register remain unchanged. If the instruction following an integer load uses the load's r[rd] register as a source operand, hardware interlocks add one or more delay cycles to the following instruction depending upon the memory subsystem.
Traps:
illegal_instruction (if i=1) privileged_instruction (if S=0) memory_address_not_aligned data_access_exception
Format:
31 30 29 25 24 19 18 14 13 12 54 0
11
rd
010000
rs1
i=0
asi
rs2
MATRA MHS Rev. A (10/09/96)
63
SPARC V7.0
LDC
Operation: Assembler Syntax: Description: c[rd] ld [address], cregrd
Load Coprocessor register
[r[rs1] + (r[rs2] or sign extnd(simm13))]
LDC
The LDC instruction moves a word from memory into a coprocessor register, c[rd]. The effective memory address is derived by summing the contents of r[rs1] and either the contents of r[rs2] if the instruction's i bit equals zero, or the 13-bit, sign-extended immediate operand contained in the instruction if i equals one. If the PSR's EC bit is set to zero or if no coprocessor is present, a cp_disabled trap will be gener ated. If LDC takes a trap, the state of the coprocessor depends on the particular implementa tion. If the instruction following a coprocessor load uses the load's c[rd] register as a source operand, hardware interlocks add one or more delay cycles to the following instruction depending upon the memory subsystem. Programming note: If rs1 is set to 0 and i is set to 1, any location in the lowest or highest 4 kbytes of an address space can be accessed without setting up a register.
Traps:
cp_disabled cp_exception memory_address_not_aligned data_access_exception
Format:
31 30 29 25 24 19 18 14 13 12 54 0
11
31 30 29
rd
110000
25 24 19 18
rs1
14
i=0
13 12
ignored
rs2
0
11
rd
110000
rs1
i=1
simm13
64
MATRA MHS Rev. A (10/09/96)
SPARC V7.0
LDCSR
Operation: Assembler Syntax: Description: CSR ld [address], %csr
Load Coprocessor State Register
[r[rs1] + (r[rs2] or sign extnd(simm13))]
LDCSR
The LDCSR instruction moves a word from memory into the Coprocessor State Register. The effective memory address is derived by summing the contents of r[rs1] and either the contents of r[rs2] if the instruction's i bit equals zero, or the 13-bit, sign-extended immediate operand contained in the instruction if i equals one. If the PSR's EC bit is set to zero or if no coprocessor is present, a cp_disabled trap will be gener ated. If LDCSR takes a trap, the state of the coprocessor depends on the particular imple mentation. If the instruction following a LDCSR uses the CSR as a source operand, hardware interlocks add one or more delay cycles to the following instruction depending upon implementation of the coprocessor. Programming note: If rs1 is set to 0 and i is set to 1, any location in the lowest or highest 4 kbytes of an address space can be accessed without setting up a register.
Traps:
cp_disabled cp_exception memory_address_not_aligned data_access_exception
Format:
31 30 29 25 24 19 18 14 13 12 54 0
11
31 30 29
rd
110001
25 24 19 18
rs1
14
i=0
13 12
ignored
rs2
0
11
rd
110001
rs1
i=1
simm13
MATRA MHS Rev. A (10/09/96)
65
SPARC V7.0
LDD
Operation: r[rd] r[rd + 1] Assembler Syntax: Description:
Load Doubleword
[r[rs1] + (r[rs2] or sign extnd(simm13))] [(r[rs1] + (r[rs2] or sign extnd(simm13))) + 4]
LDD
ldd [address], regrd The LDD instruction moves a doubleword from memory into a destination register pair, r[rd] and r[rd+1]. The effective memory address is derived by summing the contents of r[rs1] and either the contents of r[rs2] if the instruction's i bit equals zero, or the 13-bit, sign-extended immediate operand contained in the instruction if i equals one. The most significant memory word is always moved into the even-numbered destination register and the least significant memory word is always moved into the next odd-numbered register (see discussion in Section NO TAG). If a data_access_exception trap takes place during the effective address memory access, the destination registers remain unchanged. If the instruction following an integer load uses the load's r[rd] register as a source operand, hardware interlocks add one or more delay cycles to the following instruction depending upon the memory subsystem. For an LDD, this applies to both destination registers. Programming note: If rs1 is set to 0 and i is set to 1, any location in the lowest or highest 4 kbytes of an address space can be accessed without setting up a register.
Traps:
memory_address_not_aligned data_access_exception
Format:
31 30 29 25 24 19 18 14 13 12 54 0
11
31 30 29
rd
000011
25 24 19 18
rs1
14
i=0
13 12
ignored
rs2
0
11
rd
000011
rs1
i=1
simm13
66
MATRA MHS Rev. A (10/09/96)
SPARC V7.0
LDDA
Operation: address space r[rd] r[rd +1] Assembler Syntax: Description:
Load Doubleword from Alternate space (Privileged Instruction)
asi
LDDA
[r[rs1] + r[rs2]] [r[rs1] + r[rs2] + 4]
ldda [regaddr] asi, regrd The LDDA instruction moves a doubleword from memory into the destination registers, r[rd] and r[rd+1]. The effective memory address is a combination of the address space value given in the asi field and the address derived by summing the contents of r[rs1] and r[rs2]. The most significant memory word is always moved into the even-numbered destination register and the least significant memory word is always moved into the next odd-numbered register (see discussion in Section NO TAG). If a trap takes place during the effective address memory access, the destination registers re main unchanged. If the instruction following an integer load uses the load's r[rd] register as a source operand, hardware interlocks add one or more delay cycles to the following instruction depending upon the memory subsystem. For an LDDA, this applies to both destination registers.
Traps:
illegal_instruction (if i=1) privileged_instruction (if S=0) memory_address_not_aligned data_access_exception
Format:
31 30 29 25 24 19 18 14 13 12 54 0
11
rd
010011
rs1
i=0
asi
rs2
MATRA MHS Rev. A (10/09/96)
67
SPARC V7.0
LDDC
Operation: c[rd ] c[rd + 1] Assembler Syntax: Description:
Load Doubleword Coprocessor
[r[rs1] + (r[rs2] or sign extnd(simm13))] [(r[rs1] + (r[rs2] or sign extnd(simm13))) + 4]
LDDC
ldd [address], cregrd The LDDC instruction moves a doubleword from memory into the coprocessor registers, c[rd] and c[rd+1]. The effective memory address is derived by summing the contents of r[rs1] and either the contents of r[rs2] if the instruction's i bit equals zero, or the 13-bit, sign-extended immediate operand contained in the instruction if i equals one. The most significant memory word is always moved into the even-numbered destination register and the least significant memory word is always moved into the next odd-numbered register (see discussion in Section NO TAG). If the PSR's EC bit is set to zero or if no coprocessor is present, a cp_disabled trap will be gener ated. If LDDC takes a trap, the state of the coprocessor depends on the particular implementa tion. If the instruction following a coprocessor load uses the load's c[rd] register as a source operand, hardware interlocks add one or more delay cycles to the following instruction depending upon the memory subsystem and coprocessor implementation. For an LDDC, this applies to both destination registers. Programming note: If rs1 is set to 0 and i is set to 1, any location in the lowest or highest 4 kbytes of an address space can be accessed without setting up a register.
Traps:
cp_disabled cp_exception memory_address_not_aligned data_access_exception
Format:
31 30 29 25 24 19 18 14 13 12 54 0
11
31 30 29
rd
110011
25 24 19 18
rs1
14
i=0
13 12
ignored
rs2
0
11
rd
110011
rs1
i=1
simm13
68
MATRA MHS Rev. A (10/09/96)
SPARC V7.0
LDDF
Operation: f[rd] f[rd + 1] Assembler Syntax: Description:
Load Doubleword Floating-Point
[r[rs1] + (r[rs2] or sign extnd(simm13))] [(r[rs1] + (r[rs2] or sign extnd(simm13))) + 4]
LDDF
ldd [address], fregrd The LDDF instruction moves a doubleword from memory into the floating-point registers, f[rd] and f[rd+1]. The effective memory address is derived by summing the contents of r[rs1] and either the contents of r[rs2] if the instruction's i bit equals zero, or the 13-bit, sign-extended immediate operand contained in the instruction if i equals one. The most significant memory word is always moved into the even-numbered destination register and the least significant memory word is always moved into the next odd-numbered register (see discussion in Section NO TAG). If the PSR's EF bit is set to zero or if no floating point unit is present, an fp_disabled trap will be generated. If a trap takes place during the effective address memory access, the destination registers remain unchanged. If the instruction following a floating point load uses the load's f[rd] register as a source oper and, hardware interlocks add one or more delay cycles to the following instruction depending upon the memory subsystem. For an LDDF, this applies to both destination registers. Programming note: If rs1 is set to 0 and i is set to 1, any location in the lowest or highest 4 kbytes of an address space can be accessed without setting up a register.
Traps:
fp_disabled fp_exception* memory_address_not_aligned data_access_exception
Format:
31 30 29 25 24 19 18 14 13 12 54 0
11
31 30 29
rd
100011
25 24 19 18
rs1
14
i=0
13 12
ignored
rs2
0
11
rd
100011
rs1
i=1
simm13
* NOTE: An attempt to execute any FP instruction will cause a pending FP exception to be recognized by the integer unit.
MATRA MHS Rev. A (10/09/96)
69
SPARC V7.0
LDF
Operation: Assembler Syntax: Description: f[rd] ld [address], freg rd
Load Floating-Point register
[r[rs1] + (r[rs2] or sign extnd(simm13))]
LDF
The LDF instruction moves a word from memory into a floating-point register, f[rd]. The effective memory address is derived by summing the contents of r[rs1] and either the contents of r[rs2] if the instruction's i bit equals zero, or the 13-bit, sign-extended immediate operand contained in the instruction if i equals one. If the PSR's EF bit is set to zero or if no Floating Point Unit is present, an fp_disabled trap will be generated. If LDF takes a trap, the contents of the destination register remain unchanged. If the instruction following a floating point load uses the load's f[rd] register as a source oper and, hardware interlocks add one or more delay cycles to the following instruction depending upon the memory subsystem. Programming note: If rs1 is set to 0 and i is set to 1, any location in the lowest or highest 4 kbytes of an address space can be accessed without setting up a register.
Traps:
fp_disabled fp_exception* memory_address_not_aligned data_access_exception
Format:
31 30 29 25 24 19 18 14 13 12 54 0
11
31 30 29
rd
100000
25 24 19 18
rs1
14
i=0
13 12
ignored
rs2
0
11
rd
100000
rs1
i=1
simm13
* NOTE: An attempt to execute any FP instruction will cause a pending FP exception to be recognized by the integer unit.
70
MATRA MHS Rev. A (10/09/96)
SPARC V7.0
LDFSR
Operation: Assembler Syntax: Description: FSR ld [address], %fsr
Load Floating-Point State Register
[r[rs1] + (r[rs2] or sign extnd(simm13))]
LDFSR
The LDFSR instruction moves a word from memory into the floating-point state register. The effective memory address is derived by summing the contents of r[rs1] and either the contents of r[rs2] if the instruction's i bit equals zero, or the 13-bit, sign-extended immediate operand contained in the instruction if i equals one. This instruction will wait for all pending FPops to complete execution before it loads the memory word into the FSR. If the PSR's EF bit is set to zero or if no floating point unit is present, an fp_disabled trap will be generated. If LDFSR takes a trap, the contents of the FSR remain unchanged. If the instruction following a LDFSR uses the FSR as a source operand, hardware interlocks add one or more cycle delay to the following instruction depending upon the memory subsys tem. Programming note: If rs1 is set to 0 and i is set to 1, any location in the lowest or highest 4 kbytes of an address space can be accessed without setting up a register.
Traps:
fp_disabled fp_exception* memory_address_not_aligned data_access_exception
Format:
31 30 29 25 24 19 18 14 13 12 54 0
11
31 30 29
rd
100001
25 24 19 18
rs1
14
i=0
13 12
ignored
rs2
0
11
rd
100001
rs1
i=1
simm13
* NOTE: An attempt to execute any FP instruction will cause a pending FP exception to be recognized by the integer unit.
MATRA MHS Rev. A (10/09/96)
71
SPARC V7.0
LDSB
Operation: Assembler Syntax: Description: r[rd] ldsb [address], regrd
Load Signed Byte
sign extnd[r[rs1] + (r[rs2] or sign extnd(simm13))]
LDSB
The LDSB instruction moves a signed byte from memory into the destination register, r[rd]. The effective memory address is derived by summing the contents of r[rs1] and either the contents of r[rs2] if the instruction's i bit equals zero, or the 13-bit, sign-extended immediate operand contained in the instruction if i equals one. The fetched byte is right-justified and sign-extended in r[rd]. If LDSB takes a trap, the contents of the destination register remain unchanged. If the instruction following an integer load uses the load's r[rd] register as a source operand, hardware interlocks add one or more delay cycles to the following instruction depending upon the memory subsystem. Programming note: If rs1 is set to 0 and i is set to 1, any location in the lowest or highest 4 kbytes of an address space can be accessed without setting up a register.
Traps: Format:
data_access_exception
31 30 29
25 24
19 18
14
13
12
54
0
11
31 30 29
rd
001001
25 24 19 18
rs1
14
i=0
13 12
ignored
rs2
0
11
rd
001001
rs1
i=1
simm13
72
MATRA MHS Rev. A (10/09/96)
SPARC V7.0
LDSBA
Operation: address space r[rd] Assembler Syntax: Description:
Load Signed Byte from Alternate space (Privileged Instruction)
asi
LDSBA
sign extnd[r[rs1] + r[rs2]]
ldsba [regaddr] asi, regrd The LDSBA instruction moves a signed byte from memory into the destination register, r[rd]. The effective memory address is a combination of the address space value given in the asi field and the address derived by summing the contents of r[rs1] and r[rs2]. The fetched byte is right-justified and sign-extended in r[rd]. If LDSBA takes a trap, the contents of the destination register remain unchanged. If the instruction following an integer load uses the load's r[rd] register as a source operand, hardware interlocks add one or more delay cycles depending upon the memory subsystem.
Traps:
illegal_instruction (if i=1) privileged_instruction (if S=0) data_access_exception
Format:
31 30 29 25 24 19 18 14 13 12 54 0
11
rd
011001
rs1
i=0
asi
rs2
MATRA MHS Rev. A (10/09/96)
73
SPARC V7.0
LDSH
Operation: Assembler Syntax: Description: r[rd] ldsh [address], regrd
Load Signed Halfword
sign extnd[r[rs1] + (r[rs2] or sign extnd(simm13))]
LDSH
The LDSH instruction moves a signed halfword from memory into the destination register, r[rd]. The effective memory address is derived by summing the contents of r[rs1] and either the contents of r[rs2] if the instruction's i bit equals zero, or the 13-bit, sign-extended immediate operand contained in the instruction if i equals one. The fetched halfword is right-justified and sign-extended in r[rd]. If LDSH takes a trap, the contents of the destination register remain unchanged. If the instruction following an integer load uses the load's r[rd] register as a source operand, hardware interlocks add one or more delay cycles depending upon the memory subsystem. Programming note: If rs1 is set to 0 and i is set to 1, any location in the lowest or highest 4 kbytes of an address space can be accessed without setting up a register.
Traps:
memory_address_not_aligned data_access_exception
Format:
31 30 29 25 24 19 18 14 13 12 54 0
11
31 30 29
rd
001010
25 24 19 18
rs1
14
i=0
13 12
ignored
rs2
0
11
rd
001010
rs1
i=1
simm13
74
MATRA MHS Rev. A (10/09/96)
SPARC V7.0
LDSHA
Operation: address space r[rd] Assembler Syntax: Description:
Load Signed Halfword from Alternate space (Privileged Instruction)
asi
LDSHA
sign extnd[r[rs1] + r[rs2]]
ldsha [regaddr ] asi, regrd The LDSHA instruction moves a signed halfword from memory into the destination register, r[rd]. The effective memory address is a combination of the address space value given in the asi field and the address derived by summing the contents of r[rs1] and r[rs2]. The fetched halfword is right-justified and sign-extended in r[rd]. If LDSHA takes a trap, the contents of the destination register remain unchanged. If the instruction following an integer load uses the load's r[rd] register as a source operand, hardware interlocks add one or more delay cycles depending upon the memory subsystem.
Traps:
illegal_instruction (if i=1) privileged_instruction (if S=0) memory_address_not_aligned data_access_exception
Format:
31 30 29 25 24 19 18 14 13 12 54 0
11
rd
011010
rs1
i=0
asi
rs2
MATRA MHS Rev. A (10/09/96)
75
SPARC V7.0
LDSTUB
Operation: r[rd] Assembler Syntax: Description:
Atomic Load/Store Unsigned Byte
zero extnd[r[rs1] + (r[rs2] or sign extnd(simm13))] FFFFFFFF H
LDSTUB
[r[rs1] + (r[rs2] or sign extnd(simm13))]
ldstub [address], regrd The LDSTUB instruction moves an unsigned byte from memory into the destination register, r[rd], and rewrites the same byte in memory to all ones, while preventing asynchronous trap interruptions. In a multiprocessor system, two or more processors executing atomic load/store instructions which address the same byte simultaneously are guaranteed to execute them serially, in some order. The effective memory address is derived by summing the contents of r[rs1] and either the con tents of r[rs2] if the instruction's i bit equals zero, or the 13 bit, sign extended immediate oper and contained in the instruction if i equals one. The fetched byte is right justified and zero extended in r[rd]. If the instruction following an integer load uses the load's r[rd] register as a source operand, hardware interlocks add one or more delay cycles depending upon the memory subsystem. If LDSTUB takes a trap, the contents of the memory address remain unchanged. Programming note: If rs1 is set to 0 and i is set to 1, any location in the lowest or highest 4 kbytes of an address space can be accessed without setting up a register.
Traps: Format:
data_access_exception
31 30 29
25 24
19 18
14
13
12
54
0
11
31 30 29
rd
001101
25 24 19 18
rs1
14
i=0
13 12
ignored
rs2
0
11
rd
001101
rs1
i=1
simm13
76
MATRA MHS Rev. A (10/09/96)
SPARC V7.0
LDSTUBA
Atomic Load/Store Unsigned Byte in Alternate space (Privileged Instruction)
LDSTUBA
Operation:
address space r[rd] [r[rs1] + r[rs2]]
asi FFFFFFFF H
zero extnd[r[rs1] + r[rs2]]
Assembler Syntax: Description:
ldstuba [regaddr ] asi, regrd The LDSTUBA instruction moves an unsigned byte from memory into the destination register, r[rd], and rewrites the same byte in memory to all ones, while preventing asynchronous trap interruptions. In a multiprocessor system, two or more processors executing atomic load/store instructions which address the same byte simultaneously are guaranteed to execute them in some serial order. The effective memory address is a combination of the address space value given in the asi field and the address derived by summing the contents of r[rs1] and r[rs2]. The fetched byte is right justified and zero extended in r[rd]. If the instruction following an integer load uses the load's r[rd] register as a source operand, hardware interlocks add one or more delay cycles depending upon the memory subsystem. If LDSTUBA takes a trap, the contents of the memory address remain unchanged.
Traps:
illegal_instruction (if i=1) privileged_instruction (if S=0) data_access_exception
Format:
31 30 29 25 24 19 18 14 13 12 54 0
11
rd
011101
rs1
i=0
asi
rs2
MATRA MHS Rev. A (10/09/96)
77
SPARC V7.0
LDUB
Operation: Assembler Syntax: Description: r[rd] ldub [address], regrd
Load Unsigned Byte
zero extnd[r[rs1] + (r[rs2] or sign extnd(simm13))]
LDUB
The LDUB instruction moves an unsigned byte from memory into the destination register, r[rd]. The effective memory address is derived by summing the contents of r[rs1] and either the contents of r[rs2] if the instruction's i bit equals zero, or the 13-bit, sign-extended immediate operand contained in the instruction if i equals one. The fetched byte is right-justified and zero-extended in r[rd]. If LDUB takes a trap, the contents of the destination register remain unchanged. If the instruction following an integer load uses the load's r[rd] register as a source operand, hardware interlocks add one or more delay cycles depending upon the memory subsystem. Programming note: If rs1 is set to 0 and i is set to 1, any location in the lowest or highest 4 kbytes of an address space can be accessed without setting up a register.
Traps: Format:
data_access_exception
31 30 29
25 24
19 18
14
13
12
54
0
11
31 30 29
rd
000001
25 24 19 18
rs1
14
i=0
13 12
ignored
rs2
0
11
rd
000001
rs1
i=1
simm13
78
MATRA MHS Rev. A (10/09/96)
SPARC V7.0
LDUBA
Operation: address space r[rd] Assembler Syntax: Description:
Load Unsigned Byte from Alternate space (Privileged Instruction)
asi
LDUBA
zero extnd[r[rs1] + r[rs2]]
lduba [regaddr ] asi, regrd The LDUBA instruction moves an unsigned byte from memory into the destination register, r[rd]. The effective memory address is a combination of the address space value given in the asi field and the address derived by summing the contents of r[rs1] and r[rs2]. The fetched byte is right-justified and zero-extended in r[rd]. If LDUBA takes a trap, the contents of the destination register remain unchanged. If the instruction following an integer load uses the load's r[rd] register as a source operand, hardware interlocks add one or more delay cycles depending upon the memory subsystem.
Traps:
illegal_instruction (if i=1) privileged_instruction (if S=0) data_access_exception
Format:
31 30 29 25 24 19 18 14 13 12 54 0
11
rd
010001
rs1
i=0
asi
rs2
MATRA MHS Rev. A (10/09/96)
79
SPARC V7.0
LDUH
Operation: Assembler Syntax: Description: r[rd] lduh [address], regrd
Load Unsigned Halfword
zero extnd[r[rs1] + (r[rs2] or sign extnd(simm13))]
LDUH
The LDUH instruction moves an unsigned halfword from memory into the destination register, r[rd]. The effective memory address is derived by summing the contents of r[rs1] and either the contents of r[rs2] if the instruction's i bit equals zero, or the 13-bit, sign-extended immediate operand contained in the instruction if i equals one. The fetched halfword is right-justified and zero-extended in r[rd]. If LDUH takes a trap, the contents of the destination register remain unchanged. If the instruction following an integer load uses the load's r[rd] register as a source operand, hardware interlocks add one or more delay cycles depending upon the memory subsystem. Programming note: If rs1 is set to 0 and i is set to 1, any location in the lowest or highest 4 kbytes of an address space can be accessed without setting up a register.
Traps:
memory_address_not_aligned data_access_exception
Format:
31 30 29 25 24 19 18 14 13 12 54 0
11
31 30 29
rd
000010
25 24 19 18
rs1
14
i=0
13 12
ignored
rs2
0
11
rd
000010
rs1
i=1
simm13
80
MATRA MHS Rev. A (10/09/96)
SPARC V7.0
LDUHA
Operation: address space r[rd] Assembler Syntax: Description:
Load Unsigned Halfword from Alternate space (Privileged Instruction)
asi
LDUHA
zero extnd[r[rs1] + r[rs2]]
lduha [regaddr] asi, regrd The LDUHA instruction moves an unsigned halfword from memory into the destination register, r[rd]. The effective memory address is a combination of the address space value given in the asi field and the address derived by summing the contents of r[rs1] and r[rs2]. The fetched halfword is rightjustified and zero-extended in r[rd]. If LDUHA takes a trap, the contents of the destination register remain unchanged. If the instruction following an integer load uses the load's r[rd] register as a source operand, hardware interlocks add one or more delay cycles depending upon the memory subsystem.
Traps:
illegal_instruction (if i=1) privileged_instruction (if S=0) memory_address_not_aligned data_access_exception
Format:
31 30 29 25 24 19 18 14 13 12 54 0
11
rd
010010
rs1
i=0
asi
rs2
MATRA MHS Rev. A (10/09/96)
81
SPARC V7.0
MULScc
Operation:
Multiply Step and modify icc
MULScc
op1 = (n XOR v) CONCAT r[rs1]<31:1> if (Y<0> = 0) op2 = 0, else op2 = r[rs2] or sign extnd(simm13) r[rd] op1 + op2 Y r[rs1]<0> CONCAT Y<31:1> n r[rd]<31> z if [r[rd]]=0 then 1, else 0 ((op1<31> AND op2<31> AND not r[rd]<31>) v OR (not op1<31> AND not op2<31> AND r[rd]<31>)) c ((op1<31> AND op2<31>) OR (not r[rd] AND (op1<31> OR op2<31>))
Assembler Syntax: Description:
mulscc regrs1 , reg_or_imm, regrd The multiply step instruction can be used to generate the 64-bit product of two signed or unsigned words. MULScc works as follows: 1. The incoming partial product" in r[rs1] is shifted right by one bit and the high order bit is replaced by the sign of the previous partial product (n XOR v). This is operand1. 2. If the least significant bit of the multiplier in the Y register equals zero, then operand2 is set to zero. If the LSB of the Y register equal one, then operand2 becomes the multiplicand, which is either the contents of r[rs2] if the instruction i field is zero, or sign extnd(simm13) if the i field is one. Operand2 is then added to operand1 and stored in r[rd] (the outgoing partial product). 3. The multiplier in the Y register is then shifted right by one bit and its high order bit is re placed by the least significant bit of the incoming partial product in r[rs1]. 4. The PSR's integer condition codes are updated according to the addition performed in step 2.
Traps: Format:
none
31 30 29
25 24
19 18
14
13
12
54
0
10
31 30 29
rd
100100
25 24 19 18
rs1
14
i=0
13 12
ignored
rs2
0
10
rd
100100
rs1
i=1
simm13
82
MATRA MHS Rev. A (10/09/96)
SPARC V7.0
OR
Operation: Assembler Syntax: Description: r[rd] or regrs1 , reg_or_imm, regrd
Inclusive-Or
r[rs1] OR (r[rs2] or sign extnd(simm13))
OR
This instruction does a bitwise logical OR of the contents of register r[rs1] with either the contents of r[rs2] (if bit field i=0) or the 13-bit, sign-extended immediate value contained in the instruction (if bit field i=1). The result is stored in register r[rd]. none
Traps: Format:
31 30 29
25 24
19 18
14
13
12
54
0
10
31 30 29
rd
000010
25 24 19 18
rs1
14
i=0
13 12
ignored
rs2
0
10
rd
000010
rs1
i=1
simm13
MATRA MHS Rev. A (10/09/96)
83
SPARC V7.0
ORcc
Operation: r[rd] n z v c Assembler Syntax: Description: r[rd]<31>
Inclusive-Or and modify icc
r[rs1] OR (r[rs2] or sign extnd(simm13)) if [r[rd]]=0 then 1, else 0 0 0
ORcc
orcc regrs1 , reg_or_imm, regrd This instruction does a bitwise logical OR of the contents of register r[rs1] with either the contents of r[rs2] (if bit field i=0) or the 13-bit, sign-extended immediate value contained in the instruction (if bit field i=1). The result is stored in register r[rd]. ORcc also modifies all the integer condition codes in the manner described above. none
Traps: Format:
31 30 29
25 24
19 18
14
13
12
54
0
10
31 30 29
rd
010010
25 24 19 18
rs1
14
i=0
13 12
ignored
rs2
0
10
rd
010010
rs1
i=1
simm13
84
MATRA MHS Rev. A (10/09/96)
SPARC V7.0
ORN
Operation: Assembler Syntax: Description: r[rd] orn regrs1 , reg_or_imm, regrd
Inclusive-Or Not
r[rs1] OR not(operand2), where operand2 = (r[rs2] or sign extnd(simm13))
ORN
This instruction does a bitwise logical OR of the contents of register r[rs1] with the one's complement of either the contents of r[rs2] (if bit field i=0) or the 13-bit, sign-extended immediate value contained in the instruction (if bit field i=1). The result is stored in register r[rd]. none
Traps: Format:
31 30 29
25 24
19 18
14
13
12
54
0
10
31 30 29
rd
000110
25 24 19 18
rs1
14
i=0
13 12
ignored
rs2
0
10
rd
000110
rs1
i=1
simm13
MATRA MHS Rev. A (10/09/96)
85
SPARC V7.0
ORNcc
Operation: r[rd] n z v c Assembler Syntax: Description: r[rd]<31>
Inclusive-Or Not and modify icc
ORNcc
r[rs1] OR not(operand2), where operand2 = (r[rs2] or sign extnd(simm13)) if [r[rd]]=0 then 1, else 0 0 0
orncc regrs1 , reg_or_imm, regrd This instruction does a bitwise logical OR of the contents of register r[rs1] with the one's complement of either the contents of r[rs2] (if bit field i=0) or the 13-bit, sign-extended immediate value contained in the instruction (if bit field i=1). The result is stored in register r[rd]. ORNcc also modifies all the integer condition codes in the manner described above. none
Traps: Format:
31 30 29
25 24
19 18
14
13
12
54
0
10
31 30 29
rd
010110
25 24 19 18
rs1
14
i=0
13 12
ignored
rs2
0
10
rd
010110
rs1
i=1
simm13
86
MATRA MHS Rev. A (10/09/96)
SPARC V7.0
RDPSR
Operation: Assembler Syntax: Description: Traps: Format:
31 30 29 25 24
Read Processor State Register (Privileged Instruction)
RDPSR
r[rd]
PSR
rd %psr, regrd RDPSR copies the contents of the PSR into the register specified by the rd field. privileged-instruction (if S=0)
19 18
0
10
rd
101001
ignored
MATRA MHS Rev. A (10/09/96)
87
SPARC V7.0
RDTBR
Operation: Assembler Syntax: Description: Traps: Format:
31 30 29 25 24
Read Trap Base Register (Privileged Instruction)
RDTBR
r[rd]
TBR
rd %tbr, regrd RDTBR copies the contents of the TBR into the register specified by the rd field. privileged_instruction (if S=0)
19 18
0
10
rd
101011
ignored
88
MATRA MHS Rev. A (10/09/96)
SPARC V7.0
RDWIM
Operation: Assembler Syntax: Description: Traps: Format:
31 30 29
Read Window Invalid Mask register (Privileged Instruction)
RDWIM
r[rd]
WIM
rd %wim, regrd RDWIM copies the contents of the WIM register into the register specified by the rd field. privileged_instruction (if S=0)
25 24
19 18
0
10
rd
101010
ignored
MATRA MHS Rev. A (10/09/96)
89
SPARC V7.0
RDY
Operation: Assembler Syntax: Description: Traps: Format:
31 30 29 25 24
Read Y register
r[rd] Y
RDY
rd %y, regrd RDY copies the contents of the Y register into the register specified by the rd field. none
19 18
0
10
rd
101000
ignored
90
MATRA MHS Rev. A (10/09/96)
SPARC V7.0
RESTORE
Operation: ncwp result CWP r[rd] CWP + 1 ncwp result
Restore caller's window
RESTORE
r[rs1] + (r[rs2] or sign extnd(simm13))
RESTORE does not affect condition codes Assembler Syntax: Description:
restore regrs1 , reg_or_imm, regrd RESTORE adds one to the Current Window Pointer (modulo the number of implemented windows) and compares this value against the Window Invalid Mask register. If the new window number corresponds to an invalidated window (WIM AND 2ncwp = 1), a window_underflow trap is generated. If the new window number is not invalid (i.e., its corresponding WIM bit is reset), then the contents of r[rs1] is added to either the contents of r[rs2] (field bit i = 1) or to the 13-bit, sign-extended immediate value contained in the instruction (field bit i = 0). Because the CWP has not been updated yet, r[rs1] and r[rs2] are read from the currently addressed window (the called window). The new CWP value is written into the PSR, causing the previous window (the caller's window) to become the active window. The result of the addition is now written into the r[rd] register of the restored window. Note that arithmetic operations involving the CWP are always done modulo the number of im plemented windows (8 for the CY7C601).
Traps: Format:
window_underflow
31 30 29
25 24
19 18
14
13
12
54
0
10
31 30 29
rd
111101
25 24 19 18
rs1
14
i=0
13 12
ignored
rs2
0
10
rd
111101
rs1
i=1
simm13
MATRA MHS Rev. A (10/09/96)
91
SPARC V7.0
RETT
Operation: ncwp ET PC nPC CWP S Assembler Syntax: Description: pS 1 CWP + 1
Return from Trap (Privileged Instruction)
RETT
nPC r[rs1] + (r[rs2] or sign extnd(simm13)) ncwp
rett address RETT adds one to the Current Window Pointer (modulo the number of implemented windows) and compares this value against the Window Invalid Mask register. If the new window number corresponds to an invalidated window (WIM AND 2ncwp = 1), a window_underflow trap is generated. If the new window number is not invalid (i.e., its corresponding WIM bit is reset), then RETT causes a delayed control transfer to the address derived by adding the contents of r[rs1] to either the contents of r[rs2] (field bit i = 1) or to the 13-bit, sign-extended immediate value contained in the instruction (field bit i = 0). Before the control transfer takes place, the new CWP value is written into the PSR, causing the previous window (the one in which the trap was taken) to become the active window. In addi tion, the PSR's ET bit is set to one (traps enabled) and the previous Supervisor bit (pS) is re stored to the S field. Although in theory RETT is a delayed control transfer instruction, in practice, RETT must al ways be immediately preceded by a JMPL instruction, creating a delayed control transfer cou ple (see Section NO TAG). This has the effect of annulling the delay instruction. If traps were already enabled before encountering the RETT instruction, an illegal_instruction trap is generated. If traps are not enabled (ET=0) when the RETT is encountered, but (1) the processor is not in supervisor mode (S=0), or (2) the window underflow condition described above occurs, or (3) if either of the two low order bits of the target address are nonzero, then a reset trap occurs. If a reset trap does occur, the tt field of the TBR encodes the trap condition: privileged_instruction, window_underflow, or memory_address_not_aligned. Programming note: To re execute the trapping instruction when returning from a trap handler, use the following sequence: jmpl rett %17, %0 %18 ! old PC ! old nPC
Note that the CY7C601 saves the PC in r[17] (local 1) and the nPC in r[18] (local2) of the trap window upon entering a trap.
To return to the instruction after the trapping instruction (e.g., when the trapping instruction is emulated), use the sequence: jmpl rett %18, %0 ! old nPC ! old nPC + 4 %18 + 4
92
MATRA MHS Rev. A (10/09/96)
SPARC V7.0
RETT
Traps:
Return from Trap (Privileged Instruction)
illegal_instruction reset (privileged_instruction) reset (memory_address_not_aligned) reset (window_underflow)
RETT
Format:
31 30 29 25 24 19 18 14 13 12 54 0
10
ignored
111001
19 18
rs1
14
i=0
13 12
ignored
rs2
0
31 30 29
25 24
10
ignored
111001
rs1
i=1
simm13
MATRA MHS Rev. A (10/09/96)
93
SPARC V7.0
SAVE
Operation: ncwp result CWP r[rd] CWP - 1 ncwp result
Save caller's window
SAVE
r[rs1] + (r[rs2] or sign extnd(simm13))
SAVE does not affect condition codes Assembler Syntax: Description:
save regrs1 , reg_or_imm, regrd SAVE subtracts one from the Current Window Pointer (modulo the number of implemented windows) and compares this value against the Window Invalid Mask register. If the new window number corresponds to an invalidated window (WIM AND 2ncwp = 1), a window_overflow trap is generated. If the new window number is not invalid (i.e., its corresponding WIM bit is reset), then the contents of r[rs1] is added to either the contents of r[rs2] (field bit i = 1) or to the 13-bit, sign-extended immediate value contained in the instruction (field bit i = 0). Because the CWP has not been updated yet, r[rs1] and r[rs2] are read from the currently addressed window (the calling window). The new CWP value is written into the PSR, causing the active window to become the previous window, and the called window to become the active window. The result of the addition is now written into the r[rd] register of the new window. Note that arithmetic operations involving the CWP are always done modulo the number of im plemented windows (8 for the CY7C601).
Traps: Format:
window_overflow
31 30 29
25 24
19 18
14
13
12
54
0
10
31 30 29
rd
111100
25 24 19 18
rs1
14
i=0
13 12
ignored
rs2
0
10
rd
111100
rs1
i=1
simm13
94
MATRA MHS Rev. A (10/09/96)
SPARC V7.0
SETHI
Operation: r[rd]<31:10> r[rd]<9:0> Assembler Syntax: 0 imm22
Set High 22 bits of r register
SETHI
sethi const22, regrd sethi %hi value, regrd
Description:
SETHI zeros the ten least significant bits of the contents of r[rd] and replaces its high-order 22 bits with imm22. The condition codes are not affected. Programming note: SETHI 0, %0 is the preferred instruction to use as a NOP, because it will not increase execution time if it follows a load instruction.
Traps: Format:
none
31 30 29
25 24
22
21
0
00
rd
100
imm22
MATRA MHS Rev. A (10/09/96)
95
SPARC V7.0
SLL
Operation: Assembler Syntax: Description: r[rd] sll regrs1 , reg_or_imm, regrd
Shift Left Logical
r[rs1] SLL by (r[rs2] or shcnt)
SLL
SLL shifts the contents of r[rs1] left by the number of bits specified by the shift count, filling the vacated positions with zeros. The shifted results are written into r[rd]. No shift occurs if the shift count is zero. If the i bit field equals zero, the shift count for SLL is the least significant five bits of the contents of r[rs2]. If the i bit field equals one, the shift count for SLL is the 13 bit, sign extended immedi ate value, simm13. In the instruction format and the operation description above, the least sig nificant five bits of simm13 is called shcnt. This instruction does not modify the condition codes.
Traps: Format:
none
31 30 29
25 24
19 18
14
13
12
54
0
10
31 30 29
rd
100101
25 24 19 18
rs1
14
i=0
13 12
ignored
54
rs2
0
10
rd
100101
rs1
i=1
ignored
shcnt
96
MATRA MHS Rev. A (10/09/96)
SPARC V7.0
SRA
Operation: Assembler Syntax: Description: r[rd] sra regrs1 , reg_or_imm, regrd
Shift Right Arithmetic
r[rs1] SRA by (r[rs2] or shcnt)
SRA
SRA shifts the contents of r[rs1] right by the number of bits specified by the shift count, filling the vacated positions with the MSB of r[rs1]. The shifted results are written into r[rd]. No shift occurs if the shift count is zero. If the i bit field equals zero, the shift count for SRA is the least significant five bits of the con tents of r[rs2]. If the i bit field equals one, the shift count for SRA is the 13 bit, sign extended immediate value, simm13. In the instruction format and the operation description above, the least significant five bits of simm13 is called shcnt. This instruction does not modify the condition codes. Programming note: A Shift Left Arithmetic by 1 (and calculate overflow)" can be implemented with an ADDcc instruction.
Traps: Format:
none
31 30 29
25 24
19 18
14
13
12
54
0
10
31 30 29
rd
100111
25 24 19 18
rs1
14
i=0
13 12
ignored
54
rs2
0
10
rd
100111
rs1
i=1
ignored
shcnt
MATRA MHS Rev. A (10/09/96)
97
SPARC V7.0
SRL
Operation: Assembler Syntax: Description: r[rd] srl regrs1 , reg_or_imm, regrd
Shift Right Logical
r[rs1] SRL by (r[rs2] or shcnt)
SRL
SRL shifts the contents of r[rs1] right by the number of bits specified by the shift count, filling the vacated positions with zeros. The shifted results are written into r[rd]. No shift occurs if the shift count is zero. If the i bit field equals zero, the shift count for SRL is the least significant five bits of the con tents of r[rs2]. If the i bit field equals one, the shift count for SRL is the 13 bit, sign extended immediate value, simm13. In the instruction format and the operation description above, the least significant five bits of simm13 is called shcnt. This instruction does not modify the condition codes.
Traps: Format:
none
31 30 29
25 24
19 18
14
13
12
54
0
10
31 30 29
rd
100110
25 24 19 18
rs1
14
i=0
13 12
ignored
54
rs2
0
10
rd
100110
rs1
i=1
ignored
shcnt
98
MATRA MHS Rev. A (10/09/96)
SPARC V7.0
ST
Operation: Assembler Syntax: Description: st regrd , [address]
Store Word
[r[rs1] + (r[rs2] or sign extnd(simm13))] r[rd]
ST
The ST instruction moves a word from the destination register, r[rd], into memory. The effective memory address is derived by summing the contents of r[rs1] and either the contents of r[rs2] if the instruction's i bit equals zero, or the 13-bit, sign-extended immediate operand contained in the instruction if i equals one. If ST takes a trap, the contents of the memory address remain unchanged. Programming note: If rs1 is set to 0 and i is set to 1, any location in the lowest or highest 4 kbytes of an address space can be written to without setting up a register.
Traps:
memory_address_not_aligned data_access_exception
Format:
31 30 29 25 24 19 18 14 13 12 54 0
11
31 30 29
rd
000100
25 24 19 18
rs1
14
i=0
13 12
ignored
rs2
0
11
rd
000100
rs1
i=1
simm13
MATRA MHS Rev. A (10/09/96)
99
SPARC V7.0
STA
Operation: address space [r[rs1] + r[rs2]] Assembler Syntax: Description: asi
Store Word into Alternate space (Privileged Instruction)
STA
r[rd]
sta regrd , [regaddr] asi The STA instruction moves a word from the destination register, r[rd], into memory. The effective memory address is a combination of the address space value given in the asi field and the address derived by summing the contents of r[rs1] and r[rs2]. If STA takes a trap, the contents of the memory address remain unchanged.
Traps:
illegal_instruction (if i=1) privileged_instruction (if S=0) memory_address_not_aligned data_access_exception
Format:
31 30 29 25 24 19 18 14 13 12 54 0
11
rd
010100
rs1
i=0
asi
rs2
100
MATRA MHS Rev. A (10/09/96)
SPARC V7.0
STB
Operation: Assembler Syntax: stb regrd , [address] synonyms: stub, stsb Description:
Store Byte
[r[rs1] + (r[rs2] or sign extnd(simm13))] r[rd]
STB
The STB instruction moves the least significant byte from the destination register, r[rd], into memory. The effective memory address is derived by summing the contents of r[rs1] and either the contents of r[rs2] if the instruction's i bit equals zero, or the 13-bit, sign-extended immediate operand contained in the instruction if i equals one. If STB takes a trap, the contents of the memory address remain unchanged. Programming note: If rs1 is set to 0 and i is set to 1, any location in the lowest or highest 4 kbytes of an address space can be written to without setting up a register.
Traps: Format:
data_access_exception
31 30 29
25 24
19 18
14
13
12
54
0
11
31 30 29
rd
000101
25 24 19 18
rs1
14
i=0
13 12
ignored
rs2
0
11
rd
000101
rs1
i=1
simm13
MATRA MHS Rev. A (10/09/96)
101
SPARC V7.0
STBA
Operation: address space [r[rs1] + r[rs2]] Assembler Syntax: asi r[rd]
Store Byte into Alternate space (Privileged Instruction)
STBA
stba regrd , [regaddr] asi synonyms: stuba, stsba
Description:
The STBA instruction moves the least significant byte from the destination register, r[rd], into memory. The effective memory address is a combination of the address space value given in the asi field and the address derived by summing the contents of r[rs1] and r[rs2]. If STBA takes a trap, the contents of the memory address remain unchanged.
Traps:
illegal_instruction (if i=1) privileged_instruction (if S=0) data_access_exception
Format:
31 30 29 25 24 19 18 14 13 12 54 0
11
rd
010101
rs1
i=0
asi
rs2
102
MATRA MHS Rev. A (10/09/96)
SPARC V7.0
STC
Operation: Assembler Syntax: Description: st creg rd , [address]
Store Coprocessor register
[r[rs1] + (r[rs2] or sign extnd(simm13))] c[rd]
STC
The STC instruction moves a word from a coprocessor register, c[rd], into memory. The effective memory address is derived by summing the contents of r[rs1] and either the contents of r[rs2] if the instruction's i bit equals zero, or the 13-bit, sign-extended immediate operand contained in the instruction if i equals one. If the PSR's EC bit is set to zero or if no coprocessor is present, a cp_disabled trap will be gener ated. If STC takes a trap, memory remains unchanged. Programming note: If rs1 is set to 0 and i is set to 1, any location in the lowest or highest 4 kbytes of an address space can be written to without setting up a register.
Traps:
cp_disabled cp_exception memory_address_not_aligned data_access_exception
Format:
31 30 29 25 24 19 18 14 13 12 54 0
11
31 30 29
rd
110100
25 24 19 18
rs1
14
i=0
13 12
ignored
rs2
0
11
rd
110100
rs1
i=1
simm13
MATRA MHS Rev. A (10/09/96)
103
SPARC V7.0
STCSR
Operation: Assembler Syntax: Description: st %csr, [address]
Store Coprocessor State Register
CSR
STCSR
[r[rs1] + (r[rs2] or sign extnd(simm13))]
The STCSR instruction moves the contents of the Coprocessor State Register into memory. The effective memory address is derived by summing the contents of r[rs1] and either the contents of r[rs2] if the instruction's i bit equals zero, or the 13-bit, sign-extended immediate operand contained in the instruction if i equals one. If the PSR's EC bit is set to zero or if no coprocessor is present, a cp_disabled trap will be gener ated. If STCSR takes a trap, the contents of the memory address remain unchanged. Programming note: If rs1 is set to 0 and i is set to 1, any location in the lowest or highest 4 kbytes of an address space can be written to without setting up a register.
Traps:
cp_disabled cp_exception memory_address_not_aligned data_access_exception
Format:
31 30 29 25 24 19 18 14 13 12 54 0
11
31 30 29
rd
110101
25 24 19 18
rs1
14
i=0
13 12
ignored
rs2
0
11
rd
110101
rs1
i=1
simm13
104
MATRA MHS Rev. A (10/09/96)
SPARC V7.0
STD
Operation: Assembler Syntax: Description:
Store Doubleword
[r[rs1] + (r[rs2] or sign extnd(simm13))] [r[rs1] + (r[rs2] or sign extnd(simm13)) + 4] r[rd] r[rd + 1]
STD
std regrd , [address] The STD instruction moves a doubleword from the destination register pair, r[rd] and r[rd+1], into memory. The effective memory address is derived by summing the contents of r[rs1] and either the contents of r[rs2] if the instruction's i bit equals zero, or the 13-bit, sign-extended immediate operand contained in the instruction if i equals one. The most significant word in the even-numbered destination register is written into memory at the effective address and the least significant memory word in the next odd-numbered register is written into memory at the effective address + 4. If a data_access_exception trap takes place during the effective address memory access, memory remains unchanged. Programming note: If rs1 is set to 0 and i is set to 1, any location in the lowest or highest 4 kbytes of an address space can be written to without setting up a register.
Traps:
memory_address_not_aligned data_access_exception
Format:
31 30 29 25 24 19 18 14 13 12 54 0
11
31 30 29
rd
000111
25 24 19 18
rs1
14
i=0
13 12
ignored
rs2
0
11
rd
000111
rs1
i=1
simm13
MATRA MHS Rev. A (10/09/96)
105
SPARC V7.0
STDA
Operation: address space
Store Doubleword into Alternate space (Privileged Instruction)
asi r[rd] r[rd + 1]
STDA
[r[rs1] + (r[rs2] or sign extnd(simm13))] [r[rs1] + (r[rs2] or sign extnd(simm13)) + 4] Assembler Syntax: Description:
stda regrd , [regaddr] asi The STDA instruction moves a doubleword from the destination register pair, r[rd] and r[rd+1], into memory. The effective memory address is a combination of the address space value given in the asi field and the address derived by summing the contents of r[rs1] and r[rs2]. The most significant word in the even-numbered destination register is written into memory at the effective address and the least significant memory word in the next odd-numbered register is written into memory at the effective address + 4. If a data_access_exception trap takes place during the effective address memory access, memory remains unchanged.
Traps:
illegal_instruction (if i=1) privileged_instruction (if S=0) memory_address_not_aligned data_access_exception
Format:
31 30 29 25 24 19 18 14 13 12 54 0
11
rd
010111
rs1
i=0
asi
rs2
106
MATRA MHS Rev. A (10/09/96)
SPARC V7.0
STDC
Operation: Assembler Syntax: Description:
Store Doubleword Coprocessor
[r[rs1] + (r[rs2] or sign extnd(simm13))] [r[rs1] + (r[rs2] or sign extnd(simm13)) + 4] c[rd] c[rd + 1]
STDC
std creg rd , [address] The STDC instruction moves a doubleword from the coprocessor register pair, c[rd] and c[rd+1], into memory. The effective memory address is derived by summing the contents of r[rs1] and either the contents of r[rs2] if the instruction's i bit equals zero, or the 13-bit, sign-extended immediate operand contained in the instruction if i equals one. The most significant word in the even-numbered destination register is written into memory at the effective address and the least significant memory word in the next odd-numbered register is written into memory at the effective address + 4. If the PSR's EC bit is set to zero or if no coprocessor is present, a cp_disabled trap will be gener ated. If a data_access_exception trap takes place during the effective address memory access, memory remains unchanged. Programming note: If rs1 is set to 0 and i is set to 1, any location in the lowest or highest 4 kbytes of an address space can be written to without setting up a register.
Traps:
cp_disabled cp_exception memory_address_not_aligned data_access_exception
Format:
31 30 29 25 24 19 18 14 13 12 54 0
11
31 30 29
rd
110111
25 24 19 18
rs1
14
i=0
13 12
ignored
rs2
0
11
rd
110111
rs1
i=1
simm13
MATRA MHS Rev. A (10/09/96)
107
SPARC V7.0
STDCQ
Operation:
Store Doubleword Coprocessor Queue (Privileged Instruction)
STDCQ
[r[rs1] + (r[rs2] or sign extnd(simm13))] [r[rs1] + (r[rs2] or sign extnd(simm13)) + 4]
CQ.ADDR CQ.INSTR
Assembler Syntax: Description:
std %cq, [address] The STDCQ instruction moves the front entry of the Coprocessor Queue into memory. The effective memory address is derived by summing the contents of r[rs1] and either the contents of r[rs2] if the instruction's i bit equals zero, or the 13-bit, sign-extended immediate operand contained in the instruction if i equals one. The address portion of the queue entry is written into memory at the effective address and the instruction portion of the entry is written into memory at the effective address + 4. If the PSR's EC bit is set to zero or if no coprocessor is present, a cp_disabled trap will be gener ated. If a data_access_exception trap takes place during the effective address memory access, memory remains unchanged. Programming note: If rs1 is set to 0 and i is set to 1, any location in the lowest or highest 4 kbytes of an address space can be written to without setting up a register.
Traps:
cp_disabled cp_exception privileged_instruction (if S=0) memory_address_not_aligned data_access_exception
Format:
31 30 29 25 24 19 18 14 13 12 54 0
11
31 30 29
rd
110110
25 24 19 18
rs1
14
i=0
13 12
ignored
rs2
0
11
rd
110110
rs1
i=1
simm13
108
MATRA MHS Rev. A (10/09/96)
SPARC V7.0
STDF
Operation: Assembler Syntax: Description:
Store Doubleword Floating-Point
[r[rs1] + (r[rs2] or sign extnd(simm13))] [r[rs1] + (r[rs2] or sign extnd(simm13)) + 4] f[rd] f[rd + 1]
STDF
std fregrd , [address] The STDF instruction moves a doubleword from the floating-point register pair, f[rd] and f[rd+1], into memory. The effective memory address is derived by summing the contents of r[rs1] and either the contents of r[rs2] if the instruction's i bit equals zero, or the 13-bit, sign-extended immediate operand contained in the instruction if i equals one. The most significant word in the even-numbered destination register is written into memory at the effective address and the least significant memory word in the next odd-numbered register is written into memory at the effective address + 4. If the PSR's EF bit is set to zero or if no floating point unit is present, an fp_disabled trap will be generated. If a trap takes place, memory remains unchanged. Programming note: If rs1 is set to 0 and i is set to 1, any location in the lowest or highest 4 kbytes of an address space can be written to without setting up a register.
Traps:
fp_disabled fp_exception* memory_address_not_aligned data_access_exception
Format:
31 30 29 25 24 19 18 14 13 12 54 0
11
31 30 29
rd
100111
25 24 19 18
rs1
14
i=0
13 12
ignored
rs2
0
11
rd
100111
rs1
i=1
simm13
* NOTE: An attempt to execute any FP instruction will cause a pending FP exception to be recognized by the integer unit.
MATRA MHS Rev. A (10/09/96)
109
SPARC V7.0
STDFQ
Operation:
Store Doubleword Floating-Point Queue (Privileged Instruction)
STDFQ
[r[rs1] + (r[rs2] or sign extnd(simm13))] [r[rs1] + (r[rs2] or sign extnd(simm13)) + 4]
FQ.ADDR FQ.INSTR
Assembler Syntax: Description:
std %fq, [address] The STDFQ instruction moves the front entry of the floating-point queue into memory. The effective memory address is derived by summing the contents of r[rs1] and either the contents of r[rs2] if the instruction's i bit equals zero, or the 13-bit, sign-extended immediate operand contained in the instruction if i equals one. The address portion of the queue entry is written into memory at the effective address and the instruction portion of the entry is written into memory at the effective address + 4. If the FPU is in exception mode, the queue is then advanced to the next entry, or it becomes empty (as indicated by the qne bit in the FSR). If the PSR's EF bit is set to zero or if no floating point unit is present, an fp_disabled trap will be generated. If a trap takes place, memory remains unchanged. Programming note: If rs1 is set to 0 and i is set to 1, any location in the lowest or highest 4 kbytes of an address space can be written to without setting up a register.
Traps:
fp_disabled fp_exception* privileged_instruction (if S=0) memory_address_not_aligned data_access_exception
Format:
31 30 29 25 24 19 18 14 13 12 54 0
11
31 30 29
rd
100110
25 24 19 18
rs1
14
i=0
13 12
ignored
rs2
0
11
rd
100110
rs1
i=1
simm13
* NOTE: An attempt to execute any FP instruction will cause a pending FP exception to be recognized by the integer unit.
110
MATRA MHS Rev. A (10/09/96)
SPARC V7.0
STF
Operation: Assembler Syntax: Description: st freg rd , [address]
Store Floating-Point register
[r[rs1] + (r[rs2] or sign extnd(simm13))] f[rd]
STF
The STF instruction moves a word from a floating-point register, f[rd], into memory. The effective memory address is derived by summing the contents of r[rs1] and either the contents of r[rs2] if the instruction's i bit equals zero, or the 13-bit, sign-extended immediate operand contained in the instruction if i equals one. If the PSR's EF bit is set to zero or if no floating point unit is present, an fp_disabled trap will be generated. If STF takes a trap, memory remains unchanged. Programming note: If rs1 is set to 0 and i is set to 1, any location in the lowest or highest 4 kbytes of an address space can be written to without setting up a register.
Traps:
fp_disabled fp_exception* memory_address_not_aligned data_access_exception
Format:
31 30 29 25 24 19 18 14 13 12 54 0
11
31 30 29
rd
100100
25 24 19 18
rs1
14
i=0
13 12
ignored
rs2
0
11
rd
100100
rs1
i=1
simm13
* NOTE: An attempt to execute any FP instruction will cause a pending FP exception to be recognized by the integer unit.
MATRA MHS Rev. A (10/09/96)
111
SPARC V7.0
STFSR
Operation: Assembler Syntax: Description: st %fsr, [address]
Store Floating-Point State Register
FSR
STFSR
[r[rs1] + (r[rs2] or sign extnd(simm13))]
The STFSR instruction moves the contents of the Floating-Point State Register into memory. The effective memory address is derived by summing the contents of r[rs1] and either the contents of r[rs2] if the instruction's i bit equals zero, or the 13-bit, sign-extended immediate operand contained in the instruction if i equals one. This instruction will wait for all pending FPops to complete execution before it writes the FSR into memory. If the PSR's EF bit is set to zero or if no floating point unit is present, an fp_disabled trap will be generated. If STFSR takes a trap, the contents of the memory address remain unchanged. Programming note: If rs1 is set to 0 and i is set to 1, any location in the lowest or highest 4 kbytes of an address space can be written to without setting up a register.
Traps:
fp_disabled fp_exception* memory_address_not_aligned data_access_exception
Format:
31 30 29 25 24 19 18 14 13 12 54 0
11
31 30 29
rd
100101
25 24 19 18
rs1
14
i=0
13 12
ignored
rs2
0
11
rd
100101
rs1
i=1
simm13
* NOTE: An attempt to execute any FP instruction will cause a pending FP exception to be recognized by the integer unit.
112
MATRA MHS Rev. A (10/09/96)
SPARC V7.0
STH
Operation: Assembler Syntax: Description:
Store Halfword
[r[rs1] + (r[rs2] or sign extnd(simm13))] r[rd]
STH
sth regrd , [address] synonyms: stuh, stsh The STH instruction moves the least significant halfword from the destination register, r[rd], into memory. The effective memory address is derived by summing the contents of r[rs1] and either the contents of r[rs2] if the instruction's i bit equals zero, or the 13-bit, sign-extended immediate operand contained in the instruction if i equals one. If STH takes a trap, the contents of the memory address remain unchanged. Programming note: If rs1 is set to 0 and i is set to 1, any location in the lowest or highest 4 kbytes of an address space can be written to without setting up a register.
Traps:
memory_address_not_aligned data_access_exception
Format:
31 30 29 25 24 19 18 14 13 12 54 0
10
31 30 29
rd
000110
25 24 19 18
rs1
14
i=0
13 12
ignored
rs2
0
10
rd
000110
rs1
i=1
simm13
MATRA MHS Rev. A (10/09/96)
113
SPARC V7.0
STHA
Operation: address space asi
Store Halfword into Alternate space (Privileged Instruction)
STHA
[r[rs1] + (r[rs2] or sign extnd(simm13))] Assembler Syntax:
r[rd]
stha regrd , [address] synonyms: stuha, stsha
Description:
The STHA instruction moves the least significant halfword from the destination register, r[rd], into memory. The effective memory address is a combination of the address space value given in the asi field and the address derived by summing the contents of r[rs1] and r[rs2]. If STHA takes a trap, the contents of the memory address remain unchanged.
Traps:
illegal_instruction (if i=1) privileged_instruction (if S=0) memory_address_not_aligned data_access_exception
Format:
31 30 29 25 24 19 18 14 13 12 54 0
11
rd
010110
rs1
i=0
asi
rs2
114
MATRA MHS Rev. A (10/09/96)
SPARC V7.0
SUB
Operation: Assembler Syntax: Description: r[rd] sub regrs1 , reg_or_imm, regrd
Subtract
r[rs1] - (r[rs2] or sign extnd(simm13))
SUB
The SUB instruction subtracts either the contents of the register named in the rs2 field, r[rs2], if the instruction's i bit equals zero, or the 13-bit, sign-extended immediate operand contained in the instruction if i equals one, from register r[rs1]. The result is placed in the register specified in the rd field. none
Traps: Format:
31 30 29
25 24
19 18
14
13
12
54
0
10
31 30 29
rd
000100
25 24 19 18
rs1
14
i=0
13 12
ignored
rs2
0
10
rd
000100
rs1
i=1
simm13
MATRA MHS Rev. A (10/09/96)
115
SPARC V7.0
SUBcc
Operation: r[rd] n z v c r[rd]<31>
Subtract and modify icc
r[rs1] - operand2, where operand2 = (r[rs2] or sign extnd(simm13)) if r[rd] =0 then 1, else 0 (r[rs1]<31> AND not operand2<31> AND not r[rd]<31>) OR (not r[rs1]<31> AND operand2<31> AND r[rd]<31>) (not r[rs1]<31> AND operand2<31>) OR (r[rd]<31> AND (not r[rs1]<31> OR operand2<31>))
SUBcc
Assembler Syntax: Description:
subcc regrs1, reg_or_imm, regrd The SUBcc instruction subtracts either the contents of register r[rs2] (if the instruction's i bit equals zero) or the 13-bit, sign-extended immediate operand contained in the instruction (if i equals one) from register r[rs1]. The result is placed in register r[rd]. In addition, SUBcc modifies all the integer condition codes in the manner described above. Programming note: A SUBcc instruction with rd = 0 can be used for signed and unsigned inte ger comparison.
Traps: Format:
none
31 30 29
25 24
19 18
14
13
12
54
0
10
31 30 29
rd
010100
25 24 19 18
rs1
14
i=0
13 12
ignored
rs2
0
10
rd
010100
rs1
i=1
simm13
116
MATRA MHS Rev. A (10/09/96)
SPARC V7.0
SUBX
Operation: Assembler Syntax: Description: r[rd]
Subtract with Carry
r[rs1] - (r[rs2] or sign extnd(simm13)) - c
SUBX
subx regrs1 , reg_or_imm, regrd SUBX subtracts either the contents of register r[rs2] (if the instruction's i bit equals zero) or the 13-bit, sign-extended immediate operand contained in the instruction (if i equals one) from register r[rs1]. It then subtracts the PSR's carry bit (c) from that result. The final result is placed in the register specified in the rd field. none
Traps: Format:
31 30 29
25 24
19 18
14
13
12
54
0
10
31 30 29
rd
001100
25 24 19 18
rs1
14
i=0
13 12
ignored
rs2
0
10
rd
001100
rs1
i=1
simm13
MATRA MHS Rev. A (10/09/96)
117
SPARC V7.0
SUBXcc
Operation: r[rd] n z v c r[rd]<31>
Subtract with Carry and modify icc
SUBXcc
r[rs1] - operand2 - c, where operand2 = (r[rs2] or sign extnd(simm13)) if r[rd] =0 then 1, else 0 (r[rs1]<31> AND not operand2<31> AND not r[rd]<31>) OR (not r[rs1]<31> AND operand2<31> AND r[rd]<31>) (not r[rs1]<31> AND operand2<31>) OR (r[rd]<31> AND (not r[rs1]<31> OR operand2<31>))
Assembler Syntax: Description:
subxcc regrs1 , reg_or_imm, regrd SUBXcc subtracts either the contents of register r[rs2] (if the instruction's i bit equals zero) or the 13-bit, sign-extended immediate operand contained in the instruction (if i equals one) from register r[rs1]. It then subtracts the PSR's carry bit (c) from that result. The final result is placed in the register specified in the rd field. In addition, SUBXcc modifies all the integer condition codes in the manner described above. none
Traps: Format:
31 30 29
25 24
19 18
14
13
12
54
0
10
31 30 29
rd
011100
25 24 19 18
rs1
14
i=0
13 12
ignored
rs2
0
10
rd
011100
rs1
i=1
simm13
118
MATRA MHS Rev. A (10/09/96)
SPARC V7.0
SWAP
Operation: word temp r[rd]
Swap r register with memory
[r[rs1] + (r[rs2] or sign extnd(simm13))]
SWAP
r[rd] word r[rs1] + (r[rs2] or sign extnd(simm13)) Assembler Syntax: Description:
temp
swap [source], regrd SWAP atomically exchanges the contents of r[rd] with the contents of a memory location, i.e., without allowing asynchronous trap interruptions. In a multiprocessor system, two or more processors executing SWAP instructions simultaneously are guaranteed to execute them serially, in some order. The effective memory address is derived by summing the contents of r[rs1] and either the con tents of r[rs2] if the instruction's i bit equals zero, or the 13 bit, sign extended immediate oper and contained in the instruction if i equals one. If SWAP takes a trap, the contents of the memory address and the destination register remain unchanged. Programming note: If rs1 is set to 0 and i is set to 1, any location in the lowest or highest 4 kbytes of an address space can be accessed without setting up a register.
Traps:
memory_address_not_aligned data_access_exception
Format:
31 30 29 25 24 19 18 14 13 12 54 0
11
31 30 29
rd
001111
25 24 19 18
rs1
14
i=0
13 12
ignored
rs2
0
11
rd
001111
rs1
i=1
simm13
MATRA MHS Rev. A (10/09/96)
119
SPARC V7.0
SWAPA
Operation: address space word temp r[rd] r[rd] word
Swap r register with memory in Alternate space (Privileged Instruction)
asi
SWAPA
[r[rs1] + r[rs2]]
[r[rs1] + r[rs2]] Assembler Syntax: Description:
temp
swapa [regsource] asi, regrd SWAPA atomically exchanges the contents of r[rd] with the contents of a memory location, i.e., without allowing asynchronous trap interruptions. In a multiprocessor system, two or more processors executing SWAPA instructions simultaneously are guaranteed to execute them serially, in some order. The effective memory address is a combination of the address space value given in the asi field and the address derived by summing the contents of r[rs1] and r[rs2]. If SWAPA takes a trap, the contents of the memory address and the destination register remain unchanged.
Traps:
illegal_instruction (if i=1) privileged_instruction (if S=0) memory_address_not_aligned data_access_exception
Format:
31 30 29 25 24 19 18 14 13 12 54 0
11
rd
011111
rs1
i=0
asi
rs2
120
MATRA MHS Rev. A (10/09/96)
SPARC V7.0
TADDcc
Operation: r[rd] n z v r[rd]<31>
Tagged Add and modify icc
TADDcc
r[rs1] + operand2, where operand2 = (r[rs2] or sign extnd(simm13)) if r[rd]=0 then 1, else 0 (r[rs1]<31> AND operand2<31> AND not r[rd]<31>) OR (not r[rs1]<31> AND not operand2<31> AND r[rd]<31>) OR (r[rs1]<1:0> 0 OR operand2<1:0> 0)
c
(r[rs1]<31> AND operand2<31> OR (not r[rd]<31> AND (r[rs1]<31> OR operand2<31>))
Assembler Syntax: Description:
taddcc regrs1 , reg_or_imm, regrd TADDcc adds the contents of r[rs1] to either the contents of r[rs2] if the instruction's i bit equals zero, or to a 13-bit, sign-extended immediate operand if i equals one. The result is placed in the register specified in the rd field. In addition to the normal arithmetic overflow, an overflow condition also exists if bit 1 or bit 0 of either operand is not zero. TADDcc modifies all the integer condition codes in the manner described above. none
Traps: Format:
31 30 29
25 24
19 18
14
13
12
54
0
10
31 30 29
rd
100000
25 24 19 18
rs1
14
i=0
13 12
ignored
rs2
0
10
rd
100000
rs1
i=1
simm13
MATRA MHS Rev. A (10/09/96)
121
SPARC V7.0
TADDccTV
Operation:
Tagged Add (modify icc) Trap on Overflow
TADDccTV
result r[rs1] + operand2, where operand 2 = (r[rs2] or sign extnd(simm13)) (r[rs1]<31> AND operand2<31> AND not r[rd]<31>) tv OR (not r[rs1]<31> AND not operand2<31> AND r[rd]<31>) OR (r[rs1]<1:0> 0 OR operand2<1:0> 0) if tv = 1, then tag overflow trap; else n r[rd]<31> z v c r[rd] if r[rd]=0 then 1, else 0 tv (r[rs1]<31> AND operand2<31> OR (not r[rd]<31> AND (r[rs1]<31> OR operand2<31>)) result
Assembler Syntax: Description:
taddcctv regrs1 , reg_or_imm, regrd TADDccTV adds the contents of r[rs1] to either the contents of r[rs2] if the instruction's i bit equals zero, or to a 13-bit, sign-extended immediate operand if i equals one. In addition to the normal arithmetic overflow, an overflow condition also exists if bit 1 or bit 0 of either operand is not zero. If TADDccTV detects an overflow condition, a tag_overflow trap is generated and the destina tion register and condition codes remain unchanged. If no overflow is detected, TADDccTV places the result in the register specified in the rd field and modifies all the integer condition codes in the manner described above (the overflow bit is, of course, set to zero).
Traps: Format:
tag_overflow
31 30 29
25 24
19 18
14
13
12
54
0
10
31 30 29
rd
100010
25 24 19 18
rs1
14
i=0
13 12
ignored
rs2
0
10
rd
100010
rs1
i=1
simm13
122
MATRA MHS Rev. A (10/09/96)
SPARC V7.0
Ticc
Operation: tt else PC nPC nPC + 4 nPC Assembler Syntax:
Trap on integer condition codes
If condition true, then trap_instruction; 128 + [r[rs1] + (r[rs2] or sign extnd(simm13))]<6:0>
Ticc
ta{,a} tn{,a} tne{,a} te{,a} tg{,a} tle{,a} tge{,a} tl{,a} tgu{,a} tleu{,a} tcc{,a} tcs{,a} tpos{,a} tneg{,a} tvc{,a} tvs{,a}
label label label label label label label label label label label label label label label label
synonym: tnz synonym: tz
synonym: tgeu synonym: tlu
Description:
A Ticc instruction evaluates specific integer condition code combinations (from the PSR's icc field) based on the trap type as specified by the value in the instruction's cond field. If the specified combination of condition codes evaluates as true, and there are no higher-priority traps pending, then a trap_instruction trap is generated. If the condition codes evaluate as false, the trap is not generated. If a trap_instruction trap is generated, the tt field of the Trap Base Register (TBR) is written with 128 plus the least significant seven bits of r[rs1] plus either r[rs2] (bit field i =0) or the 13 bit sign extended immediate value contained in the instruction (bit field i =1). See Section NO TAG for the complete definition of a trap.
Traps:
trap_instruction
MATRA MHS Rev. A (10/09/96)
123
SPARC V7.0
Ticc
Mnemonic TN TE TLE TL TLEU TCS TNEG TVS TA TNE TG TGE TGU TCC TPOS TVC Format:
31 30 29 28 25 24
Trap on integer condition codes
Cond. 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Trap Never Trap on Equal Trap on Less or Equal Trap on Less Trap on Less or Equal, Unsigned Trap on Carry Set (Less then, Unsigned) Trap on Negative Trap on oVerflow Set Trap Always Trap on Not Equal Trap on Greater Trap on Greater or Equal Trap on Greater, Unsigned Trap on Carry Clear (Greater than or Equal, Unsigned) Trap on Positive Trap on oVerflow Clear Operation z icc Test No test
Ticc
z OR (n XOR v) n XOR v c OR z c n v No test not z not(z OR (n XOR v)) not(n XOR v) not(c OR z) not c not n not v
19 18
14
13
12
54
0
1 0 ign. cond. 1 1 1 0 1 0
31 30 29 28 25 24 19 18
rs1
14
i=0
13 12
ignored
rs2
0
1 0 ign. cond. 1 1 1 0 1 0
ign. = ignored cond. = condition
rs1
i=1
simm13
124
MATRA MHS Rev. A (10/09/96)
SPARC V7.0
TSUBcc
Operation: r[rd] n z v c r[rd]<31>
Tagged Subtract and modify icc
r[rs1] - operand2, where operand2 = (r[rs2] or sign extnd(simm13))
TSUBcc
if r[rd]=0 then 1, else 0 (r[rs1]<31> AND not operand2<31> AND not r[rd]<31>) OR (not r[rs1]<31> AND operand2<31> AND r[rd]<31>) OR (r[rs1]<1:0> 0 OR operand2<1:0> 0) (not r[rs1]<31> AND operand2<31> OR (r[rd]<31> AND (not r[rs1]<31> OR operand2<31>))
Assembler Syntax: Description:
tsubcc regrs1 , reg_or_imm, regrd TSUBcc subtracts either the contents of register r[rs2] (if the instruction's i bit equals zero) or the 13-bit, sign-extended immediate operand contained in the instruction (if i equals one) from register r[rs1]. The result is placed in the register specified in the rd field. In addition to the normal arithmetic overflow, an overflow condition also exists if bit 1 or bit 0 of either operand is not zero. TSUBcc modifies all the integer condition codes in the manner described above. none
Traps: Format:
31 30 29
25 24
19 18
14
13
12
54
0
10
31 30 29
rd
100001
25 24 19 18
rs1
14
i=0
13 12
ignored
rs2
0
10
rd
100001
rs1
i=1
simm13
MATRA MHS Rev. A (10/09/96)
125
SPARC V7.0
TSUBccTV
Operation: result tv
Tagged Subtract (modify icc) Trap on Overflow
TSUBccTV
r[rs1] - operand2, where operand2 = (r[rs2] or sign extnd(simm13)) (r[rs1]<31> AND not operand2<31> AND not r[rd]<31>) OR (not r[rs1]<31> AND operand2<31> AND r[rd]<31>) OR (r[rs1]<1:0> 0 OR operand2<1:0> 0)
if tv = 1, then tag overflow trap; else n z v c r[rd] Assembler Syntax: Description: r[rd]<31> if r[rd]=0 then 1, else 0 tv (not(r[rs1]<31>) AND operand2<31> OR result
(r[rd]<31> AND (not(r[rs1]<31>) OR operand2<31>))
tsubcctv regrs1 , reg_or_imm, regrd TSUBccTV subtracts either the contents of register r[rs2] (if the instruction's i bit equals zero) or the 13-bit, sign-extended immediate operand contained in the instruction (if i equals one) from register r[rs1]. In addition to the normal arithmetic overflow, an overflow condition also exists if bit 1 or bit 0 of either operand is not zero. If TSUBccTV detects an overflow condition, a tag_overflow trap is generated and the destina tion register and condition codes remain unchanged. If no overflow is detected, TSUBccTV places the result in the register specified in the rd field and modifies all the integer condition codes in the manner described above (the overflow bit is, of course, set to zero).
Traps: Format:
tag_overflow
31 30 29
25 24
19 18
14
13
12
54
0
10
31 30 29
rd
100011
25 24 19 18
rs1
14
i=0
13 12
ignored
rs2
0
10
rd
100011
rs1
i=1
simm13
126
MATRA MHS Rev. A (10/09/96)
SPARC V7.0
UNIMP
Operation: Assembler Syntax: Description: illegal instruction trap unimp const22
Unimplemented instruction
UNIMP
Executing the UNIMP instruction causes an immediate illegal_instruction trap. The value in the const22 field is ignored. Programming note: UNIMP can be used as part of the protocol for calling a function that is ex pected to return an aggregate value, such as a C language structure. 1. An UNIMP instruction is placed after (not in) the delay slot after the CALL instruction in the calling function. 2. If the called function is expecting to return a structure, it will find the size of the structure that the caller expects to be returned as the const22 operand of the UNIMP instruction. The called function can check the opcode to make sure it is indeed UNIMP. 3. If the function is not going to return a structure, upon returning, it attempts to execute UNIMP rather than skipping over it as it should. This causes the program to terminate. The behavior adds some run time checking to an interface that cannot be checked properly at compile time.
Traps: Format:
illegal_instruction
31 30 29
25 24
22
21
0
00
ignored
000
const2 2
MATRA MHS Rev. A (10/09/96)
127
SPARC V7.0
WRPSR
Operation: Assembler Syntax: Description: PSR
Write Processor State Register (Privileged Instruction)
r[rs1] XOR (r[rs2] or sign extnd(simm13))
WRPSR
wr regrs1 , reg_or_imm, %psr WRPSR does a bitwise logical XOR of the contents of register r[rs1] with either the contents of r[rs2] (if bit field i=0) or the 13-bit sign-extended immediate value contained in the instruction (if bit field i=1). The result is written into the writable subfields of the PSR. However, if the result's CWP field would point to an unimplemented window, an illegal_instruction trap is generated and the PSR remains unchanged. WRPSR is a delayed write instruction: 1. If any of the three instructions following a WRPSR uses any PSR field that WRPSR modi fied, the value of that field is unpredictable. Note that any instruction which references a non-global register makes use of the CWP, so following WRPSR with three NOPs would be the safest course. 2. If a WRPSR instruction is updating the PSR's Processor Interrupt Level (PIL) to a new val ue and is simultaneously setting Enable Traps (ET) to one, this could result in an interrupt trap at a level equal to the old PIL value. 3. If any of the three instructions after a WRPSR instruction reads the modified PSR, the val ue read is unpredictable. 4. If any of the three instructions after a WRPSR is trapped, a subsequent RDPSR in the trap handler will get the register's new value. Programming note: Two WRPSR instructions should be used when enabling traps and changing the PIL value. The first WRPSR should specify ET=0 with the new PIL value, and the second should specify ET=1 with the new PIL value.
Traps: Format:
illegal_instruction privileged_instruction (if S=0)
31 30 29
25 24
19 18
14
13
12
54
0
10
ignored
110001
19 18
rs1
14
i=0
13 12
ignored
rs2
0
31 30 29
25 24
10
ignored
110001
rs1
i=1
simm13
128
MATRA MHS Rev. A (10/09/96)
SPARC V7.0
WRTBR
Operation: Assembler Syntax: Description: TBR
Write Trap Base Register (Privileged Instruction)
r[rs1] XOR (r[rs2] or sign extnd(simm13))
WRTBR
wr regrs1 , reg_or_imm, %tbr WRTBR does a bitwise logical XOR of the contents of register r[rs1] with either the contents of r[rs2] (if bit field i=0) or the 13-bit sign-extended immediate value contained in the instruction (if bit field i=1). The result is written into the Trap Base Address field of the TBR. WRTBR is a delayed write instruction: 1. If any of the three instructions following a WRTBR causes a trap, the TBA used may be ei ther the old or the new value. 2. If any of the three instructions after a WRTBR is trapped, a subsequent RDTBR in the trap handler will get the register's new TBA value.
Traps: Format:
privileged_instruction (if S=0)
31 30 29
25 24
19 18
14
13
12
54
0
10
ignored
110011
19 18
rs1
14
i=0
13 12
ignored
rs2
0
31 30 29
25 24
10
ignored
110011
rs1
i=1
simm13
MATRA MHS Rev. A (10/09/96)
129
SPARC V7.0
WRWIM
Operation: Assembler Syntax: Description: WIM
Write Window Invalid Mask register (Privileged Instruction)
r[rs1] XOR (r[rs2] or sign extnd(simm13))
WRWIM
wr regrs1 , reg_or_imm, %wim WRWIM does a bitwise logical XOR of the contents of register r[rs1] with either the contents of r[rs2] (if bit field i=0) or the 13-bit, sign-extended immediate value contained in the instruction (if bit field i=1). The result is written into the writable bits of the WIM register. WRWIM is a delayed write instruction: 1. If any of the three instructions following a WRWIM is a SAVE, RESTORE, or RETT, the occurrence of window_overflow and window_underflow is unpredictable. 2. If any of the three instructions after a WRWIM instruction reads the modified WIM, the value read is unpredictable. 3. If any of the three instructions after a WRWIM is trapped, a subsequent RDWIM in the trap handler will get the register's new value.
Traps: Format:
privileged_instruction (if S=0)
31 30 29
25 24
19 18
14
13
12
54
0
10
ignored
110010
19 18
rs1
14
i=0
13 12
ignored
rs2
0
31 30 29
25 24
10
ignored
110010
rs1
i=1
simm13
130
MATRA MHS Rev. A (10/09/96)
SPARC V7.0
WRY
Operation: Assembler Syntax: Description: Y wr regrs1 , reg_or_imm, %y
Write Y register
r[rs1] XOR (r[rs2] or sign extnd(simm13))
WRY
WRY does a bitwise logical XOR of the contents of register r[rs1] with either the contents of r[rs2] (if bit field i=0) or the 13-bit, sign-extended immediate value contained in the instruction (if bit field i=1). The result is written into the Y register. WRY is a delayed write instruction: 1. If any of the three instructions following a WRY is a MULScc or a RDY, the value of Y used is unpredictable. 2. If any of the three instructions after a WRY instruction reads the modified Y register, the value read is unpredictable. 3. If any of the three instructions after a WRY is trapped, a subsequent RDY in the trap han dler will get the register's new value.
Traps: Format:
none
31 30 29
25 24
19 18
14
13
12
54
0
10
ignored
110000
19 18
rs1
14
i=0
13 12
ignored
rs2
0
31 30 29
25 24
10
ignored
110000
rs1
i=1
simm13
MATRA MHS Rev. A (10/09/96)
131
SPARC V7.0
XNOR
Operation: Assembler Syntax: Description: r[rd] xnor regrs1 , reg_or_imm, regrd
Exclusive-Nor
r[rs1] XOR not(r[rs2] or sign extnd(simm13))
XNOR
This instruction does a bitwise logical XOR of the contents of register r[rs1] with the one's complement of either the contents of r[rs2] (if bit field i=0) or the 13-bit sign-extended immediate value contained in the instruction (if bit field i=1). The result is stored in register r[rd]. none
Traps: Format:
31 30 29
25 24
19 18
14
13
12
54
0
10
31 30 29
rd
000111
25 24 19 18
rs1
14
i=0
13 12
ignored
rs2
0
10
rd
000111
rs1
i=1
simm13
132
MATRA MHS Rev. A (10/09/96)
SPARC V7.0
XNORcc
Operation: r[rd] n z v c Assembler Syntax: Description: r[rd]<31>
Exclusive-Nor and modify icc
r[rs1] XOR not(r[rs2] or sign extnd(simm13)) if r[rd] =0 then 1, else 0 0 0
XNORcc
xnorcc regrs1 , reg_or_imm, regrd This instruction does a bitwise logical XOR of the contents of register r[rs1] with the one's complement of either the contents of r[rs2] (if bit field i=0) or the 13-bit, sign-extended immediate value contained in the instruction (if bit field i=1). The result is stored in register r[rd]. XNORcc also modifies all the integer condition codes in the manner described above. none
Traps: Format:
31 30 29
25 24
19 18
14
13
12
54
0
10
31 30 29
rd
010111
25 24 19 18
rs1
14
i=0
13 12
ignored
rs2
0
10
rd
010111
rs1
i=1
simm13
MATRA MHS Rev. A (10/09/96)
133
SPARC V7.0
XOR
Operation: Assembler Syntax: Description: r[rd] xor regrs1 , reg_or_imm, regrd
Exclusive-Or
r[rs1] XOR (r[rs2] or sign extnd(simm13))
XOR
This instruction does a bitwise logical XOR of the contents of register r[rs1] with either the contents of r[rs2] (if bit field i=0) or the 13-bit, sign-extended immediate value contained in the instruction (if bit field i=1). The result is stored in register r[rd]. none
Traps: Format:
31 30 29
25 24
19 18
14
13
12
54
0
10
31 30 29
rd
000011
25 24 19 18
rs1
14
i=0
13 12
ignored
rs2
0
10
rd
000011
rs1
i=1
simm13
134
MATRA MHS Rev. A (10/09/96)
SPARC V7.0
XORcc
Operation: r[rd] n z v c Assembler Syntax: Description: r[rd]<31>
Exclusive-Or and modify icc
r[rs1] XOR (r[rs2] or sign extnd(simm13)) if r[rd] =0 then 1, else 0 0 0
XORcc
xorcc regrs1 , reg_or_imm, regrd This instruction does a bitwise logical XOR of the contents of register r[rs1] with either the contents of r[rs2] (if bit field i=0) or the 13-bit, sign-extended immediate value contained in the instruction (if bit field i=1). The result is stored in register r[rd]. XORcc also modifies all the integer condition codes in the manner described above. none
Traps: Format:
31 30 29
25 24
19 18
14
13
12
54
0
10
31 30 29
rd
010011
25 24 19 18
rs1
14
i=0
13 12
ignored
rs2
0
10
rd
010011
rs1
i=1
simm13
MATRA MHS Rev. A (10/09/96)
135

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