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TM8SK64JPN 8388608 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULE -- SODIMM
SMMS717 - JULY 1998
D D D D D D D D
Organization: - TM8SK64JPN . . . 8 388 608 x 64 Bits Single 3.3-V Power Supply (10% Tolerance) Designed for 66-MHz 4-Clock Systems JEDEC 144-Pin Small Outline Dual-In-Line Memory Module (SODIMM) Without Buffer for Use With Socket Uses Eight 64M-Bit Synchronous Dynamic RAMs (SDRAMs) (8M x 8-Bit) in Plastic Thin Small-Outline Packages (TSOPs) Byte-Read/Write Capability Performance Ranges: High-Speed, Low-Noise, Low-Voltage TTL (LVTTL) Interface
D D D D D D D D
Read Latencies 2 and 3 Supported Support Burst-Interleave and Burst-Interrupt Operations Burst Length Programmable to 1, 2, 4, and 8 Four Banks for On-Chip Interleaving (Gapless Access) Ambient Temperature Range 0C to 70C Gold-Plated Contacts Pipeline Architecture Serial Presence Detect (SPD) Using EEPROM
SYNCHRONOUS CLOCK CYCLE TIME tCK3 tCK2 '8SK64JPN-10 10 ns 15 ns
ACCESS TIME CLOCK TO OUTPUT tAC3 tAC2 7.5 ns 7.5 ns
REFRESH INTERVAL tREF 64 ms
description
The TM8SK64JPN is a 64M-byte, 144-pin SODIMM. The SODIMM is composed of eight TMS664814DGE, 8 388 608 x 8-bit SDRAMs, each in a 400-mil, 54-pin plastic thin small-outline package (TSOP) mounted on a substrate with decoupling capacitors. See the TMS664814 data sheet (literature number SMOS695).
operation
The TM8SK64JPN operates as eight TMS664814DGE devices that are connected as shown in the functional block diagram.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright (c) 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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TM8SK64JPN 8388608 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULE -- SODIMM
SMMS717 - JULY 1998
DUAL-IN-LINE MEMORY MODULE ( TOP VIEW )
TM8SK64JPN ( SIDE VIEW ) A[0:11] A[0:8] A13/BA0 A12/BA1 CAS CKE0 CK[0:1] DQ[0:63] DQMB[0:7] NC RAS S0 SCL SDA VDD VSS WE
PIN NOMENCLATURE Row-Address Inputs Column-Address Inputs Bank Select Zero Bank Select One Column-Address Strobe Clock Enable System Clock Data In / Data Out Data in/Data Out Mask Enable No Connect Row-Address Strobe Chip Select SPD Clock SPD Address / Data 3.3-V Supply Ground Write Enable
1
59
61
144
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TM8SK64JPN 8388608 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULE -- SODIMM
SMMS717 - JULY 1998
Pin Assignments
PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 NAME VSS VSS DQ0 DQ32 DQ1 DQ33 DQ2 DQ34 DQ3 DQ35 VDD VDD DQ4 DQ36 DQ5 DQ37 DQ6 DQ38 DQ7 DQ39 VSS VSS DQMB0 DQMB4 DQMB1 DQMB5 VDD VDD A0 A3 A1 A4 A2 A5 VSS VSS NO. 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 PIN NAME DQ8 DQ40 DQ9 DQ41 DQ10 DQ42 DQ11 DQ43 VDD VDD DQ12 DQ44 DQ13 DQ45 DQ14 DQ46 DQ15 DQ47 VSS VSS NC NC NC NC CK0 CKE0 VDD VDD RAS CAS WE NC S0 NC NC NC NO. 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 PIN NAME NC CK1 VSS VSS NC NC NC NC VDD VDD DQ16 DQ48 DQ17 DQ49 DQ18 DQ50 DQ19 DQ51 VSS VSS DQ20 DQ52 DQ21 DQ53 DQ22 DQ54 DQ23 DQ55 VDD VDD A6 A7 A8 A13/BA0 VSS VSS NO. 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 PIN NAME A9 A12/BA1 A10 A11 VDD VDD DQMB2 DQMB6 DQMB3 DQMB7 VSS VSS DQ24 DQ56 DQ25 DQ57 DQ26 DQ58 DQ27 DQ59 VDD VDD DQ28 DQ60 DQ29 DQ61 DQ30 DQ62 DQ31 DQ63 VSS VSS SDA SCL VDD VDD
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TM8SK64JPN 8388608 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULE -- SODIMM
SMMS717 - JULY 1998
small-outline dual-in-line memory module and components
The small-outline dual-in-line memory module and components include:
D D D
PC substrate: 1,10 0,1 mm (0.04 inch) nominal thickness Bypass capacitors: Multilayer ceramic Contact area: Nickel plate and gold plate over copper
functional block diagram
S0 RC CS CS CK: U0, UB0 CK0 UB0 CK1 RC CK: U1, UB1 DQMB0 R DQ[0:7] 8 DQM DQ[0:7] U0 DQMB4 R DQ[32:39] 8 DQM DQ[0:7] RC CK: U2, UB2 RC CK: U3, UB3
CS
CS R = 10
DQMB1 R DQ[8:15] 8
DQM DQ[0:7]
U1
DQMB5 R DQ[40:47] 8
DQM DQ[0:7]
UB1
RC = 10
CS
CS VDD U[0:3], UB[0:3] Two 0.22 F and one 0.01 F per SDRAM U[0:3], UB[0:3]
DQMB2 R DQ[16:23] 8
DQM DQ[0:7]
U2
DQMB6 R DQ[48:55] 8
DQM DQ[0:7]
UB2
VSS
CS
CS
DQMB3 DQ[24:31] R 8
DQM DQ[0:7]
U3
DQMB7 R DQ[56:63] 8
DQM DQ[0:7]
UB3
RAS CAS WE CKE0 A[0:13]
RAS: SDRAM U[0:3], UB[0:3] CAS: SDRAM U[0:3], UB[0:3] WE: SDRAM U[0:3], UB[0:3] CKE: SDRAM U[0:3], UB[0:3] A[0:13]: SDRAM U[0:3], UB[0:3] LEGEND: CS = SPD =
SPD EEPROM SCL A0 A1 A2 SDA
VSS Chip select Serial Presence Detect
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TM8SK64JPN 8388608 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULE -- SODIMM
SMMS717 - JULY 1998
absolute maximum ratings over operating ambient temperature range (unless otherwise noted)
Supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 4.6 V Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 W Operating ambient temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 55C to 125C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
MIN VDD VSS VIH VIH-SPD VIL TA Supply voltage Supply voltage High-level input voltage High-level input voltage for SPD device Low-level input voltage Operating ambient temperature 2 2 -0.3 0 3 NOM 3.3 0 VDD + 0.3 5.5 0.8 70 MAX 3.6 UNIT V V V V V C
capacitance over recommended ranges of supply voltage and ambient temperature, f = 1 MHz (see Note 2)
PARAMETER Ci(CK) Ci(AC) Ci(CKE) Co Ci(DQMBx) Ci(Sx) Ci/o(SDA) Input capacitance, CK input Input capacitance, address and control inputs: A0 - A13, RAS, CAS, WE Input capacitance, CKE input Output capacitance Input capacitance, DQMBx input Input capacitance, Sx input Input/output capacitance, SDA input 4 2.5 2.5 MIN 2.5 2.5 MAX 4 5 5 6.5 5 5 9 7 UNIT pF pF pF pF pF pF pF pF
Ci(SPD) Input capacitance, SPD inputs (except SDA) Specifications in this table represent a single SDRAM device. NOTE 2: VDD = 3.3 V 0.3 V. Bias on pins under test is 0 V.
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TM8SK64JPN 8388608 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULE -- SODIMM
SMMS717 - JULY 1998
electrical characteristics over recommended ranges of supply voltage and ambient temperature (unless otherwise noted) (see Note 3)
PARAMETER VOH VOL II IO High-level output voltage Low-level output voltage Input current (leakage) Output current (leakage) IOH = - 2 mA IOL = 2 mA 0 V < VI < VDD + 0.3 V, All other pins = 0 V to VDD 0 V < VO < VDD + 0.3 V, Output disabled Burst length = 1, tRC tRC MIN IOH/IOL = 0 mA, (see Notes 4, 5, and 6) CAS latency = 2 CAS latency = 3 TEST CONDITIONS MIN 2.4 0.4 MAX UNIT V V A A mA mA mA mA mA mA mA mA mA mA mA mA mA mA
"10 "10
105 115 1 1 40 5 8 8 60 10 140 200 1 50 150
ICC1 ICC2P ICC2PS ICC2N ICC2NS ICC3P ICC3PS ICC3N ICC3NS
Operating current
Precharge standby current in power down mode power-down Precharge standby current in nonpower-down g y mode
CKE VIL MAX, tCK = 15 ns (see Note 7) CKE and CK VIL MAX, tCK = (see Note 8) CKE VIH MIN, tCK = 15 ns (see Note 7) tCK = (see Note 8) CKE VIL MAX, tCK = 15 ns (see Notes 4 and 7) CKE and CK VIL MAX, tCK = (see Notes 4 and 8) CKE VIH MIN, tCK = 15 ns (see Notes 4 and 7) CKE VIH MIN, CK VIL MAX, tCK = (see Notes 4 and 8) Page burst, IOH/IOL = 0 mA CAS latency = 2 All banks activated, , nCCD = one cycle CAS latency = 3 (see Notes 9 and 10) tRC tRC MIN (see Notes 5 and 8) CAS latency = 2 CAS latency = 3
Active standby current in power-down mode
Active standby current in nonpower-down mode
ICC4
Burst current
ICC5
Autorefresh current
ICC6 Self-refresh current CKE VIL MAX 2 mA Specifications in this table represent a single SDRAM device. NOTES: 3. All specifications apply to the device after power-up initialization. All control and address inputs must be stable and valid. 4. Only one bank is activated. 5. tRC tRC MIN 6. Control and address inputs change state twice during tRC. 7. Control and address inputs change state once every 30 ns. 8. Control and address inputs do not change state (stable). 9. Control and address inputs change state once every cycle. 10. Continuous burst access, nCCD = 1 cycle
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TM8SK64JPN 8388608 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULE -- SODIMM
SMMS717 - JULY 1998
ac timing requirements
MIN tCK2 tCK3 tCH tCL tAC2 tAC3 tOH tLZ tHZ tIS tIH tCESP tRAS tRC tRCD tRP tRRD tRSA tAPR Cycle time, CK Cycle time, CK Pulse duration, CK high Pulse duration, CK low Access time, CK high to data out (see Note 11) Access time, CK high to data out (see Note 11) Hold time, CK high to data out Delay time, CK high to DQ in low-impedance state (see Note 12) Delay time, CK high to DQ in high-impedance state (see Note 13) Setup time, address, control, and data input Hold time, address, control, and data input time address control Power down/self-refresh exit time Delay time, ACTV command to DEAC or DCAB command Delay time, ACTV, MRS, REFR, or SLFR to ACTV, MRS, REFR, or SLFR command Delay time ACTV command to READ, READ-P, WRT, or WRT-P command (see Note 14) Delay time, DEAC or DCAB command to ACTV, MRS, REFR, or SLFR command Delay time, ACTV command in one bank to ACTV command in the other bank Delay time, MRS command to ACTV, MRS, REFR, or SLFR command 2 1 10 50 80 30 30 20 20 100000 CAS latency = 2 CAS latency = 3 3 2 10 CAS latency = 2 CAS latency = 3 15 10 3 3 7.5 7.5 MAX UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Final data out of READ-P operation to ACTV, MRS, SLFR, or REFR command tRP - (CL-1)* tCK ns tAPW Final data in of WRT-P operation to ACTV, MRS, SLFR, or REFR command tRP + 1 tCK ns tT Transition time 1 5 ms All references are made to the rising transition of CK unless otherwise noted. Specifications in this table represent a single SDRAM device. NOTES: 11. tAC is referenced from the rising transition of CK that precedes the data-out cycle. For example, the first data out tAC is referenced from the rising transition of CK that is read latency (one cycle after the READ command). Access time is measured at output reference level 1.4 V. 12. tLZ is measured from the rising transition of CK that is read latency (one cycle after the READ command). 13. tHZ (max) defines the time at which the outputs are no longer driven and is not referenced to output voltage levels. 14. For read or write operations with automatic deactivate, tRCD must be set to satisfy minimum tRAS.
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TM8SK64JPN 8388608 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULE -- SODIMM
SMMS717 - JULY 1998
clock timing requirements
MIN tREF nCCD nCDD nCLE nCWL nDID nDOD nHZP2 nHZP3 nWCD Refresh interval Delay time, READ or WRT command to an interrupting command Delay time, CS low or high to input enabled or inhibited Delay time, CKE high or low to CLK enabled or disabled Delay time, final data in of WRT operation to READ, READ-P, WRT, or WRT-P Delay time, ENBL or MASK command to enabled or masked data in Delay time, ENBL or MASK command to enabled or masked data out Delay time, DEAC or DCAB, command to DQ in high-impedance state Delay time, DEAC or DCAB, command to DQ in high-impedance state Delay time, WRT command to first data in CAS latency = 2 CAS latency = 3 0 1 0 1 1 0 2 0 2 2 3 0 1 MAX 64 UNIT ms cycles cycles cycles cycles cycles cycles cycles cycles cycles
nWR Delay time, final data in of WRT operation to DEAC or DCAB command 1 cycle All references are made to the rising transition of CK unless otherwise noted. A CK cycle can be considered as contributing to a timing requirement for those parameters defined in cycle units only when not gated by CKE (those CK cycles occurring during the time when CKE is asserted low).
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SMMS717 - JULY 1998
serial presence detect
The serial presence detect (SPD) is contained in a 2K-bit serial EEPROM located on the module. The SPD nonvolatile EEPROM contains various data such as module configuration, SDRAM organization, and timing parameters (see Table 1). Only the first 128 bytes are programmed by Texas Instruments, while the remaining 128 bytes are available for customer use. Programming is done through an IIC bus using the clock (SCL) and data (SDA) signals. All Texas Instruments modules comply with the current JEDEC SPD standards. See the Texas Instruments Serial Presence Detect Technical Reference (literature number SMMU001) for further details. Table 1 lists the SPD contents. Table 1. Serial Presence Detect Data
BYTE NO. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 DESCRIPTION OF FUNCTION Defines number of bytes written into serial memory during module manufacturing Total number of bytes of SPD memory device Fundamental memory type (FPM, EDO, SDRAM, . . .) Number of row addresses on this assembly Number of column addresses on this assembly Number of module rows on this assembly Data width of this assembly Data width continuation Voltage interface standard of this assembly SDRAM cycle time at maximum supported CAS latency (CL), CL = X SDRAM access from clock at CL = X SODIMM configuration type (non-parity, parity, error correcting code [ECC]) Refresh rate / type SDRAM width, primary DRAM Error-checking SDRAM data width Minimum clock delay, back-to-back random column addresses Burst lengths supported Number of banks on each SDRAM device CAS latencies supported CS latency Write latency SDRAM module attributes LVTTL tCK = 10 ns tAC = 7.5 ns Non-Parity 15.6 s/ self-refresh x8 N/A 1 CK cycle 1, 2, 4, and 8 4 banks 2, 3 0 0 Non-buffered/ Non-registered VDD tolerance = ("10%) Burst read / write, precharge all, auto precharge tCK = 15 ns ITEM 128 bytes 256 bytes SDRAM 12 9 1 bank 64 bits DATA 80h 08h 04h 0Ch 09h 01h 40h 00h 01h A0h 75h 00h 80h 08h 00h 01h 0Fh 04h 06h 01h 01h 00h
22
SDRAM device attributes: general
0Eh
23
Minimum clock cycle time at CL = X - 1
F0h
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TM8SK64JPN 8388608 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULE -- SODIMM
SMMS717 - JULY 1998
serial presence detect (continued)
Table 1. Serial Presence Detect Data (Continued)
BYTE NO. 24 25 26 27 28 29 30 31 32 33 34 35 - 61 62 63 64 - 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 - 90 91 92 93 - 94 95 - 98 99 - 125 126 127 128-166 DESCRIPTION OF FUNCTION Maximum data-access time from clock at CL = X - 1 Minimum clock cycle time at CL = X - 2 Maximum data-access time from clock at CL = X - 2 Minimum row-precharge time Minimum row-active to row-active delay Minimum RAS-to-CAS delay Minimum RAS pulse width Command and address signal input setup time Command and address signal input hold time Data signal input setup time Data signal input hold time Superset features (may be used in the future) SPD revision Checksum for byte 0 - 62 Manufacturer's JEDEC ID code per JEP - 106E Manufacturing location Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Die revision code PCB revision code Manufacturing date Assembly serial number Manufacturer-specific data Clock frequency SDRAM component and clock interconnection details System integrator's specific data Rev. 1.2 14 97 TBD T M 8 S K 6 4 J P N 1 0 SPACE TBD TBD TBD TBD TBD 66 MHz 199 TBD 66h C7h 54h 4Dh 38h 53h 4Bh 36h 34h 4Ah 50h 4Eh 2Dh 31h 30h 20h 12h 0Eh 9700...00h ITEM tAC = 7.5 ns N/A N/A tRP = 30 ns tRRD = 20 ns tRCD = 30 ns tRAS =50 ns tIS = 2 ns tIH = 1 ns tIS = 2 ns tIH = 1 ns DATA 75h 00h 00h 1Eh 14h 1Eh 32h 20h 10h 20h 10h
167-255 Open TBD indicates values are determined at manufacturing time and are module dependent. These TBD values are determined and programmed by the customer (optional).
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SMMS717 - JULY 1998
device symbolization (TM8SK64JPN)
TM8SK64JPN
-SS
YYMMT
YY MM T -SS
= = = =
Year Code Month Code Assembly Site Code Speed Code
NOTE A: Location of symbolization may vary.
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TM8SK64JPN 8388608 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULE -- SODIMM
SMMS717 - JULY 1998
MECHANICAL DATA
BDQ (R-SODIMM-N144)
2.665 (67,69) 2.655 (67,44) Notch 0.157 (4,00) x 0.079 (2,00) Deep 2 Places Notch 0.060 (1,52) x 0.158 (4,01) Deep 0.044 (1,12) 0.036 (0,91)
SMALL OUTLINE DUAL IN-LINE MEMORY MODULE
0.024 (0,61) TYP 0.098 (2,49) 0.196 (4,98)
0.031 (0,79)
0.010 (0,25) MAX 0.788 (20,00) TYP 1.130 (28,70) 1.120 (28,45) 0.157 (4,00) 0.126 (3,20) 0.095 (2,41) MAX 0.150 (3,81) MAX (For Double-Sided Module Only) 4088188/A 07/97
NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MO-190
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Copyright (c) 1998, Texas Instruments Incorporated

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