View SMMS693A_1003920.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

TM4EJ64KPU, TM4EJ64NPU, TM4FJ64KPU, TM4FJ64NPU, 4194304 BY 64-BIT TM8EJ64KPU, TM8EJ64NPU, TM8FJ64KPU, TM8FJ64NPU, 8388608 BY 64-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES -- SODIMM
SMMS693A - AUGUST 1997 - REVISED NOVEMBER 1997
D D D D D D D D D
description
The TM4xJ64KPU is a 32M-byte, 144-pin, small-outline dual-in-line memory module (SODIMM). The SODIMM is composed of four TMS465169/P, 4 194 304 x 16-bit 4K normal or low-power battery-backup refresh EDO dynamic random-access memory (DRAM) devices, each in a 400-mil, 50-pin plastic thin small-outline package (TSOP) (DGE suffix) package mounted on a substrate with decoupling capacitors. See the TMS465169/P data sheet (literature number SMHS566). The TM4xJ64NPU is a 32M-byte, 144-pin SODIMM. The SODIMM is composed of four TMS464169/P, 4 194 304 x 16-bit 8K normal or low-power battery-backup refresh EDO DRAMs, each in a 400-mil, 50-pin plastic TSOP (DGE suffix) mounted on a substrate with decoupling capacitors. See the TMS464169/P data sheet (literature number SMHS566). The TM8xJ64KPU is a 64M-byte, 144-pin SODIMM. The SODIMM is composed of eight TMS465169/P, 4 194 304 x 16-bit 4K normal or low-power battery-backup refresh EDO DRAMs, each in a 400-mil, 50-pin plastic TSOP (DGE suffix) mounted on a substrate with decoupling capacitors. The TM8xJ64NPU is a 64M-byte, 144-pin SODIMM. The SODIMM is composed of eight TMS464169/P, 4 194 304 x 16-bit 8K normal or low-power battery-backup refresh EDO DRAMs, each in a 400-mil, 50-pin plastic TSOP (DGE suffix) mounted on a substrate with decoupling capacitors.
operation
The TM4xJ64xPU operates as four TMS46x169/Ps that are connected as shown in the TMxxJ64xPU functional block diagram. The TM8xJ64xPU operates as eight TMS46x169/Ps that are connected as shown in the TMxxJ64xPU functional block diagram.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright (c) 1997, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
1
PRODUCT PREVIEW
Organization - TM4xJ64xPU-xx . . . 4 194304 x 64 Bits - TM8xJ64xPU-xx . . . 8 388608 x 64 Bits Single 3.3-V Power Supply (10% Tolerance) JEDEC 144-Pin Small-Outline Dual-In-Line Memory Module (SODIMM) Without Buffer for Use With Socket TM4xJ64xPU-xx -- Utilizes Four 64M-Bit High-Speed (4M x 16-Bit) Dynamic RAMs TM4xJ64xPU-xx -- Utilizes Eight 64M-Bit High-Speed (4M x 16-Bit) Dynamic RAMs High-Speed, Low-Noise LVTTL Interface High-Reliability 50-Lead 400-Mil-Wide Surface-Mount Thin Small-Outline Package (TSOP) (DGE Suffix) 3-State Output Gold-Plated Contacts
D
D D D D
Long Refresh Periods: - TMxEJ64KPU: 64 ms (4 096 Cycles) - TMxEJ64NPU: 64 ms (8 192 Cycles) - TMxFJ64KPU: 128 ms (4 096 Cycles) - TMxFJ64NPU: 128 ms (8 192 Cycles) Extended Data Out (EDO) Operation With CAS-Before-RAS (CBR), RAS-Only, and Hidden Refresh Serial Presence-Detect (SPD) Using EEPROM Ambient Temperature Range 0C to 70C Performance Ranges
ACCESS TIME tRAC (MAX) 40 ns 50 ns 60 ns ACCESS ACCESS EDO TIME TIME CYCLE tCAC tAA tHPC (MAX) (MAX) (MIN) 11 ns 20 ns 16 ns 13 ns 25 ns 20 ns 15 ns 30 ns 25 ns
'xxJ64xPU-40 'xxJ64xPU-50 'xxJ64xPU-60
TM4EJ64KPU, TM4EJ64NPU, TM4FJ64KPU, TM4FJ64NPU, 4194304 BY 64-BIT TM8EJ64KPU, TM8EJ64NPU, TM8FJ64KPU, TM8FJ64NPU, 8388608 BY 64-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES -- SODIMM
SMMS693A - AUGUST 1997 - REVISED NOVEMBER 1997
DUAL-IN-LINE MEMORY MODULE ( TOP VIEW )
TM4xJ64xPU ( SIDE VIEW )
TM8xJ64xPU ( SIDE VIEW )
PIN NOMENCLATURE - TMxxJ64KPU A[0:11] A[0:9] DQ[0:63] CAS[0:7] RAS0 and RAS1 WE0 OE0 SDA SCL NC VDD VSS Row Address Inputs Column Address Inputs Data In / Data Out Column-Address Strobe Row-Address Strobe Write Enable Output Enable Serial PD Address / Data Serial PD Clock No-Connect Pin 3.3-V Supply Ground
1
PIN NOMENCLATURE - TMxxJ64NPU A[0:12] A[0:8] DQ[0:63] CAS[0:7] RAS0 and RAS1 WE0 OE0 SDA SCL NC VDD VSS Row Address Inputs Column Address Inputs Data In / Data Out Column-Address Strobe Row-Address Strobe Write Enable Output Enable Serial PD Address / Data Serial PD Clock No-Connect Pin 3.3-V Supply Ground
59
PRODUCT PREVIEW
61
143
2
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
AAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAA A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A A AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A A AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A A AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AA A A A A A A AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AA A AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAAAAAAAAA A AA AA A A AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAA
NO. 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 10 11 9 8 7 6 5 4 3 2 1
TM4EJ64KPU, TM4EJ64NPU, TM4FJ64KPU, TM4FJ64NPU, 4194304 BY 64-BIT TM8EJ64KPU, TM8EJ64NPU, TM8FJ64KPU, TM8FJ64NPU, 8388608 BY 64-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES -- SODIMM
PIN
NAME
DQ36
DQ35
DQ34
DQ33
DQ32
VDD VDD
DQ4
DQ3
DQ2
DQ1
DQ0
VSS VSS
NO.
50
49
48
47
46
45
44
43
42
41
40
39
38
37
PIN NAME
Pin Assignments
DQ45
DQ13
DQ44
DQ12
DQ43
DQ42
DQ10
DQ41
DQ40
DQ11
VDD VDD
DQ9
DQ8
NO.
86
85
84
83
82
81
80
79
78
77
76
75
74
73
PIN NAME
DQ49
DQ17
DQ48
DQ16
SMMS693A - AUGUST 1997 - REVISED NOVEMBER 1997
VDD VDD
VSS VSS
OE0
NC
NC
NC
NC
NC
NO.
122
121AAAAAA DQ24
120
109
119
118
117
116
115
114
113
112AAAAAA NC
110
111
PIN NAME
DQ56
CAS7
CAS3
CAS6
CAS2
VDD VDD
VSS VSS
A10
A12
A9
PRODUCT PREVIEW
CAS5
CAS1
CAS4
CAS0
DQ39
DQ38
DQ37
VDD VDD
DQ7
DQ6
DQ5
VSS VSS
VSS VSS
A5
A2
A4
A1
A3
A0
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
POST OFFICE BOX 1443
RAS1
RAS0
DQ47
DQ15
DQ46
DQ14
WE0
VDD VDD
VSS VSS
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
* HOUSTON, TEXAS 77251-1443
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 DQ55 DQ23 DQ54 DQ22 DQ53 DQ21 DQ52 DQ20 DQ51 DQ19 DQ50 DQ18 VDD VDD VSS VSS VSS VSS A11 A8 A7 A6 144 143 142 141 140 139 138AAAAAA DQ63 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 DQ31 DQ62 DQ30 DQ61 DQ29 DQ60 DQ28 DQ59 DQ27 DQ58 DQ26 DQ57 DQ25 VDD VDD VDD VDD SDA VSS VSS SCL
3
TM4EJ64KPU, TM4EJ64NPU, TM4FJ64KPU, TM4FJ64NPU, 4194304 BY 64-BIT TM8EJ64KPU, TM8EJ64NPU, TM8FJ64KPU, TM8FJ64NPU, 8388608 BY 64-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES -- SODIMM
SMMS693A - AUGUST 1997 - REVISED NOVEMBER 1997
small-outline dual-in-line memory module and components
The small-outline dual-in-line memory module and components include:
D D D
PC substrate: 1,10
" 0,1 mm (0.04 inch) nominal thickness
Bypass capacitors: Multilayer ceramic Contact area: Nickel plate and gold plate over copper
The following table shows the SODIMM modules and devices (Ux/UBx) that are used. Table 1. Component Table
MODULE TM4xJ64xPU TM8xJ64xPU DEVICES USED U[0:3] U[0:3], UB[0:3]
functional block diagram for the TMxxJ64xPU
RAS0 WE0 OE0 CS W RAS LCAS DQ[0:7] U0 CAS1 DQ[8:15] UCAS DQ[8:15] RAS1
PRODUCT PREVIEW
CAS0 DQ[0:7]
CS W RAS LCAS DQ[0:7] UB0 UCAS DQ[8:15]
CAS2 DQ[16:23]
CS W RAS LCAS DQ[0:7] U1
CS W RAS LCAS DQ[0:7] UB1 UCAS DQ[8:15]
CAS3 DQ[24:31]
UCAS DQ[8:15]
CAS4 DQ[32:39]
CS W RAS LCAS DQ[0:7] U2
CS W RAS LCAS DQ[0:7] UB2 UCAS DQ[8:15] SCL A0 A1 VSS A[0:12] A[0:12] U[0:3], UB[0:3] A2 SPD EEPROM SDA
CAS5 DQ[40:47]
UCAS DQ[8:15]
CAS6 DQ[48:55]
CS W RAS LCAS DQ[0:7] U3
CS W RAS LCAS DQ[0:7] UB3 UCAS DQ[8:15]
CAS7 DQ[56:63]
UCAS DQ[8:15]
LEGEND: SPD = Serial Presence Detect CS = Chip Select
A12 is not used in TM4xJ64KPU, TM8xP64KPU
4
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
TM4EJ64KPU, TM4EJ64NPU, TM4FJ64KPU, TM4FJ64NPU, 4194304 BY 64-BIT TM8EJ64KPU, TM8EJ64NPU, TM8FJ64KPU, TM8FJ64NPU, 8388608 BY 64-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES -- SODIMM
SMMS693A - AUGUST 1997 - REVISED NOVEMBER 1997
absolute maximum ratings over ambient temperature range (unless otherwise noted)
Supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 4.6 V Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Power dissipation: TM4xJ64xPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 W TM8xJ64xPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 W Ambient temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 55C to 125C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS.
VIL TA
Low-level input voltage Ambient temperature
- 0.3 0
0.8 70
V
C
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
5
PRODUCT PREVIEW
AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA
MIN 3 2 NOM MAX UNIT V V V V VDD VSS Supply voltage Supply voltage 3.3 0 3.6 VIH VIH-SPD High-level input voltage High-level input voltage for the SPD device 2AAA VDD + 0.3 5.5
recommended operating conditions
TM4EJ64KPU, TM4EJ64NPU, TM4FJ64KPU, TM4FJ64NPU, 4194304 BY 64-BIT TM8EJ64KPU, TM8EJ64NPU, TM8FJ64KPU, TM8FJ64NPU, 8388608 BY 64-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES -- SODIMM
SMMS693A - AUGUST 1997 - REVISED NOVEMBER 1997
electrical characteristics over recommended ranges of supply voltage and ambient temperature (unless otherwise noted) TM4xJ64KPU
PARAMETER High-level output voltage Low-level output voltage Input current (leakage) Output current (leakage) Average read- or write-cycle current TEST CONDITIONS IOH = - 2 mA IOH = - 100 A IOL = 2 mA IOL = 100 A LVTTL LVCMOS LVTTL LVCMOS '4xJ64KPU - 40 MIN 2.4 VDD - 0.2 0.4 0.2 10 10 MAX '4xJ64KPU -50 MIN 2.4 VDD - 0.2 0.4 0.2 10 10 MAX '4xJ64KPU - 60 MIN 2.4 V VDD - 0.2 0.4 V 0.2 10 10 A A MAX UNIT
VOH
VOL II IO
VDD = 3.6 V, VI = 0 V to 3.9 V, All others = 0 V to VDD VDD = 3.6 V, CASx high VO = 0 V to VDD,
PRODUCT PREVIEW
ICC1
VDD = 3.6 V,
Minimum cycle
640
520
440
mA
ICC2
Average g standby current
VIH = 2 V LVTTL), After one memory cycle, RASx and CASx high VIH = VDD - 0.2 V (LVCMOS), ( ), After one memory cycle, RASx and CASx high '4EJ64KPU '4FJ64KPU
4
4
4
mA
2 .6
2 .6
2 mA .6
ICC3
RASx-only refresh, average refresh curren Average EDO current Average CBR refresh current Average self-refresh current Average battery back-up operating current, CBR only
VDD = 3.6 V, RASx cycling,
Minimum cycle, CASx high
640
520
440
mA
ICC4 ICC5
VDD = 3.6 V, RASx low,
tHPC = MIN, CASx cycling
600
480
400
mA
VDD = 3.6 V, Minimum cycle, RASx low after CASx low CASx < 0.2 V, RASx < 0.2 V, Measured after tRASS min tRC = 31.25 s, tRAS 300 ns, VDD - 0.2 V VIH 3.9 V, 0 V VIL 0.2 V, WE0 and OE0 = VIH, Address and data stable
640
520
440
mA
ICC6#
1.2
1.2
1.2
mA
ICC10#
1.6
1.6
1.6
mA
For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements. Measured with outputs open Measured with a maximum of one address change while RASx = VIL Measured with a maximum of one address change during each EDO cycle, tHPC # For TM4FJ64KPU only
6
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
TM4EJ64KPU, TM4EJ64NPU, TM4FJ64KPU, TM4FJ64NPU, 4194304 BY 64-BIT TM8EJ64KPU, TM8EJ64NPU, TM8FJ64KPU, TM8FJ64NPU, 8388608 BY 64-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES -- SODIMM
SMMS693A - AUGUST 1997 - REVISED NOVEMBER 1997
electrical characteristics over recommended ranges of supply voltage and ambient temperature (unless otherwise noted) (continued) TM4xJ64NPU
PARAMETER High-level output voltage Low-level output voltage Input current (leakage) Output current (leakage) Average read- or write-cycle current TEST CONDITIONS IOH = - 2 mA IOH = - 100 A IOL = 2 mA IOL = 100 A LVTTL LVCMOS LVTTL LVCMOS '4xJ64NPU - 40 MIN 2.4 VDD - 0.2 0.4 0.2 10 10 MAX '4xJ64NPU -50 MIN 2.4 VDD - 0.2 0.4 0.2 10 10 MAX '4xJ64NPU - 60 MIN 2.4 V VDD - 0.2 0.4 V 0.2 10 10 A A MAX UNIT
VOH
VOL II IO
VDD = 3.6 V, VI = 0 V to 3.9 V, All others = 0 V to VDD VDD = 3.6 V, CASx high VO = 0 V to VDD,
ICC2
Average g standby current
VIH = 2 V (LVTTL), After one memory cycle, RASx and CASx high VIH = VDD - 0.2 V (LVCMOS), ( ), After one memory cycle, RAS and CASx high '4EJ64NPU '4FJ64NPU
4
4
4
mA
2 .6
2 .6
2 mA .6
ICC3
RASx-only refresh, average refresh curren Average EDO current Average CBR refresh current Average self-refresh current Average battery back-up operating current, CBR only
VDD = 3.6 V, RASx cycling,
Minimum cycle, CASx high
540
440
400
mA
ICC4 ICC5
VDD = 3.6 V, RASx low,
tHPC = MIN, CASx cycling
560
440
360
mA
VDD = 3.6 V, Minimum cycle, RASx low after CASx low CASx < 0.2 V, RASx < 0.2 V, Measured after tRASS min tRC = 31.25 s, tRAS 300 ns, VDD - 0.2 V VIH 3.9 V, 0 V VIL 0.2 V, WE0 and OE0 = VIH, Address and data stable
640
520
440
mA
ICC6#
1.2
1.2
1.2
mA
ICC10#
1.6
1.6
1.6
mA
For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements. Measured with outputs open Measured with a maximum of one address change while RASx = VIL Measured with a maximum of one address change during each EDO cycle, tHPC # For TM4FJ64NPU only
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
7
PRODUCT PREVIEW
ICC1
VDD = 3.6 V,
Minimum cycle
540
440
400
mA
TM4EJ64KPU, TM4EJ64NPU, TM4FJ64KPU, TM4FJ64NPU, 4194304 BY 64-BIT TM8EJ64KPU, TM8EJ64NPU, TM8FJ64KPU, TM8FJ64NPU, 8388608 BY 64-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES -- SODIMM
SMMS693A - AUGUST 1997 - REVISED NOVEMBER 1997
electrical characteristics over recommended ranges of supply voltage and ambient temperature (unless otherwise noted) (continued) TM8xJ64KPU
PARAMETER High-level output voltage Low-level output voltage Input current (leakage) Output current (leakage) Average read- or write-cycle current TEST CONDITIONS IOH = - 2 mA IOH = - 100 A IOL = 2 mA IOL = 100 A LVTTL LVCMOS LVTTL LVCMOS '8xJ64KPU - 40 MIN 2.4 VDD- 0.2 0.4 0.2 10 10 MAX '8xJ64KPU -50 MIN 2.4 VDD - 0.2 0.4 0.2 10 10 MAX '8xJ64KPU - 60 MIN 2.4 V VDD - 0.2 0.4 V 0.2 10 10 A A MAX UNIT
VOH
VOL II IO
VDD = 3.6 V, VI = 0 V to 3.9 V, All others = 0 V to VDD VDD = 3.6 V, CASx high VO = 0 V to VDD,
PRODUCT PREVIEW
ICC1
VDD = 3.6 V,
Minimum cycle
644
524
444
mA
ICC2
Average g standby current
VIH = 2 V (LVTTL), After one memory cycle, RASx and CASx high VIH = VDD - 0.2 V (LVCMOS), ( ), After one memory cycle, RASx and CASx high '8EJ64KPU '8FJ64KPU
8
8
8
mA
4 1.2
4 1.2
4 mA 1.2
ICC3
RASx-only refresh, average refresh curren Average EDO current Average CBR refresh current Average self-refresh current Average battery back-up operating current, CBR only
VDD = 3.6 V, RASx cycling,
Minimum cycle, CASx high
644
524
444
mA
ICC4 ICC5
VDD = 3.6 V, RASx low,
tHPC = MIN, CASx cycling
604
484
404
mA
VDD = 3.6 V, Minimum cycle, RASx low after CASx low CASx < 0.2 V, RASx < 0.2 V, Measured after tRASS min tRC = 31.25 s, tRAS 300 ns, VDD - 0.2 V VIH 3.9 V, 0 V VIL 0.2 V, WE0 and OE0 = VIH, Address and data stable
644
524
444
mA
ICC6#
2.4
2.4
2.4
mA
ICC10#
3.2
3.2
3.2
mA
For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements. Measured with outputs open Measured with a maximum of one address change while RASx = VIL Measured with a maximum of one address change during each EDO cycle, tHPC # For TM8FJ64KPU only
8
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
TM4EJ64KPU, TM4EJ64NPU, TM4FJ64KPU, TM4FJ64NPU, 4194304 BY 64-BIT TM8EJ64KPU, TM8EJ64NPU, TM8FJ64KPU, TM8FJ64NPU, 8388608 BY 64-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES -- SODIMM
SMMS693A - AUGUST 1997 - REVISED NOVEMBER 1997
electrical characteristics over recommended ranges of supply voltage and ambient temperature (unless otherwise noted) (continued) TM8xJ64NPU
PARAMETER High-level output voltage Low-level output voltage Input current (leakage) Output current (leakage) Average read- or write-cycle current TEST CONDITIONS IOH = - 2 mA IOH = - 100 A IOL = 2 mA IOL = 100 A LVTTL LVCMOS LVTTL LVCMOS '8xJ64NPU - 40 MIN 2.4 VDD - 0.2 0.4 0.2 10 10 MAX '8xJ64NPU -50 MIN 2.4 VDD - 0.2 0.4 0.2 10 10 MAX '8xJ64NPU - 60 MIN 2.4 V VDD - 0.2 0.4 V 0.2 10 10 A A MAX UNIT
VOH
VOL II IO
VDD = 3.6 V, VI = 0 V to 3.9 V, All others = 0 V to VDD VDD = 3.6 V, CASx high VO = 0 V to VDD,
ICC2
Average g standby current
VIH = 2 V (LVTTL), After one memory cycle, RASx and CASx high VIH = VDD - 0.2 V (LVCMOS), ( ), After one memory cycle, RASx and CASx high '8EJ64NPU '8FJ64NPU
8
8
8
mA
4 1.2
4 1.2
4 mA 1.2
ICC3
RASx-only refresh, average refresh curren Average EDO current Average CBR refresh current Average self-refresh current Average battery back-up operating current, CBR only
VDD = 3.6 V, RASx cycling,
Minimum cycle, CASx high
544
444
404
mA
ICC4 ICC5
VDD = 3.6 V, RASx low,
tHPC = MIN, CASx cycling
564
444
364
mA
VDD = 3.6 V, Minimum cycle, RASx low after CASx low CASx < 0.2 V, RASx < 0.2 V, Measured after tRASS min tRC = 31.25 s, tRAS 300 ns, VDD - 0.2 V VIH 3.9 V, 0 V VIL 0.2 V, WE0 and OE0 = VIH, Address and data stable
644
524
444
mA
ICC6#
2.4
2.4
2.4
mA
ICC10#
3.2
3.2
3.2
mA
For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements. Measured with outputs open Measured with a maximum of one address change while RAS = VIL Measured with a maximum of one address change during each EDO cycle, tHPC # For TM8FJ64NPU only
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
9
PRODUCT PREVIEW
ICC1
VDD = 3.6 V,
Minimum cycle
544
444
404
mA
TM4EJ64KPU, TM4EJ64NPU, TM4FJ64KPU, TM4FJ64NPU, 4194304 BY 64-BIT TM8EJ64KPU, TM8EJ64NPU, TM8FJ64KPU, TM8FJ64NPU, 8388608 BY 64-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES -- SODIMM
SMMS693A - AUGUST 1997 - REVISED NOVEMBER 1997
capacitance over recommended ranges of supply voltage and ambient temperature, f = 1 MHz (see Note 2)
PARAMETER Ci(A) Ci(OE) Ci(CAS) Ci(RAS) Ci(W) Co Ci/o(SDA) Ci(SPD) Input capacitance, A0 - A12 Input capacitance, OE0 Input capacitance, CASx Input capacitance, RASx Input capacitance, WE0 Output capacitance Input/output capacitance, SDA input Input capacitance,SPD inputs (except SDA) '4xJ64xPU MIN MAX 22 16 9 16 16 9 9 7 '8xJ64xPU MIN MAX 42 30 9 16 30 16 9 7 UNIT pF pF pF pF pF pF pF pF
NOTE 2: VDD = NOM supply voltage 10%, and the bias on pins under test is 0 V.
switching characteristics over recommended ranges of supply voltage and ambient temperature (see Note 3)
PRODUCT PREVIEW
PARAMETER tAA tCAC tCPA tRAC tOEA tCLZ tOEZ tREZ tCEZ tWEZ Access time from column address (see Note 4) Access time from CASx (see Note 4) Access time from CASx precharge (see Note 4) Access time from RASx (see Note 4) Access time from OE0 (see Note 4) Delay time, CASx to output in the low-impedance state Output buffer turnoff delay from OE0 (see Note 5) Output buffer turnoff delay from RASx (see Note 5) Output buffer turnoff delay from CASx (see Note 5) Output buffer turnoff delay from WE0 (see Note 5)
'xxJ64xPU-40 MIN MAX 20 11 22 40 11 0 3 3 3 3 11 11 11 11
'xxJ64xPU - 50 MIN MAX 25 13 28 50 13 0 3 3 3 3 13 13 13 13
'xxJ64xPU - 60 MIN MAX 30 15 35 60 15 0 3 3 3 3 15 15 15 15
UNIT ns ns ns ns ns ns ns ns ns ns
NOTES: 3. With ac parameters, it is assumed that tT = 2 ns. 4. Access times are measured with output reference levels of VOH = 2 V and VOL = 0.8 V. 5. The MAX specifications of tREZ , tCEZ , tWEZ and tOEZ are specified when the output is no longer driven. Data-in should not be driven until one of the applicable maximum specifications is satsified.
EDO timing requirements (see Note 3)
'xxJ64xPU - 40 MIN tHPC tPRWC tCSH tCHO tDOH tCAS tWPE tCP tOCH tOEP Cycle time, EDO page-mode read or write Cycle time, EDO read-write Delay time, RASx active to CASx precharge Hold time, OE0 from CASx Hold time, output from CASx active Pulse duration, CASx active (see Note 6) Pulse duration, WE0 (output disable only) Pulse duration, CASx precharge Setup time, OE0 before CASx Precharge time, OE0 (output disable only) 16 47 32 5 5 6 5 6 5 5 10 000 MAX 'xxJ64xPU - 50 MIN 20 57 40 5 5 8 5 8 5 5 10 000 MAX 'xxJ64xPU - 60 MIN 25 68 48 5 5 10 5 10 5 5 10 000 MAX UNIT ns ns ns ns ns ns ns ns ns ns
NOTES: 3. With ac parameters, it is assumed that tT = 2 ns. 6. In a read-write cycle, tCWD and tCWL must be observed.
10
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
TM4EJ64KPU, TM4EJ64NPU, TM4FJ64KPU, TM4FJ64NPU, 4194304 BY 64-BIT TM8EJ64KPU, TM8EJ64NPU, TM8FJ64KPU, TM8FJ64NPU, 8388608 BY 64-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES -- SODIMM
SMMS693A - AUGUST 1997 - REVISED NOVEMBER 1997
ac timing requirements (see Note 3)
'xxJ64xPU -40 MIN tRC tRWC tRASP tRAS tRP tWP tASC tASR tDS tRCS tCWL tRWL tWCS tWRP tCSR tCAH tDH tRAH tRCH tRRH tWCH tRHCP tOEH tROH tWRH tCHS tAWD tCHR tCRP tCWD Cycle time, read Cycle time, read-write Pulse duration, RASx active, page mode (see Note 7) Pulse duration, RASx active, nonpage mode (see Note 7) Pulse duration, RASx precharge Pulse duration, write command Setup time, column address Setup time, row address Setup time, data in (see Note 8) Setup time, read command Setup time, write command before CASx precharge Setup time, write command before RASx precharge Setup time, write command before CASx active (early-write only) Setup time, write before RASx active (CBR refresh only) Setup time, CASx referenced to RASx (CBR refresh only) Hold time, column address Hold time, data in (see Note 8) Hold time, row address Hold time, read command referenced to CASx (see Note 9) Hold time, read command referenced to RASx (see Note 9) Hold time, write command during CASx active (early-write only) Hold time, RASx active from CASx precharge Hold time, OE0 command Hold time, RASx referenced to OE0 Hold time, write after RASx active (CBR refresh only) Hold time, CASx active after RASx precharge (self-refresh) Delay time, column address to write command (read-write only) Delay time, CASx referenced to RASx (CBR refresh only) Delay time, CASx precharge to RASx Delay time, CASx to write command (read-write operation only) With ac parameters, it is assumed that tT = 2 ns. In a read-write cycle, tRWD and tRWL must be observed. Referenced to the later of CASx or WE0 in write operations Either tRRH or tRCH must be satisfied for a read cycle. 69 92 40 100 000 40 25 6 0 0 0 0 6 6 0 5 5 6 6 6 0 0 6 22 11 6 6 - 50 35 6 5 26 10 000 MAX 'xxJ64xPU - 50 MIN 84 111 50 100 000 50 30 8 0 0 0 0 8 8 0 5 5 8 8 8 0 0 8 28 13 8 8 - 50 42 8 5 30 10 000 MAX 'xxJ64xPU - 60 MIN 104 135 60 100 000 60 40 10 0 0 0 0 10 10 0 5 5 10 10 10 0 0 10 35 15 10 10 - 50 49 10 5 34 10 000 MAX UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
NOTES: 3. 7. 8. 9.
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
11
PRODUCT PREVIEW
TM4EJ64KPU, TM4EJ64NPU, TM4FJ64KPU, TM4FJ64NPU, 4194304 BY 64-BIT TM8EJ64KPU, TM8EJ64NPU, TM8FJ64KPU, TM8FJ64NPU, 8388608 BY 64-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES -- SODIMM
SMMS693A - AUGUST 1997 - REVISED NOVEMBER 1997
ac timing requirements (see Note 3) (continued)
'xxJ64xPU -40 MIN tOED tRAD tRAL tCAL tRCD tRPC tRSH tRWD tCPW tRASS tRPS tREF Delay time, OE0 to data in Delay time, RASx to column address (see Note 10) Delay time, column address to RASx precharge Delay time, column address to CASx precharge Delay time, RASx to CASx (see Note 10) Delay time, RASx precharge to CASx Delay time, CASx active to RASx precharge Delay time, RASx active to write command (read-write only) Delay time, CASx precharge to write command (read-write only) Pulse duration, RASx active, self-refresh (see Note 11) Pulse duration, RASx precharge after self refresh Refresh time interval 'xEJ64xPU 'xFJ64xPU 11 8 20 12 10 5 6 55 37 100 70 64 128 29 20 MAX 'xxJ64xPU - 50 MIN 13 10 25 15 12 5 8 67 45 100 90 64 128 37 25 MAX 'xxJ64xPU - 60 MIN 15 12 30 18 14 5 10 79 54 100 110 64 128 45 30 MAX UNIT ns ns ns ns ns ns ns ns ns s ns ms ms
PRODUCT PREVIEW
tT Transition time 1 50 1 50 1 50 ns NOTES: 3. With ac parameters, it is assumed that tT = 2 ns. 10. The maximum value is specified only to assure access time. 11. During the period of 10 s tRASS 100 s, the device is in transition state from normal operational mode to self-refresh mode.
12
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
TM4EJ64KPU, TM4EJ64NPU, TM4FJ64KPU, TM4FJ64NPU, 4194304 BY 64-BIT TM8EJ64KPU, TM8EJ64NPU, TM8FJ64KPU, TM8FJ64NPU, 8388608 BY 64-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES -- SODIMM
SMMS693A - AUGUST 1997 - REVISED NOVEMBER 1997
serial presence detect
The serial presence detect (SPD) is contained in a 2K-bit serial EEPROM located on the module. The SPD nonvolatile EEPROM contains various data such as module configuration, DRAM organization, and timing parameters (see tables below). Only the first 128 bytes are programmed by Texas Instruments, while the remaining 128 bytes are available for customer use. Programming is done through an IIC bus using the clock (SCL) and data (SDA) signals. All Texas Instruments modules comply with the current JEDEC SPD Standard. See the Texas Instruments Serial Presence Detect Technical Reference (literature number SMMU001) for further details. Tables in this section list the SPD contents as follows: Table 2--TM4EJ64KPU Table 4--TM8EJ64KPU Table 6--TM4FJ64KPU Table 8--TM8FJ64KPU Table 3-- TM4EJ64NPU Table 5--TM8EJ64NPU Table 7--TM4FJ64NPU Table 9--TM8FJ64NPU
Table 2. Serial-Presence-Detect Data for the TM4EJ64KPU
BYTE NO. 0 FUNCTION DESCRIBED Defines number of bytes written into serial memory during module manufacturing Total number of bytes of SPD memory device Fundamental memory (FPM, EDO, SDRAM) type '4EJ64KPU-40 ITEM 128 bytes DATA 80h '4EJ64KPU-50 ITEM 128 bytes DATA 80h '4EJ64KPU-60 ITEM 128 bytes DATA 80h
1 2 3 4 5 6 7 8 9 10 11 12 13 14 62 63
256 bytes EDO 12 10 1 bank 64 bits
08h 02h 0Ch 0Ah 01h 40h 00h
256 bytes EDO 12 10 1 bank 64 bits
08h 02h 0Ch 0Ah 01h 40h 00h
256 bytes EDO 12 10 1 bank 64 bits
08h 02h 0Ch 0Ah 01h 40h 00h
Number of row addresses on this assembly Number of column addresses on this assembly Number of module banks on this assembly Data width of this assembly Data width continuation Voltage interface standard of this assembly RASx access time of module CASx access time of module SODIMM configuration type (non-parity, parity, error correcting code [ECC]) Refresh rate / type DRAM width, primary DRAM Error-checking SDRAM data width SPD revision Checksum for bytes 0 - 62
LVTTL tRAC = 40 ns tCAC = 11 ns Non-parity 15.6 s x16 N/A Rev. 1 38
01h 28h 0Bh 00h 00h 10h 00h 01h 26h
LVTTL tRAC = 50 ns tCAC = 13 ns Non-parity 15.6 s x16 N/A Rev. 1 50
01h 32h 0Dh 00h 00h 10h 00h 01h 32h
LVTTL tRAC = 60 ns tCAC = 15 ns Non-parity 15.6 s x16 N/A Rev. 1 62
01h 3Ch 0Fh 00h 00h 10h 00h 01h 3Eh
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
13
PRODUCT PREVIEW
TM4EJ64KPU, TM4EJ64NPU, TM4FJ64KPU, TM4FJ64NPU, 4194304 BY 64-BIT TM8EJ64KPU, TM8EJ64NPU, TM8FJ64KPU, TM8FJ64NPU, 8388608 BY 64-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES -- SODIMM
SMMS693A - AUGUST 1997 - REVISED NOVEMBER 1997
serial presence detect (continued)
Table 2. Serial-Presence-Detect Data for the TM4EJ64KPU (Continued)
BYTE NO. 64-71 72 73-90 91 92 93-94 95-98 99-125 126-127 128-166 FUNCTION DESCRIBED Manufacturer's JEDEC ID code per JEP-106E Manufacturing location Manufacturer's part number Die revision code PCB revision code Manufacturing date Assembly serial number Manufacturer specific data Vendor specific data System integrator's specific data '4EJ64KPU-40 ITEM 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD DATA 9700...00h '4EJ64KPU-50 ITEM 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD DATA 9700...00h '4EJ64KPU-60 ITEM 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD DATA 9700...00h
PRODUCT PREVIEW
167-255 Open TBD indicates values are determined at manufacturing time and are module dependent. These TBD values are determined and programmed by the customer (optional).
14
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
TM4EJ64KPU, TM4EJ64NPU, TM4FJ64KPU, TM4FJ64NPU, 4194304 BY 64-BIT TM8EJ64KPU, TM8EJ64NPU, TM8FJ64KPU, TM8FJ64NPU, 8388608 BY 64-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES -- SODIMM
SMMS693A - AUGUST 1997 - REVISED NOVEMBER 1997
serial presence detect (continued)
Table 3. Serial-Presence-Detect Data for the TM4EJ64NPU
BYTE NO. 0 FUNCTION DESCRIBED Defines number of bytes written into serial memory during module manufacturing Total number of bytes of SPD memory device Fundamental memory (FPM, EDO, SDRAM) type '4EJ64NPU-40 ITEM 128 bytes DATA 80h '4EJ64NPU-50 ITEM 128 bytes DATA 80h '4EJ64NPU-60 ITEM 128 bytes DATA 80h
1 2 3 4 5 6 7 8 9 10 11 12 13 14 62 63 64-71 72 73-90 91 92 93-94 95-98 99-125 126-127 128-166
256 bytes EDO 13 9 1 bank 64 bits
08h 02h 0Dh 09h 01h 40h 00h
256 bytes EDO 13 9 1 bank 64 bits
08h 02h 0Dh 09h 01h 40h 00h
256 bytes EDO 13 9 1 bank 64 bits
08h 02h 0Dh 09h 01h 40h 00h
Number of row addresses on this assembly Number of column addresses on this assembly Number of module banks on this assembly Data width of this assembly Data width continuation Voltage interface standard of this assembly RASx access time of module CASx access time of module SODIMM configuration type (non-parity, parity, error correcting code [ECC]) Refresh rate / type DRAM width, primary DRAM Error-checking SDRAM data width SPD revision Checksum for bytes 0 - 62 Manufacturer's JEDEC ID code per JEP-106E Manufacturing location Manufacturer's part number Die revision code PCB revision code Manufacturing date Assembly serial number Manufacturer specific data Vendor specific data System integrator's specific data
LVTTL tRAC = 40 ns tCAC = 11 ns Non-parity 15.6 s x16 N/A Rev. 1 38 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD
01h 28h 0Bh 00h 00h 10h 00h 01h 26h 9700...00h
LVTTL tRAC = 50 ns tCAC = 13 ns Non-parity 15.6 s x16 N/A Rev. 1 50 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD
01h 32h 0Dh 00h 00h 10h 00h 01h 32h 9700...00h
LVTTL tRAC = 60 ns tCAC = 15 ns Non-parity 15.6 s x16 N/A Rev. 1 62 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD
01h 3Ch 0Fh 00h 00h 10h 00h 01h 3Eh 9700...00h
167-255 Open TBD indicates values are determined at manufacturing time and are module dependent. These TBD values are determined and programmed by the customer (optional).
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
15
PRODUCT PREVIEW
TM4EJ64KPU, TM4EJ64NPU, TM4FJ64KPU, TM4FJ64NPU, 4194304 BY 64-BIT TM8EJ64KPU, TM8EJ64NPU, TM8FJ64KPU, TM8FJ64NPU, 8388608 BY 64-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES -- SODIMM
SMMS693A - AUGUST 1997 - REVISED NOVEMBER 1997
serial presence detect (continued)
Table 4. Serial-Presence-Detect Data for the TM8EJ64KPU
BYTE NO. 0 FUNCTION DESCRIBED Defines number of bytes written into serial memory during module manufacturing Total number of bytes of SPD memory device Fundamental memory (FPM, EDO, SDRAM) type '8EJ64KPU-40 ITEM 128 bytes DATA 80h '8EJ64KPU-50 ITEM 128 bytes DATA 80h '8EJ64KPU-60 ITEM 128 bytes DATA 80h
1 2 3 4 5
256 bytes EDO 12 10 2 banks 64 bits
08h 02h 0Ch 0Ah 02h 40h 00h
256 bytes EDO 12 10 2 banks 64 bits
08h 02h 0Ch 0Ah 02h 40h 00h
256 bytes EDO 12 10 2 banks 64 bits
08h 02h 0Ch 0Ah 02h 40h 00h
Number of row addresses on this assembly Number of column addresses on this assembly Number of module banks on this assembly Data width of this assembly Data width continuation Voltage interface standard of this assembly RASx access time of module CASx access time of module SODIMM configuration type (non-parity, parity, error correcting code [ECC]) Refresh rate / type DRAM width, primary DRAM Error-checking SDRAM data width SPD revision Checksum for bytes 0 - 62 Manufacturer's JEDEC ID code per JEP-106E Manufacturing location Manufacturer's part number Die revision code PCB revision code Manufacturing date Assembly serial number Manufacturer specific data Vendor specific data System integrator's specific data
PRODUCT PREVIEW
6 7 8 9 10 11 12 13 14 62 63 64-71 72 73-90 91 92 93-94 95-98 99-125 126-127 128-166
LVTTL tRAC = 40 ns tCAC = 11 ns Non-parity 15.6 s x16 N/A Rev. 1 39 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD
01h 28h 0Bh 00h 00h 10h 00h 01h 27h 9700...00h
LVTTL tRAC = 50 ns tCAC = 13 ns Non-parity 15.6 s x16 N/A Rev. 1 51 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD
01h 32h 0Dh 00h 00h 10h 00h 01h 33h 9700...00h
LVTTL tRAC = 60 ns tCAC = 15 ns Non-parity 15.6 s x16 N/A Rev. 1 63 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD
01h 3Ch 0Fh 00h 00h 10h 00h 01h 3Fh 9700...00h
167-255 Open TBD indicates values are determined at manufacturing time and are module dependent. These TBD values are determined and programmed by the customer (optional).
16
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
TM4EJ64KPU, TM4EJ64NPU, TM4FJ64KPU, TM4FJ64NPU, 4194304 BY 64-BIT TM8EJ64KPU, TM8EJ64NPU, TM8FJ64KPU, TM8FJ64NPU, 8388608 BY 64-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES -- SODIMM
SMMS693A - AUGUST 1997 - REVISED NOVEMBER 1997
serial presence detect (continued)
Table 5. Serial-Presence-Detect Data for the TM8EJ64NPU
BYTE NO. 0 FUNCTION DESCRIBED Defines number of bytes written into serial memory during module manufacturing Total number of bytes of SPD memory device Fundamental memory (FPM, EDO, SDRAM) type 8EJ64NPU-40 ITEM 128 bytes DATA 80h '8EJ64NPU-50 ITEM 128 bytes DATA 80h '8EJ64NPU-60 ITEM 128 bytes DATA 80h
1 2 3 4 5 6 7 8 9 10 11 12 13 14 62 63 64-71 72 73-90 91 92 93-94 95-98 99-125 126-127 128-166
256 bytes EDO 13 9 2 banks 64 bits
08h 02h 0Dh 09h 02h 40h 00h
256 bytes EDO 13 9 2 banks 64 bits
08h 02h 0Dh 09h 02h 40h 00h
256 bytes EDO 13 9 2 banks 64 bits
08h 02h 0Dh 09h 02h 40h 00h
Number of row addresses on this assembly Number of column addresses on this assembly Number of module banks on this assembly Data width of this assembly Data width continuation Voltage interface standard of this assembly RASx access time of module CASx access time of module SODIMM configuration type (non-parity, parity, error correcting code [ECC]) Refresh rate / type DRAM width, primary DRAM Error-checking SDRAM data width SPD revision Checksum for bytes 0 - 62 Manufacturer's JEDEC ID code per JEP-106E Manufacturing location Manufacturer's part number Die revision code PCB revision code Manufacturing date Assembly serial number Manufacturer specific data Vendor specific data System integrator's specific data
LVTTL tRAC = 40 ns tCAC = 11 ns Non-parity 15.6 s x16 N/A Rev. 1 39 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD
01h 28h 0Bh 00h 00h 10h 00h 01h 27h 9700...00h
LVTTL tRAC = 50 ns tCAC = 13 ns Non-parity 15.6 s x16 N/A Rev. 1 51 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD
01h 32h 0Dh 00h 00h 10h 00h 01h 33h 9700...00h
LVTTL tRAC = 60 ns tCAC = 15 ns Non-parity 15.6 s x16 N/A Rev. 1 63 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD
01h 3Ch 0Fh 00h 00h 10h 00h 01h 3Fh 9700...00h
167-255 Open TBD indicates values are determined at manufacturing time and are module dependent. These TBD values are determined and programmed by the customer (optional).
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
17
PRODUCT PREVIEW
TM4EJ64KPU, TM4EJ64NPU, TM4FJ64KPU, TM4FJ64NPU, 4194304 BY 64-BIT TM8EJ64KPU, TM8EJ64NPU, TM8FJ64KPU, TM8FJ64NPU, 8388608 BY 64-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES -- SODIMM
SMMS693A - AUGUST 1997 - REVISED NOVEMBER 1997
serial presence detect (continued)
Table 6. Serial-Presence-Detect Data for the TM4FJ64KPU
BYTE NO. 0 FUNCTION DESCRIBED Defines number of bytes written into serial memory during module manufacturing Total number of bytes of SPD memory device Fundamental memory (FPM, EDO, SDRAM) type '4FJ64KPU-40 ITEM 128 bytes DATA 80h '4FJ64KPU-50 ITEM 128 bytes DATA 80h '4FJ64KPU-60 ITEM 128 bytes DATA 80h
1 2 3 4 5
256 bytes EDO 12 10 1 banks 64 bits
08h 02h 0Ch 0Ah 01h 40h 00h
256 bytes EDO 12 10 1 banks 64 bits
08h 02h 0Ch 0Ah 01h 40h 00h
256 bytes EDO 12 10 1 banks 64 bits
08h 02h 0Ch 0Ah 01h 40h 00h
Number of row addresses on this assembly Number of column addresses on this assembly Number of module banks on this assembly Data width of this assembly Data width continuation Voltage interface standard of this assembly RASx access time of module CASx access time of module SODIMM configuration type (non-parity, parity, error correcting code [ECC]) Refresh rate / type DRAM width, primary DRAM Error-checking SDRAM data width SPD revision Checksum for bytes 0 - 62 Manufacturer's JEDEC ID code per JEP-106E Manufacturing location Manufacturer's part number Die revision code PCB revision code Manufacturing date Assembly serial number Manufacturer specific data Vendor specific data System integrator's specific data
PRODUCT PREVIEW
6 7 8 9 10 11
LVTTL tRAC = 40 ns tCAC = 11 ns Non-parity 15.6 s /selfrefresh x16 N/A Rev. 1 166 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD
01h 28h 0Bh 00h
LVTTL tRAC = 50 ns tCAC = 13 ns Non-parity 15.6 s /selfrefresh x16 N/A Rev. 1 178 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD
01h 32h 0Dh 00h
LVTTL tRAC = 60 ns tCAC = 15 ns Non-parity 15.6 s /selfrefresh x16 N/A Rev. 1 190 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD
01h 3Ch 0Fh 00h
12 13 14 62 63 64-71 72 73-90 91 92 93-94 95-98 99-125 126-127 128-166
80h 10h 00h 01h A6h 9700...00h
80h 10h 00h 01h B2h 9700...00h
80h 10h 00h 01h BEh 9700...00h
167-255 Open TBD indicates values are determined at manufacturing time and are module dependent. These TBD values are determined and programmed by the customer (optional).
18
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
TM4EJ64KPU, TM4EJ64NPU, TM4FJ64KPU, TM4FJ64NPU, 4194304 BY 64-BIT TM8EJ64KPU, TM8EJ64NPU, TM8FJ64KPU, TM8FJ64NPU, 8388608 BY 64-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES -- SODIMM
SMMS693A - AUGUST 1997 - REVISED NOVEMBER 1997
serial presence detect (continued)
Table 7. Serial-Presence-Detect Data for the TM4FJ64NPU
BYTE NO. 0 FUNCTION DESCRIBED Defines number of bytes written into serial memory during module manufacturing Total number of bytes of SPD memory device Fundamental memory (FPM, EDO, SDRAM) type '4FJ64NPU-40 ITEM 128 bytes DATA 80h '4FJ64NPU-50 ITEM 128 bytes DATA 80h '4FJ64NPU-60 ITEM 128 bytes DATA 80h
1 2 3 4 5 6 7 8 9 10 11
256 bytes EDO 13 9 1 bank 64 bits
08h 02h 0Dh 09h 01h 40h 00h
256 bytes EDO 13 9 1 bank 64 bits
08h 02h 0Dh 09h 01h 40h 00h
256 bytes EDO 13 9 1 bank 64 bits
08h 02h 0Dh 09h 01h 40h 00h
Number of row addresses on this assembly Number of column addresses on this assembly Number of module banks on this assembly Data width of this assembly Data width continuation Voltage interface standard of this assembly RASx access time of module CASx access time of module SODIMM configuration type (non-parity, parity, error correcting code [ECC]) Refresh rate / type DRAM width, primary DRAM Error-checking SDRAM data width SPD revision Checksum for bytes 0 - 62 Manufacturer's JEDEC ID code per JEP-106E Manufacturing location Manufacturer's part number Die revision code PCB revision code Manufacturing date Assembly serial number Manufacturer specific data Vendor specific data System integrator's specific data
LVTTL tRAC = 40 ns tCAC = 11 ns Non-parity 15.6 s /selfrefresh x16 N/A Rev. 1 166 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD
01h 28h 0Bh 00h
LVTTL tRAC = 50 ns tCAC = 13 ns Non-parity 15.6 s /selfrefresh x16 N/A Rev. 1 178 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD
01h 32h 0Dh 00h
LVTTL tRAC = 60 ns tCAC = 15 ns Non-parity 15.6 s /selfrefresh x16 N/A Rev. 1 190 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD
01h 3Ch 0Fh 00h
12 13 14 62 63 64-71 72 73-90 91 92 93-94 95-98 99-125 126-127 128-166
80h 10h 00h 01h A6h 9700...00h
80h 10h 00h 01h B2h 9700...00h
80h 10h 00h 01h BEh 9700...00h
167-255 Open TBD indicates values are determined at manufacturing time and are module dependent. These TBD values are determined and programmed by the customer (optional).
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
19
PRODUCT PREVIEW
TM4EJ64KPU, TM4EJ64NPU, TM4FJ64KPU, TM4FJ64NPU, 4194304 BY 64-BIT TM8EJ64KPU, TM8EJ64NPU, TM8FJ64KPU, TM8FJ64NPU, 8388608 BY 64-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES -- SODIMM
SMMS693A - AUGUST 1997 - REVISED NOVEMBER 1997
serial presence detect (continued)
Table 8. Serial-Presence-Detect Data for the TM8FJ64KPU
BYTE NO. 0 FUNCTION DESCRIBED Defines number of bytes written into serial memory during module manufacturing Total number of bytes of SPD memory device Fundamental memory (FPM, EDO, SDRAM) type '8FJ64KPU-40 ITEM 128 bytes DATA 80h '8FJ64KPU-50 ITEM 128 bytes DATA 80h '8FJ64KPU-60 ITEM 128 bytes DATA 80h
1 2 3 4 5
256 bytes EDO 12 10 2 banks 64 bits
08h 02h 0Ch 0Ah 02h 40h 00h
256 bytes EDO 12 10 2 banks 64 bits
08h 02h 0Ch 0Ah 02h 40h 00h
256 bytes EDO 12 10 2 banks 64 bits
08h 02h 0Ch 0Ah 02h 40h 00h
Number of row addresses on this assembly Number of column addresses on this assembly Number of module banks on this assembly Data width of this assembly Data width continuation Voltage interface standard of this assembly RASx access time of module CASx access time of module SODIMM configuration type (non-parity, parity, error correcting code [ECC]) Refresh rate / type DRAM width, primary DRAM Error-checking SDRAM data width SPD revision Checksum for bytes 0 - 62 Manufacturer's JEDEC ID code per JEP-106E Manufacturing location Manufacturer's part number Die revision code PCB revision code Manufacturing date Assembly serial number Manufacturer specific data Vendor specific data System integrator's specific data
PRODUCT PREVIEW
6 7 8 9 10 11
LVTTL tRAC = 40 ns tCAC = 11 ns Non-parity 15.6 s /selfrefresh x16 N/A Rev. 1 167 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD
01h 28h 0Bh 00h
LVTTL tRAC = 50 ns tCAC = 13 ns Non-parity 15.6 s/selfrefresh x16 N/A Rev. 1 179 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD
01h 32h 0Dh 00h
LVTTL tRAC = 60 ns tCAC = 15 ns Non-parity 15.6 s/selfrefresh x16 N/A Rev. 1 191 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD
01h 3Ch 0Fh 00h
12 13 14 62 63 64-71 72 73-90 91 92 93-94 95-98 99-125 126-127 128-166
80h 10h 00h 01h A7h 9700...00h
80h 10h 00h 01h B3h 9700...00h
80h 10h 00h 01h BFh 9700...00h
167-255 Open TBD indicates values are determined at manufacturing time and are module dependent. These TBD values are determined and programmed by the customer (optional).
20
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
TM4EJ64KPU, TM4EJ64NPU, TM4FJ64KPU, TM4FJ64NPU, 4194304 BY 64-BIT TM8EJ64KPU, TM8EJ64NPU, TM8FJ64KPU, TM8FJ64NPU, 8388608 BY 64-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES -- SODIMM
SMMS693A - AUGUST 1997 - REVISED NOVEMBER 1997
serial presence detect (continued)
Table 9. Serial-Presence-Detect Data for the TM8FJ64NPU
BYTE NO. 0 FUNCTION DESCRIBED Defines number of bytes written into serial memory during module manufacturing Total number of bytes of SPD memory device Fundamental memory (FPM, EDO, SDRAM) type 8FJ64NPU-40 ITEM 128 bytes DATA 80h '8FJ64NPU-50 ITEM 128 bytes DATA 80h '8FJ64NPU-60 ITEM 128 bytes DATA 80h
1 2 3 4 5 6 7 8 9 10 11
256 bytes EDO 13 9 2 banks 64 bits
08h 02h 0Dh 09h 02h 40h 00h
256 bytes EDO 13 9 2 banks 64 bits
08h 02h 0Dh 09h 02h 40h 00h
256 bytes EDO 13 9 2 banks 64 bits
08h 02h 0Dh 09h 02h 40h 00h
Number of row addresses on this assembly Number of column addresses on this assembly Number of module banks on this assembly Data width of this assembly Data width continuation Voltage interface standard of this assembly RASx access time of module CASx access time of module DIMM configuration (non-parity, parity, correcting code [ECC]) Refresh rate / type DRAM width, primary DRAM Error-checking SDRAM data width SPD revision Checksum for bytes 0 - 62 Manufacturer's JEDEC ID code per JEP-106E Manufacturing location Manufacturer's part number Die revision code PCB revision code Manufacturing date Assembly serial number Manufacturer specific data Vendor specific data System integrator's specific data type error
LVTTL tRAC = 40 ns tCAC = 19 ns Non-parity 15.6 s /selfrefresh x16 N/A Rev. 1 167 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD
01h 28h 0Bh 00h
LVTTL tRAC = 50 ns tCAC = 13 ns Non-parity 15.6 s/selfrefresh x16 N/A Rev. 1 179 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD
01h 32h 0Dh 00h
LVTTL tRAC = 60 ns tCAC = 15 ns Non-parity 15.6 s/selfrefresh x16 N/A Rev. 1 191 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD
01h 3Ch 0Fh 00h
12 13 14 62 63 64-71 72 73-90 91 92 93-94 95-98 99-125 126-127 128-166
80h 10h 00h 01h A7h 9700...00h
80h 10h 00h 01h B3h 9700...00h
80h 10h 00h 01h BFh 9700...00h
167-255 Open TBD indicates values are determined at manufacturing time and are module dependent. These TBD values are determined and programmed by the customer (optional).
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
21
PRODUCT PREVIEW
TM4EJ64KPU, TM4EJ64NPU, TM4FJ64KPU, TM4FJ64NPU, 4194304 BY 64-BIT TM8EJ64KPU, TM8EJ64NPU, TM8FJ64KPU, TM8FJ64NPU, 8388608 BY 64-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES -- SODIMM
SMMS693A - AUGUST 1997 - REVISED NOVEMBER 1997
device symbolization (TM4EJ64KPU illustrated)
TM4EJ64KPU
-SS
YYMMT
YY MM T -SS
= = = =
Year Code Month Code Assembly Site Code Speed Code
NOTES: A. Location of symbolization may vary.
PRODUCT PREVIEW
22
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
TM4EJ64KPU, TM4EJ64NPU, TM4FJ64KPU, TM4FJ64NPU, 4194304 BY 64-BIT TM8EJ64KPU, TM8EJ64NPU, TM8FJ64KPU, TM8FJ64NPU, 8388608 BY 64-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES -- SODIMM
SMMS693A - AUGUST 1997 - REVISED NOVEMBER 1997
MECHANICAL DATA
BDM (R-SODIMM-N144) SMALL OUTLINE DUAL IN-LINE MEMORY MODULE
2.665 (67,69) 2.655 (67,44) Notch 0.157 (4,00) x 0.079 (2,00) Deep (2 Places) Notch 0.060 (1,52) x 0.158 (4,01) Deep 0.044 (1,12) 0.036 (0,91)
0.024 (0,61) TYP 0.098 (2,49) 0.196 (4,98)
0.031 (0,79)
0.010 (0,25) MAX 0.788 (20,00) TYP 1.005 (25,53) 0.995 (25,27) 0.157 (4,00) 0.126 (3,20) 0.095 (2,41) MAX 0.150 (3,81) MAX (For Double Sided Module Only) 4088187/A 07/97
NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MO-190
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
23
PRODUCT PREVIEW
IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 1998, Texas Instruments Incorporated

▲Up To Search▲

Price & Availability of SMMS693A

	To Download SMMS693A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .