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TM4SK64KPU 4194304 BY 64-BIT TM8SK64KPU 8388608 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULES -- SODIMM
SMMS691A - AUGUST 1997 - REVISED NOVEMBER 1997
D D D D D D D D
Organization: - TM4SK64KPU . . . 4 194 304 x 64 Bits - TM8SK64KPU . . . 8 388 608 x 64 Bits Single 3.3-V Power Supply (10% Tolerance) Designed for 66-MHz 4-Clock Systems. JEDEC 144-Pin Small-Outline Dual-In-Line Memory Module (SODIMM) Without Buffer for Use With Socket TM4SK64KPU -- Uses Four 64M-Bit Synchronous Dynamic RAMs (SDRAMs) (4M x 16-Bit) in Plastic Thin Small-Outline Packages (TSOPs) TM8SK64KPU -- Uses Eight 64M-Bit SDRAMs (4M x 16-Bit) in Plastic TSOPs Byte-Read/Write Capability Performance Ranges:
SYNCHRONOUS CLOCK CYCLE TIME tCK3 tCK2 ACCESS TIME CLOCK TO OUTPUT tAC3 tAC2 7.5 ns 8 ns 9 ns 9.5 ns 64 ms REFRESH INTERVAL tREF
D D D D D D D D D
High-Speed, Low-Noise Low-Voltage TTL (LVTTL) Interface Read Latencies 2 and 3 Supported Support Burst-Interleave and Burst-Interrupt Operations Burst Length Programmable to 1, 2, 4, 8, and Full Page Four Banks for On-Chip Interleaving (Gapless Access) Ambient Temperature Range 0C to 70C Gold-Plated Contacts Pipeline Architecture Serial Presence-Detect (SPD) Using EEPROM
'xSK64KPU - 10 'xSK64KPU - 12
10 ns 12 ns
10 ns 12 ns
description
The TM4SK64KPU is a 32M-byte, 144-pin small-outline dual-in-line memory module (SODIMM). The SODIMM is composed of four TMS664164DGE, 4 194 304 x 16-bit SDRAMs, each in a 400-mil, 54-pin plastic thin small-outline package (TSOP) mounted on a substrate with decoupling capacitors. See the TMS664164 data sheet (literature number SMOS690). The TM8SK64KPU is a 64M-byte, 144-pin SODIMM. The SODIMM is composed of eight TMS664164DGE, 4 194 304 x 16-bit SDRAMs, each in a 400-mil, 54-pin plastic TSOP mounted on a substrate with decoupling capacitors. See the TMS664164 data sheet (literature number SMOS690).
operation
The TM4SK64KPU operates as four TMS664164DGE devices that are connected as shown in the TM4SK64KPU functional block diagram. The TM8SK64KPU operates as eight TMS664164DGE devices connected as shown in the TM8SK64KPU functional block diagram.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright (c) 1997, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
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PRODUCT PREVIEW
TM4SK64KPU 4194304 BY 64-BIT TM8SK64KPU 8388608 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULES -- SODIMM
SMMS691A - AUGUST 1997 - REVISED NOVEMBER 1997
DUAL-IN-LINE MEMORY MODULE ( TOP VIEW )
TM4SK64KPU TM8SK64KPU ( SIDE VIEW ) ( SIDE VIEW )
PIN NOMENCLATURE A[0:11] A[0:7] A13/BA0 A12/BA0 CAS CKE[0:1] CK[0:3] DQ[0:63] DQMB[0:7] NC RAS S[0:1] SCL SDA VDD VSS WE Row Address Inputs Column Address Inputs Bank-Select Zero Bank-Select One Column-Address Strobe Clock Enable System Clock Data-In / Data-Out Data-In/Data-Out Mask Enable No Connect Row-Address Strobe Chip-Select SPD Clock SPD Address / Data 3.3-V Supply Ground Write Enable
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PRODUCT PREVIEW
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143
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TM4SK64KPU 4194304 BY 64-BIT TM8SK64KPU 8388608 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULES -- SODIMM
SMMS691A - AUGUST 1997 - REVISED NOVEMBER 1997
Pin Assignments
PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 NAME VSS VSS DQ0 DQ32 DQ1 DQ33 DQ2 DQ34 DQ3 DQ35 VDD VDD DQ4 DQ36 DQ5 DQ37 DQ6 DQ38 DQ7 DQ39 VSS VSS DQMB0 DQMB4 DQMB1 DQMB5 VDD VDD A0 A3 A1 A4 A2 A5 VSS VSS NO. 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 PIN NAME DQ8 DQ40 DQ9 DQ41 DQ10 DQ42 DQ11 DQ43 VDD VDD DQ12 DQ44 DQ13 DQ45 DQ14 DQ46 DQ15 DQ47 VSS VSS NC NC NC NC CK0 CKE0 VDD VDD RAS CAS WE CKE1 S0 NC S1 NC NO. 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 PIN NAME NC CK1 VSS VSS NC NC NC NC VDD VDD DQ16 DQ48 DQ17 DQ49 DQ18 DQ50 DQ19 DQ51 VSS VSS DQ20 DQ52 DQ21 DQ53 DQ22 DQ54 DQ23 DQ55 VDD VDD A6 A7 A8 A13/BA0 VSS VSS NO. 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 PIN NAME A9 A12/BA1 A10 A11 VDD VDD DQMB2 DQMB6 DQMB3 DQMB7 VSS VSS DQ24 DQ25 DQ57 DQ26 DQ58 DQ27 DQ59 VDD VDD DQ28 DQ60 DQ29 DQ61 DQ30 DQ62 DQ31 DQ63 VSS VSS SDA SCL VDD VDD DQ56
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TM4SK64KPU 4194304 BY 64-BIT TM8SK64KPU 8388608 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULES -- SODIMM
SMMS691A - AUGUST 1997 - REVISED NOVEMBER 1997
small-outline dual-in-line memory module and components
The small-outline dual-in-line memory module and components include:
D D D
PC substrate: 1,10 0,1 mm (0.04 inch) nominal thickness Bypass capacitors: Multilayer ceramic Contact area: Nickel plate and gold plate over copper
functional block diagram for the TM4SK64KPU
S0 RC CS DQMB0 R DQ[0:7] DQMB4 R DQ[32:39] 8 8 DQM DQ[0:7] DQM DQ[0:7] U0 DQMB2 R DQ[16:23] DQMB6 R DQ[48:55] 8 8 CS DQM DQ[0:7] DQM DQ[0:7] CK2 U2 CK1 CK: U0 CK0 RC CK: U1 RC CK: U2 RC CK: U3 RC C RC CK3 S1 CS DQMB1 R DQ[8:15] DQMB5 R DQ[40:47] 8 8 DQM DQ[0:7] DQM DQ[0:7] U1 DQMB3 R DQ[24:31] DQMB7 R DQ[56:63] 8 8 CS DQM DQ[0:7] DQM DQ[0:7] U3 R = 10 RC = 10 C = 10 pF VDD U[0:3] Two 0.1 F (minimum) per SDRAM U[0:3] C
PRODUCT PREVIEW
VSS
RAS CAS WE CKE0 A[0:11]
RAS: SDRAM U[0:3] CAS: SDRAM U[0:3] WE: SDRAM U[0:3] CKE: SDRAM U[0:3] A[0:11]: SDRAM U[0:3]
SPD EEPROM SCL A0 A1 VSS A2 SDA
LEGEND: CS = SPD =
Chip select Serial Presence Detect
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TM4SK64KPU 4194304 BY 64-BIT TM8SK64KPU 8388608 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULES -- SODIMM
SMMS691A - AUGUST 1997 - REVISED NOVEMBER 1997
functional block diagram for the TM8SK64KPU
S0 CS DQMB0 R DQ[0:7] DQMB4 R DQ[32:39] 8 8 DQM DQ[0:7] DQM DQ[0:7] U0 DQMB4 R DQ[32:39] DQMB0 R DQ[0:7] 8 8 S1 CS DQM DQ[0:7] DQM DQ[0:7] UB0 VSS VDD U[0:3], UB[0:3] Two 0.1 F (minimum) per SDRAM U[0:3], UB[0:3] R = 10 Rc = 10 VDD 10 K CS DQMB1 R DQ[8:15] DQMB5 R DQ[40:47] 8 8 DQM DQ[0:7] DQM DQ[0:7] U1 DQMB5 R DQ[40:47] DQMB1 R DQ[8:15] 8 8 CS DQM DQ[0:7] DQM DQ[0:7] UB1 CKE1 CKE0 RAS CAS WE A[0:13] CKE: UB[0:3] CKE: U[0:3] RAS: U[0:3], UB[0:3] CAS: U[0:3], UB[0:3] WE: U[0:3], UB[0:3]
CS DQMB2 R DQ[16:23] DQMB6 R DQ[48:55] 8 8 DQM DQ[0:7] DQM DQ[0:7] U2 DQMB6 R DQ[48:55] DQMB2 R DQ[16:23] 8 8
CS DQM DQ[0:7] DQM DQ[0:7] CK2 UB2 CK1 CK0
RC RC RC RC RC C
CK: U0, UB0 CK: U1, UB1 CK: U2, UB2 CK: U3, UB3
CS DQMB3 R DQ[24:31] DQMB7 R DQ[56:63] 8 8 DQM DQ[0:7] DQM DQ[0:7] U3 DQMB7 R DQ[56:63] DQMB3 R DQ[24:31] 8 8
CS DQM DQ[0:7] DQM DQ[0:7] SPD EEPROM SCL A0 A1 VSS A2 SDA UB3 RC CK3 C
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PRODUCT PREVIEW
A[0:13]: U[0:3], UB[0:3]
TM4SK64KPU 4194304 BY 64-BIT TM8SK64KPU 8388608 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULES -- SODIMM
SMMS691A - AUGUST 1997 - REVISED NOVEMBER 1997
absolute maximum ratings over ambient temperature range (unless otherwise noted)
Supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 4.6 V Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Power dissipation: TM4SK64KPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 W TM8SK64KPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 W Ambient temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 55C to 125C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
MIN VDD VSS VIH VIH-SPD VIL TA Supply voltage Supply voltage High-level input voltage High-level input voltage for the SPD device Low-level input voltage Ambient temperature 2 2 -0.3 0 3 NOM 3.3 0 VDD + 0.3 5.5 0.8 70 MAX 3.6 UNIT V V V V V C
PRODUCT PREVIEW
capacitance over recommended ranges of supply voltage and ambient temperature, f = 1 MHz (see Note 2)
PARAMETER Ci(CK) Ci(AC) Ci(CKE) Co Ci(DQMBx) Ci(Sx) Ci/o(SDA) Ci(SPD) Input capacitance, CK input Input capacitance, address and control inputs: A0 - A13, RAS, CAS, WE Input capacitance, CKE input Output capacitance Input capacitance, DQMBx input Input capacitance, Sx input Input/output capacitance, SDA input Input capacitance, SPD inputs (except SDA) TM4SK64KPU MIN MAX 12 22 22 10 7 22 9 7 TM8SK64KPU MIN MAX 22 42 22 16 12 22 9 7 UNIT pF pF pF pF pF pF pF pF
NOTE 2: VDD = 3.3 V 0.3 V. Bias on pins under test is 0 V.
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TM4SK64KPU 4194304 BY 64-BIT TM8SK64KPU 8388608 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULES -- SODIMM
SMMS691A - AUGUST 1997 - REVISED NOVEMBER 1997
electrical characteristics over recommended ranges of supply voltage and ambient (unless otherwise noted) (see Note 3)
TM4SK64KPU
PARAMETER VOH VOL II IO High-level output voltage Low-level output voltage Input current (leakage) Output current (leakage) IOH = - 2 mA IOL = 2 mA 0 V < VI < VDD + 0.3 V, All other pins = 0 V to VDD 0 V < VO < VDD +0.3 V, Output disabled Burst length = 1, tRC tRC MIN IOH/IOL = 0 mA, (see Notes 4, 5, and 6) CAS latency = 2 CAS latency = 3 TEST CONDITIONS '4SK64KPU-10 MIN 2.4 0.4 MAX '4SK64KPU-12 MIN 2.4 0.4 MAX UNIT V V A A mA mA mA mA mA mA mA mA mA mA mA mA mA mA
"10 "10
480 540 8 8 160 12 40 80 560 160 1000 1480 1 320 1 560
"10 "10
460 480 8 8 160 12 80 80 520 160 960 1 240 1 280 1 280
ICC1 ICC2P ICC2PS ICC2N ICC2NS ICC3P ICC3PS ICC3N ICC3NS
Operating current
Precharge standby current in CKE VIL MAX, tCK = 15 ns (see Note 7) g y power-down mode CKE and CK VIL MAX, tCK = (see Note 8) Precharge standby current in CKE VIH MIN, tCK = 15 ns (see Note 7) g y non-power-down mode tCK = (see Note 8) CKE VIL MAX, tCK = 15 ns (see Notes 4 and 7) Active standby current in CKE and CK VIL MAX, tCK = power-down mode (see Notes 4 and 8) CKE VIH MIN, tCK = 15 ns (see Notes 4 and 7) Active standby current in CKE VIH MIN, CK VIL MAX, tCK = non-power-down mode (see Notes 4 and 8) Page burst, IOH/IOL = 0 mA CAS latency = 2 All banks activated, , nCCD = one cycle CAS latency = 3 (see Notes 9 and 10) tRC tRC MIN (see Notes 5 and 8) CAS latency = 2 CAS latency = 3
ICC4
Burst current
ICC5
Auto refresh current Auto-refresh
ICC6 Self-refresh current CKE VIL MAX 16 16 mA NOTES: 3. All specifications apply to the device after power-up initialization. All control and address inputs must be stable and valid. 4. Only one bank is activated. 5. tRC MIN 6. Control and address inputs change state twice during tRC. 7. Control and address inputs change state once every 30 ns. 8. Control and address inputs do not change state (stable). 9. Control and address inputs change once every cycle. 10. Continuous burst access, nCCD = 1 cycle
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PRODUCT PREVIEW
TM4SK64KPU 4194304 BY 64-BIT TM8SK64KPU 8388608 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULES -- SODIMM
SMMS691A - AUGUST 1997 - REVISED NOVEMBER 1997
electrical characteristics over recommended ranges of supply voltage and ambient temperature (unless otherwise noted) (see Note 3)
TM8SK64KPU
PARAMETER VOH VOL II IO High-level output voltage Low-level output voltage Input current (leakage) Output current (leakage) IOH = - 2 mA IOL = 2 mA 0 V < VI < VDD + 0.3 V, All other pins = 0 V to VDD 0 V < VO < VDD +0.3 V, Output disabled Burst length = 1, tRC tRC MIN IOH/IOL = 0 mA, (see Notes 4, 5, and 6) CAS latency = 2 CAS latency = 3 TEST CONDITIONS '8SK64KPU-10 MIN 2.4 0.4 MAX '8SK64KPU-12 MIN 2.4 0.4 MAX UNIT V V A A mA mA mA mA mA mA mA mA mA mA mA mA mA mA
"10 "10
488 588 16 16 320 24 80 80 560 160 588 868 668 788
"10 "10
468 488 16 16 320 24 80 80 520 160 568 728 648 648
ICC1 ICC2P ICC2PS
Operating current
Precharge standby current in CKE VIL MAX, tCK = 15 ns (see Note 7) g y power-down mode CKE and CK VIL MAX, tCK = (see Note 8) Precharge standby current in CKE VIH MIN, tCK = 15 ns (see Note 7) g y non-power-down mode tCK = (see Note 8) CKE VIL MAX, tCK = 15 ns (see Notes 4 and 7) Active standby current in CKE and CK VIL MAX, tCK = power-down mode (see Notes 4 and 8) CKE VIH MIN, tCK = 15 ns (see Notes 4 and 7) Active standby current in CKE VIH MIN, CK VIL MAX, tCK = non-power-down mode (see Note 4 and 8) Page burst, IOH/IOL = 0 mA CAS latency = 2 All banks activated, , nCCD = one cycle CAS latency = 3 (see Notes 9 and 10) tRC tRC MIN (see Notes 5 and 8) CAS latency = 2 CAS latency = 3
PRODUCT PREVIEW
ICC2N ICC2NS ICC3P ICC3PS ICC3N ICC3NS
ICC4
Burst current
ICC5
Auto refresh current Auto-refresh
ICC6 Self-refresh current CKE VIL MAX 16 16 mA NOTES: 3. All specifications apply to the device after power-up initialization. All control and address inputs must be stable and valid. 4. Only one bank is activated. 5. tRC MIN 6. Control and address inputs change state twice during tRC. 7. Control and address inputs change state once every 30 ns. 8. Control and address inputs do not change state (stable). 9. Control and address inputs change once every cycle. 10. Continuous burst access, nCCD = 1 cycle
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TM4SK64KPU 4194304 BY 64-BIT TM8SK64KPU 8388608 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULES -- SODIMM
SMMS691A - AUGUST 1997 - REVISED NOVEMBER 1997
ac timing requirements
'xSK64KPU-10 MIN tCK2 tCK3 tCH tCL tAC2 tAC3 tOH tLZ tHZ tIS tIH tCESP tRAS tRC tRCD tRP tRRD tRSA tAPR tAPW tWR Cycle time, CK Cycle time, CK Pulse duration, CK high Pulse duraction, CK low Access time, CK high to data out (see Note 11) Access time, CK high to data out (see Note 11) Hold time, CK high to data out Delay time, CK high to DQ in low-impedance state (see Note 12) Delay time, CK high to DQ in high-impedance state (see Note 13) Setup time, address, control, and data input Hold time, address, control, and data input time address control Power down/self-refresh exit time Delay time, ACTV command to DEAC or DCAB command Delay time, ACTV,MRS,REFR,or SLFR to ACTV,MRS,REFR,or SLFR command Delay time ACTV command to READ,READ-P,WRT,or WRT-P command (see Note 14) Delay time, DEAC or DCAB command to ACTV,MRS,REFR, or SLFR command Delay time,ACTV command in one bank to ACTV command in the other bank Delay time,MRS command to ACTV,MRS,REFR,or SLFR command Final data out of READ-P operation to ACTV,MRS,SLFR,or REFR command Final data in of WRT-P operation to ACTV,MRS,SLFR,or REFR command Delay time, final data in of WRT operation to DEAC or DCAB command 10 3 1 10 50 80 30 30 20 20 CAS latency = 2 CAS latency = 3 3 2 8 3 1 12 60 90 30 30 24 24 tRP - (CL-1)* tCK tRP + 1 tCK 12 CAS latency = 2 CAS latency = 3 15 10 3 3 9 7.5 3 2 8 MAX 'xSK64KPU-12 MIN 15 12 4 4 9.5 8 MAX UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns
ns ns ns ns ns ns ns
tT Transition time 1 5 1 5 ms All references are made to the rising transition of CK unless otherwise noted. NOTES: 11. tAC is referenced from the rising transition of CK that precedes the data-out cycle. For example, the first data out tAC is referenced from the rising transition of CK that is read latency (one cycle after the READ command). Access time is measured at output reference level 1.4 V. 12. tLZ is measured from the rising transition of CK that is read latency (one cycle after the READ command). 13. tHZ (max) defines the time at which the outputs are no longer driven and is not referenced to output voltage levels. 14. For read or write operations with automatic deactivate, tRCD must be set to satisfy minimum tRAS.
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PRODUCT PREVIEW
ns
TM4SK64KPU 4194304 BY 64-BIT TM8SK64KPU 8388608 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULES -- SODIMM
SMMS691A - AUGUST 1997 - REVISED NOVEMBER 1997
clock timing requirements
'xSK64KPU-10 MIN tREF nCCD nCDD nCLE nCWL nDID nDOD nHZP2 nHZP3 Refresh interval Delay time READ or WRT command to an interrupting command time, Delay time, CS low or high to input enabled or inhibited Delay time, CKE high or low to CLK enabled or disabled Delay time, final data in of WRT operation to READ, READ-P, WRT, or WRT-P Delay time, ENBL or MASK command to enabled or masked data in Delay time, ENBL or MASK command to enabled or masked data out Delay time, DEAC or DCAB, command to DQ in high-impedance state Delay time, DEAC or DCAB, command to DQ in high-impedance state CAS latency = 2 CAS latency = 3 1 0 1 1 0 2 0 2 2 3 0 1 MAX 64 1 0 1 1 0 2 0 2 2 3 0 1 'xSK64KPU-12 MIN MAX 64 UNIT ms cycles cycles cycles cycles cycles cycles cycles cycles
PRODUCT PREVIEW
nWCD Delay time, WRT command to first data in 0 0 0 0 cycles All references are made to the rising transition of CK unless otherwise noted. A CK cycle can be considered as contributing to a timing requirement for those parameters defined in cycle units only when not gated by CKE (those CK cycles occurring during the time when CKE is asserted low).
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TM4SK64KPU 4194304 BY 64-BIT TM8SK64KPU 8388608 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULES -- SODIMM
SMMS691A - AUGUST 1997 - REVISED NOVEMBER 1997
serial presence detect
The serial presence detect (SPD) is contained in a 2K-bit serial EEPROM located on the module. The SPD nonvolatile EEPROM contains various data such as module configuration, SDRAM organization, and timing parameters (see tables below). Only the first 128 bytes are programmed by Texas Instruments, while the remaining 128 bytes are available for customer use. Programming is done through an IIC bus using the clock (SCL) and data (SDA) signals. All Texas Instruments modules comply with the current JEDEC SPD Standard. See the Texas Instruments Serial Presence Detect Technical Reference (literature number SMMU001) for further details. Tables in this section list the SPD contents as follow: Table 1--TM4SK64KPU. Table 2--TM8SK64KPU. Table 1. Serial-Presence-Detect Data for the TM4SK64KPU
BYTE NO. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 DESCRIPTION OF FUNCTION Defines number of bytes written into serial memory during module manufacturing Total number of bytes of SPD memory device Fundamental memory type (FPM, EDO, SDRAM, . . .) Number of row addresses on this assembly Number of column addresses on this assembly Number of module banks on this assembly Data width of this assembly Data width continuation Voltage interface standard of this assembly SDRAM cycle time at maximum supported CAS latency (CL), CL = X SDRAM access from clock at CL = X SODIMM configuration type (non-parity, parity, error correcting code [ECC]) Refresh rate / type SDRAM width, primary DRAM Error-checking SDRAM data width Minimum clock delay, back-to-back random column addresses Burst lengths supported Number of banks on each SDRAM device CAS latencies supported CS latency Write latency SDRAM module attributes LVTTL tCK = 10 ns tAC = 7.5 ns Non-Parity 15.6 s/ self-refresh x16 N/A 1 CK cycle 1, 2, 4, 8, full page 4 banks 2, 3 0 0 Non-buffered/ Non-registered VDD tolerance = ("10%), Burst read / write, precharge all, auto precharge tCK = 15 ns TM4SK64KPU-10 ITEM 128 bytes 256 bytes SDRAM 12 8 1 bank 64 bits DATA 80h 08h 04h 0Ch 08h 01h 40h 00h 01h A0h 75h 00h 80h 10h 00h 01h 8Fh 04h 06h 01h 01h 00h LVTTL tCK = 12 ns tAC = 8 ns Non-Parity 15.6 s/ self-refresh x16 N/A 1 CK cycle 1, 2, 4, 8, full page 4 banks 2, 3 0 0 Non-buffered/ Non-registered VDD tolerance = ("10%), Burst read / write, precharge all, auto precharge tCK = 15 ns TM4SK64KPU-12 ITEM 128 bytes 256 bytes SDRAM 12 8 1 bank 64 bits DATA 80h
04h 0Ch 08h 01h 40h 00h 01h C0h 80h 00h 80h 10h 00h 01h 8Fh 04h 06h 01h 01h 00h
22
SDRAM device attributes: general
0Eh
0Eh
23
Minimum clock cycle time at CL = X - 1
F0h
F0h
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PRODUCT PREVIEW
08h
TM4SK64KPU 4194304 BY 64-BIT TM8SK64KPU 8388608 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULES -- SODIMM
SMMS691A - AUGUST 1997 - REVISED NOVEMBER 1997
serial presence detect (continued)
Table 1. Serial-Presence-Detect Data for the TM4SK64KPU (Continued)
BYTE NO. 24 25 26 27 28 29 30 31 32 - 61 62 63 64 - 71 DESCRIPTION OF FUNCTION Maximum data-access time from clock at CL = X - 1 Minimum clock cycle time at CL = X - 2 Maximum data-access time from clock at CL = X - 2 Minimum row precharge time Minimum row-active to row-active delay Minimum RASx-to-CASx delay Minimum RASx pulse width Density of each bank on module Superset features (may be used in the future) SPD revision Checksum for byte 0 - 62 Manufacturer's JEDEC ID code per JEP - 106E Manufacturing location Manufacturer's part number Die revision code PCB revision code Manufacturing date Assembly serial number Manufacturer specific data Vendor specific data System integrator's specific data Open Rev. 1 60 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD 01h 3Ch 9700...00h Rev. 1 122 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD 01h 7Ah 9700...00h TM4SK64KPU-10 ITEM tAC = 9 ns N/A N/A tRP = 30 ns tRRD = 20 ns tRCD = 30 ns tRAS = 50 ns 32M Bytes DATA 90h 00h 00h 1Eh 14h 1Eh 32h 08h TM4SK64KPU-12 ITEM tAC = 9.5ns N/A N/A tRP = 30 ns tRRD = 24 ns tRCD = 30 ns tRAS = 60 ns 32M Bytes DATA 95h 00h 00h 1Eh 18h 1Eh 3Ch 08h
PRODUCT PREVIEW
72 73 - 90 91 92 93 - 94 95 - 98 99 - 125 126 - 127 128-166 167-255
TBD indicates values are determined at manufacturing time and are module dependent. These TBD values are determined and programmed by the customer (optional).
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TM4SK64KPU 4194304 BY 64-BIT TM8SK64KPU 8388608 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULES -- SODIMM
SMMS691A - AUGUST 1997 - REVISED NOVEMBER 1997
serial presence detect (continued)
Table 2. Serial-Presence-Detect Data for the TM8SK64KPU
BYTE NO. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 DESCRIPTION OF FUNCTION Defines number of bytes written into serial memory during module manufacturing Total number of bytes of SPD memory device Fundamental memory type (FPM, EDO, SDRAM, . . .) Number of row addresses on this assembly Number of column addresses on this assembly Number of module banks on this assembly Data width of this assembly Data width continuation Voltage interface standard of this assembly SDRAM cycle time at maximum supported CAS latency (CL), CL = X SDRAM access from clock at CL = X SODIMM configuration type (non-parity, parity, error correcting code [ECC]) Refresh rate / type SDRAM width, primary DRAM Error-checking SDRAM data width Minimum clock delay, back-to-back random column addresses Burst lengths supported Number of banks on each SDRAM device CAS latencies supported CS latency Write latency SDRAM module attributes LVTTL tCK = 10 ns tAC = 7.5 ns Non-Parity 15.6 s/ self-refresh x16 N/A 1 CK cycle 1, 2, 4, 8, full page 4 banks 2, 3 0 0 Non-buffered/ Non-registered VDD tolerance = ("10%), Burst read / write, precharge all, auto precharge tCK = 15 ns tAC = 9 ns N/A N/A TM8SK64KPU-10 ITEM 128 bytes 256 bytes SDRAM 12 8 2 banks 64 bits DATA 80h 08h 04h 0Ch 08h 02h 40h 00h 01h A0h 75h 00h 80h 10h 00h 01h 8Fh 04h 06h 01h 01h 00h LVTTL tCK = 12 ns tAC = 8 ns Non-Parity 15.6 s/ self-refresh x16 N/A 1 CK cycle 1, 2, 4, 8, full page 4 banks 2, 3 0 0 Non-buffered/ Non-registered VDD tolerance = ("10%), Burst read / write, precharge all, auto precharge tCK = 15 ns tAC = 9.5 ns N/A N/A TM8SK64KPU-12 ITEM 128 bytes 256 bytes SDRAM 12 8 2 banks 64 bits DATA 80h 08h 04h 0Ch 08h 02h 40h 00h 01h C0h 80h 00h 80h 10h 00h 01h 8Fh 04h 06h 01h 01h 00h
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SDRAM device attributes: general
0Eh
0Eh
23 24 25 26
Minimum clock cycle time at CL = X - 1 Maximum data-access time from clock at CL = X - 1 Minimum clock cycle time at CL = X - 2 Maximum data-access time from clock at CL = X - 2
F0h 90h 00h 00h
F0h 95h 00h 00h
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PRODUCT PREVIEW
TM4SK64KPU 4194304 BY 64-BIT TM8SK64KPU 8388608 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULES -- SODIMM
SMMS691A - AUGUST 1997 - REVISED NOVEMBER 1997
serial presence detect (continued)
Table 2. Serial-Presence-Detect Data for the TM8SK64KPU (Continued)
BYTE NO. 27 28 29 30 31 32-61 62 63 64 - 71 72 73 - 90 91 DESCRIPTION OF FUNCTION Minimum row precharge time Minimum row-active to row-active delay Minimum RAS-to-CAS delay Minimum RAS pulse width Density of each bank on module Superset features (may be used in the future) SPD revision Checksum for byte 0 - 62 Manufacturer's JEDEC ID code per JEP - 106E Manufacturing location Manufacturer's part number Die revision code PCB revision code Manufacturing date Assembly serial number Manufacturer specific data Vendor specific data System integrator's specific data Open Rev. 1 61 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD 01h 3Dh 9700...00h Rev. 1 123 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD 01h 7Bh 9700...00h TM8SK64KPU-10 ITEM tRP = 30 ns tRRD = 20 ns tRCD = 30 ns tRAS = 50 ns 32M Bytes DATA 1Eh 14h 1Eh 32h 08h TM8SK64KPU-12 ITEM tRP = 30 ns tRRD = 24 ns tRCD = 30 ns tRAS = 60 ns 32M Bytes DATA 1Eh 18h 1Eh 3Ch 08h
PRODUCT PREVIEW
92 93 - 94 95 - 98 99 - 125 126 - 127 128-166 167-255
TBD indicates values are determined at manufacturing time and are module dependent. These TBD values are determined and programmed by the customer (optional).
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TM4SK64KPU 4194304 BY 64-BIT TM8SK64KPU 8388608 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULES -- SODIMM
SMMS691A - AUGUST 1997 - REVISED NOVEMBER 1997
device symbolization (TM4SK64KPU)
TM4SK64KPU YY MM T -SS = = = =
-SS Year Code Month Code Assembly Site Code Speed Code
YYMMT
NOTE A: Location of symbolization may vary.
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15
PRODUCT PREVIEW
TM4SK64KPU 4194304 BY 64-BIT TM8SK64KPU 8388608 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULES -- SODIMM
SMMS691A - AUGUST 1997 - REVISED NOVEMBER 1997
MECHANICAL DATA
BDQ (R-SODIMM-N144) SMALL OUTLINE DUAL IN-LINE MEMORY MODULE
2.665 (67,69) 2.655 (67,44) Notch 0.157 (4,00) x 0.079 (2,00) Deep 2 Places Notch 0.060 (1,52) x 0.158 (4,01) Deep 0.044 (1,12) 0.036 (0,91)
PRODUCT PREVIEW
0.024 (0,61) TYP 0.098 (2,49) 0.196 (4,98)
0.031 (0,79)
0.010 (0,25) MAX 0.788 (20,00) TYP 1.130 (28,70) 1.120 (28,45) 0.157 (4,00) 0.126 (3,20) 0.095 (2,41) MAX 0.150 (3,81) MAX (For Double-Sided Module Only) 4088188/A 07/97
NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MO-190
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