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TM2EJ64DPN, TM2FJ64DPN 2097152 BY 64-BIT TM2EJ64EPN, TM2FJ64EPN 2097152 BY 64-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES -- SODIMM
SMMS685 - AUGUST 1997
D D D D D
Organization - TM2xJ64xPN-xx . . . 2 097152 x 64 Bits Single 3.3-V Power Supply (10% Tolerance) JEDEC 144-Pin Small Outline Dual-In-Line Memory Module (SODIMM) Without Buffer for Use With Socket TM2xJ64xPN-xx -- Utilizes Eight 16M-Bit (2M x 8-Bit) Dynamic RAMs in TSOPs Performance ranges
ACCESS ACCESS ACCESS TIME TIME TIME tRAC tCAC tAA MAX MAX MAX 50 ns 13 ns 25 ns 60 ns 15 ns 30 ns 70 ns 18 ns 35 ns EDO CYCLE tHPC MIN 20 ns 25 ns 30 ns
D D D D D D D D
'2xJ64xPN-50 '2xJ64xPN-60 '2xJ64xPN-70
High-Speed, Low-Noise LVTTL Interface Long Refresh Period: - TM2EJ64DPN: 32 ms (2 048 cycles) - TM2EJ64EPN: 64 ms (4 096 cycles) Low-Power, Battery-Backup Refresh Available: - TM2FJ64DPN: 128 ms (2048 cycles) - TM2FJ64EPN: 128 ms (4 096 cycles) 3-State Output Extended-Data-Out (EDO) Operation With CAS-Before-RAS (CBR), RAS-Only, and Hidden Refresh Serial Presence-Detect (SPD) Using EEPROM Ambient Temperature Range 0C to 70C Gold-Plated Contacts
description
The TM2EJ64DPN is a 16M-byte, 144-pin, small outline dual-in-line memory module (SODIMM). The SODIMM is composed of eight TMS427809A, 2 097 152 x 8-bit 2K-refresh EDO dynamic random-access memories (DRAMs), each in a 400-mil, 28-pin plastic thin small-outline package (TSOP) (DGC suffix) mounted on a substrate with decoupling capacitors. See the TMS427809A data sheet (literature number SMKS894). The TM2EJ64EPN is an 16M-byte, 144-pin SODIMM. The SODIMM is composed of eight TMS426809A, 2 097 152 x 8-bit 4K-refresh EDO DRAMs, each in a 400-mil, 28-pin plastic TSOP (DGC suffix) mounted on a substrate with decoupling capacitors. See the TMS426809A data sheet (literature number SMKS894). The TM2FJ64DPN is a 16M-byte, 144-pin SODIMM. The SODIMM is composed of eight TMS427809AP, 2 097 152 x 8-bit 2K low-power battery-backup refresh EDO DRAMs, each in a 400-mil, 28-pin plastic TSOP (DGC suffix) mounted on a substrate with decoupling capacitors. See the TMS427809AP data sheet (literature number SMKS894). The TM2FJ64EPN is a 16M-byte, 144-pin SODIMM. The SODIMM is composed of eight TMS426809AP, 2 097 152 x 8-bit 4K low-power battery-backup refresh EDO DRAMs, each in a 400-mil, 28-pin plastic TSOP (DGC suffix) mounted on a substrate with decoupling capacitors. See the TMS426809AP data sheet (literature number SMKS894).
operation
The TM2xJ64xPN operates as eight TMS42x809A/Ps, connected as shown in the functional block diagram.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright (c) 1997, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
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1
PRODUCT PREVIEW
TM2EJ64DPN, TM2FJ64DPN 2097152 BY 64-BIT TM2EJ64EPN, TM2FJ64EPN 2097152 BY 64-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES -- SODIMM
SMMS685 - AUGUST 1997
DUAL-IN-LINE MEMORY MODULE ( TOP VIEW )
TM2xJ64xPN ( SIDE VIEW ) A[0:11] A[0:9] DQ[0:63] CAS[0:7] RAS0 WE0 OE0 SDA SCL NC VDD VSS
PIN NOMENCLATURE Row Address Inputs Column Address Inputs Data In / Data Out Column-Address Strobe Row-Address Strobe Write Enable Output Enable Serial PD Address / Data Serial PD Clock No-Connect Pin 3.3-V Supply Ground
1
A11 is NC for TM2xJ64DPN
59
PRODUCT PREVIEW
61
143
2
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AAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAA A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A A AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A A AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A A AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AA A A A A A A AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AA A AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAAAAAAAAA A AA AA A A AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAA
NO. 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 10 11 9 8 7 6 5 4 3 2 1 PIN NAME CAS5 CAS1 CAS4 CAS0 DQ39 DQ38 DQ37 DQ36 DQ35 DQ34 DQ33 DQ32 VDD VDD VDD VDD DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 VSS VSS VSS VSS VSS VSS A5 A2 A4 A1 A3 A0 NO. 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37
TM2EJ64DPN, TM2FJ64DPN 2097152 BY 64-BIT TM2EJ64EPN, TM2FJ64EPN 2097152 BY 64-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES -- SODIMM
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PIN NAME
Pin Assignments
RAS0
DQ45
DQ13
DQ44
DQ12
DQ43
DQ42
DQ10
DQ41
DQ40
DQ11
VDD VDD
DQ9
DQ8
NO.
86
85
84
83
82
81
80
79
78
77
76
75
74
73
PIN NAME
DQ49
DQ17
DQ48
DQ16
VDD VDD
VSS VSS
NC
NC
NC
NC
NC
OE
NO.
122
121AAAAAA DQ24
120
109
119
118
117
116
115
114
113
112AAAAAA NC
110
111
PIN NAME
DQ56
CAS7
CAS3
CAS6
CAS2
SMMS685 - AUGUST 1997
VDD VDD
VSS VSS
A10
NC
A9
PRODUCT PREVIEW
DQ47
DQ15
DQ46
DQ14
WE0
VDD VDD
VSS VSS
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
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108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 DQ55 DQ23 DQ54 DQ22 DQ53 DQ21 DQ52 DQ20 DQ51 DQ19 DQ50 DQ18 VDD VDD VSS VSS VSS VSS A11 A8 A7 A6 144 143 142 141 140 139 138AAAAAA DQ63 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 DQ31 DQ62 DQ30 DQ61 DQ29 DQ60 DQ28 DQ59 DQ27 DQ58 DQ26 DQ57 DQ25 VDD VDD VDD VDD SDA VSS VSS SCL
3
TM2EJ64DPN, TM2FJ64DPN 2097152 BY 64-BIT TM2EJ64EPN, TM2FJ64EPN 2097152 BY 64-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES -- SODIMM
SMMS685 - AUGUST 1997
small outline dual-in-line memory module and components
The small-outline dual-in-line memory module and components include:
D D D
PC substrate: 1,10
" 0,1 mm (0.04 inch) nominal thickness
Bypass capacitors: Multilayer ceramic Contact area: Nickel plate and gold plate over copper
functional block diagram for the TM2xJ64xPN
RAS0 WE0 OE0 CAS0 DQ[0:7] CAS OE W RAS DQ[0:7] U0 RAS0 WE0 OE0 CAS4 DQ[32:39] CAS OE W RAS
DQ[0:7] UB0
PRODUCT PREVIEW
CAS1 DQ[8:15]
CAS OE W RAS DQ[0:7] U1
CAS5 DQ[40:47]
CAS
OE W RAS
DQ[0:7] UB1
CAS2 DQ[16:23]
CAS OE W RAS DQ[0:7] U2
CAS6 DQ[48:55]
CAS
OE W RAS
DQ[0:7] UB2
CAS3 DQ[24:31]
CAS OE W RAS DQ[0:7] U3
CAS7 DQ[56:63]
CAS
OE W RAS
DQ[0:7] UB3
TM2xJ64DPN: A[0 : 10] TM2xJ64EPN: A[0: 11] A[0: 11] : U[0: 3], UB[0: 3] VSS VDD U[0:3], UB[0:3] Two 0.1 F (minimum) per DRAM U[0:3], UB[0:3] A[0 :10] : U[0: 3], UB[0: 3] SCL SPD EEPROM A0 A1 A2 SDA
VSS
4
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TM2EJ64DPN, TM2FJ64DPN 2097152 BY 64-BIT TM2EJ64EPN, TM2FJ64EPN 2097152 BY 64-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES -- SODIMM
SMMS685 - AUGUST 1997
absolute maximum ratings over ambient temperature range (unless otherwise noted)
Supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 4.6 V Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Power dissipation: TM2xP64DPN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 W TM2xP64EPN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 W Ambient temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 55C to 125C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS.
VIL TA
Low-level input voltage Ambient temperature
-0.3 0
0.8 70
V
C
capacitance over recommended ranges of supply voltage and ambient temperature, f = 1 MHz (see Note 2)
PARAMETER Ci(A) Ci(OE) Ci(CAS) Ci(RAS) Ci(W) Co Ci/o(SDA) Input capacitance, A0 - A10 Input capacitance, OE0 Input capacitance, CASx Input capacitance, RAS0 Input capacitance, WE0 Output capacitance Input/output capacitance, SDA input '2xJ64xPN MIN MAX 42 58 9 58 58 9 9 7 UNIT pF pF pF pF pF pF pF pF
Ci(SPD) Input capacitance, SA0, SA1, SA2, SCL inputs NOTE 2: VDD = NOM supply voltage 10%, and the bias on pins under test is 0 V.
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PRODUCT PREVIEW
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MIN 3 2 2 NOM MAX 3.6 UNIT V V V V VDD VSS Supply voltage Supply voltage 3.3 0 VIH VIH-SPD High-level input voltage High-level input voltage for the SPD device VDD + 0.3 5.5
recommended operating conditions
TM2EJ64DPN, TM2FJ64DPN 2097152 BY 64-BIT TM2EJ64EPN, TM2FJ64EPN 2097152 BY 64-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES -- SODIMM
SMMS685 - AUGUST 1997
electrical characteristics over recommended ranges of supply voltage and ambient temperature (unless otherwise noted)
TM2EJ64DPN
PARAMETER VOH VOL II IO ICC1 High-level output g voltage Low-level output voltage Input current (leakage) Output current (leakage) Read- or write-cycle current TEST CONDITIONS IOH = - 2 mA IOH = - 100 A IOL = 2 mA LVTTL LVCMOS LVTTL '2EJ64DPN-50 MIN 2.4 VDD - 0.2 0.4 0.2 10 10 MAX '2EJ64DPN-60 MIN 2.4 VDD- 0.2 0.4 0.2 10 10 MAX '2EJ64DPN-70 MIN 2.4 VDD - 0.2 0.4 0.2 10 10 MAX UNIT V V A A
IOL = 100 A LVCMOS VDD = 3.6 V, VI = 0 V to 3.9 V, All others = 0 V to VDD VDD = 3.6 V, CASx high VDD = 3.6 V, VO = 0 V to VDD,
Minimum cycle
960
800
720
mA
PRODUCT PREVIEW
ICC2
Standby current
VIH = 2 V (LVTTL), After one memory cycle, RAS0 and CASx high VIH = VDD - 0.2 V (LVCMOS), After one memory cycle, RAS0 and CASx high VDD= 3.6 V, Minimum cycle, RAS0 cycling, CASx high (RAS-only refresh), RAS0 low after CASx low (CBR) VDD = 3.6 V, RAS0 low, tHPC = MIN, CASx cycling
16
16
16
mA
8
8
8
mA
ICC3
Average refresh current (RAS-only refresh or CBR) Average EDO current
960
800
720
mA
ICC4
880
720
640
mA
For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements. Measured with outputs open Measured with a maximum of one address change while RAS0 = VIL Measured with a maximum of one address change during each EDO cycle, tHPC
6
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TM2EJ64DPN, TM2FJ64DPN 2097152 BY 64-BIT TM2EJ64EPN, TM2FJ64EPN 2097152 BY 64-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES -- SODIMM
SMMS685 - AUGUST 1997
electrical characteristics over recommended ranges of supply voltage and ambient temperature (unless otherwise noted)
TM2EJ64EPN
PARAMETER VOH VOL II IO ICC1 High-level output g voltage Low-level output voltage Input current (leakage) Output current (leakage) Read- or write-cycle current TEST CONDITIONS IOH = - 2 mA IOH = - 100 A IOL = 2 mA LVTTL LVCMOS LVTTL '2EJ64EPN-50 MIN 2.4 VDD - 0.2 0.4 0.2 10 10 MAX '2EJ64EPN-60 MIN 2.4 VDD - 0.2 0.4 0.2 10 10 MAX '2EJ64EPN-70 MIN 2.4 VDD- 0.2 0.4 0.2 10 10 MAX UNIT V V A A
IOL = 100 A LVCMOS VDD = 3.6 V, VI = 0 V to 3.9 V, All others = 0 V to VDD VDD = 3.6 V, CASx high VDD = 3.6 V, VO = 0 V to VDD,
Minimum cycle
720
560
480
mA
ICC2
Standby current
VIH = VDD - 0.2 V (LVCMOS), After one memory cycle, RAS0 and CASx high VDD = 3.6 V, Minimum cycle, RASx cycling, CASx high (RAS-only refresh), RAS0 low after CASx low (CBR) VDD = 3.6 V, RAS0 low, tHPC = MIN, CASx cycling
8
8
8
mA
ICC3
Average refresh current (RAS-only refresh or CBR) Average EDO current
720
560
480
mA
ICC4
800
720
640
mA
For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements. Measured with outputs open Measured with a maximum of one address change while RAS0 = VIL Measured with a maximum of one address change during each EDO cycle, tHPC
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PRODUCT PREVIEW
VIH = 2 V (LVTTL), After one memory cycle, RAS0 and CASx high
16
16
16
mA
TM2EJ64DPN, TM2FJ64DPN 2097152 BY 64-BIT TM2EJ64EPN, TM2FJ64EPN 2097152 BY 64-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES -- SODIMM
SMMS685 - AUGUST 1997
electrical characteristics over recommended ranges of supply voltage and ambient temperture (unless otherwise noted) (continued)
TM2FJ64DPN
PARAMETER VOH VOL II IO ICC1 High-level output g voltage Low-level output voltage Input current (leakage) Output current (leakage) Read- or write-cycle current TEST CONDITIONS IOH = - 2 mA IOH = - 100 A IOL = 2 mA LVTTL LVCMOS LVTTL '2FJ64DPN-50 MIN 2.4 VDD - 0.2 0.4 0.2 10 10 MAX '2FJ64DPN-60 MIN 2.4 VDD - 0.2 0.4 0.2 10 10 MAX '2FJ64DPN-70 MIN 2.4 VDD - 0.2 0.4 0.2 10 10 MAX UNIT V V A A
IOL = 100 A LVCMOS VDD = 3.6 V, VI = 0 V to 3.9 V, All others = 0 V to VDD VDD = 3.6 V, CASx high VDD = 3.6 V, VO = 0 V to VDD,
Minimum cycle
960
800
720
mA
PRODUCT PREVIEW
ICC2
Standby current
VIH = 2 V (LVTTL), After one memory cycle, RAS0 and CASx high VIH = VDD - 0.2 V (LVCMOS), After one memory cycle, RAS0 and CASx high VDD= 3.6 V, Minimum cycle, RAS0 cycling, CASx high (RAS-only refresh), RAS0 low after CASx low (CBR) VDD = 3.6 V, RAS0 low, tHPC = MIN, CASx cycling
8
8
8
mA
1.2
1.2
1.2
mA
ICC3
Average refresh current (RAS-only refresh or CBR) Average EDO current Average self-refresh current Average battery back-up operating current (equivalent refresh time is 128 ms), CBR only
960
800
720
mA
ICC4 ICC6
880
720
640
mA
CASx < 0.2 V, RAS0 < 0.2 V, Measured after tRASS min tRC = 31.25 s, tRAS 300 ns VDD - 0.2 V VIH 3.9 V, 0 V VIL 0.2 V, WE0 and OE0 = VIH, Address and data stable
1.6
1.6
1.6
mA
ICC10
2.8
2.8
2.8
mA
For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements. Measured with outputs open Measured with a maximum of one address change while RAS0 = VIL Measured with a maximum of one address change during each EDO cycle, tHPC
8
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TM2EJ64DPN, TM2FJ64DPN 2097152 BY 64-BIT TM2EJ64EPN, TM2FJ64EPN 2097152 BY 64-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES -- SODIMM
SMMS685 - AUGUST 1997
electrical characteristics over recommended ranges of supply voltage and ambient temperature (unless otherwise noted) (continued)
TM2FJ64EPN
PARAMETER VOH VOL II IO ICC1 High-level output g voltage Low-level output voltage Input current (leakage) Output current (leakage) Read- or write-cycle current TEST CONDITIONS IOH = - 2 mA IOH = - 100 A IOL = 2 mA LVTTL LVCMOS LVTTL '2FJ64EPN-50 MIN 2.4 VDD - 0.2 0.4 0.2 10 10 MAX '2FJ64EPN-60 MIN 2.4 VDD - 0.2 0.4 0.2 10 10 MAX '2FJ64EPN-70 MIN 2.4 VDD - 0.2 0.4 0.2 10 10 MAX UNIT V V A A
IOL = 100 A LVCMOS VDD = 3.6 V, VI = 0 V to 3.9 V, All others = 0 V to VDD VDD = 3.6 V, CASx high VDD = 3.6 V, VO = 0 V to VDD,
Minimum cycle
720
560
480
mA
ICC2
Standby current
VIH = VDD - 0.2 V (LVCMOS), After one memory cycle, RAS0 and CASx high VDD = 3.6 V, Minimum cycle, RAS0 cycling, CASx high (RAS-only refresh), RAS0 low after CASx low (CBR) VDD = 3.6 V, RAS0 low, tHPC = MIN, CASx cycling
1.2
1.2
1.2
mA
ICC3
Average refresh current (RAS-only refresh or CBR) Average EDO current Average self-refresh current Average battery back-up operating current (equivalent refresh time is 128 ms), CBR only
720
560
480
mA
ICC4 ICC6
800
720
640
mA
CASx < 0.2 V, RAS0 < 0.2 V, Measured after tRASS min tRC = 31.25 s, tRAS 300 ns VDD - 0.2 V VIH 3.9 V, 0 V VIL 0.2 V, WE0 and OE0 = VIH, Address and data stable
2
2
2
mA
ICC10
2.8
2.8
2.8
mA
For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements. Measured with outputs open Measured with a maximum of one address change while RAS0 = VIL Measured with a maximum of one address change during each EDO cycle, tHPC
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PRODUCT PREVIEW
VIH = 2 V (LVTTL), After one memory cycle, RAS0 and CASx high
8
8
8
mA
TM2EJ64DPN, TM2FJ64DPN 2097152 BY 64-BIT TM2EJ64EPN, TM2FJ64EPN 2097152 BY 64-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES -- SODIMM
SMMS685 - AUGUST 1997
switching characteristics over recommended ranges of supply voltage and ambient temperature (see Note 3)
PARAMETER tAA tCAC tCPA tRAC tOEA tCLZ tREZ tCEZ tOEZ tWEZ Access time from column address (see Note 4) Access time from CASx (see Note 4) Access time from CASx precharge (see Note 4) Access time from RAS0 (see Note 4) Access time from OE0 (see Note 4) Delay time, CASx to output in low impedance Output buffer turn off delay from RAS0 (see Note 5) Output buffer turn off delay from CASx (see Note 5) Output buffer turn off delay from OE0 (see Note 5) Output buffer turn off delay from WE0 (see Note 5) 0 3 3 3 3 13 13 13 13 '2XJ64xPN-50 MIN MAX 25 13 28 50 13 0 3 3 3 3 15 15 15 15 '2XJ64xPN-60 MIN MAX 30 15 35 60 15 0 3 3 3 3 18 18 18 18 '2XJ64xPN-70 MIN MAX 35 18 40 70 18 UNIT ns ns ns ns ns ns ns ns ns ns
PRODUCT PREVIEW
NOTES: 3. With ac parameters, it is assumed that tT = 2 ns. 4. Access times are measured with output reference levels of VOH = 2 V and VOL = 0.8 V. 5. The maximum values of tREZ, tCEZ, tOEZ, and tWEZ are specified when the outputs are no longer driven. Data-in should not be driven until one of the applicable maximum values is satisfied.
EDO timing requirements (see Note 3)
'2XJ64xPN-50 MIN tHPC tPRWC tCSH tCHO tDOH tCAS tWPE tCP tOCH tOEP Cycle time, EDO page mode, read-write Cycle time, EDO read-write Delay time, RAS0 active to CASx precharge Hold time, OE0 from CASx Hold time, output from CASx Pulse duration, CASx active Pulse duration, WE0 active (output disable only) Pulse duration, CASx precharge Setup time, OE0 before CASx Precharge time, OE0 20 57 40 7 5 8 7 8 8 5 10 000 MAX '2XJ64xPN-60 MIN 25 68 48 10 5 10 7 10 10 5 10 000 MAX '2XJ64xPN-70 MIN 30 78 58 10 5 12 7 10 10 5 10 000 MAX UNIT ns ns ns ns ns ns ns ns ns ns
NOTE 3: With ac parameters, it is assumed that tT = 2 ns.
10
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TM2EJ64DPN, TM2FJ64DPN 2097152 BY 64-BIT TM2EJ64EPN, TM2FJ64EPN 2097152 BY 64-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES -- SODIMM
SMMS685 - AUGUST 1997
ac timing requirements (see Note 3)
'2xJ64xPN-50 MIN tRC tRWC tRASP tRAS tRP tWP tRASS tRPS tASC tASR tDS tRCS tCWL tRWL tWCS tWRP tCSR tCAH tDH tRAH tRCH tRRH tWCH tROH tWRH tCHR tOEH tRHCP tCHS tAWD Cycle time, random read or write Cycle time, read-write Pulse duration, RAS0 active, fast page mode (see Note 6) Pulse duration, RAS0 active, non-page mode (see Note 6) Pulse duration, RAS0 precharge Pulse duration, write command Pulse duration, RAS0 active, self refresh (see Note 7) Pulse duration, RAS0 precharge after self refresh Setup time, column address Setup time, row address Setup time, data in (see Note 8) Setup time, read command Setup time, write command before CASx precharge Setup time, write command before RAS0 precharge Setup time, write command before CASx active (early-write only) Setup time, WE0 high before RAS0 low (CBR refresh only) Setup time, CASx referenced to RAS0 ( CBR refresh only ) Hold time, column address Hold time, data in (see Note 8) Hold time, row address Hold time, read command referenced to CASx (see Note 9) Hold time, read command referenced to RAS0 (see Note 9) Hold time, write command during CASx active ( early-write only ) Hold time, RAS0 referenced to OE0 Hold time, WE0 high after RAS0 low (CBR refresh only) Hold time, CASx referenced to RAS0 ( CBR refresh only ) Hold time, OE0 command Hold time, RAS0 active from CASx precharge Hold time, CASx referenced to RAS0 (self refresh only) Delay time, column address to write command ( read-write only ) 84 111 50 50 30 8 100 90 0 0 0 0 8 8 0 10 5 8 8 8 0 0 8 8 10 10 13 28 - 50 42 100 000 10 000 MAX '2xJ64xPN-60 MIN 104 135 60 60 40 10 100 110 0 0 0 0 10 10 0 10 5 10 10 10 0 0 10 10 10 10 15 35 - 50 49 100 000 10 000 MAX '2xJ64xPN-70 MIN 124 160 70 70 50 10 100 130 0 0 0 0 12 12 0 10 5 12 12 10 0 0 12 10 10 10 18 40 - 50 57 100 000 10 000 MAX UNIT ns ns ns ns ns ns
ms
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tCRP Delay time, CASx precharge to RAS0 5 5 5 ns NOTES: 3. With ac parameters, it is assumed that tT = 2 ns. 6. In a read-write cycle, tRWD and tRWL must be observed. 7. During the period of 10 s tRASS 100 s, the device is in a transition state from normal-operation mode to self-refresh mode. 8. Referenced to the later of CASx or WE0 in write operations 9. Either tRRH or tRCH must be satisfied for a read cycle.
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11
PRODUCT PREVIEW
TM2EJ64DPN, TM2FJ64DPN 2097152 BY 64-BIT TM2EJ64EPN, TM2FJ64EPN 2097152 BY 64-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES -- SODIMM
SMMS685 - AUGUST 1997
ac timing requirements (see Note 3) (continued)
'2xJ64xPN-50 MIN tCWD tOED tRAD tRAL tCAL tRCD tRPC tRSH tRWD tCPW Delay time, CASx to write command (read-write only) Delay time, OE0 to data in Delay time, RAS0 to column address (see Note 10) Delay time, column address to RAS0 precharge Delay time, column address to CASx precharge Delay time, RAS0 to CASx (see Note 10) Delay time, RAS0 precharge to CASx Delay time, CASx active to RAS0 precharge Delay time, RAS0 to write command (read-write only) Delay time, CASx precharge to write command (read-write only) '2EJ64DPN tREF Refresh time interval '2EJ64EPN '2FJ64xPN tT Transition time NOTES: 3. With ac parameters, it is assumed that tT = 2 ns. 10. The maximum value is specified only to ensure access time. 2 0 0 8 8 0 5 5 8 67 45 32 64 128 30 2 MAX '2xJ64xPN-60 MIN 0 0 10 10 0 5 5 10 79 54 32 64 128 30 2 MAX '2xJ64xPN-70 MIN 0 0 12 12 0 5 5 12 92 62 32 64 128 30 ns MAX UNIT ns ns ns ns ns ns ns ns ns ns ms
PRODUCT PREVIEW
12
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TM2EJ64DPN, TM2FJ64DPN 2097152 BY 64-BIT TM2EJ64EPN, TM2FJ64EPN 2097152 BY 64-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES -- SODIMM
SMMS685 - AUGUST 1997
serial presence detect
The serial presence detect (SPD) is contained in a 2K-bit serial EEPROM located on the module. The SPD nonvolatile EEPROM contains various data such as module configuration, DRAM organization, and timing parameters (see tables below). Only the first 128 bytes are programmed by Texas Instruments, while the remaining 128 bytes are available for customer use. Programming is done through an IIC bus using the clock (SCL) and data (SDA) signals. All Texas Instruments modules comply with the current JEDEC SPD Standard. See the Texas Instruments Serial Presence Detect Technical Reference (literature number SMMU001) for further details. Tables in this section list the SPD contents as follows: Table 1-TM2EJ64DPN Table 3-TM2FJ64DPN Table 2-TM2EJ64EPN Table 4-TM2FJ64EPN
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PRODUCT PREVIEW
TM2EJ64DPN, TM2FJ64DPN 2097152 BY 64-BIT TM2EJ64EPN, TM2FJ64EPN 2097152 BY 64-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES -- SODIMM
SMMS685 - AUGUST 1997
serial presence detect (continued)
Table 1. Serial Presence-Detect Data for the TM2EJ64DPN
BYTE NO. 0 FUNCTION DESCRIBED Defines number of bytes written into serial memory during module manufacturing Total number of bytes of SPD memory device Fundamental memory type (FPM, EDO, SDRAM) Number of row addresses on this assembly Number of column addresses on this assembly Number of module banks on this assembly Data width of this assembly Data width continuation Voltage interface standard of this assembly RAS0 access time of module CASx access time of module SODIMM configuration type (non-parity, parity, ECC) Refresh rate / type DRAM width, primary DRAM Error-checking SDRAM data width SPD revision Checksum for bytes 0 - 62 Manufacturer's JEDEC ID code per JEP-106E Manufacturing location Manufacturer's part number Die revision code PCB revision code Manufacturing date Assembly serial number Manufacturer specific data Vendor specific data System integrator's specific data Open LVTTL tRAC = 50 ns tCAC = 13 ns Non-parity 15.6 s x8 N/A Rev. 1 41 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD '2EJ64DPN-50 ITEM 128 bytes DATA 80h '2EJ64DPN-60 ITEM 128 bytes DATA 80h '2EJ64DPN-70 ITEM 128 bytes DATA 80h
1 2 3 4 5
256 bytes EDO 11 10 1 bank 64 bits
08h 02h 0Bh 0Ah 01h 40h 00h 01h 32h 0Dh 00h 00h 08h 00h 01h 29h 9700...00h
256 bytes EDO 11 10 1 bank 64 bits
08h 02h 0Bh 0Ah 01h 40h 00h
256 bytes EDO 11 10 1 bank 64 bits
08h 02h 0Bh 0Ah 01h 40h 00h
PRODUCT PREVIEW
6 7 8 9 10 11 12 13 14 62 63 64-71 72 73-90 91 92 93-94 95-98 99-125 126-127 128-166 167-255
LVTTL tRAC = 60 ns tCAC = 15 ns Non-parity 15.6 s x8 N/A Rev. 1 53 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD
01h 3Ch 0Fh 00h 00h 08h 00h 01h 35h 9700...00h
LVTTL tRAC = 70 ns tCAC = 18 ns Non-parity 15.6 s x8 N/A Rev. 1 66 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD
01h 46h 12h 00h 00h 08h 00h 01h 42h 9700...00h
TBD indicates values are determined at manufacturing time and are module dependent. These TBD values are determined and programmed by the customer (optional).
14
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TM2EJ64DPN, TM2FJ64DPN 2097152 BY 64-BIT TM2EJ64EPN, TM2FJ64EPN 2097152 BY 64-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES -- SODIMM
SMMS685 - AUGUST 1997
serial presence detect (continued)
Table 2. Serial Presence-Detect Data for the TM2EJ64EPN
BYTE NO. 0 FUNCTION DESCRIBED Defines number of bytes written into serial memory during module manufacturing Total number of bytes of SPD memory device Fundamental memory type (FPM, EDO, SDRAM) Number of row addresses on this assembly Number of column addresses on this assembly Number of module banks on this assembly Data width of this assembly Data width continuation Voltage interface standard of this assembly RAS0 access time of module CASx access time of module SODIMM configuration type (non-parity, parity, ECC) Refresh rate / type DRAM width, primary DRAM Error-checking SDRAM data width SPD revision Checksum for bytes 0 - 62 Manufacturer's JEDEC ID code per JEP-106E Manufacturing location Manufacturer's part number Die revision code PCB revision code Manufacturing date Assembly serial number Manufacturer specific data Vendor specific data System integrator's specific data LVTTL tRAC = 50 ns tCAC = 13 ns Non-parity 15.6 s x8 N/A Rev. 1 41 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD '2EJ64EPN-50 ITEM 128 bytes DATA 80h '2EJ64EPN-60 ITEM 128 bytes DATA 80h '2EJ64EPN-70 ITEM 128 bytes DATA 80h
1 2 3 4 5 6 7 8 9 10 11 12 13 14 62 63 64-71 72 73-90 91 92 93-94 95-98 99-125 126-127 128-166
256 bytes EDO 12 9 1 bank 64 bits
08h 02h 0Ch 09h 01h 40h 00h 01h 32h 0Dh 00h 00h 08h 00h 01h 29h 9700...00h
256 bytes EDO 12 9 1 bank 64 bits
08h 02h 0Ch 09h 01h 40h 00h
256 bytes EDO 12 9 1 bank 64 bits
08h 02h 0Ch 09h 01h 40h 00h
LVTTL tRAC = 60 ns tCAC = 15 ns Non-parity 15.6 s x8 N/A Rev. 1 53 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD
01h 3Ch 0Fh 00h 00h 08h 00h 01h 35h 9700...00h
LVTTL tRAC = 70 ns tCAC = 18 ns Non-parity 15.6 s 08h N/A Rev. 1 66 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD
01h 46h 12h 00h 00h 08h 00h 01h 42h 9700...00h
167-255 Open TBD indicates values are determined at manufacturing time and are module dependent. These TBD values are determined and programmed by the customer (optional).
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PRODUCT PREVIEW
TM2EJ64DPN, TM2FJ64DPN 2097152 BY 64-BIT TM2EJ64EPN, TM2FJ64EPN 2097152 BY 64-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES -- SODIMM
SMMS685 - AUGUST 1997
serial presence detect (continued)
Table 3. Serial Presence-Detect Data for the TM2FJ64DPN
BYTE NO. 0 FUNCTION DESCRIBED Defines number of bytes written into serial memory during module manufacturing Total number of bytes of SPD memory device Fundamental memory type (FPM, EDO, SDRAM) Number of row addresses on this assembly Number of column addresses on this assembly Number of module banks on this assembly Data width of this assembly Data width continuation Voltage interface standard of this assembly RAS0 access time of module CASx access time of module SODIMM configuration type (non-parity, parity, ECC) Refresh rate / type DRAM width, primary DRAM Error-checking SDRAM data width SPD revision Checksum for bytes 0 - 62 Manufacturer's JEDEC ID code per JEP-106E Manufacturing location Manufacturer's part number Die revision code PCB revision code Manufacturing date Assembly serial number Manufacturer specific data Vendor specific data System integrator's specific data LVTTL tRAC = 50 ns tCAC = 13 ns Non-parity 15.6 s / self-refresh x8 N/A Rev. 1 169 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD '2FJ64DPN-50 ITEM 128 bytes DATA 80h '2FJ64DPN-60 ITEM 128 bytes DATA 80h '2FJ64DPN-70 ITEM 128 bytes DATA 80h
1 2 3 4 5
256 bytes EDO 11 10 1 bank 64 bits
08h 02h 0Bh 0Ah 01h 40h 00h 01h 32h 0Dh 00h 80h 08h 00h 01h A9h 9700...00h
256 bytes EDO 11 10 1 bank 64 bits
08h 02h 0Bh 0Ah 01h 40h 00h
256 bytes EDO 11 10 1 bank 64 bits
08h 02h 0Bh 0Ah 01h 40h 00h
PRODUCT PREVIEW
6 7 8 9 10 11 12 13 14 62 63 64-71 72 73-90 91 92 93-94 95-98 99-125 126-127 128-166
LVTTL tRAC = 60 ns tCAC = 15 ns Non-parity 15.6 s / self-refresh x8 N/A Rev. 1 181 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD
01h 3Ch 0Fh 00h 80h 08h 00h 01h B5h 9700...00h
LVTTL tRAC = 70 ns tCAC = 18 ns Non-parity 15.6 s / self-refresh x8 N/A Rev. 1 194 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD
01h 46h 12h 00h 80h 08h 00h 01h C2h 9700...00h
167-255 Open TBD indicates values are determined at manufacturing time and are module dependent. These TBD values are determined and programmed by the customer (optional).
16
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TM2EJ64DPN, TM2FJ64DPN 2097152 BY 64-BIT TM2EJ64EPN, TM2FJ64EPN 2097152 BY 64-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES -- SODIMM
SMMS685 - AUGUST 1997
serial presence detect (continued)
Table 4. Serial Presence-Detect Data for the TM2FJ64EPN
BYTE NO. 0 FUNCTION DESCRIBED Defines number of bytes written into serial memory during module manufacturing Total number of bytes of SPD memory device Fundamental memory type (FPM, EDO, SDRAM) Number of row addresses on this assembly Number of column addresses on this assembly Number of module banks on this assembly Data width of this assembly Data width continuation Voltage interface standard of this assembly RAS0 access time of module CASx access time of module SODIMM configuration type (non-parity, parity, ECC) Refresh rate / type DRAM width, primary DRAM Error-checking SDRAM data width SPD revision Checksum for bytes 0 - 62 Manufacturer's JEDEC ID code per JEP-106E Manufacturing location Manufacturer's part number Die revision code PCB revision code Manufacturing date Assembly serial number Manufacturer specific data Vendor specific data System integrator's specific data LVTTL tRAC = 50 ns tCAC = 13 ns Non-parity 15.6 s / self-refresh x8 N/A Rev. 1 169 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD '2FJ64EPN-50 ITEM 128 bytes DATA 80h '2FJ64EPN-60 ITEM 128 bytes DATA 80h '2FJ64EPN-70 ITEM 128 bytes DATA 80h
1 2 3 4 5 6 7 8 9 10 11 12 13 14 62 63 64-71 72 73-90 91 92 93-94 95-98 99-125 126-127 128-166
256 bytes EDO 12 9 1 bank 64 bits
08h 02h 0Ch 09h 02h 40h 00h 01h 32h 0Dh 00h 80h 08h 00h 01h A9h 9700...00h
256 bytes EDO 12 9 1 bank 64 bits
08h 02h 0Ch 09h 02h 40h 00h
256 bytes EDO 12 9 1 bank 64 bits
08h 02h 0Ch 09h 02h 40h 00h
LVTTL tRAC = 60 ns tCAC = 15 ns Non-parity 15.6 s / self-refresh x8 N/A Rev. 1 181 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD
01h 3Ch 0Fh 00h 80h 08h 00h 01h B5h 9700...00h
LVTTL tRAC = 70 ns tCAC = 18 ns Non-parity 15.6 s / self-refresh x8 N/A Rev. 1 194 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD
01h 46h 12h 00h 80h 08h 00h 01h C2h 9700...00h
167-255 Open TBD indicates values are determined at manufacturing time and are module dependent. These TBD values are determined and programmed by the customer (optional).
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PRODUCT PREVIEW
TM2EJ64DPN, TM2FJ64DPN 2097152 BY 64-BIT TM2EJ64EPN, TM2FJ64EPN 2097152 BY 64-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES -- SODIMM
SMMS685 - AUGUST 1997
device symbolization (TM2EJ64DPN illustrated)
TM2EJ64DPN
-SS
YYMMT
YY MM T -SS
= = = =
Year Code Month Code Assembly Site Code Speed Code
NOTE A: Location of symbolization may vary.
PRODUCT PREVIEW
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TM2EJ64DPN, TM2FJ64DPN 2097152 BY 64-BIT TM2EJ64EPN, TM2FJ64EPN 2097152 BY 64-BIT EXTENDED-DATA-OUT DYNAMIC RAM MODULES -- SODIMM
SMMS685 - AUGUST 1997
MECHANICAL DATA
BDM (R-SODIMM-N144) SMALL OUTLINE DUAL IN-LINE MEMORY MODULE
2.665 (67,69) 2.655 (67,44) Notch 0.157 (4,00) x 0.079 (2,00) Deep (2 Places) Notch 0.060 (1,52) x 0.158 (4,01) Deep 0.044 (1,12) 0.036 (0,91)
0.024 (0,61) TYP 0.098 (2,49) 0.196 (4,98)
0.031 (0,79)
0.010 (0,25) MAX 0.788 (20,00) TYP 1.005 (25,53) 0.995 (25,27) 0.157 (4,00) 0.126 (3,20) 0.095 (2,41) MAX 0.150 (3,81) MAX (For Double Sided Module Only) 4088187/A 07/97
NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MO-190
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PRODUCT PREVIEW
IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 1998, Texas Instruments Incorporated

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