View SMMS132D_1003881.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

TM124BBK32, TM124BBK32S 1048576 BY 32-BIT TM248CBK32, TM248CBK32S 2097152 BY 32-BIT DYNAMIC RAM MODULE
SMMS132D - JANUARY 1991 - REVISED JUNE 1995
D D D D D D D D D D
Organization TM124BBK32 . . . 1 048 576 x 32 TM248CBK32 . . . 2 097 152 x 32 Single 5-V Power Supply (10 % Tolerance) 72-pin Single In-Line Memory Module (SIMM) for Use With Sockets TM124BBK32-Utilizes Eight 4-Megabit DRAMs in Plastic Small-Outline J-Lead (SOJ) Packages TM248CBK32-Utilizes Sixteen 4-Megabit DRAMs in Plastic Small-Outline J-Lead (SOJ) Packages Distributed Refresh Period 16 ms (1024 Cycles) All Inputs, Outputs, Clocks Fully TTL Compatible 3-State Output Common CAS Control for Eight Common Data-In and Data-Out Lines, In Four Blocks Presence Detect
D
Performance Ranges:
ACCESS TIME tRAC (MAX) 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns ACCESS TIME tCAC (MAX) 15 ns 18 ns 20 ns 15 ns 18 ns 20 ns READ OR WRITE CYCLE (MIN) 110 ns 130 ns 150 ns 110 ns 130 ns 150 ns
D D D D
TM124BBK32-60 TM124BBK32-70 TM124BBK32-80 TM248CBK32-60 TM248CBK32-70 TM248CBK32-80
Low Power Dissipation Operating Free-Air-Temperature Range 0C to 70C Gold-Tabbed Versions Available: - TM124BBK32 - TM248CBK32 Tin-Lead (Solder) Tabbed Versions Available: - TM124BBK32S - TM248CBK32S
description
TM124BBK32 The TM124BBK32 is a dynamic random-access memory (DRAM) organized as four times 1 048 576 x 8 in a 72-pin leadless single in-line memory module (SIMM). The SIMM is composed of eight TMS44400, 1 048 576 x 4-bit DRAMs, each in 20/26-lead plastic SOJ packages, mounted on a substrate together with decoupling capacitors. Each TMS44400 is described in the TMS44400 data sheet. The TM124BBK32 is available in the single-sided BK leadless module for use with sockets. The TM124BBK32 features RAS access times of 60 ns, 70 ns and 80 ns. This device is rated for operation from 0C to 70C TM248CBK32 The TM248CBK32 is a dynamic random-access memory organized as four times 2 097 152 x 8 in a 72-pin leadless SIMM. The SIMM is composed of sixteen TMS44400, 1 048 576 x 4-bit dynamic RAMs, each in 20/26-lead plastic SOJ packages SOJs, mounted on a substrate together with decoupling capacitors. Each TMS44400 is described in the TMS44400 data sheet. The TM248CBK32 is available in the double-sided BK leadless module for use with sockets. The TM248CBK32 features RAS access times of 60 ns, 70 ns and 80 ns. This device is rated for operation from 0C to 70C
operation
TM124BBK32 The TM124BBK32 operates as eight TMS44400DJs connected as shown in the functional block diagram. Refer to the TMS44400 data sheet for details of operation. The common I/O feature of the TM124BBK32 dictates the use of early write cycles to prevent contention on D and Q.
Part numbers in this data sheet are for the gold-tabbed version; the information applies to both gold-tabbed and solder-tabbed versions.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 1995, Texas Instruments Incorporated
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
1
TM124BBK32, TM124BBK32S 1048576 BY 32-BIT TM248CBK32, TM248CBK32S 2097152 BY 32-BIT DYNAMIC RAM MODULE
SMMS132D - JANUARY 1991 - REVISED JUNE 1995
TM248CBK32 The TM248CBK32 operates as sixteen TMS44400DJs connected as shown in the functional block diagram. Refer to the TMS44400 data sheet for details of operation. The common I/O feature of the TM248CBK32 dictates the use of early write cycles to prevent contention on D and Q.
refresh
Refresh period is extended to 16 ms and, during this period, each of the 1024 rows must be strobed with RAS in order to retain data. A0-A9 address lines must be refreshed every 16 ms as required by the TMS44400 DRAM. CAS can remain high during the refresh sequence to conserve power.
single in-line memory module and components
PC substrate: 1,27 0,1 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage Bypass capacitors: Multilayer ceramic Contact area for TM124BBK32 AND TM248CBK32: Nickel plate and gold plate over copper. Contact area for TM124BBK32S AND TM248CBK32S: Nickel plate and tin-lead over copper.
2
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
TM124BBK32, TM124BBK32S 1048576 BY 32-BIT TM248CBK32, TM248CBK32S 2097152 BY 32-BIT DYNAMIC RAM MODULE
SMMS132D - JANUARY 1991 - REVISED JUNE 1995
BK SINGLE IN-LINE MEMORY MODULE (TOP VIEW)
TM124BBK32 (SIDE VIEW)
TM248CBK32 (SIDE VIEW)
VSS DQ0 DQ16 DQ1 DQ17 DQ2 DQ18 DQ3 DQ19 VCC NC A0 A1 A2 A3 A4 A5 A6 NC DQ4 DQ20 DQ5 DQ21 DQ6 DQ22 DQ7 DQ23 A7 NC VCC A8 A9 RAS3 RAS2 NC NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
NC NC VSS CAS0 CAS2 CAS3 CAS1 RAS0 RAS1 NC W NC DQ8 DQ24 DQ9 DQ25 DQ10 DQ26 DQ11 DQ27 DQ12 DQ28 VCC DQ29 DQ13 DQ30 DQ14 DQ31 DQ15 NC PD1 PD2 PD3 PD4 NC VSS
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
PIN NOMENCLATURE A0-A9 CAS0-CAS3 DQ0-DQ31 NC PD1- PD4 RAS0-RAS3 VCC VSS W Address Inputs Column-Address Strobe Data In/Data Out No Connection Presence Detects Row-Address Strobe 5-V Supply Ground Write Enable
PRESENCE DETECT SIGNAL (PIN) 80 ns TM124BBK32 70 ns 60 ns 80 ns TM248CBK32 70 ns 60 ns PD1 (67) VSS VSS VSS NC NC NC PD2 (68) VSS VSS VSS NC NC NC PD3 (69) NC VSS NC NC VSS NC PD4 (70) VSS NC NC VSS NC NC
The packages shown here are not drawn to scale.
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
3
SMMS132D - JANUARY 1991 - REVISED JUNE 1995
TM124BBK32, TM124BBK32S 1048576 BY 32-BIT TM248CBK32, TM248CBK32S 2097152 BY 32-BIT DYNAMIC RAM MODULE
functional block diagram (for TM124BBK32 and TM248CBK32, Side 1)
4
POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443
Template Release Date: 7-11-94
A0 - A9 RAS0 W CAS0
10 RAS2
CAS1 10 1M x 4 A0 - A9 RAS W CAS OE DQ1- DQ4 10 1M x 4 A0 - A9 RAS W CAS OE DQ1 - DQ4
CAS2 10 1M x 4 A0 - A9 RAS W CAS OE DQ1 - DQ4
CAS3 10 1M x 4 A0 - A9 RAS W CAS OE DQ1 - DQ4
DQ0 - DQ3 10
DQ8 - DQ11 10
DQ16 - DQ19 10
DQ24 - DQ27
10
1M x 4 A0 - A9 RAS W CAS OE DQ1 - DQ4
DQ4- DQ7
1M x 4 A0 - A9 RAS W CAS OE DQ1 - DQ4
DQ12 - DQ15
1M x 4 A0 - A9 RAS W CAS OE DQ1 - DQ4
DQ20 - DQ23
1M x 4 A0 - A9 RAS W CAS OE DQ1 - DQ4
DQ28 - DQ31
functional block diagram (for TM248CBK32, Side 2)
10 A0 - A9 RAS1 W CAS0 10 1M x 4 A0 - A9 RAS W CAS OE DQ1 - DQ4 CAS1 10 1M x 4 A0 - A9 RAS W CAS OE DQ1 - DQ4 CAS2 10 1M x 4 A0 - A9 RAS W CAS OE DQ1 - DQ4 CAS3 10 1M x 4 A0 - A9 RAS W CAS OE DQ1 - DQ4 RAS3
POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443
DQ0 - DQ3 10
DQ8 - DQ11 10
DQ16 - DQ19 10
DQ24 - DQ27
10
1M x 4 A0 - A9 RAS W CAS OE DQ1 - DQ4
DQ4 - DQ7
1M x 4 A0 - A9 RAS W CAS OE DQ1 - DQ4
DQ12 - DQ15
1M x 4 A0 - A9 RAS W CAS OE DQ1 - DQ4
DQ20 - DQ23
1M x 4 A0 - A9 RAS W CAS OE DQ1 - DQ4
TM124BBK32, TM124BBK32S 1048576 BY 32-BIT TM248CBK32, TM248CBK32S 2097152 BY 32-BIT DYNAMIC RAM MODULE
DQ28 - DQ31
SMMS132D - JANUARY 1991 - REVISED JUNE 1995
5
TM124BBK32, TM124BBK32S 1048576 BY 32-BIT TM248CBK32, TM248CBK32S 2097152 BY 32-BIT DYNAMIC RAM MODULE
SMMS132D - JANUARY 1991 - REVISED JUNE 1995
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 1 V to 7 V Voltage range on VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 1 V to 7 V Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 W Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 55C to 125C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
MIN VCC VIH VIL TA Supply voltage High-level input voltage Low-level input voltage (see Note 2) Operating free-air temperature 4.5 2.4 -1 0 NOM 5 MAX 5.5 6.5 0.8 70 UNIT V V V C
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only.
electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER VOH VOL II IO ICC1 High-level output voltage Low-level output voltage Input current (leakage) Output current (leakage) Read- or write-cycle current (see Note 3) TEST CONDITIONS IOH = - 5 mA IOL = 4.2 mA VCC = 5 V, VI = 0 V to 6.5 V, All other pins = 0 V to VCC VCC = 5.5 V, CAS high VCC = 5.5 V, VO = 0 V to VCC, Minimum cycle '124BBK32-60 MIN 2.4 0.4 10 10 840 MAX '124BBK32-70 MIN 2.4 0.4 10 10 720 MAX '124BBK32-80 MIN 2.4 0.4 10 10 640 MAX UNIT V V A A mA
ICC2
Standby current
After 1 memory cycle, RAS and CAS high, VIH = 2.4 V (TTL) After 1 memory cycle, RAS and CAS high, VIH = VCC - 0.2 V (CMOS) VCC = 5.5 V, Minimum cycle, RAS cycling, CAS high (RAS only), RAS low after CAS low (CBR) VCC = 5.5 V, RAS low, tPC = minimum, CAS cycling
16
16
16 mA
8
8
8
ICC3
Average refresh current (RAS only or CBR) (see Note 3) Average page current (see Note 4)
840
720
640
mA
ICC4
720
640
560
mA
NOTES: 3. Measured with a maximum of one address change while RAS = VIL 4. Measured with a maximum of one address change while CAS = VIH
6
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
TM124BBK32, TM124BBK32S 1048576 BY 32-BIT TM248CBK32, TM248CBK32S 2097152 BY 32-BIT DYNAMIC RAM MODULE
SMMS132D - JANUARY 1991 - REVISED JUNE 1995
electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER VOH VOL II IO ICC1 High-level output voltage Low-level output voltage Input current (leakage) Output current (leakage) Read- or write-cycle current (see Note 3) TEST CONDITIONS IOH = - 5 mA IOL = 4.2 mA VCC = 5 V, VI = 0 V to 6.5 V, All other pins = 0 V to VCC VCC = 5.5 V, CAS high VCC = 5.5 V, VO = 0 V to VCC, '248CBK32-60 MIN 2.4 0.4 20 20 856 MAX '248CBK32-70 MIN 2.4 0.4 20 20 736 MAX '248CBK32-80 MIN 2.4 0.4 20 20 656 MAX UNIT V V A A mA
Minimum cycle
ICC2
Standby current
After 1 memory cycle, RAS and CAS high, VIH = 2.4 V (TTL) After 1 memory cycle, RAS and CAS high, VIH = VCC - 0.2 V (CMOS) VCC = 5.5 V, Minimum cycle, RAS cycling, CAS high (RAS only), RAS low after CAS low (CBR) VCC = 5.5 V, RAS low, tPC = minimum, CAS cycling
32
32
32 mA
16
16
16
ICC3
Average refresh current (RAS only or CBR) (see Note 3) Average page current (see Note 4)
1680
1440
1280
mA
ICC4
736
656
576
mA
NOTES: 3. Measured with a maximum of one address change while RAS = VIL 4. Measured with a maximum of one address change while CAS = VIH
capacitance over recommended ranges of supply voltage and operating free-air temperature f = 1 MHz (see Note 5)
'124BBK32 MIN Ci(A) Ci(R) Ci(C) Ci(W) Co(DQ) Input capacitance, address inputs Input capacitance, RAS Input capacitance, CAS Input capacitance, W Output capacitance on DQ pins MAX 40 28 14 56 7 '248CBK32 MIN MAX 80 28 28 112 14 UNIT pF pF pF pF pF
NOTE 5: VCC = 5 V 0.5 V and the bias on pins under test is 0 V.
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
PARAMETER tAA tCAC tCPA tRAC tCLZ tOFF Access time from column-address Access time from CAS low Access time from column precharge Access time from RAS low CAS to output in low Z Output disable time after CAS high (see Note 6) 0 0 15 '124BBK32-60 '248CBK32-60 MIN MAX 30 15 35 60 0 0 18 '124BBK32-70 '248CBK32-70 MIN MAX 35 18 40 70 0 0 20 '124BBK32-80 '248CBK32-80 MIN MAX 40 20 45 80 ns ns ns ns ns ns UNIT
NOTE 6: tOFF is specified when the output is no longer driven.
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
7
TM124BBK32, TM124BBK32S 1048576 BY 32-BIT TM248CBK32, TM248CBK32S 2097152 BY 32-BIT DYNAMIC RAM MODULE
SMMS132D - JANUARY 1991 - REVISED JUNE 1995
timing requirements over recommended range of supply voltage and operating free-air temperature
'124BBK32-60 '248CBK32-60 MIN tRC tPC tCP tCAS tRP tRASP tRAS tWP tASC tASR tDS tRCS tWCS tWSR tCWL tRWL tWTS tCAH tRAH tAR tDHR tDH tRCH tRRH tWCH tWHR tWCR tWTH tCSH tCRP tRCD tCHR tCSR tRAD Cycle time, random read or write (see Note 7) Cycle time, page-mode read or write (see Note 8) Pulse duration, CAS high Pulse duration, CAS low Pulse duration, RAS high (precharge) Pulse duration, page mode, RAS low Pulse duration, nonpage mode, RAS low Pulse duration, write Setup time, column address before CAS low Setup time, row address before RAS low Setup time, data Setup time, read before CAS low Setup time, W low before CAS low Setup time, W high (CBR refresh only) Setup time, W low before CAS high Setup time, W low before RAS high Setup time, W low (test mode only) Hold time, column address after CAS low Hold time, row address after RAS low Hold time, column address after RAS low (see Note 9) Hold time, data after RAS low (see Note 9) Hold time, data Hold time, read after CAS high (see Note 10) Hold time, read after RAS high (see Note 10) Hold time, write after CAS low Hold time, W high (CBR refresh only) Hold time, write after RAS low Hold time, W low (test mode only) Delay time, RAS low to CAS high Delay time, CAS high to RAS low Delay time, RAS low to CAS low (see Note 11) Delay time, RAS low to CAS high (CBR refresh only) Delay time, CAS low to RAS low (CBR refresh only) Delay time, RAS low to column address (see Note 11) 110 40 10 15 40 60 100 000 60 15 0 0 0 0 0 10 15 15 10 10 10 50 50 10 0 0 15 10 50 10 60 0 20 15 10 15 30 45 10 000 10 000 MAX '124BBK32-70 '248CBK32-70 MIN 130 45 10 18 50 70 100 000 70 15 0 0 0 0 0 10 18 18 10 15 10 55 55 15 0 0 15 10 55 10 70 0 20 15 10 15 35 35 52 10 000 10 000 MAX '124BBK32-80 '248CBK32-80 MIN 150 50 10 20 60 80 100 000 80 15 0 0 0 0 0 10 20 20 10 15 10 60 60 15 0 0 15 10 60 10 80 0 20 20 10 15 40 40 60 10 000 10 000 MAX ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns UNIT
tRAL Delay time, column address to RAS high 30 NOTES: 7. All cycle times assume tT = 5 ns. 8. To assure tPLmin, tASC should be 5 ns. 9. The minimum value is measured when tRCD is set to tRCD min as a reference. 10. Either tRRH or tRCH must be satisfied for a read cycle. 11. Maximum value specified only to assure access time.
8
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
TM124BBK32, TM124BBK32S 1048576 BY 32-BIT TM248CBK32, TM248CBK32S 2097152 BY 32-BIT DYNAMIC RAM MODULE
SMMS132D - JANUARY 1991 - REVISED JUNE 1995
timing requirements over recommended range of supply voltage and operating free-air temperature (concluded)
'124BBK32-60 '248CBK32-60 MIN tCAL tRPC tRSH tTAA tTRAC tTCPA tREF tT Delay time, column address to CAS high Delay time, RAS high to CAS low (CBR refresh only) Delay time, CAS low to RAS high Access time from address (test mode) Access time from RAS (test mode) Access time from column precharge (test mode) Refresh time interval Transition time 2 30 0 15 35 65 40 16 50 2 MAX '124BBK32-70 '248CBK32-70 MIN 35 0 18 40 75 45 16 50 2 MAX '124BBK32-80 '248CBK32-80 MIN 40 0 20 45 85 50 16 50 MAX ns ns ns ns ns ns ms ns UNIT
device symbolization (TM124BBK32 illustrated)
TM124BBK36B
-SS
YYMMT
YY MM T -SS
= = = =
Year Code Month Code Assembly Site Code Speed Code
NOTE: Location of symbolization may vary.
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
9
TM124BBK32, TM124BBK32S 1048576 BY 32-BIT TM248CBK32, TM248CBK32S 2097152 BY 32-BIT DYNAMIC RAM MODULE
SMMS132D - JANUARY 1991 - REVISED JUNE 1995
10
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 1999, Texas Instruments Incorporated

▲Up To Search▲

Price & Availability of SMMS132D

	To Download SMMS132D Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .