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UCC5680 9 LINE LVD ONLY SCSI TERMINATOR WITH INTEGRATED SPI 3 DELAYS
SLUS313C - MARCH 1999 - REVISED JUNE 2000
D LVD-Only Active Termination D 2.7 V to 5.25 V Operation D Differential Failsafe Bias
description
D Built-In SPI-3 Mode Change Filter/Delay D Standards Supported: SPI-3, Ultra2
(Fast 40), Ultra3/Ultra160 (Fast 80)
The UCC5680 is an LVD-only Small Computer System Interface (SCSI) terminator that integrates the mode change delay function required by the SPI-3 specification. The device senses what types of SCSI drivers are present on the bus via the voltage on the DIFFSENS SCSI control line. Single-ended (SE) and high-voltage differential (HVD) SCSI drivers (EIA485) are not supported. If the chip detects the presence of an SE or HVD SCSI driver, it disconnects itself by switching all terminating resistors off the bus and enters a high-impedance state. The terminator can also be commanded to disconnect the terminating resistors with the DISCNCT input. Impedance is trimmed for accuracy and maximum effectiveness. Bus lines are biased to a failsafe state to ensure signal integrity. The UCC5680 is offered in both 24-pin and 28-pin TSSOP (PW) packages for a temperature range of 0C to 70C.
functional block diagram
2.15 V DIFFB 11
+
100 ms TO 300 ms DELAY/ FILTER
HIGH-VOLTAGE DIFFERENTIAL LOW-VOLTAGE DIFFERENTIAL SINGLE-ENDED -15 mA ISOURCE -5 mA 50 A ISINK 200 A REF 1.3V 12 DIFSENS 27 LVD{
+
0.6 V
10 A DISCNCT 15 TRMPWR 28 MODE SE LVD HVD DISCNCT ENABLE
REF 1.25V
124
56 mV -+ 56 mV +-
52 4 52 3 L1+ L1 -
ALL SWITCHES OPEN DOWN OPEN OPEN 124 56 mV -+ 56 mV +- 1 REG 52 26 L9+ 52 25 L9 -
14 GND
{28-PIN PACKAGE ONLY
UDG-00067
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 2000, Texas Instruments Incorporated
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SLUS313C - MARCH 1999 - REVISED JUNE 2000
UCC5680 9 LINE LVD ONLY SCSI TERMINATOR WITH INTEGRATED SPI 3 DELAYS
TSSOP PACKAGE (TOP VIEW)
PW PACKAGE (TOP VIEW)
REG L1+ L1 - L2+ L2 - L3+ L3 - L4+ L4 - DIFFB DIFSENS GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 REG TRMPWR N/C L9+ L1+ L9 - L1 - L8+ L8 - L7+ L7 - L6+ L6 - DIFFB 11 L5+ DIFSENS 12 L5 - DISCNCT N/C GND 13 14 17 L5 - 16 N/C 15 DISCNCT 18 L5+ L2+ L2 - L3+ L3 - L4+ 4 5 6 7 8 9 25 L9 - 24 L8+ 23 L8 - 22 L7+ 3 26 L9+ 2 27 LVD 1
PW PACKAGE (TOP VIEW)
28 TRMPWR
21 L7 - 20 L6+ 19 L6 -
L4 - 10
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
TERMPWR Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V Signal Line Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to 5 V Package Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 W Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to 150C Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
TERMPWR Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7 V to 5.25 V Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C
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UCC5680 9 LINE LVD ONLY SCSI TERMINATOR WITH INTEGRATED SPI 3 DELAYS
SLUS313C - MARCH 1999 - REVISED JUNE 2000
electrical characteristics over recommended operating free-air temperature range, TA = TJ = 0C to 70C, TRMPWR = 2.7 V to 5.25 V
PARAMETER TRMPWR Supply Current Section LVD Mode (No Load) TRMPWR supply current Regulator Section Regulator output voltage Regulator short-circuit source current Regulator short-circuit sink current DIFSENS Output Section Output voltage Short-circuit source current Short-circuit sink current Differential impedance Common-mode impedance Differential bias voltage Common-mode bias voltage Output leakage Output capacitance DISCNCT and DIFFB Input Section DISCNCT threshold DISCNCT input current DIFFB SE to LVD threshold DIFFB LVD to HVD threshold 0 V VDIFFB 2.75 V Low Voltage Differential (LVD) Status Bit Section (See Note 4) DIFFB input current ISOURCE ISINK Time Delay/Filter Section Mode change delay Thermal Shutdown Section Themal shutdown threshold Themal shutdown hysteresis NOTES: 1. VCM is applied to all L+ and L- lines simultaneously. (2.0V * 0.5V) 2. Z + @ VCM(max) = 2.0, VCM(min) = 0.5 V CM I *I VCM(max) VCM(min) 3. Ensured by design, not production tested. 4. This applies to the 28-pin package only. For increasing temperature 140 155 10 170 C C A new mode change can start any time after a previous mode change has been detected 100 190 300 ms VLOAD = 2.4 V VLOAD = 0.4 V VDISCNCT = 0 V and 2.0 V 0.8 -30 0.5 1.9 -10 -6 2 5 -10 0.7 2.4 10 -4 2.0 V A V V A mA mA Single-ended measurement to ground, See Note 3 L+ and L- shorted together Disconnected Termination Section (Applies to each line pair , 1-9, in DISCNCT, SE or HVD mode) 400 3 nA pF L+ and L- shorted together, See Note 2 -5 mA IDIFSENS 50 A VDIFSENS = 0 V VDIFSENS = 2.75 V 1.2 -15 50 100 110 100 1.15 1.25 105 150 1.3 1.4 -5 200 110 165 125 1.35 V mA A mV V 0.5 V VCM 2.0, See Note 1 VREG = 0 V VREG = 3.0 V 1.15 80 1.25 -100 100 1.35 -80 V mA mA Disabled Mode 35 500 mA A TEST CONDITIONS MIN TYP MAX UNIT
Differential Termination Section (Applies to each line pair , 1-9, in LVD mode)
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SLUS313C - MARCH 1999 - REVISED JUNE 2000
UCC5680 9 LINE LVD ONLY SCSI TERMINATOR WITH INTEGRATED SPI 3 DELAYS
pin descriptions
DIFFB: DIFFSENS input pin. Connect through a 20-k resistor to DIFSENS and through a 0.1-F capacitor to ground. Input to comparators that detect what types of drivers are connected to the SCSI bus. DIFSENS: SCSI bus DIFSENS line driver. DISCNCT: Disconnect pin. Shuts down the terminator (switches terminating resistors off the bus) when open or active (high). The disconnect pin low enables the terminator. GND: Power supply return. LINEn-: Line termination pins. Negative line in differential pair. LINEn+: Line termination pins. Positive line in differential pair. LVD: (28-pin package only) Indicates that the bus is in LVD mode. REG: Regulator bypass pin. Bypass near the terminator with a 4.7-F and a high-frequency, low-ESR 0.01-F capacitor to ground. TRMPWR: VIN 2.75 V to 5.25 V supply. Bypass near the terminator with a 4.7-F and a high-frequency, low-ESR 0.01-F capacitor to ground.
APPLICATION INFORMATION
All SCSI buses require a termination network at each end to function properly. Specific termination requirements differ, depending on which types of SCSI driver devices are present on the bus. The UCC5680 is a low-voltage differential (LVD)-only device. It senses which types of drivers are present on the bus. If it detects the presence of a single-ended (SE) or high-voltage differential (HVD) driver, the UCC5680 will place itself in a high-impedance input state, effectively disconnecting the chip from the bus. The UCC5680 senses what kinds of drivers are present on the bus by the voltage on SCSI bus control line DIFFSENS, which is monitored by the DIFFB input pin. The DIFSENS output pin on the UCC5680 attempts to drive a DIFFSENS control line to 1.3 V. If only LVD devices are present, the DIFFSENS line will be successfully driven to that voltage. If HVD drivers are present, they will pull the DIFFSENS line high. If any single-ended drivers are present, they pull the DIFSENS line to ground (even if HVD drivers are also present on the bus). If the voltage on the DIFFB is below 0.5 V or above 2.4 V, the UCC5680 enters the high-impedance SE/HVD state. If it is between 0.7 V and 1.9 V, the UCC5680 enters the LVD mode. These thresholds accommodate differences in ground potential that can occur between the ends of long bus lines. Three UCC5680 ICs are required at each end of the SCSI bus to terminate 27 lines (18 data, 9 control). Every UCC5680 contains a DIFSENS driver, but only one should be used to drive the line at each end. The DIFSENS pin on the other devices should be left unconnected. On power up (the voltage on the TRMPWR pin rising above 2.7 V), the UCC5680 assumes the SE/HVD mode. If the voltage on the DIFFB input indicates LVD mode, the chip waits 100 ms to 300 ms before changing the mode of the bus. If the voltage at the DIFFB input later crosses one of the thresholds, the UCC5680 again waits 100 ms to 300 ms before changing the mode of the bus. The magnitude of the delay is the same when changing in or out of either bus mode. A new mode change can start anytime after a previous mode change has been detected. The DIFFB inputs on all three chips at each end of the bus should be connected together. Properly filtered, noise on DIFFB will not cause a false mode change. There should be a shared 50-Hz noise filter implemented on DIFFB at each end of the bus as close as possible to the DIFFB pins. This is implemented with a 20-k resistor between the DIFFB and DIFSENS pins, and a 0.1-F capacitor from DIFFB to ground. See the Typical Application diagram at the end of this datasheet.
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UCC5680 9 LINE LVD ONLY SCSI TERMINATOR WITH INTEGRATED SPI 3 DELAYS
SLUS313C - MARCH 1999 - REVISED JUNE 2000
APPLICATION INFORMATION (continued)
In LVD mode, the regulated voltage is switched to 1.25 V and a resistor network is presented to each line pair that provides common-mode impedance of 150 and differential impedance of 105 . The lines in each differential pair are biased so that when not driven, Line(n)+ and Line(n)- are driven 56 mV below and above the common-mode bias voltage (1.25 V) respectively. In SE/HVD mode, all the terminating resistors are switched off the bus. The 1.25-V and 1.3-V (DIFSENS) regulators are left on. When the disconnect input (DISCNCT) is active (high), the terminating resistors are switched off the bus and both voltage regulators are turned off to save power. The mode change filter/delay function is still active and the LVD pin (in the 28-pin package) continues to indicate the correct bus mode. The UCC5680 operates down to a TRMPWR voltage of 2.7 V. This accommodates a 3.3-V system with allowance for supply tolerance (10%), a unidirectional fusing device, and cable drop. The UCC3916 is recommended in place of a fuse and diode implementation, as its lower voltage drop provides additional voltage margin for the system. Layout is important in all SCSI implementations and critical in SPI-3 systems, which have stringent requirements on both the absolute value of capacitance on differential signal lines and the balancing of capacitance between paired lines and from pair to pair. Feedthroughs, through-hole connections, and etch lengths need to be carefully balanced. Standard multilayer power and ground plane spacing adds about 1 pF to each plane. Each feed-through will add 2.5 pF to 3.5 pF. Enlarging the clearance holes on both power and ground planes reduces capacitance. Opening up the power and ground planes under a through-hole connector reduces added capacitance in those applications. Capacitance is also affected by components in close proximity on both sides of the board.
maximum capacitance
SCSI Class Ultra1 Ultra2 Ultra3/Ultra160 Ultra320 Trace to GND: REQ, ACK, DATA, Parity, P_CRCA 25 pF 20 pF 15 pF 13 pF Trace to Trace: REQ, ACK, DATA, Parity, P_CRCA N/A 10 pF 8 pF 6.5 pF Trace to GND: Other signals 25 pF 25 pF 25 pF 21 pF (est.) Trace to Trace: Other Signals N/A 13 pF 13 pF 10 pF (est.)
TI terminators are designed with very tightly controlled capacitance on their signal lines. Between the positive and negative lines in a differential pair the difference is typically no more than 0.1 pF, and only 0.3 pF between pairs. Multi-layer boards need to adhere to the 120- impedance standard, including the connector and feedthroughs. Bus traces are normally run on the outer layers of the board with 4-mil etch and 4-mil spacing between the two lines in each differential pair, and a minimum of 8-mil spacing to adjacent pairs to minimize crosstalk. Microstrip technology is too low in impedance and should not be used--it is designed for 50 rather than 120- differential systems. Decoupling capacitors should be installed as close as possible to the following input pins of the UCC5680: TRMPWR: 4.7-F capacitor to ground, 0.01-F capacitor to ground (high-frequency, low ESR) REG: 4.7-F capacitor to ground, 0.01-F capacitor to ground (high-frequency, low ESR)
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UCC5680 9 LINE LVD ONLY SCSI TERMINATOR WITH INTEGRATED SPI 3 DELAYS
TYPICAL APPLICATION
UCC5680PW28 TERMPWR 28 TRMPWR L1+ L1- 27 LVD L9+ 26 3 4 CONTROL LINES (9) 23 22 (DIFFSENS) 11 L9+ L9- DIFSENS DIFFB 20k 0.1 F 20k 10 0.1 F REG 1 4.7 F 0.01 F DISCNCT 13 2 3 L1+ L1- UCC5680PW24 TRMPWR 24 TERMPWR
15
DISCNCT
L9- 25 DIFSENS REG 1 0.01 F 4.7 F DIFFB 11 12
UCC5680PW28 L1+ L1- 28 TRMPWR
3 4 DATA LINES (9)
2 3
L1+ UCC5680PW24 L1- TRMPWR 24
L9+ 0.01 F 15 4.7 F DISCNCT DIFSENS REG 1 0.01 F DIFFB 11
26
23 22 N/C 11
L9+ L9- DISCNCT 13 DIFSENS DIFFB 10 REG 1 4.7 F 0.01 F
0.01 F
L9- 25 12 N/C
4.7 F
4.7 F
UCC5680PW28 L1+ L1- 28 TRMPWR
3 4 DATA LINES (9)
2 3
L1+ UCC5680PW24 L1- TRMPWR 24
L9+
26
23 22 N/C 11
L9+ L9- DIFSENS DIFFB 10 REG 1 S2* 4.7 F 0.01 F DISCNCT 13
L9- 25 15 DISCNCT DIFSENS REG 1 S1{ 0.01 F 4.7 F DIFFB 11 12 N/C
SCSI CONTROLLER DIFFSENS INPUT { CLOSE S1 and S2 TO CONNECT TERMINATORS
UDG-00005
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IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 2000, Texas Instruments Incorporated

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