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| application INFO available UCC1570 UCC2570 UCC3570 Low Power Pulse Width Modulator FEATURES * Low Power BiCMOS Process * 85A Start-up Current * 1mA Run Current * 1A Peak Gate Drive Output * Voltage Feed Forward * Programmable Duty Cycle Clamp * Optocoupler Interface * 500kHz Operation * Soft Start * Fault Counting Shutdown * Fault Latch Off or Automatic Restart DESCRIPTION The UCC1570 family of pulse width modulators is intended for application in isolated switching supplies using primary side control and a voltage mode feedback loop. Made with a BiCMOS process, these devices feature low startup current for efficient off-line starting with a bootstrapped low voltage supply. Operating current is also very low; yet these devices maintain the ability to drive a power MOSFET gate at frequencies above 500kHz. Voltage feedforward provides fast and accurate response to wide line voltage variation without the noise sensitivity of current mode control. Fast current limiting is included with the ability to latch off after a programmable number of repetitive faults has occurred. This allows the power supply to ride through a temporary overload, while still shutting down in the event of a permanent fault. Additional versatility is provided with a maximum duty cycle clamp programmable within a 20% to 80% range and line voltage sensing with a programmable window of allowable operation. BLOCK DIAGRAM FREQ 11 CLOCK GENERATOR CLK RAMP VALLEY 1V VFWD 6 4.5V 10 I3 I3 S RAMP LATCH R 10 I4 SLOPE 7 RAMP 10 1V 5V GENERATOR 12 13 VREF GND 15V 13/9V ISET 9 I4 4V HIGH LINE LOW LINE 1V FEEDBK 8 I4 SOFTST 14 PWM S RD PWM LATCH 5 4 4V RAMP PEAK 3 VCC OUT PGND CURLIM 2 0.2V CURRENT LIMIT I4 SD CLK COUNT 1 R R SD 4V SHUTDOWN LATCH SHUTDOWN 0.6V APRIL 1999 - REVISED JULY 2000 - SLUS296A UCC1570 UCC2570 UCC3570 ABSOLUTE MAXIMUM RATINGS Supply Voltage (Limit Supply Current to 20mA) . . . . . . . Self Limiting at 15V Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +20mA Analog Inputs (CURLIM, VFWD, FEEBK) . . . . . . . . . . . . . . 6V Programming Current ISLOPE, IISET . . . . . . . . . . . . . . . . . -1mA Output Current IOUT DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180mA Pulse (0.5ms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2A CONNECTION DIAGRAMS DIL-14 (TOP VIEW) N or J Package Note: All voltages are with respect to GND. Currents are positive into the specified terminal. Consult Packaging Section of Databook for thermal limitations and considerations of package. ORDERING INFORMATION UCC1570J UCC2570D UCC2750N UCC3570D UCC3570N Temperature Range -55C to +125C -40C to +85C 0C to +70C Package Ceramic Dip SOIC Plastic Dip SOIC Plastic Dip SOIC-14 (TOP VIEW) D Package ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for TA = 0 to 70C for the UCC3570, TA= -40 to 85C for the UCC2570, TA=-55 to 125C for the UCC1570, RISET=100k, RSLOPE=121k, CFREQ=180pF, CRAMP=150pF, VCC=11V and TA=TJ. PARAMETER Reference VREF Line Regulation Load Regulation Short Circuit Current VCC Vth (On) Vth (Off) Hysteresis VCC IVCC Start IVCC Run TEST CONDITIONS VCC =10 to 13V, IVREF = 0 to 2mA VCC = 10 to 13V IVREF = 0 to 2mA VREF = 0 Min 4.9 Typ 5 2 2 10 13 9 4 15 85 1 Max 5.1 10 10 50 Units V mV mV mA V V V V A mA IVCC = 10mA VCC = 11V, VCC Comparator Off VCC Comparator On 12 8 3 13.5 10 5 16 150 1.5 2 UCC1570 UCC2570 UCC3570 ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for TA = 0 to 70C for the UCC3570, TA= -40 to 85C for the UCC2570, TA=-55 to 125C for the UCC1570, RISET=100k, RSLOPE=121k, CFREQ=180pF, CRAMP=150pF, VCC=11V and TA=TJ. PARAMETER Line Sense Vth High Line Comparator Vth Low Line Comparator lib (VFWD) Oscillator Frequency Ramp Generator IRAMP/ISLOPE -IRAMP/IISET Peak Ramp Voltage Valley Ramp Voltage ISET Voltage Level Soft Start Saturation ISOFTST/IISET Pulse Width Modulator lib(FEEDBK) FEEDBK Current Limit lib(CURLIM) Vth Current Limit Vth Shutdown Fault Counter Vth Vsat ICOUNT/IISET Output Driver Vsat High Vsat Low Rise/Fall Time IOUT = -100mA IOUT = 100mA COUT = 1nF, (Note 1) VCC = 11V, VCC Comparator Off 0.8 TEST CONDITIONS Min 3.9 0.96 Typ 4 1 0 100 10 10 4 1 1 25 1 0 1 4 0 200 600 4 0 1 0.4 0.4 20 Max 4.1 1.04 100 110 11 11 4.2 1.05 1.05 100 1.2 100 1.1 4.2 100 220 700 4.2 100 1.2 1 1 100 Units V V nA kHz A/A A/A V V V mV A/A nA V V nA mV mV V mV A/A V V ns 90 9 9 3.8 0.95 0.95 Zero Duty Cycle Maximum Duty Cycle, (Note 1) 0.9 3.8 180 500 3.8 0.8 Note 1: This parameter guaranteed by design but not 100% tested in production. PIN DESCRIPTIONS VCC: Chip supply voltage pin. Bypass to PGND with a low ESL/ESR 0.1F capacitor plus a capacitor for gate charge storage. Lead lengths must be minimum. PGND: Ground pin for the output driver. Keep connections less than 2cm. Carefully maintain low impedance path for high current return. OUT: Gate drive output pin. Connect to the gate of a power MOSFET with a resistor greater than 2 . Keep connection lengths under 2cm. 3 VFWD: Voltage Feed Forward and Line Sense pin. Connect to input DC line using a resistive divider. SLOPE: Program the charging current for RAMP with a resistor from this pin to GND. This pin will follow VFWD. FEEDBK: Input to the pulse width modulator comparator. Drive this pin with an optocoupler to GND and a resistor to VREF. Modulation input range is from 1V to 4V. ISET: A resistor from this pin to GND programs RAMP discharge current, FREQ current, SOFTST current, and COUNT current. UCC1570 UCC2570 UCC3570 PIN DESCRIPTIONS (cont.) RAMP: Ramp Pin. Connect a capacitor to GND. Rising slope is programmed by current in SLOPE. This slope is compared to FEEDBK for pulse width modulation. The falling slope is programmed by the current in ISET and used to limit maximum duty cycle. FREQ: Oscillator pin. Program the frequency with a capacitor to GND. VREF: Precision 5V reference, and bypass point for internal circuitry. Bypass this pin with a 1F minimum capacitor to GND. GND: Analog ground. Connect to a low impedance ground plane containing all analog low current returns. SOFTST: Soft start pin. Program with a capacitor to GND. COUNT: Program the time that fault events will be tolerated before shutdown occurs with a capacitor and resistor to GND. CURLIM: Current Limit Sense pin. Terminates OUT gate drive pulse for inputs over 0.2V. Enables fault counting function (COUNT). For inputs over 0.6V, the shutdown latch is activated. APPLICATION INFORMATION (Note: Refer to Typical Application for external component names.) All the equations given below should be considered as first order approximations with final values determined empirically for a specific application. Power Sequencing VCC normally connects through a high impedance (R5) to the rectified line, with an additional path(R6) to a low voltage, bootstrap on the winding power transformer. VFWD normally connects to a divider (R1 and R2) from the rectified line. For circuit activation, all of the following considerations are required: 1. VFWD between 1V and 4V 2. VCC has been under 9V (to reset the shutdown latch) 3. VCC over 13V At this time, the circuit will activate. IVCC will increase from its start up value of 85A to its run value of 1mA. The capacitor on SOFTST is charged with a current determined by: -I SOFTST = 1V . R4 Output Inhibit During normal operation, OUT is driven high at the start of a clock period and back low when RAMP either crosses FEEDBK or equals 4V. If, however, any of the following occur, OUT is immediately driven low for the remainder of the clock period: 1. VFWD is outside the range of 1V to 4V 2. CURLIM is greater than 0.2V 3. FEEDBK or SOFTST is less than 1V Normal output pulses will not resume until the beginning of the next clock period in which none of the above conditions exist. Current Limiting CURLIM is monitored by two internal comparators. The current limit comparator threshold is 0.2V. If the current limit comparator is triggered, OUT is immediately driven low and held low for the remainder of the clock cycle, providing pulse-by-pulse overcurrent control for excessive loads. This comparator also causes CF to be charged for the remainder of the clock cycle. The charging current is -ICOUNT = 1V . R4 When SOFTST rises above 1V, output pulses will begin and IVCC will further rise to a level dictated by gate charge requirements asIVCC 1mA + QTfs. With output pulses, the low voltage bootstrap winding should now power the controller. If VCC falls below 9V, the controller will turn off and the start sequence will reset and retry. VCC Clamp An internal shunt regulator clamps VCC so that it will not exceed 15V. If repetitive cycles are terminated by the current limit comparator causing COUNT to rise above 4V, the shutdown latch is set. The COUNT integration delay feature will be bypassed by the shutdown comparator which has a 0.6V threshold. The shutdown comparator immediately sets the shutdown latch. RF in parallel with CF resets the COUNT integrator following transient faults. RF must be ( 4 * R 4) . greater than (1 - DMAX ) 4 UCC1570 UCC2570 UCC3570 APPLICATION INFORMATION (cont.) Latched Shutdown If CURLIM rises above 0.6V, or COUNT rises to 4V, the shutdown latch will be set. This will force OUT low, discharge SOFTST and COUNT, and reduce IVCC to approximately 1mA. When, and if, VCC falls below 9V, the shutdown latch will reset and IVCC will fall to 85A, allowing the circuit to restart. If VCC remains above 9V, an alternate restart will occur if VFWD is momentarily reduced below 1V. External shutdown commands from any source may be added into either the COUNT or CURLIM pins. Deadtime Control The voltage waveform on RAMP has independently controlled rising and falling edges. At the start of the clock period, RAMP is at 1V and rises to 4V. It then discharges back to 1V and awaits the next clock period. OUT can only be high during the rising part of the waveform, while it is positively blanked off during the falling portion. Setting the -dV/dt slope by R4 from ISET to GND establishes a minimum deadtime as: Choose R4 between 20k and 200k and CR greater than 50pF. In order to have a pulse at OUT in the next clock period, RAMP must fall to 1V prior to the end of the current period. If it does not, OUT will remain low for the entire next clock period. Voltage Feedforward The +dV/dt on RAMP is made proportional to line voltage. The slope is: dV VFWD = 10 * dt (R3 * CR ) where VFWD is line voltage scaled by R1 and R2. Therefore, a changing line voltage will accomplish an immediate proportionate pulse width change without any action from the feedback amplifier. This will result in constant volt-second drive to the power transformer providing both international voltage operation, and excellent dynamic line regulation. VFWD is intended to operate over a 4:1 range (1V to 4V) with undervoltage and overvoltage sensors designed to drive OUT low if this range is exceeded. Choose R3 between 20k and 200k. td = 0.3 * R 4 * CR Figure 1. UCC1570 typical application. 5 UCC1570 UCC2570 UCC3570 APPLICATION INFORMATION (cont.) Frequency Set A capacitor from FREQ to GND will determine a constant clock frequency. Frequency is: be able to sink (4 * I4) with at a voltage less than the 3.5V upper threshold of the oscillator. It must also be able to source 36 * I4 at a voltage greater than the 1.5V lower threshold of the oscillator. As long as FREQ is held high, the output is guaranteed to be low. Gate Drive Output The UCC1570 is capable of 1A peak output current. Bypass VCC with at least 0.1F directly to PGND. Use a capacitor with low equivalent series resistance and inductance. The connection from OUT to the MOSFET gate should have a 2 or greater damping resistor and the length should be minimized. A low impedance connection must be established between the MOSFET source (or the ground side of the current sense resistor), the VCC bypass capacitor and PGND. PGND should then be connected by a single path (shown as RGND in the application) to GND. F= (R 4 * CT ) 1.8 If required, frequency can be trimmed down from the above equation by the addition of RT from FREQ to GND. The reduction in frequency is a function of the ratio of RT/R4. RT should be greater than 2.4 * R4 for reliable operation. External synchronization can be accomplished by coupling a narrow pulse to a resistor inserted in series with the ground side of CT. The value should be less than R4/200 and the synchronizing pulse width should be less than 5% of the oscillator period. External synchronization can also be accomplished by driving FREQ with an CMOS inverter. The inverter must CLOCK FEEDBK RAMP OUT HIGH VIN LOW VIN FAULT VIN Figure 2. Ramp and PWM waveforms. 6 UCC1570 UCC2570 UCC3570 APPLICATION INFORMATION (cont.) Figure 3. Clock generator. Figure 4. External clock synchronization. Figure 5. Frequency dependence on RT/ R4 ratio. 7 APPLICATION INFORMATION (cont.) UCC1570 UCC2570 UCC3570 UNITRODE CORPORATION 7 CONTINENTAL BLVD. * MERRIMACK, NH 03054 TEL. (603) 424-2410 FAX (603) 424-3460 8 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof. Copyright (c) 2000, Texas Instruments Incorporated |
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