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SI9113 New Product Vishay Siliconix High-Voltage Current Mode PWM Controller for ISDN Power Supplies FEATURES D D D D D BiC/DMOS Technology Current Mode Control Max 50% Duty Cycle Operation 1.3-MHz Error Amp Up to 500-kHz Internal Oscillator D D D D D Soft-Start 0.6-V Fast Over-Current Protection <5-mA Supply Current for +VIN <18 V 23.5-V to 200-V Input Voltage Range Programmable Start/Stop Capability D Internal Start-Up Circuit D Power_Good Output DESCRIPTION SI9113 is a current mode PWM controller for ISDN power supplies. In a 14-pin SOIC package, it provides all necessary functions to implement a single-switch PWM with a minimum of external parts. To maximize the circuit integration, the SI9113 is designed with a 200-V depletion mode MOSFET capable of powering directly off the high input bus without an external start-up circuit. The Start and Stop input voltage thresholds can be programmed within the operating input voltage range by means of a resistor divider, provided +VIN (Start) > +VIN (Stop). The internal clock frequency is set with a single external resistor and is capable of capacitor-coupled external synchronization. In order to satisfy the stringent ambient temperature requirements, the SI9113 is rated to handle the industrial range of -40_C to 85_C. FUNCTIONAL BLOCK DIAGRAM VIN (23.5 V to 200 V) VOUT Start-Up Stop/Start Drive Current Power_Good Comparator VREF = 1.3 V Fast Current Limit Comparator For Detailed Block Diagram See Page 7. Document Number: 71093 S-99453--Rev. A . 29-Nov-99 www.siliconix.com S FaxBack 408-970-5600 1 SI9113 Vishay Siliconix ABSOLUTE MAXIMUM RATINGS VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 V VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V Logic Inputs (OSC IN, OSC OUT, PWR_GOOD) . . . -0.3 V to VCC + 0.3 V or "10 mA Linear Inputs (FB, VREF, SENSE, SS) . . . . . . . . . . . . -0.3 V to VCC + 0.3 V Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to 150_C Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 to 85_C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150_C Power Dissipation (Package)a 14-Pin SOIC (Y Suffix)b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900 mW Thermal Impedance (QJA) 14-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140_C/W Notes a. Device mounted with all leads soldered or welded to PC board. b. Derate 7.2 mW/_C above 25_C. New Product Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING RANGE VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.5 V to 200 V VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 V to 14 V Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to VCC Linear Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to VCC - 3 V FOSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 kHz to 500 kHz SPECIFICATIONSa Test Conditions Unless Otherwise Specified Parameter Reference Output Voltage Short Circuit Current Load Regulation Line Regulation VREF ISREF DVREF OSCIN = - VIN (OSC Disabled) RL = 10 MW VREF = -VIN IREF = 0 to -0.5 mA VCC = 10 to 14 V Room Full Room Full Full 1.275 1.26 1.3 1.3 -25 "10 "2 1.325 1.34 -10 40 mV 5 V mA Limits -40 to 85_C Symbol VCC = 10 V, +VIN = 48 V, ROSC = 390 kW Tempb Minc Typd Maxc Unit UVLO Under Voltage Lockout VUVSTART VUVSTOP ISTART ISTOP Pre-Regulated VCC UVLO for VCC VREG - VCCUV VREG VCCUV VD Turn-On Turn-Off VSTOP = 8 V, VSTART = 8 V Full Full Room Room Room Room Room 8.5 7.9 0.3 9.0 8.4 0.6 8.10 8.10 8.8 8.8 9.50 9.50 0.05 0.05 9.5 8.9 V V Input Bias Current mA PWR_Good Comparator Rise Time Fall Time Output Logic Low trpg tfpg Room CPWR Good = 100 nF PWR_Good ISINK = 2.5 mA Room Room 35 25 0.4 0.8 mS mS V Soft-Start SS Current Output Inhibit Voltage ISS VSS Room Room 11 3.3 mA V Oscillator Maximum Frequencye Initial Accuracy Voltage Stability Temperature Coefficiente Maximum Duty Cycle fMAX fOSC Df/f TOSC DMAX fOSC = 100 kHz ROSC = 0 ROSC = 390 k (Note f) ROSC = 180 k (Note f ) Df/f = (f [14 V] - f [10 V]) / f [10 V] Room Room Room Room Full Room 500 80 160 100 200 10 450 50 120 240 15 650 % ppm/_C % Document Number: 71093 S-99453--Rev. A . 29-Nov-99 kHz kH www.siliconix.com S FaxBack 408-970-5600 2 SI9113 New Product SPECIFICATIONSa Test Conditions Unless Otherwise Specified Parameter Error Amplifier Open Loop Voltage Gaine Input BIAS Current Feedback Input Voltage Dynamic Output Impedancee Unity Gain Bandwidthe Output Current Power Supply Rejectione AVOL IBIAS VFB ZOUT BW IOUT PSRR Source VFB = 0.8 V Sink VFB = 1.8 V OSC IN = - VIN VFB = 1.3 V FB Tied to COMP, OSC IN = - VIN Room Room Full Room Room Room Room Room 0.12 50 1 50 -1 1.28 1 1.3 -5 0.15 70 dB -1 mA 60 1 1.32 2 dB mA V kW MHz Vishay Siliconix Limits -40 to 85_C Symbol VCC = 10 V, +VIN = 48 V, ROSC = 390 kW Tempb Minc Typd Maxc Unit Current Limit Comparator Threshold Voltage Delay to Outpute VSOURCE td VFB = 0 V VSENSE = 0.85 V, See Figure 1 Full Full 0.5 0.6 100 0.7 150 V ns Output Drive Output High Voltage Output Low Voltage Rise Time Fall Time VOH VOL tr tf IOUT = -10 mA IOUT = 10 mA CL = 500 p pF (10% t 90%) to Room Full Room Full Room Room 40 40 9.7 9.5 0.3 0.5 75 ns 75 V Supply ICC Supply Current IVIN Supply Current UVLO Mode IVIN VCC = 10 V, ROSC = 390 kW VUVUP vVIN v 200 V Excluding I From Resistive Divider of Stop and Start Pins +VIN v 18 V, VSTART (Pin 14) < 8.8 V Full Room Room 1 75 2 1.4 100 5 mA m mA Notes a. Refer to PROCESS OPTION FLOWCHART for additional information. b. Room = 25_C, Full = -40 to 85_C. c. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum. d. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. e. Guaranteed by design, not subject to production test. f. CSTRAY Pin 8 = v 5 pF. TIMING WAVEFORMS 0.85 V - 50% td VCC OUTPUT 0- 90% SENSE 0 tr v 10 ns FIGURE 1. Delay Time for Current Sense Document Number: 71093 S-99453--Rev. A . 29-Nov-99 www.siliconix.com S FaxBack 408-970-5600 3 SI9113 Vishay Siliconix New Product TYPICAL CHARACTERISTICS (25_C UNLESS NOTED) 1.306 VREF vs. Temperature (VIN = 48 V) 9.1 9.0 VUVSTART /VUVSTOP (v) 8.9 8.8 8.7 8.6 8.5 VUVSTART/VUVSTOP vs. Temperature VCC = 14 V 1.304 VREF - (V) 1.302 VCC = 12 V VCC = 10 V 1.300 1.298 -50 -25 0 25 50 75 100 8.4 -50 -25 0 25 50 75 100 Temperature (_C) Temperature (_C) Output Frequency vs. Oscillator Resistance 300 2.0 Supply Current vs. Output Frequency VCC = 10 V FOUT (kHz) I CC (mA) 1.6 VCC = 14 V 1.2 VCC = 10 V VCC = 12 V 0.8 100 0.4 10 10 100 FOSC (kW) 1000 2000 0 0 50 100 150 FOUT (kHz) 200 250 300 Output Frequency vs. Supply Voltage 24 ROSC = 1 MW 22 85_C FOUT (kHz) -40_C 18 I SS ( m A) 20 25_C 12 13 Soft-Start Current vs. Temperature VCC = 10 V 11 10 9 16 8 14 9 10 11 12 VCC (V) www.siliconix.com S FaxBack 408-970-5600 13 14 15 7 -40 -20 0 20 40 60 80 100 Temperature (_C) Document Number: 71093 S-99453--Rev. A . 29-Nov-99 4 SI9113 New Product TYPICAL CHARACTERISTICS (25_C UNLESS NOTED) Vishay Siliconix UVLO Supply Current vs. VIN 10 80 Output Rise Time vs. Load VCC = 10 V 60 85_C I IN ( (mA) Rise/Fall Time (nS) -40_C 0.1 11 13 15 VIN (V) 17 19 21 0 0 200 400 COUT (pF) 600 800 VIN = 28 V VIN = 48 V VIN = 99 V 50 40 30 20 10 0 200 400 600 WO (mW) 800 1000 1 25_C 40 20 Efficiency vs. Output Power 90 80 70 Efficiency (%) 60 Document Number: 71093 S-99453--Rev. A . 29-Nov-99 www.siliconix.com S FaxBack 408-970-5600 5 SI9113 Vishay Siliconix New Product PIN CONFIGURATION SOIC-14 STOP VIN SENSE PWR_GOOD -VIN DRIVER VCC 1 2 3 4 5 6 7 Top View 14 START 13 COMP 12 FB ORDERING INFORMATION Part Number SI9113DY SI9113DY-T1 Temperature Range -40 to 85_C Package Bulk Tape and Reel SI9113 11 VREF 10 SS 9 8 OSCOUT OSCIN Eval Kit SI9113D1 SI9113D2 Temperature Range -10 to 70_C Board Type Surface Mount and Thru-Hole Th H l PIN DESCRIPTION Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Name STOP +VIN SENSE PWR_GOOD -VIN DRIVER VCC OSCIN OSCOUT SS VREF FB COMP START Input voltage to UVLO and Start-Up circuitry Function Set up the stop threshold of +VIN for VCC via resistive dividers Current sense amplifier input for current mode control and OCP. Logic high PWR_Good signal indicates FB voltage is within regulation. Ground pin MOSFET gate drive signal. Supply voltage to internal circuitry and MOSFET gate drive. ROSC terminal ROSC terminal, square waveform output Soft-Start, time programmed by capacitor value. 1.3-V reference. Decoupled with 0.1-mF capacitor. Inverting input of an error amplifier. Error amplifier output for external compensation network. Set up the start threshold of +VIN for VCC via resistive dividers www.siliconix.com S FaxBack 408-970-5600 6 Document Number: 71093 S-99453--Rev. A . 29-Nov-99 SI9113 New Product DETAILED BLOCK DIAGRAM Vishay Siliconix 8 OSCIN COMP 13 VCC OSC 4 12 11 - + Error Amplifier 3.6 V +- - + S Ref Gen + - 0.6 V C/L Comparator PWM Comparator R Q MOS Driver Clock (1/2 fOSC) 9 OSCOUT PWR_GOOD FB VREF 6 DRIVER 5 -VIN SS 10 3 SENSE VCC VIN STOP START 7 2 1 14 Enable Programmable Start/Stop Circuit Start-Up Pre-Regulator DETAILED DESCRIPTION Start-Up The SI9113 start-up circuit prevents the internal circuits from turning on until the voltage on the +VIN pin, via the resistor divider R3, R4, R5, is sufficiently positive such that the voltage across R3 (VSTART) is >8.8 V (typical value for the internal reference VUVSTART [see Figure 2]). When this occurs, the internal 1.3-V reference, soft-start and oscillator circuits are enabled. A constant current source provides the current to the external soft-start capacitor, which allows the output voltage to rise gradually without overshoot. The output drive circuit is disabled until the soft-start voltage reaches 3.3 V. The controller is continuously powered in the state until the VIN voltage falls and VSTOP drops below 8.8 V (the typical value for the internal reference VUVSTOP). The user can program the +VIN START and +VIN STOP voltage with the external resistor divider R3-R5 (see Figure 2) as follows: V IN(START) + V IN(STOP) + R3 ) R4 ) R5 R5 R3 ) R5 R5 V UVSTART (1) V UVSTOP (2) Since VUVSTART = VUVSTOP = 8.8 V (typical) the hysteresis voltage can be expressed as: Document Number: 71093 S-99453--Rev. A . 29-Nov-99 www.siliconix.com S FaxBack 408-970-5600 7 SI9113 Vishay Siliconix New Product DV IN + R4 R5 V UVSTART (3) VCC Circuit The depletion MOSFET process allows the SI9113 controller to power directly from the high input bus voltage. Once VUVSTART is met, the pre-regulator start-up circuit generates the 9.0-V VCC voltage. The VCC voltage is used internally to power the IC as well as providing the drive current for the external MOSFET. An internal VCC circuit is disabled once a higher external voltage (X10 V) is applied to this pin. If VCC is below VCCUV, the SI9113 will inhibit the driver output switching. REF The reference voltage of SI9113 is set at 1.3 V. The reference voltage is internally connected to the non-inverting input of error amplifier. The reference is decoupled with 0.1-mF capacitor. Soft-Start The soft-start circuit provides a constant 10-mA current to external capacitor attached to SS pin. A constant soft-start current forces a gradual increase in duty cycle which in turn ensures gradual output voltage rise without overshooting. The soft-start time is programmed by the capacitance value. Oscillator The oscillator consists of a ring of CMOS inverters, capacitors, and a capacitor discharge switch. An external resistor, ROSC, between the OSCIN and OSCOUT pins sets the frequency. The maximum frequency is obtained when ROSC = 0 W. A frequency divider in the logic section limits the switch duty cycle to 50% by locking the switching frequency to one-half of the oscillator frequency. PWM Mode period eliminating any chance of undesirable noise frequency. When the output load current decreases to 0 A, the controller is forced to enter the pulse skipping mode. This is a natural phenomenal for all controllers since the duty cycle cannot decrease linearly to 0%. Error Amplifier The error amplifier gain-bandwidth product and slew rate are critical parameters which determine the transient response of converter. The transient response is the function of both small and large signal responses. The small signal response is determined by the converter closed loop bandwidth and phase margin while the large signal is determined by the error amplifier dv/dt and the inductor di/dt slew rate. Besides the inductance value, the error amplifier determines the converter response time. In order to minimize the response time, the SI9113 is designed with 1.3-MHz error amplifier gain-bandwidth product to generate the widest converter bandwidth. Current Limit Over current protection circuit is provided by monitoring the voltage on the Sense pin. Once the current sense voltage reaches 0.6V peak, the output drive stage is disabled for the remainder of the clock cycle. Power_Good Comparator The PWR_Good signal indicates the status of output voltage. If the output voltage and VCC are within regulation, the PWR_Good signal generates a logic high output by monitoring the voltage on COMP and VCC pins. If either one is out of regulation, a logic low PWR_Good signal is generated. The capacitor at the PWR_Good pin determines the rise time of the power good signal, once all the conditions are met for power good. The PWR_Good signal is an open collector output capable of sinking 2.5 mA. MOSFET Gate Drive As the load and line voltage vary, the switching frequency remains constant. The switching frequency is programmed by the ROSC value as shown by the oscillator curve. In the PWM mode, a duty cycle pulse is generated for each switching The DRIVER pin is designed to drive the low-side n-channel MOSFET. Typically, the driver stage is sized to sink and source 200-mA of peak current when VCC = 12 V. www.siliconix.com S FaxBack 408-970-5600 8 Document Number: 71093 S-99453--Rev. A . 29-Nov-99 SI9113 New Product TYPICAL APPLICATION CIRCUITS Vishay Siliconix 28 - 99 V +VIN 4 3 -VIN BR1 AC + AC - DF02S R13 C4 1 mF 2.7 W 3.3 V 1 2 + C1 22 mF 160 V D1 ESIG D3 B130LB 8 7 NS3 9 T1 XFMR_EPC17 1 D2 ESIG 3 + 1 40 V 6 C10 NS2 2.2 mF 50 V 3 D4* BZX84C43 COM2 NP 5 C5 0.1 mF R9 20 kW R1 R10 13 kW 1 MW C7 0.001 mF C6 0.1 mF 8 OSCIN 9 OSCOUT 10 SS 11 VREF 12 FB 13 COMP 14 R2 C8 300 kW 0.01 mF C3 100 pF START VIN STOP 1 ICS 2 PWR_G 3 GND 4 DR 5 VCC 6 7 COM1 C12 0.1 mF C10 220 mF 10 V 1, 2, 5, 6 3 4 Q01 Si3420DV R1 1 1 kW C9 220 pF R3 5.1 MW R2 2W 1/ W 2 SI9113 R4 1 MW R5 3.96 MW *Optional FIGURE 2. Dual Output Flyback Converter with 2% Regulation for 3.3 V ( As used on Demo Board--DB1) Document Number: 71093 S-99453--Rev. A . 29-Nov-99 www.siliconix.com S FaxBack 408-970-5600 9 SI9113 Vishay Siliconix TYPICAL APPLICATION CIRCUITS New Product 28 - 99 V +VIN 4 3 -VIN BR1 AC + AC - DF02S R13 2.7 W 1 2 + C1 22 mF 160 V D1 ESIG 8 T1 XFMR_EPC17 4 D2 ESIG 3 + 40 V 5 C10 NS2 2.2 mF 50 V 3 D4* BZX84C43 COM2 1 NP R9 89 kW C4 1 mF NS3 9 2 D3 B130LB 3.3 V NS1 R10 12.7 kW R1 1 MW C7 0.001 mF C6 0.1 mF 8 OSCIN 9 OSCOUT 10 SS 11 VREF 12 FB 13 COMP 14 R2 C8 300 kW 0.01 mF C3 100 pF START VIN STOP 1 ICS 2 1 kW C9 470 pF R3 5.1 MW R4 1 MW R5 3.96 MW *Optional R2 2W 1/ W 2 PWR_G 3 R11 GND 4 DR 5 4 VCC 6 7 C5 0.1 mF 3 1, 2, 5, 6 6 1 C11 220 mF 10 V + C12 0.1 mF COM1 Q01 Si3420DV SI9113 FIGURE 3. Dual Output Flyback Converter with Moderately Regulated Outputs (As used on Demo Board DB-2) www.siliconix.com S FaxBack 408-970-5600 10 Document Number: 71093 S-99453--Rev. A . 29-Nov-99 |
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