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W83697SF WINBOND I/O
W83697SF Data Sheet Revision History
Pages Dates Version Version on Web 1 2 3 4 5 6 7 8 9 10 n.a. 111 04/16/01 04/27/01 12/16/02 0.50 0.51 1.0 0.50 0.51 1.0 First published Update the Top Marking New Update Main Contents
Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
W83697SF
TABLE OF CONTENT
GENERAL DESCRIPTION.............................................................................................................. 1 PIN CONFIGURATION FOR 697SF ................................................................................................ 6 1. PIN DESCRIPTION................................................................................................................... 7 1.1 LPC INTERFACE ........................................................................................................................ 9 1.2 FDC INTERFACE........................................................................................................................ 9 1.3 MULTI-MODE PARALLEL PORT.....................................................................................................11 1.4 SERIAL PORT INTERFACE............................................................................................................16 1.5 INFRARED PORT........................................................................................................................17 1.6 FLASH ROM INTERFACE ............................................................................................................17 1.7 GENERAL PURPOSE I/O PORT .....................................................................................................18 1.8 SMART CARD INTERFACE............................................................................................................18 1.9 PWM & GENERAL PURPOSE I/O PORT 8 ......................................................................................19 1.10 GAME PORT & MIDI PORT........................................................................................................19 1.11 POWER PINS ......................................................................................................................20 2. SMART CARD READER INTERFACE (SCR) ...............................................................................21 2.1 FEATURES ..............................................................................................................................21 2.2 REGISTER FILE..........................................................................................................................22 2.3 SMART CARD ID NUMBER (BASE ADDRESS + 2 WHEN BDLAB = 1, FIXED AT 70H) .................................37 2.4 FUNCTIONAL DESCRIPTION..........................................................................................................37 2.5 INITIALIZATION .........................................................................................................................37 2.6 ACTIVATION.............................................................................................................................38 2.7 ANSWER-TO-RESET...................................................................................................................38 2.8 DATA TRANSFER ......................................................................................................................40 2.9 COLD RESET AND WARM RESET ....................................................................................................40 2.10 POWER STATES......................................................................................................................40 2.11 DISABLED STATE ....................................................................................................................40 2.12 ACTIVE STATE........................................................................................................................41 2.13 IDLE STATE............................................................................................................................41 2.14 POWER DOWN STATE...............................................................................................................41 3. CONFIGURATION REGISTER ..................................................................................................42 3.1 PLUG AND PLAY CONFIGURATION ................................................................................................42 3.2 COMPATIBLE PNP .....................................................................................................................42 3.2.1 Extended Function Registers .............................................................................................42 3.2.2 Extended Functions Enable Registers (EFERs) ..................................................................43 3.2.3 Extended Function Index Registers (EFIRs), Extended Function Data Registers(EFDRs)........43 3.3 CONFIGURATION SEQUENCE.........................................................................................................43
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W83697SF
3.3.1 Enter the extended function mode......................................................................................43 3.3.2 Configurate the configuration registers................................................................................43 3.3.3 Exit the extended function mode ........................................................................................44 3.3.4 Software programming example .........................................................................................44 3.4 CHIP (GLOBAL) CONTROL REGISTER .............................................................................................45 3.5 LOGICAL DEVICE 0 (FDC)...........................................................................................................51 3.6 LOGICAL DEVICE 1 (PARALLEL PORT) ...........................................................................................55 3.7 LOGICAL DEVICE 2 (UART A)......................................................................................................56 3.8 LOGICAL DEVICE 3 (UART B)......................................................................................................57 3.9 LOGICAL DEVICE 7 (GAME PORT AND GPIO PORT 1) .......................................................................59 3.10 LOGICAL DEVICE 8 (MIDI PORT AND GPIO PORT 5).......................................................................60 3.11 LOGICAL DEVICE 9 (GPIO PORT 2 ~ GPIO PORT 4 ).....................................................................62 3.12 LOGICAL DEVICE A (ACPI)........................................................................................................63 3.13 LOGICAL DEVICE B (PWM).......................................................................................................69 3.14 LOGICAL DEVICE C (SMART CARD)..........................................................................................69 3.15 LOGICAL DEVICE D (GPIO PORT 6 )...........................................................................................70 3.16 LOGICAL DEVICE E (GPIO PORT 7 )...........................................................................................71 3.17 LOGICAL DEVICE F (GPIO PORT 8) ............................................................................................72 4. SPECIFICATIONS ...................................................................................................................74 4.1 ABSOLUTE MAXIMUM RATINGS.....................................................................................................74 4.2 DC CHARACTERISTICS .........................................................................................................74 5. APPLICATION CIRCUITS ........................................................................................................82 5.1 PARALLEL PORT EXTENSION FDD................................................................................................82 5.2 PARALLEL PORT EXTENSION 2FDD ..............................................................................................83 5.3 FOUR FDD MODE .....................................................................................................................83 6. ORDERING INSTRUCTION ......................................................................................................84 7. HOW TO READ THE TOP MARKING........................................................................................84 8. PACKAGE DIMENSIONS .........................................................................................................85 APPENDIX A : DEMO CIRCUIT.....................................................................................................86
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Publication Release Date: Dec 2002 Revision 1.0
W83697SF
GENERAL DESCRIPTION
The W83697SF is evolving product from Winbond's most popular I/O family. They feature a whole new interface, namely LPC (Low Pin Count) interface, which will be supported in the new generation chipset. This interface as its name suggests is to provide an economical implementation of I/O's interface with lower pin count and still maintains equivalent performance as its ISA interface counterpart. Approximately 40 pin counts are saved in LPC I/O comparing to ISA implementation. W this ith additional freedom, we can implement more devices on a single chip as demonstrated in W83697SF's integration of Game Port and MIDI Port. It is fully transparent in terms of software which means no BIOS or device driver update is needed except chip-specific configuration. As Smart Card application is gaining more and more attention, W83697SF also implements a smart card reader interface featuring Smart wake-up function. This smart card reader interface fully meets the ISO7816 and PC/SC (Personal C omputer/Smart Card Workgroup) standards. W83697SF provides a minimum external components and lowest cost solution for smart card applications. The disk drive adapter functions of W83697SF include a floppy disk drive controller compatible with the industry standard 82077/ 765, data separator, write pre-compensation circuit, decode logic, data rate selection, clock generator, drive interface control logic, and interrupt and DMA logic. The wide range of functions integrated onto the W83697SF greatly reduces the number of components required for interfacing with floppy disk drives. The W83697SF supports four 360K, 720K, 1.2M, 1.44M, or 2.88M disk drives and data tranSFer rates of 250 Kb/s, 300 Kb/s, 500 Kb/s,1 Mb/s, and 2 Mb/s. The W83697SF provides two high-speed serial communication ports (UARTs), one of which supports serial Infrared communication. Each UART includes a 16-byte send/receive FIFO, a programmable baud rate generator, complete modem control capability, and a processor interrupt system. Both UARTs provide legacy speed with baud rate up to 115.2k bps and also advanced speed with baud rates of 230k, 460k, or 921k bps which support higher speed modems. In addition, the W83697SF provides IR functions: IrDA 1.0 (SIR for 1.152K bps) and TV remote IR ( onsumer IR, supporting NEC, RC-5, C extended RC-5, and RECS-80 protocols). The W83697SF supports one PC-compatible printer port (SPP), Bi-directional Printer port (BPP) and also Enhanced Parallel Port (EPP) and Extended Capabilities Port (ECP). Through the printer port interface pins, also available are: Extension FDD Mode and Extension 2FDD Mode allowing one or two external floppy disk drives to be connected. The configuration registers support mode selection, function enable/disable, and power down function selection. Furthermore, the configurable PnP features are compatible with the plug-and-play feature demand of Windows 95/98
TM
, which makes system resource allocation more efficient than ever.
The W83697SF provides a set of flexible I/O control functions to the system designer through a set of General Purpose I/O ports. These GPIO ports may serve as simple I/O or may be individually configured
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W83697SF
to provide a predefined alternate function. General Purpose Port 1 is designed to be functional even in power down mode (VCC is off).
(c) The W83697SF is made to fully comply with Microsoft(c) PC98 and PC99 Hardware Design Guide, and meet the requirements of ACPI.
The W83697SF contains a game port and a MIDI port. The game port is designed to support 2 joysticks and can be applied to all standard PC game control devices, They are very important for a entertainment or consumer computer. The W83697SF provides Flash ROM interface. That can support up to 4M legacy flash ROM. Moreover, W83697SF support 3 sets PWM Fan Speed Control, which are very important for a highend computer system to work stably and properly.
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W83697SF
FEATURES
General
* * * * * * * * Meet LPC Spec. 1.1 Support LDRQ#(LPC DMA), SERIRQ (serial IRQ) Include all the features of Winbond I/O W83877TF Integrate Smart Card functions Compliant with Microsoft PC98/PC99 Hardware Design Guide Support DPM (Device Power Management), ACPI Programmable configuration settings Single 24 or 48 MHz clock input
FDC
* * * * * * * * * * * * * Compatible with IBM PC AT disk drive systems Variable write pre-compensation with track selectable capability Support vertical recording format DMA enable logic 16-byte data FIFOs Support floppy disk drives and tape drives Detects all overrun and underrun conditions Built-in address mark detection circuit to simplify the read electronics FDD anti-virus functions with software write protect and FDD write enable signal (write data signal was forced to be inactive) Support up to four 3.5-inch or 5.25-inch floppy disk drives Completely compatible with industry standard 82077 360K/720K/1.2M/1.44M/2.88M format; 250K, 300K, 500K, 1M, 2M bps data transfer rate Support 3-mode FDD, and its Win95/98 driver
UART
* * * Two high-speed 16550 compatible UARTs with 16-byte send/receive FIFOs MIDI compatible Fully programmable serial-interface characteristics: --- 5, 6, 7 or 8-bit characters --- Even, odd or no parity bit generation/detection --- 1, 1.5 or 2 stop bits generation Publication Release Date: Dec 2002 Revision 1.0
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W83697SF
*
Internal diagnostic capabilities: --- Loop-back controls for communications link fault isolation --- Break, parity, overrun, framing error simulation
* *
Programmable baud generator allows division of 1.8461 MHz and 24 MHz by 1 to (216-1) Maximum baud rate up to 921k bps for 14.769 MHz and 1.5M bps for 24 MHz
Infrared
* * * Support IrDA version 1.0 SIR protocol with maximum baud rate up to 115.2K bps Support SHARP ASK-IR protocol with maximum baud rate up to 57,600 bps Support Consumer IR with Wake-Up function.
Parallel Port
* * * * * * Compatible with IBM parallel port Support PS/2 compatible bi-directional parallel port Support Enhanced Parallel Port (EPP) - Compatible with IEEE 1284 specification Support Extended Capabilities Port (ECP) - Compatible with IEEE 1284 specification Extension FDD mode supports disk drive B; and Extension 2FDD mode supports disk drives A and B through parallel port Enhanced printer port back-drive current protection
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Game Port
* * Support two separate Joysticks Support every Joystick two axes (X,Y) and two buttons (S1,S2) controllers
MIDI Port
* * * The baud rate is 31.25 Kbaud 16-byte input FIFO 16-byte output FIFO
Flash ROM Interface
* Support up to 4M flash ROM
General Purpose I/O Ports
* * * 60 programmable general purpose I/O ports General purpose I/O ports can serve as simple I/O ports, watch dog timer output, power LED output, infrared I/O pins, suspend LED output, Beep output Functional in power down mode
Smart Card Reader Interface * *
ISO7816 protocol compliant PC/SC T=0, T=1 compliant
Fan Speed Control
* 3 Sets PWM Fan Speed Control
Package
* 128-pin PQFP
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GP63 GP62 GP61 GP60 SCPSNT/GP77 SCIO/GP76 SCCLK/GP75 SCRST/GP74 GP73 SCC8/GP72 SCPWR/GP71 SCC4/GP70 PWM2/PLED/GP83 PWM1/GP82 PWM0/GP81 WDTO/GP80 MSI/GP51 MSO/GP50 GPAS2/GP17 GPBS2/GP16 GPAY/GP15 GPBY/GP14 GPBX/GP13 GPAX/GP12 GPBS1/GP11 GPAS1/GP10 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
PIN CONFIGURATION FOR 697SF
W83697SF
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DRVDEN0 INDEX# MOA# DSB# VCC DSA# MOB# DIR# STEP# WD# WE# TRAK0# WP# RDATA# HEAD# DSKCHG# CLKIN GND PCICLK LDRQ# SERIRQ VCC3 LAD3 LAD2 LAD1 LAD0 LFRAME# LRESET# SLCT PE BUSY ACK# ERR# SLIN# PD7 PD6 PD5 PD4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39
102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 GP64 GP65 GP66 GP67 PME# MEMW#/GP52 MEMR#GP53 ROMCS#/GP54 XD0/GP20 XD1/GP21 XD2/GP22 XD3/GP23 GND XD4/GP24 XD5/GP25 XD6/GP26 XD7/GP27 XA0/GP30 XA1/GP31 XA2/GP32 XA3/GP33 XA4/GP34 XA5/GP35 XA6/GP36 XA7/GP37 XA8/GP40 XA9/GP41 VCC XA10/GP42 XA11/GP43 XA12/GP44 XA13/GP45 XA14/GP46 XA15/GP47 XA16/GP55 XA17/GP56 XA18/GP57 IRTX
W83697SF
Publication Release Date: Dec 2002 Revision 1.0
IRRX RIB# DCDB# SOUTB/PEN48 GND SINB DTRB# RTSB# DSRB# CTSB# RIA# DCDA# SOUTA/PENROM# SINA DTRA#/PNPCSV# RTSA#/HEFRAS DSRA# CTSA# STB# VCC AFD# INIT# PD0 PD1 PD2 PD3
W83697SF
1. PIN DESCRIPTION
Note: Please refer to Section 10.2 DC CHARACTERISTICS for details
PIN DESCRIPTION
I/O8t I/O12t I/O24t I/O12tp3 I/O12ts I/O24ts I/O24tsp3 I/OD12t I/OD24t I/OD24c I/OD24a I/OD12ts I/OD24ts I/OD12cs I/OD16cs I/OD24cs I/OD12csd I/OD12csu O4 O8 O12 O16 O24 O12p3 O24p3 OD12 OD24 TTL level bi-directional pin with 8mA source-sink capability TTL level bi-directional pin with 12mA source-sink capability TTL level bi-directional pin with 24 mA source-sink capability 3.3V TTL level bi-directional pin with 12mA source-sink capability TTL level Schmitt-trigger bi-directional pin with 12mA source-sink capability TTL level Schmitt-trigger bi-directional pin with 24mA source-sink capability 3.3V TTL level Schmitt-trigger bi-directional pin with 24mA source-sink capability TTL level bi-directional pin and open-drain output with 12mA sink capability TTL level bi-directional pin and open-drain output with 24mA sink capability CMOS level bi-directional pin and open-drain output with 24mA sink capability Bi-directional pin with analog input and open-drain output with 24mA sink capability TTL level Schmitt-trigger bi-directional pin and open-drain output with 12mA sink capability TTL level Schmitt-trigger bi-directional pin and open-drain output with 24mA sink capability CMOS level Schmitt-trigger bi-directional pin and open-drain output with 12mA sink capability CMOS level Schmitt-trigger bi-directional pin and open-drain output with 16mA sink capability CMOS level Schmitt-trigger bi-directional pin and open-drain output with 24mA sink capability CMOS level Schmitt-trigger bi-directional pin with internal pull down resistor and open-drain output with 12mA sink capability CMOS level Schmitt-trigger bi-directional pin with internal pull up resistor and open-drain output with 12mA sink capability Output pin with 4 mA source-sink capability Output pin with 8 mA source-sink capability Output pin with 12 mA source-sink capability Output pin with 16 mA source-sink capability Output pin with 24 mA source-sink capability 3.3V output pin with 12 mA source-sink capability 3.3V output pin with 24 mA source-sink capability Open-drain output pin with 12 mA sink capability Open-drain output pin with 24 mA sink capability
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W83697SF
OD12p3 INt INtp3 INtd INtu INts INtsp3 INc INcu INcd INcs INcsu
3.3V open-drain output pin with 12 mA sink capability TTL level input pin 3.3V TTL level input pin TTL level input pin with internal pull dow n resistor TTL level input pin with internal pull up resistor TTL level Schmitt-trigger input pin 3.3V TTL level Schmitt-trigger input pin CMOS level input pin CMOS level input pin with internal pull up resistor CMOS level input pin with internal pull down resistor CMOS level Schmitt-trigger input pin CMOS level Schmitt-trigger input pin with internal pull up resistor
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W83697SF
1.1 LPC Interface
SYMBOL CLKIN PME# PCICLK LDRQ# SERIRQ LAD[3:0] LFRAME# LRESET# PIN 17 98 19 20 21 23-26 27 28 I/O INtp3 OD12p3 INtsp3 O12p3 I/O12tp3 I/O12tp3 INtsp3 INtsp3 FUNCTION System clock input. According to the input frequency 24MHz or 48MHz, it is selectable through register. Default is 24MHz input. Generated PME event. PCI clock input. Encoded DMA Request signal. Serial IRQ input/Output. These signal lines communicate address, control, and data information over the LPC bus between a host and a peripheral. Indicates start of a new cycle or termination of a broken cycle. Reset signal. It can connect to PCIRST# signal on the host.
1.2 FDC Interface
SYMBOL DRVDEN0 INDEX# PIN 1 2 I/O OD24 INcsu Drive Density Select bit 0. This Schmitt-triggered input from the disk drive is active low when the head is positioned over the beginning of a track marked by an index hole. This input pin is pulled up internally by a 1 K resistor. The resistor can be disabled by bit 7 of L0-CRF0 (FIPURDWN). Motor A On. When set to 0, this pin enables disk drive 0. This is an open drain output. Drive Select B. When set to 0, this pin enables disk drive B. This is an open drain output. Drive Select A. When set to 0, this pin enables disk drive A. This is an open drain output. Motor B On. When set to 0, this pin enables disk drive 1. This is an open drain output. Direction of the head step motor. An open drain output. Logic 1 = outward motion Logic 0 = inward motion STEP# 9 OD24 Step output pulses. This active low open drain output produces a pulse to move the head to another track. Publication Release Date: Dec 2002 Revision 1.0 FUNCTION
MOA# DSB# DSA# MOB2#
3 4 6 7
OD24 OD24 OD24 OD24
DIR#
8
OD24
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W83697SF
WD# WE# TRAK0#
10 11 12
OD24 OD24 INcsu
Write data. This logic low open drain writes pre-compensation serial data to the selected FDD. An open drain output. Write enable. An open drain output. Track 0. This Schmitt-triggered input from the disk drive is active low when the head is positioned over the outermost track. This input pin is pulled up internally by a 1 K resistor. The resistor can be disabled by bit 7 of L0-CRF0 (FIPURDWN). Write protected. This active low Schmitt input from the disk drive indicates that the diskette is write-protected. This input pin is pulled up internally by a 1 K resistor. The resistor can be disabled by bit 7 of L0-CRF0 (FIPURDWN). The read data input signal from the FDD. This input pin is pulled up internally by a 1 K resistor. The resistor can be disabled by bit 7 of L0-CRF0 (FIPURDWN). Head select. This open drain output determines which disk drive head is active. Logic 1 = side 0 Logic 0 = side 1 Diskette change. This signal is active low at power on and whenever the diskette is removed. This input pin is pulled up internally by a 1 K resistor. The resistor can be disabled by bit 7 of L0-CRF0 (FIPURDWN).
WP#
13
INcsu
RDATA#
14
INcsu
HEAD#
15
OD24
DSKCHG#
16
INcsu
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W83697SF
1.3 Multi-Mode Parallel Port
The following pins have alternate functions, which are controlled by CR28 and L3-CRF0. SYMBOL SLCT PIN 29 I/O INts FUNCTION PRINTER MODE: An active high input on this pin indicates that the printer is selected. This pin is pulled high internally. Refer to the description of the parallel port for definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: WE2# This pin is for Extension FDD B; its function is the same as the WE# pin of FDC. EXTENSION 2FDD MODE: WE2# This pin is for Extension FDD A and B; its function is the same as the WE# pin of FDC. PRINTER MODE: An active high input on this pin indicates that the printer has detected the end of the paper. This pin is pulled high internally. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: WD2# This pin is for Extension FDD B; its function is the same as the WD# pin of FDC. EXTENSION 2FDD MODE: WD2# This pin is for Extension FDD A and B; its function is the same as the WD# pin of FDC.
WE2#
OD12
PE
30
INts
WD2#
OD12
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W83697SF
1.3 Multi-Mode Parallel Port, continued
SYMBOL BUSY
PIN 31
I/O INts
FUNCTION PRINTER MODE: An active high input indicates that the printer is not ready to receive data. This pin is pulled high internally. Refer to the description of the parallel port for definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: MOB2# This pin is for Extension FDD B; its function is the same as the MOB# pin of FDC. EXTENSION 2FDD MODE: MOB2# This pin is for Extension FDD A and B; its function is the same as the MOB# pin of FDC. PRINTER MODE: ACK# An active low input on this pin indicates that the printer has received data and is ready to accept more data. This pin is pulled high internally. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: DSB2# This pin is for the Extension FDD B; its functions is the same as the DSB# pin of FDC. EXTENSION 2FDD MODE: DSB2# This pin is for Extension FDD A and B; its function is the same as the DSB# pin of FDC. PRINTER MODE: ERR# An active low input on this pin indicates that the printer has encountered an error condition. This pin is pulled high internally. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: HEAD2# This pin is for Extension FDD B; its function is the same as the HEAD#pin of FDC. EXTENSION 2FDD MODE: HEAD2# This pin is for Extension FDD A and B; its function is the same as the HEAD# pin of FDC.
MOB2#
OD12
ACK#
32
INts
DSB2# OD12
ERR#
33
INts
HEAD2# OD12
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W83697SF
1.3 Multi-Mode Parallel Port, continued
SYMBOL SLIN#
PIN 34
I/O OD12
FUNCTION PRINTER MODE: SLIN# Output line for detection of printer selection. This pin is pulled high internally. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: STEP2# This pin is for Extension FDD B; its function is the same as the STEP# pin of FDC. EXTENSION 2FDD MODE: STEP2# This pin is for Extension FDD A and B; its function is the same as the STEP# pin of FDC. PRINTER MODE: INIT# Output line for the printer initialization. This pin is pulled high internally. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: DIR2# This pin is for Extension FDD B; its function is the same as the DIR# pin of FDC. EXTENSION 2FDD MODE: DIR2# This pin is for Extension FDD A and B; its function is the same as the DIR# pin of FDC. PRINTER MODE: AFD# An active low output from this pin causes the printer to auto feed a line after a line is printed. This pin is pulled high internally. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: DRVDEN0 This pin is for Extension FDD B; its function is the same as the DRVDEN0 pin of FDC. EXTENSION 2FDD MODE: DRVDEN0 This pin is for Extension FDD A and B; its function is the same as the DRVDEN0 pin of FDC.
STEP2#
OD12
INIT#
43
OD12
DIR2#
OD12
AFD#
44
OD12
DRVDEN0 OD12
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W83697SF
1.3 Multi-Mode Parallel Port, continued
SYMBOL STB#
PIN 46
I/O OD12
FUNCTION PRINTER MODE: STB# An active low output is used to latch the parallel data into the printer. This pin is pulled high internally. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: This pin is a tri-state output. EXTENSION 2FDD MODE: This pin is a tri-state output. PRINTER MODE: PD0 Parallel port data bus bit 0. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: INDEX2# This pin is for Extension FDD B; its function is the same as the INDEX# pin of FDC. It is pulled high internally. EXTENSION 2FDD MODE: INDEX2# This pin is for Extension FDD A and B; its function is the same as the INDEX# pin of FDC. It is pulled high internally. PRINTER MODE: PD1 Parallel port data bus bit 1. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: TRAK02# This pin is for Extension FDD B; its function is the same as the TRAK0# pin of FDC. It is pulled high internally. EXTENSION. 2FDD MODE: TRAK02# This pin is for Extension FDD A and B; its function is the same as the TRAK0# pin of FDC. It is pulled high internally. PRINTER MODE: PD2 Parallel port data bus bit 2. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: WP2# This pin is for Extension FDD B; its function is the same as the WP# pin of FDC. It is pulled high internally. EXTENSION. 2FDD MODE: WP2# This pin is for Extension FDD A and B; its function is the same as the WP# pin of FDC. It is pulled high internally.
PD0
42
I/O12ts
INDEX2#
INts
PD1
41
I/O12ts
TRAK02#
INts
PD2
40
I/O12ts
WP2#
INts
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W83697SF
1.3 Multi-Mode Parallel Port, continued
SYMBOL PD3
PIN 39
I/O I/O12ts
FUNCTION PRINTER MODE: PD3 Parallel port data bus bit 3. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: RDATA2# This pin is for Extension FDD B; its function is the same as the RDATA# pin of FDC. It is pulled high internally. EXTENSION 2FDD MODE: RDATA2# This pin is for Extension FDD A and B; its function is the same as the RDATA# pin of FDC. It is pulled high internally. PRINTER MODE: PD4 Parallel port data bus bit 4. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: DSKCHG2# This pin is for Extension FDD B; the function of this pin is the same as the DSKCHG# pin of FDC. It is pulled high internally. EXTENSION 2FDD MODE: DSKCHG2# This pin is for Extension FDD A and B; this function of this pin is the same as the DSKCHG# pin of FDC. It is pulled high internally. PRINTER MODE: PD5 Parallel port data bus bit 5. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: This pin is a tri-state output. EXTENSION 2FDD MODE: This pin is a tri-state output. PRINTER MODE: PD6 Parallel port data bus bit 6. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: This pin is a tri-state output. EXTENSION. 2FDD MODE: MOA2# This pin is for Extension FDD A; its function is the same as the MOA# pin of FDC. PRINTER MODE: PD7 Parallel port data bus bit 7. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: This pin is a tri-state output. EXTENSION 2FDD MODE: DSA2# This pin is for Extension FDD A; its function is the same as the DSA# pin of FDC.
RDATA2#
INts
PD4
38
I/O12ts
DSKCHG2#
INts
PD5
37
I/O12ts
PD6
36
I/OD12ts -
MOA2#
OD12
PD7
35
I/OD12ts
DSA2#
OD12
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1.4 Serial Port Interface
SYMBOL CTSA# CTSB# DSRA# DSRB# RTSA# HEFRAS PIN 47 55 48 56 49 I/O INt FUNCTION Clear To Send. It is the modem control input. The function of these pins can be tested by reading bit 4 of the handshake status register. Data Set Ready. An active low signal indicates the modem or data set is ready to establish a communication link and transfer data to the UART. UART A Request To Send. An active low signal informs the modem or data set that the controller is ready to send data. During power-on reset, this pin is pulled down internally and is defined as HEFRAS, which provides the power-on value for CR26 bit 6 (HEFRAS). A 4.7 k is recommended if intends to pull up. (select 4EH as configuration I/O ports address) UART B Request To Send. An active low signal informs the modem or data set that the controller is ready to send data. UART A Data Terminal Ready. An active low signal informs the modem or data set that the controller is ready to communicate. During power-on reset, this pin is pulled down internally and is defined as PNPCSV#, which provides the power-on value for CR24 bit 0 (PNPCSV#). A 4.7 k is recommended if intends to pull up. (clear the default value of FDC, UARTs, and PRT) UART B Data Terminal Ready. An active low signal informs the modem or data set that controller is ready to communicate. Serial Input. It is used to receive serial data through the communication link. UART A Serial Output. It is used to transmit serial data out to the communication link. During power on reset , this pin is pulled down internally and is defined as PENROM#, which provides the power on value for CR24 bit 1. A 4.7k is recommended if intends to pull up . UART B Serial Output. During power-on reset, this pin is pulled down internally and is defined as PEN48, which provides the poweron value for CR24 bit 6 (EN48). A 4.7 k resistor is recommended if intends to pull up. Data Carrier Detect. An active low signal indicates the modem or data set has detected a data carrier. Ring Indicator. An active low signal indicates that a ring signal is being received from the modem or data set.
INt
O8 INcd
RTSB# DTRA# PNPCSV#
57 50
O8 O8 INcd
DTRB# SINA SINB SOUTA PENROM# SOUTB PEN48
58 51 59 52
O8 INt O8
INcd 61 O8 INcd
DCDA# DCDB# RIA# RIB#
53 62 54 63
INt INt
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1.5 Infrared Port
SYMBOL IRRX PIN 64 I/O INts FUNCTION Alternate Function Input: Infrared Receiver input. General purpose I/O port 3 bit 6. IRTX 65 O12 Alternate Function Output: Infrared Transmitter Output. General purpose I/O port 3 bit 7.
1.6 Flash ROM Interface
SYMBOL XA18-XA16 GP57-GP55 XA15-XA10 GP47-GP42 XA9-XA8 GP41-GP40 XA7-XA0 GP37-GP30 XD7-XD4 GP27-GP24 XD3-XD0 GP23-GP20 ROMCS# GP54 MEMR# GP53 MEMW# GP52 97 96 95 91-94 86-89 78-85 76-77 69-74 PIN 66-68 I/O O12 I/OD12t O12 I/OD12t O12 I/OD12t O12 I/OD12t I/O12t I/OD12t I/O12t I/OD12t O12 I/OD12t O12 I/OD12t O12 I/OD12t FUNCTION Flash ROM interface Address[18:16] General purpose I/O port 5 bit7-5 Flash ROM interface Address[15:10] General purpose I/O port 4 bit7-2 Flash ROM interface Address[9:8] General purpose I/O port 4 bit1-0 Flash ROM interface Address[7:0] General purpose I/O port 3 bit7-0 Flash ROM interface Data Bus[7:4] General purpose I/O port 2 bit7-4 Flash ROM interface Data Bus [3:0] General purpose I/O port 2 bit3-0 Flash ROM interface Chip Select General purpose I/O port 5 bit4 Flash ROM interface Memory Read Enable General purpose I/O port 5 bit3 Flash ROM interface Memory Write Enable General purpose I/O port 5 bit2
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1.7 General Purpose I/O Port
SYMBOL GP73 GP80 WDTO GP67 GP66 GP65 GP64 GP63 GP62 GP61 GP60 99 100 101 102 103 104 105 106 PIN 111 118 I/O I/OD12t I/OD12t O12 I/OD12t I/OD12t I/OD12t I/OD12t I/OD12t I/OD12t I/OD12t I/OD12t FUNCTION General purpose I/O port 7 bit3 General purpose I/O port 8 bit0 Watch dog timer output. General purpose I/O port 6 bit7. General purpose I/O port 6 bit6. General purpose I/O port 6 bit5. General purpose I/O port 6 bit4. General purpose I/O port 6 bit3. General purpose I/O port 6 bit2. General purpose I/O port 6 bit1. General purpose I/O port 6 bit0.
1.8 Smart Card Interface
SYMBOL SCPSNT GP77 SCIO GP76 SCCLK GP75 SCRST GP74 SCC8 GP72 SCPWR GP71 SCC4 GP70 108 109 110 112 113 114 PIN 107 I/O INts I/OD24t I/O24t I/OD24t O4 I/OD4t O24 I/OD24t I/O24t I/OD24t O12 I/OD12t I/O24t I/OD24t FUNCTION Smart card present detection Schmitt-trigger input. General purpose I/O port 7 bit7. Smart card data I/O channel. General purpose I/O port 7 bit6. Smart card clock output. General purpose I/O port 7 bit5. Smart card reset output. General purpose I/O port 7 bit4. Smart card General Purpose I/O channel. General purpose I/O port 7 bit2. Smart card power control. General purpose I/O port 7 bit1. Smart card General Purpose I/O channel. General purpose I/O port 7 bit0.
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1.9 PWM & General Purpose I/O Port 8
SYMBOL PWM2 PLED GP83 PWM1-0 GP82-81 116117 PIN 115 I/O O12 O12 I/OD12t O12 I/OD12t FUNCTION Fan speed control . Use the Pulse Width Modulation (PWM) Power LED output, this signal is low after system reset. General purpose I/O port 8 bit2-1 Fan speed control . Use the Pulse Width Modulation (PWM) Techno knowledge to control the Fan's RPM. General purpose I/O port 8 bit2-1
1.10 Game Port & MIDI Port
SYMBOL MSI GP51 MSO GP50 GPAS2 GP17 GPBS2 GP16 GPAY GP15 GPBY GP14 124 123 122 120 121 PIN 119 I/O INcu I/OD24c O12 I/OD12t INcs I/OD24cs INcs I/OD24cs I/OD24a I/OD24cs I/OD24a I/OD24cs MIDI serial data input . General purpose I/O port 5 bit 1. MIDI serial data output. General purpose I/O port 5 bit 0. Active-low, Joystick I switch input 2. This pin has an internal pull-up resistor. (Default) General purpose I/O port 1 bit 7. Active-low, Joystick II switch input 2. This pin has an internal pull-up resistor. (Default) General purpose I/O port 1 bit 6. Joystick I timer pin. this pin connect to Y positioning variable resistors for the Joystick. (Default) General purpose I/O port 1 bit 5. Joystick II timer pin. this pin connect to Y positioning variable resistors for the Joystick. (Default) General purpose I/O port 1 bit 4. FUNCTION
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1.10 Game Port & MIDI Port, continued
SYMBOL GPBX GP13 GPAX GP12 GPBS1 GP11 GPAS1 GP10
PIN 125
I/O I/OD24a I/OD24cs
FUNCTION Joystick II timer pin. this pin connect to X positioning variable resistors for the Joystick. (Default) General purpose I/O port 1 bit 3. Joystick I timer pin. This pin connect to X positioning variable resistors for the Joystick. (Default) General purpose I/O port 1 bit 2. Active-low, Joystick II switch input 1. This pin has an internal pull-up resistor. (Default) General purpose I/O port 1 bit 1. Active-low, Joystick I switch input 1. This pin has an internal pull-up resistor. (Default) General purpose I/O port 1 bit 0.
126
I/OD24a I/OD24cs
127
Incs I/OD24cs
128
Incs I/OD24cs
1.11 POWER PINS
SYMBOL VCC VCC3V GND PIN 5, 45, 75, 22 18, 60, 90, FUNCTION +5V power supply for the digital circuitry. +3.3V power supply for driving 3V on host interface. Ground.
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2. SMART CARD READER INTERFACE (SCR)
2.1 Features
Winbond's implementation of Smart Card Reader interface is based on ISO/IEC 7816-3 standard and fully compliant with PC/SC Specifications 1.0. Except for pins specified in ISO/IEC 7816-3, W83697SF's SCI also includes SCPSNT (Smart Card Present) monitoring status of card insertion/extraction, SCLED (Smart Card traffic LED display) which is active high when host is accessing information to/from card, and two general-purpose I/O pins SCC4 and SCC8 (only available in W83697SF) for users to design application-specific functions. Register file (control and status registers) of Winbond's Smart Card interface is designed in an UART-like structure so that users with previous UART experience should have no trouble to implement Winbond's SCI applications. Power consumption is minimized by sophisticated device's operation scheme.
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2.2 Register file
Complete register file table Bit Number
Register file Base + 0 BDLAB = 0 Base + 0 BDLAB = 0 Base + 1 BDLAB = 0 Base + 2 BDLAB = 0 Base + 2 BDLAB = 0 Receiver Buffer Register (Read only) Transmitter Buffer Register (Write only) Interrupt Enable Register default Interrupt Status Register (Read only) Smart Card FIFO control Register (Write only) default Register default Base + 4 Clock Base Register default Base + 5 Smart Card Status SCSR Register (Read only) Base + 6 Guard Time Register default Base + 7 Extended Control Register default Base + 0 BDLAB = 1 Base + 1 BDLAB = 1 Baud rate divisor Latch Lower byte default Baud rate divisor Latch Higher byte default BLH BLL ECR GTR CBR ISR IER SCC8 x FIFO enabled RxTL1 (note) 0 (note) 0 Bit 7 0 RxFEI (note) Bit 7 0 Cold reset 0 Bit 7 0 Bit 15 0 x Bit 6 0 TSRE (note) Bit 6 0 x Bit 5 0 TBRE (note) Bit 5 0 (note) x Bit 6 0 Bit 14 0 0 Bit 5 0 Bit 13 0 SCC4 x FIFO enabled RxTL0 (note) 0 x x EPE (note) 0 Bit 4 0 SBD (note) Bit 4 0 (note) 1 Bit 4 1 Bit 12 0 x PBE (note) 0 Bit 3 1 NSER (note) Bit 3 0 (note) 0 Bit 3 1 Bit 11 0 x Bit 2 1 PBER (note) Bit 2 0 CLKSTP (note) 0 Bit 2 1 Bit 10 0 x Bit 1 0 OER (note) Bit 1 0 SCIODIR (note) 1 Bit 1 1 Bit 9 0 0 Bit 0 0 RDR (note) Bit 0 1 Warm reset 0 Bit 0 1 Bit 8 0 SCC8_IO SCC4_IO (note) 0 SCPSNT (note) 0 SCPTI (note) ESCPTI (note) 0 INTS2 (note) ESCSRI (note) 0 INTS1 (note) ETBREI (note) 0 INTS0 (note) RxFRST (note) 0 ERDRI (note) 0 Interrupt pending Enable FIFO 0 TBR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Abbr. RBR 7 Bit 7 6 Bit 6 5 Bit 5 4 Bit 4 3 Bit 3 2 Bit 2 1 Bit 1 0 Bit 0
SCFR
Reserved Reserved Reserved TxFRST (note) 0
Base + 3 Smart Card Control SCCR BDLAB Reserved Reserved
Reserved Reserved SC_SEL
Reserved SCKFS1
SCKFS0 CLKSTPL
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Base + 2
Smart Card ID BDLAB = number (Read only) 1
0
1
1
1
0
0
0
0
Note: Abbreviation explanation (in alphabetical order) - BDLAB - Baud rate divisor latch access bit. CLKSTP - Stop Smart Card interface's clock SCCLK. CLKSTPL - Set SCCLK level when CLKSTP is "1". EPE - Even parity enable. ERDRI - Enable RBR (Receiver Buffer Register) data ready interrupt. ESCPTI - Enable SCPSNT interrupt. ESCSRI - Enable interrupts of SCSR (read only Smart Card Status Register at base address + 5) events. ETBREI - Enable TBR (write only Transmitter Buffer Register at base address + 0) empty interrupt. INTS2 ~ INTS0 - Interrupt status bits. Refer to description of ISR (read only Interrupt Status Register at base address + 2) for details. NSER - No stop bit error. OER - Overrun error. PBE - Parity bit enable. PBER - Parity bit error. RDR - Receiver data ready status. RxFEI - Receiver FIFO error indication. RxFRST - Receiver FIFO reset. RxTL1 ~ RxTL0 - Receiver threshold level setting bits. Refer to description of SCFR (write only Smart Card FIFO control register at base address + 2) for details. SBD - Silent byte detected. SCIODIR - SCIO direction bit (0/1 mean output/input respectively). SCKFS1 ~ SCKFS0 - Smart Card interface clock frequency selection bits. Refer to description of ECR (Extended Control Register at base address + 7) for details. SCPTI - SCPSNT toggle interrupt status. SC_SEL - Smart Card socket selection.
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TBRE - TBR (write only Transmitter Buffer Register at base address + 0) empty status. TSRE - TSR (Transmitter shift register) empty status. TxFRST - Transmitter FIFO reset.
Receiver Buffer Register (RBR at base address + 0 when BDLAB = 0, read only) This register is the access port for receiver FIFO. It is active when Smart Card interface is in input mode with SCIODIR (bit 1 of ECR at base address + 7) set to "1". The depth of receiver FIFO is 16 bytes.
7 6 5 4 3 2 1 0 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
Bit 7 ~ bit 0: Access port for receiver FIFO. Receiver Buffer Register (RBR at base address + 0 when BDLAB = 0, read only) This register is the access port for transmitter FIFO. It is active when Smart Card interface is in output mode with SCIODIR (bit 1 of ECR at base address + 7) set to "0". The depth of transmitter FIFO is 16 bytes.
7 6 5 4 3 2 1 0 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
Bit 7 ~ bit 0: Access port for receiver FIFO.
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Interrupt Enable Register (IER at base address + 1 when BDLAB = 0) This register includes four control bits to enable interrupt events. The other four bits are allocated for control of general-purpose I/O pins which are usually connected to C4 and C8 pads of a smart card for application specific function.
7 6 5 4 3 2 1 0 ERDRI ETBREI ESCSRI ESCPTI SCC4_IO SCC8_IO SCC4 SCC8
Bit 7: SCC8 means Smart Card C8 pad. When SCC8_IO (bit 5) is set to "0" for output mode, this bit controls the voltage level of SCC8 pin which is high when SCC8 is set to "1" and low for setting of "0". Its value reflects what could be observed on SCC8 pin when SCC8_IO is set to "1" for input mode with the same convention as in output mode. Bit 6: SCC4 means Smart Card C4 pad. When SCC4_IO (bit 4) is set to "0" for output mode, this bit controls the voltage level of SCC4 pin which is high when SCC4 is set to "1" and low for setting of "0". Its value reflects what is observed on SCC4 pin when SCC4_IO is set to "1" for input mode with the same convention as in output mode. Bit 5: SCC8_IO means input/output direction control for SCC8 pin. =0 =1 SCC8 is in output mode. SCC8 is in input mode.
Bit 4: SCC4_IO means input/output direction control for SCC4 pin. =0 =1 SCC4 is in output mode. SCC4 is in input mode.
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Bit 3: ESCPTI means SCPSNT toggle interrupt enable bit. triggers an interrupt if this bit is set to "1". =0 =1 SCPSNT toggle interrupt is disabled. SCPSNT toggle interrupt is enabled.
A rising/falling edge of SCPSNT signal
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Bit 2: ESCSRI means interrupt enable bit for SCSR-related events such as silent byte detected error, no stop bit error, parity bit error or overrun e rror. Any SCSR-related event as described above will trigger an interrupt if this bit is set to "1". =0 =1 SCSR-related event interrupt is disabled. SCSR-related event interrupt is enabled.
Bit 1: ETBREI means interrupt enable bit for TBR (Transmitter Buffer Register) empty condition. An interrupt is issued when TBR is empty and this bit is set to "1". It is used in output mode (SDIODIR = 0) to request host's attention to transfer data byte to card. =0 =1 TBR empty interrupt is disabled. TBR empty interrupt is enabled.
Bit 0: ERDRI means interrupt enable bit for receiver data ready status. The active FIFO threshold level for this kind of interrupt when FIFO is enabled is specified in RxTL1 and RxTL0 (bit 7 and bit 6 of SCFR at base address + 2. Refer to description of SCFR for details). An interrupt is issued if a data byte is ready for host to read when FIFO is disabled or incoming data from card reaches active FIFO threshold level when FIFO is enabled. = 0 Receiver data ready interrupt is disabled. = 1 Receiver data ready interrupt is enabled. Interrupt Status Register (ISR at base address + 2 when BDLAB = 0, read only) This register contains mainly interrupt status including transmission-related interrupts and SCPSNT toggle interrupt. Transmission-related interrupt status is coded and prioritized as in UART implementation. User may also find FIFO enable/disabled status reflecting what is set in bit 0 of SCFR (write only Smart Card FIFO Register at base address + 2 when BDLAB = 0) and SCPSNT line status.
7
6
5
4
3
2
1
0 Interrupt pending INTS0 INTS1 INTS2 SCPTI SCPSNT FIFO enabled FIFO enabled
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Bit 7, 6: FIFO enabled status bits reflect what is set in bit 0 of SCFR (write only Smart Card FIFO Register at base address + 2 when BDLAB = 0). Bit 5: SCPSNT line status. User may poll this bit to see SCPSNT pin's voltage level. Bit 4: SCPTI means SCPSNT toggle interrupt status. A rising/falling edge of SCPSNT signal triggers an interrupt and set this status bit if ESCPTI (IER bit 3) is set to "1" to enable SCPSNT toggle interrupt. =0 =1 No SCPSNT toggle interrupt. SCPSNT toggle interrupt occurs.
Bit 3 ~ 1: INTS2 ~ INTS0 mean interrupt status bit 2 ~ 0. The combination indicates which kind of transmission-related interrupt has occurred. Refer to the following table for details.
ISR bit 3 0 0 2 0 1 1 0 1 0 1 0 Priority first Interrupt type Data receiving status
Interrupt set and function Interrupt source No interrupt pending 1. OER = 1 2. PBER = 1 3. NSER = 1 4. SBD = 1 Read SCSR Clear interrupt condition -
0
1
0
0
second RBR data ready
1. RBR data ready 2. FIFO interrupt active level reached
1. Read RBR 2. Read RBR until FIFO is under active level
1
1
0
0
second FIFO data time out
Data present in Rx FIFO Read RBR for 4-character period of time since last access of Rx FIFO. TBR empty 1. Write data to TBR 2. Read ISR (if priority is third)
0
0
1
0
third
TBR empty
Bit 0: Interrupt pending status bit. This bit is a logical "1" if there is no interrupt pending. If one of the interrupt sources occurs, this bit will be set to a logical "0". =0 =1 Interrupt pending. No interrupt occurs.
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Smart Card FIFO control Register (SCFR at base address + 2 when BDLAB = 0, write only) This register controls FIFO function of Smart Card interface.
7 6 5 4 3 2 1 0 Enable FIFO RxFRST TxFRST Reserved Reserved Reserved RxTL0 RxTL1
Bit 7, 6: RxTL1 and RxTL0 mean receiver FIFO active threshold level control bits. These two bits are used to set the active level for the receiver FIFO interrupt. For example, if the interrupt active level is set as 4 bytes, once there are at least 4 data characters in the receiver FIFO, an interrupt is activated to notify host to read data from FIFO. Default to be 00b.
RxTL1 0 0 1 1 Bit 5 ~ 3: Reserved.
RxTL0 0 1 0 1
Rx FIFO Interrupt Active Level (Bytes) 01 04 08 14
Bit 2: TxFRST means transmitter FIFO reset control bit. Setting this bit to a logical "1" resets the transmitter FIFO counter to initial state. This bit is self-cleared to "0" after being set to "1". Default is "0". Bit 1: RxFRST means receiver FIFO reset control bit. Setting this bit to a logical "1" resets the receiver FIFO counter to initial state. This bit is self-cleared to "0" after being set to "1". Default is "0". Bit 0: This bit enables FIFO of Smart Card interface. It should be set to a logical "1" before other bits of SCFR are programmed. Default is "0".
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Smart Card Control Register (SCCR at base address + 3) In contrast to its UART counterpart, Smart Card Control Register only controls parity bit setting because data length is fixed at 8-bit long for Smart Card interface protocol.
7 6 5 4 3 2 1 0 Reserved Reserved Reserved PBE EPE Reserved Reserved BDLAB
Bit 7: BDLAB means baud rate divisor latch access bit. When this bit is set to a logical "1", users may access baud rate divisor (in 16-bit binary format) through divisor latches (BLH and BLL) of baudrate generator during a read/write operation. A special Smart Card ID can also be read at base address + 2 when BDLAB is "1". When this bit is set to "0", accesses to base address + 0, 1 or 2 refer to RBR/TBR, IER or ISR/SCFR respectively. Bit 6 ~ 5: Reserved. Bit 4: EPE means even parity enable. This bit is only available when bit 3 of SCCR is programmed to "1". It prescribes number of logical 1s in a data word including parity bit. When this bit is set to "1", even parity is required for transmission and reception. Odd parity is demanded when this bit is set to "0". Bit 3: PBE means parity bit enable. When this bit is set, a parity bit is inserted between last data bit and stop bit for transmission integrity check. Bit 2 ~ 0: Reserved.
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Clock Base Register (CBR at base address + 4, default 0Ch) This register combining with BLH and BLL (baud rate latches) determine internal sampling clock frequency. For example, CBR defaults to be 0Ch and BLH, BLL default to be 1Fh which mean SCCLK clock frequency is 372 (12 x 31) times of internal sampling clock frequency. The default values of CBR, BLH and BLL are corresponding to default values of transmission factors F and D specified in ISO/IEC 7816-3. The value of 0Ch of CBR means there're 12 sampling clock pulses to detect a 1-etu (elementary time unit) data bit on SCIO signal. It is recommended that user sets CBR to be around 16 to maintain better data integrity and transmission stability.
7 6 5 4 3 2 1 0 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
Bit 7 ~ 0: Clock base value. It specifies number of internal sampling clock pulses for a data bit. Default to be 0Ch. Smart Card Status Register (SCSR at base address + 5) This 8-bit register provides information about status of data transfer during communication.
7 6 5 4 3 2 1 0 RDR OER PBER NSER SBD TBRE TSRE RxFEI
Bit 7: RxFEI means receiver FIFO error indication. This bit is set to "1" when there is at least one parity bit error, no stop bit error or silent byte detected error in receiver FIFO. It is cleared by reading from SCSR if there is no remaining error left in receiver FIFO. Bit 6: TSRE means transmitter shift register empty. This bit is set to "1" when transmitter shift register is empty.
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Bit 5: TBRE means transmitter buffer register empty. In non-FIFO mode, this bit will be set to a logical 1 when a data byte is transferred from TBR to TSR. If ETBREI of IER is a logical 1, an interrupt is generated to notify host to write the following data bytes. In FIFO mode, this bit is set to "1" when the transmitter FIFO is empty. It is cleared to "0" when host writes data bytes into TBR or FIFO. Bit 4: SBD means silent byte detected. This bit is set to "1" to indicate that received data byte are kept in silent state for a full byte time, including start bit, data bits, parity bit, and stop bits. In FIFO mode, it indicates the same condition for the data on top of FIFO. When host reads SCSR, it clears this bit to "0". Bit 3: NSER means no stop bit error. This bit is set to "1" to indicate that received data has no stop bit. In FIFO mode, it indicates the same condition for the data on top of FIFO. When host reads SCSR, it clears this bit to "0". Bit 2: PBER means parity bit error. This bit is set to "1" to indicate that parity bit of received data is wrong. In FIFO mode, it indicates the same condition for the data on top of the FIFO. When host reads SCSR, it clears this bit to "0". Bit 1: OER means overrun error. This bit is set to "1" to indicate previously received data is overwritten by the next received data before it is read by host. In FIFO mode, it indicates the same condition instead of FIFO full. When host reads SCSR, it clears this bit to "0". Bit 0: RDR means receiver data ready. This bit is set to "1" to indicate received data is ready to be read by host in RBR or FIFO. If no data are left in RBR or FIFO, the bit is cleared to "0". Guard Time Register (GTR at base address + 6, default 01h) This register specifies number of stop bits appended in the end of data byte.
7 6 5 4 3 2 1 0 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
Bit 7 ~ 0: Guard time values. Default to be 01h.
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Extended Control Register (ECR at base address + 7, default 12h) This register contains reset control bits, clock frequency selection bits, clock stop control bits and SCIO direction control bit.
7 6 5 4 3 2 1 0 Warm reset SCIODIR CLKSTP CLKSTPL SCKFS0 SCKFS1 Reserved Cold reset
Bit 7: Cold reset. Setting "1" to this bit turns off power to Smart Card interface by pulling up SCPWR#. SCCLK is stopped, SCRST# kept low, SCIO in input mode and SCLED is inactive. ECR's SCIODIR, SCKFS1 and SCKFS0 control bits and control bits in CBR, GTR, BLH and BLL are cleared to default values. User must write a "0" to this bit to recover to normal state. Bit 6: Reserved. Bit 5, 4: SCKFS1 and SCKFS0 means SCCLK frequency selection bit 1 and 0. They selects working clock frequency as following table. Default values are 01h.
SCKFS1, SCKFS0 00 01 10 11
SCCLK frequency 1.5 MHz 3.0 MHz 6.0 MHz 12 MHz
Bit 3: CLKSTP means clock stop control bit. Setting "1" to this bit stops SCCLK at a voltage level specified by CLKSTPL (bit 2 of ECR). Bit 2: CLKSTPL means clock stop voltage level. Publication Release Date: Dec 2002 Revision 1.0
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W83697SF
=0 =1
SCCLK stops at low if CLKSTP is also set to "1". SCCLK stops at high if CLKSTP is also set to "1".
Bit 1: SDIODIR means SDIO direction. =0 =1 SDIO is in output mode. SDIO is in input mode.
Bit 0: Warm reset. Setting "1" to this bit pulls down SCRST#. SCCLK is stopped, SCIO in input mode and SCLED is inactive. ECR's SCIODIR, SCKFS1 and SCKFS0 control bits and control bits in CBR, GTR, BLH and BLL are cleared to default values. User must write a "0" to this bit to recover to normal state. This bit is similar to cold reset except SCPWR# stays active low. Baud rate divisor Latch Lower byte (BLL at base address + 0 when BDLAB = 1, default 1Fh) This register combining with BLH and CBR determine internal sampling clock frequency.
7 6 5 4 3 2 1 0 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
Bit 7 ~ 0: Baud rate divisor latch lower byte values. Default to be 1Fh.
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Baud rate divisor Latch Higher byte (BLH at base address + 1 when BDLAB = 1, default 00h) This register combining with BLL and CBR determine internal sampling clock frequency.
7 6 5 4 3 2 1 0 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
Bit 7 ~ 0: Baud rate divisor latch higher byte values. Default to be 00h.
2.3 Smart Card ID number (base address + 2 when BDLAB = 1, fixed at 70h)
This register contains a specific value of 70h for driver to identify Smart Card interface.
2.4 Functional description
The following description uses abbreviations to refer to control/status registers and their contents of Smart Card interface. Also, PnP resources of Smart Card interface are assumed to have been programmed and allocated appropriately by system BIOS.
2.5 Initialization
User needs to program control registers so that ATR (Answer To Reset) data streams can be properly decoded after card insertion. Initialization settings include the following steps where sequential order is irrelevant. 1. BLH, BLL and CBR are written with 00h, 1Fh and 0Ch respectively to comply with default transmission factors Fd and Dd which are 372 and 1 as specified in ISO/IEC 7816-3. 2. GTR is programmed with 01h for one stop bit. 3. Set SCFR bit 1 to "1" to enable FIFO. 4. PBE needs to be "1" for parity bit enable but EPE is optional. 5. Set SDIODIR to "1" to put SDIO in reception mode. 6. Set SCKFS1 and SCKFS0 to "01" to select 3 MHz for SCCLK.
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Most default values of above control bits are designed as specified in initialization step but it is recommended that user performs all the initialization sequence to avoid any ambiguity. The relationship between transmission factors and settings of BLH, BLL and CBR is best described in the following example. 1etu = Therefore, Fd 372 = = (BLH , BLL ) x CBR = 31 x 12 Dd 1 F1 x (f means SCCLK frequency) Df
2.6 Activation
Card insertion pulls up SCPSNT (assuming SCPSNT is active high with CRF0 bit 0 SCPSNT_POL = 0) and in consequence SCPWR# is pulled down to activate power MOS to supply power to card slot after a delay of about 5 ms. This delay is for card slot mechanism to settle down before power is actually applied. SCCLK starts to output clocks right after SCPWR# is active while SCIO is in reception mode and pulled up externally. SCRST# keeps low initially to reset card but will output high after 512 clock cycles to meet requirement of tb of more than 400 clock cycles (specified in ISO/IEC 7816-3). To meet another timing requirement, tc of ISO/IEC 7816-3, a counter based on SCCLK is implemented to start counting on the rising edge of SCRST#. SCPWR# is deactivated if no ATR (Answer To Reset) is detected after 65536 clock cycles from the rising edge of SCRST#.
2.7 Answer-to-Reset
Answer-to-Reset (ATR) is the data streams sent by the card to the interface as an answer to a reset on SCRST# signal. Refer to ISO/IEC 7816-3 for detailed description of ATR. There're two kind of cards specified in ISO/IEC 7816-3, inverse convention card and direct convention card. Although these two conventions treat logical meanings (0 or 1) of voltage levels (low or high) differently, Winbond's implementation of Smart Card interface decodes a high voltage level data bit as "1" and low voltage level data bit "0" nevertheless and resorts to software t interpret incoming data. o Software driver needs to interpret initial character of ATR first to determine which convention is for inserted card and chooses a conversion procedure for it. Subsequent incoming data bytes must be passed through a conversion procedure before actually transfers these data bytes to host. Similar conversion procedure must be applied to outgoing data byte before writing to TBR too. For example, the raw data byte for initial character of inverse-convention ATR would be 03h. Software driver therefore needs a conversion procedure to reverse bit-significance and polarity to process subsequent raw data bytes. On the other hand, initial character of direct-convention ATR is 3Bh which needs no conversion procedure to process data byte.
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2.8 Data transfer
Software driver might need to configure control registers again based on information contained in ATR before process subsequent data transfer. The following guidelines are provided for programming reference. 1. 2. 3. 4. 5. 6. EPE should be set to "1" for direct-convention card and otherwise for inverse-convention card. BLH, BLL and CBR should be set to comply with Fi and Di. GTR is used for various stop bit requirement of different transmission protocols. SCIODIR controls direction of data transfer. Use interrupt resources to control communication sequence. Monitor SCSR for transmission integrity.
2.9 Cold reset and warm reset
Cold reset is achieved by writing a "1" to bit 7 of ECR. It deactivates SCPWR# to high. Consequentially, SCRST# is pulled down and SCCLK is stopped. User must write a "0" to ECR bit 7 to resume Smart Card interface to a normal activation state as described in section 2.3 assuming card is still present. Writing a "1" to ECR bit 0 triggers a warm reset. This is a self-cleared reset operation unlike cold reset which needs explicit cancellation. Its effect is similar to cold reset except SCPWR# is kept activated and therefore power supply to card stays on.
2.10 Power states
W83697SF employs a sophisticated algorithm to partition Smart Card interface's internal circuits to achieve optimal power utilization. However, users must pay extra care in the design of application circuits following guidelines stated below to prevent potential signal conflict and unnecessary power consumption. There're four power states: disabled state, active state, idle state and power down state. Disabled state is the default state when power is first applied to the IC. Active state is entered by setting a "1" to enable bits at bit 0 of CR30 in logical device 0 (refer to Configuration Register section for details). Idle state means that I/O pins of deselected socket output a predetermined voltage level to disable power to socket and to prevent leakage from floating connections while Smart Card interface core circuits might still be servicing other selected socket. SCPWD (Smart Card Power Down, bit 7 of CR22 global control register) controls whether in active state (SCPWD = 0) or in power down state (SCPWD = 1).
2.11 Disabled state
Smart Card interface is in disabled state initially. Clock is stopped in this state and therefore it is the least power-consuming state. To prevent current leakage from floating connections, it is designed to output a predetermined voltage level on all the I/O pins of Smart Card interface as follows: SCPWR# outputs high to disable power supply to socket; SCRST#, SCCLK, SCIO, SCC4, SCC8 and SCLED output low; SCPSNT is tri-stated.
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These I/O conditions also apply to both socket A and socket B in power down state (SCPWD = 1) or deselected socket in idle state. Designers of application circuits must take extra care so that no contention occurs when Smart Card interface is in those power-saving states. Please refer to Winbond's recommended application circuit for example.
2.12 Active state
Active state is when Smart Card interface is actually performing all its functions: configuration of control and interrupt registers, detection of card insertion/extraction, reception of ATR (Answer To Reset) packet and communication of information between host and card. Refer to section 2.3 for detailed function description. Smart Card interface enters active state by setting a "1" to bit 0 of CR30 in logical device 0. This is the most power-consuming state and actual power consumption is dependent on traffic of interface.
2.13 Idle state
W83697SF supports up to two Smart Card sockets. Only one socket could be active at a time and the other deselected socket is considered to be in idle state. Selection of active socket is controlled through socket selection bits which are bits 0 at base address + 3. I/O pins of deselected socket also output a predetermined voltage level as described in section 2.4.1. Power consumption in this state is similar to active state because one of the two sockets is selected and core circuit is still functioning. There is no idle state for W83697SF because only one Smart Card socket is supported and it is always selected.
2.14 Power down state
Transition from active state to power down state is accomplished by setting SCPWD to "1". Clock is stopped for most internal core circuits except detection circuit for SCPSNT toggle (card insertion/extraction). SCPWD could be reset by SCPSNT toggle and through this feature Smart Card interface in power down state can be waken up by card insertion/extraction. User may also directly write a "0" to SCPWD to wake up Smart Card interface. Smart Card interface spends a little bit more power to maintain SCPSNT toggle detection circuit in power down state than in disabled state while spares even more power than in active state by stopping clock to core circuit. Users must make sure that all on-going transactions are concluded before putting Smart Card interface into power down state to prevent potential miss-operation of internal state machine.
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3. CONFIGURATION REGISTER
3.1 Plug and Play Configuration
The W83697SF uses Compatible PNP protocol to access configuration registers for setting up different types of configurations. In W83697SF, there are eleven Logical Devices (from Logical Device 0 to Logical Device B with the exception of logical device 4 for backward compatibility) which correspond to eleven individual functions: FDC (logical device 0), PRT (logical device 1), UART1 (logical device 2), UART2 (logical device 3), CIR (Consumer IR, logical device 6), GPIO1 (logical device 7), GPIO5(logical device 8),GPIO2 ~GPIO4(logical device 9), ACPI ((logical device A), and Hardware monitor (logical device B). Each Logical Device has its own configuration registers (above C R30). Host can access those registers by writing an appropriate logical device number into logical device select register at CR7. 7 x 5 x 4 x 3 x 1 0
6 x
2 x
DRATE0 DRATE1
3.2 Compatible PnP
3.2.1 Extended Function Registers In Compatible PnP, there are two ways to enter Extended Function and read or write the configuration registers. HEFRAS (CR26 bit 6) can be used to select one out of these two methods of entering the Extended Function mode as follows: HEFRAS 0 1 address and value write 87h to the location 2Eh twice write 87h to the location 4Eh twice
After Power-on reset, the value on RTSA# (pin 49) is latched by HEFRAS of CR26. In Compatible PnP, a specific value (87h) must be written twice to the Extended Functions Enable Register (I/O port address 2Eh or 4Eh). Secondly, an index value (02h, 07h-FFh) must be written to the Extended Functions Index Register (I/O port address 2Eh or 4Eh same as Extended Functions Enable Register) to identify which configuration register is to be accessed. The designer can then access the desired configuration register through the Extended Functions Data Register (I/O port address 2Fh or 4Fh). After programming of the configuration register is finished, an additional value (AAh) should be written to EFERs to exit the Extended Function mode to prevent unintentional access to those configuration
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registers. The designer can also set bit 5 of CR26 (LOCKREG) to high to protect the configuration registers against accidental accesses. The configuration registers can be reset to their default or hardware settings only by a cold reset (pin MR = 1). A warm reset will not affect the configuration registers. 3.2.2 Extended Functions Enable Registers (EFERs) After a power-on reset, the W83697SF enters the default operating mode. Before the W83697SF enters the extended function mode, a specific value must be programmed into the Extended Function Enable Register (EFER) so that the extended function register can be accessed. The Extended Function Enable Registers are write-only registers. On a PC/AT system, their port addresses are 2Eh or 4Eh (as described in previous section). 3.2.3 Extended Function Index Registers (EFIRs), Extended Function Data Registers(EFDRs) After the extended function mode is entered, the Extended Function Index Register (EFIR) must be loaded with an index value (02h, 07h-FEh) to access Configuration Register 0 (CR0), Configuration Register 7 (CR07) to Configuration Register FE (CRFE), and so forth through the Extended Function Data Register (EFDR). The EFIRs are write-only registers with port address 2Eh or 4Eh on PC/AT systems; the EFDRs are read/write registers with port address 2Fh or 4Fh on PC/AT systems.
3.3 Configuration Sequence
To program W83697SF configuration registers, the following configuration sequence must be followed: (1). Enter the extended function mode (2). Configure the configuration registers (3). Exit the extended function mode
3.3.1 Enter the extended function mode To place the chip into the extended function mode, two successive wrtites of 0x87 must be applied to Extended Function Enable Registers(EFERs, i.e. 2Eh or 4Eh). 3.3.2 Configurate the configuration registers The chip selects the logical device and activates the desired logical devices through Extended Function Index Register(EFIR) and Extended Function Data Register(EFDR). EFIR is located at the same address as EFER, and EFDR is located at address (EFIR+1). First, write the Logical Device Number (i.e.,0x07) to the EFIR and then write the number of the desired logical device to the EFDR. If accessing the Chip(Global) Control Registers, this step is not required. Secondly, write the address of the desired configuration register within the logical device to the EFIR and then write (or read) the desired configuration register through EFDR.
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3.3.3 Exit the extended function mode To exit the extended function mode, one write of 0xAA to EFER is required. Once the chip exits the extended function mode, it is in the normal running mode and is ready to enter the configuration mode. 3.3.4 Software programming example The following example is written in Intel 8086 assembly language. It assumes that the EFER is located at 2Eh, so EFIR is located at 2Eh and EFDR is located at 2Fh. If HEFRAS (CR26 bit 6) is set, 4Eh can be directly replaced by 4Eh and 2Fh replaced by 4Fh. ;----------------------------------------------------------------------------------; Enter the extended function mode ,interruptible double-write ;----------------------------------------------------------------------------------MOV OUT OUT DX,2EH DX,AL DX,AL MOV AL,87H |
;----------------------------------------------------------------------------; Configurate logical device 1, configuration register CRF0 | ;----------------------------------------------------------------------------MOV MOV OUT MOV MOV OUT ; MOV MOV OUT MOV OUT DX,2EH AL,F0H DX,AL DX,2FH DX,AL ; update CRF0 with value 3CH | ; select CRF0 DX,2EH AL,07H DX,AL DX,2FH AL,01H DX,AL ; select logical device 1 ; point to Logical Device Number Reg.
MOV AL,3CH ;-----------------------------------------; Exit extended function mode ;-----------------------------------------MOV OUT DX,2EH DX,AL Publication Release Date: Dec 2002 Revision 1.0 MOV AL,AAH
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3.4 Chip (Global) Control Register
CR02 (Default 0x00) (Write only) Bit [7:1]: Bit 0 CR07 Bit [7:0]: LDNB7 - LDNB0 --> Logical Device Number Bit 7 - 0 CR20 (read only) Bit [7:0]: DEVIDB7 - DEBIDB0 --> Device ID Bit 7 - Bit 0 = 0x 68 (for W83697SF) Reserved. = 1 SWRST --> Soft Reset.
CR21 (read only) Bit [7:0]: DEVREVB7 - DEBREVB0 --> Device Rev = 0x0X (for W83697SF) X : Version change number. (Bit [3:0]) --> begin from 1
CR22 (Default 0xef) Bit 7: SCPWD 0 1 Bit 6: Bit 5: Bit 4: Bit 3: Power down No Power down
Reserved Reserved Reserved URBPWD 0 1 Power down No Power down Power down Publication Release Date: Dec 2002 Revision 1.0
Bit 2:
URAPWD 0
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1 Bit 1: 0 1 Bit 0: 0 1 CR23 (Default 0xfe)
No Power down Power down No Power down Power down No Power down
PRTPWD
FDCPWD
Bit [7:1]: Reserved. Bit 0: IPD (Immediate Power Down). When set to 1, it will put the whole chip into power down mode immediately. CR24 (Default 0s1000ss) Bit 7: Flash ROM I/F Address Segment (000F0000h ~ 000FFFFFh) enable/disable 0 1 Bit 6: 0 1 Enable Disable The clock input on Pin 1 should be 24 MHz. The clock input on Pin 1 should be 48 MHz. The corresponding power-on setting pin is SOUTB (pin 61). Bit [5:4]: ROM size select 00 01 10 11 Bit 3: 0 1 1M 2M 4M Reserved MEMW# Disable MEMW# Enable
CLKSEL(Enable 48Mhz)
MEMW# Select (PIN97)
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Bit 2:
Flash ROM I/F Address Segment (000E0000h ~ 000EFFFFh) enable/disable 0 1 Enable Disable Flash ROM Interface is enabled after hardware reset Flash ROM Interface is disabled after hardware reset The corresponding power-on setting pin is PENROM#(pin 52)
Bit 1 :
Enable Flash ROM Interface 0 1
Bit 0:
PNPCSV 0 1 The Compatible PnP address select registers have default values. The Compatible PnP address select registers have no default value. The corresponding power-on setting pin is DTRA# (pin 50).
CR25 (Default 0x00) Bit 7: Bit 6: Bit 5: Bit 4: Bit 3: Bit 2: Bit 1: Bit 0: SCTRI Reserved Reserved Reserved URBTRI URATRI PRTTRI FDCTRI
CR26 (Default 0x00) Bit 7: SEL4FDD 0 1 Bit 6: Select two FDD mode. Select four FDD mode.
HEFRAS These two bits define how to enable Configuration mode. The corresponding power-on setting pin is RTSA #(pin 49). HEFRAS Address and Value 0 1 Write 87h to the location 2E twice. Write 87h to the location 4E twice.
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Bit 5:
LOCKREG 0 1 Enable R/W Configuration Registers. Disable R/W Configuration Registers.
Bit 4: Bit 3:
Reserved DSFDLGRQ 0 1 Enable FDC legacy mode on IRQ and DRQ selection, then DO register bit 3 is effective on selecting IRQ Disable FDC legacy mode on IRQ and DRQ selection, then DO register bit 3 is not effective on selecting IRQ Enable PRT legacy mode on IRQ and DRQ selection, then DCR bit 4 is effective on selecting IRQ Disable PRT legacy mode on IRQ and DRQ selection, then DCR bit 4 is not effective on selecting IRQ Enable UART A/C legacy mode IRQ selecting, then HCR bit 3 is effective on selecting IRQ Disable UART A/C legacy mode IRQ selecting, then HCR bit 3 is not effective on selecting IRQ Enable UART B/D legacy mode IRQ selecting, then HCR bit 3 is effective on selecting IRQ Disable UART B/D legacy mode IRQ selecting, then HCR bit 3 is not effective on selecting IRQ
Bit 2:
DSPRLGRQ 0 1
Bit 1:
DSUALGRQ 0 1
Bit 0:
DSUBLGRQ 0 1
CR28 (Default 0x00) Bit [7:4]: Reserved. Bit [3]: Flash ROM I/F Address Segment (FFE80000h ~ FFEFFFFFh) enable/disable 0 1 0xx 100 101 110 Disable Enable Parallel Port Mode Reserved External FDC Mode Reserved
Bit [2:0]: PRTMODS2 - PRTMODS0
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111
External two FDC Mode
CR29 (GPIO1,5(50~51) & Game port & MIDI port Select. Default 0x00 ) Bit 7: Port Select (select Game Port or General Purpose I/O Port 1) 0 1 00 01 10 11 00 01 10 11 Bit 2: Game Port General Purpose I/O Port 1 (pin121~128 select function GP10~GP17) MSI Reserved Reserved GP51 MSO Reserved Reserved GP50
Bit [6:5]: (Pin119)
Bit [4:3]: (Pin 120)
Reserved
Bit [1:0]: Reserved CR2A(GPIO2 ~ 5& Flash ROM Interface Select, default 0xFF if PENROM# = 0 during POR, default 0x00 otherwise) Bit 7: (PIN 86 ~89 & 91 ~94) 0 1 Bit 6: 0 1 Bit 5: 0 1 GPIO 2 Flash IF (xD7 ~ XD0) GPIO 3 Flash IF (XA7 ~ XA0) GPIO 4 Flash IF (XA15 ~ XA10 & XA9 ~ A8)
(PIN 78 ~ 85)
(PIN 69 ~ 74 & 76 ~77)
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Bit 4:
(PIN 66 ~ 68 & 95 ~ 97) 0 1 GPIO 5(GP52 ~ 57) Flash IF(XA18 ~ XA16 , ROMCS#, MEMR #, MEMW#)
Bit [3:0]: Reserved CR2B(PWM & GPIO8, GPIO6 Select) Default 0x03 Bit [7]: Reserved. 00 01 10 11 Bit [4]: 0 1 Bit [3]: 0 1 Bit [2]: 0 1 Bit [1]: 0 1 Bit [0]: 0 1 PWM2 PLED Reserved GP83 PWM1 GP82 PWM0 GP81 WDTO GP80 Reserved GPIO6(GP67, GP66, GP65, GP64, GP61, GP60) Reserved GPIO6(GP63, GP62) Bit [6:5]: (Pin115)
(Pin116)
(Pin117)
(Pin118)
(Pin99, Pin100, Pin101, Pin102, Pin105, Pin106)
(Pin103, Pin104)
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CR2C(SC & GPIO7 Select) Default 0x30 Bit [7:6]: (Pin107, Pin108, Pin109, Pin110, Pin113) 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 SC(SCPSNT, SCIO,SCCLK, SCRST, SCPWR) Reserved Reserved GPIO7(GP77, GP76, GP75, GP74, GP71) Reserved Reserved Reserved GP73 SCC8 Reserved Reserved GP72 SCC4 Reserved Reserved GP70
Bit [5:4]: (Pin111)
Bit [3:2]: (Pin112)
Bit [1:0]: (Pin114)
3.5 Logical Device 0 (FDC)
CR30 (Default 0x01 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit [7:1]: Reserved. Bit 0: 1 0 Activates the logical device. Logical device is inactive.
CR60, CR61 (Default 0x03, 0xf0 if PNPCSV = 0 during POR, default 0x00, 0x00 otherwise) These two registers select FDC I/O base address [0x100:0xFF8] on 8 byte boundary.
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CR70 (Default 0x06 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit [7:4]: Reserved. Bit [3:0]: These bits select IRQ resource for FDC. CR74 (Default 0x02 if PNPCSV = 0 during POR, default 0x04 otherwise) Bit [7:3]: Reserved. Bit [2:0]: These bits select DRQ resource for FDC. = 0x00 DMA0 = 0x01 DMA1 = 0x02 DMA2 = 0x03 DMA3 = 0x04 - 0x07 No DMA active CRF0 (Default 0x0E) FDD Mode Register Bit 7: FIPURDWN This bit controls the internal pull-up resistors of the FDC input pins RDATA, INDEX, TRAK0, DSKCHG, and WP. 0 1 Bit 6: The internal pull-up resistors of FDC are turned on.(Default) The internal pull-up resistors of FDC are turned off.
INTVERTZ This bit determines the polarity of all FDD interface signals. 0 1 FDD interface signals are active low. FDD interface signals are active high.
Bit 5:
DRV2EN (PS2 mode only) When this bit is a logic 0, indicates a second drive is installed and is reflected in status register A.
Bit 4:
Swap Drive 0, 1 Mode 0 1 11 10 01 00 No Swap (Default) Drive and Motor select 0 and 1 are swapped. AT Mode (Default) (Reserved) PS/2 Model 30 Publication Release Date: Dec 2002 Revision 1.0
Bit 3 - 2 Interface Mode
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Bit 1:
FDC DMA Mode 0 1 Burst Mode is enabled Non-Burst Mode (Default) Normal Floppy Mode (Default) Enhanced 3-mode FDD
Bit 0
Floppy Mode 0 1
CRF1 (Default 0x00) Bit 7 - 6 Boot Floppy 00 01 10 11 FDD A FDD B FDD C FDD D
Bit [5:4]: Media ID1, Media ID0. These bits will be reflected on FDC's Tape Drive Register bit 7, 6. Bit [3:2]: Density Select 00 01 10 11 Bit 1: 0 1 Bit 0: 0 1 Normal (Default) Normal 1 ( Forced to logic 1) 0 ( Forced to logic 0) Enable FDD write. Disable FDD write(forces pins WE, WD stay high). Normal, use WP to determine whether the FDD is write protected or not. FDD is always write-protected.
DISFDDWR
SWWP
CRF2 (Default 0xFF) Bit [7:6]: FDD D Drive Type Bit [5:4]: FDD C Drive Type Bit [3:2]: FDD B Drive Type Bit [1:0]: FDD A Drive Type
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CRF4 (Default 0x00) FDD0 Selection: Bit 7: Bit 6: Reserved. Precomp. Disable. 1 0 Bit 5: Disable FDC Precompensation. Enable FDC Precompensation.
Reserved. 00 01 10 11 Select Regular drives and 2.88 format 3-mode drive 2 Meg Tape Reserved
Bit 4 - 3: DRTS1, DRTS0: Data Rate Table select (Refer to TABLE A).
Bit 2:
Reserved.
Bit [1:0]: DTYPE0, DTYPE1: Drive Type select (Refer to TABLE B). CRF5 (Default 0x00) FDD1 Selection: Same as FDD0 of CRF4. TABLE A Drive Rate Table Select DRTS1 DRTS0 0 0 Data Rate DRATE1 1 0 0 1 1 0 0 1 1 0 0 1 DRATE0 1 0 1 0 1 0 1 0 1 0 1 0 Selected Data Rate MFM 1Meg 500K 300K 250K 1Meg 500K 500K 250K 1Meg 500K 2Meg 250K FM --250K 150K 125K --250K 250K 125K --250K --125K SELDEN
0
1
1
0
1 1 0 0 1 1 0 0 1 1 0 0
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TABLE B DTYPE0 0 DTYPE1 0 DRVDEN0(pin 2) SELDEN DRVDEN1(pin 3) DRATE0 DRIVE TYPE 4/2/1 MB 3.5"" 2/1 MB 5.25" 2/1.6/1 MB 3.5" (3-MODE)
0 1 1
1 0 1
DRATE1 SELDEN DRATE0
DRATE0 DRATE0 DRATE1
3.6 Logical Device 1 (Parallel Port)
CR30 (Default 0x01 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit [7:1]: Reserved. Bit 0: 1 0 Activates the logical device. Logical device is inactive.
CR60, CR61 (Default 0x03, 0x78 if PNPCSV = 0 during POR, default 0x00, 0x00 otherwise) These two registers select Parallel Port I/O base address. [0x100:0xFFC] on 4 byte boundary (EPP not supported) or [0x100:0xFF8] on 8 byte boundary (all modes supported, EPP is only available when the base address is on 8 byte boundary). CR70 (Default 0x07 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit [7:4]: Reserved. Bit [3:0]: These bits select IRQ resource for Parallel Port.
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CR74 (Default 0x03) Bit [7:3]: Reserved. Bit [2:0]: These bits select DRQ resource for Parallel Port. 0x00=DMA0 0x01=DMA1 0x02=DMA2 0x03=DMA3 0x04 - 0x07= No DMA active CRF0 (Default 0x3F) Bit 7: Reserved. Bit [6:3]: ECP FIFO Threshold. Bit [2:0]: Parallel Port Mode (CR28 PRTMODS2 = 0) 100 000 001 101 010 011 111 Printer Mode Standard and Bi-direction (SPP) mode EPP - 1.9 and SPP mode EPP - 1.7 and SPP mode ECP mode ECP and EPP - 1.9 mode ECP and EPP - 1.7 mode (Default)
3.7 Logical Device 2 (UART A)
CR30 (Default 0x01 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit [7:1]: Reserved. Bit 0: 1 0 Activates the logical device. Logical device is inactive.
CR60, CR61 (Default 0x03, 0xF8 if PNPCSV = 0 during POR, default 0x00, 0x00 otherwise) These two registers select Serial Port 1 I/O base address [0x100:0xFF8] on 8 byte boundary. CR70 (Default 0x04 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit [7:4]: Reserved.
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Bit [3:0]: These bits select IRQ resource for Serial Port 1. CRF0 (Default 0x00) Bit 7: Bit 6: Reserved. 1 0 Activates the logical device IRQ sharing function. Logical device IRQ sharing is inactive.
Bit [5:2]: Reserved. Bit [1:0]: SUACLKB1, SUACLKB0 00 01 10 11 UART A clock source is 1.8462 Mhz (24MHz/13) UART A clock source is 2 Mhz (24MHz/12) UART A clock source is 24 Mhz (24MHz/1) UART A clock source is 14.769 Mhz (24mhz/1.625)
3.8 Logical Device 3 (UART B)
CR30 (Default 0x01 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit [7:1]: Reserved. Bit 0: 1 0 Activates the logical device. Logical device is inactive.
CR60, CR61 (Default 0x02, 0xF8 if PNPCSV = 0 during POR, default 0x00, 0x00 otherwise) These two registers select Serial Port 2 I/O base address [0x100:0xFF8] on 8 byte boundary. CR70 (Default 0x03 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit [7:4]: Reserved. Bit [3:0]: These bits select IRQ resource for Serial Port 2. CRF0 (Default 0x00) Bit 7: Bit 6: Reserved. 1 0 Activates the logical device IRQ sharing function. Logical device IRQ sharing is inactive.
Bit [5:4]: Reserved.
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Bit 3:
RXW4C 0 1 No reception delay when SIR is changed from TX mode to RX mode. Reception delays 4 characters-time (40 bit-time) when SIR is changed from TX mode to RX mode. No transmission delay when SIR is changed from RX mode to TX mode. Transmission delays 4 characters-time (40 bit-time) when SIR is changed from RX mode to TX mode. UART B clock source is 1.8462 Mhz (24MHz/13) UART B clock source is 2 Mhz (24MHz/12) UART B clock source is 24 Mhz (24MHz/1) UART B clock source is 14.769 Mhz (24mhz/1.625)
Bit 2:
TXW4C 0 1
Bit [1:0]: SUBCLKB1, SUBCLKB0 00 01 10 11
CRF1 (Default 0x00) Bit 7: Bit 6: Reserved. IRLOCSEL. IR I/O pins' location select. 0 1 Bit 5: Bit 4: Bit 3: Through SINB/SOUTB. Through IRRX/IRTX.
IRMODE2. IR function mode selection bit 2. IRMODE1. IR function mode selection bit 1. IRMODE0. IR function mode selection bit 0.
IR MODE 00X 010* 011* 100 101 110 111*
IR FUNCTION Disable IrDA IrDA ASK-IR ASK-IR ASK-IR ASK-IR tri-state
IRTX high Active pulse 1.6 S Active pulse 3/16 bit time Inverting IRTX/SOUTB pin Inverting IRTX/SOUTB & 500 KHZ clock Inverting IRTX/SOUTB Inverting IRTX/SOUTB & 500 KHZ clock
IRRX
Demodulation into SINB/IRRX Demodulation into SINB/IRRX routed to SINB/IRRX routed to SINB/IRRX Demodulation into SINB/IRRX Demodulation into SINB/IRRX
Note: The notation is normal mode in the IR function.
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Bit 2:
HDUPLX. IR half/full duplex function select. 0 1 The IR function is Full Duplex. The IR function is Half Duplex. the SOUTB pin of UART B function or IRTX pin of IR function in normal condition. inverse the SOUTB pin of UART B function or IRTX pin of IR function. the SINB pin of UART B function or IRRX pin of IR function in normal condition. inverse the SINB pin of UART B function or IRRX pin of IR function
Bit 1:
TX2INV. 0 1
Bit 0:
RX2INV. 0 1
3.9 Logical Device 7 (Game Port and GPIO Port 1)
CR30 (Default 0x00) Bit [7:1]: Reserved. Bit 0: 1 0 Game/GP1 Port is active. Game/GP1 Port is inactive.
CR60, CR61 (Default 0x02, 0x01 if PNPCSV = 0 during POR, default 0x00 otherwise) These two registers select the Game Port base address [0x100:0xFFF] on 8 byte boundary. CR62, CR63 (Default 0x00, 0x00) These two registers select the GPIO1 base address [0x100:0xFFF] on 1 byte boundary IO address : CRF1 base address
CRF0 (GP10-GP17 I/O selection register. Default 0xFF) When set to a '1', respective GPIO port is programmed as an input port. When set to a '0', respective GPIO port is programmed as an output port. CRF1 (GP10-GP17 data register. Default 0x00) If a port is programmed to be an output port, then its respective bit can be read/written If a port is programmed to be an input port, then its respective bit can only be read. CRF2 (GP10-GP17 inversion register. Default 0x00) When set to a '1', the incoming/outgoing port value is inverted.
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When set to a '0', the incoming/outgoing port value is the same as in data register.
3.10 Logical Device 8 (MIDI Port and GPIO Port 5)
CR30 (MIDI Port Default 0x00) Bit [7:1]: Reserved. Bit 0: 1 0 MIDI/GP5 port is activate MIDI/GP5 port is inactive.
CR60, CR61 (Default 0x03, 0x30 if PNPCSV = 0 during POR, default 0x00 otherwise) These two registers select the MIDI Port base address [0x100:0xFFF] on 2byte boundary. CR62, CR63 (Default 0x00, 0x00 ) These two registers select the GPIO5 base address [0x100:0xFFF] on 4byte boundary. IO address : CRF1 base address IO address + 1 : CRF3 base address IO address + 2 : CRF4 base address IO address + 3 : CRF5 base address CR70 (Default 0x09 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit [7:4]: Reserved. Bit [3:0]: These bits select IRQ resource for MIDI Port . CRF0 (GP5 selection register. Default 0xFF) When set to a '1', respective GPIO port is programmed as an input port. When set to a '0', respective GPIO port is programmed as an output port. CRF1 (GP5 data register. Default 0x00) If a port is programmed to be an output port, then its respective bit can be read/written. If a port is programmed to be an input port, then its respective bit can only be read. CRF2 (GP5 inversion register. Default 0x00) When set to a '1', the incoming/outgoing port value is inverted. When set to a '0', the incoming/outgoing port value is the same as in data register. Publication Release Date: Dec 2002 Revision 1.0
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CRF3 (PLED mode register. Default 0x00) Bit [7:3] Reserved . : Bit 2: select WDTO count mode. 0 1 00 01 10 11 second minute Power LED pin is tri-stated. Power LED pin is droved low. Power LED pin is a 1Hz toggle pulse with 50 duty cycle. Power LED pin is a 1/4Hz toggle pulse with 50 duty cycle.
Bit [1:0]: select PLED mode
CRF4 (Default 0x00) Watch Dog Timer Time-out value. Writing a non-zero value to this register causes the counter to load the value to Watch Dog Counter and start counting down. Reading this register returns current value in Watch Dog Counter instead of Watch Dog Timer Time-out value. Bit [7:0]: = 0x00 Time-out Disable = 0x01 Time-out occurs after 1 second/minute = 0x02 Time-out occurs after 2 second/minutes = 0x03 Time-out occurs after 3 second/minutes ................................................ = 0xFF Time-out occurs after 255 second/minutes CRF5 (Default 0x00) Bit [7] : Bit [6] : Bit 5: Bit 4: Reserved . invert Watch Dog Timer Status Force Watch Dog Timer Time-out, Write only* 1 1 0 Force Watch Dog Timer time-out event; this bit is self-clearing. Watch Dog Timer time-out occurred. Watch Dog Timer counting Watch Dog Timer Status, R/W
Bit [3:0]: These bits select IRQ resource for Watch Dog. Setting of 2 selects SMI.
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3.11 Logical Device 9 (GPIO Port 2 ~ GPIO Port 4 )
CR30 (Default 0x00) Bit [7:3]: Reserved. Bit 2: Bit 1: Bit 0: 1 0 1 0 1 0 GP4 port is active. GP4 port is inactive GP3 port is active. GP3 port is inactive GP2 port is active. GP2 port is inactive.
CR60,CR61(Default 0x00,0x00). These two registers select the GP2,3,4 base address(0x100:FFF) ON 3 bytes boundary. IO address: CRF1 base address IO address + 1 : CRF4 base address IO address + 2 : CRF7 base address CRF0 (GP2 I/O selection register. Default 0xFF ) When set to a '1', respective GPIO port is programmed as an input port. When set to a '0', respective GPIO port is programmed as an output port. CRF1 (GP2 data register. Default 0x00 ) If a port is programmed to be an output port, then its respective bit can be read/written. If a port is programmed to be an input port, then its respective bit can only be read. CRF2 (GP2 inversion register. Default 0x00 ) When set to a '1', the incoming/outgoing port value is inverted. When set to a '0', the incoming/outgoing port value is the same as in data register. CRF3 (GP3 I/O selection register. Default 0xFF ) When set to a '1', respective GPIO port is programmed as an input port. When set to a '0', respective GPIO port is programmed as an output port. CRF4 (GP3 data register. Default 0x00 ) If a port is programmed to be an output port, then its respective bit can be read/written. If a port is programmed to be an input port, then its respective bit can only be read. Publication Release Date: Dec 2002 Revision 1.0
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CRF5 (GP3 inversion register. Default 0x00 ) When set to a '1', the incoming/outgoing port value is inverted. When set to a '0', the incoming/outgoing port value is the same as in data register. CRF6 (GP4 I/O selection register. Default 0xFF ) When set to a '1', respective GPIO port is programmed as an input port. When set to a '0', respective GPIO port is programmed as an output port. CRF7 (GP4 data register. Default 0x00 ) If a port is programmed to be an output port, then its respective bit can be read/written. If a port is programmed to be an input port, then its respective bit can only be read. CRF8 (GP4 inversion register. Default 0x00 ) When set to a '1', the incoming/outgoing port value is inverted. When set to a '0', the incoming/outgoing port value is the same as in data register.
3.12 Logical Device A (ACPI)
CR30 (Default 0x00) Bit [7:1]: Reserved. Bit 0: 1 0 Activates the logical device. Logical device is inactive.
CR70 (Default 0x00) Bit [7:4]: Reserved. Bit [3:0]: These bits select IRQ resources for SMI PME / CRF0 (Default 0x00) Bit 7: CHIPPME. Chip level auto power management enable. 0 1 Bit 6: disable the auto power management functions enable the auto power management functions.
Reserved. (Return zero when read)
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Bit 5:
MIDIPME. MIDI port auto power management enable. 0 1 disable the auto power management functions enable the auto power management functions
Bit 4: Bit 3:
Reserved. (Return zero when read) PRTPME. PRT auto power management enable. 0 1 disable the auto power management functions. enable the auto power management functions. disable the auto power management functions. enable the auto power management functions. disable the auto power management functions. enable the auto power management functions. disable the auto power management functions. enable the auto power management functions.
Bit 2:
FDCPME. FDC auto power management enable. 0 1
Bit 1:
URAPME. UART A auto power management enable. 0 1
Bit 0:
URBPME. UART B auto power management enable. 0 1
CRF1 (Default 0x00) Bit 7: WAK_STS. This bit is set when the chip is in the sleeping state and an enabled resume event occurs. Upon setting this bit, the sleeping/working state machine will transition the system to the working state. This bit is only set by hardware and is cleared by writing a 1 to this bit position or by the sleeping/working state machine automatically when the global standby timer expires. 0 1 Bit 6: Bit 5: Bit 4: Bit 3: Bit 2: Bit 1: Bit 0: the chip is in the sleeping state. the chip is in the working state.
Reserved. (Return zero when read) MIDI's trap status. Reserved. (Return zero when read) PRT's trap status. FDC's trap status. URA's trap status. URB's trap status.
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CRF2 (Default 0x00) Bit [7:3]: Reserved. (Return zero when read) Bit 2: Bit 1: Bit 0: SC's trap status. Reserved Reserved
CRF3 (Default 0x00) These bits indicate the IRQ status of the individual device respectively. The device's IRQ status bit is set by their source device and is cleared by writing a 1. Writing a 0 has no effect. Bit 7: Bit 6: Bit 3: Bit 2: Bit 1: Bit 0: Reserved Reserved PRTIRQSTS. PRT IRQ status. FDCIRQSTS. FDC IRQ status. URAIRQSTS. UART A IRQ status. URBIRQSTS. UART B IRQ status.
Bit [5:4]: Reserved. (Return zero when read)
CRF4 (Default 0x00) These bits indicate the IRQ status of the individual GPIO function or logical device respectively. The status bit is set by their source function or device and is cleared by writing a 1. Writing a 0 has no effect. Bit 7: Bit 6: Bit 2: Bit 1: Bit 0: Reserved. (Return zero when read) SCIRQSTS. SC IRQ status. WDTIRQSTS. Watch dog timer IRQ status. Reserved. (Return zero when read). MIDIIRQSTS. MIDI IRQ status.
Bit [5:3]: Reserved. (Return zero when read)
CRF6 (Default 0x00) These bits enable the generation of an SMI / PME interrupt due to any IRQ of the devices. SMI / PME logic output = (PRTIRQEN and PRTIRQSTS) or (FDCIRQEN and FDCIRQSTS) or (URAIRQEN and URAIRQSTS) or (URBIRQEN and URBIRQSTS) or (WDTIRQEN and WDTIRQSTS) or (MIDIIRQEN and MIDIIRQEN) or (SCIRQEN and SCIRQEN) Bit 7: Reserved
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0 1 Bit 6:
disable the generation of an SMI / PME interrupt due to URD's IRQ. enable the generation of an SMI / PME interrupt due to URD's IRQ.
Reserved 0 1 disable the generation of an SMI / PME interrupt due to URC's IRQ. enable the generation of an SMI / PME interrupt due to URC's IRQ.
Bit [5:4]: Reserved (Return zero when read) Bit 3: PRTIRQEN. 0 1 Bit 2: disable the generation of an SMI / PME interrupt due to PRT's IRQ. enable the generation of an SMI / PME interrupt due to PRT's IRQ.
FDCIRQEN. 0 1 disable the generation of an SMI / PME interrupt due to FDC's IRQ. enable the generation of an SMI / PME interrupt due to FDC's IRQ.
Bit 1:
URAIRQEN. 0 1 disable the generation of an SMI / PME interrupt due to UART A's IRQ. enable the generation of an SMI / PME interrupt due to UART A's IRQ.
Bit 0:
URBIRQEN. 0 1 disable the generation of an SMI / PME interrupt due to UART B's IRQ. enable the generation of an SMI / PME interrupt due to UART B's IRQ.
CRF7 (Default 0x00) These bits enable the generation of an SMI / PME interrupt due to any IRQ of the devices. Bit 7: Bit 6: Reserved. (Return zero when read) SCIRQEN. 0 1 disable the generation of an SMI / PME interrupt due to SC timer's IRQ. enable the generation of an SMI / PME interrupt due to SC timer's IRQ.
Bit [5:3]: Reserved. (Return zero when read) Bit 2: WDTIRQEN. 0 1 Bit 1: Bit 0: disable the generation of an SMI / PME interrupt due to watch dog timer's IRQ. enable the generation of an SMI / SMI interrupt due to watch dog timer's IRQ.
Reserved. (Return zero when read) MIDIIRQEN.
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0 1
disable the generation of an SMI / PME interrupt due to MIDI's IRQ. enable the generation of an SMI / PME interrupt due to MIDI's IRQ.
CRF9 (Default 0x00) Bit [7:3]: Reserved. Return zero when read. Bit 2: PME_EN: Select the power management events to be either an PME or SMI interrupt for the IRQ events. Note that: this bit is valid only when SMIPME_OE = 1. 0 1 Bit 1: the power management events will generate an SMI event. the power management events will generate an PME event. 1S 8 mS
FSLEEP: This bit selects the fast expiry time of individual devices. 0 1
Bit 0:
SMIPME_OE: This is the SMI and PME output enable bit. 0 1 neither SMI nor PME will be generated. Only the IRQ status bit is set. an SMI or PME event will be generated.
CRFA (Default 0x00) Bit [7:3]: Reserved. (Return zero when read) Bit 2: SCPME. SC auto power management enable. 0 1 Bit 1: Bit 0: disable the auto power management functions. enable the auto power management functions.
Reserved Reserved
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3.13 Logical Device B (PWM)
CR30 (Default 0x00) Bit [7:1]: Reserved. Bit 0: 1 0 Activates the logical device. Logical device is inactive.
CR60, CR61 (Default 0x00, 0x00) These two registers select Pulse Width Modulation base address [0x100:0xFFF] on 8-byte boundary.
3.14 Logical Device C (SMART CARD)
CR30 (Default 0x00) Bit [7:1]: Reserved. Bit 0: 1 0 Activates the logical device. Logical device is inactive.
CR60, CR61 (Default 0x00, 0x00) These two registers select Smart Card base address [0x100:0xFFF] on 8-byte boundary. CR70 (Default 0x00) Bit [7:4]: Reserved. Bit [3:0]: These bit select IRQ resource for Smart Card interface. CRF0 (Default 0x00) Bit [7:1]: Reserved. Bit 0: 1 0 Smart Card present signal (SCPSNT) is LOW active. SCPSNT is HIGH active.
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3.15 Logical Device D (GPIO Port 6 )
CR30 (Default 0x00) Bit [7:2]: Reserved. Bit 1: Bit 0: 1 0 Activate GPIO6. GPIO6 is inactive Reserved
CR60, CR61 (Default 0x03, 0xE8 if PNPCSV = 0 during POR, default 0x00, 0x00 otherwise) These two registers select the Serial Port 3 I/O base address [0x100:0xFF8] on 8yte boundary. CR62, CR63 (Default 0x00) These two registers select the GPIO6 base address [0x100:0xFFF] on 4byte boundary. IO address: CRF2 base address
CR70 (Default 0x00) Bit [7:4]: Reserved. Bit [3:0]: These bits select IRQ resource for Serial Port 3. CRF0 (Default 0x00) Bit 7: Bit 6: Reserved. 1 0 Activates the logical device IRQ sharing function. Logical device IRQ sharing is inactive.
Bit [5:2]: Reserved. Bit [1:0]: SUCCLKB1, SUCCLKB0 00 01 10 11 UART C clock source is 1.8462 Mhz (24MHz/13) UART C clock source is 2 Mhz (24MHz/12) UART C clock source is 24 Mhz (24MHz/1) UART C clock source is 14.769 Mhz (24mhz/1.625)
CRF1 (GP6 selection register. Default 0xFF) When set to a '1', respective GPIO port is programmed as an input port. When set to a '0', respective GPIO port is programmed as an output port.
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CRF2 (GP6 data register. Default 0x00 ) If a port is programmed to be an output port, then its respective bit can be read/written. If a port is programmed to be an input port, then its respective bit can only be read. CRF3 (GP6 inversion register. Default 0x00 ) When set to a '1', the incoming/outgoing port value is inverted. When set to a '0', the incoming/outgoing port value is the same as in data register. CRF4 (GP6 output style register. Default 0x00 ) When set to a '1', the outgoing port is pulse mode. When set to a '0', the outgoing port is level mode.
3.16 Logical Device E (GPIO Port 7 )
CR30 (Default 0x00) Bit [7:2]: Reserved. Bit 1: Bit 0: 1 0 Activate GPIO7. GPIO7 is inactive Reserved
CR60, CR61 (Default 0x02, 0xE8 if PNPCSV = 0 during POR, default 0x00, 0x00 otherwise) These two registers select the Serial Port 4 I/O base address [0x100:0xFF8] on 8yte boundary. CR62, CR63 (Default 0x00) These two registers select the GPIO7 base address [0x100:0xFFF] on 4byte boundary. IO address : CRF2 base address
CR70(Default 0x00) Bit [7:4]: Reserved. Bit [3:0]: These bits select IRQ resource for Serial Port 4.
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CRF0 (Default 0x00) Bit 7: Bit 6: Reserved. 1 0 Activates the logical device IRQ sharing function. Logical device IRQ sharing is inactive.
Bit [5:2]: Reserved. Bit [1:0]: SUDCLKB1, SUDCLKB0 00 01 10 11 UART D clock source is 1.8462 Mhz (24MHz/13) UART D clock source is 2 Mhz (24MHz/12) UART D clock source is 24 Mhz (24MHz/1) UART D clock source is 14.769 Mhz (24mhz/1.625)
CRF1 (GP7 selection register. Default 0xFF) When set to a '1', respective GPIO port is programmed as an input port. When set to a '0', respective GPIO port is programmed as an output port. CRF2 (GP7 data register. Default 0x00 ) If a port is programmed to be an output port, then its respective bit can be read/written. If a port is programmed to be an input port, then its respective bit can only be read. CRF3 (GP7 inversion register. Default 0x00 ) When set to a '1', the incoming/outgoing port value is inverted. When set to a '0', the incoming/outgoing port value is the same as in data register.
3.17 Logical Device F (GPIO Port 8)
CR30 (Default 0x00) Bit [7:1]: Reserved. Bit 0: 1 0 Activate GPIO8. PIO8 is inactive.
CR60, CR61 (Default 0x00) These two registers select the GPIO8 base address [0x100:0xFFF] on 2byte boundary. IO address : CRF1 base address
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CRF0 (GP8 selection register. Default 0xFF) When set to a '1', respective GPIO port is programmed as an input port. When set to a '0', respective GPIO port is programmed as an output port. CRF1 (GP8 data register. Default 0x00 ) If a port is programmed to be an output port, then its respective bit can be read/written. If a port is programmed to be an input port, then its respective bit can only be read. CRF2 (GP8 inversion register. Default 0x00 ) When set to a '1', the incoming/outgoing port value is inverted. When set to a '0', the incoming/outgoing port value is the same as in data register.
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4. SPECIFICATIONS
4.1 Absolute Maximum Ratings
PARAMETER Power Supply Voltage (5V) Input Voltage RTC Battery Voltage VBAT Operating Temperature Storage Temperature RATING -0.5 to 7.0 -0.5 to VDD+0.5 2.2 to 4.0 0 to +70 -55 to +150 UNIT V V V C C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.
4.2 DC CHARACTERISTICS
(Ta = 0 C to 70 C, VDD = 5V 10%, VSS = 0V) PARAMETER RTC Battery Quiescent Current ACPI Stand-by Power Supply Quiescent Current SYM. IBAT IBAT MIN. TYP. MAX. 2.4 2.0 UNIT uA mA CONDITIONS VBAT = 2.5 V VSB = 5.0 V, All ACPI pins are not connected.
I/O8t - TTL level bi-directional pin with 8mA source-sink capability Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage VIL VIH VOL VOH ILIH ILIL 2.4 +10 -10 2.0 0.4 0.8 V V V V A A IOL = 8 mA IOH = - 8 mA VIN = 5V VIN = 0V
I/O12t - TTL level bi-directional pin with 12mA source-sink capability Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input High Leakage VIL VIH VOL VOH ILIH 2.4 +10 2.0 0.4 0.8 V V V V A IOL = 12 mA IOH = -12 mA VIN = 5V
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Input Low Leakage 4.2 DC CHARACTERISTICS, continuedILIL PARAMETER SYM. MIN. TYP.
-10 MAX.
A UNIT
VIN = 0V CONDITIONS
I/O24t - TTL level bi-directional pin with 24mA source-sink capability Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage VIL VIH VOL VOH ILIH ILIL 2.4 +10 -10 2.0 0.4 0.8 V V V V A A IOL = 24 mA IOH = -24 mA VIN = 5V VIN = 0V
I/O12tp3 - 3.3V TTL level bi-directional pin with 12mA source-sink capability Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage VIL VIH VOL VOH ILIH ILIL 2.4 +10 -10 2.0 0.4 0.8 V V V V A A IOL = 12 mA IOH = -12 mA VIN = 3.3V VIN = 0V
I/O12ts - TTL level Schmitt-trigger bi-directional pin with 12mA source-sink capability Input Low Threshold Voltage Input High Threshold Voltage Hystersis Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage VtVt+ VTH VOL VOH ILIH ILIL 2.4 +10 -10 0.5 1.6 0.5 0.8 2.0 1.2 0.4 1.1 2.4 V V V V V A A VDD=5V IOL = 12 mA IOH = -12 mA VIN = 5V VIN = 0V
I/O24ts - TTL level Schmitt-trigger bi-directional pin with 24mA source-sink capability Input Low Threshold Voltage Input High Threshold Voltage Hystersis Output Low Voltage Output High Voltage VtVt+ VTH VOL VOH 2.4 0.5 1.6 0.5 0.8 2.0 1.2 0.4 1.1 2.4 V V V V V VDD=5V IOL = 24 mA IOH = -24 Ma
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4.2 DC CHARACTERISTICS, continued
PARAMETER Input High Leakage Input Low Leakage
SYM. ILIH ILIL
MIN.
TYP. MAX. +10 -10
UNIT A A
CONDITIONS VIN = 5V VIN = 0V
I/O24tsp3 - 3.3V TTL level Schmitt-trigger bi-directional pin with 24mA source-sink capability Input Low Threshold Voltage Input High Threshold Voltage Hystersis Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage VtVt+ VTH VOL VOH ILIH ILIL 2.4 +10 -10 0.5 1.6 0.5 0.8 2.0 1.2 0.4 1.1 2.4 V V V V V A A VDD=3.3V IOL = 24 mA IOH = -24 mA VIN = 3.3V VIN = 0V
I/OD12t - TTL level bi-directional pin and open-drain output with 12mA sink capability Input Low Voltage Input High Voltage Output Low Voltage Input High Leakage Input Low Leakage VIL VIH VOL ILIH ILIL 2.0 0.4 +10 -10 0.8 V V V A A IOL = 12 mA VIN = 5V VIN = 0V
I/OD24t - TTL level bi-directional pin and open-drain output with 24mA sink capability Input Low Voltage Input High Voltage Output Low Voltage Input High Leakage Input Low Leakage VIL VIH VOL ILIH ILIL 2.0 0.4 +10 -10 0.8 V V V A A IOL = 24 mA VIN = 5V VIN = 0V
I/OD24c - CMOS level bi-directional pin and open drain output with 24mA sink capability Input Low Voltage Input High Voltage Output Low Voltage Input High Leakage Input Low Leakage VIL VIH VOL ILIH ILIL 3.5 0.4 +10 -10 1.5 V V V A A IOL = 24 mA VIN = 5V VIN = 0 V
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4.2 DC CHARACTERISTICS, continued
PARAMETER
SYM.
MIN.
TYP. MAX.
UNIT
CONDITIONS
I/OD24a - Bi-directional pin with analog input and open-drain output with 24mA sink capability Output Low Voltage Input High Leakage Input Low Leakage VOL ILIH ILIL 0.4 +10 -10 V A A IOL = 24 mA VIN = 5V VIN = 0V
I/OD12ts - TTL level Schmitt-trigger bi-directional pin and open drain output with 12mA sink capability Input Low Threshold Voltage Input High Threshold Voltage Hystersis Output Low Voltage Input High Leakage Input Low Leakage VtVt+ VTH VOL ILIH ILIL 0.5 1.6 0.5 0.8 2.0 1.2 0.4 +10 -10 1.1 2.4 V V V V A A VDD=5V IOL = 12 mA VIN = 5V VIN = 0V
I/OD24ts - TTL level Schmitt-trigger bi-directional pin and open drain output with 24mA sink capability Input Low Threshold Voltage Input High Threshold Voltage Hystersis Output Low Voltage Input High Leakage Input Low Leakage VtVt+ VTH VOL ILIH ILIL 0.5 1.6 0.5 0.8 2.0 1.2 0.4 +10 -10 1.1 2.4 V V V V A A VDD=5V IOL = 24 mA VIN = 5V VIN = 0V
I/OD12cs - CMOS level Schmitt-trigger bi-directional pin and open drain output with 12mA sink capability Input Low Threshold Voltage Input High Threshold Voltage Hystersis Output Low Voltage Input High Leakage Input Low Leakage VtVt+ VTH VOL ILIH ILIL 1.3 3.2 1.5 1.5 3.5 2 0.4 +10 -10 1.7 3.8 V V V V A A VDD = 5 V VDD = 5 V VDD = 5 V IOL = 12 mA VIN = 5V VIN = 0 V
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4.2 DC CHARACTERISTICS, continued
PARAMETER
SYM.
MIN.
TYP.
MAX.
UNIT
CONDITIONS
I/OD16cs - CMOS level Schmitt-trigger bi-directional pin and open drain output with 16mA sink capability Input Low Threshold Voltage Input High Threshold Voltage Hystersis Output Low Voltage Input High Leakage Input Low Leakage VtVt+ VTH VOL ILIH ILIL 1.3 3.2 1.5 1.5 3.5 2 0.4 +10 -10 1.7 3.8 V V V V A A VDD = 5 V VDD = 5 V VDD = 5 V IOL = 16 mA VIN = 5V VIN = 0 V
I/OD24cs - CMOS level Schmitt-trigger bi-directional pin and open drain output with 24mA sink capability Input Low Threshold Voltage Input High Threshold Voltage Hystersis Output Low Voltage Input High Leakage Input Low Leakage VtVt+ VTH VOL ILIH ILIL 1.3 3.2 1.5 1.5 3.5 2 0.4 +10 -10 1.7 3.8 V V V V A A VDD = 5 V VDD = 5 V VDD = 5 V IOL = 24 mA VIN = 5V VIN = 0 V
I/OD12csd - CMOS level Schmitt-trigger bi-directional pin with internal pull down resistor and open drain output with 12mA sink capability Input Low Threshold Voltage Input High Threshold Voltage Hystersis Output Low Voltage Input High Leakage Input Low Leakage VtVt+ VTH VOL ILIH ILIL 1.3 3.2 1.5 1.5 3.5 2 0.4 +10 -10 1.7 3.8 V V V V A A VDD = 5 V VDD = 5 V VDD = 5 V IOL = 12 mA VIN = 5V VIN = 0 V
I/OD12csu - CMOS level Schmitt-trigger bi-directional pin with internal pull up resistor and open drain output with 12mA sink capability Input Low Threshold Voltage Input High Threshold Voltage Hystersis Output Low Voltage VtVt+ VTH VOL 1.3 3.2 1.5 1.5 3.5 2 0.4 1.7 3.8 V V V V VDD = 5 V VDD = 5 V VDD = 5 V IOL = 12 mA
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Publication Release Date: Dec 2002 Revision 1.0
W83697SF
Input High Leakage
4.2 DC CHARACTERISTICS, continued
ILIH
+10
A
VIN = 5V
PARAMETER Input Low Leakage
SYM. ILIL
MIN.
TYP.
MAX. -10
UNIT A
CONDITIONS VIN = 0 V
O4 - Output pin with 4mA source-sink capability Output Low Voltage Output High Voltage VOL VOH 2.4 0.4 V V IOL = 4 mA IOH = -4 mA
O8 - Output pin with 8mA source-sink capability Output Low Voltage Output High Voltage VOL VOH 2.4 0.4 V V IOL = 8 mA IOH = -8 mA
O12 - Output pin with 12mA source-sink capability Output Low Voltage Output High Voltage VOL VOH 2.4 0.4 V V IOL = 12 mA IOH = -12 mA
O16 - Output pin with 16mA source-sink capability Output Low Voltage Output High Voltage VOL VOH 2.4 0.4 V V IOL = 16 mA IOH = -16 mA
O24 - Output pin with 24mA source-sink capability Output Low Voltage Output High Voltage VOL VOH 2.4 0.4 V V IOL = 24 mA IOH = -24 mA
O12p3 - 3.3V output pin with 12mA source-sink capability Output Low Voltage VOL 0.4 V IOL = 12 mA
O24p3 - 3.3V output pin with 24mA source-sink capability Output Low Voltage VOL 0.4 V IOL = 24 mA
OD12 - Open drain output pin with 12mA sink capability Output Low Voltage VOL 0.4 V IOL = 12 mA
OD24 - Open drain output pin with 24mA sink capability Output Low Voltage VOL 0.4 V IOL = 24 mA
OD12p3 - 3.3V open drain output pin with 12mA sink capability Output Low Voltage INt - TTL level input pin Input Low Voltage VOL 0.4 V IOL = 12 mA
3.2 DC CHARACTERISTICS, continued
VIL
0.8
V
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Publication Release Date: Dec 2002 Revision 1.0
W83697SF
4.2 DC CHARACTERISTICS, continued
PARAMETER Input High Voltage Input High Leakage Input Low Leakage INtp3 - 3.3V TTL level input pin Input Low Voltage Input High Voltage Input High Leakage Input Low Leakage
SYM. VIH ILIH ILIL
MIN. 2.0
TYP.
MAX.
UNIT V
CONDITIONS
+10 -10
A A
VIN = 5V VIN = 0 V
VIL VIH ILIH ILIL 2.0
0.8
V V A A
+10 -10
VIN = 3.3V VIN = 0 V
INtd - TTL level input pin with internal pull down resistor Input Low Voltage Input High Voltage Input High Leakage Input Low Leakage VIL VIH ILIH ILIL 2.0 +10 -10 0.8 V V A A VIN = 5V VIN = 0 V
INtu - TTL level input pin with internal pull up resistor Input Low Voltage Input High Voltage Input High Leakage Input Low Leakage INts VIL VIH ILIH ILIL 2.0 +10 -10 0.8 V V A A VIN = 5V VIN = 0 V
- TTL level Schmitt-trigger input pin VtVt+ VTH ILIH ILIL 0.8 1.8 0.8 0.9 1.9 1.0 +10 -10 1.0 2.0 V V V A A VDD = 5 V VDD = 5 V VDD = 5 V VIN = 5V VIN = 0 V
Input Low Threshold Voltage Input High Threshold Voltage Hystersis Input High Leakage Input Low Leakage
INtsp3 - 3.3 V TTL level Schmitt-trigger input pin Input Low Threshold Voltage Input High Threshold Voltage Hystersis Input High Leakage Input Low Leakage VtVt+ VTH ILIH ILIL 0.8 1.8 0.8 0.9 1.9 1.0 +10 -10 1.0 2.0 V V V A A VDD = 3.3 V VDD = 3.3 V VDD = 3.3 V VIN = 3.3 V VIN = 0 V
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Publication Release Date: Dec 2002 Revision 1.0
W83697SF
4.2 DC CHARACTERISTICS, continued
PARAMETER INc
SYM.
MIN.
TYP.
MAX.
UNIT
CONDITIONS
- CMOS level input pin VIL VIH ILIH ILIL 3.5 +10 -10 1.5 V V A A VIN = 5V VIN = 0 V
Input Low Voltage Input High Voltage Input High Leakage Input Low Leakage INcu
- CMOS level input pin with internal pull up resistor VIL VIH ILIH ILIL 3.5 +10 -10 1.5 V V A A VIN = 5V VIN = 0 V
Input Low Voltage Input High Voltage Input High Leakage Input Low Leakage INcd
- CMOS level input pin with internal pull down resistor VIL VIH ILIH ILIL 3.5 +10 -10 1.5 V V A A VIN = 5V VIN = 0 V
Input Low Voltage Input High Voltage Input High Leakage Input Low Leakage INcs
- CMOS level Schmitt-trigger input pin VtVt+ VTH ILIH ILIL 1.3 3.2 1.5 1.5 3.5 2 +10 -10 1.7 3.8 V V V A A VDD = 5 V VDD = 5 V VDD = 5 V VIN = 5 V VIN = 0 V
Input Low Threshold Voltage Input High Threshold Voltage Hystersis Input High Leakage Input Low Leakage INcsu
- CMOS level Schmitt-trigger input pin with internal pull up resistor VtVt+ VTH ILIH ILIL 1.3 3.2 1.5 1.5 3.5 2 +10 -10 1.7 3.8 V V V A A VDD = 5 V VDD = 5 V VDD = 5 V VIN = 5V VIN = 0 V
Input Low Threshold Voltage Input High Threshold Voltage Hystersis Input High Leakage Input Low Leakage
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Publication Release Date: Dec 2002 Revision 1.0
W83697SF
5. APPLICATION CIRCUITS
5.1 Parallel Port Extension FDD
JP13
WE2/SLCT WD2/PE MOB2/BUSY DSB2/ACK PD7 PD6 PD5 DCH2/PD4 RDD2/PD3 STEP2/SLIN WP2/PD2 DIR2/INIT TRK02/PD1 HEAD2/ERR IDX2/PD0 RWC2/AFD STB 13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 14 1
JP 13A
DCH2 HEAD2 RDD2
WP2
TRK02 WE2 WD2 STEP2 DIR2 MOB2 DSB2 IDX2
RWC2
34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2
33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1
EXT FDC
PRINTER PORT
Parallel Port Extension FDD Mode Connection Diagram
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Publication Release Date: Dec 2002 Revision 1.0
W83697SF
5.2 Parallel Port Extension 2FDD
JP13
WE2/SLCT WD2/PE MOB2/BUSY DSB2/ACK DSA2/PD7 MOA2/PD6 PD5 DCH2/PD4 RDD2/PD3 STEP2/SLIN WP2/PD2 DIR2/INIT TRK02/PD1 HEAD2/ERR IDX2/PD0 RWC2/AFD STB 13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 14 1
JP 13A
DCH2 HEAD2 RDD2
WP2
TRK02 WE2 WD2 STEP2 DIR2 MOB2 DSA2 DSB2 MOA2 IDX2
RWC2
34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2
33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1
EXT FDC
PRINTER PORT
Parallel Port Extension 2FDD Connection Diagram
5.3 Four FDD Mode
74LS139 W83977F DSA DSB MOA MOB G2 A2 B2 G1 A1 B1 1Y0 1Y1 1Y2 1Y3 2Y0 2Y1 2Y2 2Y3 DSA DSB DSC DSD MOA MOB MOC MOD 7407(2)
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Publication Release Date: Dec 2002 Revision 1.0
W83697SF
6. ORDERING INSTRUCTION
PART NO. W83697SF PACKAGE 128-pin QFP REMARKS
7. HOW TO READ THE TOP MARKING
Example: The top marking of W83697SF
SMART@IO
W83697SF 109G5BBBA
1st line: Winbond logo & SMART@IO 2nd line: the type number: W83697SF 3th line: the tracking code 109 G 5B B BA 109: packages made in 2001, week 09 G: assembly house ID; A means ASE, S means SPIL, G means GR, etc. 5B: Winbond internal use. B: IC revision; A means version A, B means version B BA: Winbond internal use.
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Publication Release Date: Dec 2002 Revision 1.0
W83697SF
8. PACKAGE DIMENSIONS
(128-pin PQFP)
HE E
102 65
Symbol Min
Dimension in mm
Dimension in inch
Nom
0.35 2.72 0.20 0.15 14.00 20.00 0.50
Max
0.45 2.87 0.30 0.20 14.10 20.10
Min
0.010 0.101 0.004 0.004 0.547
Nom Max
0.014 0.107 0.008 0.006 0.551 0.018 0.113 0.012 0.008 0.555 0.791
103
64
D
HD
128
39
1
e
b
38
A1 A2 b c D E e HD HE L L1 y 0
c
0.25 2.57 0.10 0.10 13.90 19.90
0.783 0.787 0.020
17.00 23.00 0.65
17.20 23.20 0.80 1.60
17.40 23.40 0.95
0.669 0.905 0.025
0.677 0.913 0.031 0.063
0.685 0.921 0.037
0.08 0 7 0
0.003 7
Note:
1.Dimension D & E do not include interlead flash. 2.Dimension b does not include dambar protrusion/intrusion . 3.Controlling dimension : Millimeter 4.General appearance spec. should be based on final visual inspection spec.
A A2
See Detail F Seating Plane
A1 y
L L1 Detail F
5. PCB layout please use the "mm".
Headquarters
No. 4, Creation Rd. III Science-Based Industrial Park Hsinchu, Taiwan TEL: 886-35-770066 FAX: 886-35-789467 www: http://www.winbond.com.tw/
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II 123 Hoi Bun Rd., Kwun Tong Kowloon, Hong Kong TEL: 852-27516023-7 FAX: 852-27552064
Winbond Electronics (North America) Corp.
2730 Orchard Parkway San Jose, CA 95134 U.S.A. TEL: 1-408-9436666 FAX: 1-408-9436668
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd. Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502 TLX: 16485 WINTPE
Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their original owners
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Publication Release Date: Dec 2002 Revision 1.0
W83697SF
APPENDIX A : DEMO CIRCUIT
W83697SF
3 3 3 ROMCS# MEMR# MEMW# PME#
XD0 XD1 XD2 XD3 XD4 XD5 XD6 XD7 XA0 XA1 XA2 XA3 XA4 XA5 XA6 XA7 XA8 XA9 XA10 XA11 XA12 XA13 XA14 XA15 XA16 XA17 XA18
XD[0..7]
XD[0..7]
3
GP67 GP66 GP65 GP64 GP63 GP62 GP61 GP60
XA[0..18]
XA[0..18]
3
VCC
IRTX 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 U1
2
GP64 GP65 GP66 GP67 PME# MEMW#/GP52 MEMR#/GP53 ROMCS#/GP54 XD0/GP20 XD1/GP21 XD2/GP22 XD3/GP23 GND XD4/GP24 XD5/GP25 XD6/GP26 XD7/GP27 XA0/GP30 XA1/GP31 XA2/GP32 XA3/GP33 XA4/GP34 XA5/GP35 XA6/GP36 XA7/GP37 XA8/GP40 XA9/GP41 VCC XA10/GP42 XA11/GP43 XA12/GP44 XA13/GP45 XA14/GP46 XA15/GP47 XA16/GP55 XA17/GP56 XA18/GP57 IRTX
IR
IRRX RIB# DCDB# SOUTB GND SINB DTRB# RTSB# DSRB# CTSB# RIA# DCDA# SOUTA SINA DTRA# RTSA# DSRA# CTSA# STB# VCC AFD# INIT# PD0 PD1 PD2 PD3 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 IRRX RIB# DCDB# SOUTB SINB DTRB# RTSB# DSRB# CTSB# RIA# DCDA# SOUTA SINA DTRA# RTSA# DSRA# CTSA# STB# AFD# INIT# 2 2 2 2,4 2 2 2 2 2 2 2 2,4 2 2,4 2,4 2 2 2 2 2
4 4 4 SMART CARD INTERFACE 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3
FAN PWM OUTPUT
MIDI PORT
GAME PORT
SCPSNT SCIO SCCLK SCRST GP73 SCC8 SCPWR SCC4 PWM2 PWM1 PWM0 WDTO MSI MSO GPAS2 GPBS2 GPAY GPBY GPBX GPAX GPBS1 GPAS1
103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
GP63 GP62 GP61 GP60 SCPSNT/GP77 SCIO/GP76 SCCLK/GP75 SCRST/GP74 GP73 SCC8/GP72 SCPWR/GP71 SCC4/GP70 PWM2/PLED/GP83 PWM1/GP82 PWM0/GP81 WDTO/GP80 MSI/GP51 MSO/GP50 GPAS2/GP17 GPBS2/GP16 GPAY/GP15 GPBY/GP14 GPBX/GP13 GPAX/GP12 GPBS1/GP11 GPAS1/GP10
& COMB
W83697SF
COMA
VCC
C1 0.1u
DRVDEN0 INDEX# MOA# DSB# VCC DSA# MOB# DIR# STEP# WD# WE# TRAK0# WP# RDATA# HEAD# DSKCHG# CLKIN GND PCICLK LDRQ# SERIRQ VCC3 LAD3 LAD2 LAD1 LAD0 LFRAME# LRESET# SLCT PE BUSY ACK# ERR# SLIN# PD7 PD6 PD5 PD4
Printer
PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD[0..7] PD[0..7] 2
J1 2 1 4 3 6 5 8 7 10 9 12 11 14 13 16 15 18 17 20 19 22 21 24 23 26 25 28 27 30 29 32 31 34 33 HEADER 17X2
RWC# INDEX# MOA# DSB# DSA# MOB# DIR# STEP# WD# WE# TRAK0# WP# RDATA# HEAD# DSKCHG# 1 OSC1 NC OUTPUT 5 24/48MHz PCICLK LDRQ# VCC3V SERIRQ LAD[0..3] VCC3V R2 LAD[0..3]4.7K VCC LFRAME# LRESET# R3 4.7K R1 4.7K LAD3 LAD2 LAD1 LAD0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
SLIN# ERR# ACK# BUSY PE SLCT VCC3V C2 0.1u C3 0.1u VCC |LINK |697SFD2.SCH |697SFD3.SCH |697SFD4.SCH |697SFD5.SCH |697SFD6.SCH
2 2 2 2 2 2
FDC
Winbond Electronic Corp. Title W83697SF Size B Date: Document Number 697SD1.SCH Thursday, August 30, 2001 Sheet 1 of 5 Rev 1.0
LAD[0~3] IS RECOMMAND PULL HIGH 3VCC
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Publication Release Date: Dec 2002 Revision 1.0
W83697SF
COM PORT
VCC 1,4 1,4 1,4 1 1 1 1 1 RTSA# DTRA# SOUTA RIA# CTSA# DSRA# SINA DCDA# 20 16 15 13 19 18 17 14 12 11 U2 VCC DA1 DA2 DA3 RY1 RY2 RY3 RY4 RY5 GND W83778 (SOP20) +12V DY1 DY2 DY3 RA1 RA2 RA3 RA4 RA9 -12V 1 5 6 8 2 3 4 7 9 10 +12V NRTSA NDTRA NSOUTA NRIA NCTSA NDSRA NSINA NDCDA -12V
IR/CIR CONNECTOR
NDCDA NSOUTA GND NRTSA NRIA J2 1 2 3 4 5 6 7 8 9 10 CN2X5B NSINA NDTRA NDSRA NCTSA
VCC JP1 1 2 3 4 5 HEADER 5
1 1
IRRX IRTX
COMA
(UARTA)
VCC 1 1 1,4 1 1 1 1 1 RTSB# DTRB# SOUTB RIB# CTSB# DSRB# SINB DCDB#
20 16 15 13 19 18 17 14 12 11
U3 VCC DA1 DA2 DA3 RY1 RY2 RY3 RY4 RY5 GND W83778 (SOP20)
+12V DY1 DY2 DY3 RA1 RA2 RA3 RA4 RA9 -12V
1 5 6 8 2 3 4 7 9 10
+12V NRTSB NDTRB NSOUTB NRIB NCTSB NDSRB NSINB NDCDB -12V
NDCDB NSOUTB GND NRTSB NRIB
J3 1 2 3 4 5 6 7 8 9 10 CN2X5B
NSINB NDTRB NDSRB NCTSB
THE IOVSB OF PIN 8 IS FOR CIR WAKE-UP FUNCTION.
COMB
(UARTB)
1
1
PRT PORT
RPACK1 2 4 6 8 33 PD0 PD1 PD2 PD3 1 3 5 7 RPACK2 2 4 6 8 33 PD4 PD5 PD6 PD7 1 3 5 7 RPACK3 2 4 6 8 33 1 1 1 1 1 ERR# ACK# BUSY PE SLCT C4 180 C13 180 C5 180 C14 180 C6 180 C15 180
D1 DIODE RP1 10P9R-2.7K RP2 10P9R-2.7K
VCC
2 3 4 5 6 7 8 9 10
1 1 1 1 1
STB# AFD# INIT# SLIN# PD[0..7] PD[0..7]
1 3 5 7
2 3 4 5 6 7 8 9 10
1 14 2 15 3 16 4 17 5 18 6 19 7 20 8 21 9 22 10 23 11 24 12 25 13
J4
DB25 C7 180 C16 180 C8 180 C17 180 C9 180 C18 180 C10 180 C19 180 C11 180 C20 180 C12 180
WINBOND ELECTRONICS CORP. Title W83697SF Size B Date: Document Number 697SD2.SCH Thursday, August 30, 2001 Sheet 2 of 5 Rev 1.0
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Publication Release Date: Dec 2002 Revision 1.0
W83697SF
GAME & MIDI PORT CIRCUIT
VCC VCC VCC VCC VCC VCC
R4 100K
R5 2.2K
R6 2.2K
R7 2.2K
R8 2.2K
L1 INDUCTOR
P1 R92.2K 1 1 1 1 1 1 1 1 1 1 MSI GPAS2 GPBS2 GPAY GPBY MSO GPAX GPBX GPBS1 GPAS1 R13 2.2K R14 2.2K 8 15 7 14 6 13 5 12 4 11 3 10 2 9 1 PRT
R10 2.2K R11 2.2K R12 2.2K
R15 1M
R16 1M
R17 1M
R18 1M
C21 0.01U C22 0.01U C23 0.01U C24 0.01U C25 0.01U
C26 0.01U
C27 0.01U
C28 0.01U
C29 0.01U
FLASH ROM
U4 1 30 2 3 29 28 4 25 23 26 27 5 6 7 8 9 10 11 12 NC/A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 13 DQ0 14 DQ1 15 DQ2 17 DQ3 18 DQ4 19 DQ5 20 DQ6 21 DQ7 XD0 XD1 XD2 XD3 XD4 XD5 XD6 XD7
R19 XA18 0
1
XA[0..18] XA[0..18] VCC
R20 4.7K
R21 4.7K
R22 4.7K
XA17 XA16 XA15 XA14 XA13 XA12 XA11 XA10 XA9 XA8 XA7 XA6 XA5 XA4 XA3 XA2 XA1 XA0
XD[0..7]
XD[0..7]
1
VCC 32 VCC 16 GND 0.1U
1 1 1
MEMW# MEMR# ROMCS#
31 WE# 24 OE# 22 CE#
W29C020/40 C30
WINBOND ELECTRONICS CORP.
Title W83697SF Size B Document Number 697SD3.SCH 3 of 5 Rev 1.0
Date: Thursday, August 30, 2001 Sheet
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Publication Release Date: Dec 2002 Revision 1.0
W83697SF
PWM Circuit for FAN speed control
+12V R23 4.7K Q1 PNP 3906 +12V R26 510 C31 + Q2 MOSFET N 10u 2N7002 JP3 3 2 1 HEADER 3 +12V 1 Q6 PNP 3906 R25 R27 4.7K 1K Q3 PNP 3906 R28 150 VCC LED C32 Q5 MOSFET N 10u 2N7002 + JP4 3 2 1 HEADER 3 D2 Q4 NPN JP2 1 PWM2 1 2 3 4 HEADER 2X2 This jumper is used selecting Pin115's Funtcion PWM20 PLED R24 1K
1
PWM1
R30 PWM0
510
R31
4.7K
R29 4.7K PLED
R32 1K
PWM20 R33
510
C33 Q7 MOSFET N 10u 2N7002
+
JP5 3 2 1 HEADER 3 5VDD 1 1 1 1 SCPWR SCPWR SCC4 SCC4 SCIO SCIO SCCLK SCCLK R34 0 R35 33 R37 33 1 2 3 4 5
U5 VCC GND PWR RST C4 NC SCIO C8 CLK PSNT SC_CON 6 7 8 9 10 SCRST R36 0
SCRST# SCC8 SCPSNT SCC8 SCPSNT
1 1
C34 10UF
MAIN BOARD SMART CARD CONNECTOR
VCC
D3 LED R38 300 Smart Card Socket Pin assignment Power:c1 Q8 MOSFET P SMART CARD SOCKET c1 c2 c3 c4 RST# CLK SCC4 SCPSNT S/W1 SCINS VCC ON c5 c6 c7 c8 Reset:c2 Clock:c3 c5:GND c6:VPP c7:I/O HEFRAS 1,2 PNPCSV 1,2 PENROM PEN48 1,2 1,2 RTSA# DTRA# SOUTA SOUTB 1 2 3 4 S1 RP3
8 7 6 5
1 3 5 7
2 4 6 8
VCC
PWRCTL#
SW DIP-4
RESP4
RFU :c4 c8:RFU (Reserve for Future Use) IO SCC8 S1 (HEFRAS) 4E S2 (PNPCSV) Clear all default value Using default value S3 (PENROM) Disable ISA ROM Interface Enable ISA ROM Interface S4 (PEN48) Using 48M be IO clk Using 24M be IO clk
C35 1UF
U6 5VDD PWRCTL# SCC4 IO CLK 1 2 3 4 5 VCC GND PWR RST C4 NC SCIO C8 CLK PSNT SC_CON C36 10UF 6 7 8 9 10 RST# SCC8 SCINS R39 10K Winbond Electronic Corp. Note:(SCPSNT S/W) had already built in the Card Socket OFF 2E
Smart Card SOCKET LAYOUT
Title W83697SF Size B Date: Document Number 697SD4.SCH Thursday, August 30, 2001 Sheet 4 of 5 Rev 1.0
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Publication Release Date: Dec 2002 Revision 1.0
W83697SF
697SF DEMO CIRCUIT VERSION CHANG NOTICE
1. 30/8/2001 DEMO CIRCUIT VERSION 1.0 RELEASE
WINBOND ELECTRONICS CORP. Title W83697SF Size B Date: Document Number 697SD5.SCH Thursday, August 30, 2001 Sheet 5 of 5 Rev 0.2
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Publication Release Date: Dec 2002 Revision 1.0

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