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 W24L01 128K x 8 CMOS STATIC RAM
GENERAL DESCRIPTION
The W24L01 is a normal-speed, very low-power CMOS static RAM organized as 131072 x 8 bits that operates on a wide voltage range from 2.3V to 3.3V power supply. The W24L01 family, W24L01-LE and W24L01-LI, can meet the requirement of various operating temperature. This device is manufactured using Winbond's high performance CMOS technology.
FEATURES
*
* * *
Low power consumption: - Active: 132 mW (max.) - Standby: 13.5 W (max.) /2.5V 0.2V 16.5 W (max.) /3.0V 0.3V Access time: 70 nS /100 nS (max.) 2.3V to 3.3V supply voltage Fully static operation
* * * * *
All inputs and outputs directly TTL compatible Three-state outputs Battery back-up operation capability Data retention voltage: 1.5V (min.) Packaged in 32-pin 450 mil SOP, standard type one TSOP (8 mm x 20 mm), small type one TSOP (8 mm x 13.4 mm) and 48-pin CSP
PIN CONFIGURATIONS
NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32-pin SOP 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VDD A1 CS2 WE A1 3 A 8 A9 A1 1 OE A10 CS 1 I/O8 I/O7 I/O6 I/O5 I/O4
BLOCK DIAGRAM
CLK GEN. A16 A14 A12 A4 A3 A2 A7 A6 A5 A9 I/O1 : I/O8 DATA CNTRL. CLK GEN. WE CS1 CS2 OE A15 A13 A8 A1A0A11A10 I/O CKT. COLUMN DECODER D E C O D E R R O W PRECHARGE CKT.
CORE CELL ARRAY 1024 ROWS 128 X 8 COLUMNS
A11 A9 A8 A13 WE CS2 A15 VDD NC A16 A14 A12 A7 A6 A5 A4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27
32-pin TSOP
26 25 24 23 22 21 20 19 18 17
OE A10 CS1 I/O8 I/O7 I/O6 I/O5 I/O4 VSS I/O3 I/O2 I/O1 A0 A1 A2 A3
PIN DESCRIPTION
SYMBOL A0-A16 I/O1-I/O8 CS1, CS2 WE OE VDD VSS NC DESCRIPTION Address Inputs Data Inputs/Outputs Chip Select Input Write Enable Input Output Enable Input Power Supply Ground No Connection
48-pin CSP TOP VIEW
A B C D E F G H 1 A0 I/O5 I/O6 V SS VCC I/O7 I/O8 A9 2 A1 A2 3 CS2 WE NC 4 A3 A4 A5 5 A6 A7 6 A8 I/O1 I/O2 VCC VSS I/O3 I/O4 A14
NC OE A10 CS1 A11
NC A16 A12
A15 A13
-1-
Publication Release Date: January 1999 Revision A5
W24L01
TRUTH TABLE
CS1 H X L L L CS2 X L H H H OE X X H L X WE X X H H L MODE Not Selected Not Selected Output Disable Read Write I/O1-I/O8 High Z High Z High Z Data Out Data In VDD CURRENT ISB, ISB1 ISB, ISB1 IDD IDD IDD
DC CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER Supply Voltage to VSS Potential Input/Output to VSS Potential Allowable Power Dissipation Storage Temperature Operating Temperature LE LI RATING -0.5 to +4.6 -0.5 to VDD +0.5 1.0 -65 to +150 -20 to 85 -40 to 85 UNIT V V W C C C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.
Operating Characteristics
(VDD = 3.0V 0.3V; VDD = 2.5V 0.2V, VSS = 0V; TA (C) = -20 to 85 for LE, -40 to 85 for LI)
PARAMETER Input Low Voltage Input High Voltage Input Leakage Current Output Leakage Current
SYM. VIL VIH ILI ILO
TEST CONDITIONS VIN = VSS to VDD VI/O = VSS to VDD, CS1 = VIH (min.) or CS2 = VIL (max.) or OE = VIH (min.)
MIN. -0.2 +2.2 -1 -1
3.0V TYP.* -
MAX. +0.4 VDD +0.3 +1 +1
MIN. -0.2 +2.0 -1 -1
2.5V TYP.* -
UNIT MAX. +0.4 VDD +0.2 +1 +1 V V A A
Output Low Voltage
VOL
Output Low Voltage
VOH
or WE = VIL (max.) IOL = +2.1 mA, VDD = 3.0V IOL = +0.5 mA, VDD = 2.5V IOH = -1.0 mA, VDD = 3.0V IOH = -0.5 mA, VDD = 2.5V
-
-
0.4
-
-
0.4
V
2.2
-
-
2.0
-
-
V
-2-
W24L01
Operating Characteristics, continued
PARAMETER Operating Power Supply Current
SYM. IDD
TEST CONDITIONS CS1 = VIL (max.) and CS2 = VIH (min.) , I/O = 0 mA, Cycle = min. Duty = 100% CS1 = VIH (min.) or CS2 = VIL (max.), Cycle = min. Duty = 100% CS1 VDD -0.2V or CS2 0.2V MIN. -
3.0V TYP.* MAX. 45 MIN. -
2.5V TYP.* MAX. 25
UNIT mA
Standby Power Supply Current
ISB
-
-
0.3
-
-
0.3
mA
ISB1
-
0.5
5
-
0.5
5
A
Note: Typical parameter is measured under ambient temperature TA = 25 C and VDD = 3.0V /2.5V
CAPACITANCE
(TA = 25 C, f = 1 MHz)
PARAMETER Input Capacitance Input/Output Capacitance
SYM. CIN CI/O
CONDITIONS VIN = 0V VOUT = 0V
MAX. 8 10
UNIT pF pF
Note: These parameters are sampled but not 100% tested.
AC CHARACTERISTICS
AC Test Conditions
PARAMETER Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level Output Load CONDITIONS 0V to 2.2V 5 nS 1.5V, VDD = 3.0V 1.1V, VDD = 2.5V See the drawing below
AC Test Loads and Waveform
1 TTL OUTPUT 100 pF Including Jig and Scope OUTPUT 5 pF Including Jig and Scope (For TCLZ, TOLZ, TCHZ, TOHZ, TWHZ, TOW ) 2.2V 0V 5 nS 90% 10% 90% 10% 5 nS 1 TTL
-3-
Publication Release Date: January 1999 Revision A5
W24L01
AC Characteristics, continued (VDD = 3.0V 0.3V; VDD = 2.5V 0.2V; VSS = 0V; TA (C) = -20 to 85 for LE, -40 to 85 for LI)
Read Cycle
PARAMETER SYM. 3.0V MIN. Read Cycle Time Address Access Time Chip Select Access Time Output Enable to Output Valid Chip Selection to Output in Low Z Output Enable to Output in Low Z Chip Deselection to Output in High Z Output Disable to Output in High Z Output Hold from Address Change
These parameters are sampled but not 100% tested
2.5V MIN. 100 15 5 15 MAX. 100 100 50 35 35 -
UNIT
MAX. 70 70 35 30 30 -
TRC TAA TACS TAOE TCLZ* TOLZ* TCHZ* TOHZ* TOH
70 10 5 10
nS nS nS nS nS nS nS nS nS
Write Cycle
PARAMETER SYM. 3.0V MIN. Write Cycle Time Chip Selection to End of Write Address Valid to End of Write Address Setup Time Write Pulse Width Write Recovery Time
CS1, CS2, WE
2.5V MIN. 100 70 70 0 70 0 50 0 10 MAX. 35 35 -
UNIT
MAX. 25 25 -
TWC TCW TAW TAS TWP TWR TDW TDH TWHZ* TOHZ* TOW
70 60 60 0 55 0 30 0 5
nS nS nS nS nS nS nS nS nS nS nS
Data Valid to End of Write Data Hold from End of Write Write to Output in High Z Output Disable to Output in High Z Output Active from End of Write
These parameters are sampled but not 100% tested
-4-
W24L01
TIMING WAVEFORMS
Read Cycle 1
(Address Controlled)
TRC Address TOH DOUT TAA TOH
Read Cycle 2
(Chip Select Controlled)
CS1
CS2 TACS TCLZ DOUT TCHZ
Read Cycle 3
(Output Enable Controlled)
T RC Address TAA OE TAOE TOLZ CS1 TOH
CS2
TACS DOUT TCLZ
T CHZ
TOHZ
-5-
Publication Release Date: January 1999 Revision A5
W24L01
Timing Waveforms, continued
Write Cycle 1
TWC Address T WR OE
T CW CS1
CS2 T AW WE TAS TOHZ D OUT T DW D IN TDH (1, 4) T WP
Write Cycle 2 (OE = VIL Fixed)
T WC Address TCW CS1 TWR
CS2 TAW WE TAS TWP TWHZ (1, 4) TOH (2) TOW (3)
D OUT
TDW DIN
TDH
Notes: 1. During this period, I/O pins are in the output state, so input signals of opposite phase to the outputs should not be applied. 2. The data output from DOUT are the same as the data written to DIN during the write cycle. 3. DOUT provides the read data for the next address. 4. Transition is measured 500 mV from steady state with CL = 5 pF. This parameter is guaranteed but not 100% tested.
-6-
W24L01
DATA RETENTION CHARACTERISTICS
(TA (C) = -20 to 85 for LE; -40 to 85 for LI)
PARAMETER VDD for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time * Read Cycle Time
SYM. VDR IDDDR TCDR TR
TEST CONDITIONS CS1 VDD -0.2V or CS2 0.2V CS1 VDD -0.2V or CS2 0.2V, VDD = 3V See data retention waveform
MIN. 1.5 0 TRC*
TYP. MAX. UNIT 5 V A nS nS
DATA RETENTION WAVEFORM
VDD
0.9 x VDD TCDR
VDR > 1.5V =
0.9 x V DD TR
CS1
CS1 > V DD - 0.2V =
CS2
0V < CS2 < 0.2V = = V
-7-
Publication Release Date: January 1999 Revision A5
W24L01
ORDERING INFORMATION
PART NO. W24L01B-70LE W24L01Q-70LE W24L01S-70LE W24L01T-70LE W24L01B-70LI W24L01Q-70LI W24L01S-70LI W24L01T-70LI
Notes: 1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure.
ACCESS TIME (nS) 100/70 100/70 100/70 100/70 100/70 100/70 100/70 100/70
OPERATING VOLTAGE (V) 2.5V/3V 2.5V/3V 2.5V/3V 2.5V/3V 2.5V/3V 2.5V/3V 2.5V/3V 2.5V/3V
OPERATING TEMPERATURE (C) -20 to 85 -20 to 85 -20 to 85 -20 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 CSP
PACKAGE
Small type one TSOP 450 mil SOP Standard type one TSOP CSP Small type one TSOP 450 mil SOP Standard type one TSOP
-8-
W24L01
PACKAGE DIMENSIONS
32-pin Small Type One TSOP
HD
Symbol
Dimension in Inches Min. Nom. Max. 0.049 0.002 0.006
Dimension in mm Min. Nom. Max. 1.25 0.05 0.95 0.17 1.00 0.20 0.15 0.15 1.05 0.27 0.16
D c
1
A A1 A2 b c D E HD e L L1
e
E
0.037 0.039 0.041 0.007 0.008 0.009
0.0056 0.0059 0.0062 0.14 0.461
b
0.465 0.469 11.70 11.80 11.90 7.90 8.00 8.10
0.311 0.315 0.319
0.520 0.528 0.536 13.20 13.40 13.60 0.020 0.012 0.020 0.028 0.027 0.000 0 3 0.004 5 0.30 0.675 0.00 0 3 0.10 5 0.50 0.50 0.70
A A
2
Y
Y
L L1
A1
Controlling dimension: Millimeters
32-pin SOP Wide Body
Dimension in Inches Dimension in mm
Symbol
17
Min.
0.004 0.101 0.014 0.006
Nom.
Max.
0.118
Min. Nom.
0.10
Max.
3.00
32
e1
E HE
L
Detail F
1
b
16
A A1 A2 b c D E e HE L LE S y
0.106 0.016 0.008 0.805
0.111 0.020 0.012 0.817 0.450 0.056 0.556 0.039 0.063 0.036 0.004
2.57 0.36 0.15
2.69 0.41 0.20 20.45
2.82 0.51 0.31 20.75 11.43 1.42 14.38 0.99 1.60 0.91 0.10
0.440 0.044 0.546 0.023 0.047
0.445 0.050 0.556 0.031 0.055
11.18 1.12 13.87 0.58 1.19
11.30 1.27 14.12 0.79 1.40
Notes:
D e1 c A2 S y e A1 A
0
10
0
10
LE
1. Dimensions D Max. & S include mold flash or tie bar burrs. 2. Dimension b does not include dambar protrusion/intrusion. 3. Dimensions D & E include mold mismatch . and determined at the mold parting line. 4. Controlling dimension: Inches 5. General appearance spec should be based on final visual inspection spec.
See Detail F
Seating Plane
-9-
Publication Release Date: January 1999 Revision A5
W24L01
Package Dimensions, continued
32-pin Standard Type One TSOP
HD
Symbol
Dimension in Inches Min. Nom. Max. 0.047 0.006 0.041 0.009 0.007
Dimension in mm Min. Nom. Max. 1.20 0.15 1.05 0.23 0.17 18.50 8.10 20.20
D c 1
A A1 A2 b
__
0.002 0.037 0.007
__ __
0.039 0.008
__
0.05 0.95 0.17 0.12
__ __
1.00 0.20 0.15
M
e E
c D E HD e L L1
0.005 0.006 0.720 0.311 0.780 0.724 0.315 0.787 0.020 0.020 0.031
0.10(0.004)
0.728 18.30 18.40 0.319 7.90 8.00 20.00 0.50 0.50 0.80
b
0.795 19.80
__
0.016
__
0.024
__
0.40
__
0.60
__
0.000 1
__
0.004 5
__
0.00 1
__
0.10 5
A A2 L L1 A1
Y
__
3
__
3
Y
Controlling dimension: Millimeters
- 10 -
W24L01
VERSION HISTORY
VERSION A1 A2 A3 DATE Feb. 1998 Apr. 1998 June 1998 PAGE 3 1 DESCRIPTION Initial Issued Add standby power supply current (ISB1) typical parameter when operation temperature TA = 25 C Change supply voltage range: from (2.7V to 3.6V) to (2.3V to 3.3V) Modify power consumption: - Active : 132 mW (max.) - Standby: 13.5 W (max.) /2.5V 0.2 16.5 W (max.) /3.0V 0.3 Correct Operating Characteristics: VIL from (-0.5V to +0.6V) to (-0.2V to +0.4V) VIH (max.) from VDD +0.5V to VDD +0.3V for 3.0V from VDD +0.5V to VDD +0.2V for 2.5V IDD (max.) from 20 mA to 45 mA for 3.0V from 20 mA to 25 mA for 2.5V ISB (max.) from 1 mA to 0.3 mA Modify VOL, VOH test conditions Correct Capacitance: CIN (max.) from 6 pF to 8 pF CI/O (max.) from 8 pF to 10 pF Correct AC Characteristics and AC Test Waveform Input Pulse Levels from (0V to 2.4V) to (0V to 2.2V) Input and Output Timing Reference Level from 1.2V to 1.5V for 3.0V form 1.2V to 1.1V for 2.5V TWHZ*, TOHZ* from 30 nS to 35 nS TCW from 50 nS to 60 nS for 3V TAW from 50 nS to 60 nS for 3V TWP from 50 nS to 55 nS for 3V Correct VDR (min.) from 2.0V to 1.5V Modify Ordering Information: access time (nS) operating voltage(V) -70 2.7V to 3.0V -100 2.3V to 2.7V W24L01-LI operating temperature(C) from -20-85 to -40-85 Add SOP package type Add SOP package pin configuration
2, 3
3
4
7 8
A4 A5
Oct. 1998 Jan. 1999
1, 8, 9 1
- 11 -
Publication Release Date: January 1999 Revision A5
W24L01
Headquarters
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II, No. 4, Creation Rd. III, 123 Hoi Bun Rd., Kwun Tong, Science-Based Industrial Park, Kowloon, Hong Kong Hsinchu, Taiwan TEL: 852-27513100 TEL: 886-3-5770066 FAX: 852-27552064 FAX: 886-3-5796096 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-27197006
Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab.
2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502
Note: All data and specifications are subject to change without notice.
- 12 -


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