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PRELIMINARY
W237
440BX/MX Spread Spectrum Frequency Synthesizer
Features
* Maximized EMI suppression using Cypress's Spread Spectrum technology * Single-chip system frequency synthesizer for Mobile Intel(R) 440BX * Two copies of CPU output * I2CTM interface for programming * Seven copies of PCI output * Two 48/24MHz outputs for USB and SIO * Three buffered reference outputs * Eight buffered SDRAM outputs provide support for 2 DIMMs * Spread Spectrum feature enabled through I2C interface and pin option * Power management control inputs
Key Specifications
CPU Cycle-to-Cycle Jitter:........................................... 250 ps CPU to CPU Output Skew:.......................................... 175 ps PCI to PCI Output Skew: ............................................. 500 ps VDDQ3: ................................................................... 3.3V5% VDDQ2: ................................................................... 2.5V5% SDRAM0:7 Delay: ............................................... +3.7 ns typ. Table 1. Clock Select Table[1] SEL100/66 (MHz) 0 1 CPU,SDRAM (MHz) 66.6 100 PCI (MHz) 33.3 33.3
Block Diagram
I2 C
Pin Configuration [2]
VDDQ3 REF0:2
{SDATA SCLK
I/O PORT Byte 0 - 5 Bit 0 - 7
X1 X2
XTAL OSC
PCI_F
Stop
PCI0:5
SEL100/ 66MHz# SPREAD# BUF_IN
PLL 1
FB
Power Down Logic
PWR_DWN#
/2//3
6
VDDQ3 SDRAM 0:5 SDRAM6/(CPU_STOP#) SDRAM7/(PCI_ST0P#)
MODE
Control Logic
Stop
2
VDDQ2 CPU0:1
REF1 REF0 GND X1 X2 MODE VDDQ3 PCI_F PCI0 GND PCI1 PCI2 PCI3 PCI4 VDDQ3 PCI5 GND *SEL100/66# SDATA I 2C SCLK VDDQ3 48/24MHz0 48/24MHz1 GND
{
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
VDDQ3 SPREAD# VDDQ3 REF2 PWR_DWN#* GND CPU0 CPU1 VDDQ2 BUF_IN FB GND SDRAM0 SDRAM1 VDDQ3 SDRAM2 SDRAM3 GND SDRAM4 SDRAM5 VDDQ3 SDRAM6/(CPU_STOP#)* SDRAM7/(PCI_STOP#)* VDDQ3
W237
PLL2
VDDQ3 48/24MHz0
48/24MHz1
Notes: 1. Mode input latched at power-up. 2. Pin function with parentheses determined by MODE pin logic state. Internal 250-k pull-up resistors present on inputs marked with *. Design should not rely solely on internal resistor to set I/O pins HIGH. Intel is a registered trademark of Intel Corporation. I2C is a trademark of Philips Corporation.
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134 * 408-943-2600 January 7, 2000, rev. **
PRELIMINARY
Pin Definitions
Pin Name CPU0:1 PCI0:5 Pin No. 42, 41 9, 11, 12, 13, 14, 16 8 Pin Type O O Pin Description
W237
CPU Clock Outputs: See Table 1 for detailed frequency information. Output voltage swing is controlled by voltage applied to VDDQ2. PCI Clock Outputs 0 through 5: These six PCI clock outputs are controlled by the PCI_STOP# control pin. Output voltage swing is controlled by voltage applied to VDDQ3. Fixed PCI Clock Output: Unlike PCI0:5 outputs, this output is not controlled by the PCI_STOP# control pin. Output voltage swing is controlled by voltage applied to VDDQ3. Mode Control: This input selects the function of device pin 26 (SDRAM7/PCI_STOP#) and pin 27 (SDRAM6/CPU_STOP#). Refer to description for those pins. Power-Down Control: When this input is LOW, device goes into a low-power condition. All outputs are held LOW while in power-down, CPU and PCI clock outputs are stopped LOW after completing a full clock cycle (2-3 CPU clock cycle latency). When brought HIGH, CPU, SDRAM, and PCI outputs start with a full clock cycle at full operating frequency (3 ms maximum latency). Feedback out Spread#: When LOW, enables spread spectrum clocking. SEL 66- or 100-MHz Input Selection: Selects power-up default CPU clock frequency as shown in Table 1 on page 1 (also determines SDRAM and PCI clock frequency selections). Clock Input: This clock input has an input threshold voltage of 1.5V (typ.). 48-/24-MHz Output: 48/24MHz is provided in normal operation. In standard systems, this output can be used as the reference for the Universal Serial Bus. This output does not have the Spread Spectrum feature. Reference Clock Outputs 0 through 2: This pin provides a fixed clock signal equal in frequency to the reference signal provided at the X1/X2 pins. SDRAM Clock Output 7 or PCI Clock Output Stop Control: This pin has dual functions, selectable by the MODE input pin. When MODE = 0, this pin becomes the PCI_STOP# input. When MODE = 1, this pin becomes SDRAM clock output 7. PCI_STOP# input: When brought LOW, clock outputs PCI0:5 are stopped LOW after completing a full clock cycle. When brought HIGH, clock outputs PCI0:5 are started beginning with a full clock cycle. Clock latency provides one PCI_F rising edge of PCI clock following PCI_STOP# state change. Regarding use as a SDRAM clock: Output voltage swing is controlled by voltage applied to VDDQ3. SDRAM Clock Output 6 or CPU Clock Output Stop Control: This pin has dual functions, selectable by the MODE input pin. When MODE = 0, this pin becomes the CPU_STOP# input. When MODE = 1, this pin becomes SDRAM clock output 6. Regarding use as a CPU_STOP# input: When brought LOW, clock outputs CPU0:1 are stopped LOW after completing a full clock cycle (2-3 CPU clock latency). When brought HIGH, clock outputs CPU0:1 are started beginning with a full clock cycle (2-3 CPU clock latency). Regarding use as a SDRAM clock: Output voltage swing is controlled by voltage applied to VDDQ3. Buffered Outputs: These six dedicated outputs provide copies of the signal provided at the BUF_IN input. The swing is set by VDDQ3. Clock pin for I2C circuitry. Data pin for I2C circuitry. Crystal Connection or External Reference Frequency Input: This pin has dual functions. It can be used as an external 14.318-MHz crystal connection or as an external reference frequency input.
PCI_F
O
MODE
6
I
PWR_DWN#
44
I
FB SPREAD# SEL100/66#
38 47 18
O I I
BUF_IN 48/24MHz0:1
39 22,23
I O
REF0:2 SDRAM7/ PCI_STOP#
2, 1,45 26
O I/O
SDRAM6/CPU_ STOP#
27
I/O
SDRAM0:5 SCLK SDATA X1
36, 35, 33, 32, 30, 29 20 19 4
O I I/O I
2
PRELIMINARY
Pin Definitions (continued)
Pin Name X2 VDDQ3 Pin No. 5 7, 15, 21, 25, 28, 34, 46, 48 40 3, 10, 17, 24, 31, 37, 43 Pin Type I P Pin Description
W237
Crystal Connection: An input connection for an external 14.318-MHz crystal. If using an external reference, this pin must be left unconnected. Power Connection: Power supply for core logic, PLL circuitry, SDRAM outputs, PCI outputs, reference outputs, 48-MHz output, and 24-MHz output. Connect to 3.3V supply. Power Connection: Power supply for CPU0:1 output buffers. Connect to 2.5V supply. Ground Connections: Connect all ground pins to the common system ground plane. Cypress's proprietary spread spectrum frequency synthesis technique is a feature of the CPU and PCI outputs. This feature reduces the peak EMI measurements of not only the output signals and their harmonics, but also of any other clock signals that are properly synchronized to them.
VDDQ2 GND
P G
Overview
The W237 was developed as a single-chip device to meet the clocking needs of the Intel 440BX. In addition to the typical outputs provided by standard 100-MHz 440BX FTGs, the W237 adds eight SDRAM output buffers supporting 2 DIMM modules in conjunction with the chipset.
3
PRELIMINARY
Spread Spectrum Frequency Timing Generator
The device generates a clock that is frequency modulated in order to increase the bandwidth that it occupies. By increasing the bandwidth of the fundamental and its harmonics, the amplitudes of the radiated electromagnetic emissions are reduced. This effect is depicted in Figure 1. As shown in Figure 1, a harmonic of a modulated clock has a much lower amplitude than that of an unmodulated signal. The reduction in amplitude is dependent on the harmonic number and the frequency deviation or spread. The equation for the reduction is: dB = 6.5 + 9*log10(P) + 9*log10(F)
W237
Where P is the percentage of deviation and F is the frequency in MHz where the reduction is measured. The output clock is modulated with a waveform depicted in Figure 2. This waveform, as discussed in "Spread Spectrum Clock Generation for the Reduction of Radiated Emissions" by Bush, Fessler, and Hardin produces the maximum reduction in the amplitude of radiated electromagnetic emissions. The deviation selected for this chip is either -0.25% or 0.5% of the selected frequency. Figure 2 details the Cypress spreading pattern. Cypress does offer options with more spread and greater EMI reduction. Contact your local Sales representative for details on these devices.
EMI Reduction SSFT G Typical Clo ck
A m p litu de (d B)
Am plitud e (dB )
Spread Spectrum Enabled
NonSpread Speactrum
Frequency Span (MHz) Center Spread
Frequency Span (MHz) Down Spread
Figure 1. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation
MAX (+0.5%)
FREQUENCY
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
10%
20%
30%
40%
50%
60%
70%
80%
90%
MIN (- 0.5%)
Figure 2. Modulation Waveform Profile
4
100%
PRELIMINARY
Serial Data Interface
The W237 features a two-pin, serial data interface that can be used to configure internal register settings that control particular device functions. Upon power-up, the W237 initializes with default register settings, therefore the use of this serial data interface is optional. The serial interface is write-only (to the clock chip) and is the dedicated function of device pins SDATA and SCLK. In motherboard applications, SDATA and SCLK are typically driven by two logic outputs of the chipset. Clock deTable 2. Serial Data Interface Control Functions Summary Control Function Clock Output Disable Description Common Application
W237
vice register changes are normally made upon system initialization, if any are required. The interface can also be used during system operation for power management functions. Table 2 summarizes the control functions of the serial data interface. Operation Data is written to the W237 in ten bytes of eight bits each. Bytes are written in the order shown in Table 3.
Any individual clock output(s) can be disabled. Dis- Unused outputs are disabled to reduce EMI abled outputs are actively held LOW. and system power. Examples are clock outputs to unused PCI slots. Provides CPU/PCI frequency selections through software. Frequency is changed in a smooth and controlled fashion. Enables or disables spread spectrum clocking. Puts clock output into a high-impedance state. For alternate microprocessors and power management options. Smooth frequency transition allows CPU frequency change under normal system operation. For EMI reduction. Production PCB testing.
CPU Clock Frequency Selection
Spread Spectrum Enabling Output Three-state (Reserved)
Reserved function for future device revision or pro- No user application. Register bit must be writduction device testing. ten as 0.
Table 3. Byte Writing Sequence Byte Sequence 1 Byte Name Slave Address Bit Sequence 11010010 Byte Description Commands the W237 to accept the bits in Data Bytes 0-6 for internal register configuration. Since other devices may exist on the same common serial data bus, it is necessary to have a specific slave address for each potential receiver. The slave receiver address for the W237 is 11010010. Register setting will not be made if the Slave Address is not correct (or is for an alternate slave receiver). Unused by the W237, therefore bit values are ignored ("don't care"). This byte must be included in the data write sequence to maintain proper byte allocation. The Command Code Byte is part of the standard serial communication protocol and may be used when writing to another addressed slave receiver on the serial data bus. Unused by the W237, therefore bit values are ignored ("don't care"). This byte must be included in the data write sequence to maintain proper byte allocation. The Byte Count Byte is part of the standard serial communication protocol and may be used when writing to another addressed slave receiver on the serial data bus. The data bits in Data Bytes 0-7 set internal W237 registers that control device operation. The data bits are only accepted when the Address Byte bit sequence is 11010010, as noted above. For description of bit control functions, refer to Table 4, Data Byte Serial Configuration Map.
2
Command Code
Don't Care
3
Byte Count
Don't Care
4 5 6 7 8 9 10
Data Byte 0 Data Byte 1 Data Byte 2 Data Byte 3 Data Byte 4 Data Byte 5 Data Byte 6
Refer to Table 4
5
PRELIMINARY
Writing Data Bytes Each bit in Data Bytes 0-7 controls a particular device function except for the "reserved" bits, which must be written as a logic 0. Bits are written MSB (most significant bit) first, which is bit Table 4. Data Bytes 0-7 Serial Configuration Map Affected Pin Bit(s) 7 6 5 4 3 2 1-0 23 22 -48/24MHZ1 48/24MHZ0 -Pin No. --47 Pin Name --SPREAD# (Reserved) (Reserved) Spread Spectrum Control Spread Spectrum Control Spreading 48/24MHZ1 Frequency Select 48/24MHZ0 Frequency Select Bit 1 0 0 1 1 Bit 0 0 1 0 1 Center Spread 0.5% 24 MHz 24 MHz Down Spread -0.25% 48 MHz 48 MHz Control Function 0 -Data Byte 0 -Bit Control 1
W237
7. Table 4 gives the bit formats for registers located in Data Bytes 0-7. Table 5 details the select functions for Byte 0, bits 1 and 0.
Default 0 0 1 0 1 1 00
Function (See Table 5 for function details) Normal Operation Test Mode Spread Spectrum Enable All Outputs Three-stated Low Low ----Low Low -Low Low Low Low Low Low Low Low Low Low Low Low Low Active Active ----Active Active -Active Active Active Active Active Active Active Active Active Active Active Active Active
Data Byte 1 7 6 5 4 3 2 1 0 Data Byte 2 7 6 5 4 3 2 1 0 Data Byte 3 7 6 5 4 3 2 26 27 29 30 32 33 SDRAM7 SDRAM6 SDRAM5 SDRAM4 SDRAM3 SDRAM2 Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable 1 1 1 1 1 1 -8 16 14 13 12 11 9 -PCI_F PCI5 PCI4 PCI3 PCI2 PCI1 PCI0 (Reserved) Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable 0 1 1 1 1 1 1 1 23 22 ----41 42 48/24MHZ1 48/24MHZ0 ----CPU1 CPU0 Clock Output Disable Clock Output Disable (Reserved) (Reserved) (Reserved) (Reserved) Clock Output Disable Clock Output Disable 1 1 0 0 0 0 1 1
6
PRELIMINARY
Table 4. Data Bytes 0-7 Serial Configuration Map (continued) Affected Pin Bit(s) 1 0 Data Byte 4 7 6 5 4 3 2 1 0 Data Byte 5 7 6 5 4 3 2 1 0 Data Byte 6 7 6 5 4 3 2 1 0 ----------------(Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) ---------------------45 1 2 -----REF2 REF1 REF0 (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) Clock Output Disable Clock Output Disable Clock Output Disable -----Low Low Low -----Active Active Active ----------------(Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) ----------------Pin No. 35 36 Pin Name SDRAM1 SDRAM0 Control Function Clock Output Disable Clock Output Disable 0 Low Low Bit Control 1 Active Active
W237
Default 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0
Table 5. Select Function for Data Byte 0, Bits 0:1 Input Conditions Data Byte 0 Function Three-state Testmode Bit 1 1 0 Bit 0 1 1 CPU0:1 HI-Z TCLK/2
[3]
Output Conditions PCI_F, PCI1:5 HI-Z TCLK/4
[3]
SDRAM HI-Z TCLK/2
[3]
REF0:1, HI-Z TCLK
[3]
24MHZ HI-Z TCLK/4
[3]
48MHZ HI-Z TCLK/2[3]
Note: 3. TCLK is a test clock driven on the X1 (crystal) input during test mode.
7
PRELIMINARY
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions
.
W237
above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. Rating -0.5 to +7.0 -65 to +150 -55 to +125 0 to +70 2 (min.) Unit V C C C kV
Parameter VDD, VIN TSTG TB TA ESDPROT
Description Voltage on any pin with respect to GND Storage Temperature Ambient Temperature under Bias Operating Temperature Input ESD Protection
DC Electrical Characteristics: TA = 0C to +70C, VDDQ3 = 3.3V5%, VDDQ2 = 2.5V5%
Parameter Supply Current IDD IDD 3.3V Supply Current 2.5V Supply Current CPU0:1 =100 MHz[4] CPU0:1 =100 MHz[4] GND - 0.3 2.0 260 25 0.8 VDD + 0.3 -25 10 IOL = 1 mA IOH = -1 mA CPU0:1, IOAPIC CPU0:1 IOAPIC REF0:1 48MHz 24MHz IOH Output High Current CPU0:1 IOAPIC REF0:1 48MHz 24MHz IOH = -1 mA VOL = 1.25V VOL = 1.25V VOL = 1.5V VOL = 1.5V VOL = 1.5V VOH = 1.25V VOH = 1.25V VOH = 1.5V VOH = 1.5V VOH = 1.5V 3.1 2.2 27 20.5 40 25 25 25 25 31 40 27 27 25 57 53 85 37 37 37 55 55 87 44 44 37 97 139 140 76 76 76 97 139 155 94 94 76 50 mA mA V V A A mV V V mA mA mA mA mA mA mA mA mA mA mA mA Description Test Condition Min. Typ. Max. Unit
Logic Inputs (All referenced to VDDQ3 = 3.3V) Input Low Voltage VIL VIH IIL IIH VOL VOH VOH IOL Input High Voltage Input Low Current[5] Input High Current[5] Output Low Voltage Output High Voltage Output High Voltage Output Low Current:
Clock Outputs
PCI_F, PCI1:5 VOL = 1.5V
PCI_F, PCI1:5 VOH = 1.5V
Notes: 4. All clock outputs loaded with 6" 60 transmission lines with 22-pF capacitors. 5. W237 logic inputs have internal pull-up devices (pull-ups not full CMOS level).
8
PRELIMINARY
DC Electrical Characteristics: TA = 0C to +70C, VDDQ3 = 3.3V5%, VDDQ2 = 2.5V5% (continued)
Parameter Crystal Oscillator VTH CLOAD CIN,X1 CIN COUT LIN X1 Input Threshold Voltage[6] Load Capacitance, Imposed on External Crystal[7] X1 Input Capacitance[8] Input Pin Capacitance Output Pin Capacitance Input Pin Inductance Pin X2 unconnected Except X1 and X2 VDDQ3 = 3.3V 1.65 14 28 5 6 7 Description Test Condition Min. Typ. Max.
W237
Unit V pF pF pF pF nH
Pin Capacitance/Inductance
AC Electrical Characteristics
TA = 0C to +70C, VDDQ3 = 3.3V5%, V DDQ2 = 2.5V 5%, fXTL = 14.31818 MHz AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock output; Spread Spectrum clocking is disabled. CPU Clock Outputs, CPU0:1 (Lump Capacitance Test Load = 20 pF) CPU = 66.6 MHz Parameter tP tH tL tR tF tD tJC Description Period High Time Low Time Output Fall Edge Rate Duty Cycle Jitter, Cycle-to-Cycle Test Condition/Comments Measured on rising edge at 1.25V Duration of clock cycle above 2.0V Duration of clock cycle below 0.4V Measured from 2.0V to 0.4V Measured on rising and falling edge at 1.25V Measured on rising edge at 1.25V. Maximum difference of cycle time between two adjacent cycles. Measured on rising edge at 1.25V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 20 15 5.6 5.3 1 1 45 4 4 55 250 15.5 CPU = 100 MHz Typ. Max. Unit 10.5 ns ns ns 4 4 55 250 V/ns V/ns % ps 10 3 2.8 1 1 45 Min. Typ. Max. Min.
Output Rise Edge Rate Measured from 0.4V to 2.0V
tSK fST
Output Skew Frequency Stabilization from Power-up (cold start) AC Output Impedance
175 3
175 3
ps ms
Zo
20
Notes: 6. X1 input threshold voltage (typical) is VDD/2. 7. The W237 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is 14 pF; this includes typical stray capacitance of short PCB traces to crystal. 8. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected).
9
PRELIMINARY
SDRAM Clock Outputs, SDRAM, SDRAM0:7 (Lump Capacitance Test Load = 30 pF) CPU = 66.6 MHz Parameter tP tH tL tR tF tPLH tPHL tD tSK Zo Description Period High Time Low Time Test Condition/Comments Measured on rising edge at 1.5V Duration of clock cycle above 2.4V, at min. edge rate (1.5 V/ns) Duration of clock cycle below 0.4V, at min. edge rate (1.5 V/ns) Measured from 2.4V to 0.4V Input edge rate faster than 1 V/ns Input edge rate faster than 1 V/ns Measured on rising and falling edge at 1.5V, at min. edge rate (1.5 V/ns) Measured on rising edge at 1.5V Average value during switching transition. Used for determining series termination value. 30 15 5.6 5.3 1.5 1.5 1 1 45 4 4 5 5 55 250 30 15.5
W237
CPU = 100 MHz Typ. Max. Unit 15.5 ns ns ns 4 4 5 5 55 250 V/ns V/ns ns ns % ps 10 3.3 3.1 1.5 1.5 1 1 45
Min. Typ. Max. Min.
Output Rise Edge Rate Measured from 0.4V to 2.4V Output Fall Edge Rate Prop Delay LH Prop Delay HL Duty Cycle Output Skew AC Output Impedance
PCI Clock Outputs, PCI_F and PCI0:5 (Lump Capacitance Test Load = 30 pF) CPU = 66.6/100 MHz Parameter tP tH tL tR tF tD tJC tSK tO fST Description Period High Time Low Time Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Jitter, Cycle-to-Cycle Output Skew CPU to PCI Clock Skew Frequency Stabilization from Power-up (cold start) AC Output Impedance Test Condition/Comments Measured on rising edge at 1.5V Duration of clock cycle above 2.4V Duration of clock cycle below 0.4V Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. Measured on rising edge at 1.5V Covers all CPU/PCI outputs. Measured on rising edge at 1.5V. CPU leads PCI output. Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 30 1.5 Min. 30 12 12 1 1 45 4 4 55 250 500 4 3 Typ. Max. Unit ns ns ns V/ns V/ns % ps ps ns ms
Zo
10
PRELIMINARY
REF0:1 Clock Output (Lump Capacitance Test Load = 20 pF) CPU = 66.6/100 MHz Parameter f tR tF tD fST Description Frequency, Actual Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Frequency Stabilization from Power-up (cold start) AC Output Impedance Test Condition/Comments Frequency generated by crystal oscillator Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 40 0.5 0.5 45 Min. Typ. 14.318 2 2 55 3 Max.
W237
Unit MHz V/ns V/ns % ms
Zo
48-MHZ Clock Output (Lump Capacitance Test Load = 20 pF) CPU = 66.6/100 MHz Parameter f fD m/n tR tF tD fST Description Frequency, Actual Deviation from 48 MHz PLL Ratio Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Frequency Stabilization from Power-up (cold start) AC Output Impedance Test Condition/Comments Determined by PLL divider ratio (see m/n below) (48.008 - 48)/48 (14.31818 MHz x 57/17 = 48.008 MHz) Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 40 0.5 0.5 45 Min. Typ. 48.008 +167 57/17 2 2 55 3 V/ns V/ns % ms Max. Unit MHz ppm
Zo
24-MHZ Clock Output (Lump Capacitance Test Load = 20 pF) CPU = 66.6/100 MHz Parameter f fD m/n tR tF tD fST Description Frequency, Actual Deviation from 24 MHz PLL Ratio Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Frequency Stabilization from Power-up (cold start) AC Output Impedance Test Condition/Comments Determined by PLL divider ratio (see m/n below) (24.004 - 24)/24 (14.31818 MHz x 57/34 = 24.004 MHz) Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 40 0.5 0.5 45 Min. Typ. 24.004 +167 57/34 2 2 55 3 V/ns V/ns % ms Max. Unit MHz ppm
Zo
Ordering Information
Ordering Code W237 Document #: 38-00868 Package Name X Package Type 48-pin TSSOP (240 mils)
11
PRELIMINARY
Layout Example
W237
+3.3V Supply FB
VDDQ3
+2.5V Supply FB
VDDQ2
10 F 10 F
C4
0.005 F
C3
C1 G
0.005 F
C2 G G
G
G
G
G
VDDQ3
5
C5 G
G C6
1G 2 3G 4 5 6G 7V 8G 9 10 G 11 12 13 14 G 15 V 16 G 17 G 18 19 20 G 21 22 23 24 G
48 47 VDDQ3 V 46 Core G 45 44 G 43 42 G 41 V 40 G 39 38 G 37 36 G 35 V 34 G 33 32 G 31 30 29 V 28 G 27 G 26 V 25
V G
G
G C1
C2
G
FB = Dale ILB1206 - 300 (300 @ 100 MHz) C1 & C3 = 10-22 F C2 & C4 = 0.005 F C5 = 47 F C6 = 0.1 F V =VIA to respective supply plane trace
G = VIA to GND plane layer
Note: Each supply plane or strip should have a ferrite bead and capacitors
All VDD by pass capacitors = 0.1 F
W 237
G
G
G
12
PRELIMINARY
Package Diagram
48-Pin Thin Shrink Small Outline Package (TSSOP, 240 mils)
W237
(c) Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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