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| W182 Full Feature Peak Reducing EMI Solution Features * Cypress PREMISTM family offering * Generates an EMI optimized clocking signal at the output * Selectable output frequency range * Single -1.25% or -3.75% down spread output * Integrated loop filter components * Operates with a 3.3 or 5V supply * Low power CMOS design * Available in 14-pin SOIC (Small Outline Integrated Circuit) Table 1. Modulation Width Selection SS% 0 1 Output Fin Fout Fin - 1.25% Fin Fout Fin - 3.75% Table 2. Frequency Range Selection FS2 0 0 1 1 FS1 0 1 0 1 Frequency Range 8 MHz FIN 10 MHz 10 MHz FIN 15 MHz 15 MHz FIN 18 MHz 18 MHz FIN 28 MHz Key Specifications Supply Voltages: .........................................VDD = 3.3V0.3V or VDD = 5V10% Frequency Range: .............................. 8 MHz Fin 28 MHz Cycle to Cycle Jitter: ......................................... 300 ps (max) Selectable Spread Percentage: ................-1.25% or -3.75% Output Duty Cycle: ............................... 40/60% (worst case) Output Rise and Fall Time: ................................... 5 ns (max) Simplified Block Diagram 3.3V or 5.0V Pin Configuration SOIC FS2 CLKIN or X1 NC or X2 GND GND SS% FS1 1 2 3 4 5 6 14 13 12 11 10 9 8 REFOUT OE# SSON# Reset VDD VDD CLKOUT X1 XTAL Input W182 X2 W182 Spread Spectrum Output (EMI suppressed) 7 3.3V or 5.0V Oscillator or Reference Input W182 Spread Spectrum Output (EMI suppressed) PREMIS is a trademark of Cypress Semiconductor Corporation. Cypress Semiconductor Corporation * 3901 North First Street * San Jose * CA 95134 * 408-943-2600 September 28 1999, rev. ** W182: 6/99 Revision: September 28, 1999 W182 Pin Definitions Pin Name CLKOUT REFOUT Pin No. 8 14 Pin Type O O Pin Description Output Modulated Frequency: Frequency modulated copy of the input clock (SSON# asserted). Non-Modulated Output: This pin provides a copy of the reference frequency. This output will not have the Spread Spectrum feature enabled regardless of the state of logic input SSON#. Crystal Connection or External Reference Frequency Input: This pin has dual functions. It may either be connected to an external crystal, or to an external reference clock. Crystal Connection: Input connection for an external crystal. If using an external reference, this pin must be left unconnected. Spread Spectrum Control (Active LOW): Asserting this signal (active LOW) turns the internal modulation waveform on. This pin has an internal pull-down resistor. Modulation Width Selection: When Spread Spectrum feature is turned on, this pin is used to select the amount of variation and peak EMI reduction that is desired on the output signal. Output Enable (Active LOW): When this pin is held HIGH, the output buffers are placed in a high-impedance mode. Modulation Profile Restart: A rising edge on this input restarts the modulation pattern at the beginning of its defined path. Frequency Selection Bit(s): These pins select the frequency range of operation. Refer to Table 2. These pins have internal pull-up resistors. Power Connection: Connected to 3.3V or 5V power supply. Ground Connection: Connect all ground pins to the common ground plane. CLKIN or X1 2 I NC or X2 SSON# 3 12 I I SS% 6 I OE# Reset FS1:2 VDD GND 13 11 7, 1 9,10 4,5 I I I P G 2 W182: 6/99 Revision: September 28, 1999 W182 Overview The W182 product is one of a series of devices in the Cypress PREMIS family. The PREMIS family incorporates the latest advances in PLL spread spectrum frequency synthesizer techniques. By frequency modulating the output with a low-frequency carrier, peak EMI is greatly reduced. Use of this technology allows systems to pass increasingly difficult EMI testing without resorting to costly shielding or redesign. In a system, not only is EMI reduced in the various clock lines, but also in all signals which are synchronized to the clock. Therefore, the benefits of using this technology increase with the number of address and data lines in the system. The Simplified Block Diagram shows a simple implementation. times the reference frequency. (Note: For the W182 the output frequency is nominally equal to the input frequency.) The unique feature of the Spread Spectrum Frequency Timing Generator is that a modulating waveform is superimposed at the input to the VCO. This causes the VCO output to be slowly swept across a predetermined frequency band. Because the modulating frequency is typically 1000 times slower than the fundamental clock, the spread spectrum process has little impact on system performance. Frequency Selection With SSFTG In Spread Spectrum Frequency Timing Generation, EMI reduction depends on the shape, modulation percentage, and frequency of the modulating waveform. While the shape and frequency of the modulating waveform are fixed for a given frequency, the modulation percentage may be varied. Using frequency select bits (FS2:1 pins), the frequency range can be set (see Table 2). Spreading percentage is set with pin SS% as shown in Table 1. A larger spreading percentage improves EMI reduction. However, large spread percentages may either exceed system maximum frequency ratings or lower the average frequency to a point where performance is affected. For these reasons, spreading percentage options are provided. Functional Description The W182 uses a phase-locked loop (PLL) to frequency modulate an input clock. The result is an output clock whose frequency is slowly swept over a narrow band near the input signal. The basic circuit topology is shown in Figure 1. The input reference signal is divided by Q and fed to the phase detector. A signal from the VCO is divided by P and fed back to the phase detector also. The PLL will force the frequency of the VCO output signal to change until the divided output signal and the divided reference signal match at the phase detector input. The output frequency is then equal to the ratio of P/Q VDD Clock Input Freq. Divider Q Phase Detector Charge Pump Reference Input VCO Post Dividers CLKOUT (EMI suppressed) Modulating Waveform Feedback Divider P PLL GND Figure 1. Functional Block Diagram 3 W182: 6/99 Revision: September 28, 1999 W182 Spread Spectrum Frequency Timing Generation The benefits of using Spread Spectrum Frequency Timing Generation are depicted in Figure 2. An EMI emission profile of a clock harmonic is shown. Contrast the typical clock EMI with the Cypress Spread Spectrum Frequency Timing Generation EMI. Notice the spike in the typical clock. This spike can make systems fail quasi-peak EMI testing. The FCC and other regulatory agencies test for peak emissions. With spread spectrum enabled, the peak energy is much lower (at least 8 dB) because the energy is spread out across a wider bandwidth. Modulating Waveform The shape of the modulating waveform is critical to EMI reduction. The modulation scheme used to accomplish the maximum reduction in EMI is shown in Figure 3. The period of the modulation is shown as a percentage of the period length along the X axis. The amount that the frequency is varied is shown along the Y axis, also shown as a percentage of the total frequency spread. Cypress frequency selection tables express the modulation percentage in two ways. The first method displays the spreading frequency band as a percent of the programmed average output frequency, symmetric about the programmed average frequency. This method is always shown using the expression fCenter XMOD% in the frequency spread selection table. The second approach is to specify the maximum operating frequency and the spreading band as a percentage of this frequency. The output signal is swept from the lower edge of the band to the maximum frequency. The expression for this approach is fMAX - XMOD%. Whenever this expression is used, Cypress has taken care to ensure that fMAX will never be exceeded. This is important in applications where the clock drives components with tight maximum clock speed specifications. Spread Spectrum Enabled NonSpread Spectrum EMI Reduction Figure 2. Typical Clock and SSFTG Comparison SSON# Pin An internal pull-down resistor defaults the chip into spread spectrum mode. When the SSON# pin is asserted (active LOW) the spreading feature is enabled. Spreading feature is disabled when SSON# is set HIGH (VDD). 100% 80% 60% 40% 20% 0% -20% -40% -60% -80% -100% Frequency Shift 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% 10% 20% 30% 40% 50% 60% 70% 80% 90% Time Figure 3. Modulation Waveform Profile 4 100% W182: 6/99 Revision: September 28, 1999 W182 Absolute Maximum Ratings Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions . above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. Rating -0.5 to +7.0 -65 to +150 0 to +70 -55 to +125 0.5 Unit V C C C W Parameter VDD, VIN TSTG TA TB PD Description Voltage on any pin with respect to GND Storage Temperature Operating Temperature Ambient Temperature under Bias Power Dissipation DC Electrical Characteristics: 0C < TA < 70C, VDD = 3.3V 0.3V Parameter IDD tON VIL VIH VOL VOH IIL IIH IOL IOH CI RP ZOUT Description Supply Current Power Up Time Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input Low Current Input High Current Output Low Current Output High Current Input Capacitance Input Pull-Up Resistor Clock Output Impedance 500 25 Note 1 Note 1 @ 0.4V, VDD = 3.3V @ 2.4V, VDD = 3.3V 15 15 7 2.4 -50 50 2.4 0.4 First locked clock cycle after Power Good Test Condition Min Typ 18 Max 32 5 0.8 Unit mA ms V V V V A A mA mA pF k Note: 1. Inputs FS2:1 have a pull-up resistor; Input SSON# has a pull-down resistor. 5 W182: 6/99 Revision: September 28, 1999 W182 DC Electrical Characteristics: 0C < TA < 70C, VDD = 5V 10% Parameter IDD tON VIL VIH VOL VOH IIL IIH IOL IOH CI RP ZOUT Description Supply Current Power Up Time Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input Low Current Input High Current Output Low Current Output High Current Input Capacitance Input Pull-Up Resistor Clock Output Impedance 500 25 Note 2 Note 2 @ 0.4V, VDD = 5V @ 2.4V, VDD = 5V 24 24 7 2.4 -50 50 0.7VDD 0.4 First locked clock cycle after Power Good Test Condition Min Typ 30 Max 50 5 0.15VDD Unit mA ms V V V V A A mA mA pF k AC Electrical Characteristics: TA = 0C to +70C, VDD = 3.3V 0.3V or 5V10% Symbol fIN fOUT tR tF tOD tID tJCYC Parameter Input Frequency Output Frequency Output Rise Time Output Fall Time Output Duty Cycle Input Duty Cycle Jitter, Cycle-to-Cycle Harmonic Reduction fout = 20 MHz, third harmonic measured, reference board, 15-pF load 8 Test Condition Input Clock Spread Off 15-pF load, 0.8V-2.4V 15-pF load, 2.4 -0.8V 15-pF load 40 40 250 Min 8 8 2 2 Typ Max 28 28 5 5 60 60 300 Unit MHz MHz ns ns % % ps dB Note: 2. Inputs FS1:2 have a pull-up resistor; Input SSON# has a pull-down resistor. 6 W182: 6/99 Revision: September 28, 1999 W182 Application Information Recommended Circuit Configuration For optimum performance in system applications the power supply decoupling scheme shown in Figure 4 should be used. VDD decoupling is important to both reduce phase jitter and EMI radiation. The 0.1-F decoupling capacitor should be placed as close to the VDD pin as possible, otherwise the increased trace inductance will negate its decoupling capability. The 10-F decoupling capacitor shown should be a tantalum type. For further EMI protection, the VDD connection can be made via a ferrite bead, as shown. Recommended Board Layout Figure 5 shows a recommended a 2-layer board layout. Xtal Connection or Reference Input Xtal Connection or NC GND 1 2 3 4 5 6 7 W182 14 13 12 11 10 9 8 R1 Clock Output C1 0.1 F C3 0.1F 3.3V or 5V System Supply FB C2 10 F Tantalum Figure 4. Recommended Circuit Configuration C1, C3 = High-frequency supply decoupling capacitor (0.1-F recommended). C2 = Common supply low frequency decoupling capacitor (10-F tantalum recommended). R1 = Match value to line impedance Xtal Connection or Reference Input Xtal Connection or NC FB = Ferrite Bead = Via To GND Plane G G C3 G C1 G G Clock Output R1 G Power Supply Input (3.3V or 5V) FB C2 Figure 5. Recommended Board Layout (2-Layer Board) Ordering Information Ordering Code W182 Document #: 38-00789 Package Name G Package Type 14-Pin Plastic SOIC (150-mil) 7 W182: 6/99 Revision: September 28, 1999 W182 Package Diagram 14-Pin Small Outline Integrated Circuit (SOIC, 150-mil) (c) Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. |
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