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TLK2201 Serdes EVM Kit Setup and Usage
User's Guide
July 2000
Mixed Signal DSP Solutions
SLLU011
IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 2000, Texas Instruments Incorporated
How to Use This Manual
Preface
Read This First
About This Manual
The Texas Instruments TLK2201 Serdes evaluation module (EVM) board is used to evaluate the TLK2201 device(VQFP) and associated optical interface (GBIC Module) for point-to-point data transmission applications. The board enables the designer to connect 50- parallel buses to both transmitter and receiver connectors. Using high speed PLL technology, the TLK2201 serializes and transmits data along one differential pair. The receiver part of the device deserializes and presents data on the parallel bus. The highspeed (up to 1.6 Gbps) data lines interface to four 50- controlled-impedance SMA connectors. The designer can either use this copper interface or, with small solder modifications, send the high-speed data to a GBIC-compatible laser module for an optical interface (not provided).
How to Use This Manual
This document contains the following chapters: Chapter 1 - Introduction Chapter 2 -Typical Test and Setup Configurations Appendix A - Schematics, Board Layouts, and GBIC Configuration
Read This First
iii
iv
Running Title--Attribute Reference
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.1 TLK2201 EVM Kit Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2 TLK2201 EVM Board Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Test and Setup Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.1 Typical Test and Setup Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2 PCB Construction and Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 Schematics, Board Layouts, and GBIC Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
2
A
Figures
2-1 2-2 2-3 2-4 A-1 A-2 A-3 A-4 A-5 A-6 A-7 TLK2201 External Serial Loopback Test Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TLK2201EVM Serial PRBS Self-Test Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TLK2201EVM Serial PRBS BERT Test Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TLK2201EVM Layer Construction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TLK2201EVM Transceiver Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Optical Transceiver Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Top Layer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND Layers 2 and 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Plane Layer 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GBIC and JTAG Layer 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bottom Layer 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2-3 2-4 2-5 A-2 A-3 A-5 A-6 A-7 A-8 A-9
Tables
1-1 1-2 A-1 Default Transceiver-Board Configuration as Shipped . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 Configuration Changes Necessary for DC Coupling of the High-Speed Signals . . . . . . . . 1-4 TLK2201EVM Transceiver Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-4
Contents
v
vi
Chapter 1
Introduction
The Texas Instruments (TI) TLK2201 Serdes evaluation module (EVM) board is used to evaluate the TLK2201 device (VQFP) and associated optical interface (gigabit interface connector (GBIC) optics module) for point-to-point data transmission applications. The board enables the designer to connect 50- parallel buses to both the transmitter and receiver parallel connectors. Using high speed PLL technology, the TLK2201 serializes data and transmits this data along a differential pair. The receiver part of the device deserializes and presents the data on the parallel bus. For proper use of this device, users must provide dc-balanced encoded data on the parallel bus (that is, 8b/10b). The high-speed (up to 1.6 Gbps) data lines interface to four 50- controlled-impedance SMA connectors. The designer can either use this copper interface directly or use steering resistors to direct the high-speed side to the 75- GBIC-compatible optical interface. The board can be used to evaluate device parameters while acting as a guide for high-speed board layout. The evaluation board can be used as daughterboards that are plugged into new or existing designs. Since the TLK2201 operates over a wide range of frequencies, the designer will need to optimize the design for the frequency of interest. Additionally, the designer may wish to use buried transmission lines and provide additional noise attenuation and EMI suppression to optimize the end product.
Topic
1.1 1.2
Page
TLK2201 EVM Kit Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 TLK2201 EVM Board Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
Introduction
1-1
TLK2201 EVM Kit Contents
As the frequency of operation increases, the board designer must take special care to ensure that the highest signal integrity is maintained. To achieve this, the board's impedance is controlled to 50 (75 for the GBIC interface) for both the high-speed differential serial and parallel data connections. In addition, board impedance mismatches are reduced by designing the component pad size to be as close as possible to the width of the connecting transmission lines. Vias are minimized and, when necessary, placed as close as possible to the device drivers. Since the board contains both serial and parallel transmission lines, care was taken to control both impedance and trace-length mismatch (board skew). Overall, the board layout is designed and optimized to support high-speed operation. Thus, understanding impedance control and transmission-line effects is crucial when designing high-speed boards. Some of the advanced features offered by this board include:
-
PCB (printed-circuit board) is designed for high-speed signal integrity. Flexibility-the PCB can be configured for copper or optical interfaces. SMA and parallel fixtures are easily connected to test equipment. All input/output signals are accessible for rapid prototyping. Analog and digital power planes can be supplied through separate banana jacks for isolation, or can be combined using ferrite bridging networks. Series termination resistors provide parallel RD outputs. Onboard capacitors provide ac coupling of high-speed signals.
1.1 TLK2201 EVM Kit Contents
TLK2201 EVM board (TLK2201 Rev 1.0) TLK2201 EVM kit documentation (this document)
1.2 TLK2201 EVM Board Configuration
The TLK2201 EVM board gives the developer various options for operation, many of which are jumper-selectable. Other options can be either soldered into the EVM or connected through input connectors. The TX and RX parallel connectors, P3 and P5 of Figures A-8 and A-10 in Appendix A, provide a connection for both transmitted and received paralleldata busing. The reference clock is supplied through SMA connector J11, and jumper J10 must be installed between pins 1 and 2. A direct clock connection can also be made to J10 between the center and ground pins. The high-speed serial data is transmitted through SMA connectors J1 and J2. The received recovered clock (RBC0 and RBC1) is output through header P5. Received data connects through SMA connectors J3 and J4 on the RX side of the board. Header J9 provides static signals (normally pulled high) to configure the device for different modes of operation. Header J7 is for the optical transceiver's configuration and error checking. Refer to your specific GBIC-module documentation for proper configuration of this header.
1-2
TLK2201 EVM Board Configuration
The power planes are split three ways to provide power to different parts of the board. This prevents coupling of switching noise between the analog and digital sections of the TLK2201, and provides voltage isolation for the laser section. The laser section of the board requires 5 V (GBIC-dependent) and is energized through the VCC connector. The VDD and VDDA connectors require 2.5 V and are joined together by removable jumpers TP1 and TP3 that are installed in the default configuration. Thus, only the VDD connection is necessary to energize the TLK2201 device in the default configuration. In all sections of the board, the ground planes are common and each ground plane is tied together at every component ground connection. See Appendix A, Schematics, Board Layouts, and BGIC Configurations, for detailed schematic and layout. The board is normally delivered in a default configuration that requires external clock and data inputs. The TLK2201 is shipped with jumpers for default operation. Table 1-1 shows the default configuration for sending data.
Table 1-1. Default Transceiver-Board Configuration as Shipped
Designator J10 J9 J9 J9 J9 J9 J9 J9 TP1, TP3 C14, C15 C22, C23 C18, C19 C20, 21 Function REF CLK SEL RBCMODE ENABLE SYNC_EN LOOPEN TEST_EN PRBSEN MODESEL VDD- bridge -VDDA TX ac-coupling capacitors RX ac-coupling capacitors TX ac-coupling to GBIC RX ac-coupling to GBIC Condition Jumper installed - provides a method of supplying a input clock to the board Jumper not installed (logic 1) - for a 1/10 baud-rate clock on RBC0 (a non-DDR mode) Jumper not installed (logic 1) - this pulls up the enable pin for normal operation Jumper installed (logic 0) - disables the TLK2201 comma-detection circuitry Jumper installed (logic 0) - disables the TLK2201 internal loopback mode Jumper installed (logic 0) - disables the TLK2201 test mode Jumper installed (logic 0) - disables the TLK2201 PRBS internal production test mode Jumper installed (logic 0) - puts the parallel buses in a 10-bit mode (disables the DDR mode) Joins the VDD and VDDA power planes These capacitors (normally installed) are provided to ac-couple the transmitted signal. These capacitors (normally installed) are provided to ac-couple the received signal. These capacitors (normally not installed) are provided to ac-couple the TLK2201 transmitted data to the 75- GBIC interface. These capacitors (normally not installed) are provided to ac-couple the 75- GBIC receiver data to the TLK2201.
Introduction
1-3
TLK2201 EVM Board Configuration
Table 1-2. Configuration Changes Necessary for DC Coupling of the High-Speed Signals
Designator C14, C15 C16, C17 Function TX AC coupling capacitors RX AC coupling capacitors Condition or Changes Necessary for DC Coupling Install zero-ohm resistors Install zero-ohm resistors
1-4
Chapter 2
Test and Setup Configurations
This chapter presents the typical test and setup configurations used to evaluate and test the transceiver. The printed-circuit board construction and characteristics are included in the second section of this chapter.
Topic
2.1 2.2
Page
Typical Test and Setup Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 PCB Construction and Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Test and Setup Configurations
2-1
Typical Test and Setup Configurations
2.1 Typical Test and Setup Configurations
The following configurations are used to evaluate and test the TLK2201 transceiver. The first configuration is an external serial loopback of the high-speed signals shown in Figure 2-1. The serial loopback allows the designer to evaluate most of the functions of the transmitter and receiver sections of the TLK2201 device. To test a system, a parallel-bit error-rate tester (BERT) generates a predefined dc-balanced parallel-bit pattern. The pattern is connected to the transmitter through parallel connectors TD0-TD9 (TD0-TD4 for DDR mode). The TLK2201 device serializes and presents the data on the highspeed serial pair. The serial TX data is then looped back to the receiver side and the device deserializes and presents the data on the receive side RD0-RD9 (RD0-RD4 for DDR mode). The data is received by the BERT and compared against the transmitted pattern and monitored for valid data and errors. If any bit errors are received, a bit-error rate is evaluated at the parallel-receive BERT.
Figure 2-1. TLK2201 External Serial Loopback Test Configuration
Jumper Selection GND RBCMODE ENABLE SYNC_EN J9 LOOP_EN TEST_EN PRBS_EN MODESEL GND EXT INPUT Channel 1 O/P HP8133A Pulse Generator
Parallel BERT
REF_CLK CLK OUT TD 0-9 TX Data Out 0-9 10 bits Transmitter BERT CLK IN RX Data In 0-9 10 bits Receiver BERT RD 0-9 RX- RBC_CLK RX+ TX- TX+
TLK2201EVM Evaluation Board
2-2
Typical Test and Setup Configurations
If a parallel BERT is not available, the designer can take advantage of the built-in-test mode of the device, see Figure 2-2. If the designer asserts the PRBSEN pin high, a pseudo random bit pattern will be transmitted. This pin also puts the receiver in a mode to detect a valid PRBS pattern. A valid pattern is indicated by the SYNC_PASS pin indicating high. This test only validates the high-speed serial portion of the device and system interconnects. The PRBS pattern is compatible with most serial BERT test equipment. This function allows the operator to isolate and test the transmitter and receiver independently. A typical configuration is shown in Figure 2-3. The dashed lines represent optional connections that can be made for monitoring eye patterns and measuring jitter.
Figure 2-2. TLK2201EVM Serial PRBS Self-Test Configuration
Jumper Selection GND RBCMODE ENABLE SYNC_EN LOOP_EN TEST_EN PRBS_EN MODESEL GND J9 Channel 1 O/P HP8133A Pulse Generator EXT INPUT TRIGGER OUT HP83480 or Tek 11801 Digital Oscilloscope
CH1 CH2 Trigger
REF_CLK PRBS 2^7-1
Channel 1
TX- TX+
TDS820 Digital Oscilloscope
SYNC_PASS RD 0-9(4)
RX+ RX- PRBS 2^7-1
TLK2201EVM Evaluation Board
Test and Setup Configurations
2-3
Typical Test and Setup Configurations
Figure 2-3. TLK2201EVM Serial PRBS BERT Test Configuration
Jumper Selection GND RBCMODE ENABLE SYNC_EN LOOP_EN TEST_EN PRBS_EN MODESEL GND J9 Channel 1 O/P HP8133A Pulse Generator EXT INPUT TRIGGER OUT CLK/10 HP83480 or Tek 11801 Digital Oscilloscope
CH1 CH2 Trigger
REF_CLK Channel 1 PRBS 2^7-1 TX- TX+
Serial BERT HP7004A 3 Gbps Receiver BERT Data In
Transmitter BERT TDS820 Digital Oscilloscope SYNC_PASS RD 0-9(4) RX+ RX- PRBS 2^7-1 Data Out Data Out CLK OUT
TLK2201EVM Evaluation Board
2-4
PCB Construction and Characteristics
2.2 PCB Construction and Characteristics
The PCB characteristics are calculated and based on the layer construction and trace width of the board.
Figure 2-4. TLK2201EVM Layer Construction
Layer 1 14 Mil Layer 2 5.5 Mil Layer 3 21 Mil Layer 4 9.5 Mil Layer 5 6 Mil Layer 6 GND2 Solder 50 VDD1 75 GND1 Top 50
Notes: 1) All cores consist of 1 oz Cu. 2) Trace width A) 25 mils (for 50- layer 1) B) 11.8 mils (for 75- layer 4) C) 11.8 mils (for 50- layer 6) 3) Overall board thickness is 62 mils 5 mil 4) Copper and solder mask adds approximately 10 mils to the overall board thickness 5) Impedance is 50 10% 6) Material is G-Tek. Dielectric constant = 3.9 7) For overall thickness: add 1.2 to 1.4 mils for each metal layer in the stack
Test and Setup Configurations
2-5
2-6
Appendix A
Schematics, Board Layouts, and GBIC Configurations
This appendix contains the schematics, bill of materials, and board layouts for the TLK2201EVM transceiver board.
Schematics, Board Layouts, and GBIC Configurations
A-1
VDDA1 J1 0.01 0.01 VCC 0.01 C5 VDDA1 VCC 4.7k 4.7k 4.7k 4.7k 4.7k 4.7k C17 R1 open TP2 0.01 C6 C9 C7 C8 100p 0.01 100p 0.01 J5 0.01 Split power plane VDDA1 L2 GBIC_TXP GBIC_TXN 0.01 C14 0.01 C15 C16 0.01 C11 C18 C13 R7 R8 R4 R5 R6 R3 C22 C23 R2 open VDDA2 0.01 0.01 0.01 R10 open 0.01 J7 2 1 3 0.01 R11 49.9 0.01 P2 TMS VDD TDO 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 KEY GBIC_RXP VCC TRST TRST C44 0.01 GBIC_RXN VDD VDDA1 TMS VDDA1 R12 C24 TRST 49.9 VDDA1 C26 0.01 C38 0.01 0.01 C25 L4 TP3 Split power plane 0.01 C20 C21 P1 GBIC CONNECTOR 1 2 3 4 5 6 7 8 9 10 C19 0.01 0.01 J3 0.01 C1 J2 J4 VCC L1 Split power plane C2 C3 C4
VDDA1
VDDA1
VDDA1
A-2
GBIC_RXN GBIC_RXP L3 C10 4.7u 100p VDD TP1 2 1 3 2 4 6 8 10 12 RX_LOS MOD_DEF(0) MOD_DEF(1) MOD_DEF(2) TX_DISABLE TX_FAULT 1 3 5 7 9 11 0.01 C39 100p C43 0.01 C42 0.01 C40 100p 100p 100p C41 C33 C34 C36 C35 C37 0.01 0.01 C31 C32 100p 0.01 0.01 C30 10uF TMS TDI RSV TDO TCLK_RET CLK RSV RSV GBIC_TXP GBIC_TXN TDI 48 47 46 45 44 43 42 41 40 RD5 RD6 VDD RD7 RD8 RD9 GND VDD TDO RBC1 RBC0 LOS 39 38 VDD 37 36 35 34 33 ENABLE 35.7 35.7 R34 R35 RBC0 RBC1 25 26 27 28 29 30 31 32 LOS C51 C50 C48 0.01 35.7 35.7 35.7 35.7 R30 R31 R32 R33 RD8 RD9 VDD C46 0.01 35.7 35.7 35.7 35.7 R26 R27 R28 R29 RD4A RD5 RD6 RD7 35.7 R15 RD0 RD1 RD2 RD3 SYNC/PASS GND RD0 RD1 RD2 U1 VDD RD3 TLK2201 RD4 SYNC/PASS P5 11 12 13 14 15 16 17 18 19 20 TXP TXN RXP TMS VDD RXN VDD TCLK VDDA VDDA VDDA VDDA GNDA GNDA TRSTN GNDPLL 1 GND TD0 TD1 TD2 VDD TD3 TD4 TD5 TD6 VDD TD7 TD8 TD9 GND MODESEL PRBSEN GND GND VDD VDD TEN TD0 2 3 4 0.01 C45 5 6 7 8 9 0.01 C47 10 11 12 13 14 VDD 15 16 VDDPLL REFCLK R36 0 SYNCEN LOOPEN TD1 R21 R22 R23 R24 R25 TD2 VDD TD3 TD4 TD5 TD6 VDD TD7 TD8 TD9 10k 10k 10k 10k 10k 2 SYNC/PASS 4 RD0 6 RD1 8 RD2 10 RD3 12 RD4A 14 RD5 16 RD6 18 RD7 20 RD8 22 RD9 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 RBCMODE 24 26 RBC1 28 RBC0 30 32 LOS 17 18 19 20 21 22 23 24 4.7k 4.7k 4.7k 4.7k 4.7k 4.7k 4.7k R37 open C49 TDO 35.7 VDDA2 0.01 R51 R39 R40 R41 R42 R43 R44 35.7 0.01 0.01 35.7 R46 R38 R45 VDD VDD VDD 2 4 6 8 10 12 14 VDD R47 R50 0 R48 R49 0 MODESEL PRBSEN TEST_EN LOOP_EN SYNC_EN ENABLE RBCMODE open 49.9 1 J10 J11 2 3 0.01 VDD C52
VDD
VDD
J6
R9
1k
C12 100p
D1
GND
J8
VDD
100p
100p
VDD
C27
C28
C29
R13
0
10k
10k
10k
10k
10k
R14
open
R17
R16
R18
R19
R20
Figure A-1. TLK2201EVM Transceiver Schematic
P3
1 3 5 7 9 11 13 15 17 19
2 4 6 8 10 12 14 16 18 20
TD0 TD1 TD2 TD3 TD4 TD5 TD6 TD7 TD8 TD9
J9
1 3 5 7 9 11 13
Figure A-2. Optical Transceiver Configuration
Install or redirect steering capacitors for GBIC usage 50- high-speed data lines to SMA
75- GBIC high-speed data lines
50- high-speed data lines to SMA
Note: Simultaneous GBIC and SMA operation is not possible. Steering capacitors can either be directed to the GBIC or the SMA connectors but not to both simultaneously.
Schematics, Board Layouts, and GBIC Configurations
A-3
Table A-1.TLK2201EVM Transceiver Bill of Materials
1 2 3 4 5 6 1 1 1 1 3 39 Digi-Key Digi-Key Digi-Key Digi-Key Newark Digi-Key S2011-12-ND S2011-14-ND S2011-20-ND S1111-32-ND 39N867 PCC1784CT-ND J7 J9 P3 P5 J5,J6,J8 C1-C5, C7, C8, C10, C11, C13, C14-C21, C24-C26, C33-C36, C38-C42, C44-C52 C22 C37 L1-L4 TP2 P1 R13, R36, R49, R50 R3-R8, R39-R44, R51 R16-R25 R11, R12, R48 R1, R2, R10, R37, R14, R47 R15, R26-R35, R38, R45, R46 J11, J1-J4 STANDOFF 2X12 Header 2X14 Header 2X20 Header 2X32 Jumper Banana jack Capacitor, SMT603 10 V, 10%, 0.01 F 0.1x0.1 Centers 0.1x0.1 Centers 0.1x0.1 Centers 0.1x0.1 Centers
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
1 1 4 1 1 4 13 10 3 6 14 5 4 4 1 1 1 1 11
Digi-Key Digi-Key Digi-Key Digi-Key AMP Digi-Key Digi-Key Digi-Key Digi-Key N/A Digi-Key Newark Newark Newark TI Digi-Key 3M Digi-Key Digi-Key
PCC1842CT-ND PCC1894CT-ND 240-1018-1ND S1111-02-ND 787653 P0.0JCT-ND P4.75KLCT-ND P10.0KLCT-ND P49.9LCT-ND N/A P35.7LCT-ND 142-0711-821 92N4922 30F082 TLK2201 P1kLCT-ND 3M2514-6002UB L62711CT-ND PCC101ACVCT-ND
Capacitor, SMT0805 Capacitor, SMT1210 Ferrite bead 805 500 mA 1x2 Header GBIC Connector Resistor, SMT, 0402 Resistor, SMT, 0402 Resistor, SMT, 0402 Resistor, SMT, 0402, 1% 1/16W 50 V Resistor, SMT, 0402 1% 1/16W 50 V Resistor, SMT, 0402 1% 1/16W 50 V SMA end launch Standoff 0.5' 4-40 thread Machine screw 4-40 x 3/8'
10 V, 20%, 4.7 F 10 V, 10%, 10 F 600 at 100 MHz Header, 1x2, 0.1 center N/A 0.0 4.7 k 10.0 k 49.9 Open 35.7
U1 R9 P2 D1 C6, C9, C12, C23, C27-C32, C43
TI TLK2201 DUT Resistor, SMT, 0402 1% 1/16W 50 V IDC14M 2x14 header SMT LED red Capacitor, SMT 0603
64 pin VQFP 1 k 0.1x0.1 centers
50 V, 5%, 100 pF
A-4
Figure A-3. Top Layer 1
VCC
L1
P6
P14
P2 C9 P5 C8 PIN 1 JTAG P13
C6
C5 J4 100p
C7 100p
TEXAS INSTRUMENTS
RXN
SYNC
RBC1
RBC0
GND
GND
LOS
RD0
RD1
RD2
RD3
RD4
RD5
RD6
RD7
RD8
RD9
GND C3 C4 RX_LOS GND MOD_DEF(0) MOD_DEF(1) MOD_DEF(2) TX_DISABLE TX_FAULT TP2 R15 R26 R27 R28 R29 R30 R31 R32 R33 R34 R35 P5
GND
1.25Gbps Transceiver Evaluation Board (EVM) TLK2201 Serial Gigabit CMOS 04-OCT-1999 Rev 1.0
R36 0 35.7
R37 open J9 GND
J7 R38 R45 R46 C21 35.7 J3 C17 C16 C20 C19 C15 C14 C18 10 1 9
R8
R7
R6
R5
R4
R3
RXP
4.7k
J2
TXN
TD0 TD1 TD2 TD3 TD4 TD5 TD6 TD7 TD8 TD9
R14 open C1 C2
TD0
TD1
TD2
TD3
TD4
TD5
TD6
TD7
TD8
TD9
TXP
J1
Schematics, Board Layouts, and GBIC Configurations
0
P1 R13 GND C10 C11 L2 TP1 GND VDD
RBCMODE ENABLE SYNC_EN LOOP_EN TEST_EN PRBSEN MODESEL GND
2 19 11 12
20
PIN 1
J11
J10 C52
P3 GND GND GND VDD TP3 L4
REFCLK
C24 C25
C23 100p
VDD
C13 C37 L3 C12 100p R9 1k C22 4.7u 10uF
GND
D1
Notes: *All Capacitors are .01uf unless otherwise marked *All Resistor are 49.9 ohm unless otherwise marked
A-5
Figure A-4. GND Layers 2 and 5
A-6
Figure A-5. Power Plane Layer 3
Schematics, Board Layouts, and GBIC Configurations
A-7
Figure A-6. GBIC and JTAG Layer 4
VCC
L1
P6
P14
P2 C9 P5 C8 PIN 1 JTAG P13
C6
C5 J4 100p
C7 100p
RXN
SYNC
RBC1
RBC0
GND
GND
LOS
RD0
RD1
RD2
RD3
RD4
RD5
RD6
RD7
RD8
RD9
GND C3 C4 RX_LOS GND MOD_DEF(0) MOD_DEF(1) MOD_DEF(2) TX_DISABLE TX_FAULT TP2 R15 R26 R27 R28 R29 R30 R31 R32 R33 R34 R35 P5
GND
1.25Gbps Transceiver Evaluation Board (EVM) TLK2201 Serial Gigabit CMOS 04-OCT-1999 Rev 1.0
R36 0 35.7
R37 open J9
J7 R38 R45 R46 C21 35.7 J3 C17 C16 C20 C19 C15 C14 C18 10 1 9
R8
R7
R6
R5
R4
R3
RXP
4.7k
J2
TXN
TD0 TD1 TD2 TD3 TD4 TD5 TD6 TD7 TD8 TD9
R14 open C1 C2
TD0
TD1
TD2
TD3
TD4
TD5
TD6
TD7
TD8
TD9
TXP
J1
A-8
0
P1 R13 GND C10 C11 L2 TP1 GND VDD
GND RBCMODE ENABLE SYNC_EN LOOP_EN TEST_EN PRBSEN MODESEL GND
2 19 11 12
20
PIN 1
J11
J10 C52
P3 GND GND GND VDD TP3 L4 C24 C25
REFCLK
C23 100p
VDD
C13 L3 C12 100p R9 1k 10uF C37
GND
C22 4.7u
D1
Notes: *All Capacitors are .01uf unless otherwise marked *All Resistor are 49.9 ohm unless otherwise marked
Figure A-7. Bottom Layer 6
Schematics, Board Layouts, and GBIC Configurations
C33 100p C27 C34 100p 10k R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 C28 4.7k R39 C38 R40 R47 R41 R49 [0] R42 R43 C36 R44 100p R51 C30 R48 C26 R12 C51 C48 C46 C41 100p C32 C44 open R2 open R1 R10 [open] [open] R50 [0] C49 C50 100p C31 C47 C45 C40 C42 C43 C39 R11 C35 100p C29
A-9
A-10

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