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TSB15LV01
Video Signal Processor With IEEE 1394 Link Layer Controller
Data Manual
2000
Mixed Signal Products
SLLS425
IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 2000, Texas Instruments Incorporated
Contents
Section
1
Title
Page
1-1 1-2 1-3 1-4 1-5 2-1 2-1 2-1 2-1 2-6 2-7 2-7 2-7 2-8 2-8 2-12 2-21 2-23 2-23 2-24 2-24 2-25 2-26 2-26 2-27 2-27 2-28 2-29 2-29 2-29 2-30 2-30 2-30 2-31 3-1 3-1 3-2
2
3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 1394 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.1 Isochronous Versus Asynchronous Protocols . . . . . . . . . . . 2.1.2 Packet Format/Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.3 1394 Serial Bus Management Capabilities . . . . . . . . . . . . . 2.1.4 PHY/Link Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.5 Enabling the Transmission of Video . . . . . . . . . . . . . . . . . . . 2.2 Sensor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.1 CCD Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.2 Analog Front End Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.3 CCD/AFE Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 STAT Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 Motor Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.1 Motor Driver Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.2 Positioning System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.3 Pushbutton Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6 Video Signal Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.1 De-Mosaicing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.2 Brightness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.3 Gain and Exposure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.4 Sharpness and Saturation . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.5 White Balance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.6 Gamma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.7 YUV Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.8 Antiblooming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.9 Backlight Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.10 White Spot Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.11 Test Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 1394 Node Memory Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Top-Level Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iii
4
5 6
Register Detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.3.1 1394 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.3.2 Inquiry Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.3.3 Control and Configuration Registers . . . . . . . . . . . . . . . . . . . 3-14 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Free-Air Temperature . . . . . . . . . . . . . 4-2 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 Mechanical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
3.3
List of Illustrations
Figure Title 2-1 Top-Level Sensor Interface Signal Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 TLV990 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 AFE Serial Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 Sensor Interface Timing for ICX098/LZ24BP Sensor, Full Frame . . . . . . . . 2-5 Sensor Interface Timing for ICX084 Sensor, Full Frame . . . . . . . . . . . . . . . . 2-6 Sensor Interface Timing for TC237 Sensor, Full Frame . . . . . . . . . . . . . . . . . 2-7 Sensor Interface Timing for ICX098/LZ24BP Sensor, Start of Frame Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 Sensor Interface Timing for ICX084 Sensor, Start of Frame . . . . . . . . . . . . . 2-9 Sensor Interface Timing for TC237 Sensor, Start of Frame . . . . . . . . . . . . . 2-10 Sensor Interface Timing for ICX098/LZ24BP/ICX084 Sensor, Start of Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 Sensor Interface Timing for TC237 Sensor, Start of Line . . . . . . . . . . . . . . 2-12 Sensor Interface Timing for All Sensors, Horizontal Drive . . . . . . . . . . . . . 2-13 STATn Motor Select Pulses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 Gain and Exposure Automatic and Manual Controls . . . . . . . . . . . . . . . . . . 2-17 TSB15LV01 Built-In Test Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 TSB15LV01 Root Directory Tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 2-8 2-9 2-11 2-13 2-14 2-15
2-16 2-17 2-18 2-19 2-20 2-21 2-23 2-25 2-26 2-28 2-31 3-2
iv
List of Tables
Table Title 2-1 Isochronous Data Block Packet Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Data Payload Per Isochronous Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Video Data Payload Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 Data Structure for Y, R, G, and B Data Components . . . . . . . . . . . . . . . . . . . 2-5 Data Structure for U and V Data Components . . . . . . . . . . . . . . . . . . . . . . . . 2-6 Asynchronous Quadlet Write Request Packet Format . . . . . . . . . . . . . . . . . . 2-7 Asynchronous Block Write Request Packet Format . . . . . . . . . . . . . . . . . . . . 2-8 Asynchronous Quadlet Read Request Packet Format . . . . . . . . . . . . . . . . . 2-9 Asynchronous Block Read Request Packet Format . . . . . . . . . . . . . . . . . . . . 2-10 Approved CCD Sensors and Recommended Drivers . . . . . . . . . . . . . . . . . 2-11 Values Transmitted to AFE via Serial Interface . . . . . . . . . . . . . . . . . . . . . . . 2-12 AFE Interface Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 ICX098/LZ24BP Full Frame Timing Parameters . . . . . . . . . . . . . . . . . . . . . . 2-14 ICX084 Full Frame Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 TC237 Full Frame Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 ICX098/LZ24BP Frame Start Timing Parameters . . . . . . . . . . . . . . . . . . . . . 2-17 ICX084 Frame Start Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 TC237 Frame Start Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 ICX098/LZ24BP/ICX084 Line Start Timing Parameters . . . . . . . . . . . . . . . 2-20 TC237 Line Start Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 Horizontal Drive Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22 Status Terminal Functions Determined by STATn Register Fields . . . . . . . 2-23 Stepper Drive Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24 EEPROM Interface Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25 CCD Sensor Processing Adjustments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26 Backlight Compensation Hot Regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 TSB15LV01 Register Groupings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 1394 Address Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Top-Level Memory Map: 1394 Memory (Core CSRs) . . . . . . . . . . . . . . . . . . 3-4 Top-Level Memory Map: 1394 Memory (Device Configuration ROM) . . . . . 3-5 Top-Level Memory Map: Inquiry Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 Top-Level Memory Map: Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 Top-Level Memory Map: Configuration Registers . . . . . . . . . . . . . . . . . . . . . . 3-8 Implemented Core CSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 Serial-Bus-Dependent CSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 Base Configuration ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 Node_Unique_ID Leaf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 2-2 2-2 2-3 2-4 2-4 2-4 2-5 2-6 2-6 2-8 2-11 2-11 2-13 2-14 2-15 2-16 2-17 2-18 2-19 2-20 2-21 2-22 2-24 2-26 2-26 2-30 3-1 3-1 3-2 3-3 3-4 3-5 3-5 3-6 3-6 3-6 3-6
v
3-12 3-13 3-14 3-15 3-16 3-17 3-18 3-19 3-20 3-21 3-22 3-23 3-24 3-25 3-26 3-27 3-28 3-29 3-30 3-31 3-32 3-33 3-34 3-35 3-36 3-37 3-38 3-39 3-40 3-41
Unit Directory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unit-Dependent Directory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Vendor Name Leaf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Model Name Leaf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Video Format Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Video Format Register Proper Values for TSB15LV01 . . . . . . . . . . . . . . . . Video Format Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Video Mode Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Video Mode Proper Values for TSB15LV01 . . . . . . . . . . . . . . . . . . . . . . . . . . Video Mode Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Video Frame Rate Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Video Frame Rate Proper Values for TSB15LV01 . . . . . . . . . . . . . . . . . . . . Video Frame Rate Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Map for Basic Function Register . . . . . . . . . . . . . . . . . . . . . . . . . . . Basic Function Register Proper Values for TSB15LV01 . . . . . . . . . . . . . . . Field Descriptions for Basic Function Register . . . . . . . . . . . . . . . . . . . . . . . Memory Map for Feature Presence Registers . . . . . . . . . . . . . . . . . . . . . . . Feature Presence Registers Proper Values for TSB15LV01 . . . . . . . . . . . Field Descriptions for Feature Presence Registers . . . . . . . . . . . . . . . . . . . Memory Map for Feature Elements Inquiry Registers . . . . . . . . . . . . . . . . . Feature Elements Registers Proper Values for TSB15LV01 . . . . . . . . . . . . Field Descriptions for Feature Elements Registers . . . . . . . . . . . . . . . . . . . Camera Initialize Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . Camera Initialize Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . Memory Map for Camera Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Field Descriptions for Camera Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Map for Feature Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . Field Descriptions for Feature Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Field Descriptions for Configuration Registers . . . . . . . . . . . . . . . . . . . . . . .
3-7 3-7 3-7 3-7 3-8 3-8 3-8 3-9 3-9 3-9 3-10 3-10 3-10 3-11 3-11 3-11 3-12 3-12 3-12 3-13 3-14 3-14 3-15 3-15 3-15 3-16 3-17 3-18 3-19 3-20
vi
1 Introduction
The TSB15LV01 is a video signal processor integrated with a 1394 link layer controller. It is designed to be the center of a host-controlled, full-motion color camera when coupled with a 1394 PHY, CCD sensor and driver, analog front end, and an external EEPROM device. A camera based on the TSB15LV01 is compliant with the IEEE 1394a standard and the 1394 Trade Association's Digital Camera specification, Draft 1.04. The TSB15LV01 offers the advantage of 24-bit true-color digital video processing. This gives superior video quality at higher sustained data rates. Isochronous transfer of the video data and asynchronous control of the camera are accomplished via the 1394 high-speed serial bus, operating at data rates of up to 400 Mbits/s. This bus allows noncompressed full-motion digital video at rates of 30 frames/sec. Use of this serial connection eliminates the need for expensive video capture cards. The chipset supports the YUV 4:1:1, YUV 4:2:2, YUV 4:4:4, and RGB 24-bit formats. The video signal processor (VSP) portion of the device incorporates proprietary digital image processing techniques, implemented with an advanced digital signal processing (DSP) ASIC. These techniques enable a camera to achieve excellent color accuracy and resolution. The use of a custom advanced CMOS ASIC process allows for both the advanced digital image processing techniques and for advanced color space conversion. This allows the multiple output formats required for a multipurpose video conferencing camera. Use of this advanced, low-power CMOS process also enables the camera to be powered by a notebook computer operating on battery power. The device is designed to work with CCDs that have a pixel resolution of 640(H) y 480(V). This resolution meets the VGA square pixel standards. The 1394 link layer controller is capable of up to 400 Mbits/s operation and is compatible with both the IEEE 1394 - 1995 and 1394a standards. The TSB15LV01 implements all registers and address space required by the 1394 Trade Association's Digital Camera specification, Draft 1.04 (hereafter referred to as the Digital Camera Specification). The device supports packet speeds of up to 400 Mbits/s, but the maximum bandwidth consumed by the device is 200 Mbits/s. This means that a TSB15LV01-based camera leaves at least 200 Mbits/s available to other functions. With its balance of features and low cost, a system based on TSB15LV01 is well-suited for applications such as: * * * * * * * * * * PC Video Camera Video Conferencing Video Capture Still Picture Capture Set-Top Boxes Video Phone Gaming Webcam Robotics Security
1-1
1.1 Features
* * * Compatible With 1394 Trade Association's Digital Camera Specification, Draft 1.04 1394a Link Layer Controller With 400 Mbits/s Capability Support for Several CCD Sensors - - - * * Sony ICX084AK, ICX098AK Sharp LZ24BP Texas Instruments TC237
Integrated CCD (Charge-Coupled Device) and CDS (Correlated Double Sampling) Pulse Timer With Programmable Pulse Skew Video Controls - - - - - - - Brightness (Auto/Manual) Exposure (Auto/Manual) Sharpness (Manual) Saturation (Manual) White Balance (Auto/Manual) Gamma (Manual) Backlight Compensation (Manual)
* * * *
Three Stepper Motor Controls for Focus/Zoom/Tilt or Other Motorized Functions EEPROM Interface Programmable Status/Test Terminals Seamlessly Connects to TI's 1394 Physical Layer Devices
1-2
1.2 Functional Block Diagram
CCD Interface; AFE Sample/Hold and Black Clamp Interface Analog Front End (AFE) Video Data Interface Analog Front End (AFE) Serial Interface
Timing Generator
Pipelined Video Signal Processor Controls:
Motor Interface STAT Interface
Motor Control
Gain White Balance Gamma Brightness Saturation Sharpness
RGB / YUV and Quadlet Data Formator
Control Data Master Controller FIFO Buffer
EEPROM Interface
Feature Control/ Configure Register RAM
ASYNC Command Processor
Host Interface
CFR
Data Mover
ASYNC FIFO
Link Core
1394 Link Layer
1394 PHY I/F
1-3
1.3 Terminal Assignments
TQFP PACKAGE (TOP VIEW)
PHASE1_A PHASE1_B PHASE2_A PHASE2_B GND IR_SIG MOTOR_PLUS MOTOR_MINUS EN VDD_CAP VCC_CORE PG2 EEPROM_SO VCC EEPROM_CS EEPROM_SI EEPROM_SCLK VCC CLAMP SV SR NC OBCLP GND SERIAL_CS SERIAL_DATA SERIAL_CLK NC GND ADCLK VCC PIXEL_DATA9 PIXEL_DATA8 PIXEL_DATA7 PIXEL_DATA6 PIXEL_DATA5 TEST_SE_IN
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53
TESTMODE RESET GND
52 51 50 49 48 47 46 45 44 43 42
TSB15LV01PFC (TQFP)
41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
LREQ PG1 SCLK VCC CTL0 CTL1 GND D0 D1 D2 D3 VCC D4 D5 D6 D7 GND STAT0 STAT1 STAT2
NC - No internal connection
1-4
GND PIXEL_DATA4 PIXEL_DATA3 PIXEL_DATA2 PIXEL_DATA1 PIXEL_DATA0 VCC CAM_POWER IAG_XV3 VCC_CORE VDD_CAP ABSP_XSG XV2 SAG_XV1 ABD_XSUB GND H2 SRG_H1 RST_RG VCC
1.4 Terminal Functions
TERMINAL NAME ADCLK CLAMP OBCLP PIXEL_DATA9- PIXEL_DATA0 SERIAL _CS SERIAL _DATA SERIAL _CLK SR SV NO. 13 2 6 15 - 19, 22 - 26 8 9 10 4 3 I/O DESCRIPTION Analog Front End (AFE) Interface O O O I O O O O O ADC clock. Triggers the AFE's analog/digital converter to sample the amplifier output, and clocks the digital data out of the AFE to the TSB15LV01. Pulse that instructs AFE to electrically clamp the ac-coupled pixel pulse to a fixed reference voltage. Optical Black Clamp pulse. Instructs the AFE to clamp its ADC output to a digital black reference value. Samples occur during the black pixel portion of the CCD's image signal. Data bus that inputs processed video data from the AFE's analog/digital converter. PIXEL_DATA_IN9 is the MSB of these 10 bits. Serial interface chip select. Allows programming of AFE control registers. Signifies the beginning of data transmission on SERIAL_DATA. Serial interface digital data input. Allows programming of AFE control registers. Serial interface clock. Allows programming of AFE control registers. Clocks data out of SERIAL_DATA. CCD reset-pedestal sampling pulse. Triggers the AFE to sample the reset pedestal of the pixel pulse received from the CCD image sensor. CCD video data sampling pulse. Triggers the AFE to sample the data pedestal of the pixel pulse received from the CCD image sensor. CCD Interface ABD_XSUB ABSP_XSG H2 IAG_XV3 RST_RG SAG_XV1 SRG_H1 XV2 CTL1, CTL0 D[7..0] LREQ RESET SCLK EEPROM_CS EEPROM_SCLK EEPROM_SI EEPROM_SO 35 32 37 29 39 34 38 33 55 56 45 - 48, 50 - 53 60 62 58 66 64 65 68 O O O O O O O O I/O I/O I/O I I O O O I Image area clear bias. Goes high to clear the image area. This pulse performs an electronic shutter function, controlling the integration time of the CCD image. Performed at the beginning of every frame. Antiblack smear. Goes low to increase the pixel well size during parallel transfer. Horizontal transfer 2. Horizontal charge transfer control for CCD. Image-area gate/vertical transfer 3. Charge transfer control for CCD. Reset gate. Reset pulse for the CCD's charge-detection amplifier, generated for every pixel moved out of the CCD. Storage-area gate/vertical transfer 1. Charge transfer control for CCD. Serial register gate/horizontal transfer 1. Horizontal charge transfer control for CCD. Vertical transfer 2. Charge transfer control for CCD. PHY Interface Control 1 and control 0 of the PHY-link control bus. Data signals of the PHY-link data bus. Data is expected on D0-D1 at 100 Mbits/s, D0-D3 at 200 Mbits/s, and D0-D7 at 400 Mbits/s. D0 is the MSB. Makes bus requests and accesses to the PHY. Reset, active low. The asynchronous reset to the link controller. System clock. SCLK is a 49.152-MHz clock supplied by the PHY. EEPROM Interface EEPROM chip select. EEPROM serial data clock. EEPROM serial data output. EEPROM serial data input.
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TERMINAL NAME IR_SIG MOTOR_MINUS MOTOR_PLUS PHASE2_B PHASE2_A PHASE1_B PHASE1_A NO. 75 73 74 77 78 79 80 I/O DESCRIPTION Motor Control Interface I I I O O O O Position feedback from infrared detectors on motorized mechanisms. Applies to the stepper motor currently selected by the STATn terminals. Negative pushbutton input. Applies to the stepper motor currently selected by the STATn terminals. Positive pushbutton input. Applies to the stepper motor currently selected by the STATn terminals. Drive signal for stepper motors, phase 2, signal B. Applies to the stepper motor currently selected by the STATn terminals. Drive signal for stepper motors, phase 2, signal A. Applies to the stepper motor currently selected by the STATn terminals. Drive signal for stepper motors, phase 1, signal B. Applies to the stepper motor currently selected by the STATn terminals. Drive signal for stepper motors, phase 1, signal A. Applies to the stepper motor currently selected by the STATn terminals. Miscellaneous Interface CAM_POWER EN GND 28 72 7, 12, 21, 36, 44, 54, 61, 76 5, 11 59, 69 41 42 43 20 63 30,70 1, 14, 27, 40, 49, 57, 67 31,71 I I Factory test terminal. Connect to ground. Factory test terminal. Connect to ground. Power/Ground VCC_CORE VCC Connect to 3.3 V. Connect to 3.3 V. I/O O I Power switch. Toggles with bit in CAMERA_POWER_CNTL register, which is low upon device power up. Used to instruct system power supply to enter power saving mode. Regulator enable. When low, the device supply power regulator is active. Should be kept low during normal operation. Connect to ground.
NC PG1, PG2 STAT2 STAT1 STAT0 TEST_SE_IN TESTMODE
No connect No connect Status signals g
VDD_CAP
Mid-supply. Connect to ground through a 0.1-F capacitor.
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2 Detailed Description
2.1 1394 Interface
The 1394 interface is used to connect the camera to external devices using the IEEE 1394 serial bus. This bus is currently capable of speeds up to 400 Mbits/s and provides adequate bandwidth in which to transmit a quality uncompressed video signal. It is assumed that the reader has a moderate level of familiarity with the 1394 serial bus. The TSB15LV01 serves as the application, transaction, and link layers of a 1394 node. This greatly simplifies implementation of the 1394 node, since only the physical layer remains to be implemented. This can be accomplished by placing a 1394 PHY, such as the TSB41LV01, between the TSB15LV01 and the 1394 connector. The 1394 interface on the TSB15LV01 provides a glueless interface to the PHY. Note that while the device supports s400 1394 packets, the maximum bandwidth consumed by the device is 200 Mbits/s. This means that a TSB15LV01-based camera leaves at least 200 Mbits/s available to other functions, assuming all devices on the bus use s400 packets. This section is not designed to be a tutorial on 1394. It is assumed that the reader has a basic knowledge of the 1394 serial bus. For more information on the 1394 bus, see the 1394 standard.
2.1.1
Isochronous Versus Asynchronous Protocols
There are two types of packets used in the 1394 link layer: isochronous and asynchronous. The TSB15LV01 uses isochronous packets to send video data to the bus and asynchronous packets to exchange control/status information with the bus. An isochronous transaction delivers a consistent amount of data that is transferred at regular 125-s intervals, with simplified addressing. Reception of an acknowledge packet is not required. Allocated flows of isochronous data are referred to as channels. Because the packets are assured to be delivered regularly, a constant data rate is achieved, making it ideal for video. In order to assure this bandwidth, a node must first request allocation of the bus resources from the node serving as the bus manager. The TSB15LV01 expects this to be performed by the node receiving the video data, referred to as the host node. The TSB15LV01 is capable of being an isochronous talker. However, it is not capable of listening to a channel of isochronous data. It is capable of transmitting isochronous data on channels 0 to 15 only. An asynchronous transaction delivers a variable amount of data to a specific address. An acknowledge packet must be received from the designated target node, assuring delivery of the packet. This protocol allows packets to be sent without any prior permission or allocation. However, isochronous packets receive priority in order to maintain a consistent data rate. The TSB15LV01 is capable of sending and receiving asynchronous packets with a payload of up to 32 quadlets per packet. All request packets received by the device are answered with a response packet. If a request packet is received between a request and its corresponding response packet, the device acknowledges that packet with a busy acknowledge code.
2.1.2
Packet Format/Protocol
2.1.2.1 Isochronous Packet Format/Protocol
All video data sent from the camera is done so using isochronous communication. Before data can be sent, the node residing in the host must first request allocation of bus resources from the node serving as the bus manager. It must then configure the TSB15LV01's control and configuration registers. After the first CCD image integration cycle that follows completion of configuration, the camera will begin to send video data. The full isochronous packet structure is shown in Table 2-1. This packet structure is defined by the 1394 standard.
2-1
Table 2-1. Isochronous Data Block Packet Format
0-7 data_length 8 -15 tg 16 - 23 channel header_CRC data payload quadlet 1 data payload quadlet 2 . . . last quadlet of data payload (padded with zeroes if necessary) data_CRC 24-31 tCode sy
The fields are defined as: * * * * * * data_length tg channel tCode sy The number of bytes in the data payload field The tag field is set to zero The isochronous channel number, as programmed in the ISO_CHANNEL_CNTL register The transaction code. The code for an isochronous data block transaction is 1010b. Synchronization value. For the first isochronous packet of a frame, this is set to 0001b. For all other isochronous packets, this is set to zero.
data payload Contains the digital video information
Isochronous data is formatted differently for each video transfer mode. Table 2-2 lists all supported transfer modes. For each mode, the table lists the total number of bits representing a single pixel. It also gives the data payload per packet for each mode, in terms of lines, pixels, and quadlets. The payload varies for each frame rate. Every video component, Y, U, V, R, G, and B, has 8-bit data. Table 2-2. Data Payload Per Isochronous Packet
MODE Mode_0 _ VIDEO FORMAT 160 x 120 YUV(4:4:4) ( ) 24 bits/pixel FRAME RATE (Frame per Second) 30 1/2 L 80 P 60 Q Mode_1 _ 320 x 240 YUV(4:2:2) ( ) 16 bits/pixel 1L 320 P 160 Q 2 L 1280 P 480 Q Mode_3 _ 640 x 480 YUV(4:2:2) ( ) 16 bits/pixel 15 1/4 L 40 P 30 Q 1/2 L 160 P 80 Q 1L 640 P 240 Q 1 L 640 P 320 Q 1 L 640 P 480 Q Mode_5 _ 640 x 480 Y ( (Mono) ) 8 bits/pixel 2 L 1280P 1L 640 P 7.5 1/8 L 20 P 15 Q 1/4 L 80 P 40 Q 1/2 L 320 P 120 Q 1/2 L 320 P 160 Q 1/2 L 320P 240Q 1/2 L 320 P 1/8 L 40 P 20 Q 1/4 L 160 P 60 Q 1/4 L 160 P 80 Q 1/4 L 160P 120Q 1/4 L 160 P 3.75
Mode_2 _
640 x 480 YUV(4:1:1) ( ) 12 bits/pixel
Mode_4 _
640 x 480 RGB 24 bits/pixel
320 Q 160 Q 80 Q 40 Q Requires s200 or faster packet speed, as programmed in the ISO_CHANNEL/SPEED_CNTL register. The others can use s100 as well. Key: L: Lines/packet P: Pixel/packet Q: Quadlet/packet
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2.1.2.2 Isochronous Video Payload
Each transfer mode requires a different data format structure, each defining how the pixels are combined to build 32-bit quadlets. Table 2-3 shows the payload structure for each mode, with the quadlets broken down into individual bytes. This data payload structure is slightly different for every video mode. In the table, N is the number of pixels/packet, as shown in Table 2-2. Table 2-3. Video Data Payload Structure
0 -7 U0 Y1 V2 . . . U N-4 Y N-3 V N-2 8 -15 Y0 V1 U3 . . . Y N-4 V N-3 U N-1 16-23 V0 U2 Y3 . . . V N-4 U N-2 Y N-1 24 -31 U1 Y2 V3 . . . U N-3 Y N-2 V N-1 YUV (4:4:4) format (Mode_0)
YUV (4:2:2) format (Mode_1, Mode_3) U0 U2 U4 . . . U N-6 U N-4 U N-2 Y0 Y2 Y4 . . . Y N-6 Y N-4 Y N-2 V0 V2 V4 . . . V N-6 V N-4 V N-2 Y1 Y3 Y5 . . . Y N-5 Y N-3 Y N-1
YUV (4:1:1) format (Mode_2) U0 Y2 Y5 . . . U N-8 Y N-6 Y N-3 RGB format (Mode_4) R0 G1 B2 . . . R N-4 G N-3 B N-2 G0 B1 R3 . . . G N-4 B N-2 R N-1 B0 R2 G3 . . . B N-4 R N-2 G N-1 R1 G2 B3 . . . R N-3 G N-2 B N-1 Y0 Y3 V4 . . . Y N-8 Y N-5 V N-4 Y1 U4 Y6 . . . Y N-7 U N-4 Y N-2 V0 Y4 Y7 . . . V N-8 Y N-4 Y N-1
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Table 2-3. Video Data Payload Structure (Continued)
0 -7 8 -15 Y (Mono) format (Mode_5) Y0 Y1 Y4 V5 . . . . . . Y N-8 Y N-4 Y N-7 V N-3 16-23 U2 Y6 . . . U N-6 Y N-2 24 -31 Y3 Y7 . . . Y N-5 Y N-1
Table 2-4 shows the data structure for Y, R, G, and B video data components. All components are unsigned 8-bit values. Table 2-4. Data Structure for Y, R, G, and B Data Components
SIGNAL LEVEL (Decimal) Highest 255 254 : 1 Lowest 0 DATA (Hexadecimal) 0xFF 0xFE : 0x01 0x00
Table 2-5 shows the data structure for U and V video data components. Both components are signed 8-bit values. Table 2-5. Data Structure for U and V Data Components
SIGNAL LEVEL (Decimal) Highest(+) 127 126 : 1 Lowest 0 -1 : -127 Highest(-) -128 DATA (Hexadecimal) 0xFF 0xFE : 0x81 0x80 0x7F : 0x01 0x00
2.1.2.3 Asynchronous Packet Format/Protocol
Asynchronous packets are used to read status information from the TSB15LV01 and write control information to it. These packets are formatted as defined by the 1394 standard. All reads and writes should correlate with the memory maps as shown in section 3, Address Space. Asynchronous reads and writes can be performed either as quadlets or as blocks. Blocks can be read in sizes of up to 32 quadlets per packet. The structure of a quadlet write request packet is shown in Table 2-6, while the structure of a block write request packet is shown in Table 2-7. Table 2-6. Asynchronous Quadlet Write Request Packet Format
0 -7 source_ID destination_offset quadlet data header_CRC 8 -15 destination_ID 16 -23 tl rt 24-31 tCode pri
destination_offset
2-4
The fields are defined as: * * * * * * * * * destination_ID tl rt 10-bit busID concatenated with 6-bit nodeID
Transaction label, specified by the host that identifies this transaction. This optional value is returned in the response packet. Retry code. Indicates whether this packet is an attempted retry and defines retry protocol. Transaction code. The code for an asynchronous write request for quadlet data is 0000b.
tCode
pri Not used. source_ID Identifies host node by specifying its bus and physical ID destination_offset quadlet_data header_CRC Address location within TSB15LV01 address space
Contains the value being written to the addressed location CRC value for the header Table 2-7. Asynchronous Block Write Request Packet Format
0 -7 source_ID destination_offset data_length header_CRC data block . . . last quadlet of data block extended_tcode (0000) 8 -15 destination_ID 16 -23 tl rt 24 -31 tCode pri
destination_offset
The fields are defined as: * * * * * * * * * * * * destination_ID 10 bit busID concatenated with 6-bit nodeID.
tl Transaction label, specified by the host that identifies this transaction. This optional value is returned in the response packet. rt Retry code. Indicates whether this packet is an attempted retry and defines retry protocol. Transaction code. The code for an asynchronous write request for block data is 0001b.
tCode pri
Not used. Identifies host node by specifying its bus and physical ID Address location within TSB15LV01 address space
source_ID
destination_offset data length
Specifies the amount of data being sent in the data field. Maximum size is 128 bytes. Reserved during write request packets
extended_tcode header_CRC data_field data_CRC
CRC value for the header
Contains the value being written to the addressed location CRC value for the data field
The structure of a quadlet read request packet is shown in Table 2-8, while the structure of a block read request packet is shown in Table 2-9.
2-5
Table 2-8. Asynchronous Quadlet Read Request Packet Format
0-7 source_ID destination_offset header_CRC 8 - 15 destination_ID 16 - 23 tl rt 24 - 31 tCode pri
destination_offset
The fields are defined as: * * * * * * * * destination_ID tl rt 10-bit busID concatenated with 6-bit nodeID
Transaction label is specified by the host that identifies this transaction. This optional value is returned in the response packet. Retry code. Indicates whether this packet is an attempted retry and defines retry protocol. Transaction code. The code for an asynchronous read request for quadlet data is 0100b.
tCode pri
Not used. Identifies host node by specifying its bus and physical ID
source_ID
destination_offset Address location within TSB15LV01 address space header_CRC CRC value for the header Table 2-9. Asynchronous Block Read Request Packet Format
0-7 source_ID destination_offset data_length extended_tcode (0000h) header_CRC 8 - 15 destination_ID 16 - 23 tl rt 24 - 31 tCode pri
destination_offset
The fields are defined as: * * * * * * * * * * destination_ID tl rt. 10-bit busID concatenated with 6-bit nodeID.
Transaction label is specified by the host that identifies this transaction. This value is reflected in the response packet that corresponds to this request packet. Retry code. Indicates whether this packet is an attempted retry and defines retry protocol. Transaction code. The code for an asynchronous read request for block data is 0101b.
tCode pri
Not used Identifies host node by specifying its bus and physical ID Address location within TSB15LV01 address space
source_ID
destination_offset data_length
Specifies the amount of data being sent in the data field. Maximum size is 128 bytes. Reserved during write request packets
extended_transaction_code header_CRC
CRC value for the header
2.1.3
1394 Serial Bus Management Capabilities
Nodes on the 1394 bus may be called on to serve in a number of bus management roles following a bus reset event. The TSB15LV01 is not designed to serve as the isochronous resource manager, a full bus manager, or the cycle master. The contents of the configuration ROM should reflect this level of capability.
2-6
2.1.4
PHY/Link Interface
The PHY/link interface consists of the signals that connect the TSB15LV01, which serves as the link layer of the 1394 node, to a physical layer device, or PHY. This interface carries all data, control, and status information that is transferred between the two layers. To take full advantage of the TSB15LV01's capabilities, a 400-Mbits/s PHY device should be used, such as TI's TSB41LV01.
2.1.4.1 Principles of Operation
The TSB15LV01 PHY/link interface consists of the SCLK, CTL0-CTL1, D0-D7, LREQ, and RESET terminals. The PHY's SYSCLK terminal provides a 49.152-MHz interface clock to the TSB15LV01's SCLK terminal. All control and data signals are synchronized to, and sampled on, the rising edge of SYSCLK. The CTL0 and CTL1 terminals form a bidirectional control bus, which controls the flow of information and data between the PHY and TSB15LV01. The D0-D7 terminals form a bidirectional data bus, which is used to transfer status information, control information, or packet data between the devices. In s100 operation only the D0 and D1 terminals are used; in s200 operation only the D0-D3 terminals are used; and in s400 operation all D0-D7 terminals are used for data transfer. When the PHY is in control of the D0-D7 bus, unused Dn terminals are driven low during s100 and s200 operations. When the TSB15LV01 is in control of the D0-D7 bus, unused Dn terminals are ignored by the PHY. The LREQ terminal is used by the TSB15LV01 to send serial service requests to the PHY in order to request access to the serial-bus for packet transmission. The PHY normally controls the CTL0-CTL1 and D0-D7 bidirectional buses. The TSB15LV01 is allowed to drive these buses only after it has been granted permission to do so by the PHY. There are three operations that may occur on the PHY-link interface: link service request, data transmit, and data receive. The TSB15LV01 issues a service request when it wants to request the PHY to gain control of the 1394 serial bus in order to transmit a packet. The PHY may initiate a status transfer autonomously. The PHY initiates a receive operation whenever a packet is received from the 1394 serial bus. The PHY initiates a transmit operation after winning control of the serial bus following a bus request by the TSB15LV01. The transmit operation is initiated when the PHY grants control of the interface to the TSB15LV01. For details on how the PHY/link interface operates, consult the 1394 specification.
2.1.5
Enabling the Transmission of Video
2.1.5.1 Enabling Isochronous Video Streaming
To enable the streaming of isochronous video data, the function control registers must be configured properly, as described in section 3.3.3.1.2. The last register to be written should be the CAMERA_POWER_CNTL register, which asserts the CAM_POWER terminal (activating the CCD circuitry, if the signal is utilized), begins processing data from the AFE interface, and begins transmitting isochronous data.
2.1.5.2 Enabling One-Shot Video Transmission
Alternatively to transmitting an isochronous stream of video data, the one-shot feature can be utilized. With this feature, a single frame is sent using the same isochronous packet structure. It is activated by asserting the one_shot field of the ONE_SHOT_CNTL register. Note that in order to use this feature, isochronous video streaming should be disabled via the ISO_EN_CNTL register. When the feature is activated, the device automatically powers up the camera, activates isochronous transmission, sends a single image, then deactivates isochronous data and powers down the camera.
2.2 Sensor Interface
The TSB15LV01 obtains its raw video data from a charge-coupled device (CCD) sensor. This information is sent to an analog front end (AFE) that amplifies the analog video information provided by the CCD, performs correlated double sampling (CDS) and gain, and converts it to a digital format recognizable by the TSB15LV01.
2-7
Figure 2-1 shows the top-level signal flow in the sensor interface.
Drive Signals CCD Drivers CCD Sensor Pixel Pulses CCD I/F Sample/Hold I/F Black Clamp I/F TSB15LV01 Serial I/F Video Data I/F AFE
Figure 2-1. Top-Level Sensor Interface Signal Flow
2.2.1
CCD Interface
2.2.1.1 General Description
The video data is sourced by a CCD sensor. The TSB15LV01 contains a CCD timing generator for the approved sensors. Some of these signals must pass through a driver circuit to undergo voltage shifting. Because the timing of the CCD interface is closely integrated with the timing of the analog front end, this topic is discussed jointly in section 2.2.3, CCD/AFE Timing.
2.2.1.2 Configuring for Different CCD Sensors
The TSB15LV01 is designed to be used with several different CCD sensors and contains the necessary logic to drive each of them. The ccd_sel field of the AFE_SETUP_CNFG register must be set to the correct value, identified in section 3.3.3.2, Configuration Registers. If this field selects the TC237 CCD, field color_bw of VIDEO_OPTIONS_CNFG register must also be set to black and white, since this is a black and white sensor. Otherwise, it should be set to color.
2.2.1.3 External Pulse Drivers
As with nearly all CCD applications, the TSB15LV01 requires use of a dedicated driver chip for the vertical drive pulses. This device performs level-shifting to high-voltage rails, as well as some logic functions. Table 2-10 shows the approved sensors with their recommended driver devices. Table 2-10. Approved CCD Sensors and Recommended Drivers
SENSOR Sony ICX084AK 1/3" color sensor Sony ICX098AK 1/4" color sensor Sharp LZ24BP 1/4" color sensor TI TC237 1/3" black and white sensor DRIVER Sony CXD1267AN Sony CXD1267AN Sony CXD1267AN or Sharp LR36685N TI TMC57253
In addition, an external driver for horizontal pulses is required in order to drive the capacitive load of the CCD sensor. A CMOS inverter device is recommended, such as the TI SN74LVCU04A.
2.2.2
Analog Front End Interface
Circuitry must be used in a TSB15LV01-based system that processes the pixel pulses received from the CCD and converts them to digital data readable by the TSB15LV01. This circuit is referred to as the analog front end (AFE). The TSB15LV01 is designed to be used with the TLV990 AFE device.
2-8
2.2.2.1 AFE Function
Figure 2-2 shows the block diagram of the TLV990.
AVDD1-5 CLVDO CLCCD CLREF RPD RBD RMD DVDD DIVDD OE Three State Latch D0
INT. REF. Clamp 1.2 V REF CDS/ MUX
CCDIN
8-Bit ADC
PGA 10
8-Bit ADC
10-Bit ADC
D9 RESET CLK SV SR BLKG OBCLP STBY ADDOS
VIDEOIN PGA Regulator
Optical Black Pixel Limits
Offset Register
Offset Register
Digital Averager/ Filter
Timing and Control Logic
DACO1
10-Bit ADC
DAC REG SCKP CS SCLK SDIN
DACO2
8-Bit DAC
DAC REG
Serial Port
VSS AGND1-5
DGND
DIGND
Figure 2-2. TLV990 Block Diagram At the beginning of each image line, the AFE resets the dc bias of the incoming video data. It then performs correlated double sampling (CDS), which effectively extracts the video data from the pixel pulse and removes the most significant forms of noise. It then enters a programmable gain array (PGA) prior to conversion to digital form via a 10-bit analog/digital converter (ADC). Before and after the PGA are offset correction circuits that maximize dynamic range of the video signal. The one prior to the PGA is considered the coarse adjustment offset, while the one after the PGA is considered the fine adjustment offset. These offset values are based either on the internal black clamping process or on values received from the TSB15LV01 via the serial interface, depending on the brightness mode. Digital/analog converters (DACs) in the AFE circuitry decode these values and apply them to the video signal flow. The TLV990 also contains a number of other registers that control operation of the device, which the TSB15LV01 is able to program. The TSB15LV01 contains an interface to the AFE that is divided into four sections. The first is the sample/hold interface, which provides the timing signals necessary for sampling of the pixel pulses. The second is the black clamping interface. The third is the serial interface, which programs control values into the AFE. The fourth is the video data interface, which is a 10-bit parallel port that receives the video from the ADC after it has been converted.
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2.2.2.2 Sample/Hold Interface
This interface provides the signals necessary for dc bias clamping and correlated double sampling (CDS) of the CCD pixel pulse. The AFE should be capacitively coupled to the CCD output signal. At the beginning of each image line, the AFE must clamp this signal to a reference voltage, thereby properly setting the dc bias of the incoming video data. To accomplish this, the TSB15LV01 sends the CLAMP terminal low. This occurs during the CCD's dummy pixel output, prior to the active data pixels. CLAMP is held low only for a few pixels, but due to very low leakage current from this node, the clamped bias holds for the duration of the line. During the active pixels portion of the line, reset pedestal and video data pedestal of the pixel pulses are sampled. The data pedestal is subtracted from the reset pedestal prior to amplification. The SR signal supplies the sampling pulse for the reset pedestal, while SV supplies the sampling pulse for the video data pedestal.
2.2.2.3 Black Clamping Interface
The dc offset is directly related to the brightness of the image. The dc offset can be controlled automatically or manually. When the TSB15LV01 is configured for autobrightness, it utilizes the black clamping feature of the TLV990. In autobrightness mode, the AFE uses an internal feedback loop to adjust the offset. It adjusts the black pixels until they match a digital value received from the TSB15LV01 via the serial interface. When the TSB15LV01 sends the OBCLP terminal low, the AFE begins to acquire the digital pixel values produced by the ADC, average them, and compare them to the black reference value. If the values are not equal, the AFE attempts to make them equal by altering the fine adjustment offset value, which changes the offset that is summed with the signal prior to the ADC. If the necessary adjustment is out of range for the fine offset, the AFE can use the coarse adjustment. The adjustments are applied until the pixel data equals the black reference value. The TSB15LV01 sends the OBCLP pulse during a time in which it knows the selected CCD is sending its black pixels. The number of lines per image and the number of pixels per line that should be sampled are stored in internal registers, programmed by the TSB15LV01 from the lines_smpl and pix_smpl fields, respectively, of the VIDEO_OPTIONS_CNFG register. See section 2.6.6, Brightness, for more information on dc offset control.
2.2.2.4 Serial Interface
The TLV990 contains several control registers. The serial interface of the TSB15LV01 provides a means of programming these values. Table 2-11 shows the values that are transmitted from the TSB15LV01 to the TLV990.
2-10
Table 2-11. Values Transmitted to AFE via Serial Interface
Source Within the TSB15LV01 Gain/exposure control loop (auto mode) TLV990 Target Register PGA register User DAC1 register Coarse dc offset DAC register Fine dc offset DAC register Optical black level register Optical black calibration register Covered in Section... 2.6.8, Gain and Exposure 2.6.7, Anti-Blooming
GAIN_CNTL register (manual mode) Blooming_value field of DAC_OFFSET_CNFG register
Brightness control loop (auto mode)
BRIGHTNESS_CNTL register (manual mode)
Brightness control loop (auto mode)
BRIGHTNESS_CNTL register (manual mode) Offset_level field of DAC_OFFSET_CNFG register Lines_smpl field of AFE_SETUP_CNFG register pixels_smpl field of AFE_SETUP_CNFG register
2.6.6, Brightness ,g
Gain and offset (brightness) sources depend on whether the respective modes are manual or automatic. The lines_smpl and pix_smpl fields of AFE_SETUP_CNFG register control the lines per image, and pixels per line, respectively, that are to be averaged (see section 2.2.2.3, Black Clamping Interface, for more information). The offset_level field of the DAC_OFFSET_CNFG register is the digital black reference value to which the dc offset is normalized. The TLV990 contains two general purpose DACs with external outputs. One of these, DAC1, can be used to convert a digital code (sourced from the TSB15LV01's DAC_OFFSET_CNFG register) to an analog signal, which can be routed to the sensor for use in antiblooming. The second DAC, DAC2, is generally not utilized, but can be controlled from the TSB15LV01 as well. See the TLV990 data sheet (literature number SLAS298) for more information about the target registers. The timing of the AFE serial interface is shown in Figure 2-3. Table 2-12 shows the AFE interface timing parameters.
S_CLK
S_CS
S_DATA
tsu tcl
th
Figure 2-3. AFE Serial Interface Timing Table 2-12. AFE Interface Timing Parameters
MIN tsu tcl th TYP 82 164 82 MAX UNIT ns ns ns
In Figure 2-3, two words are being written by the TSB15LV01 to the AFE. Each word represents a value being written to an AFE register address. The number of values written depends on the mode. For example, if autoexposure is being used, different parameters are being programmed to the AFE than if the mode is manual.
2-11
2.2.2.5 Video Data Interface
A 10-bit parallel interface is used to move the video data from the AFE ADC to the TSB15LV01. Data is clocked in with ADCLK.
2.2.3
CCD/AFE Timing
2.2.3.1 General Description
The timing of these interfaces takes into consideration two asynchronous, periodic events. The first event is the integration of light in the sensor, which occurs at a frequency dictated by the camera's frame rate. The second event is the beginning of a 1394 isochronous cycle, which determines when video data is transmitted from the TSB15LV01. The TSB15LV01 reconciles these two events in a way that produces optimal video quality while minimizing the amount of memory necessary to store the pixel data. When the integration cycle is complete, the pixel charges are transferred out of the active region of the sensor. For the TC237, which is a full frame transfer CCD, this is the parallel transfer of charge from the image area to the storage area. For the other sensors, which are interline CCDs, this is the transfer of charge to the vertical shift registers. Several dummy/black lines are subsequently clocked and processed by the AFE. At this point, timing waits for the next 1394 isochronous cycle. As data is clocked out onto the serial bus, more data is needed and therefore clocked out of the sensor and into the TSB15LV01. This method of processing reconciles the two asynchronous, periodic events. It also minimizes the size of the internal FIFO needed to buffer the data stream, since data is only taken from the CCD as it is needed. The data is packetized on the bus such that there is a period of time between frames in which no data remains to be clocked out of the sensor, and no data is being transferred on the serial bus. During such periods of inactivity, the TSB15LV01 may clock pixels out of the serial register while ignoring the resulting processed data from the AFE. This results in lines of blank dummy pixels being clocked out of the CCD at regular intervals. This action is taken because extended idle periods can allow the CCD serial register to accumulate dark current. Clocking these pixels also keeps a constant dc level at the AFE ac-coupling capacitor. Figures 2-4 through 2-12 show the sensor interface for each approved sensor. For each sensor, there are four views shown. The first view contains the timing for the acquisition and transfer of a full frame of video. The second view is a magnified portion of the start frame. The third view is a magnified portion of the start of a line, while the fourth view is a magnified portion of the horizontal drive pulses. In some cases, the pulses are identical for the different sensor options, so they are consolidated under a single figure. In all figures, the mode is YUV 4:1:1 640 x 480, at 30 frames per second, with minimum exposure time. Note that these signals are intended to be processed by one of the recommended driver devices before reaching the CCD. In addition to level-shifting, these devices perform logic on the signals. Therefore, the signals at the sensor are different than the ones shown in Figures 2-4 through 2-12.
2-12
tframe
ABD_XSUB ABSP_XSG SAG/XV1 XV2 IAG/XV3 SRG/H1 H2 RST CLAMP OBCLP SR SV ADCLK Figure 2-7
Figure 2-4. Sensor Interface Timing for ICX098/LZ24BP Sensor, Full Frame Table 2-13. ICX098/LZ24BP Full Frame Timing Parameters
MIN tframe Frame period (@ 30 frames per sec.) TYP 33.3 MAX UNIT ms
2-13
tframe
ABD_XSUB ABSP_XSG SAG/XV1 XV2 IAG/XV3 SRG/H1 H2 RST CLAMP OBCLP SR SV ADCLK Figure 2-8
Figure 2-5. Sensor Interface Timing for ICX084 Sensor, Full Frame Table 2-14. ICX084 Full Frame Timing Parameters
MIN tframe Frame period (@ 30 frames per second) TYP 33.3 MAX UNIT ms
2-14
tframe
ABD_XSUB ABSP_XSG SAG/XV1 XV2 IAG/XV3 SRG/H1 H2 RST CLAMP OBCLP SR SV ADCLK Figure 2-9
Figure 2-6. Sensor Interface Timing for TC237 Sensor, Full Frame Table 2-15. TC237 Full Frame Timing Parameters
MIN tframe Frame period (@ 30 frames per second) TYP 33.3 MAX UNIT ms
Figures 2-7 through 2-9 depict the start of a frame. Each block of pulses on the horizontal drive signals following the pulse on ABSP_XSG represents a line of video data. The gap between the fourth and fifth lines is the waiting period for the next 1394 isochronous cycle. Because the integration cycle is asynchronous with the 1394 isochronous cycle, this gap continually changes in length.
2-15
texpo txh ABD_XSUB ABSP_XSG SAG/XV1 XV2 IAG/XV3 SRG/H1 H2 RST CLAMP OBCLP SR SV ADCLK
26 Pulses
Figure 2-10 Lines of Video
Waiting for Next 1394 Isochronous Cycle
Figure 2-7. Sensor Interface Timing for ICX098/LZ24BP Sensor, Start of Frame Data Table 2-16. ICX098/LZ24BP Frame Start Timing Parameters
MIN txh texpo ABD_XSUB hold Exposure time 292 TYP 11 MAX UNIT s s
2-16
texpo txh ABD_XSUB ABSP_XSG SAG/XV1 XV2 IAG/XV3 SRG/H1 H2 RST CLAMP OBCLP SR SV ADCLK 42 s
26 Pulses
Figure 2-10
Lines of Video
Waiting for Next 1394 Isochronous Cycle
Figure 2-8. Sensor Interface Timing for ICX084 Sensor, Start of Frame Table 2-17. ICX084 Frame Start Timing Parameters
MIN txh texpo ABD_XSUB hold Exposure time 292 TYP 11 MAX UNIT s s
2-17
texpo txh
ABD_XSUB ABSP_XSG SAG/XV1 XV2 IAG/XV3 SRG/H1 H2 RST CLAMP OBCLP SR SV ADCLK 42 s 523 Pulses Figure 2-11 Lines of Video Waiting for Next 1394 Isochronous Cycle
Figure 2-9. Sensor Interface Timing for TC237 Sensor, Start of Frame Table 2-18. TC237 Frame Start Timing Parameters
MIN txh texpo tptd ABD_XSUB/ABSP_XSG hold Exposure time Parallel transfer duration 294 42 TYP 11 MAX UNIT s s s
2-18
txv1h txv2h txv2d txv3d ABD_XSUB ABSP_XSG SAG/XV1 XV2 IAG/XV3 SRG/H1 H2 RST CLAMP OBCLP SR SV ADCLK tod toh tcd tch Figure 2-12 txv3h thd
Figure 2-10. Sensor Interface Timing for ICX098/LZ24BP/ICX084 Sensor, Start of Line Table 2-19. ICX098/LZ24BP/ICX084 Line Start Timing Parameters
MIN txv1h txv2h txv3h txv2d txv3d thd tcd tch tod toh SAG/XV1 hold time XV2 hold time IAG/XV3 hold time XV2 delay time IAG/XV3 delay time Horizontal drive delay following line transfer CLAMP delay following start of horizontal drive CLAMP hold time Time between OBCLP and end of line OBCLP hold time TYP 2.7 2.7 2.7 900 900 350 280 652 1.3 160 MAX UNIT s s s ns ns ns ns ns s ns
2-19
thd txv1h ABD_XSUB ABSP_XSG SAG/XV1 XV2 IAG/XV3 SRG/H1 H2 RST CLAMP OBCLP SR SV ADCLK tcd txv3h tod tch Figure 2-12
toh
Figure 2-11. Sensor Interface Timing for TC237 Sensor, Start of Line Table 2-20. TC237 Line Start Timing Parameters
MIN txv1h txv3h thd tcd tch tod toh SAG/XV1 hold time IAG/XV3 hold time Horizontal drive delay following line transfer CLAMP delay following start of horizontal drive CLAMP hold time Time between clamp and OBCLP OBCLP hold time TYP 820 810 1.8 40 244 488 1.056 MAX UNIT ns ns s ns ns ns s
Figure 2-12 depicts the horizontal drive pulses. Note that this diagram reflects the timing when all fields in the CCD_PULSE_CNFG and CCD_PULSE_CNFG registers are set to 00. This is the nominal position. Table 2-21 shows the horizontal drive timing parameters.
2-20
th1hw ABD_XSUB ABSP_XSG SAG/XV1 XV2 IAG/XV3 SRG/H1 H2 RST CLAMP OBCLP SR SV ADCLK trh tsrh talw
th1lw
tsvh tahw
Figure 2-12. Sensor Interface Timing for All Sensors, Horizontal Drive Table 2-21. Horizontal Drive Timing Parameters
MIN th1hw th1lw trh tsrh tsvh tahw talw SRG/H1 high width SRG/H1 low width RST hold time SR hold time SV hold time ADCLK high width ADCLK low width TYP 40 40 20 20 20 40 40 MAX UNIT ns ns ns ns ns ns ns
2.2.3.2 Pulse Tuning
Maintaining maximum dynamic range of the CCD image requires that the AFE's CDS clamp and sample pulses correspond perfectly to the analog output of the CCD, and thus to the CCD clock pulses as well. This means that after a camera has been built, the CCD/AFE drive pulses need to be tuned into their proper positions. Signals that need to be adjusted include RST, H2, SRG/H1, SR, SV, and ADCLK. For each of these signals, a field exists in the CCD_PULSE_CNFG and CDS_PULSE_CNFG registers. These 6-bit fields contain values that represent the amount of delay relative to the nominal position. Each field has a maximum value of 3 F, which corresponds to approximately 16 to 18 ns.
2.3 STAT Interface
Three status terminals are provided: STAT0, STAT1, and STAT2. These terminals can be configured to provide different functions. The function of a STATn terminal is changed by writing a new signal code into the corresponding field of the STATUS_CNFG register. When one or more of the terminals is configured as a signal input, the host can read the input value by reading the st_stat field of the STATUS_CNFG register. Similarly, when one or more of the terminals is configured as a signal output, the host can change its value by writing to the st_stat field. The functions provided by the STAT interface are shown in Table 2-22.
2-21
Table 2-22. Status Terminal Functions Determined by STATn Register Fields
SIGNAL CODE I/O SIGNAL STAT0 0 1 2 3 4 5 6 7 I O O O O O O O Signal input. Configures this terminal as an input that can be read from the host via the 1394 serial bus. The input value can be found in bit 0 of the st_stat field of the STATUS_CNFG register. Signal output. Configures this terminal such that it outputs the value of bit 0 in the st_stat field of the STATUS_CNFG register, which can be written to by the host. Cycle_out. This is the link's cycle clock. It is based on the timer controls and the cycle-start messages received from the 1394 bus cyclemaster. ITF_Empty. This signal is high when the ITF (isochronous transfer FIFO) is empty. Line sync pulse. Pulses at the start of every horizontal line Clamping pulse Active region pulse. Vertical sync signal that pulses once per image frame. Focus motor select. Writing this value to the STAT0 register tells the TSB15LV01 that a motor is present that will derive its control from the FOCUS_CNTL register. STAT1 0 1 2 3 4 5 6 7 I O O O O O O O Signal input. Configures this terminal as an input that can be read from the host via the 1394 serial bus. The input value can be found in bit 1 of the st_stat field of the STATUS_CNFG register. Signal output. Configures this terminal such that it outputs the value of bit 1 in the st_stat field of the STATUS_CNFG Register, which can be written to by the host. Cycle_start. Isochronous cycle start indicator. Signals the beginning of an isochronous cycle by pulsing for one clock period. Cycle_Done. When high, an arbitration gap has been detected on the 1394 bus after the reception of a cycle-start packet. This indicates that the isochronous cycle is over. Line sync pulse. Pulses at the start of every horizontal line. Iso_Enable. Indicates that isochronous 1394 packet transmission has been activated. Active region pulse. Vertical sync signal that pulses once per image frame. Zoom motor select. Writing this value to the STAT1 register tells the TSB15LV01 that a motor is present that will derive its control from the ZOOM_CNTL register. STAT2 0 1 2 3 4 5 6 7 I O O O O O O O Signal input. Configures this terminal as an input that can be read from the host via the 1394 serial bus. The input value can be found in bit 2 of the st_stat field of the STATUS_CNFG register. Signal output. Configures this terminal such that it outputs the value of bit 2 in the st_stat field of the STATUS_CNFG register, which can be written to by the host. Dm_Rdy. Indicates that a 1394 isochronous stream is ready to be sent on the next iso cycle. While high, indicates that a valid video line is being clocked out of the CCD. If low, indicates that dummy lines are being clocked out. Line sync pulse. Pulses at the start of every horizontal line 6-MHz clock Active region pulse. Vertical sync signal that pulses once per image frame Iris motor select. Writing this value to the STAT2 register tells the TSB15LV01 that a motor is present that will derive its control from the IRIS_CNTL register.
2-22
2.4 Motor Control Interface
The TSB15LV01 provides control for three stepper motors that can be used for focus, zoom, and iris functions. Steppers provide exact, high-tolerance control. Note also that while the interface provides for focus, zoom, and iris motors, any motor with a similar function can be attached to those interfaces, such as pan or tilt.
2.4.1
Motor Driver Timing
Only one set of drivers is provided, and control of the motors is multiplexed. The STAT0, STAT1, and STAT2 terminals, when configured for stepper motors as discussed in section 2.3 STAT Interface, select which motor is being controlled. When a STATn terminal goes low, all motor terminal signals (PHASEx_n, IR_SIG, MOTOR_PLUS/MINUS) are intended for the motor corresponding to the STATn terminal in question. If only one STATn terminal is configured as a motor select, that terminal is held low continually, while the others perform the function for which they were programmed. If more than one STATn terminal is configured as a motor select, their outputs alternately pulse low. For example, if two motors are being used, each STATn terminal is active half the time. If three motors are being used, each STATn terminal is active one third the time. This is shown in Figure 2-13.
STAT0 (Enables Focus Motor)
STAT1 (Enables Zoom Motor) STAT2 (Enables Iris Motor) PHASE_xn MOTOR_PLUS/MINUS TERMINALS FOCUS POSITION ZOOM POSITION IRIS POSITION
Device Power Up
New Value Written to ZOOM_CNTL Register
Pushbuttons For Focus and Zoom are Pressed Simultaneously
Figure 2-13. STATn Motor Select Pulses In Figure 2-13, each pulse in the last three lines does not indicate a signal pulse, but rather a movement in the position of the motors. Also, the pulses for phase_xn are not literal. The pulses actually driven are as defined by the stepper drive table used by the TSB15LV01, shown in Table 2-23.
2-23
Table 2-23. Stepper Drive Table
MOTOR DRIVE TERMINAL PHASE1_A STEP 1 STEP 2 STEP 3 STEP 4 1 0 0 1 PHASE1_B 0 1 1 0 PHASE2_A 1 1 0 0 PHASE2_B 0 0 1 1
The table shows values for the forward direction. The values are driven in a cyclical pattern when the motor is to be driven forward. The values are driven cyclically in reverse when the motor is to be moved backwards. The default state for the drive terminals is high, resulting in the outgoing value of 1111. It is intended that the outputs will be used as inputs to an inverting drive circuit; therefore, the default state of the stepper drive windings is that both ends are grounded. As a result, the motor and driver assembly only draw current when actively stepping in one direction or another. Note that only one STATn terminal is needed per motor, such that if less than three motors are being used, the remaining STATn terminals can be used for other functions.
2.4.2
Positioning System
Positioning for the steppers is based on a linear scale from 000h to 3FFh (10 bit). Upon power up of the device, it seeks to align the physical motor position with the initial starting value stored in the corresponding field of the MOTOR_POS_CNFG register (ir_zoom, ir_focus, or ir_iris fields). To do this, the device first moves the stepper to a physical reference point indicated by the IR_SIG terminal. IR_SIG is assumed to have a position feedback signal attached to it, such as an infrared sensor. This point is likely near the beginning or end of the mechanism's motion. If the IR_SIG terminal is high when the device powers up, it indicates that the mechanism is in a position beyond the position reference. The TSB15LV01 steps the mechanism down until the terminal goes low. If the terminal is already low at power up, the motor steps the mechanism up until the terminal goes high, and then steps it back one. After each motor has been positioned at its reference, the TSB15LV01 associates those positions with the values in the corresponding fields of the MOTOR_POS_CNFG register. Using these values as starting points, it moves each motor to the position indicated in the value field of the feature control register corresponding to that motor (ZOOM_CNTL, FOCUS_CNTL, or IRIS_CNTL). For example, a camera can be preset to focus at a certain distance. After the TSB15LV01 has realigned the motor at the beginning or end of the focus mechanism movement, it moves the motor to the predetermined focus setting. Subsequently, any value written to the feature control registers that is not equal to the current position will cause the motor to step toward that value. Each incremental value written to the register represents one step the motor moves. When the motor position matches the value in the feature control register, the stepper shuts off, and the windings are grounded. Power up and movement of the motor can be seen in Figure 2-13. Initial positioning of the motors following power up occurs in sequential order, with the first motor pulling itself into position, then the second motor, and then the third. After this, all motor step sequences are multiplexed, which effectively causes the motors to move simultaneously.
2.4.3
Pushbutton Interface
The MOTOR_PLUS and MOTOR_MINUS terminals are designed as pushbutton inputs. Driving one of these terminals high causes the value field of the current motor's feature control register to increment or decrement accordingly. In response, the corresponding motor moves forward or backward. Holding one of these inputs high will cause the motor to step continuously. The motor to which activity on MOTOR_PLUS/MINUS is applied is determined by which motor select (STATn terminal) is currently low. If only one motor is used, only one motor select is present, allowing pushbuttons to be attached directly to the terminals.
2-24
If more than one motor is being used, it is necessary to multiplex them. As a result of the alternating STATn pulses, the switches are scanned on a periodic basis. There is no need for a debounce circuit, because the buttons are scanned at a fixed rate of approximately 30 Hz.
2.5 EEPROM Interface
An external EEPROM with serial port interface (SPI) interface is required for TSB15LV01 operation. The entire address space of the TSB15LV01 accessible from the 1394 bus is stored there. The EEPROM must provide 4096 bits of memory, such as a 512 x 8 configuration. The interface is designed to be used with the Atmel AT25040 or Xicor X25040. It utilizes a four-wire interface consisting of a chip select, an input, an output, and a clock. The 1394 bus uses 48-bit addresses. Since this is too large of a contiguous address space for most conventional EEPROMs, the TSB15LV01 converts these addresses into an 8-bit form called the internal address. The conversion is shown in section 3, Address Space. All registers are stored in the external EEPROM device. However, upon power up of the TSB15LV01, the feature control registers and the configuration registers are copied from the EEPROM into registers resident in the TSB15LV01 device. This includes all address space between F0F00800h and F0F00F24h. From that moment on, 1394 bus accesses to this address space apply to the registers in the TSB15LV01. For address space outside this range, bus accesses are executed on the EEPROM device. As a result, the role of the EEPROM with respect to these registers is to store default values, these values are saved when power is removed from the device. The values in the TSB15LV01 registers are never written back to the EEPROM by the TSB15LV01 device, and the bus is not capable of changing them since all normal run-time bus accesses to this memory space operate on the TSB15LV01. This allows for the loading of power up initialization values into the EEPROM. However, it is possible to write values to the EEPROM for any address location once a value of 12345678h has been written to the write_protect_control field of the EEPROM_CNFG register. This value is known as the write-protect control code. Once this control code has been written to the device, all register space accesses will operate upon the EEPROM. Writes operate on both the EEPROM and the TSB15LV01. Reads operate on the EEPROM only. This mechanism provides a way to program new initialization values. Figures 2-14 and 2-15 show the read and write timing (Table 2-24) associated with the TSB15LV01 EEPROM interface.
Tcssu EEPROM_CS TCL 0 EEPROM_SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Tcsd
INSTRUCTION EEPROM_SI
BYTE ADDRESS 7 6 5 4 3 2 1
8 9th BIT of ADDRESS
HIGH IMPEDANCE EEPROM_SO 7 MSB 6
Figure 2-14. Read Timing
IIIIIIIII IIIIIIIII
0 DATA OUT 5 4 3 2 1 0 2-25
II II
Tcssu EEPROM_CS TCL 0 EEPROM_SCLK 1 2 3 4 5 6 7 8
Tcsd
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
INSTRUCTION EEPROM_SI
BYTE ADDRESS 7 6 5 4 3 2 1 0 7 6 5
DATA IN 4 3 2 1 0
EEPROM_SO
tcssu tcsd tcl
EEPROM CS setup time EEPROM CS delay time Clock period
2.6 Video Signal Processor
After the CCD image data is received from the AFE, it is processed by the video signal processor (VSP). The core of the VSP is a digital signal processor (DSP) that conducts numerous essential algorithms, discussed in the sections below. Most of the video processing features present in the TSB15LV01 are included as part of the digital camera specification. As such, they are controllable via the feature control registers (see section 3.3.3.1.3, Feature Control Registers). A few others are specific to the TSB15LV01 and can be controlled with the TSB15LV01 configuration registers.
2.6.1
De-Mosaicing
The CCD image data is comprised of individual component pixels, each of which is pure red, green, or blue. The VSP de-mosaics them, a process in which they are grouped to form composite pixels that fit the RGB standard. Several adjustments can be made in the configuration registers that affect how the sensor data is compiled into the RGB image frame. These are shown in Table 2-25. Table 2-25. CCD Sensor Processing Adjustments
ADJUSTMENT H-Center and V-Center fields of CCD_OPTICS_CNFG register pix_shp fields of VIDEO_OPTIONS_CNFG register COMMENT The TSB15LV01 receives an image size greater than 640 x 480 pixels from the CCD. These fields determine which 640 x 480 rectangle is processed and transmitted to the host. Determines whether component pixels are grouped as squares or as L-shaped pieces. L-shaped pixels give a higher resolution image than square pixels but can create a jagged edge effect.
Additional information for each of these adjustments can be found in section 3.3.3.2, Configuration Registers.
2-26
III III
8 9th BIT of ADDRESS
HIGH IMPEDANCE
Figure 2-15. Write Timing Table 2-24. EEPROM Interface Timing Parameters
MIN TYP 652 652 1.304 MAX UNIT ns ns s
2.6.2
Brightness
The brightness of the image is directly related to the DC offset of the image data in the AFE. This feature can be controlled automatically or manually. When brightness is configured for automatic control via the BRIGHTNESS_CNTL register, the TSB15LV01 utilizes the TLV990's black clamping feature. This feature sets the offset at the beginning of every image frame, adjusting it so that the black pedestal is equal to the value stored in the offset_level field of the DAC_OFFSET_CNFG register. (See section 2.2.2.3, Black Clamping Interface, for more information.) Brightness can also be controlled by setting the offset manually. If the TSB15LV01's auto-brightness feature is disabled, it divides the value field of the BRIGHTNESS_CNTL register into coarse (most significant eight bits) and fine (least significant eight bits) and sends those values directly to the AFE. If autobrightness is used, there are two parameters sent to TLV990 that affect how black clamping is performed. Both are found in the AFE_SETUP_CNFG register. The first, found in the lines_smpl field, informs the TLV990 how many lines per image should be included in the black clamp averaging. The second, found in the pix_smpl field, informs the TLV990 how many samples per line should be included in the averaging. The TLV990 datasheet can provide more information on the use of these values.
2.6.3
Gain and Exposure
Gain refers to the gain stage of the AFE, while exposure refers to the CCD image integration time. These parameters can be configured manually using their corresponding feature control registers, GAIN_CNTL and EXPOSURE_CNTL (Figure 2-16). Alternatively, they can be controlled automatically using an internal feedback loop. This loop samples 4048 pixels within an image and calculates the average pixel luminance. It compares this value with the value stored in the auto-expo field of the AUTO_ADJ_CNFG register, adjusting the gain and exposure time accordingly. A control input to this block, stored in the expo_delta field of the AUTO_ADJ_CNFG register, regulates the speed at which adjustments are made to the algorithmic filter. This value must be adjusted to provide adequate damping for the feedback loop.
2-27
AFE CCD/ Driver Clamp and CDS Coarse Offset Adjust PGA
+ -
Fine Offset Adjust Gain
A/D
Black Clamp Control
TSB15LV01
Pixel Saturation Simulator SHUTTER_CNTL register - value field (backlight compensation)
Algorithmic Comparator Adjustment with Digital Filter
AUTO_ADJ_CNFG register - expo_deltafield AUTO_ADJ_CNFG register - -expo_ref field (used with auto gain/exposure)
Serial Encoder
Gain GAIN_CNTL register - value field EXPOSURE_CNTL register - value field (used with manual gain exposure)
Image Clear Pulse (ABD_XSUB)
CCD Pulse Generator
Figure 2-16. Gain and Exposure Automatic and Manual Controls The location of the sampled pixels is dictated by the backlight compensation feature, described in section 2.6.9. Gain and exposure have a similar effect on the image. In other words, the effect of a reduction in gain can be countered by a proportional increase in exposure, and vice versa. Therefore, there are many combinations of gain and exposure settings that produce a similar image. High gain settings can amplify any noise that may have been introduced to the analog signal, prior to or during its conversion to digital. Because of this, the autogain/exposure loop generally seeks to keep gain as low as possible, adjusting the exposure parameter to properly expose the image. Gain is increased when the exposure parameter alone is not sufficient to produce a proper exposure.
2.6.4
Sharpness and Saturation
Processing on the sharpness and saturation parameters is performed by the VSP. They are adjustable within reasonable boundaries by altering values in their corresponding feature control registers. The sharpness control utilizes a continuous extrapolation filter, providing smooth sharpness control. Saturation refers to color saturation, as opposed to saturation of a CCD charge.
2-28
2.6.5
White Balance
This feature alters the degree to which red and blue CCD component pixels are weighted to form composite pixels. Green is considered constant. White balance often needs to be adjusted when image lighting changes. For example, when white balance has been configured for incandescent lighting, it will need adjustment if taken to an area with fluorescent or natural lighting. This is because the spectral content of these light sources differs from incandescent light. White balance can be adjusted manually or automatically, selectable in the WHITE_BALANCE_CNTL register. If the feature is set as manual, it corresponds directly with the value in that register. The host can then alter the white balance value as it wishes. For example, it could implement its own autobalance feature. If the feature is set as automatic, an internal adjustment is used. This algorithm assumes that all incoming colors have a relatively equal amount of red, green, and blue, and makes small, iterative adjustments to the white balance. This provides very good white balance in most situations without necessitating manual adjustments. However, if red or blue is dominant in the image for a moderate period of time, the assumption is incorrect, and the image will begin to noticeably discolor.
2.6.6
Gamma
Gamma correction can be implemented to compensate for nonlinearities in cathode ray tubes, which in most cases is the device that is used to display the image. It is possible to turn this feature off, since some high-end CRTs are capable of providing their own gamma correction. The gamma correction implemented by the TSB15LV01 incorporates a correction factor equivalent to the 0.45 analog gamma standard.
2.6.7
YUV Conversion
If the transfer mode is one that uses the YUV color space, the VSP converts the RGB pixels into YUV. RGB to YUV color space conversion for gamma-corrected, fully-saturated RGB video is: Y = 0.257 R + 0.504 G + 0.098 B + 16 Cb = -0.148 R - 0.291 G + 0.439 B + 128 Cr = 0.439 R - 0.368 G - 0.071 B + 128 This matrix is approximated in the TSB15LV01, which processes video data as 8-bit digital values, by fractionalizing the coefficients with respect to 8 bits: Y = (66/256) R + (129/256) G + (25/256) B + 16 Cb = - ( 38/256) R - (74/256) G + (112/256) B + 128 Cr = (112/256) R - (94/256) G - ( 18/256) B + 128 This approximation introduces less than one least significant bit of error.
2-29
2.6.8
Antiblooming
Blooming occurs when a CCD pixel becomes saturated and overflows into surrounding pixels. This can appear on the image display as discoloration or bright speckles. CCD sensors usually have a means of allowing a cutoff level to be set, above which charge is not allowed to exceed. Setting this antiblooming level just below the saturation level prevents charge overflow. The Sony ICX084, Sony ICX098, and the Sharp LZ24BP perform this function internally. The TI TC237, however, requires the level to be set externally. To provide this voltage reference, one of the general-purpose DACs on the AFE can be utilized. The TSB15LV01 designates DAC1 as the antiblooming DAC. The DAC output can be used to set the TC237 antiblooming level. The antiblooming feature must be activated by setting the bloom_en field of the DAC_OFFSET_CNFG register. Once this has been done, the value of the blooming_value field of the DAC_OFFSET_CNFG register will be sent to the TLV990. This will set the antiblooming voltage level for the CCD sensor. The value of the other general-purpose DAC, DAC2, can be set as well via the DAC2_en and DAC2_value fields of the same corresponding registers.
2.6.9
Backlight Compensation
The TSB15LV01 provides a way to compensate for situations in which a forefront object appears dark due to excessive light in the background. This is accomplished by extracting more gain/exposure samples from image regions in which the intended object resides (see 2.6.3, Gain and Exposure). Hot regions for which this feature can be activated include those shown in Table 2-26. Table 2-26. Backlight Compensation Hot Regions
VALUES OF SHUTTER_CNTL REGISTER 0 1 2 3 4 5 6 HOT REGION Matrix (No compensation). Pixel samples are evenly spaced. Circle. All the pixel samples are taken from a circle in the center of the image. The region is 128 pixels wide. Circle, averaged. Half the samples are taken inside the same circle as circle mode, half the samples are taken outside the circle. Head and Shoulders. All the pixel samples are taken from a region that would be occupied by a person sitting in front of the camera. Top third. All the pixel samples are taken from the top third of the image. Bottom third. All the pixel samples are taken from the bottom third of the image. Middle third. All the pixel samples are taken from the middle third of the image.
The hot region for backlight compensation is selected by the SHUTTER_CNTL register. As shown in Table 2-26, the feature can be disabled, causing the gain/exposure loop samples to be evenly distributed throughout the image.
2.6.10 White Spot Compensation
CCD sensors occasionally have nonuniformities that cause some pixels to build a charge significantly greater than the light that is activating them, due to leakage current in the pixel. In a black and white sensor, this causes white spots that appear out of place. In a color sensor, it can result in discoloration or speckles. The TSB15LV01 can be configured to compensate for this error using one of two built-in filters. The first filter is a median filter. For every pixel, the median filter considers its value and the pixels on either side and replaces the original pixel with the median of the three. This removes any single-pixel abnormalities from the pixel stream. The other filter is the nonlinear interpolation filter. It compares a pixel to the ones before and after it. If it is significantly different, such that it exceeds a preset threshold, it is thrown out and replaced by the average of the two surrounding pixels. Alternatively, white spot compensation can be disabled. The white spot compensation filter is chosen by the filter field of the CCD_OPTICS_CNFG register. The threshold for how deviant a pixel is allowed to be before it is discarded by the nonlinear interpolation filter is determined by the value of the filter_limit field, also in the CCD_OPTICS_CNFG register.
2-30
The tradeoff in using one of these filters lies in the fact that the filters are indiscriminate in discarding single-pixel abnormalities. Single-pixel abnormalities may be noise, or they may be a valid part of the image. As a result, the filters remove white spots but also result in some degradation of the image due to some loss of spacial high-frequency response. The median filter is more extreme in this regard. The nonlinear interpolation filter has an amplitude threshold that defines how extreme the abnormality must be before it is discarded, giving the user more control of the tradeoff. The median filter is more effective in removing white spots, but if it has an adverse effect on the sharpness of the image, it may be desirable to use the nonlinear interpolation filter and adjust the filter limit, or disable the filter altogether.
2.6.11 Test Pattern
The TSB15LV01 can send a continuous image consisting of color bars and linear ramps. The test pattern is activated using the test_en field of the TEST_CNFG register. It is shown in Figure 2-17.
Figure 2-17. TSB15LV01 Built-In Test Pattern The upper portion of the test pattern consists of solid vertical bars of white, yellow, cyan, green, magenta, red, blue, and black (in order, as shown in Figure 2-17). The bottom portion consists of horizontal bars of white, red, green, and blue, with luminance increasing from left to right. The luminance value increases by one every two pixels (RGB 640 x 480 mode). The test pattern image is subject to changes in saturation, white balance, sharpness, and gamma control. It is not affected by changes in gain, brightness, exposure, or backlight compensation. The test pattern is useful during camera development for determining whether image problems are originating after the VSP (1394 interface) or before it (sensor interface). That is, it can verify functionality between the host and the TSB15LV01 device, isolating image problems to the CCD or AFE interface.
2-31
2-32
3 Address Space
The address space for the TSB15LV01 is divided into four areas. The first consists of registers and ROM required for any 1394 node, called 1394 memory. The second area consists of registers that reflect the level of capability of the digital camera, known as the inquiry registers. These registers are required by the Digital Camera Specification. Both 1394 memory and the inquiry registers are considered read-only. The third and fourth areas consist of registers that can be read for camera status or written to for camera control. These are called the control registers and configuration registers. The control registers are dictated by the Digital Camera Specification, while the configuration registers are unique to the TSB15LV01. Table 3-1 gives a summary of the various register groupings referred to throughout this document. Table 3-1. TSB15LV01 Register Groupings
REGISTER GROUP NAME 1394 registers Inquiry registers DESCRIPTION Registers required for 1394 nodes. Registers that describe the capability of the digital camera, allowing host to determine availability of features provided for by the Digital Camera Specification. Registers that control basic camera features, such as frame rate, output format, and video parameters. Registers that control unique TSB15LV01 features and functions. REQUIRED BY 1394 Standard Digital Camera Specification Digital Camera Specification TSB15LV01-specific DOCUMENTATION Section 3.3.1 Section 3.3.2
Control registers Configuration registers
Section 3.3.3.1 Section 3.3.3.2
The TSB15LV01 provides a memory map consistent with v1.04 of the 1394 Digital Camera Specification, and implements most of the features provided for by that document. There are a few features that are not implemented. This functionality should always be indicated in the inquiry registers. Recommended values are provided in Section 3.3.2. The inquiry registers themselves are always valid, since their function is to tell the host which features are valid and which are not, and since they are read-only by definition. The only registers that are disabled for nonsupported features are control registers.
3.1 1394 Node Memory Architecture
To understand the memory allocation of the TSB15LV01, it is useful to first understand the addressing structure for 1394 nodes in general. 1394 addresses consist of the components shown in Table 3-2. Table 3-2. 1394 Address Components
COMPONENT Bus ID Node ID Destination offset LENGTH 10 bits 6 bits 48 bits COMMENT Identifies the 1394 bus Identifies the node within the bus Identifies the address within the node
The values of the first two components are environment-dependent. Note that address values shown throughout section 3 consist only of the 48-bit destination offset. In the case of the TSB15LV01, locations in "1394 memory" have a base destination offset of FFFF F000 0000h. In contrast, the inquiry, control, and configuration registers have a base destination offset of FFFF F0F0 0000h. Various registers are determined by adding an additional offset value to the destination offset. The memory space of a typical 1394 node consists of a small collection of registers that exist at fixed addresses, called initial register space, and a number of dynamic memory structures called directories and leaves. Directories contain information and pointers to more directories and leaves. Leaves are blocks of memory that contain information but do not point to other directories or leaves.
3-1
These elements form a tree structure. A certain amount of freedom is granted to the developer of the 1394 node, allowing a variety of structures within the architecture guidelines. The root node for this structure exists in part of the initial register space, called the root directory. The root directory tree allotted in the TSB15LV01 is shown in Figure 3-1.
Root Directory
Node Unique ID Leaf
Unit Directory
Unit Dependent Directory
Vendor Name Leaf
Model Name Leaf
Figure 3-1. TSB15LV01 Root Directory Tree The TSB15LV01 memory structure is based on this dynamic concept but assumes that all memory locations are fixed. Although all the components are present, including initial register space, root directory tree, and the appropriate pointers, these structures are assigned a fixed memory location. All memory locations can be legally addressed by their fixed addresses without needing to derive them from the corresponding base address and offset. (The exceptions to this rule are the vendor and model name leaves, discussed in section 3.3.1.2, Configuration ROM). This scheme provides efficient usage of EEPROM memory. Because this memory structure is implemented in EEPROM, it is the responsibility of the system designer to ensure that it exists according to the maps shown in section 3. See section 2.5, EEPROM Interface, for more information.
3.2 Top-Level Memory Maps
The tables below give a top-level map of the TSB15LV01 address space. Along with the 1394 bus address, an internal address is given. This is the address scheme used inside the TSB15LV01 and also in interfacing with the EEPROM (see sections entitled Physical Location of Register Data and EEPROM Interface for more information). Table 3-3. Top-Level Memory Map: 1394 Memory (Core CSRs)
1394 BUS ADDRESS FFFF F000 0000 FFFF F000 0004 FFFF F000 0008 FFFF F000 000C FFFF F000 0010 FFFF F000 0014 FFFF F000 0018 FFFF F000 001C FFFF F000 0200 FFFF F000 0204 FFFF F000 0208 FFFF F000 020C FFFF F000 0210 0 1 2 3 5 6 8 9 10 11 12 INTERNAL ADDRESS
3-2
Table 3-4. Top-Level Memory Map: 1394 Memory (Device Configuration ROM)
1394 BUS ADDRESS FFFF F000 0400 FFFF F000 0404 FFFF F000 0408 FFFF F000 040C FFFF F000 0410 FFFF F000 0414 FFFF F000 0418 FFFF F000 041C FFFF F000 0420 FFFF F000 0424 FFFF F000 0428 FFFF F000 042C FFFF F000 0430 FFFF F000 0434 FFFF F000 0438 FFFF F000 043C FFFF F000 0440 FFFF F000 0444 FFFF F000 0448 FFFF F000 044C FFFF F000 0450 FFFF F000 0454 FFFF F000 0458 FFFF F000 045C FFFF F000 0460 FFFF F000 0464 FFFF F000 0468 FFFF F000 046C FFFF F000 0470 FFFF F000 0474 FFFF F000 0478 FFFF F000 047C FFFF F000 0480 FFFF F000 0484 INTERNAL ADDRESS 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 MODEL NAME LEAVES VENDOR NAME LEAF UNIT DEPENDENT DIRECTORY UNIT DIRECTORY NODE UNIQUE ROOT DIRECTORY BUS INFO BLOCK REGISTER NAME
3-3
Table 3-5. Top-Level Memory Map: Inquiry Registers
1394 BUS ADDRESS FFFF F0F0 0000 FFFF F0F0 0100 FFFF F0F0 0180 FFFF F0F0 0200 FFFF F0F0 0204 FFFF F0F0 0208 FFFF F0F0 020C FFFF F0F0 0210 FFFF F0F0 0214 FFFF F0F0 0400 FFFF F0F0 0404 FFFF F0F0 0408 FFFF F0F0 0500 FFFF F0F0 0504 FFFF F0F0 0508 FFFF F0F0 050C FFFF F0F0 0510 FFFF F0F0 0514 FFFF F0F0 0518 FFFF F0F0 051C FFFF F0F0 0520 FFFF F0F0 0524 FFFF F0F0 0528 FFFF F0F0 0580 FFFF F0F0 0584 FFFF F0F0 0588 INTERNAL ADDRESS 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 111 87 88 89 BASIC_FUNC_INQ FEATURE_HI_INQ FEATURE_LO_INQ BRIGHTNESS_INQ EXPOSURE_INQ SHARPNESS_INQ WHITE_BAL_INQ HUE_INQ SATURATION_INQ GAMMA_INQ SHUTTER_INQ GAIN_INQ IRIS_INQ FOCUS_INQ ZOOM_INQ PAN_INQ TILT_INQ RATE INQ RATE_INQ REGISTER NAME CAMERA INITIALIZATION FORMAT_INQ VIDEO_MODE_INQ
3-4
Table 3-6. Top-Level Memory Map: Control Registers
1394 BUS ADDRESS FFFF F0F0 0600 FFFF F0F0 0604 FFFF F0F0 0608 FFFF F0F0 060C FFFF F0F0 0610 FFFF F0F0 0614 FFFF F0F0 0618 FFFF F0F0 061C FFFF F0F0 0620 FFFF F0F0 0624 FFFF F0F0 0800 FFFF F0F0 0804 FFFF F0F0 0808 FFFF F0F0 080C FFFF F0F0 0810 FFFF F0F0 0814 FFFF F0F0 0818 FFFF F0F0 081C FFFF F0F0 0820 FFFF F0F0 0824 FFFF F0F0 0828 FFFF F0F0 0880 FFFF F0F0 0884 FFFF F0F0 0888 INTERNAL ADDRESS 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 112 113 114 REGISTER NAME CUR_V_FRM_RATE_CNTL CUR_V_MODE_CNTL CUR_V_FORMAT_CNTL ISO_CHANNEL/SPEED_CNTL CAMERA_POWER_CNTL ISO_EN_CNTL RESERVED ONE_SHOT_CNTL RESERVED RESERVED BRIGHTNESS_CNTL EXPOSURE_CNTL SHARPNESS_CNTL WHITE_BAL_CNTL RESERVED SATURATION_CNTL GAMMA_CNTL SHUTTER_CNTL (BACKLIGHT COMPENSATION) GAIN_CNTL IRIS_CNTL FOCUS_CNTL ZOOM_CNTL RESERVED RESERVED
Table 3-7. Top-Level Memory Map: Configuration Registers
1394 BUS ADDRESS FFFF F0F0 0F00 FFFF F0F0 0F04 FFFF F0F0 0F08 FFFF F0F0 0F0C FFFF F0F0 0F10 FFFF F0F0 0F14 FFFF F0F0 0F18 FFFF F0F0 0F1C FFFF F0F0 0F20 FFFF F0F0 0F24 INTERNAL ADDRESS 127 116 117 118 119 120 121 122 123 124 REGISTER NAME EEPROM_CNFG TEST_CNFG CCD_PULSE_CNFG CDS_PULSE_CNFG AUTO_ADJ_CNFG DAC_OFFSET_CNFG CCD_OPTICS_CNFG STATUS_CNFG VIDEO_OPTIONS_CNFG MOTOR_POSITION_CNFG
3.3 Register Detail
3.3.1 1394 Memory
The following sections define the CSR (Command and Status register) and ROM locations implemented in the TSB15LV01. For more information on the way 1394 CSR architectures are implemented, see section 3.1, 1394 Node Memory Architecture, and the 1394a specification.
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3.3.1.1 Implemented Core CSRs
The TSB15LV01 implements the following core CSRs, defined in the IEEE 1212-1991 standard (upon which the 1394 standard is based). These are shown in Table 3-8. Table 3-8. Implemented Core CSRs
Offset FFFF F000 0000h FFFF F000 0004h FFFF F000 0008h FFFF F000 000Ch FFFF F000 0010h FFFF F000 0014h FFFF F000 0018h FFFF F000 001Ch SPLIT_TIMEOUT_HI SPLIT_TIMEOUT_LO 0-7 8-15 STATE_SET NODE_IDS RESET_START 16-23 24-31 STATE_CLEAR
The TSB15LV01 implements the following serial-bus-dependent CSRs, defined by the 1394 standard. These are shown in Table 3-9. Table 3-9. Serial-Bus-Dependent CSRs
Offset FFFF F000 0200h FFFF F000 0204h FFFF F000 0208h FFFF F000 020Ch FFFF F000 0210h BUSY_TIMEOUT 0-7 8-15 16-23 CYCLE_TIME 24-31
3.3.1.2 Configuration ROM
The TSB15LV01 implements Configuration ROM defined in the IEEE 1212-1991 standard, shown in Table 3-10. Table 3-10. Base Configuration ROM
NAME Offset FFFF F000 0400h FFFF F000 0404h Bus info block FFFF F000 0408h FFFF F000 040Ch FFFF F000 0410h FFFF F000 0414h FFFF F000 0418h Root directory y FFFF F000 041Ch FFFF F000 0420h FFFF F000 0424h 03h 06h 0Dh 11h 0004h 0-7 04h 31h (1) 0010 rsv 8-15 crc_length 33h (3) FFh node_vendor_id chip_id_lo CRC module_vendor_ID value module_sw_version (070198h) Node_Unique_ID indirect_offset (000002h) unit_directory offset (000004h) max_rec 16-23 39h (9) 24-31 34h (4) rsrv chip_id_hi rom_crc_value
Note that the last two quadlets of Table 3-10 are entries that point to a leaf and a directory, respectively. The leaves are shown in Table 3-11 and Table 3-12. Table 3-11. Node_Unique_ID Leaf
NAME Node_ Unique_ID leaf _ q_ Offset FFFF F000 0428h FFFF F000 042Ch FFFF F000 0430h 0-7 0002h node_vendor_ID chip_id_lo 8-15 16-23 CRC chip_id_hi 24-31
3-6
Table 3-12. Unit Directory
NAME Offset FFFF F000 0434h Unit directory FFFF F000 0438h FFFF F000 043Ch FFFF F000 0440h 12h 13h D4h 0-7 0003h 8-15 16-23 CRC unit_spec_ID (=0x00A02D) unit_sw_version (=0x000100) unit_dependent_directory offset 24-31
The last quadlet of the unit directory in Table 3-12 contains an offset to another directory, shown below in Table 3-13. Table 3-13. Unit-Dependent Directory
NAME Offset FFFF F000 0444h Unit dependent directory Unit-dependent FFFF F000 0448h FFFF F000 044Ch FFFF F000 0450h 0-7 40h 81h 82h 8-15 16-23 CRC command_regs_base vendor_name_leaf model_name_leaf 24-31 unit_dep_info_length
In the unit-dependent directory, command_regs_base points to the base address of the inquiry, control, and configuration registers (FFFF F0F0 0000h). It is expressed in terms of quadlets, relative to the base address of initial register space (FFFF F000 0000h). Two leaves are provided that should contain ASCII strings representing the camera vendor and model names. These are referred to as the vendor name leaf and model name leaf. The unit-dependent directory also contains pointers to these leaves. Vendor_name_leaf specifies the number of quadlets from the address of the vendor_name_leaf entry (FFFF F000 044Ch) to the address of the vendor name leaf. Model_name_leaf specifies the number of quadlets from the address of the model_name_leaf entry (FFFF F000 0450h) to the address of the model name leaf. The format of the vendor and model name leaves is shown in Table 3-14 and Table 3-15. Table 3-14. Vendor Name Leaf
NAME Offset FFFF F000 0454h Vendor name leaf FFFF F000 0458h FFFF F000 045Ch FFFF F000 0460h char_0 00h char_1 0-7 leaf_length 00 0000h 0000 0000h char_2 char_3 8-15 16-23 CRC 24-31
Table 3-15. Model Name Leaf
NAME Offset FFFF F000 0464h FFFF F000 0468h Model name leaf FFFF F000 046Ch FFFF F000 0470h FFFF F000 0474h Model name leaf FFFF F000 047Ch FFFF F000 0480h FFFF F000 0480h char_n - 2 char_0 char_4 char_8 ... char_n - 1 NUL 00h char_1 char_5 0-7 leaf_length 00 0000h 0000 0000h char_2 char_6 ... char + n - 3 NUL char_3 char_7 8-15 16-23 CRC 24-31
Notice that these leaves have length that varies according to the length of the ASCII strings. A total of 13 quadlets is provided for these two leaves. Because each leaf contains a three-quadlet header, seven quadlets are available for ASCII characters. These seven quadlets can be appropriated in any way between the two name leaves, providing that the directory length field in each leaf reflects the appropriation. Also, the vendor_name_leaf and model_name_leaf fields in the unit-dependent directory leaf must point to their appropriate leaves. This is especially important for the model name leaf, since its address can move depending on the length of the vendor name leaf.
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3.3.2
Inquiry Registers
The Digital Camera Specification provides for a wide variety of features a vendor can choose to implement. However, a compliant camera must include a series of registers that indicate exactly which of the standard features are supported. These inquiry registers also provide some basic information about the way in which the camera supports these features, such as whether an automatic control exists. These values are determined during camera system development and must be written to the EEPROM when cameras are built. The TSB15LV01 supports the majority of features provided under the Digital Camera Specification. Note that setting these values does not change any camera functionality. It only changes what the host perceives the capability of the camera to be. The inquiry registers have a base destination offset of FFFF F0F0 0000h. In the tables that follow, all listed offsets are specified in bytes, relative to this base address. Most fields serve as Boolean flags that indicate availability of the feature, with a 1 indicating availability. Other types of fields are marked accordingly.
3.3.2.1 Video Format Inquiry Register
The video format describes the format of the video information being transmitted by the TSB15LV01 across the 1394 serial bus. The only format supported by v1.04 of the digital camera specification is VGA non-compressed data, which has a maximum of 640 x 480 resolution. Space is reserved for future expansion to other formats. Table 3-16. Video Format Memory Map
NAME FORMAT_INQ OFFSET 100h Format_0 0-7 Format_x 8-15 16-23 Rsrv 24-31
Table 3-17. Video Format Register Proper Values for TSB15LV01
NAME FORMAT_INQ OFFSET 100h 1 0-7 XXXXXXX 8-15 XXXXXXXX 16-23 XXXXXXXX 24-31 XXXXXXXX
Table 3-18. Video Format Field Descriptions
FIELD NAME Format_0 Format_x Reserved BITS 0 1..7 8..31 DESCRIPTION VGA noncompressed format. (Maximum 640 x 480) Reserved for other formats Reserved (all zero)
3-8
3.3.2.2 Video Mode Inquiry Registers
The video mode describes the type of data output by the digital camera. These modes correspond with those described in section 2.1.2.1, Isochronous Packet Format/Protocol. The base address is FFFF F0F0 0000h. All listed offsets are specified in bytes, relative to this base address. All fields are Boolean flags; a 1 indicates availability. Table 3-19. Video Mode Memory Map
NAME VIDEO_MODE_INQ_0 (640 x 480 VGA Format) OFFSET 100h
Mode_0 Mode_1 Mode_2 Mode_3 Mode_4 Mode_5 Mode_x
0-7
8-15
16-23 Rsrv
24-31
VIDEO_MODE_INQ_0 184h..19Fh
Reserved for other formats
Table 3-20. Video Mode Proper Values for TSB15LV01
NAME VIDEO_MODE_INQ_0 (640 x 480 VGA Format) OFFSET 100h 0-7 1 1 1 1 1 1 XX XXXXXXXX 8-15 XXXXXXXX XXXXXXXX 16-23 XXXXXXXX XXXXXXXX 24-31 XXXXXXXX XXXXXXXX
VIDEO_MODE_INQ_0 184h..19Fh
Table 3-21. Video Mode Field Descriptions
FIELD NAME Mode_0 Mode_1 Mode_2 Mode_3 Mode_4 Mode_5 Mode_x Reserved BITS 0 1 2 3 4 5 6..7 8..31 DESCRIPTION 160 x 120 YUV(4:4:4) Mode (24 bit/pixel) 320 x 240 YUV(4:2:2) Mode (16 bit/pixel) 640 x 480 YUV(4:1:1) Mode (12 bit/pixel) 640 x 480 YUV(4:2:2) Mode (16 bit/pixel) 640 x 480 RGB Mode (24 bit/pixel) 640 x 480 Y (Mono) Mode (8 bit/pixel) Reserved for other modes Reserved (all zero)
3.3.2.3 Video Frame Rate Inquiry Registers
These registers describe the availability of the various frame rates for the digital camera. A separate register is provided for each combination of format and mode, and this relationship is shown in Table 3-22. The base address is FFFF F0F0 0000h. All listed offsets are specified in bytes, relative to this base address. All fields are Boolean flags; a 1 indicates availability.
3-9
Table 3-22. Video Frame Rate Memory Map
NAME RATE_INQ_0 (160 x 120 YUV (4:4:4)) OFFSET
Frame Rate_0 Frame Rate_0 Frame Rate_0 Frame Rate_1 Frame Rate_1 Frame Rate_1 Frame Rate_2 Frame Rate_2 Frame Rate_2
0-7
Frame Rate_3 Frame Rate_3 Frame Rate_3 Frame Rate_4 Frame Rate_4 Frame Rate_4 Frame Rate_x Frame Rate_x
8-15
16-23 Rsrv
24-31
200h
RATE_INQ_1 (320 x 240 YUV (4:2:2))
204h
Rsrv
Frame Rate_0
Frame Rate_1
Frame Rate_2
Frame Rate_3
Frame Rate_4
Frame Rate_0 Frame Rate_0
Frame Rate_1 Frame Rate_1
Frame Rate_2 Frame Rate_2
Frame Rate_3 Frame Rate_3
Frame Rate_4 Frame Rate_4
Frame Rate_5
Table 3-23. Video Frame Rate Proper Values for TSB15LV01
NAME RATE_INQ_0 RATE_INQ_1 RATE_INQ_2 RATE_INQ_3 RATE_INQ_4 RATE_INQ_5 OFFSET 200h 204h 208h 20Ch 210h 214h 0-7 X0111 X1111 X1111 X1110 X1110 XXX XXX XXX XXX XXX 8-15 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 16-23 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 24-31 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
X 1 1 1 1 0 XX
Table 3-24. Video Frame Rate Field Descriptions
FIELD NAME FrameRate_0 FrameRate_1 FrameRate_2 FrameRate_3 FrameRate_4 FrameRate_5 FrameRate_x FrameRate_y Reserved BITS 0 1 2 3 4 5 5..7 6..7 6..31 Reserved 3.75 fps 7.5 fps 15 fps 30 fps 60 fps Reserved for another frame rate Reserved for another frame rate Reserved (all zero) DESCRIPTION
3-10
Frame Rate_x
RATE_INQ_5 (640 x 480 Mono)
214h
Frame Rate_x
RATE_INQ_4 (640 x 480 RGB)
210h
Frame Rate_x
RATE_INQ_3 (640 x 480 YUV (4:2:2))
20Ch
Frame Rate_x
RATE_INQ_2 (320 x 240 YUV (4:1:1))
208h
Rsrv
Rsrv
Rsrv
Rsrv
3.3.2.4 Basic Function Inquiry Register
This register describes the availability of some top-level features. The base address is FFFF F0F0 0000h. The listed offset is specified in bytes, relative to this base address. All fields are Boolean flags; a 1 indicates availability. Table 3-25. Memory Map for Basic Function Register
NAME BASIC_FUNC_INQ OFFSET 400h 0-7 Rsrv 8-15 cam_power_inq 16-23 one_shot_inq Rsrv Memory_ Channel 24-31 XXXX 0000 24-31
Table 3-26. Basic Function Register Proper Values for TSB15LV01
NAME BASIC_FUNC_INQ OFFSET 400h 0-7 XXXXXXXX 8-15 XXXXXXXX 16-23 1 X X 1 XXXX
Table 3-27. Field Descriptions for Basic Function Register
FIELD NAME Reserved cam_power_inq Reserved one_shot_inq Reserved memory_channel BITS 0..15 16 17..18 19 20..27 28..31 Reserved Camera process power on/off capability Reserved One shot transmission capability Reserved Maximum memory channel number (N) Memory channel number 0 = Factory setting memory 1 = Memory Ch 1 2 = Memory Ch 2 : N = Memory Ch N If 0000, user memory is not available. DESCRIPTION
3-11
3.3.2.5 Feature Presence Inquiry Registers
These registers indicate the availability of some low level features. The base address is FFFF F0F0 0000h. All listed offsets are specified in bytes, relative to this base address. All fields are Boolean flags; a 1 indicates availability. Table 3-28. Memory Map for Feature Presence Registers
NAME FEATURE_HI_INQ OFFSET 404h 0-7 8-15 16-23 Rsrv 24-31
Brightness Exposure Sharpness White_Balance Hue Saturation Gamma Shutter Gain Iris Focus
FEATURE_LO_INQ
408h
Zoom Pan Tilt
Rsrv
Table 3-29. Feature Presence Registers Proper Values for TSB15LV01
NAME FEATURE_HI_INQ FEATURE_LO_INQ OFFSET 404h 408h ? 00 0-7 XXXXX 8-15 XXXXX XXXXXXX 16-23 XXXXXXXX XXXXXXXX 24-31 XXXXXXXX XXXXXXXX 1 1 1101 111??
Table 3-30. Field Descriptions for Feature Presence Registers
FIELD NAME Brightness Exposure Sharpness White_Balance Hue Saturation Gamma Shutter Gain Iris Focus Zoom Pan Tilt BITS 0 1 2 3 4 5 6 7 8 9 10 11..31 0 1 2 DESCRIPTION Brightness control Exposure control Sharpness control White Balance control Hue control Saturation control Gamma control Shutter control Gain control Iris control Focus control Reserved Zoom control Pan control Tilt control
3..31 Reserved On the TSB15LV01, the shutter register controls the backlight compensation feature. The proper setting of these bits depends on whether the designer has implemented focus, zoom, and iris motorized controls on the camera.
3.3.2.6 Feature Elements Inquiry Registers
These registers indicate the availability of features provided in the Digital Camera Specification. All registers are supported except hue, pan, and tilt, and this is reflected in the proper values in Table 3-31. (Note that pan and tilt features can still be supported, as described in section 2.4, Motor Control Interface).
3-12
The base address is FFFF F0F0 0000h. All listed offsets are specified in bytes, relative to this base address. All fields are Boolean flags; a 1 indicates availability. Table 3-31. Memory Map for Feature Elements Inquiry Registers
NAME BRIGHTNESS_INQ OFFSET
Presence
0-7
Readout On/Off Auto Manual
8-15 min_value
16-23
24-31 max_value
500h
Presence
Presence
WHITE_BAL_INQ
50Ch
Readout On/Off Auto Manual
Readout On/Off Auto Manual
SHARPNESS_INQ
508h
Presence
Readout On/Off Auto Manual
EXPOSURE_INQ
504h
min_value
max_value
min_value
max_value
min_value
max_value
Presence
Presence
51Ch
Readout On/Off Auto Manual
SHUTTER_INQ
Presence
Readout On/Off Auto Manual
GAMMA_INQ
518h
Readout On/Off Auto Manual
SATURATION_INQ
514h
Readout On/Off Auto Manual
HUE_INQ
510h
Presence
min_value
max_value
min_value
max_value
min_value
max_value
min_value
max_value
Presence
Presence
Presence
Presence
On the TSB15LV01, the shutter register controls the backlight compensation feature The proper setting of these bits depends on whether the designer has implemented focus, zoom, and iris motorized mechanisms on the camera, and the individual characteristics of those mechanisms.
Readout On/Off Auto Manual
TILT_INQ
588h
Readout On/Off Auto Manual
PAN_INQ
584h
Readout On/Off Auto Manual
ZOOM_INQ
580h
Readout On/Off Auto Manual
FOCUS_INQ
528h
Readout On/Off Auto Manual
524h
Presence
IRIS_INQ
Readout On/Off Auto Manual
GAIN_INQ
520h
Presence
min_value
max_value
min_value
max_value
min_value
max_value
min_value
max_value
min_value
max_value
min_value
max_value
3-13
Table 3-32. Feature Elements Registers Proper Values for TSB15LV01
NAME BRIGHTNESS_INQ EXPOSURE_INQ SHARPNESS_INQ WHITE_BAL_INQ HUE_INQ SATURATION_INQ GAMMA_INQ SHUTTER_INQ GAIN_INQ IRIS_INQ FOCUS_INQ ZOOM_INQ PAN_INQ OFFSET 500h 504h 508h 50Ch 510h 514h 518h 51Ch 520h 524h 528h 580h 584h 1 1 1 1 0 1 1 1 1 ? ? ? 0 XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX 0-7 1011 1011 1001 1011 XXXX 1001 1001 1001 1001 1001 1001 1001 XXXX 8-15 000 000 000 000 XXX 000 000 000 000 ??? ??? ??? XXX 16-23 24-31 1FF 1FF 0FF 0FF XXX 0FF 001 007 0FF ??? ??? ??? XXX
TILT_INQ 588h 0 XXX X X X X XXX XXX On the TSB15LV01, the shutter register controls the backlight compensation feature The proper setting of these bits depends on whether the designer has implemented focus, zoom, and iris motorized mechanisms on the camera, and the individual characteristics of those mechanisms.
Table 3-33. Field Descriptions for Feature Elements Registers
FIELD NAME Presence ReadOut On/Off Auto Manual MIN_Value MAX_Value BITS 0 1..3 4 5 6 7 8..19 20..31 Presence of this feature Reserved Capability of reading the value of this feature Capability of switching this feature on and off Auto mode (in which the feature is controlled automatically by camera) Manual mode (in which the feature is controlled directly by user) MIN Value for this feature control DESCRIPTION
MAX Value for this feature control All control values in manual mode can be read. Values cannot be read during auto modes.
3.3.3
Control and Configuration Registers
These registers are used to control the digital camera, as well as allowing the host to read camera status. The control registers are required by the Digital Camera Specification. They control some of the basic camera operations, such as frame rate, output format, and video parameters. The configuration registers are unique to the TSB15LV01. They allow the user to configure features unique to the TSB15LV01 and fine-tune its interface with supporting components. As with the inquiry registers, the control and configuration registers have a base destination offset of FFFF F0F0 0000h. In the tables that follow, all listed offsets are specified in bytes, relative to this base address.
3.3.3.1 Control Registers
As stated earlier, all features provided for by the digital camera specification are listed.
3-14
3.3.3.1.1 Camera Initialize Register
This register is not used on the TSB15LV01. Table 3-34. Camera Initialize Register Memory Map
NAME INITIALIZE OFFSET 000h 0-7 8-15 Rsrv 16-23 24-31
Table 3-35. Camera Initialize Register Field Descriptions
FIELD CODE Rsrv BITS 0..31 Reserved (all zero) DESCRIPTION
3.3.3.1.2 Function Control Registers
These registers control the basic functionality of the camera. The base address is FFFF F0F0 0000h. All listed offsets are specified in bytes, relative to this base address. Table 3-36. Memory Map for Camera Registers
NAME
CUR_V_FRM_RATE_CNTL
OFFSET
600h Video_Format Video_Mode Frame_Rate
0-7
8-15
Rsrv
16-23
24-31
CUR_V_MODE_CNTL
604h
Rsrv
CUR_V_FORMAT_CNTL
608h
Rsrv
ISO_CHANNEL/SPEED_CNTL
60Ch
Iso_Speed
Iso_Chnl
Rsrv
CAMERA_POWER_CNTL
610h
Iso_Enable Cam_Power
Rsrv
ISO_EN_CNTL
614h
Rsrv
RSRV ONE_SHOT_CNTL
618h 61Ch One_Shot
Rsrv Rsrv
RSRV
620h.. 624h
Rsrv
3-15
Table 3-37. Field Descriptions for Camera Registers
FIELD NAME Frame_rate Video_mode Video_format Iso_chnl Iso_speed BITS 0..2 0..2 0..2 0..3 4..5 6..7 Current video mode (Mode_0 .. Mode_7) Current video format (Format_0 .. Format_7) 1394 isochronous channel number for video data transmission (0-15) Reserved 1394 isochronous transmit speed code 0 = s100 1 = s200 2 = s400 This register determines the on/off status of the TSB15LV01. It also directly controls the CAM_POWER terminal of the device, which can be used to control power to the CCD. 1 = power up camera 0 = power down camera. 1 = start isochronous transmission of video data 0 = stop isochronous transmission of video data 1 = only one frame of video data is transmitted. Self-cleared after transmission. Ignored if ISO_EN_CNTL (field iso_en) = 1. DESCRIPTION Current frame rate (FrameRate_0 .. FrameRate_7)
Cam_power
0
Iso_Enable One_shot
0 0
3-16
3.3.3.1.3 Feature Control Registers
These registers control features pertaining to video processing and motor control. The base address is FFFF F0F0 0000h. All listed offsets are specified in bytes, relative to this base address. Table 3-38. Memory Map for Feature Control Registers
NAME BRIGHTNESS_CNTL OFFSET
Presence
0-7
On/Off Manual
8-15 Rsrv
16-23
24-31 Value
800h
Rsrv
Presence
Presence
RSRV SATURATION_CNTL
510h
Presence On/Off Manual
On/Off Manual
WHITE_BAL_CNTL
80Ch
Presence
On/Off Manual
SHARPNESS_CNTL
508h
Rsrv
On/Off Manual
EXPOSURE_CNTL
804h
Rsrv
Rsrv
Value
Rsrv
Value
U_Value
V_Value
Rsrv Rsrv Rsrv Value
814h
Presence
Presence
RSRV ZOOM_CNTL
On/Off Manual
FOCUS_CNTL
828h
On/Off Manual
IRIS_CNTL
824h
Presence
On/Off Manual
GAIN_CNTL
820h
Presence
On/Off Manual
SHUTTER_CNTL
81Ch
Presence
On/Off Manual
GAMMA_CNTL
818h
Rsrv
Rsrv
Value
Rsrv
Rsrv
Value
Rsrv
Rsrv
Value
Rsrv
Rsrv
Value
Rsrv
Rsrv
Value
82Ch.. 87CH
Presence On/Off Manual
Rsrv Rsrv Rsrv Value
580h
RSRV
884h.. 8FCH
Rsrv
On the TSB15LV01, the shutter register controls the backlight compensation feature.
3-17
Table 3-39. Field Descriptions for Feature Registers
FIELD NAME Presence BITS 0 DESCRIPTION Presence of this feature should match the value in the corresponding feature control inquiry register. 0 : Not available 1 : Available Reserved If this field is written to, it turns the feature on or off (1 or 0, respectively). If this field is read, it indicates the on/off status of the feature. (As the inquiry registers indicate, this feature is not enabled for any of the controls in the TSB15LV01.) Indicates whether an automatic mode is active for this feature. Writing to this field changes the mode status. Reading from it indicates the mode status. 0 : Manual 1 : Auto Reserved. Value associated with the feature. If a value is written to this field while A_M_Mode indicates auto mode, this field is ignored. If readout capability for this feature is not available as indicated by the corresponding feature elements inquiry register, the value read from this address has no meaning. U-Value. Target U-value for white balance. If a value is written when A_M_Mode indicates auto mode, this field is ignored. If readout capability for this feature is not available (see Feature Elements Inquiry Register), the value read from this address has no meaning. V-Value. Target U-value for white balance. If a value is written when A_M_Mode indicates auto mode, this field is ignored. If readout capability for this feature is not available (see Feature Elements Inquiry Register), the value read from this address has no meaning.
Reserved ON_OFF
1..5 6
A_M_Mode
7
8..19 Value 20..31
U_Value
8..19
V_Value
20..31
3-18
3.3.3.1.2 Configuration Registers
These registers control features and enhancements that are unique to the TSB15LV01. Most of these features have been addressed in prior sections of this document when applicable. Table 3-40 shows a memory map of the configuration registers. The base address is FFFF F0F0 0000h. All listed offsets are specified in bytes, relative to this base address. Table 3-40. Configuration Register Memory Map
NAME EEPROM_CNFG 0F00h write_ rotect_control write_protect_control OFFSET 0 1 2 3 4 5 6 7
TEST_CNFG
0F04h
test_en
RSRV
CCD_PULSE_CNFG
0F08h RSRV RSRV RSRV
RSRV h2 rst_rg srg_h1 adclk RSRV RSRV RSRV sv sr stable min_gain expo_delta_high expo_ref expo_delta_low
CDS_PULSE_CNFG
0F0Ch
RSRV
AUTO_ADJ_CNFG
0F10h
DAC_OFFSET_CNFG
0F14h
dac2_en
bloom_en dac2_value blooming_value offset_level
RSRV
CCD_OPTICS_CNFG
0F18h RSRV RSRV RSRV
filter_limit filter h-center v-center stat_input stat2 stat1 stat0 pixels_smpl ccd_sel h_inv RSRV v_inv rb_shift color_bw afe_sel ad_inv pix_shp
STATUS_CNFG
0F1Ch
RSRV RSRV RSRV RSRV
AFE_SETUP_CNFG
0F20h
lines_smpl internal_bias
VIDEO_OPTIONS_CNFG
0F22h Hz
RSRV
3-19
Table 3-40. Configuration Register Memory Map (Continued)
NAME MOTOR_POS_CNFG OFFSET 0F24h 0 ir_en 1 RSRV ir_zoom (lsb) ir_focus (lsb) ir_iris (lsb) 2 3 4 5 6 7 ir_zoom (msb) ir_focus (msb) ir_iris (msb)
Table 3-41. Field Descriptions for Configuration Registers
REGISTER EEPROM_CNFG TEST_CNFG FIELD CODE write_protect_ control test_en h2 0 10..15 BITS 0..31 DESCRIPTION Write protect control code. Allows write access to EEPROM. Writing 12345678h unlocks, all other values lock. Color bar test pattern. Setting this bit high enables color bar test pattern H2 pulse position. H2 pulse placement register. 00h : places it at the nominal value for the chosen CCD 3Fh : places it at maximum delay RST pulse position. RST pulse placement register. 00h : places it at the nominal value for the chosen CCD 3Fh : places it at maximum delay SRG/H1 pulse position. SRG/H1 pulse placement register 00h : places it at the nominal value for the chosen CCD 3Fh : places it at maximum delay ADCLK pulse position. ADCLK pulse placement register. 00h : places it at the nominal value for the chosen CCD 3Fh : places it at maximum delay SV pulse position. SV pulse placement register. 00h : places it at the nominal value for the chosen CCD 3Fh : places it at maximum delay SR pulse position. SR pulse placement register. 00h : places it at the nominal value for the chosen CCD 3Fh : places it at maximum delay Number of frames before enabling auto exposure. Gives the image time to stabilize at start-up to prevent oscillation. Minimum gain to saturate CCD Speed control adjustment for auto exposure loop. Applies to frames in which the average luminance is very far away from the level specified in expo_ref. As this value is increased, adjustments are made to gain/exposure more quickly, but setting higher than 11011b can lead to instability. Recommended value is 10011b. Speed control adjustment for auto exposure loop. Applies to frames in which the average luminance is deviant from the level specified in expo_ref, but not to the extent as those to which expo_delta_high applies. As this value is increased, adjustments are made to gain/ exposure more quickly. Recommended value is 010b. Autoexposure reference. Target value used in the auto-gain and -exposure feedback loop. This value is the average luminance of the hot region sampled for the autoexposure loop.
rst CCD_PULSE_CNFG srg/h1
18..23
26..31
adclk
2..7
sv CDS_PULSE_CNFG sr
18..23
26..31
stable min_gain expo_delta_ high AUTO_ADJ_CNFG AUTO ADJ CNFG expo_delta_ medium
0..7 8..15 16..20
21..23
expo_ref
24..31
3-20
Table 3-41. Field Descriptions for Configuration Registers (Continued)
REGISTER FIELD CODE dac2_en BITS 0 DESCRIPTION DAC-2 enable. Enables output to general purpose DAC in AFE 0 : Disabled 1 : Enabled Blooming DAC enable. Enables output to general purpose DAC in AFE, configured to supply blooming reference values to the CCD. 0 : Disabled 1 : Enabled DAC-2 value. Output value for DAC-2 (see DAC-2 Enable, above) Blooming DAC value. Output value for Blooming DAC (see Blooming DAC Enable, above) Black offset reference. Black reference value for digital black clamping. Recommended value is 40h. Filter limit. Specifies the maximum amount of error allowed when the non-linear interpolation white spot compensation filter is used (see filter field). White spot compensation filter select. Selects between two white-spot compensation filters implemented in the TSB15LV01, or de-activates the filter. 0 : Off 1 : Median Filter 2 : Non-linear Interpolation (requires limit value in filter_limit field, above) Lens horizontal center. Indicates the horizontal position of the CCD image's upper left corner, with respect to the left-most active pixels (does not include dummy and black pixels) Lens vertical center. Indicates the vertical position of the CCD image's upper left corner, with respect to the top-most pixels (does not include dummy and black pixels) Status terminal input/output. Indicates the value being read from or written to the STAT2, STAT1, and STAT0 terminals, in order from MSB to LSB. If STAT2, STAT1, or STAT0 is configured as an output, writing to this register changes the output of that terminal. STAT2 configuration. Indicates which STAT input/output is tied to the STAT2 terminal. See Table 2-3-1 for corresponding values. STAT1 configuration. Indicates which STAT input/output is tied to the STAT1 terminal. See Table 2-3-1 for corresponding values. STAT0 configuration. Indicates which STAT input/output is tied to the STAT0 terminal. See Table 2-3-1 for corresponding values. Lines per image. This value is sent to the AFE to tell it the number of lines per image that should be sampled for black clamping. Black clamp sampling. This value is sent to the AFE to tell it the number of pixels per line that should be sampled for black clamping. AFE bias current. Set to 0110b. CCD Select. Indicates the CCD being used with this device. 0 : TI TC237 1/3 B&W sensor (if this is selected, color_bw field in VIDEO_OPTIONS_CNFG must be cleared also. 1 : Sony ICX084AK 1/3 color sensor 2 : Sony ICX098AK 1/4 color sensor; Sharp LZ24BP 1/3 color sensor Always set to 1.
bloom_en
1
DAC_OFFSET_CNFG dac2_value 8..15 blooming_value 16..23 offset_ level filter_limit filter 0..7 8..15 24..31
CCD_OPTICS_CNFG h-center 20..23
v-center st_stat
28..31 5..7
stat2 STATUS_CNFG stat1 stat0 lines_smpl pixels_smpl internal_bias AFE_SETUP_CNFG ccd_sel
13..15 21..23 29..31 0..3 4..7 8..11 12..14
afe_sel
15
3-21
Table 3-41. Field Descriptions for Configuration Registers (Continued)
REGISTER FIELD CODE h_inv BITS 20 DESCRIPTION Horizontal CCD pulse inversion. Inverts all horizontal drive pulses. Recommended value is 0. 0 : No inversion 1 : Inversion Vertical CCD pulse inversion. Inverts all vertical drive pulses. Recommended value is 0. 0 : No inversion 1 : Inversion Red/Blue pixel shift. Indicates whether one-color pixel shift is implemented. Recommended value is 1. 0 : No pixel shift 1 : Pixel shift ADCLK Inversion. Inverts pulses from the ADCLK terminal. Recommended value is 0. 0 : No inversion 1 : Inversion Integration Hz. Reduces the actual frame rate to approximately 83.3% of the one indicated in the CUR_V_FRM_RATE _CNTL register. For example, 30 fps becomes 25 fps. This can be used to reduce flicker in countries using 50-Hz lighting. 0 : No reduction 1 : Reduction Color/BW. Indicates the type of CCD being used. 0 : Black and white CCD (TC237 only) 1 : Color CCD (all others) Pixel shape. Indicates the way CCD pixel data are interpreted. 0 : L-Shaped pixels 1 : Square pixels IR_Enable. Used internally. IR_Zoom. Starting position (IR sensor location) of the zoom stepper motor. IR_Focus. Starting position (IR sensor location) of the focus stepper motor. IR_Iris. Starting position (IR sensor location) of the iris stepper motor.
v_inv
21
rb_shft
22
ad_inv VIDEO_OPTIONS_CNFG Hz
23
24
color_bw
30
pix_shp
31
ir_enable ir_zoom MOTOR_POS_CNFG MOTOR POS CNFG ir_focus ir_iris
0 2..11 12..21 22..31
3-22
4 Electrical Characteristics
4.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range (Unless Otherwise Noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 4 V Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to VCC + 0.5 V Output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Output clamp current, IOK (VO < 0 or VO > VCC (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C Virtual junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. This applies to external input and bidirectional buffers. 2. This applies to external output and bidirectional buffers.
4.2 Recommended Operating Conditions
MIN Supply voltage, VCC Input voltage, VI Output voltage, VO (see Note 3) High-level input voltage, VIH Low-level input voltage, VIL Input transition time, tf and tr (10% to 90%) Operating free-air temperature, TA Virtual junction temperature, TJC (see Note 4) 3 0 0 0.7VCC 0 0 0 0 25 25 NOM 3.3 MAX 3.6 VCC VCC VCC 0.3VCC 25 70 115 UNIT V V V V V ns C C
NOTES: 3. This applies to external output buffers. 4. The junction temperatures listed reflect simulation conditions. The customer is responsible for verifying the junction temperature.
4-1
4.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Free-Air Temperature (Unless Otherwise Noted)
PARAMETER VOH VOL IIL IIH IOZ High-level High level output voltage Low-level Low level output voltage Low-level input current High-level input current High-impedance output current IOH = -12 mA IOH = - 8 mA IOL = 24 mA IOL = 8 mA VI = VIL VI = VIH VO = VCC or GND CAMERA_POWER_CNTL and ISO_EN_CNTL activated CAMERA_POWER_CNTL and ISO_EN_CNTL deactivated 22 mA 27 TEST CONDITIONS MIN 0.8VCC 0.8VCC 0.22VCC 0.22VCC -1 1 20 TYP MAX UNIT V V A A A
ICC(Q)
Static supply current
All VCC and VCC_CORE terminals
All typical characteristics are measured at VCC = 3.3 V and TA = 25C. For ABSP_XSG, IAG_XV3, SAG_XV1, ABD_XSUB, SRG_H1, RST_RG For all other outputs.
4-2
+3.3 V 1 2 3 4 CS VCC S0 HOLD WP SCLK GND SI +3.3V 22pF 1 24.576MHz 10k 0.1uF +3.3 V 0.1uF +3.3 V PAD 2 AT25040 22pF 8 7 6 5
+3.3 V
0.1uF +3.3 V
RESET
5 Application Information
+3.3 V
CLAMP SV SR
80 PHASE1A 79 PHASE1B 78 PHASE2A 77 PHASE2B 76 GND 75 IR_SIG 74 FOCUS_PLUS 73 FOCUS_MINUS 72 ENZ 71 VDD_CAP 70 VCC_CORE 69 PG2 68 EEPROM_SO 67 VCC 66 EEPROM_CS 65 EEPROM_SI 64 EEPROM_SCLK 63 TEST_MODE 62 RESET GND 61
64 DGND 63 DGND 62 DVDD 61 DVDD 60 XO X1 59 58 PLLGND 57 PLLGND 56 PLLVDD 55 FILTER1 FILTER2 54 53 /RESET 52 AVDD 51 AVDD 50 AGND 49 AGND
+3.3 V 1uF 1000pF 6.34k, 1% 1M 56, 1% 56, 1% 1M
OBCLP
SERIAL_CS SERIAL_DATA SERIAL_CLK
TSB15LV01 TSB41LV01
AD_CLK
GND PD4 PD3 PD2 PD1 PD0 VCC CAM_POWER IAG_XV3 VCC_CORE VDD_CAP ABSP_XSG XV2 SAG_XV1 ABD_XSUB GND H2 SRG_H1 RST_RG VCC
10k +3.3 V +3.3 v
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
DGND DGND C/LKLON PC0 PC1 PC2 /ISO CPS DVDD DVDD TESTM SE SM AVDD AVDD AGND
PD9 PD8 PD7 PD6 PD5
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 VCC CLAMP SV SR SH OBCLP GND SERIAL_CS SERIAL_DATA SERIAL_CLK N/C GND ADCLK VCC PD9 PD8 PD7 PD6 PD5 TEST_SE_IN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 LREQ SYSCLK CNA CTL0 CTL1 D0 D1 D2 D3 D4 D5 D6 D7 PD LPS N/C AGND N/C N/C N/C N/C N/C AVDD R1 RO AGND TPBIAS TPA+ TPA- TPB+ TPB- AGND 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 LREQ PG1 SCLK VCC CTL0 CTL1 GND D0 D1 D2 D3 VCC D4 D5 D6 D7 GND STAT0 STAT1 STAT2
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
Shld Shld TPA+ TPA- TPB+ TPB- Gnd Pwr 1394 Connector 56, 1% 56, 1%
8 7 6 5 4 3 2 1
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
270pF PD4 PD3 PD2 PD1 PD0 10k 390k
5.1k, 1%
PD[9:0]
CAM_POWER
IAG_XV3 ABSP_XSG XV2A SAG_XV1 ABD_XSUB H2 SRG_H1 RST_RG
NOTE: PROPER BYPASS CAPACITORS MUST BE ADDED
5-1
Sheet 2
3
48 47 46 45 44 43 42 41 40 39 38 37
1 2 3 4 5 6 7
2
1uF 5.1 k ICX098 HO2 HO1 RG CSUB SUB GND VDD +15V +3.0 V PD0 PD1 PD2 PD3 PD4 PD5 0.01uF
VO1 VO3 VO2A VO2B VL GND OUT
0.1uF
CLREF /CLAMP /SV /SR AGND1 AVDD1 VSS AVDD5 RPD RMD RBD AGND5
D1 MMBD914LT1 3 0.1uF 0.01uF 100k 2200pF 1M 0.1uF
0.1uF
13 14 15 16 17 18 19 20 21 22 23 24
D6 D7 D8 D9 DIVDD DIGND AVDD3 AGND3 DACO1 DACO2 SCKP /OE
+3.3 V
1
14 13 12 11 10 09 08
H2 H2_INV H1_INV
H2_INV
PD6 PD7 PD8 PD9 +3. 3V
5-2
+15V -5.5V 0.1uF 33uF +3.0 V 0.1uF 1uF 0.1uF 1uF +3.0 V 1uF +3. 0v MMBT3904LT1 +15 V 1uF 1uF 0.1uF 0.1uF -5.5V CLAMP SV SR 1 2 3 4 5 6 7 8 9 10 CPP3 VH DCIN XSHT XV2 XV1 XSG1 XV3 XSG2 XV4 1 CXD1267 CPP1 CPP2 DCOUT VSHT VL VO2 VO1 VM VO3 VO4 20 19 18 17 16 15 14 13 12 11
0.1uF
0.01uF
ABD_XSUB SAG_XV1 XV2A ABSP_XSG
IAG_XV3
TLV990
OBCLP
+15 V 33uF
1 2 3 4 5 6 7 8 9 10 11 12 CCDIN VIDEOIN AVDD2 AGND2 DGND DVDD D0 D1 D2 D3 D4 D5
/BLKG /CLVDO /ADDOS AVDD4 AGND4 /OBCLP /STBY /RESET /CS SDIN SCLK ADCCLK
36 35 34 33 32 31 30 29 28 27 26 25
RESET SERIAL_CS SERIAL_DATA SERIAL_CLK AD_CLK
+3.0 V
SRG_H1
H1_INV
PD[9..0]
RST_RG
RG_INV
1 2 3 4 5 6 7 VCC 6_IN 6_OUT 5_IN 5_OUT 4_IN 4_OUT
1_IN 1_OUT 2_IN 2_OUT 3_IN 3_OUT GND
14 13 12 11 10 09 08
SN74LVCU04APW
1uF
6 Mechanical Information
The TSB15LV01 is packaged in a high-performance 80-pin PFC package. The following shows the mechanical dimensions of the PFC package.
PFC (S-PQFP-G80) PLASTIC QUAD FLATPACK
0,50 60
0,27 0,17 41
0,08 M
61
40
80
21
0,13 NOM
1 9,50 TYP 12,20 SQ 11,80 14,20 SQ 13,80 1,05 0,95
20 Gage Plane 0,25 0,05 MIN 0,75 0,45 Seating Plane 0- 7
1,20 MAX
0,08 4073177 / B 11/96
NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026
6-1
6-2
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