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TLC5911 LED DRIVER
SLLS402 - DECEMBER 1999
D D D D
D D
D D
Drive Capability and Output Counts - 80 mA (Current Sink) x 16 Bits Constant Current Output Range - 5 to 80 mA (Current Value Setting for All Output Terminals Using External Resistor and Internal Brightness Control Register) Constant Current Accuracy - 4 % (Maximum Error Between Bits) Voltage Applied to Constant Current Output Terminals - Minimum 0.4 V (Output Current 5 mA to 40 mA) - Minimum 0.7 V (Output Current 40 mA to 80 mA) 1024 Gray Scale Display - Pulse Width Control 1024 Steps Brightness Adjustment - All Output Current Adjustment for 64 Steps (Adjustment for Brightness Deviation Between LED Modules) - Output Current Adjustment by Output (OUT0 to OUT15) for 128 Steps (Adjustment for Brightness Deviation Between Dots) - Brightness Control by 16 Steps Frequency Division Gray Scale Control Clock (Brightness Adjustment for Panel) Gray Scale Clock Generation - Gray Scale Control Clock Generation by Internal PLL or External Input Selectable Clock Invert/Noninvert Selectable at Cascade Operation - Clock Invert Selectable to Reduce Changes in Duty Ratio
D
D D
D D D D D D D
Protection - Watchdog Timer (WDT) Function (Turn Output Off When Scan Signal Stopped) - Thermal Shutdown (TSD) Function (Turn Output Off When Junction Temperature Exceeds Limit) LOD - LED Open Detection (Detection for LED Disconnection) Data Input/Output - Port A (for Data Display) - Clock Synchronized 10 Bit Parallel Input (Schmitt-Triggered Input) - Clock Synchronized 10 Bit Parallel Output (3-State Output) - Port B (for Dot Correction Data) - Clock Synchronized 7 Bit Parallel Input (Schmitt-Triggered Input) - Clock Synchronized 7 Bit Parallel Output Input/Output Signal Level - CMOS Level Power Supply Voltage - 4.5 V to 5.5 V (Logic, Analog and Constant Current) - 3 V to 5.5 V (Interface) Maximum Output Voltage . . . 15 V Data Transfer Rate . . . 20 MHz (Max) Gray Scale Clock Frequency - 16 MHz (Max) Using Internal PLL - 8 MHz (Max) Using External Clock Operating Free-Temperature Range - 20C to 85C 100-Pin Package HTQFP (PD = 4.7 W, TA = 25C)
Adjustable for these functions independently. Allows to write all the data at port A by setting.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright (c) 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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1
TLC5911 LED DRIVER
SLLS402 - DECEMBER 1999
description
The TLC5911 is a constant current driver incorporating shift register, data latch, and constant current circuitry with a current value adjustable, PLL circuitry for gray scale control clock generation, and 1024 gray scale display using pulse width control. The output current is maximum 80 mA with 16 bits, and the current value of constant current output can be set by one external resistor. The device has two channel I/O ports. The brightness deviation between LED modules (ICs) can be adjusted by external data input from the display data port, and the brightness control for the panel can be accomplished by the brightness adjustment circuitry. Independent of these functions, the device incorporates the shift register and data latch to correct the deviation between LEDs by adjusting the output current using data from the dot correction data port. Moreover, the device incorporates WDT circuitry, which turns constant current output off when the scan signal stops during the dynamic scanning operation, and TSD circuitry, which turns constant current output off when the junction temperature exceeds the limit. Also the LED open detection (LOD) circuitry is used to make error signal output at the LED disconnection.
pin assignments
PZP PACKAGE (TOP VIEW)
GNDLED OUT0 OUT1 GNDLED OUT2 OUT3 GNDLED OUT4 OUT5 GNDLED OUT6 OUT7 GNDLED OUT8 OUT9 GNDLED OUT10 OUT11 GNDLED OUT12 OUT13 GNDLED OUT14 OUT15 GNDLED
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
TEST3 TEST2 GNDLOG TEST1 DPOL DCENA BCENA VCCLOG DCDIN6 DCDIN5 DCDIN4 DCDIN3 DCDIN2 DCDIN1 DCDIN0 DIN9 DIN8 DIN7 DIN6 DIN5 DIN4 DIN3 DIN2 DIN1 DIN0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
VCOIN RBIAS MAG0 MAG1 MAG2 PDOUT GSPOL GSCLK BLANK XENABLE XOE DCLK XLATCH DCCLK XDCLAT RSEL0 RSEL1 LEDCHK NC WDTRG XDOWN1 XDOWN2 BOUT XGSOUT XPOUT
2
VCCLED XDWN2TST GNDANA XDPOUT WDCAP TSENA IREF VCCANA DCDOUT6 DCDOUT5 DCDOUT4 DCDOUT3 DCDOUT2 DCDOUT1 DCDOUT0 DOUT9 DOUT8 DOUT7 DOUT6 DOUT5 DOUT4 DOUT3 DOUT2 DOUT1 DOUT0
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TLC5911 LED DRIVER
SLLS402 - DECEMBER 1999
functional block diagram
XOE BCENA DCLK DPOL XENABLE
DCLK Control
DOUT(9-0) XDPOUT 1 x 10 bit B.C. Data Shift Register Data Latch
DIN(9-0), XLATCH RSEL(1-0) DCDIN(6-0), XDCLAT, DCCLK 8
16 x 10 bit Data Shift Register .......... 16 x 10 bit Data Latch ..........
MAG(2-0), GSPOL, GSCLK, RBIAS, VCOIN, PDOUT BLANK WDCAP WDTRG LEDCHK XDOWN2TST TSENA
XPOUT XGSOUT
PLL
10 bit Clock Countor
16 x 10 bit Data Comparator .......... BOUT OUT0 *** OUT15 XDOWN1 XDOWN2
WDT
16 bit LED Driver+LOD .......... 16 bit Current Controller ..........
TSD
IREF 16 x 7 bit D.C. Data Latch .......... 16 x 7 bit D.C. Data Shift Register
DCENA
DCDOUT(6-0)
Legend: B.C. (Brightness Control): Adjustment for brightness deviation between LED modules, and between panels. D.C. (Dot Control): Adjustment for brightness deviation between dots. NOTE: All the input terminals are with Schmitt triggered inverter except RBIAS, VCOIN, PDOUT, IREF and WDCAP.
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3
TLC5911 LED DRIVER
SLLS402 - DECEMBER 1999
functional block diagram for shift register and data latch
XOE DATA S/R DCLK DPOL XENABLE DCCLK DCLK Controller a A b B c 10 a b c A 10 L H 10 DOUT(9-0) 10 10 16 DATA LATCH 10 16 DATA Comparator
10 DIN(9-0) DCDIN(6-0) 7
a A b B c 10 B.C. S/R 10 B.C. LATCH 10
10 HI-Z Clock Counter Current Controller
a XLATCH XDCLAT A b B c 7 DCDOUT(6-0)
RSEL(1-0)
7
D.C. S/R
7 16
D.C. LATCH
7 16
H L
7 16
DATA Comparator
7 16 BCENA DCENA Connecting to 16th 10-bit Bus Connecting to 16th 7-bit Bus Legend: B.C. (Brightness Control): Adjustment for brightness deviation between LED modules, and between panels. D.C. (Dot Control): Adjustment for brightness deviation between dots. RSEL RSEL1 L L H H RSEL0 L H L H CONNECTION A - a, B - c A - b, B - c A-c INHIBIT Default
4
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TLC5911 LED DRIVER
SLLS402 - DECEMBER 1999
equivalent input and output schematic diagrams
Input
VCCIF
DOUT0-9, DCDOUT0-6, XGSOUT, XPOUT, BOUT
VCCLOG
OUTPUT INPUT
GNDLOG
GNDLOG
XDOWN1, XDOWN2
XDOWN1, XDOWN2
OUTn
OUTn
GNDLOG
GNDLED
Terminal Functions
TERMINAL NAME NO.
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BCENA 94 I Brightness control enable. When BCENA is low, the brightness control latch is set to the default value. The output current value in this status is 100% of the value set by an external resistor. The frequency division ratio of GSCLK is1/1. When BCENA is high, writing to brightness control latch is enabled. BLANK 67 I Blank (Light off). When BLANK is high, all output of the constant current driver are turned off. When GSPOL is high, all the output is turned on (LED on) synchronizing to the falling edge of GCLK after next rising edge of GSCLK when BLANK goes from high to low. When GSPOL is low, all the output is turned on (LED on) synchronizing to the rising edge of GCLK after next falling edge of GSCLK when BLANK goes from high to low. BLANK buffered output BOUT 53 62 O I DCCLK Clock input for data transfer. The input data is from DCDIN (port B) . The output data at DCDOUT. All data on the shift register for dot correction data from DCDIN is shifted by 1 bit and is synchronized to the rising edge of DCCLK. Input for 7 bit parallel data (port B). These terminals are used as shift register input for dot correction data. Output for 7 bit parallel data (port B). These terminals are used as shift register output for dot correction data. DCDIN0 - DCDIN6 86,87,88, 89,90,91,92 I DCDOUT0 - DCDOUT6 DCENA 34,35,36, 37,38,39,40 95 O I Latch enable for dot correction data. When DCENA is low, the latch is set to the default value. At this time, the output current value is 100% of the value set by an external resistor. DCLK 64 I Clock input for data transfer. The input data is from DIN (port A) , all the data on the shift register selected by RSEL0, 1 and the output data at DOUT are shifted by 1 bit and synchronized to DCLK. Note that whether synchronizing to the rising or falling edge of DCLK is dependent on the value of DPOL.
POST OFFICE BOX 655303
I/O
DESCRIPTION
* DALLAS, TEXAS 75265
5
TLC5911 LED DRIVER
SLLS402 - DECEMBER 1999
Terminal Functions (Continued)
TERMINAL NAME NO.
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DIN0 - DIN9 76,77,78,79,80, 81,82,83,84,85 I Input for 10 bit parallel data (port A). These terminals are inputs for shift register for gray scale data, brightness control, and dot correction data. The register selected is determined by RSEL0, 1. Output for 10 bit parallel data (port A). These terminals are outputs for shift register for gray scale data, brightness control, and dot correction data. The register selected is determined by RSEL0, 1. Selects the valid edge of DCLK. When DPOL is high, the rising edge of DCLK is valid. When DPOL is low, the falling edge of DCLK is valid. Analog ground (Internally connected to GNDLOG and GNDLED) Logic ground (Internally connected to GNDANA and GNDLED) DOUT0 - DOUT9 41,42,43,44,45, 46,47,48,49,50 96 28 98 O DPOL I GNDANA GNDLOG GNDLED 1,4,7,10,13, 16,19,22,25 LED driver ground (Internally connected to GNDANA and GNDLED) GSCLK 68 I Clock input for gray scale. When MAG0 through MAG2 are all low, GSCLK is used for pulse width control. When MAG0 through MAG2 are not low, GSCLK is used for PLL timing control. The gray scale display is accomplished by lighting the LED until the number of GSCLK or PLL clocks counted is equal to the data latched. Select the valid edge of GSCLK. When GSPOL is high, the rising edge of GSCLK is valid. When GSPOL is low, the falling edge of GSCLK is valid. GSPOL 69 I IREF 32 I/O Constant current value setting. LED current is set to the desired value by connecting an external resistor between IREF and GND. The 38 times current is compared to current across the external resistor sink on the output terminal. LEDCHK 58 I LED disconnection detection enable. When LEDCHK is high, the LED disconnection detection is enabled and XDOWN2 is valid. When LEDCHK is low, the LED disconnection detection is disabled. PLL multiple ratio setting. The clock frequency generated by PLL referenced to GSCLK is set . No internal connection MAG0 - MAG2 NC 73,72,71 57 I OUT0 - DOUT15 PDOUT RBIAS 2,3,5,6,8,9,11, 12,14,15,17,18, 20,21,23,24 70 74 O Constant current output I/O I/O Resistor connection for PLL feedback adjustment Resistor connection for PLL oscillation frequency setting RSEL0 RSEL1 60 59 I Input/output port selection and shift register data latch switching. When RSEL1 is low and RSEL0 is low, the gray scale data shift register latch is selected to port A, and the dot correction register latch is selected to port B. When RSEL1 is low and RSEL0 is high, the brightness control register latch is selected to port A, and the dot correction register latch is selected to port B. When RSEL1 is high and RSEL0 is low, the dot correction register latch is selected to port A and no register latch is selected to port B. TEST. Factory test terminal. These terminals should be connected to GND. TEST1 - TEST3 THERMAL PAD TSENA 97,99,100 I Package bottom 31 33 93 26 75 30 Heat sink pad. This pad is connected to the lowest potential IC or thermal layer. I TSD enable. When TSENA is high, TSD is enabled. When TSENA is low, TSD is disabled. Analog power supply voltage Logic power supply voltage VCCANA VCCLED VCOIN VCCLOG LED driver power supply voltage I/O I/O Capacitance connection for PLL feedback adjustment WDCAP WDT detection time adjustment. WDT detection time is adjusted by connecting a capacitor between WDCAP and GND. When WDCAP is directly connected to GND, the WDT function is disabled. In this case, WDTRG should be tied to high or low level. 6
POST OFFICE BOX 655303
I/O
DESCRIPTION
* DALLAS, TEXAS 75265
TLC5911 LED DRIVER
SLLS402 - DECEMBER 1999
Terminal Functions (Continued)
TERMINAL NAME NO. 56
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WDTRG I WDT trigger input. By applying a scan signal to this terminal, the scan signal can be monitored by turning the constant current output off and protecting the LED from the damage of burning when the scan signal stops during the constant period designed. Data latch for dot correction. When XDCLAT is high, data on the shift register for dot correction data from DCDIN (port B) goes through latch. When XDCLAT is low, the data is latched. Accordingly, if data on the shift register is changed during XDCLAT high, the new value is latched (level latch). Shutdown. XDOWN1 is configured as open collector. It goes low when the constant current output is shut down by the WDT or TSD function. LED disconnection detection output. XDOWN2 is configured as open collector. XDOWN2 goes low when a LED disconnection is detected. DPOL output inverted XDCLAT 61 I XDOWN1 XDOWN2 XDPOUT 55 54 29 27 66 O O O I I XDWN2TST XENABLE Test for XDOWN2. When XDWN2TST is low, XDOWN2 goes low. (This terminal is internally pulled up with 50 k) DCLK enable. When XENABLE is low, data transfer is enabled. Data transfer starts on the valid edge of DCLK after XENABLE goes low. During XENABLE high, no data is transferred. Clock output for gray scale. When MAG0 through MAG2 are all low, a clock with GSCLK inverted appears on this terminal. When MAG0 through MAG2 are not low., PLLCLK appears on this terminal. XGSOUT 52 O XLATCH 63 I Latch. When XLATCH is high, data on shift register from DIN (port A) goes through latch. When XLATCH is low, data is latched. Accordingly, if the data on the shift register is changed during XLATCH high, this new value is latched (level latch). Data output enable. When XOE is low, the DOUT0-9 terminals are driven. When XOE is high, the DOUT0-9 terminals go to a high-impedance state. GSPOL output inverted XOE 65 51 I XPOUT O
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DESCRIPTION
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TLC5911 LED DRIVER
SLLS402 - DECEMBER 1999
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Logic supply voltage, VCC(LOG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 7 V Supply voltage for constant current circuit, VCC(LED) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 7 V Analog supply voltage, VCC(ANA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 7 V Output current (DC), IOL(C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 mA Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to VCCLOG + 0.3 V Output voltage range, V(DOUT), V(DCDOUT), V(BOUT), V(XPOUT) and V(XGSOUT) - 0.3 V to VCCLOG + 0.3 V Output voltage range, VO and V(XDOWNn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 16 V Storage temperature range, Tstr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40C to 150C Continuous total power dissipation at (or below) TA = 25C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7 W Power dissipation rating at (or above) TA = 25C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38.2m W/C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to GNDLOG terminal.
recommended operating conditions
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MIN NOM 5 5 5 MAX 5.5 5.5 5.5 UNIT V V V Logic supply voltage, VCC(LOG) 4.5 4.5 4.5 Supply voltage for constant current circuit, VCC(LED) Analog power supply, VCC(ANA) Voltage between VCC, V(DIFF1) Voltage between GND, V(DIFF2) V(DIFF1) = VCC(LOG) - VCC(ANA) VCC(LOG) - VCC(LED) VCC(ANA) - VCC(LED) V(DIFF2)= GND(LOG) - GND(ANA) GND(LOG) - GND(LED) GND(ANA) - GND(LED) OUT0 to OUT15 off -0.3 0 0.3 V -0.3 0 0.3 V Voltage applied to constant current output, VO High-level input voltage, VIH Low-level input voltage, VIL 15 V V V 0.8 VCC(LOG) GND(LOG) VCC(LOG) 0.2 VCC(LOG) -1 High-level output current, IOH VCC(LOG) = 4.5 V, DOUT0 to DOUT9, DCDOUT0 to DCDOUT5, BOUT, XGSOUT, XPOUT VCC(LOG) = 4.5 V, DOUT0 to DOUT9, DCDOUT0 to DCDOUT5, BOUT, XGSOUT, XPOUT V(CCLOG) = 4.5 V, XDOWN1, XDOWN2 OUT0 to OUT15 mA Low-level output current, IOL 1 5 mA mA C F Constant output current, IOL(C) PLL capacitance, C(VCO) PLL resistor, R(BIAS) PLL resistor, R(PD) 5 80 85 Operating free-air temperature range, TA -20 1 At 16 MHz oscillation 22 30 k k 8
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dc characteristics
* DALLAS, TEXAS 75265
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ac characteristics, VCC(LOG)= VCC(ANA) = VCC(LED) = 4.5 V to 5.5 V, TA = - 20 to 85C (unless otherwise noted)
recommended operating conditions (continued)
Hold time, th
Setup time, tsu
Rise/fall time, tr/tf
XLATCH, XDCLAT pulse duration (high-level), tw(h)
WDT pulse duration (high- or low-level), tw(h)/tw(l)
WDT clock frequency, f(WDT)
PLLCLK clock frequency, f(PLLCLK)
GSCLK pulse duration (high- or low-level), tw(h)/tw(l)
DCLK, DCCLK pulse duration (high- or low-level), tw(h)/tw(l) GSCLK clock frequency, f(GSCLK)
DCLK DCCLK clock frequency, f(DCLK)/f(DCCLK) frequency DCLK,
POST OFFICE BOX 655303
DINn - DCLK DCDINn - DCCLK XENABLE - DCLK XLATCH - DCLK XDCLAT - DCCLK RSEL - DCLK RSEL - DCCLK RSEL - XLATCH RSEL - XDCLAT
DINn - DCLK DCDINn - DCCLK BLANK - GSCLK XENABLE - DCLK XLATCH - DCLK XLATCH - GSCLK XDCLAT - DCCLK RSEL - DCLK RSEL - DCCLK RSEL - XLATCH RSEL - XDCLAT
At cascade operation
At single operation
* DALLAS, TEXAS 75265
MIN 5 5 10 15 10 10 10 10 15 30 15 15 15 20 30 20 20 20 20 10 30 40 40 20 TYP MAX 100 16 15 20 8 8 UNIT MHz MHz MHz MHz ns ns ns ns ns ns ns
SLLS402 - DECEMBER 1999
TLC5911 LED DRIVER
9
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SLLS402 - DECEMBER 1999
TLC5911 LED DRIVER
electrical characteristics, LEDCHK = L, MIN/MAX: VCC(LOG) = VCC(ANA) = VCC(LED) = 4.5 V to 5.5 V, TA = -20 to 85C, TYP: VCC(LOG) = VCC(ANA) = VCC(LED) = 5 V, TA = 25C (unless otherwise noted)
10 P(LLJITTER) V(LEDDET) V(IREF) T(tsd) T(wdt) IOL(C2) IOL(C1) IOL(C) IOL(K) IOL(C2) IOL(C1) I(LED) I(ANA) I(LOG) II VOL VOH PLL jitter Voltage applied to LED disconnection detection Voltage reference WDT detection temperature TSD detection temperature Constant output current error between bit Constant output current (includes error between bits) Constant output current (includes error between bits) Supply current (constant current driver) Supply current (analog) Supply current (logic) Input current g Low-level output voltage High-level output voltage PARAMETER
Changes in constant output current depend on output voltage
Changes in constant output current depend on supply voltage
Constant out ut leakage current output
POST OFFICE BOX 655303
VO = 0.7 V, V(IREF) = 1.2 V R(IREF) = 600 W
VO = 1 V, V(IREF) = 1.2 V, R(IREF) = 1200 W
VO = 1 V, R(IREF) = 600 all output bits turn on
VO = 1 V, R(IREF) = 1200 all output bits turn on
VO = 1 V to 3 V, R(IREF) = 600 , VIREF = 1.2 V, 1 bit output turn on
VO = 1 V, R(IREF) = 600 W, VIREF = 1.2 V
VCC(LOG)=VCC(ANA)=VCC(LED) VO = 1 V, R(IREF) = 600 W All output bits turn on
R(BIAS) = 22 k, R(PD) = 30 k, C(VCO) = 0.1 F
BCENA = L, R(IREF) = 9.6 k,
No external capacitor
Junction temperature
DOUTn, DCDOUTn (VOUTn = VCCLOG or GND)
XDOWN1, 2 (VXDOWNn = 15 V)
OUT0 to OUT15 (VOUTn = 15 V)
LED turn off, R(IREF) = 600
LED turn off, R(IREF) = 1200
BLANK = L, R(IREF) = 600
BLANK = L, R(IREF) = 1200
Data transfer, DCLK = 20 MHz, GSCLK = 15 kHz PLL multiple ratio = 1042
Data transfer, DCLK = 20 MHz, GSCLK = 8 MHz No PLL is used
Input signal is static, TSENA = H, WDCAP = OPEN, PLL multiple ratio = 1042
Input signal is static, TSENA = H, WDCAP = OPEN, No PLL is used
IOL = 5 mA, XDOWN1, XDOWN2 VI = VCC(LOG) or GND(LOG)
IOL = 1 mA, DOUTn, DCOUTn, XGSOUT, XPOUT, BOUT
IOH = - 1 mA, DOUTn, DCOUTn, XGSOUT, XPOUT, BOUT
TEST CONDITIONS
* DALLAS, TEXAS 75265
VCC(LOG) - 0.5 150 MIN 0.2 70 35 5 0.4% 1% 1% 1% TYP 160 0.3 1.2 6.5 10 80 40 20 20 12 13 39 35 12AAAmA 20AAA 3% 4% 4% MAX 170 2% 1 15 90 45 35 35 20 15 49 45 1 1 8 3 1 0.4 0.1 0.5 0.5 UNIT mA mA mA mA mA mA ms A A A A C V V V V V V
AAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A AAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A AAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A AAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A AAA A A A AAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAA A A A
NOTES: 2. MAG0 to MAG2 are all low level. 3. Until DOUT is turned on (drive) or turned off (Hi-Z).
switching characteristics, CL = 15 pF, MIN/MAX: VCC(LOG) = VCC(ANA) = VCC(LED) = 4.5 V to 5.5 V, TA = -20 to 85C, TYP: VCC(LOG) = VCC(ANA) = VCC(LED) = 5 V, TA = 25C (unless otherwise noted)
td
tf
tr
Propagation delay time
Fall time
Rise time
PARAMETER
POST OFFICE BOX 655303
LEDCHK - XDOWN2
RSEL - DOUTn
XOE - DOUTn (see Note 3)
XOE - DOUTn (see Note 3)
DCCLK - DCDOUTn
DCLK - DCDOUTn
DCLK - DOUTn
GSCLK - XGSOUT
GSCLK - OUT0 (see Note 2)
BLANK - BOUT
BLANK - OUT0
OUTn+1 - OUTn
OUTn (see Figure 1)
XGSOUT, BOUT, XPOUT
DOUTn, DCDOUTn
OUTn (see Figure 1)
XGSOUT, BOUT, XPOUT
DOUTn, DCDOUTn
TEST CONDITIONS
* DALLAS, TEXAS 75265
MIN 10 10 10 15 15 15 10 10 40 TYP 130 110 20 15 20 30 30 30 20 20 50 30 10 10 12 12 7 MAX 1000 40 25 35 45 45 45 40 40 70 45 30 30 30 30 UNIT ns ns ns
SLLS402 - DECEMBER 1999
TLC5911 LED DRIVER
11
TLC5911 LED DRIVER
SLLS402 - DECEMBER 1999
PARAMETER MEASUREMENT INFORMATION
VCC
VCC IREF 600 GND OUTn
51
15 pF
Figure 1. Rise Time and Fall Time Test Circuit for OUTn
VIH or VOH
90% 10% tr tf
VIH
100% 50%
VIL
0%
VIL or VOL td
100% 50% 0% tw(h) tw(l)
VIH
100% 50%
VIH or VOH
VIL
0%
VIL or VOL
Figure 2. Timing Requirements
12
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
TLC5911 LED DRIVER
SLLS402 - DECEMBER 1999
PRINCIPLES OF OPERATION setting for output constant current value
On the constant current output terminals (OUT0-15), approximately 38 times the current which flows through the external resistor, R(IREF) (connected between IREF and GND), can flow. The external resistor value is calculated using the following equation: R(IREF) () 38 x 1.2 (V) / IOL(C)(A) where both BCENA and DCENA are low. Note that more current flows if IREF is connected to GND directly.
constant output current operation
The constant current output turns on (sink constant current), if GSPOL is high and if all the gray scale data latched into the gray scale latch is not zero on the falling edge of the gray scale clock after the next rising edge of the gray scale clock when BLANK goes from high to low. After that, the number of the falling edge is counted by the 10-bit gray scale counter. Then, the output counted corresponding to the gray scale data is turned off (stop to sink constant current). The gray scale clock can be selected, as discussed in later section, from GSCLK or by internal PLL circuitry. If the shift register for the gray scale is updated during XLATCH high, the data on the gray scale data latch is also updated affecting the number of the gray scale of constant current output. Accordingly, during the on-state of the constant current output, XLATCH should be kept at a low level and the gray scale data latch should be held.
input/output port and shift register selection
The TLC5911 supplies two parallel input ports such as DIN (10 bits : port A) and DCDIN (7 bits: port B). The DIN and DCDIN ports also supply DCLK and DCCLK for the shift clock, XLATCH and XDCLAT for latch, and DOUT and DCDOUT for output, respectively. The device has three kinds of shift register latchs such as the gray scale data, brightness control, and dot correction. The port and shift registers can be selected by RSEL0 and RSEL1. The selection of the shift registers will be done by RESL0 and RSEL1 as shown in Table 1. Note that the RSELn setting is done at DCLK low and DPOL high (DCLK is high when DPOL is low). When only port A is used, DCDIN, DCDOUT, DCCLK, and XDCLAT should be connected to GND. Table 1. Shift Register Latch Selection
shift register latch for gray scale data
The shift register latch for the gray scale data is configured with 16 x 10 bits. The gray scale data, configured with 10 bits, represents the time when constant current output is being turned on, and the data range is 0 to 1023 (00h to 3FFh). When the gray scale data is 0, the time is shortest, and the output is not turned on (light off). On the other hand, when the gray scale data is 1023, the time is longest, and it turns on during the time of the 1023 clocks from the gray scale clock. The configuration of the shift register and the latch for gray scale data is shown in Figure 3.
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SELECTED SHIFT REGISTER LATCH PORT A PORT B RSEL1 L L RSEL0 L L H H DIN, DCLK, XLATCH, DOUT Gray scale data displayed Brightness control N/A (inhibit) DCDIN, DCCLK, XDCLAT Dot correction Dot correction N/A (inhibit) DCDOUT Dot correction Dot correction Dot correction N/A (inhibit) H H Dot correction (see Note 4) Not connected NOTE 4: Zero is output to DOUT7 through DOUT9.
POST OFFICE BOX 655303
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13
TLC5911 LED DRIVER
SLLS402 - DECEMBER 1999
PRINCIPLES OF OPERATION
Latch for Gray Scale Data OUT15 Data (10 bits) OUT14 Data (10 bits) OUT1 Data (10 bits) OUT0 Data (10 bits)
XLATCH
Shift Register for Gray Scale Data 16th byte DIN9 MSB DIN0 LSB 15th byte DIN9 MSB DIN0 LSB 2nd byte DIN9 MSB DIN0 LSB 1st byte DIN9 MSB DIN0 LSB DCLK DIN0 to 9
DOUT0 to 9
Figure 3. Relationship Between Shift Register and Latch for Gray Scale Data shift register latch for brightness control The shift register latch for brightness control is configured with 1 x 10 bits. Using the shift register latch for the brightness control, the division ratio of the gray scale clock can be set and the output current value on constant current output can be adjusted. When powered up, the latch data is indeterminate and the shift register is not initialized. When these functions are used, data should be written to the shift register latch prior to lighting-on (BLANK=L). Also, it is prohibited from rewriting the latch value for the brightness control when the constant current output is turned on. When these functions are not used, the latch value can be set to the default value setting of BCENA at low level (connect to GND). Also, DIN9 is assigned to the LSB of the reference current control to maintain compatibility with the TLC5901/02/03 family. The configuration of the shift register and the latch for brightness control is shown in Figure 4.
Latch for Brightness Control Gray Scale Clock Division Ratio Data Set XLATCH 0 MSB 0 0 0 LSB Current Data Adjusted On Constant Current Output 1 MSB 1 1 1 1 1 LSB (see Note A)
Shift Register for Brightness Control DOUT0 to 9 DIN8 DATA DIN7 DATA DIN6 DATA DIN5 DATA DIN4 DATA DIN3 DATA DIN2 DATA DIN1 DATA DIN0 DATA DIN9 DATA DCLK DIN0 to 9
NOTE A: Indicates default value at BCENA low.
Figure 4. Relationship Between Shift Register and Latch for Brightness Control shift register latch for dot correction The shift register latch for dot correction is configured with 16 x 7 bits. Using the shift register latch for dot correction, the current value on the constant current output can be set individually. When powered up, the latch data is indeterminate and the shift register is not initialized. When these functions are used, data should be written to the shift register latch prior to lighting-on (BLANK=L). Also, rewriting the latch value for dot correction when the constant current output is turned on is inhibited. When these functions are not used, the latch value can be set to the default value setting of DCENA at low level (connect to GND). The configuration of the shift register and the latch for dot correction is shown in Figure 5.
14
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
TLC5911 LED DRIVER
SLLS402 - DECEMBER 1999
PRINCIPLES OF OPERATION
Latch for Dot Correction OUT15 Data (7 bits) OUT14 Data (7 bits) OUT1 Data (7 bits) OUT0 Data (7 bits)
XDCLAT
Shift Register for Dot Correction 16th byte DCDIN6 MSB DCDIN0 LSB 15th byte DCDIN6 MSB DCDIN0 LSB 2nd byte DCDIN6 MSB DCDIN0 LSB 1st byte DCDIN6 MSB DCDIN0 LSB DCCLK DCDIN0 to 6
DCDOUT0 to 6
Using Port B (RSEL0=L or H, RSEL1=L) Latch for Dot Correction OUT15 Data (7 bits) OUT14 Data (7 bits) OUT1 Data (7 bits) OUT0 Data (7 bits)
XLATCH
Shift Register for Dot Correction 16th byte DIN6 MSB DIN0 LSB 15th byte DIN6 MSB DIN0 LSB 2nd byte DIN6 MSB DIN0 LSB 1st byte DIN6 MSB DIN0 LSB DCLK DIN0 to 6
DOUT0 to 6
Using Port A (RSEL0=L, RSEL1=H)
Figure 5. Relationship Between the Shift Register and the Latch for Dot Correction write data to shift register latch The shift register latch written is selected using the RSEL0 and RSEL1 terminal. At port A, the data is applied to the DIN data input terminal, clocked into the shift register and synchronized to the rising edge of DCLK after XENABLE is pulled low. At port B, the data is applied to the DCDIN data input terminal, clocked into the shift register, and synchronized to the rising edge of DCCLK. The shift register for the gray scale data is configured with 16 x 10 bits and the shift register for dot correction is configured with 16 x 7 bits resulting in sixteen times DCLK. The shift register for the brightness control is configured with 1 x 10 bits resulting in one times DCLK. At the number of DCLK input for each case, data can be written into the shift register. In this condition, when the XLATCH at port A or the XDCLAT at port B is pulled high, data in the shift register is clocked into the latch (data through). When the XLATCH at port A or XDCLAT at port B is pulled low, data is held (latch).
POST OFFICE BOX 655303
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15
TLC5911 LED DRIVER
SLLS402 - DECEMBER 1999
PRINCIPLES OF OPERATION brightness control function
By writing data into the brightness control latch, current on all the constant current outputs can be adjusted to control the variation of brightness between ICs. The division ratio for the gray scale clock can be set to control the variation of brightness for the total panel system. Furthermore, by writing data into the dot correction latch, current on each constant current output can be adjusted. output current adjustment on all constant current outputs - brightness adjustment between ICs By using the lower 6 bits of the brightness control latch, output current can be adjusted in 64 steps as 1 step of 0.8% of the current ratio between 100% and 50.8% when the output current is set to 100% of an external resistor (note that the current value is lower if the constant current output is corrected using the dot correction function). By using this function, the brightness control between modules (ICs) can be adjusted sending the desired data externally even if ICs are mounted on a print-circuit board. When BCENA is pulled low, the output current is set to 100%. Table 2. Relative Current Ratio For Total Constant Current Output
frequency division ratio setting for gray scale clock - panel brightness adjustment
By using the upper 4 bits of the brightness control latch, the gray scale clock can be divided into 1/1 to 1/16. If the gray scale clock is set to 16 times the speed of frequency (1024x16=16384) during horizontal scanning time, the brightness can be adjusted in 16 steps by selecting the frequency division ratio. By using this function, the total panel brightness can be adjusted at once, and applied to the brightness of day or night. When BCENA is pulled low, the gray scale clock is not divided. When BCENA is pulled high, the brightness can be adjusted as shown in Table 3. Table 3. Relative Brightness Ratio For Total Constant Current Output
16
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CURRENT RATIO % 50.8 . . . . 20 (mA) 10.2 . . . . 80 (mA) 40.6 . . . . CODE VIREF (TYP) 0.60 . . . . MSB 000000 LSB . . . . 99.2 100 19.8 20.0 79.7 80.0 111110 111111 1.19 1.20 BCENA is low.
A A A AAAAAAAAAAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAA AAAAAA A A A A A AAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAA AA A A AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAA A A A A AAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAA
CODE FREQUENCY DIVISION RATIO 1/1 . . . . RELATIVE BRIGHTNESS RATIO (%) 6.3 . . . . MSB 0000 LSB . . . . 1110 1111 1/15 1/16 93.8 100 BCENA is low.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
TLC5911 LED DRIVER
SLLS402 - DECEMBER 1999
PRINCIPLES OF OPERATION
output current adjustment on each constant current output - LED brightness adjustment By using the dot correction latch, the output current on each constant current output can be adjusted in 128 steps as 1 step of 0.8% of the current ratio between 100% and 0% when the output current is set to 100% of an external resistor at 7Fh of the latched value and the lower 6 bits of the brightness control register. By using this function, the brightness deviation from the LED brightness variation can be minimized. When DCENA is pulled low, the output current is set to 100% without the dot correction. Table 4. Relative Current Ratio By Constant Current Output
clock edge selection
The high speed clock signal is diminished due to the duty ratio change through the multiple stages of the IC or module as shown in Figure 6.
IN A OUT IN A A' OUT OUT'
IN
A OUT
a) Propagate through multiple stages buffer with slow falling edge
In Figure 6a, if the falling edge at the internal buffer is behind the rising edge, the clock will disappear if a multiple cascade connection is made. To resolve this problem, the duty ratio can be held unchanged using the connection as shown in Figure 6b if the valid clock edge can be selected (arrow in Figure 6). Note that the clock delay is not avoided even in this case. The device incorporates the clock edge selection function for each DCLK and GSCLK. By using this function, the falling edge or rising edge for the valid edge can be selected depending on the status of DPOL and GSPOL, thus the degradation for the duty ratio can be reduced. The relationship between each signal is shown in Table 5.
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CODE . . . . CURRENT RATIO % 0.0 . . . . MSB 0000000 LSB IOL(C)=40 (mA) 0.0 . . . . 1111110 1111111 99.2 100 39.7 40 DCENA is low. IN' A' OUT b) Insert inverter between buffers
Figure 6. Clock Edge Selection
POST OFFICE BOX 655303
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17
TLC5911 LED DRIVER
SLLS402 - DECEMBER 1999
PRINCIPLES OF OPERATION
The device supplies the XPOUT and XGSOUT output terminals for the cascade operation which inverts GSPOL and GSCLK respectively. It also supplies the BOUT output terminal as a buffered BLANK to make timing easy with GSCLK and XGSOUT.
gray scale clock generation
When MAG<0:2> are all low, the clock input from the GSCLK terminal is used as the gray scale clock with no change, and except for this case the internal PLL generates the clock for the gray scale control clock. When using the PLL, the gray scale clock is generated by adjusting the clock to have the same number of pulses as the multiple ratio of the GSCLK reference period (when GSCLK and GSPOL are kept at the same level). The ratio in this case is determined depending on MAG0 through MAG2 as shown in Table 6. When using the PLL, the internal PLLCLK is clocked out at the XGSOUT terminal. Therefore, the clock can be utilized for other devices on the same print-circuit board. Note that the number of ICs connected is limited depending on the frequency.
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MAG2 L L L L
H H H H
18
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DPOL H L DCLK valid edge DCLK DCLK Operation at XENABLE = H Pull DCLK to low level Pull DCLK to high level PLL operation GSPOL H L GSCLK valid edge GSCLK GSCLK Synchronize to the high level of DCLK Synchronize to the low level of DCLK
Table 5. Valid Edge For DCLK and GSCLK
Table 6. PLL Multiple Ratio
MULTIPLE RATIO
MAG1 L L
MAG0 L L L L H H H H
XGSOUT
1 (Signal to control GSCLK by GSPOL) 28+6(=262) 29+10(=522) 210+18(=1042) 211+34(=2082) 212+66(=4162)
Inverted GSCLK
H H L L
PLLCLK (Gray scale clock is internally generated)
H H
213+130(=8322) 214+258(=16642)
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
TLC5911 LED DRIVER
SLLS402 - DECEMBER 1999
PRINCIPLES OF OPERATION gray scale clock generation (continued)
MAG<2:0> GSPOL Except all low level Except all low level
GSCLK
XGSOUT
PLLCLK
Same number of pulse as ratio a) GSPOL is high
Same number of pulse as ratio a) GSPOL is low
Figure 7. Gray Scale Clock Generation The oscillation frequency bandwidth as referenced for the PLL can be set by an external resistor connected between RBIAS and GND. The relation between the external resistor and the oscillation frequency is shown in Table 7. Table 7. PLL Oscillation Frequency
Note that it takes 30 ms for the PLL to be stabilized. Furthermore, to make the PLL operation stabilized, a resistor and a capacitor connection is required between VCOIN, PDOUT and GND. The recommended values are shown in the Figure 8.
PDOUT VCOIN C(VCO) R(pd) Recommeded Value C(VCO) 0.1 to 1 F R(pd) 22 to 62 k
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RBIAS 22 k 30 k 62 k 12 0k FREQUENCY 13 to 16 MHz 8 to 14 MHz 4 to 9 MHz 3 to 5 MHz
Figure 8. Resistor and Capacitor Connection
POST OFFICE BOX 655303
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19
TLC5911 LED DRIVER
SLLS402 - DECEMBER 1999
PRINCIPLES OF OPERATION protection
This device incorporates WDT and TSD functions. If the WDT or TSD functions, the constant current output is stopped and XDOWN1 goes low. Therefore, by monitoring the XDOWN1 terminal, these failures can be detected immediately. Since the XDOWN1 output is configured as open collector, outputs of multiple ICs are brought together. WDT (watchdog timer) The constant current output is forced to turn off and XDOWN1 goes low when the fixed period elapsed after the signal applied to WDTRG has not been changed. Therefore, by connecting a scan signal (a signal to the control line displayed) to WDTRG, the stop of the scan signal can be detected and the constant current output is turned off preventing the LED from burning and damage caused by continuous LED turn on at the dynamic scanning operation. The detection time can be set using an external capacitor, C1. The typical value is approximately 10 ms without capacitor, 160 ms with a1000 pF capacitor, and 1500 ms with a 0.01 F capacitor. During static operation, the WDT function is disabled connecting the WDCAP to GND (high or low level should be applied to WDTRG). Note that normal operations will be resumed changing the WDTRG level when WDT functions. WDT operational time T (ms) 10 + 0.15 x C1 (pF)
Time (ms)
1500 Scan Signal 160 C1
TLC5911 WDTRG WDCAP
10 0 0.001 0.01 C1 - External Capacitor - F
Figure 9. WDT Operational Time and Usage Example TSD (thermal shutdown) When the junction temperature exceeds the limit, TSD functions and turns the constant current output off, and XDOWN1 goes low. When TSD is used, TSENA is pulled high. When TSD is not used, TSENA is pulled low. To recover from the constant current output off-state to normal operations, the power supply should be turned off or TSENA should be pulled low once.
20
POST OFFICE BOX 655303
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TLC5911 LED DRIVER
SLLS402 - DECEMBER 1999
PRINCIPLES OF OPERATION LOD function (LED open detection)
When LEDCHK is low, the LED disconnection detection function is disabled and XDOWN2 goes to a high-impedance state. When LEDCHK is high, the LED disconnection detection function is enabled, and XDOWN2 goes low if any LED is disconnected while monitoring the OUTn terminals to be turned on. This function is operational for sixteen OUTn terminals individually. To determine which constant current output is disconnected, the level of XDOWN2 is checked 16 times from OUT0 to OUT15 turning one constant current output on. The power supply voltage should be set so the constant current output applied is above 0.4 V when the LED is turned on normally. Also, since approximately 1000 ns is required from turning the constant current output on to XDOWN2 output, the gray scale data to be turned on during that period should be applied. Table 8 is an example of XDOWN2 output status using four LEDs . Table 8. XDOWN2 Output Example
noise reduction
concurrent switching noise reduction
Concurrent switching noise has a potential to occur when multiple outputs turn on or off at the same time. To prevent this noise, the device has delay output terminals such as XGSOUT, BOUT for GSCLK (gray scale clock), and BLANK (blanking signal) respectively. By connecting these outputs to the GSCLK and BLANK terminals of next stage IC, it allows differences in the switching time between ICs. When GSCLK is output to GSOUT through the device, duty will be changed between input and output. The number of stages to be connected will be limited depending on the frequency. delay between constant current output The constant current output has a delay time of approximately 20 ns between outputs. It means approximately 300 ns delay time exists between OUT0 and OUT15. This time difference by delay is effective for the reduction of concurrent switching noise.
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LED NUMBER LED STATUS OUTn 1 2 3 4 GOOD ON GOOD 1 NG ON NG 2 GOOD ON GOOD 3 NG ON NG 4 DETECTION RESULT XDOWN2 LED NUMBER LED STATUS OUTn LOW (by case 2, 4) GOOD ON GOOD 1 NG ON NG 2 GOOD OFF GOOD 3 NG OFF DETECTION RESULT XDOWN2 LED NUMBER LED STATUS OUTn GOOD 4 LOW (by case 2) GOOD OFF GOOD NG GOOD OFF GOOD NG OFF OFF DETECTION RESULT XDOWN2 GOOD GOOD HIGH-IMPEDANCE
POST OFFICE BOX 655303
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21
TLC5911 LED DRIVER
SLLS402 - DECEMBER 1999
PRINCIPLES OF OPERATION others
power supply The following should be taken into consideration:
D D
GND
VCCLOG, VCCANA and VCCLED should be supplied by a single power supply to minimize voltage differences between these terminals. The bypass capacitor should be located between the power supply and GND to eliminate the variation of power supply voltage.
Although GNDLOG, GNDANA, and GNDLED are internally tied together, these terminals should be externally connected to reduce noise influence. thermal pad The thermal pad should be connected to GND to eliminate the noise influence, since it is connected to the bottom side of IC chip. Also, the desired thermal effect will be obtained by connecting this pad to the PCB pattern with better thermal conductivity.
power rating free-air temperature
4.7
3.2
2.3
1.48
0 -20 0 25 85
0
TA - Free-Air Temperature - C NOTES: A. The IC is mounted on PCB. PCB size : 102 x 76 x 1.6 [mm3], four layers with the internal two layers being plane. The thermal pad is soldered to the PCB pattern of 10 x 10 [mm2]. For operation above 25C free-air temperature, derate linearly at the rate of 38.2 mW/C. VCC(LOG)=VCC(ANA)=VCC(LED)=5 V, IOL(C) = 80 mA, ICC is a typical value. B. The thermal impedance will be varied depending on the mounting conditions. Since the PZP package established a low thermal impedance by radiating heat from the thermal pad, the thermal pad should be soldered to the pattern with a low thermal impedance. C. The material for the PCB should be selected considering the thermal characteristics since the temperature will rise around the thermal pad.
Figure 10. Power Rating
22
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Output Voltage (Constant Current) - V
PD - Total Power Dissipation - W
TLC5911 LED DRIVER
SLLS402 - DECEMBER 1999
PRINCIPLES OF OPERATION
90 80
70
60
IOL(C) - mA
50
40
30
20
10
0 0.1
1.0 R(IREF) (k)
10.0
Conditions : VO = 1 V, V(IREF) = 1.2 V
I
OL(C)
(mA)
^ R (IREF)(kW)
V (V) (IREF)
38
R
(IREF)
(kW)
^I
46 OL(C) (mA)
NOTE: The brightness control and dot corrected value are set at 100%. The resistor, R(IREF), should be located as close as possible to the IREF terminal to avoid noise influence.
Figure 11. Current on Constant Current Output vs External Resistor
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SLLS402 - DECEMBER 1999
TLC5911 LED DRIVER
24 RSEL0 RSEL1 DPOL XOE XENABLE tsu(XENABLE-DCLK)
POST OFFICE BOX 655303 * DALLAS, TEXAS 75265
Template Release Date: 7-11-94
1/f(DCLK)
th(XENABLE-DCLK)
DCLK tsu(DIN-DCLK) DIN0 D00_A D01_A D02_A tw(l)(DCLK) D0E_A D0F_A tw(h)(DCLK) D00_B D0D_B D0E_B D0F_B D00_C D01_C
DIN9
D90_A
D91_A
D92_A
D9E_A
D9F_A
D90_B
D9D_B
D9E_B
D9F_B
D90_C
D91_C
th(DIN-DCLK) XLATCH
th(XLATCH-DCLK)
tsu(XLATCH-DCLK)
tw(h)(XLATCH) DOUT0 HI-Z D00_A D01_A D0E_A D0F_A D00_B
DOUT9
HI-Z td(XOE-DOUT)
D90_A
D91_A
D9E_A
D9F_A
D90_B td(XOE-DOUT)
td(DCLK-DOUT)
DPOL
DCLK
DPOL and DCLK can be replaced with the combination of these signals enclosed by the parenthesis (Both are inverted each other).
Figure 12. Timing Diagram (Shift Register for Gray Scale Data)
BCENA
RSEL0
tsu(RSEL-XLATCH)
th(RSEL-XLATCH)
RSEL1
XOE td(XOE-DOUT) DPOL
XENABLE tsu(RSEL-DCLK) DCLK tsu(RSEL-DCLK)
POST OFFICE BOX 655303 * DALLAS, TEXAS 75265
DIN0
D0_A
D0_B
D0_C
D0_J
D0_K
D0_L
D0_M
D0_N
D0_O
DIN9
D9_A
D9_B
D9_C th(XLATCH-DCLK)
D9_J
D9_K
D9_L
D9_M
D9_N
D9_O
XLATCH tw(h)(XLATCH) BCL_0-5 Default Value 1 D<5:0>_A Default Value 1
(Brightness Control Latch-Internal Signal) BCL_6-9 Default Value 0 tsu(RSEL-DOUT) DOUT0 HI-Z D<9:6>_A td(DCLK-DOUT) D0_A D0_C D0_E D0_F D0_G Default Value 0 td(XOE-DOUT) D0_H D0_I
SLLS402 - DECEMBER 1999
TLC5911 LED DRIVER
DOUT9
HI-Z
D9_A
D9_C
D9_E
D9_F
D9_G
D9_H
D9_I
DPOL and DCLK can be replaced with signals inverted each other same as shift register for gray scale data.
Figure 13. Timing Diagram (Shift Register for Brightness Control)
25
SLLS402 - DECEMBER 1999
TLC5911 LED DRIVER
26 DCENA RSEL0 tsu(XENABLE-DCLK) RSEL1 tsu(RSEL-XDCLAT) tsu(RSEL-DCCLK) DCCLK
POST OFFICE BOX 655303 * DALLAS, TEXAS 75265
Template Release Date: 7-11-94
th(RSEL-XDCLAT) tsu(RSEL-DCCLK)
DCDIN0
D0_A
D0_B
D0_C
D0_J
D0_K
D0_L
D0_M
D0_N
D0_O
DCDIN5
D5_A
D5_B
D5_C th(XDCLAT-DCCLK)
D5_J
D5_K
D5_L
D5_M
D5_N
D5_O
XDCLAT tw(h)(XDCLAT) DCL_0-15 Default Value "1" (Note) Dx<15:0>_A td(DCCLK-DCDOUT) D0_A D0_C D0_E D0_F D0_G D0_H D0_I Default Value "1"
(Dot Correction Latch-Internal Signal: 6 bit x 16) DCDOUT0
DCDOUT5
D5_A
D5_C
D5_E
D5_F
D5_G
D5_H
D5_I
NOTE : Register value is immediately before DCLAT.
Figure 14. Timing Diagram (Shift Register for Dot Correction: Using Port B)
RSEL0
RSEL1 tsu(RSEL-XLATCH) XOE td(XOE-DOUT) DPOL th(RSEL-XLATCH)
XENABLE tsu(RSEL-DCLK)
POST OFFICE BOX 655303 * DALLAS, TEXAS 75265
tsu(RSEL-DCLK)
DCLK
DIN0 ...
D0_A
D0_B
D0_C
D0_J
D0_K
D0_L
D0_M
D0_N ... D9_N
D0_O
DIN9
D9_A
D9_B
D9_C th(XLATCH-DCLK)
D9_J
D9_K
D9_L
D9_M
D9_O
XLATCH tsu(RSEL-DOUT) DOUT0 HI-Z HI-Z td(DCLK-DOUT) D0_A D5_A tw(h)(XLATCH) D0_C D5_C D0_E D5_E D0_F D5_F D0_G D5_G td(XOE-DOUT) D0_H D5_H D0_I D5_I
DOUT5
DOUT <9:6>
td(XOE-DOUT) HI-Z td(DCLK-DCDOUT)
SLLS402 - DECEMBER 1999
TLC5911 LED DRIVER
DCDOUT0 DCDOUT5 ...
D0_A D5_A
D0_C D5_C
D0_E D5_E
D0_F D5_F
D0_G D5_G
D0_H D5_H
D0_I D5_I
DPOL and DCLK can be replaced with signals inverted each other same as shift register for gray scale data.
Figure 15. Timing Diagram (Shift Register for Dot Correction: Using Port A)
27
SLLS402 - DECEMBER 1999
TLC5911 LED DRIVER
28
POST OFFICE BOX 655303 * DALLAS, TEXAS 75265
XLATCH tsu(XLATCH-GSCLK) BLANK
Template Release Date: 7-11-94
GSPOL tsu(BLANK-GSCLK) GSCLK 1/f(WDT) WDTRG tw(l)(WDTRG) tw(h)(WDTRG) td(BLANK-OUT0) OUT0 td(OUTn+1-OUTn) OUT1 OFF ON (See Note1) OFF td(GSCLK-OUT0) ON (See Note1) OFF td(GSCLK-OUT0) (SeeNote1) td(OUTn+1-OUTn) OFF (SeeNote1) OFF (SeeNote1) twdt OFF (SeeNote1) tw(l)(GSCLK) tw(h)(GSCLK) td(BLANK-OUT0) 1/f(GSCLK)
OUT15
OFF
ON (See Note1)
OFF
(SeeNote1)
OFF
(SeeNote1)
XDOWN1 XDOWN2
HI-Z (See Note2) td(GSCLK-XDOWN2) td(BLANK-BOUT) (See Note2) (See Note2)
BOUT td(GSCLK-XGSOUT) XGSOUT td(LEDCHK-XDOWN2) LEDCHK GSPOL, GSCLK and XGSOUT can be replaced with signals inverted each other. NOTE 1: ON or OFF, or ON time is varied depend on the gray scale data and BLANK. NOTE 2: When LED is disconnected. td(LEDCHK-XDOWN2)
Figure 16. Timing Diagram (Constant Current Output) - MAG0 to MAG2 Are All Zero
TLC5911 LED DRIVER
SLLS402 - DECEMBER 1999
MECHANICAL DATA
PZP (S-PQFP-G100)
0,27 0,17 51
PowerPADTM PLASTIC QUAD FLATPACK
0,50 75
0,08 M
76
50
Thermal Pad (see Note D)
100
26 0,13 NOM 1 12,00 TYP 14,20 SQ 13,80 16,20 SQ 15,80 0,25 0,15 0,05 0,75 0,45 Seating Plane 0- 7 Gage Plane 25
1,05 0,95
1,20 MAX
0,08 4146929/A 04/99
NOTES: A. B. C. D.
All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane. This pad is electrically and thermally connected to the backside of the die and possibly selected leads.The dimensions of the thermal pad are 2 mm x 2 mm (maximum). The pad is centered on the bottom of the package. E. Falls within JEDEC MS-026
PowerPAD is a trademark of Texas Instruments Incorporated.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
29
IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 2000, Texas Instruments Incorporated

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