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TL16PC564A PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER
SLLS172B - MAY 1994 - REVISED MARCH 1996
D D D D D D D
Integrated Asynchronous Communications Element Compatible With PCMCIA PC Card Standard Release 2.01 Consists of a Single TL16C550 ACE Plus PCMCIA Interface Logic Provides Common I Bus/Z Bus Microcontroller Inputs for Most IntelTM and ZilogTM Subsystems Fully Programmable 256-Byte Card Information Structure and 8-Byte Card Configuration Register Adds or Deletes Standard Asynchronous Communication Bits (Start, Stop and Parity) to or From Serial Data Stream Transmit, Receive, Line Status, and Data Set Interrupts Independently Controlled Selectable Serial Bypass Mode Provides Subsystem With Direct Parallel Access to the FIFOs
D
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Fully Programmable Serial Interface Characteristics: - 5-, 6-, 7-, or 8-Bit Characters - Even-, Odd-, or No-Parity Bit Generation and Detection - 1-, 1 1/2-, or 2-Stop Bit Generation - Baud Rate Generation Fully Prioritized Interrupt System Controls Modem Control Functions Provides TL16C450 Mode at Reset Plus Selectable Normal TL16C550 Operation or Extended 64-Byte FIFO Mode Selectable Auto-RTS Mode Deactivates RTS at 14 Bytes in 550 Mode and at 56 Bytes in Extended 550 Mode Selectable Auto-CTS Mode Deactivates Serial Transfers When CTS is Inactive
description
The TL16PC564A is designed to provide all the functions necessary for a Personal Computer Memory Card International Association (PCMCIA) universal asynchronous receiver transmitter (UART) subsystem interface. This interface provides a serial-to-parallel conversion for data to and from a modem coder decoder/digital signal processor (CODEC/DSP) function to a PCMCIA parallel data port format. A computer central processing unit (CPU), through a PCMCIA host controller, can read the status of the asynchronous communications element (ACE) interface at any point in the operation. Reported status information includes the type of transfer operation in process, the status of the operation, and any error conditions encountered. Attribute memory consists of a 256-byte card information structure (CIS) and eight 8-byte card configuration registers (CCR). The CIS, implemented with a dual port random access memory (DPRAM), is available to both the host CPU and subsystem (modem), as are the CCRs. This DPRAM is used in place of the electrically erasable programmable read-only memory (EEPROM) normally used for the CIS. At power up, attribute memory is initialized by the subsystem. The TL16PC564A uses a TL16C550 ACE-type core with an expanded 64 x 11 receiver first-in-first-out (FIFO) memory and a 64 x 8 transmitter FIFO memory. The receiver trigger logic flags have been adjusted in order to take full advantage of the increased capacity when in the extended mode. In addition, eight of the UART registers have been mapped into the subsystem (modem) memory space as read-only registers. This allows the subsystem to read UART status information. A subsystem selectable serial bypass mode has been implemented to allow the subsystem to bypass the serial portion of the UART and write directly to the receiver FIFO and read directly from the transmitter FIFO. The interrupt operation is not affected in this mode. The TL16PC564A is packaged in a 100-pin thin quad flat package (PZ).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Patent pending Intel is a trademark of Intel Corporation. Zilog is a trademark of Zilog Corporation.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 1996, Texas Instruments Incorporated
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TL16PC564A PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER
SLLS172B - MAY 1994 - REVISED MARCH 1996
PZ PACKAGE (TOP VIEW)
EXTEND VTEST SSAB GND ARBCLKI GND ARBCLKO ARBPGM0 ARBPGM1 VCC RST NANDOUT GND SAD7 SAD6 GND SAD5 SAD4 SAD3 SAD2 VCC VCC SAD1 SA8 SAD0
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
HD3 HD4 HD5 VCC HD6 HD7 CE1 OE HA9 GND HA8 WE IREQ HA7 VCC HA6 HA5 HA4 HA3 HA2 GND HA1 HA0 HD0 HD1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
HD2 STSCHG REG VCC INPACK TESTOUT GND GND RESET GND SA7 IOWR IORD CE2 SA6 VCC SA5 SA4 SA3 SA2 SA1 GND SA0 VCC UARTCLK
The terminal names not enclosed in parentheses correspond to an Intel microcontroller signal, and the terminal names enclosed in parentheses correspond to a Zilog microcontroller signal.
2
ALE (AS) IRQ SELZ/I RD(DS) GND WR(R/W) CS SIN DTR RTS VCC OUT1 BAUDOUT GND RCLK GND XIN GND OUT2 SOUT DSR VCC DCD CTS RI
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SLLS172B - MAY 1994 - REVISED MARCH 1996
block diagram
HD7 - HD0 95, 96, 98 - 100, 75 - 77 92, 90, 87, 85 - 81, 79, 78 10 73 94 62 89 93 63 8 10 DATA ADDR
HA9 - HA0 REG CE1 CE2 WE OE IORD
Host CPU Control Logic 10 Reset Control 8
OE WE Reset Attribute Memory (CIS 256 x 8, CCR 8 x 8 plus arbitration logic)
ARBCLKI ARBPGM1 - ARBPGM0 SAD7 - SAD0 SA8-SA0 SELZ / I SSAB ALE(AS) WR(R/W) RD(DS) CS
5 9,8 2 8 14, 15, 17 - 20, 23, 25 8 24,65,61, 59 - 55,53 28 3 26 31 29 32 9 9 Subsystem Control Logic DATA
ADDR OE WE
7
ARBCLKO
Reset
71 74 27 88 51 11
INPACK STSCHG IRQ IREQ UARTCLK RST
RESET
67
Reset Validation UART TL16C550C 6 Divide by N UART Select Master Clock Reset 38 34 37 44 35 45 BAUDOUT DTR OUT1 OUT2 RTS SOUT
IOWR EXTEND
64 1
XIN SIN RCLK CTS DCD DSR RI
42 33 40 49 48 46 50
Reset
Bit 0 is the least significant bit (LSB).
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SLLS172B - MAY 1994 - REVISED MARCH 1996
Terminal Functions
TERMINAL NAME ALE (AS) NO. 26 INTER INTERFACE S I/O I DESCRIPTION Address latch enable/address strobe. ALE(AS) is an address latch enable in the Intel mode and an address strobe in the Zilog mode. ALE (AS) is active high for an Intel subsystem and active low for a Zilog subsystem. Arbitration clock output. ARBCLKO is equal to the input on ARBCLKI divided by the binary coded divisor input on ARBPGM (1 - 0). Arbitration clock input. ARBCLKI is the base clock used in arbitration for the attribute memory DRAM and the reset validation circuitry. Arbitration clock divisor program. These two bits set the divisor for ARBCLKI. Clock divisors 1, 2, 4, and 8 are available. Baud output. BAUDOUT is an active-low 16 x signal for the transmitter section of the UART. The clock rate is established by the reference clock (UARTCLK) frequency divided by a divisor specified by the baud rate generator divisor latches. BAUDOUT may also be used for the receiver section by tying this output to the RCLK input. Card enable 1 and card enable 2 are active-low signals. CE1 enables even numbered address bytes, and CE2 enables odd numbered address bytes. A multiplexing scheme based on HA0, CE1, and CE2 allows an 8-bit host to access all data on HD0 through HD7 if desired. These signals have internal pullup resistors. Chip select. CS is the active-low chip select from the Zilog or Intel microcontroller. Clear to send. CTS is an active-low modem status signal. Its condition can be checked by reading bit 4 (CTS) of the modem status register (MSR). Bit 0 (delta clear to send) of the MSR indicates that the signal has changed states since the last read from the MSR. If the modem status interrupt is enabled when CTS changes states, an interrupt is generated. Data carrier detect. DCD is an active-low modem status signal. Its condition can be checked by reading bit 7 (DCD) of the MSR. Bit 3 (delta data carrier detect) of the MSR indicates that the signal has changed states since the last read from the MSR. If the modem status interrupt is enabled when DCD changes states, an interrupt is generated. Data set ready. DSR is an active-low modem status signal. Its condition can be checked by reading bit 5 (DSR) of the MSR. Bit 1 (delta data set ready) of the MSR indicates that the signal has changed states since the last read from the MSR. If the modem status interrupt is enabled when DSR changes states, an interrupt is generated. Data terminal ready. DSD is an active-low signal. When active, DTR informs the modem or data set that the UART is ready to establish communication. DTR is placed in the active state by setting the DTR bit 0 of the modem control register (MCR) to a high level. DTR is placed in the inactive state either as a result of a reset, doing a loop mode operation, or clearing bit 0 (DTR) of the MCR. FIFO extend. When EXTEND is high, the UART is configured as a standard TL16C550 with 16-byte transmit and receive FIFOs. When EXTEND is low and FIFO control register (FCR) bit 5 is set, the FIFOs are extended to 64 bytes and the receiver interrupt trigger levels adjust accordingly. EXTEND low in conjunction with FCR bit 4 set high enables the auto-RTS. Common ground
ARBCLKO ARBCLKI ARBPGM0 ARBPGM1 BAUDOUT
7 5 8 9 38
M M M U
O I I O
CE1 CE2
94 62
H
I
CS CTS
32 49
S U
I I
DCD
48
U
I
DSR
46
U
I
DTR
34
U
O
EXTEND
1
U
I
GND
4, 6, 13,16,30, 39,41, 43, 54, 66, 68, 69,80, 91
M
HA0 78 H I H address bus. The 10-bit address bus addresses the attribute memory (bits 1 - 8) and HA1 79 addresses the internal UART as either PCMCIA I/O (bits 0 - 2) or as a standard COM port HA2 81 (bits 0 - 9). HA3 82 HA4 83 HA5 84 HA6 85 HA7 87 HA8 90 HA9 92 Host = H, Subsystem = S, UART = U, Miscellaneous = M
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Terminal Functions (Continued)
TERMINAL NAME HD0 HD1 HD2 HD3 HD4 HD5 HD6 HD7 INPACK IORD NO. 77 76 75 100 99 98 96 95 71 63 INTER INTERFACE H I/O I/O DESCRIPTION H data bus. The 8-bit bidirectional data bus transfers data to and from the attribute memory and the internal UART.
H H
O I
Input port acknowledge. INPACK is an active-low output signal that is asserted when the card responds to an I/O read cycle at the address on the HA bus. I/O read strobe. IORD is an active-low input signal activated to read data from the card I/O space. The REG signal and at least one of the card enable inputs (CE1, CE2) must also be active for the I/O transfer to take place. This signal has an internal pullup resistor. I/O write strobe. IORW is an active-low input signal activated to write data to the card I/O space. The REG signal and at least one of the card enable inputs (CE1, CE2) must also be active for the I/O transfer to take place. This signal has an internal pullup resistor. Interrupt request. IREQ is an active-low output signal asserted by the card to indicate to the host CPU that a card device requires host software service. This signal doubles as the READY/BUSY signal during power-up initialization. Interrupt request. An active-high IRQ to the subsystem indicates a host CPU write to attribute memory has occurred. This is a production test output. Output enable. OE is an active-low input signal that gates memory read data from the card. This signal has an internal pullup resistor. Output 1 and output 2 are active-low signals. OUT1 and OUT2 are user-defined output terminals that are set to their active state by setting the respective MCR bits (OUT1 and OUT2). OUT1 and OUT2 are set to their inactive (high) state as a result of a reset, by doing loop mode operation, or by clearing bit 2 (OUT1) or bit 3 (OUT2) of the MCR. These signals have open-drain outputs. Receiver clock. RCLK is the 16 x-baud rate clock input for the receiver section of the UART. Read enable or data strobe input. RD(DS) is the active-low read enable in the Intel mode and the active-low data strobe in the Zilog mode. Attribute memory select. This active-low input signal is generated by the host CPU and accesses attribute memory (OE and WE active) and I/O space (IORD or IOWR active). PCMCIA common memory access is excluded. This signal has an internal pullup resistor and hysteresis on the input buffer. Reset. RESET is an active-high input that serves as the master reset for the device. RESET clears the UART, placing the card in an unconfigured state. This signal has an internal pullup resistor. Ring indicator. RI is an active-low modem status signal. Its condition can be checked by reading bit 6 (RI) of the MSR. The trailing edge of ring indicator (TERI) bit 2 of the MSR indicates that RI has transitioned from a low to a high state since the last read from the MSR. If the modem status interrupt is enabled when this transition occurs, an interrupt is generated. This is the qualified active-low reset signal. RST has a fail safe open-drain output. Request to send. RTS is an active-low signal. When active, RTS informs the modem of the data set that the UART is ready to receive data. RTS is set to its active state by setting the RTS modem control register bit and is set to its inactive (high) state either as a result of a reset, by doing a loop mode operation, or by clearing bit 1 (RTS) of the MCR.
IOWR
64
H
I
IREQ
88
H
O
IRQ NANDOUT OE OUT1 OUT2
27 12 93 37 44
S M H U
O O I O
RCLK RD(DS) REG
40 29 73
U S H
I I I
RESET
67
H
I
RI
50
U
I
RST RTS
11 35
M U
O O
Host = H, Subsystem = S, UART = U, Miscellaneous = M
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TL16PC564A PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER
SLLS172B - MAY 1994 - REVISED MARCH 1996
Terminal Functions (Continued)
TERMINAL NAME SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SAD0 SAD1 SAD2 SAD3 SAD4 SAD5 SAD6 SAD7 SELZ / I SIN NO. 53 55 56 57 58 59 61 65 24 25 23 20 19 18 17 15 14 28 33 INTER INTERFACE S I/O I DESCRIPTION Subsystem address bus. When SSAB is high, this is the subsystem address bus and SAD (7- 0) is the subsystem data bus. When SSAB is low, this bus is not used and SAD(7- 0) is the subsystem multiplexed address/data bus.
S S
I I/O
Address bit 8 is bit 8 of the subsystem address bus. Subsystem address/data bus. This is a multiplexed bidirectional address/data bus to the attribute memory DPRAM and CCRs when SSAB is low. This becomes a bidirectional data bus when SSAB is high.
S U
I I
Select Zilog or Intel mode. SELZ / I selects between a Zilog-like or Intel-like microcontroller. SELZ / I is asserted high to select Zilog. SELZ / I is asserted low to select Intel. Serial data input. SIN moves information from the communication line or modem to the TL16PC564A UART receiver circuits. Data on the serial bus is disabled when operating in the loop mode. Serial out. SOUT is the composite serial data output to a connected communication device. SOUT is set to the marking (high) state as a result of a reset. Separate subsystem address bus. SSAB selects between a multiplexed address/data bus subsystem interface (SSAB = 0) and a subsystem interface with separate address and data buses (SSAB = 1). This signal has an internal pulldown resistor. Status change. STSCHG is an optional active-low output signal that alerts the host that a subsystem write to attribute memory has occurred. This signal has an open-drain output. Test output. This is a production test output. UART clock. UARTCLK is a clock output. Its frequency is determined by the frequency on XIN and the divisor value on the programmable clock (PGMCLK) register. 3.3-V or 5-V supply voltage
SOUT SSAB
45 3
U S
O I
STSCHG TESTOUT UARTCLK VCC
74 70 51 10,21, 22, 36, 47,52, 60, 72, 86, 97 2 89 31 42
H M M M
O O O
VTEST WE WR(R/W) XIN
M H S M
I I I I
Voltage test. VTEST is an active-high production test input with an internal pulldown resistor. It can be left open or tied to ground. Write enable. WE is an active-low input signal used for strobing attribute memory write data into the card. This signal has an internal pullup resistor Write or read/write enable. WR(R/W) is the active-low write enable in the Intel mode and read/write in the Zilog mode. Crystal input. XIN is a clock input divided internally based on the PGMCLK register value, then used as the primary UART clock input.
Host = H, Subsystem = S, UART = U, Miscellaneous = M
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detailed description
reset validation circuit A reset validation circuit has been implemented to qualify the active-high RESET input. At power up, the level on the RST output is unknown. Whenever RESET is stable for at least eight ARBCLKIs, RST reflects the inverted state of that stable value of RESET. Any changes on RESET must be valid for eight ARBCLKI clocks before the change is reflected on RST. This 8-clock filter provides needed hysteresis on the master reset input. RST is driven by a low noise, open-drain, fail safe output buffer. host CPU memory map The host CPU attribute memory space is mapped as shown in Table 1. Table 1. Host CPU Attribute Memory Space
Host CPU Address Bits 9-1 (HA0 = 0) 0 - 255 256 257 258 259 260 261 262 263 Attribute Memory Space CIS CCR0 CCR1 CCR2 CCR3 CCR4 CCR5 CCR6 CCR7
The host CPU I/O space is mapped as shown in Table 2. Table 2. Host CPU I/O Memory Space
Normal Mode 0 (DLAB = 0) 0 (DLAB = 0) 0 (DLAB = 1) 1 (DLAB = 0) 1 (DLAB = 1) 2 2 3 4 5 6 7 Address Mode (hex) COM1 3F8 3F8 3F8 3F9 3F9 3FA 3FA 3FB 3FC 3FD 3FE 3FF COM2 2F8 2F8 2F8 2F9 2F9 2FA 2FA 2FB 2FC 2FD 2FE 2FF COM3 3E8 3E8 3E8 3E9 3E9 3EA 3EA 3EB 3EC 3ED 3EE 3EF COM4 2E8 2E8 2E8 2E9 2E9 2EA 2EA 2EB 2EC 2ED 2EE 2EF I/O Space UART receiver buffer register (RBR) - read only UART transmitter holding register (THR) - write only UART divisor latch LSB (DLL) UART interrupt enable register (IER) UART divisor latch MSB (DLM) UART interrupt identification register (IIR) - read only UART FIFO control register (FCR) - write only UART line control register (LCR) UART modem control register (MCR) - bit 5 read only UART line status register (LSR) UART modem status register (MSR) UART scratch register (SCR)
DLAB is bit 7 of the line control register (LCR).
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TL16PC564A PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER
SLLS172B - MAY 1994 - REVISED MARCH 1996
subsystem memory map The subsystem attribute memory space is mapped as shown in Table 3. Table 3. Subsystem Attribute Memory Space
Subsystem Address Bits 8-0 0 - 255 256 257 258 259 260 261 262 263 Attribute Memory Space CIS CCR0 CCR1 CCR2 CCR3 CCR4 CCR5 CCR6 CCR7
The subsystem control space is mapped as shown in Table 4. Table 4. Subsystem Control Memory Space
Subsystem Address Bits 8 - 0 272 288 Control Space Control Register PGMCLK Register (write only)
The subsystem UART space is mapped as shown in Table 5. Table 5. Subsystem UART Memory Space
Subsystem Address Bits 8 - 0 304 304 305 306 307 308 309 310 311 320 320 UART Space UART MCR bit 5 (write only) UART DLL (read only) UART IER (read only) UART FCR (read only) UART LCR (read only) UART MCR (read only) UART LSR (read only) UART MSR (read only) UART DLM (read only) UART transmitter FIFO (read only) UART receiver FIFO (write only)
Only when serial bypass mode is enabled
host CPU/attribute memory interface The host CPU/attribute memory interface is comprised of one port of the internal DPRAM, the eight CCRs, and necessary control circuitry. Signals HA0 and CE1 are gated together internally so that the output of the gate is low when both signals have been asserted by the host CPU. This output is combined with REG and the decoded address, HA(9-1), to provide the chip enable for the DPRAM and CCRs. This composite chip enable in combination with WE or OE allows writes and reads to the DPRAM and CCRs.
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subsystem/attribute memory interface The subsystem/attribute memory interface is comprised of the second port of the internal DPRAM, the eight CCRs, and necessary control circuitry. When in multiplexed mode (SSAB = 0), the combination of signals SELZ/I and ALE(AS) allows either a positive pulse Intel or a negative pulse Zilog address latch enable strobe to latch the address on SA8 and SAD(7- 0). When in the Zilog mode (SELZ /I high), the combination of read/write [WR(R/W)], data strobe [RD(DS)], and decoded address allows ZBUS access. When in the Intel configuration (SELZ/I low), the combination of read [RD(DS)], write [WR(R/W)], and decoded address allows IBUS access. When in nonmultiplexed mode (SSAB = 1), SA(7- 0) become the lower-order address bits, SAD(7- 0) are strictly the bidirectional data bus, and ALE(AS) is nonfunctional. All other interface signals function the same. Table 6. Subsystem/Attribute Memory Interface
SSAB 0 0 0 0 1 1 1 1 SELZ /I 0 0 1 1 0 0 1 1 RD(DS) 0 1 0 0 0 1 0 0 WR(R/W) 1 0 1 0 1 0 1 0 Address SA8, SAD(7- 0) SA8, SAD(7- 0) SA8, SAD(7- 0) SA8, SAD(7- 0) SA(8 - 0) SA(8 - 0) SA(8 - 0) SA(8 - 0) Operation Intel read Intel write Zilog read Zilog write Intel read Intel write Zilog read Zilog write
attribute memory arbitration Arbitration for the attribute memory is necessary whenever there is simultaneous access to the same DPRAM or CCR address for the conditions of:
* * *
Host CPU read and subsystem write Host CPU write and subsystem read Host CPU write and subsystem write
If arbitration were not provided, attribute memory data would be corrupted and invalid data read due to uncontrolled access to the same DPRAM or CCR address. The arbitration control circuitry synchronizes the asynchronous accesses of the host CPU and subsystem to the DPRAM and CCR and controls the access based on the pending host CPU and subsystem attribute memory operation. The synchronizing and control circuitry needs a clock called the arbitration clock. The external clock (ARBCLKI) goes through a programmable divider and can be divided by 1, 2, 4, or 8 to generate a clock frequency within an allowed range for the arbitration logic to work correctly. The output of this frequency divider is named ARBCLKO. The programmable divider bits are defined as shown in Table 7. Table 7. Programmable Divider Bits
ARBPGM1 L L H H ARBPGM0 L H L H INTERNAL ARBITRATION CLOCK ARBCLKI/1 ARBCLKI/2 ARBCLKI/4 ARBCLKI/8
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SLLS172B - MAY 1994 - REVISED MARCH 1996
attribute memory arbitration (continued) The upper period limit of ARBCLKO is N/6, where N (ns) is the shortest of the two attribute memory accesses, to either the host CPU or the subsystem. The lower period limit of ARBCLKO is based on the DPRAM specifications at the supply voltage used: 5 V = 14-ns clock cycle (71 MHz) 3.3 V = 26-ns clock cycle (38.5 MHz) For any arbitration condition, attribute memory access is controlled to ensure valid data is read for a port that is doing a read operation and valid data is written for a port that is doing a write operation. When both the host CPU and subsystem are performing simultaneous write operations to the same address, the host CPU is allowed to write and the subsystem write is ignored. host CPU/subsystem handshake Two signals are provided for handshaking between the host CPU and the subsystem. The active-high IRQ signifies to the subsystem that the host CPU has written data into attribute memory. The subsystem can clear IRQ by setting bit 6 of the subsystem control register. The active-low STSCHG signifies to the host CPU that the subsystem has written data to attribute memory provided bit 2 of the subsystem control register (STSCHG enable) is set. The host CPU clears STSCHG by reading any location in attribute memory. The control of these signals is synchronized to ARBCLKO to ensure there are no false assertions/deassertions. There is additional arbitration performed for instances of simultaneous assertion/deasseration of IRQ or STSCHG. When a subsystem write and host CPU read occur simultaneously, STSCHG may be briefly deasserted prior to being asserted, but the write ultimately wins arbitration. If the host CPU read occurs more than one-half an arbitration clock after the subsystem write, STSCHG is deasserted. IRQ is arbitrated in a similar fashion. host CPU/UART interface The UART select is derived from either host CPU address information or logic levels on CE1, CE2 and REG. In the address mode, host CPU address bits HA9, HA7, HA6, HA5, and HA3 are combined with conditional derivatives of HA4 and HA8 to select the UART (HA4 and HA8 select COM ports 1 - 4 based on settings in the subsystem control register). CE1 and CE2 are combined such that either of these two signals in combination with REG enable the UART in the event that these signals are present. In the event that CE1 or CE2 are not present, the UART must be accessed in the address mode previously described. The UART select in conjunction with IORD and IOWR allows host CPU accesses to the UART. Host CPU address bits HA2-HA0 are decoded to select which UART register is to be accessed. All UART registers remain intact with the exception of the FIFO control register (FCR) and the modem control register (MCR). The FCR (host CPU write-only address 2) bits 4 and 5 in conjunction with EXTEND control RTS operation and FIFO depth are shown in Table 8. Table 8. FIFO Control Register and EXTEND Signal Control of FIFO Depth and RTS Operation
BIT 5 X 0 0 1 1 BIT 4 X 0 1 0 1 EXTEND H L L L L RTS OPERATION Normal Normal Auto Normal Auto FIFO DEPTH 16 bytes 16 bytes 16 bytes 64 bytes 64 bytes
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host CPU/UART interface (continued) FCR bit 5 high and EXTEND low redefine the receiver FIFO trigger levels set by FCR bits 6 and 7 are shown in Table 9. Table 9. Receiver FIFO Trigger Level
BIT 7 0 0 1 1 BIT 6 0 1 0 1 RECEIVER FIFO TRIGGER LEVEL 1 16 32 56
The MCR bit 5 (host CPU address 4) is read only. This bit is controlled by the subsystem to enable (high) the auto-CTS mode of operation subsystem/UART interface The UART provides a serial communications channel to the subsystem with enhanced RTS control (see auto-RTS description). This channel is capable of operating at 115 kbps and is the main communications channel to the subsystem (refer to the TL16C550 specification for the detailed description of the serial communications channel). Many of the UART registers have been mapped into the subsystems memory space as read only. In addition, MCR bit 5 (subsystem address 130 hex) is controlled by the subsystem to enable (set) auto-CTS. The subsystem can read the MCR at address 134 hex. When reading the FCR (subsystem address 132 hex), bits 1 and 2 are always set, and bits 4 and 5 are cleared only when EXTEND is low and the host CPU has set them (64-byte FIFOs and auto-RTS enabled) (refer to the subsystem memory map). subsystem control register The subsystem control register is an 8-bit register located at subsystem address 110 (hex). This register is programmed based on host CPU configuration information and has a default selection of COM2 after a valid reset. The bit definitions are as follows (0 = LSB):
D
Bits 0 and 1: These bits define which host COM port the UART is connected to when the chip is in the address mode. COM2 is the default (power-up) condition. COM port selection is shown in Table 10. Table 10. COM Port Selection
BIT 1 0 1 0 1 BIT 0 0 0 1 1 COM PORT COM1 COM2 COM3 COM4
D D
Bit 2: This bit is a host CPU interrupt enable bit. When this bit is set, any subsystem attribute memory write cycle causes STSCHG to be asserted. This bit is cleared after a valid reset. Bit 3: This bit enables or disables address mode selection as described in the host CPU/UART interface description. This bit is cleared (disabling the address mode) after a valid reset.
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subsystem control register (continued)
D
Bits 4 and 5: These bits together ensure adherence to PCMCIA power-up requirements. At power up, the card must operate as a memory card and all host CPU I/O operations must be disabled. IREQ, which doubles as the host CPU READY/BUSY line, powers up low indicating that the memory card is busy. Once the subsystem initializes attribute memory, the subsystem sets bit 4 to indicate that the memory card is ready. Then bit 5 is cleared, changing the configuration from a memory card to an I/O card, enabling host CPU UART accesses. IREQ now becomes the host CPU interrupt request line. Memory card, I/O, and IREQ selection is shown in Table 11. Table 11. Memory Card, I/O, and IREQ Selection
BIT 5 1 1 0
BIT 4 0 1 X
CONFIGURATION Memory card and I/O operation (UART) are disabled; IREQ is low indicating that the card is busy (power-up and reset condition). Memory card and I/O operation (UART) are disabled; IREQ is high indicating that the card is ready. I/O card and I/O operation (UART) are enabled; IREQ now functions as the host CPU interrupt request line.
D D
Bit 6 is a self clearing bit that resets the subsystem IRQ signal. Writing a 1 to this location clears the IRQ interrupt. Bit 7 enables or disables serial bypass mode as described in the subsystem serial bypass mode description. This bit is cleared (disabling serial bypass mode) after a valid reset.
subsystem PGMCLK register/divide-by-n circuit The subsystem PGMCLK register is a 6-bit write-only register located at address 120 hex and selects the divisor of the divide-by-n-and-a-half circuitry. Any write to this register generates a reset to the UART and the divide-by-n circuitry. The divide-by-n circuitry allows for a divisor from 0 to 31.5 in 0.5 increments (PGMCLK0 is the half bit). The divided clock output drives the UART clock input and can be seen on UARTCLK. The UART requires a clock with a minimum high pulse duration of 50 ns and a minimum low pulse duration of 50 ns (10-MHz maximum operating frequency). A programmed divisor between 2 and 7.5 drives the UART clock low for one XIN clock cycle for integer divisors and 1.5 XIN clock cycles for integer-plus-a-half divisors. A programmed divisor of eight or greater drives the UART clock low for four XIN clock cycles for integer divisors and 4.5 XIN clock cycles for integer-plus-a-half divisors. Based on the above parameters, the acceptable XIN/divisor combinations can be derived using XIN input clock. The precision of the programmable clock generator for integer-plus-a-half divisors depends on the closeness to a 50% duty cycle for the XIN input clock (see Table 12). Table 12. Programmable Clock Generator Precision Selection
PGMCLK(0 - 5) VALUE (HEX) 0 0.5 1 1.5 2 (0) (1) (2) (3) (4) to 31.5 (3F) RESULT No clock (driven high) Divide-by-1 Divide-by-1 Divide-by-1 Divide-by-2 to divide-by-31.5
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TL16PC564A PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER
SLLS172B - MAY 1994 - REVISED MARCH 1996
subsystem serial bypass mode The optional serial bypass mode is implemented to allow a high throughput path to/from the host CPU. When this mode is enabled and subsystem control register bit 7 is high, the serial portion of the UART is bypassed and the subsystem has direct parallel access to the receiver FIFO (write address 140 hex) and the transmitter FIFO (read address 140 hex). All host CPU interrupts operate normally except for receiver parity, framing, and breaking interrupts. auto-CTS operation The optional auto-CTS operation is implemented so that the host CPU cannot overflow the modem receive buffer. Auto-CTS operation is enabled when the subsystem sets MCR bit 5 (subsystem address 130 hex). When auto-CTS enabled, deactivating CTS (high) halts the transmitter section of the UART after it completes the current transfer. Once CTS is reactivated (low) by the modem, transfers resume. Interrupt operation is not affected by enabling auto-CTS. auto-RTS operation The optional auto-RTS operation is implemented so that the subsystem cannot overflow the receiver FIFO. Auto-RTS operation is enabled when FCR bit 4 is high and EXTEND is low and operates independently from the trigger level circuitry. In the 16-byte FIFO mode, the RTS bit in the modem control register (bit 1) clears when 14 characters are in the receive FIFO. This action causes RTS to go high (inactive). In the 64-byte FIFO mode, the MCR RTS bit clears when 56 characters are in the receiver FIFO. Interrupt operation is not affected and operates the same way in either auto-RTS or nonauto-RTS mode. When enabled, a receive data available interrupt occurs after the trigger level is reached. The MCR RTS bit must then be set by the host CPU after the receiver FIFO has been read. power consumption The TL16PC564A has low power consumption under the following conditions:
* * * *
32-MHz signal on XIN Divide-by-n is set to give a 1.8432-MHz UARTCLK signal Nominal data VCC = 5 V
The current (ICC) and power consumption are 18 mA (typical) and 90 mW (typical), respectively. These current and power figures fluctuate with changes in the above conditions.
absolute maximum ratings over operating free-air temperature range
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 6 V Input voltage range, VI (standard) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to VCC + 0.5 V Input voltage range, VI (fail safe) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 6.5 V Output voltage range, VO (standard) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to VCC + 0.5 V Output voltage range, VO (fail safe) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 6.5 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Operating free-air operating temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. This applies for external input and bidirectional buffers. VI > VCC does not apply to fail safe terminals. 2. This applies for external output and bidirectional buffers. VO > VCC does not apply to fail safe terminals.
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TL16PC564A PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER
SLLS172B - MAY 1994 - REVISED MARCH 1996
recommended operating conditions
low voltage (3.3 V nominal)
MIN Supply voltage, VCC Input voltage, VI High-level input voltage (CMOS), VIH (see Note 3) Low-level input voltage (CMOS), VIL (see Note 3) Output voltage, VO (see Note 4) High-level output current, IOH Low level output current, IOL current Low-level Input transition time, tt Operating free-air temperature range, TA Junction temperature range, TJ (see Note 6) NOTES: 3. 4. 5. 6. All outputs except RST, STSCHG, OUT1, OUT2 (see Note 5) All outputs except RST RST 0 0 0 25 25 0 3 0 0.7 VCC 0.3 VCC VCC 1.8 3.2 6.4 25 70 115 NOM 3.3 MAX 3.6 VCC UNIT V V V V V mA mA ns C C
Meets TTL levels, VIHmin = 2 V and VILmax = 0.8 V on nonhysteresis inputs. Applies for external output buffers. RST, STSCHG, OUT1, and OUT2 are open-drain outputs, so IOH does not apply. These junction temperatures reflect simulation conditions. Absolute maximum junction temperature is 150C. The customer is responsible for verifying junction temperature.
standard voltage (5 V nominal)
MIN Supply voltage, VCC Input voltage, VI High-level input voltage (CMOS), VIH Low-level input voltage (CMOS), VIL Output voltage, VO (see Note 4) High-level output current, IOH Low-level Low level output current, IOL current Input transition time, tt Operating free-air temperature range, TA All outputs except RST, STSCHG, OUT1, OUT2 (see Note 5) All outputs except RST RST 0 0 25 0 4.75 0 0.7 VCC 0.2 VCC VCC 4 4 8 25 70 NOM 5 MAX 5.25 VCC UNIT V V V V V mA mA ns C
Junction temperature range, TJ (see Note 6) 0 25 115 C NOTES: 4. Applies for external output buffers. 5. RST, STSCHG, OUT1, and OUT2 are open-drain outputs, so IOH does not apply. 6. These junction temperatures reflect simulation conditions. Absolute maximum junction temperature is 150C. The customer is responsible for verifying junction temperature.
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TL16PC564A PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER
SLLS172B - MAY 1994 - REVISED MARCH 1996
electrical characteristics over recommended ranges of operating free-air temperature and supply voltage (unless otherwise noted)
low voltage (3.3 V nominal)
PARAMETER VOH VOL VIT + VIT - Vhys IOZ IIL IIH High-level output voltage Low-level output voltage Positive-going input threshold voltage (see Note 7) Negative-going input threshold voltage (see Note 7) Hysteresis (VIT + - VIT -) (see Note 7) 3-state-output high-impedance current (see Note 8) Low-level input current (see Note 9) High-level input current (see Note 10) Applies for external input and bidirectional buffers with hysteresis. The 3-state or open-drain output must be in the high-impedance state. Specifications only apply with pullup terminator turned off. Specifications only apply with pulldown terminator turned off. VI = VCC or GND VI = GND VI = VCC 0.3 VCC 0.1 VCC 0.3 VCC 10 -1 1 TEST CONDITIONS IOH = rated IOL = rated MIN VCC - 0.55 0.5 0.7 VCC MAX UNIT V V V V V A A A
NOTES: 7. 8. 9. 10.
standard voltage (5 V nominal)
PARAMETER VOH VOL VIT + VIT - Vhys IOZ IIL IIH High-level output voltage Low-level output voltage Positive-going input threshold voltage (see Note 7) Negative-going input threshold voltage (see Note 7) Hysteresis (VIT + - VIT -) (see Note 7) 3-state-output high-impedance current (see Note 8) Low-level input current (see Note 9) High-level input current (see Note 10) Applies for external input and bidirectional buffers with hysteresis. The 3-state or open-drain output must be in the high-impedance state. Specifications only apply with pullup terminator turned off. Specifications only apply with pulldown terminator turned off. VI = VCC or GND VI = GND VI = VCC 0.2 VCC 0.1 VCC 0.3 VCC 10 -1 1 TEST CONDITIONS IOH = rated IOL = rated MIN VCC - 0.8 0.5 0.7 VCC MAX UNIT V V V V V A A A
NOTES: 7. 8. 9. 10.
XIN timing requirements over recommended operating free-air temperature range (see Figure 1)
TEST CONDITIONS Input frequency tc1 1 tw1 1 tw2 2 Cycle time XIN time, Pulse duration, XIN clock high duration Pulse duration, XIN clock low duration VCC = 3.3 V VCC = 5 V VCC = 3.3 V VCC = 5 V VCC = 3.3 V VCC = 5 V VCC = 3.3 V VCC = 5 V 20 16.7 10 8 10 8 MIN MAX 50 60 UNIT MHz ns ns ns
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TL16PC564A PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER
SLLS172B - MAY 1994 - REVISED MARCH 1996
clock switching characteristics over recommended operating free-air temperature range (see Figure 1)
PARAMETER td1 td2 td3 td4 td5 Delay time, XIN to UARTCLK time Delay time, XIN to UARTCLK time TEST CONDITIONS VCC = 3.3 V VCC = 5 V VCC = 3.3 V VCC = 5 V VCC = 3.3 V VCC = 5 V VCC = 3.3 V VCC = 5 V VCC = 3.3 V VCC = 5 V MIN MAX 14 8 16 10 19.8 13 20.6 13.5 21 13.8 UNIT ns ns
Delay time, XIN to UARTCLK time
ns
Delay time, XIN to UARTCLK time
ns
Delay time, XIN to UARTCLK time
ns
host CPU I/O read cycle timing requirements over recommended ranges of operating free-air temperature and supply voltage (see Figure 2 and Note 11)
MIN th1 th2 tw4 tsu1 tsu2 th3 th4 tsu3 Hold time, HA(9 - 0) valid after IORD Hold time, REG valid after IORD Pulse duration, IORD low Setup time, HA(9 - 0) valid before IORD Setup time, CEx before IORD Hold time, CEx after IORD Hold time, HD(7 - 0) valid after IORD Setup time, REG before IORD 20 0 165 70 5 20 0 5 100 MAX UNIT ns ns ns ns ns ns ns ns ns
td6 Delay time, HD(7 - 0) valid after IORD NOTE 11. The maximum load on INPACK is one LSTTL with 50-pF total load. All timing is measured in nanoseconds.
host CPU I/O read cycle switching characteristics over recommended ranges of operating free-air temperature and supply voltage (see Figure 2 and Note 11)
PARAMETER td7 td8 Delay time, INPACK after IORD Delay time, INPACK after IORD MIN MAX 45 45 UNIT ns ns
NOTE 11. The maximum load on INPACK is one LSTTL with 50-pF total load. All timing is measured in nanoseconds.
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TL16PC564A PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER
SLLS172B - MAY 1994 - REVISED MARCH 1996
host CPU I/O write cycle timing requirements over recommended ranges of operating free-air temperature and supply voltage (see Figure 3)
MIN tsu4 th5 tw6 tsu5 th6 tsu6 th7 tsu7 th8 Setup time, HD(7 - 0) valid before IOWR Hold time, HA(9 - 0) valid after IOWR Pulse duration, IOWR low Setup time, HA(9 - 0) valid before IOWR Hold time, REG after IOWR Setup time, CEx before IOWR Hold time, CEx after IOWR Setup time, REG before IOWR Hold time, HD(7 - 0) valid after IOWR 60 20 165 70 0 5 20 5 30 MAX UNIT ns ns ns ns ns ns ns ns ns
transmitter switching characteristics over recommended ranges of operating free-air temperature and supply voltage (see Figure 4)
PARAMETER td9 td10 td11 td12 td13 Delay time, SOUT after IOWR Delay time, IREQ after SOUT Delay time, IREQ after IOWR Delay time, IREQ after IOWR Delay time, IREQ after IORD CL = 100 pF CL = 100 pF TEST CONDITIONS MIN 8 8 16 MAX 24 8 32 140 140 UNIT Baud cycles Baud cycles Baud cycles ns ns
receiver switching characteristics over recommended ranges of operating free-air temperature and supply voltage (see Figure 5)
PARAMETER td14 td15 td16 Delay time, sample CLK after RCLK Delay time, IREQ after SIN Delay time, IREQ after IORD CL = 100 pF TEST CONDITIONS MIN MAX 100 1 150 UNIT ns RCLK cycles ns
modem control switching characteristics over recommended ranges of operating free-air temperature and supply voltage, CL = 100 pF (see Figure 6)
PARAMETER td17 td18 td19 td20 Delay time, RTS, DTR, OUT1, OUT2 or after IOWR Delay time, IREQ after CTS, DSR, DCD Delay time, IREQ after IORD Delay time, IREQ after RI MIN MAX 50 30 35 30 UNIT ns ns ns ns
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TL16PC564A PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER
SLLS172B - MAY 1994 - REVISED MARCH 1996
host CPU attribute memory write cycle timing requirements over recommended ranges of operating free-air temperature and supply voltage (see Figures 7 and 8)
MIN tc2 tw8 tsu8 tsu9 tsu10 tsu11 th9 trec1 tsu12 th10 tsu13 th11 Write cycle tIme, HA(9 - 0) Pulse duration, WE low Setup time, CEx before WE Setup time, HA(9 - 0) before WE (see Note 12) Setup time, HA(9 - 0) before WE and CEx(see Note 12) Setup time, OE before WE Hold time, HD(7 - 0) IN after WE Recovery time, HA(9 - 0) after WE Setup time, HD(7 - 0) IN before WE Hold time, OE after WE Setup time, CEx before WE Hold time, CEx after WE 250 150 180 180 30 10 30 30 80 10 0 20 MAX UNIT ns ns ns ns ns ns ns ns ns ns ns ns
NOTE 12. The REG signal timing is identical to address signal timing.
host CPU attribute memory write cycle switching characteristics over recommended ranges of operating free-air temperature and supply voltage (see Figure 7)
PARAMETER tdis1 tdis2 ten1 ten2 Disable time, HD(7 - 0) OUT after WE Disable time, HD(7 - 0) OUT after OE Enable time, HD(7 - 0) OUT after WE Enable time, HD(7 - 0) OUT after OE 5 5 MIN MAX 100 100 UNIT ns ns ns ns
host CPU attribute memory read cycle timing requirements over recommended ranges of operating free-air temperature and supply voltage (see Figure 9)
MIN tc3 td22 td23 td24 th12 tsu14 th13 tsu15 th14 Read cycle time Delay time, HD(7 - 0) after HA(9 - 0) Delay time, HD(7 - 0) after CEx Delay time, HD(7 - 0) after OE Hold time, HD(7 - 0) after HA(9 - 0) Setup time, CEx before OE Hold time, HA(9 - 0) after OE Setup time, HA(9 - 0) before OE Hold time, CEx after OE 0 0 20 30 20 300 300 300 150 MAX UNIT ns ns ns ns ns ns ns ns ns
host CPU attribute memory read cycle switching characteristics over recommended ranges of operating free-air temperature and supply voltage (see Figure 9)
PARAMETER tdis3 tdis4 ten3 ten4 Disable time, HD(7 - 0) after CEx Disable time, HD(7 - 0) after OE Enable time, HD(7 - 0) after CEx Enable time, HD(7 - 0) after OE 5 5 MIN MAX 100 100 UNIT ns ns ns ns
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TL16PC564A PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER
SLLS172B - MAY 1994 - REVISED MARCH 1996
subsystem Intel mode timing requirements (32 MHz) (see Figure 10)
INTEL SYMBOL tLHLL tAVLL tPLLL tLLAX tLLWL tLLRL tWHLH tAFRL tRLRH tWLWH tRHAX tWHDX tWHPH tRHPH tPHPL JEDEC SYMBOL tw11 tsu16 td25 th15 td26 td27 td28 td29 tw12 tw13 td30 th16 td31 td32 tw14 Pulse duration, ALE high Setup time, SA8, SAD(7 - 0) valid to ALE low Delay time, CS low to ALE low Hold time, SA8, SAD(7 - 0) valid after ALE Delay time, ALE low to WR low Delay time, ALE low to RD low Delay time, WR high to ALE high Delay time, SA8, SAD(7 - 0) in high-impedance state to RD low Pulse duration, RD low Pulse duration, WR low Delay time, RD high to SA8, SAD(7 - 0) active Hold time, SA8, SAD(7 - 0) valid after WR high Delay time, WR high to CS high Delay time, RD high to CS high Pulse duration, CS high MIN 48 21 21 21 16 16 21 0 120 120 48 48 21 21 21 MAX UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
subsystem Zilog mode timing requirements (20 MHz) (see Figure 11)
ZILOG SYMBOL tdA(AS) tdAS(A) tdAS(DR) twAS tdA(DS) twDS(read) twDS(write) tdDS(DR) thDS(DR) tdDS(A) tdDS(AS) tdDO(DS) tdRW(AS) JEDEC SYMBOL tsu17 td33 td34 tw15 td35 tw16 tw17 td36 th17 th18 td37 td38 td39 Setup time, SA8 and SAD(7 - 0) valid before AS high Delay time, AS high to SA8 and SAD(7 - 0) invalid Delay time, AS high to data in on SAD(7 - 0) Pulse duration, AS low Delay time, SA8 and SAD(7 - 0) invalid to DS low Pulse duration, DS low (read) Pulse duration, DS low (write) Delay time, DS low to data in valid Hold time, DS high to data in invalid Hold time, DS high to data out invalid Delay time, DS high to AS low Delay time, SAD(7 - 0) (write data from P) valid to DS low Delay time, R/W active to AS high 0 20 30 10 20 35 0 125 65 80 MIN 20 35 150 MAX UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns
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TL16PC564A PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER
SLLS172B - MAY 1994 - REVISED MARCH 1996
subsystem Intel nonmultiplexed timing requirements (see Figure 12)
MIN tsu18 tw18 tw19 tsu19 ten4 td40 th19 th20 tdis3 Setup time, SA(8 - 0), CS valid to RD, WR Pulse duration, RD low Pulse duration, WR low Setup time, SAD(7 - 0) valid to WR Enable time, RD to SAD(7 - 0) driving Delay time, RD to SAD(7 - 0) valid Hold time, SA(8 - 0), CS valid after RD, WR Hold time, SAD(7 - 0) valid after WR Disable time, RD to SAD(7 - 0) high impedance 30 30 5 15 30 120 120 50 5 105 MAX UNIT ns ns ns ns ns ns ns ns ns
subsystem Zilog nonmultiplexed timing requirements (see Figure 13)
MIN tsu20 tsu21 tw20 tw21 tsu22 ten5 td41 th21 th22 tdis4 Setup time, SA(8 - 0), CS, R/W valid to DS (write) Setup time, SA(8 - 0), CS, R/W valid to DS (read) Pulse duration, DS low (write) Pulse duration, DS low (read) Setup time, SAD(7 - 0) valid to DS Enable time, DS to SAD(7 - 0) driving Delay time, DS to SAD(7 - 0) valid Hold time, SA(8 - 0), CS, R/W valid after DS Hold time, SAD(7 - 0), CS, R/W valid after DS Hold time, DS to SAD(7 - 0) high impedance 30 30 5 15 90 30 65 125 50 5 105 MAX UNIT ns ns ns ns ns ns ns ns ns ns
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SLLS172B - MAY 1994 - REVISED MARCH 1996
ARBCLK switching characteristics over recommended operating free-air temperature range (see Figure 14)
TEST CONDITIONS tc4 4 tc5 5 td42 td43 td44 td45 td46 td47 td48 td49 Cycle time internal arbitration clock ( ARBCLKI / ARBPGM) time, Cycle time, arbitration clock time VCC = 3.3 V VCC = 5 V VCC = 3.3 V VCC = 5 V VCC = 3.3 V VCC = 5 V VCC = 3.3 V VCC = 5 V VCC = 3.3 V VCC = 5 V VCC = 3.3 V VCC = 5 V VCC = 3.3 V VCC = 5 V VCC = 3.3 V VCC = 5 V VCC = 3.3 V VCC = 5 V VCC = 3.3 V MIN 26 14 26 14 13 7.3 15.5 10 15.3 8.8 17.5 11 19.5 11.5 21.5 13.5 22.7 13.5 25 15.7 MAX Note 13 Note 13 UNIT ns ns ns ns ns ns ns ns ns ns
Delay time, ARBCLKI to ARBCLK0 (/ 1) time Delay time, ARBCLKI to ARBCLK0 (/ 1) time
Delay time, ARBCLKI to ARBCLK0 (/ 2) time Delay time, ARBCLKI to ARBCLK0 (/ 2) time Delay time, ARBCLKI to ARBCLK0 (/ 4) time Delay time, ARBCLKI to ARBCLK0 (/ 4) time Delay time, ARBCLKI to ARBCLK0 (/ 8) time Delay time, ARBCLKI to ARBCLK0 (/ 8) time
VCC = 5 V NOTE 13. tc4 max = N/6, where N = shortest (in ns) of the two attribute memory accesses, host CPU or subsystem.
reset timing requirements over recommended ranges of operating free-air temperature and supply voltage (unless otherwise noted) (see Figure 15)
TEST CONDITIONS tw22 tw23 td50 td51 Pulse duration, RESET active Pulse duration, RESET inactive Delay time, ARBCLKI to RST low time Delay time, ARBCLKI to RST high impedance time VCC = 3.3 V VCC = 5 V VCC = 3.3 V VCC = 5 V MIN 8tc5 8tc5 10.4 7.5 13.9 9.7 MAX UNIT ns ns ns ns
subsystem interrupt request timing requirements over recommended ranges of operating free-air temperature and supply voltage (see Figure 16)
MIN td52 td53 Delay time, WE to IRQ (see Note 14) Delay time, SCR bit 6 to IRQ (see Note 15) 2tc5 tc5 MAX 3tc5 2tc5 UNIT ARBCLKI cycles ARBCLKI cycles
NOTES: 14. Synchronized to rising edge of ARBCLKI 15. Synchronized to falling edge of ARBCLKI
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TL16PC564A PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER
SLLS172B - MAY 1994 - REVISED MARCH 1996
host CPU status change timing requirements over recommended ranges of operating free-air temperature and supply voltage (see Figure 17)
MIN td54 td55 Delay time, subsystem write to STSCHG (see Note 14) Delay time, OE to STSCHG high impedance (see Note 15) 2tc5 tc5 MAX 3tc5 2tc5 UNIT ARBCLKI cycles ARBCLKI cycles
NOTES: 14. Synchronized to rising edge of ARBCLKI 15. Synchronized to falling edge of ARBCLKI
PARAMETER MEASUREMENT INFORMATION
N tw1 tc1 XIN tw2 td1 UARTCLK (1/0.5 - 1/1.5) td3 UARTCLK (1/2 - 1/7) 1 XIN Cycle td3 UARTCLK (1/2.5 - 1/7.5) 1.5 XIN Cycles td3 UARTCLK (1/8 - 1/31) 4 XIN Cycles td3 UARTCLK (1/8.5 - 1/31.5) 4.5 XIN Cycles (N - 4.5) XIN Cycles td5 (N - 4)XIN Cycles (N - 1.5)XIN Cycles td4 td5 (N - 1)XIN Cycles td4 td2
The low portion of the UARTCLK cycle = 1 XIN cycle for PGMCLK integer values of 2 to 7 and 1.5 XIN cycles for PGMCLK noninteger values 2.5 to 7.5. The low portion of the UARTCLK cycle = 4 XIN cycles for PGMCLK integer values of 8 to 31 and 4.5 XIN cycles for PGMCLK noninteger values 8.5 to 31.5.
Figure 1. XIN Clock Timing Waveforms
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SLLS172B - MAY 1994 - REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
HA(9 - 0) 90% 10%
50% th1
REG
10% tsu3 th2
10%
CE1, CE2
10% tsu2 tw4 50%
10%
IORD tsu1 INPACK
50% td7
10% td6 td8
HD(7 - 0)
Valid
NOTE A: All timings are measured at the card. Skews and delays from the system driver/receiver to the card must be accounted for by the system design.
Figure 2. Host CPU I/O Read Timing Waveforms
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IIIIIII IIIIIII IIIIIII IIIIIII IIIIIII IIIIIII
th3 10% th4 23
IIIIIII IIIIIII IIIIIII IIIIIII IIIIIII IIIIIII
TL16PC564A PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER
SLLS172B - MAY 1994 - REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
HA(9 - 0)
50%
50% th5
REG
CE1, CE2
IOWR tsu5
HD(7 - 0) NOTE A: All timings are measured at the card. Skews and delays from the system driver/receiver to the card must be accounted for by the system design.
SOUT td9 IREQ td11 IOWR (write transmitter holding register) IORD (read interrupt identification register)
24
IIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIII
10% 10% tsu7 th6 10% 10% tsu6 th7 tw6 50% 50% th8 tsu4
Figure 3. Host CPU I/O Write Timing Waveforms
50%
Start
Data Bits (5 - 8)
Parity
Stop
Start 50% td10
50%
50% td12
50%
50%
50%
td13
50%
Figure 4. Transmitter Timing Waveforms
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TL16PC564A PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER
SLLS172B - MAY 1994 - REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
8 Clocks
RCLK td14 Sample CLK (internal) TL16C450 Mode: SIN Start Data Bits (5 - 8) Parity Stop 50%
Sample CLK td15 IREQ (data read or receive ERR) 50% 50%
td16 IORD (read RBR or read LSR) 50%
Figure 5. Receiver Timing Waveforms
IOWR (write MCR)
50% td17
50% td17 50%
RTS, DTR OUT1, OUT2 CTS, DSR DCD
50%
50%
td18 IREQ 50% td19 IORD (read MSR) 50% 50%
td20 50%
RI
50%
Figure 6. Modem Control Timing Waveforms
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25
TL16PC564A PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER
SLLS172B - MAY 1994 - REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
tc2 90% 10% tsu8 90% 10% 90% 10%
HA(9 - 0)
CE1, CE2
See Note A
10% tsu9
10%
OE
90%
tsu10 90% WE tsu11 10%
tw8 90% 10% th10 tsu12 th9 90% 10% ten2 ten1 90%
See Note B HD(7 - 0) IN
90% Data Input Established 10% tdis1
tdis2 HD(7 - 0) OUT
10%
NOTES: A. The hatched portion may be either high or low. B. When the data I/O terminal is in the output state, no signals shall be applied to HD(7 - 0) by the system.
Figure 7. Host CPU Attribute Memory Write Timing Waveforms (WE Control)
26
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IIIIIIII IIIIIIII
See Note A th11 90% trec1
tsu13
IIIIII IIIIII
TL16PC564A PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER
SLLS172B - MAY 1994 - REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
tc2 90% 10% tsu10 tsu8 CE1, CE2 90% 10% and See Note B 10% 90% 90% 10% trec1
HA(9 - 0)
WE
See Note A
10% tsu12 90% 10%
See Note C
HD(7 - 0)
Data Input Established
NOTES: A. The hatched portion may be either high (H) or low (L). B. OE must be high (H). C. When the data I/O terminal is in the output state, no signals shall be applied to HD(7 - 0) by the system.
Figure 8. Host CPU Attribute Memory Write Timing Waveforms (CE Control)
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IIIIIII IIIIIII
See Note A th9 90% 10% 27
90%
IIIIII IIIIII
TL16PC564A PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER
SLLS172B - MAY 1994 - REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
tc3 td22 90% 10% 90% 10% 90% 10% th12 th13 td23 th14 90%
HA(9 - 0)
CE1, CE2
See Note A
10% tsu14 tsu15 ten3 90% 90%
OE
10% td24 ten4 tdis4 90% 10% 90% 10% 90% 10% tdis3
HD (7 - 0)
NOTE A: The shaded portion may be either high or low.
Figure 9. Host CPU Attribute Memory Read Timing Waveforms
28
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IIIIIIII IIIIIIII
See Note A
IIIIII IIIIII
TL16PC564A PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER
SLLS172B - MAY 1994 - REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
tw11 ALE
50% tsu16
50% td28 P Data td29 td26, td27 tw12, tw13 50% td25 50% td31, td32 50%
50%
th15 P Address 50%
SA8, SAD(7 - 0)
50%
50% td30, th16
WR or RD
tw14 CS
50%
NOTE A: This figure is from the microprocessor perspective, not from the UART perspective.
Figure 10. Subsystem Intel Mode Timing Waveforms
R/W
90% 10% td39
CS td34 SA8, SAD(7 - 0)
90% 10%
90% 10% th18
90% 10%
P Address
90%
90% 10%
10%
P Data Out
P Data In
90% 10%
P Out
10%
90%
td38 tsu17 90% AS 10% tw15 DS 90% 10% 10% td35 td36 90% 10% tw17 tw16 NOTE A: This figure is from the microprocessor perspective, not from the UART perspective. 90% 10% td33
th17 td37 90%
Figure 11. Subsystem Zilog Mode Timing Waveforms
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29
TL16PC564A PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER
SLLS172B - MAY 1994 - REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
SA (8 - 0) CS th19
tsu18 WR or RD
tw18, tw19
tsu19 SAD (7- 0) IN td40 ten4 SAD (7- 0) OUT Data Valid
th20
tdis3
Figure 12. Subsystem Intel Nonmultiplexed Timing Waveforms
SA (8 - 0) CS R/W tsu20 tsu21 DS tw22 tsu22 SAD (7- 0) IN td41 ten5 SAD (7- 0) OUT Data Valid tdis4 th22 tw20 th21
Figure 13. Subsystem Zilog Nonmultiplexed Timing Waveforms
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TL16PC564A PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER
SLLS172B - MAY 1994 - REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
tc5 ARBCLKI td43 td42 ARBCLKO (1/1) td45 tc4 td44 ARBCLKO (1/2) td47 td46 ARBCLKO (1/4) td49 td48 ARBCLKO (1/8) tc4 tc4
Figure 14. Arbitration Clock Timing Waveforms
tc5 ARBCLKI 1 2 3 4 tw22 RESET td50 RST td51 5 6 7 8 1 2 3 4 5 tw23 6 7 8
Figure 15. Reset Timing Waveforms
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31
TL16PC564A PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER
SLLS172B - MAY 1994 - REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
WE
SCR Bit 6 td52 IRQ td53
Figure 16. IRQ Timing Waveforms
Subsystem Write (Intel WR) (Zilog DS)
OE td54 STSCHG td55
Figure 17. STSCHG Timing Waveforms
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IMPORTANT NOTICE Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current and complete. TI warrants performance of its semiconductor products and related software to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage ("Critical Applications"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. Inclusion of TI products in such applications is understood to be fully at the risk of the customer. Use of TI products in such applications requires the written approval of an appropriate TI officer. Questions concerning potential risk applications should be directed to TI through a local SC sales office. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards should be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. Nor does TI warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used.
Copyright (c) 1998, Texas Instruments Incorporated

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