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THS1030 2.7 V to 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS243B - NOVEMBER 1999 - REVISED AUGUST 2000
D D D D D D D D D
10-Bit Resolution 30 MSPS Analog-to-Digital Converter: Configurable Input: Single-Ended or Differential Differential Nonlinearity: 0.3 LSB Signal-to-Noise: 57 dB Spurious Free Dynamic Range: 60 dB Adjustable Internal Voltage Reference Out-of-Range Indicator Power-Down Mode Pin Compatible With TLC876
28-PIN TSSOP/SOIC PACKAGE (TOP VIEW)
description
The THS1030 is a CMOS, low power, 10-bit, 14 15 30 MSPS analog-to-digital converter (ADC) that can operate with a supply range from 2.7 V to 5.5 V. The THS1030 has been designed to give circuit developers flexibility. The analog input to the THS1030 can be either single-ended or differential. The THS1030 provides a wide selection of voltage references to match the user's design requirements. For more design flexibility, the internal reference can be bypassed to use an external reference to suit the dc accuracy and temperature drift requirements of the application. The out-of-range output is used to monitor any out-of-range condition in THS1030's input range. The speed, resolution, and single-supply operation of the THS1030 are suited for applications in STB, video, multimedia, imaging, high-speed acquisition, and communications. The speed and resolution ideally suit charge-couple device (CCD) input systems such as color scanners, digital copiers, digital cameras, and camcorders. A wide input voltage range between REFBS and REFTS allows the THS1030 to be applied in both imaging and communications systems. The THS1030C is characterized for operation from 0C to 70C, while the THS1030I is characterized for operation from - 40C to 85C
AVAILABLE OPTIONS TA 0C to 70C - 40C to 85C PACKAGED DEVICES 28-TSSOP (PW) THS1030CPW THS1030IPW 28-SOIC (DW) THS1030CDW THS1030IDW
AGND DVDD I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I/O9 OVR DGND
1 2 3 4 5 6 7 8 9 10 11 12 13
28 27 26 25 24 23 22 21 20 19 18 17 16
AVDD AIN VREF REFBS REFBF MODE REFTF REFTS 876M AGND REFSENSE STBY OE CLK
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 2000, Texas Instruments Incorporated
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THS1030 2.7 V to 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS243B - NOVEMBER 1999 - REVISED AUGUST 2000
functional block diagram
AIN REFTS REFBS
Sample and Hold
Core ADC Output Buffer
10 I/O(0-9)
OVR Internal Reference B Buffer A MODE REFTF REFBF Timing Circuit VBG OE
ORG
GND
REFSENSE
VREF
STBY
CLK
Terminal Functions
TERMINAL NAME AGND AIN AVDD CLK DGND DVDD I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I/O9 MODE OE OVR REFBS REFBF REFSENSE REFTF REFTS STBY VREF 876M NO. 1, 19 27 28 15 14 2 3 4 5 6 7 8 9 10 11 12 23 16 13 25 24 18 22 21 17 26 20 I/O I I I I I I Analog ground Analog input Analog supply Clock input Digital ground Digital driver supply Digital I/O bit 0 (LSB) Digital I/O bit 1 Digital I/O bit 2 Digital I/O bit 3 Digital I/O bit 4 Digital I/O bit 5 Digital I/O bit 6 Digital I/O bit 7 Digital I/O bit 8 Digital I/O bit 9 (MSB) Mode input HI to the 3-state data bus, LO to enable the data bus Out-of-range indicator Reference bottom sense Reference bottom decoupling Reference sense Reference top decoupling Reference top sense HI = power-down mode, LO = normal operation mode Internal and external reference HI = THS1030 mode, LO = TLC876 mode (see section 4 for TLC876 mode) DESCRIPTION
O
I I O I I I I I I I/O I
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THS1030 2.7 V to 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS243B - NOVEMBER 1999 - REVISED AUGUST 2000
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage: AVDD to AGND, DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 to 6.5 V AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 to 0.3 V AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 6.5 to 6.5 V Mode input MODE to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 to AVDD + 0.3 V Reference voltage input range REFTF, REFTB, REFTS, REFBS to AGND . . . . . . . . . - 0.3 to AVDD + 0.3 V Analog input voltage range AIN to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 to AVDD + 0.3 V Reference input VREF to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 to AVDD + 0.3 V Reference output VREF to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 to AVDD + 0.3 V Clock input CLK to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 to AVDD + 0.3 V Digital input to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 to DVDD + 0.3 V Digital output to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 to DVDD + 0.3 V Operating junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 150C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C Lead temperature 1,6 mm (1/16 in) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
digital inputs
MIN High-level High level input voltage VIH voltage, Low-level in ut voltage, VIL input voltage Clock input All other inputs Clock input All other inputs 0.8 x AVDD 0.8 x DVDD 0.2 x AVDD 0.2 x DVDD NOM MAX UNIT V
V
analog inputs
MIN Analog input voltage, VI(AIN) Reference input voltage VI(VREF) VI(REFTS) VI(REFBS) REFBS 1 1 0 NOM MAX REFTS 2 AVDD AVDD-1 UNIT V V V V
power supply
MIN Supply voltage Maximum sampling rate = 30 MSPS AVDD DVDD 3 3 NOM 3.3 3.3 MAX 5.5 5.5 UNIT V
REFTS, REFBS reference voltages (MODE = AVDD)
MIN Reference input voltage (top) Reference input voltage (bottom) Differential input (REFTS - REFBS) Switched sampling input capacitance on REFTS or REFBS REFTS REFBS 1 0 1 0.6 NOM MAX AVDD AVDD-1 2 UNIT V V V pF
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THS1030 2.7 V to 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS243B - NOVEMBER 1999 - REVISED AUGUST 2000
recommended operating conditions (continued)
sampling rate and resolution
PARAMETER Fs Resolution MIN 5 10 NOM MAX 30 UNIT MSPS Bits
electrical characteristics over recommended operating conditions, AVDD = 3 V, DVDD = 3 V, Fs = 30 MSPS/50% duty cycle, MODE = AVDD, 2 V input span from 0.5 V to 2.5 V, external reference, TA = Tmin to Tmax (unless otherwise noted)
analog inputs
PARAMETER VI(AIN) CI BW Ilkg Analog input voltage Switched sampling input capacitance Full power BW (-3 dB) DC leakage current (input = FS) MIN REFBS 1.2 150 60 TYP MAX REFTS UNIT V pF MHz A
VREF reference voltages
PARAMETER Internal 1 V reference (REFSENSE = VREF) Internal 2 V reference (REFSENSE = AVSS) External reference (REFSENSE = AVDD) Reference input resistance MIN 0.95 1.90 1 680 TYP 1 2 MAX 1.05 2.10 2 UNIT V V V
REFTF, REFBF reference voltages
PARAMETER Differential input (REFTF - REFBF) Input common mode (REFTF + REFBF)/2 VREF = 1 V REFTF (MODE = AVDD) VREF = 2 V VREF = 1 V REFBF (MODE = AVDD) VREF = 2 V Input resistance between REFTF and REFBF AVDD = 3 V AVDD = 5 V AVDD = 3 V AVDD = 5 V AVDD = 3 V AVDD = 5 V AVDD = 3 V AVDD = 5 V AVDD = 3 V AVDD = 5 V TEST CONDITIONS MIN 1 1.3 2 1.5 2.5 2 3 2.5 3.5 1 0.5 2 1.5 600 TYP MAX 2 1.7 3 UNIT V V V V V V
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THS1030 2.7 V to 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS243B - NOVEMBER 1999 - REVISED AUGUST 2000
electrical characteristics over recommended operating conditions, AVDD = 3 V, DVDD = 3 V, Fs = 30 MSPS/50% duty cycle, MODE = AVDD, 2 V input span from 0.5 V to 2.5 V, external reference, TA = Tmin to Tmax (unless otherwise noted) (continued)
dc accuracy
PARAMETER INL DNL Integral nonlinearity (see Note 1) Differential nonlinearity (see Note 2) Offset error (see Note 3) Gain error (see Note 4) Missing code MIN TYP 1 0.3 0.4 1.4 MAX 2 1 1.4 3.5 UNIT LSB LSB %FSR %FSR
No missing code assured
NOTES: 1. Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero to full scale. The point used as zero occurs 1/2 LSB before the first code transition. The full-scale point is defined as a level 1/2 LSB beyond the last code transition. The deviation is measured from the center of each particular code to the true straight line between these two endpoints. 2. An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Therefore this measure indicates how uniform the transfer function step sizes are. The ideal step size is defined here as the step size for the device under test (i.e., (last transition level - first transition level) / (2 n - 2)). Using this definition for DNL separates the effects of gain and offset error. A minimum DNL better than -1 LSB ensures no missing codes. 3. Offset error is defined as the difference in analog input voltage - between the ideal voltage and the actual voltage - that will switch the ADC output from code 0 to code 1. The ideal voltage level is determined by adding the voltage corresponding to 1/2 LSB to the bottom reference level. The voltage corresponding to 1 LSB is found from the difference of top and bottom references divided by the number of ADC output levels (1024). 4. Gain error is defined as the difference in analog input voltage - between the ideal voltage and the actual voltage - that will switch the ADC output from code 1022 to code 1023. The ideal voltage level is determined by subtracting the voltage corresponding to 1.5 LSB from the top reference level. The voltage corresponding to 1 LSB is found from the difference of top and bottom references divided by the number of ADC output levels (1024).
dynamic performance
PARAMETER TEST CONDITIONS f = 3.5 MHz ENOB Effective number of bits f = 3.5 MHz, AVDD = 5 V f = 15 MHz, 3 V f = 15 MHz, AVDD = 5 V f = 3.5 MHz SFDR Spurious free dynamic range f = 3.5 MHz, AVDD = 5 V f = 15 MHz f = 15 MHz, AVDD = 5 V f = 3.5 MHz THD Total harmonic distortion f = 3.5 MHz, AVDD = 5 V f = 15 MHz f = 15 MHz, AVDD = 5 V f = 3.5 MHz SNR Signal to noise Signal-to-noise f = 3.5 MHz, AVDD = 5 V f = 15 MHz f = 15 MHz, AVDD = 5 V f = 3.5 MHz SINAD Signal-to-noise Signal to noise and distortion f = 3.5 MHz, AVDD = 5 V f = 15 MHz f = 15 MHz, AVDD = 5 V 52.5 53 56 MIN 8.4 TYP 9 9 7.8 7.7 60.6 64.6 48.5 53 - 60 - 66.9 - 47.5 - 53.1 57 56 53.1 49.4 56 56 48.6 48.1 dB dB - 56 dB dB Bits MAX UNIT
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THS1030 2.7 V to 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS243B - NOVEMBER 1999 - REVISED AUGUST 2000
electrical characteristics over recommended operating conditions, AVDD = 3 V, DVDD = 3 V, Fs = 30 MSPS/50% duty cycle, MODE = AVDD, 2 V input span from 0.5 V to 2.5 V, external reference, TA = Tmin to Tmax (unless otherwise noted) (continued)
clock
PARAMETER tc tw(CKH) tw(CKL) td(o) td(AP) Clock period Pulse duration, clock high Pulse duration, clock low Clock to data valid Pipeline latency Aperture delay Aperture uncertainty (jitter) 3 4 2 MIN 33 15 15 16.5 16.5 25 TYP MAX UNIT ns ns ns ns Cycles ns ps
power supply
PARAMETER ICC PD PD(STBY) Operating supply current Power dissipation Standby power TEST CONDITIONS AVDD = DVDD = 3 V, MODE = AGND AVDD = DVDD = 3 V AVDD = DVDD = 5 V AVDD = DVDD = 3 V, MODE = AGND MIN TYP 29 87 150 3 5 MAX 40 120 UNIT mA mW mW
PARAMETER MEASUREMENT INFORMATION
Sample 2 Sample 1 Analog Input tc tw(CKL) Sample 3 Sample 4 Sample 5
tw(CKH)
Input Clock
See Note A td(o) Pipeline Latency
Digital Output
Sample 1
Sample 2
NOTE A: All timing measurements are based on 50% of edge transition.
Figure 1. Digital Output Timing Diagram
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THS1030 2.7 V to 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS243B - NOVEMBER 1999 - REVISED AUGUST 2000
TYPICAL CHARACTERISTICS
POWER vs SAMPLING FREQUENCY
90 88 Power - mW 86 84 82 80 78 76 5 10 15 20 25 30 fs - Sampling Frequency - MHz AVDD = DVDD = 3 V FI = 3.5 MHz TA = 25C
Figure 2
EFFECTIVE NUMBER OF BITS vs TEMPERATURE
10.0 Effective Number of Bits 9.5 9.0 8.5 8.0 7.5 7 -40 AVDD = DVDD = 3 V FI = 3.5 MHz Fs = 30 MSPS
-15
10
35
60
85
TA - Temperature - C
Figure 3
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THS1030 2.7 V to 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS243B - NOVEMBER 1999 - REVISED AUGUST 2000
TYPICAL CHARACTERISTICS
EFFECTIVE NUMBER OF BITS vs SAMPLING FREQUENCY
10.0 Effective Number of Bits 9.5 9.0 8.5 8.0 7.5 7 5 10 15 20 25 30 fs - Sampling Frequency - MSPS AVDD = DVDD = 3 V FI = 3.5 MHz TA = 25C
Figure 4
EFFECTIVE NUMBER OF BITS vs SAMPLING FREQUENCY
10.0 Effective Number of Bits 9.5 9.0 8.5 8.0 7.5 7 5 AVDD = 5 V DVDD = 3 V FI = 3.5 MHz TA = 25C 10 15 20 25 30
fs - Sampling Frequency - MSPS
Figure 5
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THS1030 2.7 V to 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS243B - NOVEMBER 1999 - REVISED AUGUST 2000
TYPICAL CHARACTERISTICS
EFFECTIVE NUMBER OF BITS vs SAMPLING FREQUENCY
10.0 Effective Number of Bits 9.5 9.0 8.5 8.0 7.5 7 5 10 15 20 25 30 fs - Sampling Frequency - MSPS AVDD = DVDD = 5 V FI = 3.5 MHz TA = 25C
Figure 6
DIFFERENTIAL NONLINEARITY vs INPUT CODE
DNL - Differential Nonlinearity - LSB 1.00 0.80 0.60 0.40 0.20 -0.00 -0.20 -0.40 -0.60 -0.80 -1.00 0 128 256 384 512 Input Code 640 AVDD = 3 V DVDD = 3 V Fs = 30 MSPS
768
896
1024
Figure 7
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THS1030 2.7 V to 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS243B - NOVEMBER 1999 - REVISED AUGUST 2000
TYPICAL CHARACTERISTICS
INTEGRAL NONLINEARITY vs INPUT CODE
INL - Integral Nonlinearity - LSB 2.0 1.5 1.0 0.5 0.0 -0.5 -1.0 -1.5 -2 0 128 256 384 512 Input Code 640 768 896 1024 AVDD = 3 V DVDD = 3 V Fs = 30 MSPS
Figure 8
FFT vs FREQUENCY
0 -20 -40 FFT - dB -60 -80 -100 -120 -140 0 2 4 6 8 10 12 14 f - Frequency - MHz AVDD = 3 V DVDD = 3 V FI = 3.5 MHz, -1dBFS
Figure 9
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THS1030 2.7 V to 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS243B - NOVEMBER 1999 - REVISED AUGUST 2000
PRINCIPLES OF OPERATION
The analog input AIN is sampled in the sample and hold unit, the output of which feeds the ADC core, where the process of analog to digital conversion is performed against ADC reference voltages, REFTF and REFBF. Connecting the MODE pin to one of three voltages, AGND, AVDD or AVDD/2 sets up operating configurations. The three settings open or close internal switches to select one of the three basic methods of ADC reference generation. Depending on the user's choice of operating configuration, the ADC reference voltages may come from the internal reference buffer or may be fed from completely external sources. Where the reference buffer is employed, the user can choose to drive it from the onboard reference generator (ORG), or may use an external voltage source. A specific configuration is selected by connections to the REFSENSE, VREF, REFTS and REFBS, and REFTF and REFBF pins, along with any external voltage sources selected by the user. The ADC core drives out through output buffers to the data pins D0 to D9. The output buffers can be disabled by the OE pin. A single, sample-rate clock (30 MHz maximum) is required at pin CLK. The analog input signal is sampled on the rising edge of CLK, and corresponding data is output after the third following rising edge. The STBY pin controls the THS1030 powerdown. The user-chosen operating configuration and reference voltages determine what input signal voltage range the THS1030 can handle. The following sections explain:
D D D
The internal signal flow of the device, and how the input signal span is related to the ADC reference voltages The ways in which the ADC reference voltages can be buffered internally, or externally applied How to set the onboard reference generator output, if required, and several examples of complete configurations.
signal processing chain (sample and hold, ADC)
REFTF VP+ AIN REFTS REFBS 1 -1/2 -1/2 Sample and Hold VP- REFBF ADC Core
Figure 10. Analog Input Signal Flow Figure 10 shows the signal flow through the sample and hold unit to the ADC core.
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THS1030 2.7 V to 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER
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PRINCIPLES OF OPERATION sample and hold
The analog input signal AIN is applied to the AIN pin, either dc-coupled or ac coupled. The differential sample and hold processes AIN with respect to the voltages applied to the REFTS and REFBS pins, to give a differential output VP+ - VP - = VP given by: VP Where: VM
+ AIN * VM
+ (REFTS ) REFBS) 2
(1)
For single-ended input signals, VM is a constant voltage; usually the AIN mid-scale input voltage. However if MODE = AVDD/2 then REFTS and REFBS can be connected together to operate with AIN as a complementary pair of differential inputs (see Figures 15 and 16).
analog-to-digital converter
In all operating configurations, VP is digitized against ADC Reference Voltages REFTF and REFBF, full scale values of VP being given by:
)+ ) (REFTF2* REFBF) * (REFTF * REFBF) VPFS *+
VPFS 2
(2)
VP voltages outside the range VPFS- to VPFS+ lie outside the conversion range of the ADC. Attempts to convert out-of-range inputs are signaled to the application by driving the OVR output pin high. VP voltages less than VPFS- give ADC output code 0. VP voltages greater than VPFS+ give output code 1023.
complete system
Combining the above equations, the analog full scale input voltages at AIN which give VPFS+ and VPFS- at the sample and hold output are: A and A IN IN
+ FS )+ VM ) (REFTF * REFBF) 2 + FS *+ VM * (REFTF * REFBF) 2
(3)
(4)
The analog input span (voltage range) that lies within the ADC conversion range is: Input span
+ [(FS )) * (FS *)] + (REFTF * REFBF)
(5)
The REFTF and REFBF voltage difference sets the device input range. The next sections describe in detail the various methods available for setting voltages REFTF and REFBF to obtain the desired input span and ADC performance.
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THS1030 2.7 V to 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER
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PRINCIPLES OF OPERATION ADC reference generation
The THS1030 has three primary modes of ADC reference generation, selected by the voltage level applied to the MODE pin. Connecting the MODE pin to AGND gives full external reference mode. In this mode, the user supplies the ADC reference voltages directly to pins REFTF and REFBF. This mode is used where there is need for minimum power drain or where there are very tight tolerances on the ADC reference voltages. This mode also offers the possibility of Kelvin connection of the reference inputs to the THS1030 to eliminate any voltage drops from remote references that may occur in the system. Only single-ended input is possible in this mode. Connecting the MODE pin to AVDD/2 gives differential mode. In this mode, the ADC reference voltages REFTF and REFBF are generated by the Internal reference buffer from the voltage applied to the VREF pin. This mode is suitable for handling differentially presented inputs, which are applied to the AIN and REFTS/REFBS pins. A special case of differential mode is center span mode, in which the user applies a single-ended signal to AIN and applies the mid-scale input voltage (VM) to the REFTS and REFBS pins. Connecting the MODE pin to AVDD gives top/bottom mode. In this mode, the ADC reference voltages REFTF and REFBF are generated by the internal reference buffer from the voltages applied to the REFTS and REFBS pins. Only single-ended input is possible in top/bottom mode. When MODE is connected to AGND, the internal reference buffer is powered down, its inputs and outputs disconnected, and REFTS and REFBS internally connected to REFTF and REFBF respectively. These nodes are connected by the user to external sources to provide the ADC reference voltages. The mean of REFTF and REFBF must be equal to AVDD/2. See Figure 12.
REFTF
AIN+ REFTS REFBS
1 -1/2 -1/2
Sample and Hold
ADC Core
Internal Reference Buffer
REFBF
Figure 11. ADC Reference Generation, Full External Reference Mode, (MODE = AGND) It is also possible to use REFTS and REFBS as sense lines to drive the REFTF and REFBF lines (Kelvin mode) to overcome any voltage drops within the system. See Figure 13.
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THS1030 2.7 V to 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER
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PRINCIPLES OF OPERATION
AVDD +FS AVDD 2 -FS DC SOURCE = + FS
AIN
REFSENSE
REFTS
DC SOURCE = -FS 0.1 F
REFBS
REFTF 10 F 0.1 F REFBF MODE
0.1 F
Figure 12. Full External Reference Mode
AVDD +FS AVDD 2 -FS
AIN
REFSENSE
REFTS REFBS _ REFTF REFT = +FS + 0.1 F 10 F _ REFB = -FS + 0.1 F REFBF MODE 0.1 F
Figure 13. Full External Reference With Kelvin Connections
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PRINCIPLES OF OPERATION differential input mode (MODE = AVDD/2)
REFTF = AVDD + VREF 2
AIN+ AIN- REFTS REFBS
1 -1/2 -1/2
Sample and Hold
ADC Core
VREF AGND
Internal Reference Buffer
REFBF =
AVDD - VREF 2
Figure 14. ADC Reference Generation, MODE = AVDD/2 When MODE = AVDD/2, the internal reference buffer is enabled, its outputs internally switched to REFTF and REFBF and inputs internally switched to VREF and AGND as shown in Figure 14. The REFTF and REFBF voltages are centered on AVDD/2 by the internal reference buffer and the voltage difference between REFTF and REFBF equals the voltage at VREF. The internal REFTS to REFBS and REFTF to REFBF switches are open in this mode, allowing REFTS and REFBS to form the AIN- to the sample and hold. Depending on the connection of the REFSENSE pin, the voltage on VREF may be externally driven, or set to an internally generated voltage of 1 V, 2 V or an intermediate voltage (see the section on onboard reference generator configuration).
+FS AIN+ -FS +FS AIN- -FS REFBS REFSENSE 0.1 F AIN MODE AVDD 2
REFTS
REFTF 10 F 0.1 F REFBF
VREF
0.1 F
Figure 15. Differential Input Mode, 1 V Reference Span
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THS1030 2.7 V to 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER
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PRINCIPLES OF OPERATION
+FS VM -FS AIN MODE AVDD 2
DC SOURCE = VM VM 0.1 F
+ _
REFTS
REFBS
REFTF 10 F 0.1 F REFBF REFSENSE
0.1 F
Figure 16. Center Span Mode, 2 V Reference Span
top/bottom mode (MODE = AVDD)
REFTF = AVDD + (REFTS - REFBS) 2
AIN+ REFTS REFBS
1 -1/2 -1/2
Sample and Hold
ADC Core
Internal Reference Buffer
REFBF = AVDD - (REFTS + REFBS) 2
Figure 17. ADC Reference Generation Mode = AVDD Connecting MODE to AVDD enables the internal reference buffer. Its inputs are internally switched to the REFTS and REFBS pins and its outputs internally switched to pins REFTF and REFBF. The internal connections (REFTS to REFTF) and (REFBS to REFBF) are broken.
16
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THS1030 2.7 V to 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS243B - NOVEMBER 1999 - REVISED AUGUST 2000
PRINCIPLES OF OPERATION top/bottom mode (MODE = AVDD) (continued)
The REFTS and REFBS voltages set the analog input span limits FS+ and FS- respectively. Any voltages at AIN greater than REFTS or less than REFBS will cause ADC over-range, which is signaled by OVR going high when the conversion result is output. Typically, REFSENSE is tied to AVDD to disable the ORG output to VREF (as in Figure 18), but the user can choose to use the ORG output to VREF as either REFTS or REFBS.
AVDD +FS -FS DC SOURCE = FS+ AIN MODE
REFTS REFSENSE
DC SOURCE = FS- 0.1 F
REFBS
REFTF 10 F 0.1 F REFBF
0.1 F
Figure 18. Top/Bottom Reference Mode
onboard reference generator configuration
The onboard reference generator (ORG) can provide a supply-voltage-independent and temperatureindependent voltage on pin VREF. External connections to REFSENSE control the ORG's output to the VREF pin as shown in Table 1. Table 1. Effect of REFSENSE Connection on VREF Value
REFSENSE CONNECTION VREF pin AGND External divider junction AVDD ORG OUTPUT TO VREF 1V 2V (1 + RA/RB) Open circuit REFER TO: Figure 19 Figure 20 Figure 21 Figure 22
REFSENSE = AVDD powers the ORG down, saving power when the ORG function is not required. If MODE = AVDD/2, the voltage on VREF determines the ADC reference voltages: REFTF
+ AV2DD ) VREF 2
(6)
+ AV2DD * VREF 2 REFTF * REFBF + VREF
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THS1030 2.7 V to 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS243B - NOVEMBER 1999 - REVISED AUGUST 2000
PRINCIPLES OF OPERATION
Internal Reference Buffer Mode = AVDD 2 VREF = 1 V 0.1 F REFSENSE 1 F Tantalum
VBG
+ _
+ _
AGND
Figure 19. 1-V VREF Using ORG
Internal Reference Buffer Mode = AVDD 2 VREF = 2 V 10 k REFSENSE 10 k 0.1 F 1 F Tantalum
VBG
+ _
+ _
AGND
Figure 20. 2-V VREF Using ORG
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THS1030 2.7 V to 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER
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PRINCIPLES OF OPERATION onboard reference generator configuration (continued)
Internal Reference Buffer Mode = AVDD 2 VREF = 1 + (Ra/Rb) Ra REFSENSE Rb 0.1 F 1 F Tantalum
VBG
+ _
+ _
AGND
Figure 21. External Divider Mode
Internal Reference Buffer Mode = AVDD 2
VBG
+ _
+ _
VREF = External
REFSENSE AVDD AGND
Figure 22. Drive VREF Mode
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THS1030 2.7 V to 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS243B - NOVEMBER 1999 - REVISED AUGUST 2000
PRINCIPLES OF OPERATION operating configuration examples
This section provides examples of operating configurations. Figure 23 shows the operating configuration in top/bottom mode for a 2 V span single-ended input, using VREF to drive REFTS. Connecting the mode pin to AVDD puts the THS1030 in top/bottom mode. Connecting pin REFSENSE to AGND sets the output of the ORG to 2 V. REFTS and REFBS are user-connected to VREF and AGND respectively to match the AIN pin input range to the voltage range of the input signal.
AVDD 2V 1V 0V AIN MODE
VREF = 2 V
REFTS 0.1 F
REFTF REFSENSE 10 F 0.1 F REFBF REFBS
0.1 F
Figure 23. Operation Configuration in Top/Bottom Mode In Figure 24 the input signal is differential, so mode = AVDD/2 (differential mode) is set to allow the inverse signal to be applied to REFTS and REFBS. The differential input goes from -0.8 V to 0.8 V, giving a total input signal span of 1.6 V, REFTF- REFBF should therefore equal 1.6V. REFSENSE is connected to resistors RA and RB (external divider mode) to make VREF = 1.6 V, that is RA/RB = 0.6 (see Figure 21).
1.4 V 1V AIN+ 0.6 V 1.4 V 1V 0.6 V AVDD 2 AIN MODE
REFTS VREF = 1.6 V REFBS RA REFSENSE REFTF 10 F 0.1 F REFBF RB
AIN-
0.1 F
0.1 F
Figure 24. Differential Operation
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THS1030 2.7 V to 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS243B - NOVEMBER 1999 - REVISED AUGUST 2000
PRINCIPLES OF OPERATION operating configuration examples (continued)
Figure 25 shows a center span configuration for an input waveform swinging between 0.2 V and 1.9 V. Pins REFTS and REFBS are connected to a voltage source of 1.05 V, equal to the mid-scale of the input waveform. REFTF-REFBF should be set equal to the span of the input waveform, 1.7 V, so VREF is connected to an external source of 1.7 V. REFSENSE must be connected to AVDD to disable the ORG output to VREF (see Figure 22) to allow this external source to be applied.
1.9 V 1.05 V 0.2 V AIN MODE REFSENSE AVDD 2 AVDD
REFTS DC SOURCE = 1.05 V REFBS 0.1 F
REFTF 10 F 0.1 F REFBF
VREF
DC SOURCE = 1.7 V
0.1 F
Figure 25. Center Span Operation
power management
In power-sensitive applications (such as battery-powered systems) where the THS1030 ADC is not required to convert continuously, power can be saved between conversion intervals by placing the THS1030 into power down mode. This is achieved by setting pin 17 (STBY) to 1. In power-down mode, the device typically consumes less than 1 mW of power (from AVDD and DVDD) in either top/bottom mode or center-span mode. On power up, the THS1030 typically requires 5 ms of wake up time before valid conversion results are available in either top/bottom or center span modes. Disabling the ORG in applications where the ORG output is not required can also reduce power dissipation by 1 mA analog IDD. This is achieved by connecting the REFSENSE pin to AVDD.
output format and digital I/O
While the OE pin is held low, ADC conversion results are output at pins D0 (LSB) to D9 (MSB). The ADC input over-range indicator is output at pin OVR. OVR is also disabled when OE is held high. The ADC output data format is unsigned binary (output codes 0 to 1023).
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THS1030 2.7 V to 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS243B - NOVEMBER 1999 - REVISED AUGUST 2000
PRINCIPLES OF OPERATION driving the THS1030 analog inputs
driving AIN Figure 26 shows an equivalent circuit for the THS1030 AIN pin. The load presented to the system at the AIN pin comprises the switched input sampling capacitor, CSAMPLE, and various stray capacitances, CP1 and CP2.
AVDD CLK 1.2 pF AIN C1 8 pF AGND + _ CLK VLAST C(Sample) C2 1.2 pF
Figure 26. Equivalent Circuit of Analog Input AIN In any single-ended input mode, VLAST = the average of the previously sampled voltage at AIN and the average of the voltages on pins REFTS and REFBS. In any differential mode, VLAST = the common mode input voltage. The external source driving AIN must be able to charge and settle into CSAMPLE and the CP1 and CP2 strays to within 0.5 LSB error while sampling (CLK pin low) to achieve full ADC resolution.
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THS1030 2.7 V to 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER
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PRINCIPLES OF OPERATION driving the THS1030 analog inputs (continued)
AIN input current and input load modeling When CLK goes low, the source driving AIN must charge the total switched capacitance CS = CSAMPLE + CP2. The total charge transferred depends on the voltage at AIN and is given by: Q CHARGING
+ (AIN * VLAST)
C. S
(7)
For a fixed voltage at AIN, so that AIN and VLAST do not change between samples, the maximum amount of charge transfer occurs at AIN = FS- (charging current flows out of THS1030) and AIN = FS+ (current flows into THS1030). If AIN is held at the voltage FS+, VLAST = [(FS+) + VM]/2, giving a maximum transferred charge: Q(FS)
+ (FS )) * [(FS )) ) VM] CS + [(FS )) *2VM] 2 + (1 4 of the input voltage span) CS +3
Q(FS)
C
S (8)
If the input voltage changes between samples, then the maximum possible charge transfer is Q(max) (9)
which occurs for a full-scale input change (FS+ to FS- or FS- to FS+) between samples. The charging current pulses can make the AIN source jump or ring, especially if the source is slightly inductive at high frequencies. Inserting a small series resistor of 20 or less in the input path can damp source ringing (see Figure 30). This resistor can be made larger than 20 if reduced input bandwidth or distortion performance is acceptable.
R < 20 AIN VS
Figure 27. Damping Source Ringing Using a Small Resistor equivalent input resistance at AIN and ac coupling to AIN Some applications may require ac coupling of the input signal to the AIN pin. Such applications can use an ac-coupling network such as shown in Figure 28.
AVDD
R(Bias1) Cin AIN R(Bias2)
Figure 28. AC-Coupling the Input Signal to the AIN Pin
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THS1030 2.7 V to 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER
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PRINCIPLES OF OPERATION
equivalent input resistance at AIN and ac coupling to AIN (continued) Note that if the bias voltage is derived from the supplies, as shown in Figure 28, then additional filtering should be used to ensure that noise from the supplies does not reach AIN. Working with the input current pulse equations given in the previous section is awkward when designing ac-coupling input networks. For such design, it is much simpler to model the AIN input as an equivalent resistance, RAIN, from the AIN pin to a voltage source VM where VM = (REFTS + REFBS)/2 and RAIN = 1 / (Cs x Fclk) where Fclk is the CLK frequency. The high-pass -3 dB cut-off frequency for the circuit shown in Figure 28 is: f (*3 dB)
+
1 2
p
R
tot IN
(10)
where RINtot is the parallel combination of Rbias1, Rbias2 and RAIN. This approximation is good provided that the clock frequency, Fclk, is much higher than f(-3 dB). Note also that the effect of the equivalent RAIN and VM at the AIN pin must be allowed for when designing the bias network dc level. details The above value for RAIN is derived by noting that the average AIN voltage must equal the bias voltage supplied by the ac coupling network. The average value of VLAST in equation 8 is thus a constant voltage VLAST = V(AIN bias) - VM For an input voltage Vin at the AIN pin, Qin = (Vin - VLAST) x Cs Provided that f (-3 dB) is much lower than Fclk, a constant current flowing over the clock period can approximate the input charging pulse Iin = Qin / Tclk = Qin x Fclk = (Vin - VLAST) x Cs x Fclk
The ac input resistance RAIN is then RAIN = dIin / dVin = 1 / (dVin / dIin) = 1 / (Cs x Fclk)
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THS1030 2.7 V to 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS243B - NOVEMBER 1999 - REVISED AUGUST 2000
PRINCIPLES OF OPERATION
driving the VREF pin (differential mode) Figure 29 shows the equivalent load on the VREF pin when driving the internal reference buffer via this pin (MODE = AVDD/2 and REFSENSE = AVDD ).
AVDD
RIN VREF 14 k REFSENSE = AVDD, Mode = AVDD 2
AGND + _ AVDD + VREF 4
Figure 29. Equivalent Circuit of VREF The current flowing into IIN is given by I
+ IN
3
VREF 4
* AVDD
IN
R
(11)
Note that the actual IIN may differ from this value by up to 50% due to device-to-device processing variations and allowing for operating temperature variations. The user should ensure that VREF is driven from a low noise, low drift source, well-decoupled to analog ground and capable of driving IIN. driving the internal reference buffer (top/bottom mode) Figure 30 shows the load present on the REFTS and REFBS pins in TOP/BOTTOM mode due to the internal reference buffer only. The sample and hold must also be driven via these pins, which adds additional load.
AVDD
REFTS REFBS
RIN 14 k Mode = AVDD AGND
AVDD + REFTS + REFBS 4
+ _
Figure 30. Equivalent Circuit of Inputs to Internal Reference Buffer
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PRINCIPLES OF OPERATION
driving the internal reference buffer (top/bottom mode) (continued) Equations for the currents flowing into REFTS and REFBS are: I TS IN
+ +
3
REFTS
* AVDD * REFBS
R
4 3 REFBS
I
BS IN
* AVDD * REFTS
R IN
IN
(12)
4
(13)
These currents must be provided by the sources on REFTS and REFBS in addition to the requirements of driving the sample and hold. Tolerance on these currents are 50%. driving REFTS and REFBS
AVDD CLK 0.6 pF REFTS REFBS C1 7 pF AGND Mode = AVDD + _ Internal Reference Buffer CLK VLAST CSAMPLE C2 0.6 pF
Figure 31. Equivalent Circuit of REFTS and REFBS Inputs This is essentially a combination of driving the ADC internal reference buffer (if in top/bottom mode) and also driving a switched capacitor load like AIN, but with the sampling capacitor and CP2 on each pin now being 0.6 pF and about 0.6 pF respectively. driving REFTF and REFBF (full external reference mode)
AVDD
REFTF
To REFBS (For Kelvin Connection) AGND AVDD
680 R
REFBF
To REFTS (For Kelvin Connection) AGND
Figure 32. Equivalent Circuit of REFTF and REFBF Inputs Note the need for off-chip decoupling.
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SLAS243B - NOVEMBER 1999 - REVISED AUGUST 2000
PRINCIPLES OF OPERATION driving the clock input
Obtaining good performance from the THS1030 requires care when driving the clock input. Different sections of the sample-and-hold and ADC operate while the clock is low or high. The user should ensure that the clock duty cycle remains near 50% to ensure that all internal circuits have as much time as possible in which to operate. The CLK pin should be driven from a low jitter source for best dynamic performance. To maintain low jitter at the CLK input, any clock buffers external to the THS1030 should have fast rising edges. Use a fast logic family such as AC or ACT to drive the CLK pin, and consider powering any clock buffers separately from any other logic on the PCB to prevent digital supply noise appearing on the buffered clock edges as jitter. The CLK input threshold is nominally around AVDD/2 - ensure that any clock buffers have an appropriate supply voltage to drive above and below this level.
digital output loading and circuit board layout
The THS1030 outputs are capable of driving rail-to-rail with up to 20 pF of load per pin at 30 MHz clock and 3 V digital supply. Minimizing the load on the outputs will improve THS1030 signal-to-noise performance by reducing the switching noise coupling from the THS1030 output buffers to the internal analog circuits. The output load capacitance can be minimized by buffering the THS1030 digital outputs with a low input capacitance buffer placed as close to the output pins as physically possible, and by using the shortest possible tracks between the THS1030 and this buffer. Noise levels at the output buffers, and hence coupling to the analog circuits within THS1030, becomes worse as the THS1030 digital supply voltage is increased. Where possible, consider using the lowest DVDD that the application can tolerate. Use good layout practices when designing the application PCB to ensure that any off-chip return currents from the THS1030 digital outputs (and any other digital circuits on the PCB) do not return via the supplies to any sensitive analog circuits. The THS1030 should be soldered directly to the PCB for best performance. Socketing the device will degrade performance by adding parasitic socket inductance and capacitance to all pins.
user tips for obtaining best performance from the THS1030
D D D D D D D D
Voltages on AIN, REFTF and REFBF and REFTS and REFBS must all be inside the supply rails. ORG modes offer the simplest configurations for ADC reference generation. Choose differential input mode for best distortion performance. Choose a 2-V ADC input span for best noise performance. Choose a 1-V ADC input span for best distortion performance. If the ORG is not used to provide ADC reference voltages, its output may be used for other purposes in the system. Care should be taken to ensure noise is not injected into the THS1030. Use external voltage sources for ADC reference generation where there are stringent requirements on accuracy and drift. Drive clock input CLK from a low-jitter, fast logic stage, with a well-decoupled power supply and short PCB traces.
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THS1030 2.7 V to 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS243B - NOVEMBER 1999 - REVISED AUGUST 2000
PRINCIPLES OF OPERATION TLC876 mode
The THS1030 is pin compatible with the TI TLC876 and thus enables users of TLC876 to upgrade to higher speed by dropping the THS1030 into their sockets. Grounding the 1876M pin effectively puts the THS1030 into 876 mode using the external ADC reference. The MODE pin should either be grounded or left floating. The REFSENSE pin is connected to DVDD when the THS1030 is dropped into a TLC876 socket. For DVDD = 5 V applications, this will disable the ORG. For TLC876 applications using DVDD = 3.3 V, the VREF pin will be driven to AVSS. In TLC876/AD876 mode, the pipeline latency is increased to 3.5 clock cycles to match the TLC876 latency.
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SLAS243B - NOVEMBER 1999 - REVISED AUGUST 2000
MECHANICAL DATA
PW (R-PDSO-G**)
14 PINS SHOWN
PLASTIC SMALL-OUTLINE
0,65 14 8
0,30 0,19
0,10 M
0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 A 7 0- 8 0,75 0,50
Seating Plane 1,20 MAX 0,15 0,05 0,10
PINS ** DIM A MAX
8
14
16
20
24
28
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153
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THS1030 2.7 V to 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER
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MECHANICAL DATA
DW (R-PDSO-G**)
16 PINS SHOWN 0.050 (1,27) 16 0.020 (0,51) 0.014 (0,35) 9
PLASTIC SMALL-OUTLINE
0.010 (0,25) M
0.419 (10,65) 0.400 (10,15) 0.299 (7,59) 0.293 (7,45) 0.010 (0,25) NOM
Gage Plane 0.010 (0,25) 1 A 8 0- 8 0.050 (1,27) 0.016 (0,40)
Seating Plane 0.104 (2,65) MAX 0.012 (0,30) 0.004 (0,10) PINS ** DIM A MAX 0.004 (0,10)
16 0.410 (10,41) 0.400 (10,16)
20 0.510 (12,95) 0.500 (12,70)
24 0.610 (15,49) 0.600 (15,24)
28 0.710 (18,03) 0.700 (17,78) 4040000 / C 07/96
A MIN
NOTES: A. B. C. D.
All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). Falls within JEDEC MS-013
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