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TLV987 3-V 10-BIT 27 MSPS AREA CCD SENSOR SIGNAL PROCESSOR
SLAS211A - MARCH 1999 - REVISED SEPTEMBER 1999
D D D D D D D D D D D
48 47 46 45 44 43 42 41 40 39 38 37 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 36 35 34 33 32 31 30 29 28 27 26 25
CLREF CLAMP SV SR AGND1 AVDD1 VSS AVDD5 RPD RMD RBD AGND5
D D D
10-Bit, 27 MSPS, A/D Converter Single 3-V Supply Operation Low Power: 200 mW Typical at 3 V, 2 mW Power-Down Mode Differential Nonlinearity Error: <0.6 LSB Typ Integral Nonlinearity Error: <2 LSB Typ DIN Programmable Gain Amplifier (PGA) With PIN 0-dB to 36-dB Gain Range (0.09 dB/step) AVDD2 Automatic or Programmable Black Level AGND2 and Offset Calibration DGND Additional DACs for External Analog DVDD Setting D0 Serial Interface for Register Configuration D1 D2 Internal Reference Voltages D3 48-Pin TQFP Package
D4 D5
PFB PACKAGE (TOP VIEW)
applications
Digital Still Camera Digital Camcorder Digital Video Camera
BLKG TPP TPM AVDD4 AGND4 OBCLP STBY RESET CS SDIN SCLK ADCCLK
D6 D7 D8 D9
AVAILABLE OPTIONS TA 0C to 70C PACKAGE TQFP (PFB) TLV987CPFB
description
The TLV987 is a highly integrated monolithic analog signal processor/digitizer designed to interface the area charge-coupled device (CCD) sensors in digital camera applications. The TLV987 performs all the analog processing functions necessary to maximize the dynamic range, corrects various errors associated with the CCD sensor, and then converts the results from analog to digital using the on-chip high-speed analog-to-digital converter (ADC). The key components of the TLV987 include input clamp circuitry, a correlated double sampler (CDS), and a programmable gain amplifier (PGA). The PGA has 0-dB to 36-dB gain range. In addition, the TLV987 has two internal digital-to-analog converters (DACs) for automatic or programmable optical black level and offset calibration. The TLV987 also has two additional DACs for external system control, and internal reference voltages. The TLV987 has a parallel data port for easy microprocessor interface and a serial port for configuring internal control registers. Designed in advanced CMOS process, the TLV987 operates from a single 3-V power supply with a normal power consumption of 200 mW and a 2 mW power-down mode. Very high throughput rate, single 3-V operation, low power consumption, and fully integrated analog processing circuitry make the TLV987 an ideal CCD sensor interfacing solution for digital camera applications. The device is available in a 48-pin TQFP package and is characterized for operation over 0C to 70C operating free-air temperature range.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. TI is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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DIVDD DIGND AVDD3 AGND3 DACO1 DACO2 DACT OE
Copyright (c) 1999, Texas Instruments Incorporated
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TLV987 3-V 10-BIT 27 MSPS AREA CCD SENSOR SIGNAL PROCESSOR
SLAS211A - MARCH 1999 - REVISED SEPTEMBER 1999
functional block diagram
CLAMP (47) CLREF (48) TPP TPM (35) (34) RPD RBD RMD (40) (38) (39) Internal Reference
Clamp (1) (2) (23)
1.3 V
(24)
OE
DIN PIN DACT
CDS
PGA 9
10-Bit ADC
Three State Latch
(7-16)
D0-D9
8-Bit DAC DACO1 (21) 8-Bit DAC DAC Register Offset Register
PGA Register
8-Bit DAC
Digital Averager Control Logic
(29) (25) (46) (45) (36)
RESET ADCCLK SV SR
Offset Register
OB CAL Register
BLKG (31) OBCLP (30) STBY (28) CS (26) SCLK (27) SDIN
DACO2
(22)
8-Bit DAC
DAC Register Coarse Offset Control Overflow Digital Comparator Fine Offset Control
Serial Port
Vb Register
2
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TLV987 3-V 10-BIT 27 MSPS AREA CCD SENSOR SIGNAL PROCESSOR
SLAS211A - MARCH 1999 - REVISED SEPTEMBER 1999
Terminal Functions
TERMINAL NAME ADCCLK AGND1 AGND2 AGND3 AGND4 AGND5 AVDD1 AVDD2 AVDD3 AVDD4 AVDD5 BLKG CLAMP CLREF CS DACO1 DACO2 DACT DGND DIGND DIN DIVDD DVDD D0 - D9 OBCLP OE PIN RBD RMD RPD RESET SCLK SDIN SR STBY SV TPM TPP VSS NO. 25 44 4 20 32 37 43 3 19 33 41 36 47 48 28 21 22 23 5 18 1 17 6 7 - 16 31 24 2 38 39 40 29 26 27 45 30 46 34 35 42 O I I I O O O I I I I I I O O I I I O I O O O I/O I ADC clock input. Analog ground for internal CDS circuits Analog ground for internal PGA circuits Analog ground for internal DAC circuits Analog ground for internal ADC circuits Analog ground for internal REF circuits Analog supply voltage for internal CDS circuits, 3 V Analog supply voltage for internal PGA circuits, 3 V Analog supply voltage for internal DAC circuits, 3 V Analog supply voltage for internal ADC circuits, 3 V Analog supply voltage for internal ADC circuits, 3 V Control input. CDS operation is disabled when BLKG is pulled low. CCD signal clamp control input Clamp reference voltage output. Chip select. A logic low on this input enables the TLV987. Digital-to-analog converter output1 Digital-to-analog converter output2 MUXed test output for internal offset DACs Digital ground Digital interface circuit ground Input signal from CCD Digital interface circuit supply voltage, 1.8 V to 4.4 V Digital supply voltage, 3 V 10-bit three-state ADC output data or offset DACs test data Optical black level and offset calibration control input. Active low. Output data enable. Active low. Input signal from CCD Internal bandgap reference for external decoupling Ref- output for external decoupling Ref+ output for external decoupling Hardware reset input, active low. This signal forces a reset of all internal registers. Serial clock input. This clock synchronizes the serial data transfer. Serial data input to configure the internal registers. CCD reference level sample clock input Hardware power-down control input, active low CCD signal level sample clock input MUXed test output: PGA noninverting output or inverted PGA clock MUXed test output: PGA inverting output or inverted CDS clock Silicon substrate, normally connected to analog ground DESCRIPTION
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TLV987 3-V 10-BIT 27 MSPS AREA CCD SENSOR SIGNAL PROCESSOR
SLAS211A - MARCH 1999 - REVISED SEPTEMBER 1999
absolute maximum ratings over operating free-air temperature (unless otherwise noted) Supply voltage range, AVDD, DVDD, DIVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 6.5V Analog input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to AVDD+0.3 V Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to DVDD+0.3 V Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40C to 150C Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
power supplies
MIN Analog supply voltage, AVDD Digital supply voltage, DVDD Digital interface supply voltage, DIVDD 2.7 2.7 1.8 NOM 3 3 MAX 3.3 3.3 4.4 UNIT V V V
digital inputs
MIN High-level input voltage, VIH Low-level input voltage, VIL Clock frequency, ADCCLK, fclock1 Pulse duration, ADCCLK, high, tw(CLKH)1 Pulse duration, ADCCLK, low, tw(CLKL)1 Clock frequency, SCLK, fclock2 Pulse duration, SCLK high, tw(CLKH)2 Pulse duration, SCLK low, tw(CLKL)2 DIVDD = 3 V DIVDD = 3 V DVDD = 3 V DVDD = 3 V DVDD = 3 V DVDD = 3 V DVDD = 3 V DVDD = 3 V 12.5 12.5 18.5 18.5 40 0.8DIVDD 0.2DIVDD 27 NOM MAX UNIT V V MHz ns ns MHz ns ns
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TLV987 3-V 10-BIT 27 MSPS AREA CCD SENSOR SIGNAL PROCESSOR
SLAS211A - MARCH 1999 - REVISED SEPTEMBER 1999
electrical characteristics over recommended operating free-air temperature range, AVDD = DVDD = 3 V, ADCCLK = 27 MHz (unless otherwise noted)
total device
PARAMETER AICC DICC Analog operating supply current Digital operation supply current Device power consumption Power consumption in power-down mode DNL INL Full channel differential nonlinearity Full channel integral nonlinearity -1 TEST CONDITIONS MIN TYP 66 1 200 2 0.6 2 1.5 MAX UNIT mA mA mW mW LSB LSB
analog-to-digital converter (ADC)
PARAMETER ADC resolution Full-scale input span Conversion rate ADC output latency No missing codes 4.5 Assured 2 27 TEST CONDITIONS MIN TYP MAX 10 UNIT Bits VPP MHz CLK cycles
correlated double sampler (CDS) and programmable gain amplifier (PGA)
PARAMETER CDS and PGA sample rate CDS full-scale input span Input capacitance of CDS Minimum PGA gain Maximum PGA gain PGA gain resolution PGA programming code resolution 8-bit monotonic gain control 35 Single-ended input 4 0 36 0.09 9 1 37 TEST CONDITIONS MIN TYP MAX 27 1 UNIT MHz V pF dB dB dB Bits
internal digital-to-analog converters (DAC) for offset correction
PARAMETER DAC resolution INL DNL Integral nonlinearity Differential nonlinearity Output settling time To 1% accuracy 0.6 0.5 80 TEST CONDITIONS MIN TYP MAX 8 1.2 .99 UNIT Bits LSB LSB ns
user digital-to-analog converters (DAC)
PARAMETER DAC resolution INL DNL Integral nonlinearity Differential nonlinearity Output voltage Output settling time 10-pF external load, Settle to 1 mV 0 4 0.5 0.5 TEST CONDITIONS MIN TYP MAX 8 1.2 .99 AVDD UNIT Bits LSB LSB V s
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TLV987 3-V 10-BIT 27 MSPS AREA CCD SENSOR SIGNAL PROCESSOR
SLAS211A - MARCH 1999 - REVISED SEPTEMBER 1999
electrical characteristics over recommended operating free-air temperature range, AVDD = DVDD = 3 V, ADCCLK = 27 MHz (unlessotherwise noted)
reference voltages
TEST CONDITIONS Internal bandgap voltage reference Temperature coefficient Voltage reference noise Positive reference voltage, ADC Ref+ Negative reference voltage, ADC Ref- Externally decoupled Externally decoupled 1.8 0.8 MIN 1.43 TYP 1.5 100 0.5 2 1 2.2 1.2 MAX 1.58 UNIT V ppm/C LSB V V
digital specifications
PARAMETER LOGIC INPUTS IIH IIL Ci VOH VOL IOZ C High-level input current Low-level input current Input capacitance High-level output voltage Low-level output voltage High-impedance output current Output capacitance IOH = 50 A, DIVDD = 3 V IOL = 50 A, DIVDD = 3 V -10 5 DIVDD = 3 V DIVDD = 3 V -10 -10 5 DIVDD-0.4 0.4 10 10 10 A A pF V V A pF TEST CONDITIONS MIN TYP MAX UNIT
LOGIC OUTPUTS
timing requirements
PARAMETER tw(SR) tw(SV) tsu1 th2 td tsu2 th1 Pulse duration, SR Pulse duration, SV Setup time, OBCLP before ADCCLK Hold time, ADCCLK after OBCLP Delay time, ADCCLK to ADCOUT valid Setup time, CS before SCLK Hold time, SCLK after CS 4 0 5 9 ns ns ns 50% to 50% 50% to 50% Minimum 0.25 x ADCCLK clock cycle TEST CONDITIONS MIN 10 10 TYP MAX UNIT ns ns
40 35 30 25 Gain - dB 20 15 10 5 0 0 28 56 84 112 140 168 196 224 252 280 308 336 364 392 420 448 476 504 PGA - Gain Code
Figure 1. TLV987 PGA Gain Code vs Gain
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TLV987 3-V 10-BIT 27 MSPS AREA CCD SENSOR SIGNAL PROCESSOR
SLAS211A - MARCH 1999 - REVISED SEPTEMBER 1999
PARAMETER MEASUREMENT INFORMATION
Optical Black Interval CCD Output n n+1 Dummy Black (Blanking) Interval Signal Interval
SR tw(SR) SV tw(SV) BLKG CLAMP OBCLP tsu1 ADCCLK td ADC OUT Latency = 4.5 Cycles n n+1 th1
Figure 2. System Operation Timing Diagram
tsu2 CS
th2
1 SCLK
2
3
4
5
6
7
16
SDIN
DI15
DI14
DI13
DI12
DI10
DI9
DI8
DI0
Figure 3. Timing Diagram
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TLV987 3-V 10-BIT 27 MSPS AREA CCD SENSOR SIGNAL PROCESSOR
SLAS211A - MARCH 1999 - REVISED SEPTEMBER 1999
APPLICATION INFORMATION
AVDD 0.1 F AVDD 0.1 F SR SV CLAMP (see Note D) 1 F 0.1 F 1 F 1 F 0.1 F 1 F
10 F 46 SV 45 SR 44 AGND1 AV DD1 43 42 V SS 41 AV DD5 40 RPD 39 RMD 38 RBD 37 AGND5 AREA CCD 1 F 48 47
AVDD 0.1 F
CLREF
1 2 3
CLAMP
DIN PIN
BLKG 36 TPP 35
BLKG TPP TPM
AVDD 0.1 F DVDD 0.1 F
13 D6 14 D7 15 D8 16 D9 17 DIVDD 18 DIGND 19 AV DD3 20 AGND3 21 DACO1 22 DACO2 23 DACT 24 OE
AVDD2 4 AGND2 5 DGND 6 DVDD 7 D0 8 D1 9 D2 10 D3 11 D4 12 D5
TLV987CPFB
TPM 34 AVDD4 33 32 AGND4 OBCLP 31 30 STBY 29 RESET 28 CS 27 SDIN 26 SCLK 25 ADCCLK
OBCLP STBY RESET CS SDIN SCLK ADCCLK
D (9-0) DIVDD AVDD DVDD DIVDD NOTES: A. B. C. D. 3V 3V 1.8 V to 4.4 V Analog Ground Digital Ground 0.1 F 0.1 F
OE DACT DACO2 DACO1 AVDD
All analog outputs should be buffered if the load is resistive or if the load is capacitive with more than 2-pF loading. When using the TPP and TPM pins to test internal PGA, the AVDD supply voltage should be 3.3 V. Clock signals on the TPP and TPM pins are inverted. These two capacitors should be placed as close to the device as possible.
Figure 4. Typical Application Connections
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TLV987 3-V 10-BIT 27 MSPS AREA CCD SENSOR SIGNAL PROCESSOR
SLAS211A - MARCH 1999 - REVISED SEPTEMBER 1999
PRINCIPLES OF OPERATION register definitions
serial input data format
DI15 X A3 0 0 0 0 0 0 0 0 1 D9 - D0 DI14 X A2 0 0 0 0 1 1 1 1 0 DI13 A3 A1 0 0 1 1 0 0 1 1 0 DI12 A2 A0 0 1 0 1 0 1 0 1 0 Control register. PGA gain register User DAC 1 register User DAC 2 register Coarse offset DAC Fine offset DAC Digital Vb register. Set reference code level at the ADC output during the optical black interval Optical black register. Set the number of black pixels per line and number of lines for digital averaging Test register 10-bit data to be written into the selected register DI11 A1 DI10 A0 DI9 D9 DI8 D8 DI7 D7 DI6 D6 DI5 D5 DI4 D4 DI3 D3 DI2 D2 DI1 D1 DI0 D0
control register format
D9 STBY D8 PDD1 D7 PDD2 D6 ACD D5 AFD D4 X D3 X D2 X D1 RTOB D0 RTSY
control register description
BIT D9 D8 D7 D6 NAME STBY PDD1 PDD2 ACD DESCRIPTION Device power down control: 1 = standby, 0 = active (default) Power down the user DAC1: 1 = standby, 0 = active (default) Power down the user DAC2: 1 = standby, 0 = active (default) Coarse offset DAC mode control: 0 = Auto calibration (default) 1 = Bypass auto calibration Note: When D6 is set to 0, D5 must also be set to 0 (auto mode); otherwise, the auto mode will be disabled on both offset DACs. Fine offset DAC mode control: 0 = Auto calibration (default) 1 = Bypass auto calibration Note: D5 can be set to 0 with or without D6 being set to 0. Reserved A write of a 1 to this bit resets the calculated black level results in the digital averager. A write of a 1 to this bit resets the entire system to the default settings.
D5
AFD
D4 - D2 D1 D0
X RTOB RTSY
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TLV987 3-V 10-BIT 27 MSPS AREA CCD SENSOR SIGNAL PROCESSOR
SLAS211A - MARCH 1999 - REVISED SEPTEMBER 1999
PRINCIPLES OF OPERATION
PGA register format
D9 X D8 Bit8 D7 Bit7 D6 Bit6 D5 Bit5 D4 Bit4 D3 Bit3 D2 Bit2 D1 Bit1 D0 Bit0
Default PGA gain = X000000000 or 0dB
user DAC1 and DAC2 registers format
D9 X D8 X D7 Bit7 D6 Bit6 D5 Bit5 D4 Bit4 D3 Bit3 D2 Bit2 D1 Bit1 D0 Bit0
Default user DAC register value = XX00000000
coarse offset DAC register format
D9 X D8 SIGN D7 Bit7 D6 Bit6 D5 Bit5 D4 Bit4 D3 Bit3 D2 Bit2 D1 Bit1 D0 Bit0
coarse offset DAC register description
BIT D9 D8 D7-D0 X SIGN NAME Reserved Coarse DAC sign bit, 0 = + sign (default), 1 = - sign Coarse DAC control data when D6 in the control register is set to 1 DESCRIPTION
Default coarse DAC register value = X000000000
fine offset DAC register format
D9 X D8 SIGN D7 Bit7 D6 Bit6 D5 Bit5 D4 Bit4 D3 Bit3 D2 Bit2 D1 Bit1 D0 Bit0
fine offset DAC register description
BIT D9 D8 D7-D0 X SIGN NAME Reserved Fine DAC sign bit, 0 = + sign (default), 1 = - sign Fine DAC control data when D5 in the control register is set to 1 DESCRIPTION
Default fine DAC register value = X000000000
digital Vb (optical black level) register format
D9 Bit9 D8 Bit8 D7 Bit7 D6 Bit6 D5 Bit5 D4 Bit4 D3 Bit3 D2 Bit2 D1 Bit1 D0 Bit0
Default Vb register value = 40 Hex.
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TLV987 3-V 10-BIT 27 MSPS AREA CCD SENSOR SIGNAL PROCESSOR
SLAS211A - MARCH 1999 - REVISED SEPTEMBER 1999
PRINCIPLES OF OPERATION
optical black calibration register format
D9 OMUX1 D8 OMUX0 D7 LN4 D6 LN3 D5 LN2 D4 LN1 D3 MP D2 PN2 D1 PN1 D0 PN0
optical black calibration register description
BIT D9, D8 NAME OMUX1, OMUX0 DESCRIPTION These two bits multiplex digital output (data presented at D(9-0) pins: OMUX1 OMUX0 0 0 D(9-0) = ADC output (default) 0 1 D(9-0) = ADC output 1 0 D9 = Fine/coarse (1/0) auto-correction flag D8 = Coarse DAC sign D(7-0) = Coarse DAC value 1 1 D9 = Fine/coarse (1/0) auto-correction flag D8 = Fine DAC sign D(7-0) = Fine DAC value Number of black lines for moving average = 2L L can be 0, 1, 2, 3, 4, 5, 6, 7, and 8. Or number of lines can be 1 (default), 2 4, 8, 16, 32, 64, 128, and 256. The maximum number of lines is 256 even if L > 8. When this bit is 1, the number of black pixels to be averaged per line (2N) is multiplied by 3. By setting the MP and PN2-PN0 bits together, the number of optical black pixels can be programmed to have the following numbers: 1, 2, 3 (1 x 3), 4, 6 (2 x 3), 8, 12 (4 x 3), 16, 24 (8 x 3), 32, 48 (16 x 3), 64, 96 (32 x 3), and 192 (64 x 3). Default: MP = 0, no multiplication D2-D0 PN2-PN0 Number of black pixels per line to average = 2N N can be 0, 1, 2, 3, 4, 5, and 6. Or number of pixels per line can be 1, 2, 4, 8 (default), 16, 32, and 64. The maximum number of pixels per line is 64 even if N > 6.
D7-D4
LN4-LN0
D3
MP
Default optical black calibration register value = 0000000011
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TLV987 3-V 10-BIT 27 MSPS AREA CCD SENSOR SIGNAL PROCESSOR
SLAS211A - MARCH 1999 - REVISED SEPTEMBER 1999
PRINCIPLES OF OPERATION
test register format
D9 TB9 D8 TB8 D7 TB7 D6 TB6 D5 TB5 D4 TB4 D3 TB3 D2 TB2 D1 TB1 D0 TB0
Default test register value =1010000000
test register description
BIT D9 - D6 NAME TB9 - TB6 DESCRIPTION These four bits are used to program the internal DC bias current. The bias current programming uses the following equation: Ibias = 8 A + (code) x 2 A Hence, Ibias varies from 8 A (code=0000) to 38 A (code=1111), with a linear step of 2 A. The recommended setting of the code is 1010 which sets the nominal Ibias value to 28 A. Test outputs (pin 34/35 - TPM/TPP) control: TB5 TB4 0 0 or 1 High impedance outputs at pin TPP and TPM. 1 0 Inverted internal CDS clock at pin TPP, Inverted internal PGA clock at pin TPM. 1 1 PGA non-inverting output at pin TPP, PGA inverting output at pin TPM. 1 = Use external reference, power down internal reference 0 = Use internal reference (default). Reserved Test output (pin 23, DACT) control for offset DACs: TB1 TB0 0 0 or 1 High impedance outputs at pin DACT (default = 00) 1 0 Fine offset DAC output at pin DACT 1 1 Coarse offset DAC output at pin DACT
D5, D4
TB5, TB4
D3 D2 D1, D0
TB3 TB2 TB1, TB0
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TLV987 3-V 10-BIT 27 MSPS AREA CCD SENSOR SIGNAL PROCESSOR
SLAS211A - MARCH 1999 - REVISED SEPTEMBER 1999
PRINCIPLES OF OPERATION CDS/PGA signal processor
The output from the CCD sensor is first fed to a correlated double sampler (CDS). The CCD signal is sampled and held during the reset reference interval and the video signal interval. By subtracting two resulting voltage levels, the CDS removes low-frequency noise from the output of the CCD sensor and obtains the voltage difference between the CCD reference level and the video level of each pixel. Two sample and hold control pulses (SR and SV) are required to perform the CDS function. The CCD output is capacitively coupled to the TLV987. The ac coupling capacitor is clamped to establish proper dc bias during the dummy pixel interval by the CLAMP input. The bias at the input to the TLV987 is set to 1.3 V. Normally, CLAMP is applied at the sensor's line rate. A capacitor, with a value ten times larger than that of the input ac coupling capacitor, should be connected between the CLREF pin and the AGND pin. When operating the TLV987 at its maximum speed, the CCD internal source resistance should be smaller than 50 . Otherwise, CCD output buffering is required. The signal is sent to the PGA after the CDS function is complete. The PGA gain can be adjusted from 0 dB to 36 dB by programming the internal gain register via the serial port. The PGA is digitally controlled with 9-bit resolution on a linear dB scale, resulting in a 0.09-dB gain step. The gain can be expressed by the following equation: Gain = PGA code x 0.09375 dB Where, the PGA code has a range of 0 to 383. For example, if the PGA code = 64, then the PGA gain = 6 dB (or gain of 2) The TLV987 has direct access to the PGA outputs through the TPP pin and the TPM pin. See test register description paragraph for details.
ADC
The ADC employs a pipelined architecture to achieve high throughput and low power consumption. Fully differential implementation and digital error correction ensure 10-bit resolution. The latency of the ADC data output is 4.5 ADCCLK cycles as shown in Figure 2. Pulling the OE pin (pin 24) high puts the ADC output in high impedance.
user DACs
The TLV987 includes two user DACs that can be used for external analog settings. The output voltage of each DAC can be independently set and has a range of 0 V to the supply voltage with 8-bit resolution. When the user DACs are not used in a camera system, they can be put in the standby mode by programming control bits in the control register.
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TLV987 3-V 10-BIT 27 MSPS AREA CCD SENSOR SIGNAL PROCESSOR
SLAS211A - MARCH 1999 - REVISED SEPTEMBER 1999
PRINCIPLES OF OPERATION internal timing
The SR and SV signals are required to operate the CDS as previously explained. The user needs to synchronize the SR and SV clocks with the CCD signal waveform. The output of the ADC is read out to external circuitry by the ADCCLK signal that is also used internally to control both ADC and PGA operations. It is required that the positive half cycle of the ADCCLK signal always falls in between two adjacent SV pulses as shown in Figure 2. The user can then fine tune the ADCCLK timing in relation to the CDS timing to achieve optimal performance. The TLV987 has direct access to the CDS and PGA internal clocks through the TPP pin and the TPM pin, which may be used to assist timing alignment. See test register description paragraph for details. The CLAMP signal is used to activate the input clamping, and the OBCLP signal is used to activate auto optical black and offset correction.
input blanking function
During some periods of operation, large input transients may occur at the TLV987 input, which can saturate the input circuits and cause long recovery time. To prevent circuit saturation under such a situation, the TLV987 includes an input blanking function that blocks the input signals by disabling CDS operation whenever the BLKG input is pulled low.
3-wire serial interface
A simple 3-wire (SCLK, SDIN, and CS) serial interface is provided to allow writing to the internal registers of the TLV987. The serial clock SCLK can be run at a maximum speed of 40 MHz. The serial data SDIN is 16 bits long. After two leading null bits, there are four address bits for which internal register is to be updated, the following ten bits are the data to be written to the register. To enable the serial port, the CS pin must be held low. The data transfer is initiated by the incoming SCLK after CS falls.
device reset
When the reset pin (pin 29) is pulled low, all internal registers are set to their default values. The device also resets itself when it is first powered on. In addition, the TLV987 has a software-reset function that resets the device when writing a control bit to the control register. See test register description paragraph for the register default values.
voltage references
An internal precision voltage reference of 1.5 V nominal is provided. This reference voltage is used to generate the ADC Ref- voltage of 1 V and Ref+ voltage of 2 V. All internally-generated voltages are fixed values and cannot be adjusted.
power-down mode (standby)
The TLV987 implements both hardware and software power-down modes. Pulling the STBY pin (pin 30) low puts the device in the low-power stand-by mode. Total supply current drops to about 0.6 mA. Setting a power-down control bit in the control register can also activate the power-down mode. The user can still program all internal registers during the power-down mode.
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PRINCIPLES OF OPERATION power supply
The TLV987 has several power supply pins. Each major internal analog block has a dedicated AVDD supply pin. All internal digital circuitry is powered by DVDD. Both AVDD and DVDD are 3 V nominal. The DIVDD and DIGND pins supply power to the output digital driver (D9-D0). The DIVDD pin is independent of the DVDD pin and can be operated from 1.8 V to 4.4 V. This allows the outputs to interface with digital ASICs requiring different supply voltages.
grounding and decoupling
General practices should apply to the PCB design to limit high frequency transients and noise that are fed back into the supply and reference lines. This requires that the supply and reference pins be sufficiently bypassed. In the case of power supply decoupling, 0.1-F ceramic chip capacitors are adequate to keep the impedance low over a wide frequency range. Recommended external decoupling for the three voltage reference pins is shown in Figure 3. Since their effectiveness depends largely on the proximity to the individual supply pin, all decoupling capacitors should be placed as close to the supply pins as possible. To reduce high frequency and noise coupling, it is highly recommended that the digital ground and analog ground be shorted immediately outside the package. This can be accomplished by running a low impedance line between the DGND and AGND pins, under the package.
automatic optical black and offset correction
In the TLV987, the optical black and system channel offset corrections are performed by an auto digital feedback loop. Two DACs are used to compensate for both channel offset and the optical black offset. A coarse correction DAC (CDAC) is located before the PGA gain stage and a fine correction DAC (FDAC) is located after the gain stage. The digital calibration system is capable of correcting the optical black and channel offset down to one ADC LSB accuracy. The TLV987 automatically starts auto-calibration whenever the OBCLP input is pulled low. The OBCLP pulse should be wide enough to cover one positive half cycle of the ADCCLK as shown in Figure 1. For each line, the optical black pixels plus the channel offset are sampled and converted to digital data by the ADC. A digital circuit averages the data during the optical black pixels. The final averaged result is compared digitally with the desired output code stored in the Vb register (default is 40h), then control logic adjusts the FDAC to make the ADC output equal to the Vb. If the offset is out of the range of the FDAC (255 ADC LSBs), the error is corrected by both the CDAC and FDAC. The CDAC increments or decrements by one CDAC LSB depending on whether the offset is negative or positive, until the output is within the range of the FDAC. The remaining residue is corrected by the FDAC. The relationship among the FDAC, CDAC, and ADC in terms of the number of ADC LSBs is as follows: 1 FDAC LSB = 1 ADC LSB, 1 CDAC LSB = 0.5 x PGA linear gain x 1 ADC LSB. For example, if PGA gain = 2 (6 dB), then, 1 CDAC LSB = 1 ADC LSB. After auto-calibration is complete, the ADC digital output during CCD signal interval can be expressed by the following equation: ADC output [D9-D0] = CCD_input x PGA gain + Vb, Where, Vb is the desired black level selected by the user. The total offset including optical black offset is calibrated to be equal to the Vb by adjusting the offset correction DAC during auto-calibration.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
15
TLV987 3-V 10-BIT 27 MSPS AREA CCD SENSOR SIGNAL PROCESSOR
SLAS211A - MARCH 1999 - REVISED SEPTEMBER 1999
PRINCIPLES OF OPERATION
The number of black pixels in each line and the number of lines are programmable. The number of black pixels per line that can be averaged is equal to 2N, where N can be 0, 1, 2, 3, 4, 5, and 6. In addition, if the MP bit is set to 1, then the number of black pixels that are averaged per line will be 3 2N. The number of lines is equal to 2L, where L can be 0, 1, 2, 3, 4, 5, 6, 7, and 8.
The auto-calibration feature can be bypassed if the user prefers to directly program the offset DAC registers. Switching from auto-calibration mode to direct programming mode requires two register writes. First, the control bits for the offset DACs in the control register need to be changed, then the desired offset value for the register is loaded into the offset DAC registers for proper error correction. If the total offset including optical black level is less than 255 ADC LSBs, only the FDAC needs to be programmed. When switching from the direct programming mode to the auto-calibration mode, the previous DAC register values are used as starting offsets rather than default DAC register values. A detailed block diagram for internal automatic optical black and offset correction is shown in Figure 5. The timing diagram in Figure 6 illustrates the operation of the calibration system. In the example, the TLV987 is programmed to average four black pixels (N = 2) per line for two lines (L = 1).
16
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
TLV987 3-V 10-BIT 27 MSPS AREA CCD SENSOR SIGNAL PROCESSOR
SLAS211A - MARCH 1999 - REVISED SEPTEMBER 1999
PRINCIPLES OF OPERATION
ADCCLK
ADC<9:0> CDS PGA ADC
COARSE DAC SIGN_CDAC
SIGN_FDAC
PGA GAIN REGISTER
FINE DAC
BYPASS AUTOCOARSE CS SCLK SDIN SERIAL PORT
1COARSE DAC LSB = 0.5 ADC LSB x PGA Gain SIGN + CDAC <7:0>
1FINE DAC LSB = 1 ADC LSB
1 SIGN + FDAC <7:0> 0 DATA OUT
REGISTER
BYPASS AUTOFINE 0 1
REGISTER ADC<9:0> 0 AUTO FDAC CONTROL RESET TIMING AND CALIBRATION LOGIC FDAC CDAC OBCLP SP<8:0>
SP<9:0>
1 SP<8:0>
VB
OBREG
AUTO CDAC CONTROL
L<3:0>,N<2:0>
VB<9:0>
Figure 5. Optical Black and Offset Correction Block Diagram
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
17
TLV987 3-V 10-BIT 27 MSPS AREA CCD SENSOR SIGNAL PROCESSOR
SLAS211A - MARCH 1999 - REVISED SEPTEMBER 1999
PRINCIPLES OF OPERATION
First Line SR SV Second Line
CCD output
CCD CCD CCD CCD 1 2 3 4
CCD CCD 1 2
CCD CCD 3 4
CDS OUT (internal) OBCLP
PGA samples "CCD1"
ADCCLK
ADD255 (internal)
2N+1 PIXELS During this interval an offset of 255 LSB is intentionally added to the PGA output (see Note)
2N+1 PIXELS 3 half cycles allow settling
OBPC (internal)
OBLC (internal) Latency = 4.5 Cycles ADC OUT for black pixels
Initiates internal counters, etc.
DACs are updated
ADC ADC ADC ADC 1 2 3 4
Figure 6. Optical Black and Offset Correction Timing To avoid the ADC being clipped on differential negative input signals, an internal offset that is equal to 255 ADC LSBs is intentionally added to the PGA output signal. This offset is only added during the optical black pixel interval with a total duration of 2N + 3 pixels, where three additional pixels are necessary for accommodating internal latency adjustment.
18
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
TLV987 3-V 10-BIT 27 MSPS AREA CCD SENSOR SIGNAL PROCESSOR
SLAS211A - MARCH 1999 - REVISED SEPTEMBER 1999
MECHANICAL DATA
PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK
0,50 36 25
0,27 0,17
0,08 M
37
24
48
13 0,13 NOM 1 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 0,05 MIN 1,05 0,95 Seating Plane 0,75 0,45 Gage Plane 0,25 0- 7 12
1,20 MAX
0,08 4073176 / B 10/96
NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
19
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Copyright (c) 1999, Texas Instruments Incorporated

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