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TLFD500PN 3.3 V INTEGRATED G.LITE ANALOG FRONT END
SLAS207B - JUNE 1999 - REVISED MAY 2000
D D D D D D D D D
Complies With ITU G.992.2 Standard 14-Bit Integrated A/D and D/A Converters 1.104 Msps Update Rate for the RX Channel 276 ksps Update Rate for the TX Channel Minimum 50 dB Missing Tone Rejection for DMT Signals Integrated TX/RX Filters Integrated Digital Phase Lock Loop (DPLL) and VCXO DAC Integrated Equalizer for Receive Channel Integrated PGA in Receive, and PAA in Transmit Channels
D D D D D D D D
Direct Single Serial Interface to TI's C54x or C6x DSP (Data and Control) Eight General-Purpose I/O Pins Software and Hardware Power-Down Modes Industrial Temperature Range (-40C to 85C) Integrated Auxiliary Amplifiers for System Flexibility Single 3.3 V Supply 80-Pin LQFP (PN) Package 2s Complement Data Format
description
The TLFD500PN is a high-speed analog front end for a remote terminal-side ADSL G.Lite modem. The device is designed to perform transmit encoding (D/A conversion), receive decoding (A/D conversion), transmit and receive filtering functions, and receive equalizer functions for a frequency division multiplex (FDM) G.Lite application. The receive channel has an update rate of 1.104 Msps, while the transmit channel has an update rate of 276 ksps. Both channels use 2s complement data format. When used in a G.Lite system, the TLFD500PN requires a minimum number of external components. The device incorporates integrated filtering, DPLL, VCXO DAC (uses 2s complement data format), and 8 general-purpose I/O ports. The general-purpose I/O ports provide a means of reading or writing status bits in the system. Four auxiliary amplifiers on the chip can be configured (external components may be required) to provide additional onboard filtering and amplification. A simple serial interface for data transfer on the digital side reduces system component count. The interface can be connected directly to the TI C6x and C54x families of DSPs. The TLFD500PN device is available in an 80-pin PN LQFP package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 2000, Texas Instruments Incorporated
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TLFD500PN 3.3 V INTEGRATED G.LITE ANALOG FRONT END
SLAS207B - JUNE 1999 - REVISED MAY 2000
PN PACKAGE (TOP VIEW)
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
AMP4OUTP AMP4OUTM NC AMP3OUTP AMP3INM AMP3INP AMP3OUTM AVDD_RX AVSS_RX RXINP RXINM HPF2OUTP HPF2INM HPF2INP HPF2OUTM HPF1OUTP HPF1INM HPF1INP HPF1OUTM VSS
AMP4INM AMP4INP NC DVSS_RX DVSS_RX DVSS_RX DVSS_RX NC DVSS_RX DVDD_RX VMID_RX AVSS_RX AVDD_RX AVDD_REF REFP REFM AVSS_REF
RXBANDGAP PLLSEL DVSS
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 1 23 45 6
40 39 38 37 36 35 34 33 32 31 30 29 27 27 26 25 24 23 22 21 7 8 9 10 11 12 13 14 15 16 17 18 19 20
TLFD500PN
DVSS DVDD RESET MCLKIN/PLLCLKIN NC DGPO DVSS DVSS_IO DVDD_IO DVDD GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 FSX FSR
NC - No connection
2
AMP2OUTM AMP2INP AMP2INM AMP2OUTP TXOUTP TXOUTM AVDD_TX AVSS_TX AMP1OUTP AMP1INM AMP1INP AMP1OUTM VCXOCNTL TXBANDGAP COMPDAC2 COMPDAC1 PWRDN SDX SCLK SDR
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TLFD500PN 3.3 V INTEGRATED G.LITE ANALOG FRONT END
SLAS207B - JUNE 1999 - REVISED MAY 2000
functional block diagram
30 kHz to 138 kHz 276 KSPS 30 kHz Digital HPF 138 kHz Digital LPF 0 to -24 dB (-1 dB/step) TX PAA PAA TXOUTP/ TXOUTM
14 Bit 4.416 MSPS TX DAC
138 kHz TX LPF
FSR FSX SDR SDX SCLK Serial Interface and Control
Digital Loop-back 14 Bit 4.416 MSPS ADC 0 to 9 dB (0.25 dB/Step) RX PGA3 PGA
Analog Loop-back 552 kHz Equalizer+ RX LPF
552 kHz RX LPF
RXINP/ RXINM See Note
1104 KSPS
INTERNAL CLOCK
0 to 18 dB (6 dB/step) RX PGA2 PGA
180 kHz HPF2
0 to 12 dB (3 dB/Step) RX PGA1 PGA
HPF2OUTP/ HPF2OUTM HPF2INP/ HPF2INM See Note
Clock Generator 180 kHz HPF1
HPF1OUTP/ HPF1OUTM HPF1INP/ HPF1INM AMPOUTP/ AMPOUTM AMPINP/ AMPINM
VCXO DAC
DPLL
INTERNAL REFERENCE
General Purpose I/O
AUX Amps(4)
VCXOCNTL
MCLKIN
MCLKIN VMID_RX GPI00-GPI07 External Oscillator 35.328 MHz REFP REFM TXBANDGAP/ RXBANDGAP
External VCXO 35.328 MHz
NOTE: Refer to Figure 17 for application details.
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Terminal Functions
TERMINAL NAME AMP1INP- AMP4INP AMP1INM- AMP4INM AMP1OUTP- AMP2OUTP AMP3OUTP- AMP4OUTP AMP1OUTM- AMP2OUTM AMP3OUTM- AMP4OUTM AVDD_REF AVDD_RX AVDD_TX AVSS_REF AVSS_RX AVSS_TX COMPDAC1 COMPDAC2 DGPO NO. 11,2,66,59 10,3,65,60 9,4 64, 61 12,1 67,62 47 48,68 7 44 49,69 8 16 15 35 I/O I I O O O O I I I I I I I I O Auxiliary amplifier 1-4 positive input Auxiliary amplifier 1-4 negative input Auxiliary amplifier 1-2 positive output. Outputs are self-biased to AVDD_TX/2. Auxiliary amplifier 3-4 positive output. Outputs are self-biased to AVDD_RX/2. Auxiliary amplifier 1-2 negative output. Outputs are self-biased to AVDD_TX/2. Auxiliary amplifier 3-4 negative output. Outputs are self-biased to AVDD_RX/2. Analog supply for reference circuit RX channel analog supply TX channel analog supply Analog supply return for reference(analog ground) RX channel analog supply return (analog ground) TX channel analog supply return (analog ground) TX channel decoupling cap input A. Add 1 F capacitor to AVDD_TX TX channel decoupling cap input B. Add 1 F capacitor to AVDD_TX Direct general-purpose output. This pin reflects the last value written to the DGPO bit location in the SDR data stream. It is a general-purpose output that does not require a secondary transfer to control. Digital power supply Digital I/O buffer supply RX channel digital supply Digital ground Digital I/O buffer supply return (digital ground) RX channel digital supply return (digital ground) Serial port frame sync transmit signal Serial port frame sync receive signal General-purpose I/O RX channel stage 1 amplifier positive input. Input signal needs to have AVDD_RX/2 common mode voltage. RX channel stage 1 amplifier negative input. Input signal needs to have AVDD_RX/2 common mode voltage. RX channel stage 2 positive input. Input signal need to have AVDD_RX/2 common mode voltage. RX channel stage 2 negative input. Input signal need to have AVDD_RX/2 common mode voltage. RX channel stage 1 amplifier positive output. Used to connect external components to obtain stage 1 HPF. RX channel stage 1 amplifier negative output. Used to connect external components to obtain stage 1 HPF. RX channel stage 2 positive output. Output signal has AVDD_RX/2 common mode voltage. RX channel stage 2 negative output. Output signal has AVDD_RX/2 common mode voltage. Multiplexed pin based on value of PLLSEL. Selects master clock input, or clock input for PLL mode. DESCRIPTION
DVDD DVDD_IO DVDD_RX DVSS DVSS_IO DVSS_RX FSX FSR GPIO0-GPIO7 HPF1INP HPF1INM HPF2INP HPF2INM HPF1OUTP HPF1OUTM HPF2OUTP HPF2OUTM MCLKIN/PLLCLKIN
31,39 32 51 34,40,41 33 52,54,55, 56,57 22 21 23-30 78 77 74 73 76 79 72 75 37
I I I I I I O O I/O I I I I O O O O I
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SLAS207B - JUNE 1999 - REVISED MAY 2000
Terminal Functions (Continued)
TERMINAL NAME NC PLLSEL PWRDN REFM NO. 36,53, 58, 63 42 17 45 I I O I/O No connection. Keep floating. Selects between VCXO mode and DPLL mode. If the pin is tied high PLL mode is selected. Pin should be tied low for VCXO mode. Cannot be left floating. Power-down pin. When PWRDN is pulled low the device goes into power-down mode. The default state of this pin is low. Negative reference filter node. This terminal is provided for low-pass filtering of the internal band-gap reference. The optimal ceramic capacitor value is 10 F (tantalum) and 0.1 F (ceramic), connected to analog ground. The nominal dc voltage at this terminal is 0.5 V. Positive reference filter node. This terminal is provided for low-pass filtering of the internal band-gap reference. The optimal ceramic capacitor value is 10 F (tantalum) 0.1 F (ceramic), connected to analog ground. The nominal dc voltage at this terminal is 2.5 V. Device reset input pin. Initializes all the device's internal registers to their default values. The default state of this pin is low. RX channel band-gap filter node. This terminal is provided for decoupling of the 1.5-V band-gap reference. The optimal capacitor value is 10 F (tantalum) and 0.1 F (ceramic). This node should not be used as a voltage source. RX channel stage 3 positive input. The input is self-biased at AVDD_RX/2. RX channel stage 3 negative input. The input is self-biased at AVDD_RX/2. Serial port shift clock (transmit and receive) Serial data receive from DSP Serial data transmit to DSP TX channel band-gap filter node. This terminal is provided for decoupling of the 1.5-V band-gap reference. The optimal capacitor value is 10 F (tantalum) and 0.1 F (ceramic). This node should not be used as a voltage source. TX channel positive output TX channel negative output DAC output to control onboard VCXO Decoupling Vmid for ADC. Add 10 F (tantalum) and 0.1 F (ceramic) capacitors to analog ground. Substrate. Connect to analog ground. DESCRIPTION
REFP
46
O
RESET RXBANDGAP
38 43
I O
RXINP RXINM SCLK SDR SDX TXBANDGAP
70 71 19 20 18 14
I I O I O O
TXOUTP TXOUTM VCXOCNTL VMID_RX VSS
5 6 13 50 80
O O O I/O I
detailed description
transmit The transmit channel is powered by a high performance DAC. The transmit channel update rate is 276 kHz. The DAC is a 14-bit DAC at 4.416-MHz. This provides 16X oversampling. A band-pass filter limits the output of the transmitter to a frequency range of 30 kHz to 138 kHz. A differential amplifier drives the output into the external line driver. The differential amplifier has programmable attenuation for added flexibility. The transmitter high-pass filter can be bypassed by writing the appropriate bit to the filter bypass control register (BCR). The output spectrum of the DAC complies with the nonoverlapped power spectrum density (PSD) mask specified in the ITU draft recommendation G.992.2 for G.Lite. The TXPAA is a programmable-attenuation amplifier. It provides 0 dB to 24 dB of attenuation in1-dB steps. The TXPAA is controlled via the PAA control register (PCR). For details about register programming see the register programming section.
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detailed description (continued)
receive The receive channel consists of a high-pass filter, a programmable gain amplifier, an ADC, and filters. In addition, it has an equalizer to attain maximum system performance. The input of the receiver is fully differential. The ADC in the receive channel is a 14-bit converter which samples at 4.416 Msps for 4X oversampling. An on-chip decimator reduces the sampling frequency to 1.104 MHz. The low pass filtering of the receive channel limits the converted data to frequencies below 552 kHz. The high-pass analog filter is used to reject the near-end echo to maximize the dynamic range of the ADC. The high-pass filter consists of two stages: (1) a second order high-pass filter (HPF1) and, (2) a third order elliptic high-pass filter (HPF2). Both stages have a cutoff at 180 kHz. The filter is divided into two stages to minimize the noise from a single stage being amplified throughout. Together, the two high-pass filters typically attenuate the echo power by 30 dB. There is a programmable gain amplifier (PGA) between the two filters for coarse gain adjustments of 0-dB -12-dB in 3-dB steps. After the high-pass filter stage, the receiver channel has a 0-dB -18-dB PGA that can be adjusted in 6-dB steps. HPF2 and PGAs are integrated in one block. Figure 1(a), 1(b), and 1(c) show the frequency response of HPF1 and HPF2 (with PGAs). The PGA is followed by a 552-kHz low-pass filter with a programmable 25-dB/MHz slope (5-dB/MHz step) equalizer incorporated. After the equalizer, there is a fine-gain adjustment PGA of 0-dB to 9-dB in 0.25-dB steps. All the RX PGAs are controlled via the PGA control registers (PCR-RX1 and PCR-RX2). See the register programming section for details about register programming.
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SLAS207B - JUNE 1999 - REVISED MAY 2000
detailed description (continued)
50 0 -50 Gain - dB Gain - dB 0 0.5 1 f - Frequency - Hz 1.5 x 105 2 2 0 -2
-100 -150 -200 -250
-4 -6 -8
-10
1
1.2
1.6 1.4 f - Frequency - Hz
1.8
2 x 105
(a) RX-Stage HPF1 Frequency Response (0 to 200 kHz)
(b) RX-Stage HPF1 Frequency Response (100 kHz to 200 kHz)
0 - 3 - 6 - 9 -12 -15 -18 -21 -24 -27 38.6 90.6 142. 194. 6 kHz 6 246. 6 298. 6
dB
(c) RX-Stage HPF2 Frequency Response (PGA1 = PGA2 = 0 dB)
Figure 1. RX Stage HPF1 and HPF2 Frequency Response clock control - VCXO mode The VCXODAC uses a 12-bit, 2s complement number to control a 0-V to 3-V analog output. The two 8-bit registers, VCR-M and VCR-L, are used to generate the 12-bit control code (2s complement). This implies the use of 16 bits to obtain a 12-bit number. VCR-M register occupy the most significant 8 bits in the 12-bit number and the lower 4 bits of the VCR-L register (VCR-L[3:0] ) are used for the low 4 bits of the 12-bit number. The 12-bit code is updated every time either register is updated. VCR-L[7:4] must always be zero.
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TLFD500PN 3.3 V INTEGRATED G.LITE ANALOG FRONT END
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clock control - DPLL mode As an alternative to the VCXODAC and VCXO, an off-chip crystal oscillator (XO) followed by an on-chip digital PLL are also implemented. Refer to Figure 7 for an internal function block diagram. The input clock (35.328 MHz) goes to a programmable frequency divider to generate sampling clock for the ADC and DAC converters. By changing the divide ratio, the phase of the sampling clock can be adjusted. Setting PLLSEL (pin 42) high will enable the DPLL mode. Refer to DPLL section for detail. clock generation The clock generation block creates the necessary internal and external clocks needed by the device. All the clocks generated are produced from the CLKIN signal. The following are recommended operational parameters for the external VCXO: 3.3-V supply, 35.328 MHz 50 PPM center frequency, and input control voltage range of 0 V-3 V. The recommended duty cycle is 50/50. clock generation - SCLK SCLK is an output and is used for serial data transfer. It runs at 35.328 MHz. Although SCLK and MCLK run at the same speed, there is no fixed phase relationship between them. serial interface The serial interface on the TLFD500PN connects directly to TI's C54x or C6x families of DSPs. The interface operates at 35.328 MHz. The serial port consists of five signals: SCLK, FSX, FSR, SDX, and SDR. A typical connection diagram is shown in Figure 2.
DSP CLKR CLKX FSX FSR DX DR SCLK FSR FSX SDR SDX TLFD500PN
Figure 2. Typical Serial Port Connection The serial port utilizes a primary/secondary scheme to transfer conversion data and control register data. A primary transfer scheme, used to transfer conversion data, occurs every conversion period. A secondary transfer scheme, used to transfer control data, happens only when requested by the host processor. The host processor requests a secondary transfer by using the LSB of the SDR data of the primary scheme. A value of 1 indicates a secondary transfer request. Once the secondary request is made and the primary transfer has been completed, secondary frame sync pulse (FSX/FSR) are transmitted to the host processor to indicate the beginning of the secondary transfer. The secondary FSX signal arrives 16 SCLKs after the primary FSX, and thus 48 SCLKs after the host processor request. This is because the span between FSX pulses for primary transfers is always 32 SCLKs. Each bit is read/written at the rising edge of the SCLK clock. Data bit mappings and example data transfers are shown in Table 1.
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detailed description (continued)
Table 1. SDR LSB Control Function
CONTROL BIT D0 0 1 CONTROL BIT FUNCTION No secondary transfer requested Secondary transfer requested
primary transfer data mapping The data bit mapping of a primary transfer is shown in Figure 3. Bits D2-D15 of the SDR data stream are DAC data. D1 is the control bit for the DGPO pin. The value written to this bit is reflected on the DGPO pin. See the timing diagram in Figures 5 and 6 for detailed timing information. D0 is the secondary transfer request bit. When a 1 is written to this bit, the host is requesting a secondary data transfer. In the SDX data stream, D2-D15 contain the ADC conversion data. D0 and D1 can be set to reflect the values of GPIO1 and GPIO2. To set D0 and D1 to reflect the GPIO values, the proper bit in the MCR register needs to be set.
Secondary Transfer Request
Data to CODEC
DGPO Bit
SDR
D15 - D2
D1
D0
Data from CODEC
GPIOx Status if Configured as Input. Zero if GPIOx Configured as output or if Masked Off
SDX
D15 - D2
GPIO1
GPIO0
Figure 3. Primary Transfer Data Bit Mapping secondary transfer data mapping Secondary serial communication is used to configure the device. The data bit mapping for a secondary transfer is shown in Figure 4. Bits D10-D14 of the SDR data from the host contain the address of the control register involved in the transfer. D15 is a R/W bit. To read out the control register by the host processor, bit R/W must be set to 1. To write to the control register by the host processor, bit R/W must be set to 0. During a read operation, bits D0-D7 are don't care. For a write operation, bits D0-D7 contain the data for the register addressed by D10-D14. The eight bits of SDX always reflect the status of GPI00-7. If the secondary transfer is a read operation, the contents of the control register addressed by D10-D14 of the SDR data are reflected in bits D0-D7 of the SDX data stream. If the secondary transfer is a write operation, bits D0-D7 on SDX will be all zeroes.
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secondary transfer data mapping (continued)
D15 SDR (Read) 1 A4 A3 A2 A1 A0 D9 D8 D7 Don't Care D0
Register Address D15 SDX (Read) GPIO0 - 7 Status
Don't Care D8 D7 Register Data D0
Read Cycle (Codec Register Data Read by DSP)
D9 SDR (Write) 0 A4 A3 A2 A1 A0
D8
D7
D0
Register Address D15 SDX (Write) GPIO0 - 7 Status
Don't Care D8 D7
Data to the Register D0 All 0
Write Cycle (DSP Data Write to Codec Register)
Figure 4. Secondary Transfer Data Bit Mapping example data transfers Figures 5(a) and 5(b) show the timing relationship for SCLK, FSX, SDX, FSR, and SDR in a primary communication. The timing sequence for this operation is as follows: 1. FS is set high and remains high during one SCLK period, then returns to low. 2. A 16-bit word is transmitted from the ADC (SDX), and a 16-bit word is received for DAC conversion (SDR). Figure 6(a) and 6(b) shows the timing relationship with secondary request.
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detailed description (continued)
SCLK (Output)
FSX (output)
SDX (Output)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
t1 t2 t3 t1: DSP detects FSX t2: TLFD500PN sends data t3: DSP latches data (a) TLFD500PN to DSP
SCLK (Output)
FSR (output)
SDR (Input)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
t1 t2
t3 t1: DSP detects FSR t2: DSP sends data t3: TLFD500PN latches data (b) DSP to TLFD500PN
NOTE: TI DSP requires 10 ns after the positive edge of the SCLK to give the SDR data. This plus the board delay, output buffer (for SCLK) and input buffer delay (for SDR) to around 17 ns. As a consequence the SDR data can not be latched at the negative edge of SCLK.
Figure 5. Data Transfers
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detailed description (continued)
128 SCLKs
FSR
P
S
P
48 SCLKs FSX 16 SCLKs SDR Data P P S P P P
SDX
Data
FSR
P
32 SCLKs FSX 16 SCLKs SDR Data P P P P P
SDX
Data
12
IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII
IIIIIIIIIIIIII IIIIIII IIIIIIIIIIIIII IIIIIII IIIIIIIIIIIIII IIIIIII
Don't Care Command Don't Care Zeroes Data Status Data Zeroes Data Zeroes (a) With Secondary Request 128 SCLKs P Don't Care Zeroes Data Zeroes Data Zeroes Data Zeroes (b) Without Secondary Request
Data
Data
Data
Data
Figure 6. Data Transfers
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detailed description (continued)
general purpose I/O port (GPIO) The general-purpose I/O port provides eight input/output pins and one output-only pin for control of external circuitry, or for reading the status of external devices. The eight input/output pins are labeled GPIO0 -GPIO7. The output-only pin is labeled DGPO (direct general-purpose output). This pin is labeled as direct because a secondary transfer is not required to write to this pin. The GPIO pins are controlled and read in the GPR-D register. The GPR-C register is used to configure the GPIO pins as input or output pins. The default reset condition is 11111111b, indicating that all are configured as inputs. For further details on register programming see the register programming section. The DGPO pin does not need configuring and is controlled by the D1 bit in the SDR data stream (that is, from the DSP to the TLFD500PN) during primary data transfers. In addition, a secondary transfer is not required to read GPIO0 and GPIO1 when they are configured as inputs. Their values can be mapped into the lower two bits of the SDX data stream (that is, from TLFD500PN to DSP) during primary data transfers. To map the values of GPIO0 and GPIO1 into the lower two bits of the SDX ADC data stream, set the appropriate bit in the MCR register. For more flexibility, the values of GPIO0 - GPIO7 are mapped into the upper eight data bits of the SDX data stream on secondary data transfers. This allows the host processor to read the values of the GPIO pins and the contents of another control register during the same secondary data transfer. When a GPIO pin is being configured as an output, its corresponding status bit in the SDX data stream will be the last value written to the output pin. Each output is capable of driving 2 mA. reference system The integrated reference provides voltage and current to the internal analog blocks. It is also brought out to external pins for noise decoupling. They should not be used as dc voltage source. When the internal reference is being used by the device, the device may be powered down by writing the appropriate reference control bit in the main control register (MCR) to achieve power savings during periods of device inactivity. auxiliary amplifiers Four auxiliary high-performance operational amplifiers on the chip allow for additional onboard filtering and amplification with minimal component count. Each op-amp has differential inputs and outputs, with 2 input pins and 2 output pins. Each op-amp can be enabled by register programming. The typical specifications for the operational amplifiers are as follows: DC Gain: Bandwidth: PSRR: Output common-mode: Input interface: device power-up sequence All digital and analog supplies must be properly biased. All supply pins are mandatory. The power supply can not be switched, even when the codec has been powered down or parts of the codec are in power-down mode. Reset must be held at least 20 s after power up. To reset the reference circuit and registers requires 100 ms. When the chip is woken up from hardware power-down mode, it takes100 ms to reset the reference circuit before the chip works in normal mode. When the chip is woken up from software power-down mode, only 20 s is needed before valid data comes out (reference must be kept on). Register values will not change in either wake-up operation. 126 dB 116 MHz 100 dB at dc, 70 dB at 1 MHz, and 40 dB at 4 MHz AVDD_RX/2 (auxiliary amplifier 3,4) or AVDD_TX/2 (auxiliary amplifier 1,2) AC coupled
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detailed description (continued)
register programming The codec registers are listed in Table 2, with each bit of each register defined. All registers are 8-bit wide.
NOTE: Bits not defined in the table are reserved for future use. During a read, the reserved bit read value is not guaranteed. During a write, only zeroes can be written to reserved bits.
Table 2. Codec Registers
REGISTER NAME BCR ADDRESS A4 A3 A2 A1 A0 00001 MODE R/W FUNCTION D0: Power-down RX HP filter 1 D1: Power-down RX HP filter 2 D2: Bypass TX digital HP filter D3: Echo mode: Echo SDR data back to SDX D4: Reserved D5: Reserved D6: Reserved D[5:0] = RXPGA3[5:0]; Fine gain, 0 to 9 dB, 0.25-dB steps D[2:0] = RXPGA1[2:0]; 0 to 12dB, 3-dB steps D[4:3] = RXPGA2[1:0]; 0 to 18 dB, 6-dB steps D[4:0] = TX PAA[4:0]; 0 to -24dB, -1-dB steps D[2:0] = EQ[2:0] 0 to 25 dB, 5 dB/MHz steps; D[6:4] = EQ_PGA[2:0] 0 to 6 dB, 1 dB steps D[7:0] = VCXO DAC control Bit[11:4]. D[3:0] = VCXO DAC control Bit[3:0]. D[7:4] must always be zero. D[7:0] = GPIO1 I/O control (0 = output, 1 = input) D[7:0] = GPIO data register For future use. Read or write of register not allowed. D0: Enable auxiliary amplifier 2 D1: Enable auxiliary amplifier 1 D2: Enable auxiliary amplifier 3 D3: Enable auxiliary amplifier 4 D[7:0] = Default NCO divide number D[7:0] = Number of samples, from current secondary transfer, after which effect of delta will occur. D[7:4] = Delta from default for first sample of data frame (-8 through 7) D[3:0] = Number of times NCO divider remains changed from default before being set back to default (0 through 15) D0: S/W Power-down main reference D1: S/W Power-down TX channel with reference still on D2: S/W Power-down RX channel with reference still on D3: S/W Power-down VCXO with reference still on D4: S/W Reset D5: Analog loop back (refer to block diagram) D6: Digital loop back (refer to block diagram) D7: Enable GPIO 1 and 2 to show in SDX primary data
PCR-RX1 PCR-RX2 PCR-TX EQR VCR-M VCR-L GPR-C GPR-D Reserved AUXR
00010 00011 00100 00101 00110 00111 01000 01001 01010 01011
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
NCO_DEF NCO_DIV_DELAY NCO_DELTA
01100 01101 01110
R/W R/W R/W
MCR
01111
R/W
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BCR - bypass control register
Address: 00001b D7 Reserved D6 Reserved Contents at reset: 00000000b D5 Reserved D4 Reserved D3 ECHO D2 TXHPEN D1 RXHP2PD D0 RXHP1PD
Table 3. EQR Bit Definition
D7 R - - - - - - - - - - - D6 - R - - - - - - - - - - D5 - - R - - - - - - - - - D4 - - - R - - - - - - - - D3 - - - - 0 1 - - - - - - D2 - - - - - - 0 1 - - - - D1 - - - - - - - - 0 1 - - D0 - - - - - - - - - - 0 1 REG. VALUE - - - - - 0x08 - 0x04 - 0x02 - 0x01 BIT NAME Reserved Reserved Reserved Reserved ECHO TXHPEN RXHP2PD RXHP1PD DESCRIPTION Bit reserved for future use Bit reserved for future use Bit reserved for future use Bit reserved for future use Do not echo SDR data on SDX Echo SDR data on SDX (see Note 1) Enable TX HP Filter Bypass TX HP Filter Power up RX HP Filter 2 Power down RX HP Filter 2 Power up RX HP Filter 1 Power down RX HP Filter 1
NOTE 1: ECHO mode allows for a quick verification of the serial interface operation. It sends back the data from input data buffer to the output data buffer and does not exercise the RX or TX channel.
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PCR-RX1 - programmable gain control register 1 for RX channel PGA3
Address: 00010b D7 Reserved D6 Reserved Contents at reset: 00000000b D5 RXPGA3[5] D4 RXPGA3[4] D3 RXPGA3[3] D2 RXPGA3[2] D1 RXPGA3[1] D0 RXPGA3[0]
Table 4. PCR-RX1 Gain
D7 R - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - D6 - R D5 - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 D4 - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 D3 - - 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 D2 - - 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 D1 - - 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 D0 - - 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 HEX VALUE - - 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 BIT NAME Reserved Reserved RXPGA3[5:0] DESCRIPTION Bit reserved for future use Bit reserved for future use 0dB 0.25dB 0.50dB 0.75dB 1.00dB 1.25dB 1.50dB 1.75dB 2.00dB 2.25dB 2.50dB 2.75dB 3.00dB 3.25dB 3.50dB 3.75dB 4.00dB 4.25dB 4.50dB 4.75dB 5.00dB 5.25dB 5.50dB 5.75dB 6.00dB 6.25dB 6.50dB 6.75dB 7.00dB 7.25dB 7.50dB 7.75dB 8.00dB 8.25dB 8.50dB
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Table 4. PCR-RX1 Gain (Continued)
D7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - D6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - D5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D4 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D3 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 HEX VALUE 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F BIT NAME RXPGA3[5:0] DESCRIPTION 8.75dB 9.00dB INVALID INVALID INVALID INVALID INVALID INVALID INVALID INVALID INVALID INVALID INVALID INVALID INVALID INVALID INVALID INVALID INVALID INVALID INVALID INVALID INVALID INVALID INVALID INVALID INVALID INVALID INVALID
NOTE 2: The formula to convert bit value to RXPGA3 gain in dB is RXPGA3 gain (in dB) = RXPGA3[5:0] (in decimal) x 0.25dB Similarly one can compute the RXPGA3 [5:0] bit combination needed, given the gain in dB.
CAUTION: Performance of the codec for invalid combination of bits is not guaranteed and such combinations should not be used. The user should make no assumption that the code bits will saturate to a maximum or minimum value or wrap around to a valid combination.
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PCR-RX2 - programmable gain control register 2 for RX channel PGA1 and PGA2
Address: 00011b D7 Reserved D6 Reserved Contents at reset: 00000000b D5 Reserved D4 RXPGA2[1] D3 RXPGA2[0] D2 RXPGA1[2] D1 RXPGA1[1] D0 RXPGA1[0]
Table 5. PCR-RX2 Gain
D7 R - - - - - - - - - - - - - - D6 - R - - - - - - - - - - - - - D5 - - R - - - - - - - - - - - - D4 - - - 0 0 1 1 - - - - - - - - D3 - - - 0 1 0 1 - - - - - - - - D2 - - - - - - - 0 0 0 0 1 1 1 1 D1 - - - - - - - 0 0 1 1 0 0 1 1 D0 - - - - - - - 0 1 0 1 0 1 0 1 HEX VALUE - - - 0x00 0x08 0x10 0x18 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 RXPGA1[2:0] BIT NAME Reserved Reserved Reserved RXPGA2[1:0] DESCRIPTION Bit reserved for future use Bit reserved for future use Bit reserved for future use 0dB 6dB 12dB 18dB 0dB 3dB 6dB 9dB 12dB INVALID INVALID INVALID
NOTES: 3. The formula to convert bit value to RXPGA2 gain in dB is RXPGA2 gain (in dB) = RXPGA2[1:0] (in decimal) x 6dB Similarly the needed RXPGA2[1:0] bit combination can be computed, given the gain in dB. 4. The formula to convert bit value to RXPGA1 gain in dB is RXPGA1 gain (in dB) = RXPGA1[2:0] (in decimal) x 3dB Similarly the needed RXPGA1[2:0] bit combination can be computed, given the gain in dB.
CAUTION: Performance of the codec for invalid combination of bits is not guaranteed and such combinations should not be used. The user should make no assumption that the code bits will saturate to a maximum or minimum value or wrap around to a valid combination.
PCR-TX - programmable attenuation control register for TX channel
Address: 00100b D7 Reserved D6 Reserved Contents at reset: 00000000b D5 Reserved D4 TXPAA[4] D3 TXPAA[3] D2 TXPAA[2] D1 TXPAA[1] D0 TXPAA[0]
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PCR-TX - programmable attenuation control register for TX channel (continued)
Table 6. PCR-TX Attenuation
D7 R - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - D6 - R - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - D5 - - R - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - D4 - - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D3 - - - 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 - - - 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D1 - - - 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D0 - - - 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 HEX VALUE - - - 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F BIT NAME Reserved Reserved Reserved TXPAA[4:0] DESCRIPTION Bit reserved for future use Bit reserved for future use Bit reserved for future use -0 dB -1 dB -2 dB -3 dB -4 dB -5 dB -6 dB -7 dB -8 dB -9 dB -10 dB -11 dB -12 dB -13 dB -14 dB -15 dB -16 dB -17 dB -18 dB -19 dB -20 dB -21 dB -22 dB -23 dB -24 dB INVALID INVALID INVALID INVALID INVALID INVALID INVALID
NOTE 5: The formula to convert bit value to TXPAA attenuation in dB is TXPAA attenuation (in dB) = TXPAA[4:0] (in decimal) x (-1)dB Similarly one can compute the TXPAA[4:0] bit combination needed, given the attenuation in dB.
CAUTION: Performance of the codec for invalid combination of bits is not guaranteed and such combinations should not be used. The user should make no assumption that the code bits will saturate to a maximum or minimum value or wrap around to a valid combination.
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EQR - equalizer slope and gain control register
Address: 00101b D7 Reserved D6 EQPGA[2] Contents at reset: 00000000b D5 EQPGA[1] D4 EQPGA[0] D3 Reserved D2 EQ[2] D1 EQ[1] D0 EQ[0]
Table 7. EQR Slope and Gain
D7 R - - - - - - - - - - - - - - - - - D6 - 0 0 0 0 1 1 1 1 - - - - - - - - - D5 - 0 0 1 1 0 0 1 1 - - - - - - - - - D4 - 0 1 0 1 0 1 0 1 - - - - - - - - - D3 - - - - - - - - - R - - - - - - - - D2 - - - - - - - - - - 0 0 0 0 1 1 1 1 D1 - - - - - - - - - - 0 0 1 1 0 0 1 1 D0 - - - - - - - - - - 0 1 0 1 0 1 0 1 HEX VALUE - 0x00 0x10 0x20 0x30 0x40 0x50 0x60 0x70 - 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 Reserved EQ[2:0] BIT NAME Reserved EQPGA[2:0] DESCRIPTION Bit reserved for future use 0dB 1dB 2dB 3dB 4dB 5dB 6dB INVALID Bit reserved for future use 0dB slope 5dB slope 10dB slope 15dB slope 20dB slope 25dB slope INVALID INVALID
NOTES: 6. The formula to convert bit value to EQPGA gain in dB is EQPGA gain (in dB) = EQPGA[2:0] (in decimal) x 1 dB Similarly one can compute the EQPGA[2:0] bit combination needed, given the gain in dB. 7. The formula to convert bit value to EQ slope in dB is EQ slope (in dB/MHz) =EQ[2:0] (in decimal) x 5 dB/MHz Similarly one can compute the EQ[2:0] bit combination needed, given the slope in dB/MHz.
CAUTION: Performance of the codec for invalid combination of bits is not guaranteed and such combinations should not be used. The user should make no assumption that the code bits will saturate to a maximum or minimum value or wrap around to a valid combination.
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VCR-M - VCXO DAC control register MSB
Address: 00110b D7 VCR-M[7] D6 VCR-M[6] Contents at reset: 00000000b D5 VCR-M[5] D4 VCR-M[4] D3 VCR-M[3] D2 VCR-M[2] D1 VCR-M[1] D0 VCR-M[0]
VCR-L - VCXO DAC control register LSB
Address: 00111b D7 0 D6 0 Contents at reset: 00000000b D5 0 D4 0 D3 VCR-L[3] D2 VCR-L[2] D1 VCR-L[1] D0 VCR-L[0]
Table 8 shows some representative analog outputs. Table 8. Representative Analog Outputs
OPERATION VCR-M[7:0] * 24 + VCR-L[3:0] HEX RESULT 0x800 0x801 ... 0xFFF 0x000 0x001 ... 0x7FE 0x7FF Where step-size, = (3/4095) V. ANALOG OUTPUT 0V V ... 2047V 2048V 2049V ... 4094V 4095V COMMENTS Min scale Just above min ... Just below mid Mid scale Just above mid ... Just below max Max scale
For example, if 0xAA7 is desired, VCR-M and VCR-L should be set to 0xAA and 0x07; if 0x539 is desired, VCR-M and VCR-L should be set to 0x53 and 0x09.
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GPR-C - GPIO I/O direction control register
Address: 01000b D7 GPIOC[7] D6 GPIOC[6] Contents at reset: 11111111b D5 GPIOC[5] D4 GPIOC[4] D3 GPIOC[3] D2 GPIOC[2] D1 GPIOC[1] D0 GPIOC[0]
Table 9. GPR-C Direction Control
D7 0 1 - - - - - - - - - - - - - - D6 - - 0 1 - - - - - - - - - - - - D5 - - - - 0 1 - - - - - - - - - - D4 - - - - - - 0 1 - - - - - - - - D3 - - - - - - - - 0 1 - - - - - - D2 - - - - - - - - - - 0 1 - - - - D1 - - - - - - - - - - - - 0 1 - - D0 - - - - - - - - - - - - - - 0 1 REG VALUE - 0x80 - 0x40 - 0x20 - 0x10 - 0x08 - 0x04 - 0x02 - 0x01 BIT NAME GPIOC[7] GPIOC[6] GPIOC[5] GPIOC[4] GPIOC[3] GPIOC[2] GPIOC[1] GPIOC[0] DESCRIPTION Configure GPIO 7 pin as output Configure GPIO 7 pin as input Configure GPIO 6 pin as output Configure GPIO 6 pin as input Configure GPIO 5 pin as output Configure GPIO 5 pin as input Configure GPIO 4 pin as output Configure GPIO 4 pin as input Configure GPIO 3 pin as output Configure GPIO 3 pin as input Configure GPIO 2 pin as output Configure GPIO 2 pin as input Configure GPIO 1 pin as output Configure GPIO 1 pin as input Configure GPIO 0 pin as output Configure GPIO 0 pin as input
NOTE 8: A particular GPIOC control bit configures direction for the corresponding GPIOD data bit.
GPR-D - GPIO data register
Address: 01001b D7 GPIOD[7] D6 GPIOD[6] Contents at reset: 00000000b D5 GPIOD[5] D4 GPIOD[4] D3 GPIOD[3] D2 GPIOD[2] D1 GPIOD[1] D0 GPIOD[0]
CAUTION: GPIOD[7:0] corresponds to pins GPIO7-GPIO0 respectively.
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AUXR - auxiliary amplifier enable register
Address: 01011b D7 Reserved D6 Reserved Contents at reset: 00000000b D5 Reserved D4 Reserved D3 AMP4EN D2 AMP3EN D1 AMP1EN D0 AMP2EN
Table 10. Auxiliary Amplifier-Control
D7 R - - - - - - - - - - - D6 - R - - - - - - - - - - D5 - - R - - - - - - - - - D4 - - - R - - - - - - - - D3 - - - - 0 1 - - - - - - D2 - - - - - - 0 1 - - - - D1 - - - - - - - - 0 1 - - D0 - - - - - - - - - - 0 1 REG VALUE - - - - - 0x08 - 0x04 - 0x02 - 0x01 BIT NAME Reserved Reserved Reserved Reserved AMP4EN AMP3EN AMP1EN AMP2EN DESCRIPTION Bit reserved for future use Bit reserved for future use Bit reserved for future use Bit reserved for future use Disable amplifier 4 Enable amplifier 4 Disable amplifier 3 Enable amplifier 3 Disable amplifier 1 Enable amplifier 1 Disable amplifier 2 Enable amplifier 2
CAUTION: Performance of the codec for invalid combination of bits is not guaranteed and such combinations should not be used. The default condition is with the amplifiers switched off.
NCO_DEF - numerically controlled oscillator default value register
Address: 01100b D7 Reserved D6 NCDEF[6] Contents at reset: 01000000b (64 decimal) D5 NCDEF[5] D4 NCDEF[4] D3 NCDEF[3] D2 NCDEF[2] D1 NCDEF[1] D0 NCDEF[0]
Table 11. NCO Default Value Table
D7 R - - - - - - - - D6 - 0 ... 0 0 ... 1 1 ... D5 - 0 ... 1 1 ... 0 0 ... D4 - 0 ... 0 1 ... 1 1 ... D3 - 0 ... 1 0 ... 1 1 ... D2 - 0 ... 1 0 ... 1 1 ... D1 - 0 ... 1 0 ... 0 1 ... D0 - 0 ... 1 0 ... 1 0 ... HEX VALUE - 0x00 0x01 - 0x2E 0x2F 0x30 0x31 - 0x5C 0x5D 0x5E 0x5F - 0xFF NCDEF[7:0] BIT NAME Reserved DESCRIPTION Bit reserved for future use Decimal 0, INVALID Decimal 1 to 46, INVALID Decimal 47, INVALID Decimal 48, INVALID Decimal 49 to 92, VALID Decimal 93, INVALID Decimal 94, INVALID Decimal 95 onwards, INVALID
CAUTION: The sum NCDEF[7:0] + NCDEL[3:0] should always be between 48 and 93. Out-of-bound values should not be used.
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NCO_DIV_DELAY - numerically controlled oscillator delay control register
Address: 01101b D7 NCDLY[7] D6 NCDLY[6] Contents at reset: 00000000b D5 NCDLY[5] D4 NCDLY[4] D3 NCDLY[3] D2 NCDLY[2] D1 NCDLY[1] D0 NCDLY[0]
Table 12. NCO Default Value
D7 0 0 0 D6 0 0 0 D5 0 0 0 D4 0 0 0 D3 0 0 0 D2 0 0 0 D1 0 0 1 D0 0 1 0 HEX VALUE 0x00 0x01 0x02 NCDLY[7:0] ... 1 1 ... 1 1 ... 1 1 ... 1 1 ... 1 1 ... 1 1 ... 1 1 ... 0 1 0x03 - 0xFD 0xFE 0xFF BIT NAME INVALID INVALID ADCLK jittered 2 sample clocks (of ADCLK) after write into the NCO_DIV_DELAY register (see Note 10) Jitter after 3 to 253 sample clocks (All individual values are valid) Jitter after 254 sample clocks Jitter after 255 sample clocks DESCRIPTION
NOTES: 9. The formula to convert NCDLY[7:0] to delay is straightforward. Delay (number of ADCLK periods) = NDCLK[7:0] (except for 0 and 1). 10. ADCLK-A/D converter sampling clock
CAUTION: This register is also the only means of communicating to the codec that the ADCLK must be jittered. Thus not writing a value implies that jitter will not take place even if other registers have non-default values. As a side consequence, this register does not remember its value. All the others store them unless RESET. Writing 0 or 1 is not recommended
examples: 1. NCDEF[7:0] = 64 (dec.), NCDEL[4:0] = 1, NCRPT[2:0] = 2, NCDLY[7:0] = 5. This shows a default division value of 64, giving a normal ADCLK of 2.208 MHz (assuming 35.328 MHz input); the division ratio will be 64 + 1 = 65 to effect the jitter, that is, pulling in the clock phase. The jitter will be repeated for 2 consecutive samples. The jitter will take effect 5 ADCLK sample periods after writing to NCDLY. 2. NCDEF[7:0] = 63 (decimal), NCDEL[4:0] = -1, NCRPT[2:0] = 2, NCDLY[7:0] = 5. Similar to 1. The default frequency is slightly less than 2.208 MHz. Since the division ratio is 63 - 1 = 62, the clock phase is pushed out. 3. NCDEF[7:0] = 64 (decimal), NCDEL[4:0] = 0, NCRPT[2:0] = 2, NCDLY[7:0] = 5. Here the jitter will not be observed, since the delta register is zero. 4. NCDEF[7:0] = 64 (decimal), NCDEL[4:0] = 1, NCRPT[2:0] = 0, NCDLY[7:0] = 5. Here the jitter will not be observed, since the repeat register is zero. 5. NCDEF[7:0] = 64 (decimal), NCDEL[4:0] = 1, NCRPT[2:0] = 2, NCDLY[7:0] = 0. This is invalid and not recommended. NCDLY[7:0] can not be 0 or 1. 6. NCDEF[7:0] = 64 (decimal), NCDEL[4:0] = 1, NCRPT[2:0] = 2. Here the jitter will not occur since there was not writing to NCDLY. The other registers will retain their values as in all other cases.
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NCO_DELTA - numerically controlled oscillator delta value register
Address: 01110b D7 NCDEL[3] D6 NCDEL[2] Contents at reset: 00000000b D5 NCDEL[1] D4 NCDEL[0] D3 NCRPT[3] D2 NCRPT[2] D1 NCRPT[1] D0 NCRPT[0]
Table 13. NCO_DELTA - DELTA and REPEAT
D7 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 - - - - - - - - - - - - - - - - D6 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 - - - - - - - - - - - - - - - - D5 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 - - - - - - - - - - - - - - - - D4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 - - - - - - - - - - - - - - - - D3 - - - - - - - - - - - - - - - - 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 - - - - - - - - - - - - - - - - 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D1 - - - - - - - - - - - - - - - - 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D0 - - - - - - - - - - - - - - - - 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 HEX VALUE 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F NCRPT[3:0] NCDEL[3:0] BIT NAME DESCRIPTION DELTA = 0 DELTA = 1 DELTA = 2 DELTA = 3 DELTA = 4 DELTA = 5 DELTA = 6 DELTA = 7 DELTA = -8 DELTA = -7 DELTA = -6 DELTA = -5 DELTA = -4 DELTA = -3 DELTA = -2 DELTA = -1 REPEAT = 0 (same as DELTA = 0) REPEAT =1 REPEAT =2 REPEAT =3 REPEAT =4 REPEAT =5 REPEAT =6 REPEAT =7 REPEAT =8 REPEAT =9 REPEAT =10 REPEAT =11 REPEAT =12 REPEAT =13 REPEAT =14 REPEAT =15
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MCR - master control register
Address: 01111b D7 GP12EN D6 DLBEN Contents at reset: 00000000b D5 ALBEN D4 SWRST D3 VCDACPD D2 RXPD D1 TXPD D0 SWREFPD
Table 14. MCR Control
D7 0 1 - - - - - - - - - - - - - - D6 - - 0 1 - - - - - - - - - - - - D5 - - - - 0 1 - - - - - - - - - - D4 - - - - - - 0 1 - - - - - - - - D3 - - - - - - - - 0 1 - - - - - - D2 - - - - - - - - - - 0 1 - - - - D1 - - - - - - - - - - - - 0 1 - - D0 - - - - - - - - - - - - - - 0 1 REG VALUE - 0x80 - 0x40 - 0x20 - 0x10 - 0x08 - 0x04 - 0x02 - 0x01 BIT NAME GP12EN DLBEN ALBEN SWRST VCDACPD RXPD TXPD SWREFPD DESCRIPTION No effect on SDX Show GPIO 1 and 2 in SDX primary. No effect on digital loop back Enable digital loop back No effect on analog loop back Enable analog loop back No effect on reset Perform soft reset Power up VCXODAC Power down VCXODAC Power up RX channel Power down RX channel Power up TX channel Power down TX channel Power up (soft) main reference Power down (soft) main reference
NOTES: 11. The SWRST and SWREFPD refer to the word software, since the reset is done by register programming as opposed to hard resets done by forcing pin logic levels. 12. Analog loop-back means looping back of the analog TX output to the RX input. This way the codec can be tested without need of external analog sources. 13. Digital loop-back means looping back the digital RX output to the TX input. Here we can test the code without the need for a DSP and serial data transfer.
CAUTION: All power downs of VCXODAC, RX, and TX channels occur with the reference still on.
DPLL detailed description
The default value of register NCO_DEF is 64. With the 35.328 MHz input clock, the output frequency of the PLL is 4 x 35.328 = 141.312 MHz. To obtain an ADC clock of 2.208 MHz the divide ratio (controlled by register NCO_DEF) needs to be 64. Increasing or decreasing this ratio (for example, 65 or 63) can effect a temporary phase shift. The ratio is controlled by the DSP through register programming. In DPLL mode, the ADC clock (ADCLK) will work at 2.208 MHz instead of the 4.416 MHz used in the VCXO mode. The DAC clock (DACLK) will continue to work at 4.416 MHz. When the ADCLK is jittered, the DACLK is also jittered.
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DPLL detailed description (continued)
MCLKIN/ PLLCLKIN PLL (X4) NCO_DEF NCO_DIV_DELAY CLOCK TO CONVERTER
+
NCO_DELTA [3:0]
NCO_DELTA [7:4]
Figure 7. DPLL Internal Function Block Diagram Example: Assume MCLKIN/PLLCLKIN=35.328 MHz. When NCO_DEF is programmed as 64, a 2.208 MHz clock is provided to the ADC converter according to the following formula: 35.328 x 4/64 = 2.208 If NCO_DELTA [7:4] is set to -1, NCO_DELTA [3:0] is set to 3, and NCO_DIV_DELAY is set to 2 (NCO_DIV_DELAY should be the last register to be programmed), register NCO_DEF will change to 63,63,63,64 at the beginning of the third sampling period. Each number (63 or 64) only last one clock (2.208 MHz) cycle. And the combination 63,63,63,64 occurs only once. Reprogramming of register NCO_DIV_DELAY is needed if further adjustment is required. Figure 7 shows the timing of SCLK with the following setting: NCO_DELTA [7:4] = 1 (Delta) NCO_DELTA [3:0] = 1 (Repeat) NCO_DIV_DELAY = 2 (Delay) Also note that in DPLL mode, the ADC clock will work at 2.208 MHz, 2 times oversampled, (instead of 4.416 MHz used in the VCXO mode) and the DAC clock will continue to work at 4.416 MHz.
16/35.328 MHz 16 SCLKs SCLK 21 ns 21 ns 16/35.328 MHz 16 SCLKs 16/35.328 MHz+1/(4*35.328 MHz) 16 SCLKs 16/35.328 MHz 16 SCLKs
ADCLK NCO_DIV_DELAY is Programmed by DSP Start Counting 1 ADCLK Over 2 ADCLK Over Jitter is Done
Figure 8. ADCLK Jitter Example
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TLFD500PN 3.3 V INTEGRATED G.LITE ANALOG FRONT END
SLAS207B - JUNE 1999 - REVISED MAY 2000
DPLL detailed description (continued)
To prevent variation in the serial clock width (SCLK) due to jitter, the serial clock is modified to have a fixed high level of 14 ns and a low level of 7 ns, thus resulting in a period of 21 ns. The average clock frequency is still 35.328 MHz. After the 16 SCLKs are complete, the clock goes quiet (no toggle zone) until the rising edge of the next ADCLK. The length of the no-toggle zone varies with the ADCLK. Figure 9 illustrates an example.
14 ns SCLK 35.328 MHz 7 ns 1/35.328 MHz ADCLK 2.208 MHz
DACLK 4.416 MHz
Figure 9. Relation of SCLK With ADCLK/DACLK in DPLL Mode
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage, AVDD to AGND, DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 4.5 V Analog input voltage range to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to AVDD+0.3 V Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to DVDD+0.3 V Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40C to 150C Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40C to 85C Storage temperature range, Tstr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
power supply
MIN Supply voltage AVDD_RX, AVDD_TX, AVDD_REF DVDD, DVDD_IO, DVDD_RX 3 3 NOM 3.3 3.3 MAX 3.6 3.6 UNIT V
digital inputs
MIN High-level input voltage, VIH Low-level input voltage, VIL Digital power supply = 3.3 V 33 2.4 0.6 NOM MAX UNIT V
analog input
MIN Analog input signal range AVDD_RX = 3.3 V, The input signal is measured single ended. AVDD_RX = 3.3 V, The input signal is measured differentially. NOM AVDD_RX/20.75 3 MAX UNIT V Vp-p
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TLFD500PN 3.3 V INTEGRATED G.LITE ANALOG FRONT END
SLAS207B - JUNE 1999 - REVISED MAY 2000
recommended operating conditions (continued)
clock
MIN Input clock frequency Input clock duty cycle NOM 35.328 50% MAX UNIT MHz
electrical characteristics over recommended operating free-air temperature range, fMCLKIN = 35.328 MHz, AVDD_RX/AVDD_TX/AVDD_REF = 3.3 V, DVDD = DVDD_IO = DVDD_RX = 3.3 V, (unless otherwise noted)
TX channel (measured differentially)
PARAMETER Gain error PAA step gain error DC offset Cross-talk Idle channel noise Group delay Power supply rejection ratio (PSRR) Analog output voltage AC Performance SNR THD TSNR MT Signal-to-noise ratio Total harmonic distortion ratio Signal-to-noise + harmonic distortion ratio 30.1875 kHz Missing-tone test (see Note 15) 81.9375 kHz 129.375 kHz Channel Frequency Response (Refer to Figure 13) 30 kHz Filter gain relative to gain at 77.625 kHz Pass-band (ripple) 180 kHz -1.5 -1 -70 1.5 1 dB 70 kHz at -1 dB (see Note 14) 70 75 68 -71 -71 -71 dB dB dB dB 200 mVp-p at 75 kHz Load = 2000 RX to TX channel TEST CONDITIONS MIN -1.5 0.25 50 -70 65 30 70 3 100 TYP MAX 1.5 UNIT dB dB mV dB Vrms s dB Vp-p
NOTES: 14. The input signal is the digital equivalent of a sine wave (digital full scale = 0 dB). The normal differential output with this input condition is 3 Vpp. 15. 27 tones, 25.875 to 138 kHz, 4.3125 kHz/step, 0 dB
reference outputs
MIN REFP REFM TXBANDGAP RXBANDGAP VMID_RX AVDD_REF = 3.3 V 2.2 0.3 1.4 1.4 NOM 2.5 0.5 1.5 1.5 1.5 MAX 2.8 0.7 1.6 1.6 UNIT V V V V V
digital outputs
MIN VOH VOL High-level output voltage Low-level output voltage IOH = 2 mA IOL = -2 mA 2.4 0.6 NOM MAX UNIT V
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TLFD500PN 3.3 V INTEGRATED G.LITE ANALOG FRONT END
SLAS207B - JUNE 1999 - REVISED MAY 2000
electrical characteristics over recommended operating free-air temperature range, fMCLKIN = 35.328 MHz, AVDD_RX/AVDD_TX/AVDD_REF = 3.3 V, DVDD = DVDD_IO = DVDD_RX = 3.3 V, (unless otherwise noted) (continued)
RX channel (measured differentially)
PARAMETER Gain error PGA 1 (0 to 12 dB in 3-dB steps) PGA step gain error DC offset Cross-talk Group delay Idle-channel noise Common-mode rejection ratio (CMRR) Power supply rejection ratio (PSRR) Analog input self-bias dc voltage RXINP/M Input impedance AC Performance SNR THD TSNR MT Signal-to-noise ratio Total harmonic distortion ratio Signal-to-noise + harmonic distortion ratio 163.875 kHz Missing-tone test (see Note 17) 301.875 kHz 508.875 kHz Channel Frequency Response (EQ[2:0] = 0 dB/MHz) (Refer to Figures 15 and 16) 180 kHz Filter gain relative to gain at 276 kHz Pass-band (ripple) 800 kHz NOTES: 16. The analog input test signal is a sine wave with 0 dB = 3 Vp-p as the reference level. 17. 123 tones, 25.875 kHz to 552 kHz, 4.3125 kHz/step, -6 dB. -1.5 -1 -25 1.5 1 dB 270 kHz at -1 dB (see Note 16) 72 82 72 -57 -57 -57 dB dB HPF1INP/M HPF2INP/M 200 mVp-p at 75 kHz TX to RX channel PGA 2 (0 to 18 dB in 6-dB steps) PGA 3 (0 to 9 dB in 0.25-dB steps) TEST CONDITIONS MIN -1.5 1 1 0.15 50 -55 25 100 70 70 1.5 7 70 70 100 mV dB s Vrms dB dB V k pF pF dB TYP MAX 1.5 UNIT dB
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TLFD500PN 3.3 V INTEGRATED G.LITE ANALOG FRONT END
SLAS207B - JUNE 1999 - REVISED MAY 2000
electrical characteristics over recommended operating free-air temperature range, fMCLKIN = 35.328 MHz, AVDD_RX/AVDD_TX/AVDD_REF = 3.3 V, DVDD = DVDD_IO = DVDD_RX = 3.3 V, (unless otherwise noted) (continued)
VCXO DAC
PARAMETER Resolution DNL INL Differential nonlinearity Integral nonlinearity Monotonicity Channel gain error Offset error Analog Output Full scale output voltage Output load Load = 50 k, VDD = 3.3 V 3 50 V k -100 100 TEST CONDITIONS MIN TYP 12 1 4 12 MAX UNIT Bits LSB LSB Bits dB mV
power dissipation
MIN Active mode Hardware power down Power dissipation Power-down Power down mode TX only Software power down RX only TX + RX + Reference mW TYP 700 50 MAX 850 100 UNIT mW
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TLFD500PN 3.3 V INTEGRATED G.LITE ANALOG FRONT END
SLAS207B - JUNE 1999 - REVISED MAY 2000
timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
serial port (see Figures 7 and 8) and DGPO (see Figure 9)
PARAMETER tc1 td1 td2 td3 td4 td5 td6 tf th1 tr tsu1 Period, SCLK Delay time, FSR high before SCLK Delay time, FSR high after SCLK Delay time, FSX high before SCLK Delay time, FSX high after SCLK Delay time, SDX data valid after SCLK Delay time, GPIO becomes valid after data is sent Falling time, SCLK change from high to low Hold time, SDR keep valid after SCLK Rising time, SCLK change from low to high Setup time, SDR valid before SCLK tc1 SCLK (Output) td1 FSR (Output) tsu1 SDR (Input) D15 th1 D14 D13 D12 D11 td2 tf tr 6 2 4.6 7 7 7 7 7 7 4.4 MIN TYP 28.3 MAX UNIT ns ns ns ns ns ns ns ns ns ns ns
Figure 10. Data Transfers From DSP to TLFD500PN
SCLK (Output) td3 FSX (Output) td5 SDX (Output) td4
Figure 11. Data Transfers From TLFD500PN to DSP
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SLAS207B - JUNE 1999 - REVISED MAY 2000
td6 = 7 ns
SCLK
GPIO
Valid Data
Figure 12. GPIO Bit-to-Pin Update Timing
TRANSMIT CHANNEL RESPONSE
50
0
Gain - dB
-50
-100
-150
-200 0 0.2 0.4 0.6 f - Frequency - MHz 0.8 1
Figure 13. Transfer Characteristic of the Transmit Filters (Complies with ITU G.992.2 PSD requirement)
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TLFD500PN 3.3 V INTEGRATED G.LITE ANALOG FRONT END
SLAS207B - JUNE 1999 - REVISED MAY 2000
TRANSMIT CHANNEL RESPONSE WITH HP FILTER BYPASSED
50
0
-50 Gain - dB -100 -150 -200 0 0.2 0.4 0.6 0.8 1 f - Frequency - MHz
Figure 14. Transfer Characteristic of the Transmit Filters With HP Filter Bypassed (Complies with ITU G.992.2 PSD requirement)
RECEIVE CHANNEL RESPONSE WITH DIFFERENT EQUALIZER SETTINGS
20 0 -20 -40 -60 -80 -100 -120 -140 -460 -180 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 f - Frequency - MHz
Figure 15. Transfer Characteristic of the Receive Filters (including out of band 0-1.6 MHz) (Complies with ITU G.992.2 PSD requirement)
Gain - dB
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TLFD500PN 3.3 V INTEGRATED G.LITE ANALOG FRONT END
SLAS207B - JUNE 1999 - REVISED MAY 2000
RECEIVE CHANNEL RESPONSE WITH DIFFERENT EQUALIZER SETTINGS
20
10
0
-10 Gain - dB
-20
-30
-40
-50
-60
0
0.1
0.2
0.3 f - Frequency - MHz
0.4
0.5
0.6
Figure 16. Transfer Characteristic of the Receive Filters (in-band 0-0.6 MHz) (Complies with ITU G.992.2 PSD requirement)
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TLFD500PN 3.3 V INTEGRATED G.LITE ANALOG FRONT END
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APPLICATION INFORMATION
To VCXO External clock Digital Interface to DSP
Digital Power Supply DVDD 31, 39 DVDD_RX 51 DVDD_IO 18 Digital Ground
VCXOCNTL 13
RESET 38
PWRDN 17 PLLSEL 42
GPIO0-GPIO7 23-30
DGPO 35
MCLKIN/PLLCLKIN 37
Output Signal
5 TXOUP 6 TXOUM 70 RXINP 71 RXINM
SCLK 19
SDR 20
75 HPF2OUTM 72 HPF2OUTP 73 HPF2INM 74 HPF2INP 76 HPF1OUTP 79 HPF1OUTM Input signal need to have AVDD_RX/2 common mode voltage 77 HPF1INM 78 HPF1INP 43 RXBANDGAP 14 TXBANDGAP 16 COMPDAC1 15 COMPDAC2 50 V MID_RX Analog Power Supply AVDD_REF 47 AVDD_RX 48 AVDD_RX 68 AVDD_TX 7 VSS 80 AVSS_REF 44 AVSS_RX 49 AVSS_RX 69 AVSS_TX 8 45 REFM 46 REFP Analog Ground
TLFD500PN
1.0 F
1.0 F
10 F
0.1 F
10 F
0.1 F
10 F
0.1 F
10 F
SDX 18
0.1 F
FSR 21
FSX 22
DVSS 34,40,41 DVSS_IO 33 DVSS_RX 52,54,57
10 F
0.1 F
Analog Power Supply
Analog Ground
Figure 17. Typical Application Circuit
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TLFD500PN 3.3 V INTEGRATED G.LITE ANALOG FRONT END
SLAS207B - JUNE 1999 - REVISED MAY 2000
MECHANICAL DATA
PN (S-PQFP-G80)
0,27 0,17 41
PLASTIC QUAD FLATPACK
0,50 60
0,08 M
61
40
80
0,13 NOM 21
1 9,50 TYP 12,20 SQ 11,80 14,20 SQ 13,80 1,45 1,35
20
Gage Plane
0,25 0,05 MIN 0- 7
0,75 0,45
Seating Plane 1,60 MAX 0,08 4040135 / B 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026
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Copyright (c) 2000, Texas Instruments Incorporated

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