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TLC976C 10-BIT, 20 MSPS, AREA CCD SIGNAL PROCESSOR
SLAS193 - OCTOBER 1998
D D D D D D D D D D D D D D D D D
Correlated Double Sampling (CDS), AGC and High Speed 10-Bit ADC in a Single Package 5-V Analog Power Supply and 3.3-V Digital Power Supply Power Down Mode 56-Pin TSSOP (DGG) Package with Multichip Module Assembly for Isolation
DGG PACKAGE (TOP VIEW)
CDS/AGC
AGC Gain Range of 5 dB to 39 dB Black Level Clamp Circuit Direct Connection to ADC Input Voltage Reference for ADC
Analog-to-Digital Converter
10-Bit Resolution Maximum Conversion Rate . . . 20 MSPS (MIN) Differential Nonlinearity . . . 0.75 LSB (TYP) Analog Input Voltage Range of 2 Vp-p 3.3 V CMOS Digital Interface
Applications
PC Camera Digital Camera Camcorder CCD Scanner
SHV GND1 BLK-PULSE OFFSET VCC3 DRIVE-OUT GND3 CDS-STBY VRB-OUT VRT-OUT A-SUB D-SUB DVSS D0 D1 D2 D3 D4 DVSS DVDD D5 D6 D7 D8 D9 RESET DVSS AVDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
SHR VCC1 CLP2 DATA-IN PIN AGCGAIN OBCLP AGCCLP SH-PULSE GND2 VCC2 A-SUB DVDD AVSS AVSS VIN D-SUB AVSS VRB-IN VRB-IN VRT-IN VRT-IN AVSS AVDD AVDD AD-STBY OE CLK
description
The TLC976 is a multichip module (MCM) subsystem designed for interfacing Charge-Coupled Device (CCD) in camcorder and digital camera systems. The TLC976 includes correlated double sampler (CDS), automatic gain control (AGC), black level clamp circuit, 10 bit, 20 MSPS analog-to-digital converter (ADC), and internal reference voltage generator for ADC. The CDS/AGC can be connected directly to the ADC input or a separate signal can be connected directly to the ADC input. A power-down mode is provided. Assembled using the MCM process, the TLC976 provides isolation between the noisy digital domain and the noise sensitive analog signals. The CDS/PGA, black level clamps are on one die and the ADC is on a separate die. The separate dies significantly reduce the substrate noise to the analog section. The TLC976 comes in a 56-pin TSSOP package with 0,50 mm pin pitch. This is about 25% smaller than using two separate 32-pin quad flat packs (QFP).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 1998, Texas Instruments Incorporated
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1
TLC976C 10-BIT, 20 MSPS, AREA CCD SIGNAL PROCESSOR
SLAS193 - OCTOBER 1998
functional block diagram
SHR SHV AGCGAIN AGCCLP OBCLP
AGCCLP SH-PULSE PIN SH SH LPF AGC DATA-IN SH CLP1 CLP2 CLP2 CDS-STBY OFFSET DRV DRIVE-OUT Auto Calibration Circuit D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Lower Data Latch Lower Data Latch Upper Data Latch Upper Data Latch Upper Sampling Comparators + DAC - Lower Sampling Comparators VRT-IN Reference Voltage VRB-IN Clock Generator CLK AD-STBY OE RESET SH BLK VRB VRT BLK-PULSE VRB-OUT VRT-OUT
S&H
VIN
2
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TLC976C 10-BIT, 20 MSPS, AREA CCD SIGNAL PROCESSOR
SLAS193 - OCTOBER 1998
Terminal Functions
TERMINAL NAME AD-STBY AGCCLP AGCGAIN A-SUB AVDD AVSS BLK-PULSE CDS-STBY CLK CLP2 D0-D9 DATA-IN DRIVE-OUT D-SUB DVDD DVSS GND1 GND2 GND3 OBCLP OE OFFSET NO. 31 49 51 11, 45 28, 32, 33 34, 39, 42, 43 3 8 29 54 14-18, 21-25 53 6 12, 40 20, 44 13, 19, 27 2 47 7 50 30 4 I I I I I I I I O I O I/O I I I ADC standby mode L level in operation DESCRIPTION
H level in standby mode
AGC clamp capacitor (connect 0.1 F to GND) AGC gain control Analog GND ADC analog power supply Analog GND for ADC DRIVE-OUT terminal is clamped to 1.66 V internally when BLK-PULSE = L. CDS/AGC standby mode control L level in operation H level in standby mode CLK input for ADC CCD signal clamp control input Digital data output, D0 (pin 14): LSB, D9 (pin 25): MSB CCD signal input CDS/AGC output Analog GND ADC digital power supply Digital GND for ADC CDS/AGC analog GND CDS/AGC analog GND GND for CDS output circuit Control input for clamping optical black level after AGC ADC output enable L level in operation H level in Hi-Z DRIVE-OUT offset - 450 mV - 280 mV 550 mV
CDS/AGC output offset control: DC voltage at OFFSET pin 0V 0.5 V 3V CCD signal input
PIN RESET SHV SH-PULSE SHR VCC1 VCC2 VCC3 VIN VRB-OUT VRB-IN VRT-OUT VRT-IN
52 26 1 48 56 55 46 5 41 9 37, 38 10 35, 36
I I I I I
Reset for calibration circuit. Restart of startup calibration. CCD signal level sample clock input Sample and hold pulse input CCD reset level sample clock input CDS/AGC analog power supply CDS/AGC analog power supply CDS/AGC analog power supply
I O I O I
ADC analog signal input ADC bottom reference voltage output (1.5 V typ) Connect to VRB-OUT ADC top reference voltage output (3.5 V typ) Connect to VRT-OUT
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TLC976C 10-BIT, 20 MSPS, AREA CCD SIGNAL PROCESSOR
SLAS193 - OCTOBER 1998
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Analog supply voltage, VCC1, VCC2, VCC3, AVDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . - 0.4 V to 7 V Digital supply voltage, DVDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.4 V to 7 V Analog input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.4 V to AVCC1, 2,3 + 0.5 V Continuous total power dissipation (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1344 mW Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . 260C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltages are with respect to GND. 2. For operation above 25C free-air temperature, derate linearly at the rate of 10.75 mW/C.
recommended operating conditions
MIN Analog supply voltage, VCC1, VCC2, VCC3, AVDD ADC digital output supply voltage, DVDD Difference, AGND to DGND High-level input voltage Low-level input voltage ADC analog input voltage full scale range ADC CLK pulse width Operating temperature High level Low level 2 25 25 0 70 4.75 3 -100 2 0.8 NOM 5 3.3 MAX 5.25 3.6 100 UNIT V V mV V V V ns C
electrical characteristics over recommended operating junction temperature range, AVCC = VCC1-3 = 4.75 V, DVDD = 3.3 V, VRT = 3.5 V, VRB = 1.5 V, Fs = 20 MSPS, TA = 25C (unless otherwise noted)
total device
PARAMETER CDS/AGC supply current ADC supply current CDS/AGC standby current ADC standby current Digital supply Analog supply TEST CONDITIONS AGCGAIN = 0 V, STBY = 0 V NTSC ramp input CDS-STBY = High AD-STBY = HIGH, CDS STBY = HIGH, (VIN = VRT-IN = VRB-IN = Hi-Z) VRT = VRB = Open, MIN TYP 30 3 32 5.6 0.5 MAX 38 6 35 11 1 UNIT mA mA mA mA
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TLC976C 10-BIT, 20 MSPS, AREA CCD SIGNAL PROCESSOR
SLAS193 - OCTOBER 1998
electrical characteristics over recommended operating junction temperature range, AVCC = VCC1-3 = 4.75 V, DVDD = 3.3 V, VRT = 3.5 V, VRB = 1.5 V, Fs = 20 MSPS, TA = 25C (unless otherwise noted) (continued)
CDS input/AGC
PARAMETER Input signal clamp voltage Input current for SHR, SHV, CLP2 SHR SHV AGC gain High input Low input Minimum Maximum VIN = 3 V VIN = 0 V AGCGAIN = 0 V AGCGAIN = 3 V 34 5 37 TEST CONDITIONS MIN TYP 2.7 1 -1 7 39 1 -1 20 MAX UNIT V A A dB A A MHz
High-level input current, OBCLP, BLK pulse Low-level input current, OBCLP, BLK pulse CDS input clock frequency
driver output
PARAMETER Output offset voltage Internal black level Nominal signal voltage at DRIVE-OUT High Low TEST CONDITIONS OFFSET = 3 V OFFSET = 0 V - 0.35 1.36 MIN TYP 0.55 - 0.45 1.66 2 1.96 MAX 0.65 UNIT V V V Vp-p
reference voltage
PARAMETER VRT output voltage VRB output voltage TEST CONDITIONS 300 , AVDD = VCC1- 3 = 4.75 V VCC1 4 75 MIN 3.47 1.45 TYP 3.50 1.50 MAX 3.53 1.55 UNIT V V
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TLC976C 10-BIT, 20 MSPS, AREA CCD SIGNAL PROCESSOR
SLAS193 - OCTOBER 1998
electrical characteristics over recommended operating junction temperature range, AVCC = VCC1-3 = 4.75 V, DVDD = 3.3 V, VRT = 3.5 V, VRB = 1.5 V, Fs = 20 MSPS, TA = 25C (unless otherwise noted) (continued)
A/D converter
PARAMETER Integral non-linearity Differential non-linearity Analog input capacitance Reference voltage output current Reference voltage output impedance Zero scale offset error Full scale offset error High-level input current Low-level input current High-level output current Low-level output current High-level output voltage Low-level output voltage High-level output leakage current Low-level output leakage current Automatic starting calibration voltage DVDD = MAX, DVDD = MAX, OE = GND, VOH = DVDD - 0.5 V OE = GND, VOL = 0.4 V DVDD = 3 V - 5.25 V, DVDD = 3 V - 5.25 V, OE = DVDD, VOH = DVDD OE = DVDD, VOL = 0 V DVDD-DGND VRT-VRB VIH = DVDD VIL = 0 V DVDD = MIN, DVDD = MIN, IOH = 2 mA IOL = 1 mA DVDD = MAX, DVDD = MIN, 2.5 1 VDD- 0.7V 0.8 1 1 3 5 (VRT IN - VRB IN) TEST CONDITIONS Fs = 20 MSPS, VIN = 1.8 V - 3.8 V MIN TYP 1.5 0.75 10 6.5 300 20 20 10 10 MAX 2.5 1.25 UNIT LSB LSB pF mA mV mV A A mA mA V V A A V
A/D converter operating characteristics
PARAMETER Sampling rate Analog input bandwidth (- 3 dB) Data output, propagation delay Differential gain Differential phase Sampling delay time Signal to noise ratio Fin = 1 MHz CL = 20 pF NTSC 40 IRE mod ramp FS = 14 3 MSPS ramp, 14.3 15 1% 0.3 5 55 Degree ns dB TEST CONDITIONS VIN = 1.8 V - 3.8 V, Fin = 1 kHz ramp MIN 0.5 10 ns TYP MAX 20 UNIT MSPS MHz
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TLC976C 10-BIT, 20 MSPS, AREA CCD SIGNAL PROCESSOR
SLAS193 - OCTOBER 1998
TYPICAL CHARACTERISTICS
AGCGAIN vs VOLTAGE
45 40 35 AGCGAIN - dB 30 25 20 15 10 5 0 0 0.3 0.6 0.9 1.2 1.5 1.8 AGCGAIN - V 2.1 2.4 2.7 3
Figure 1. AGC Characteristics
OUTPUT OFFSET VOLTAGE vs OFFSET CONTROL VOLTAGE
0.6 0.5 0.4 DRIVE OUT Offset Voltage 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 0.5 1 1.5 2 2.5 Control Voltage at OFFSET Pin (V) 3
Figure 2. OFFSET IN Terminal Input/Output Characteristics
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TLC976C 10-BIT, 20 MSPS, AREA CCD SIGNAL PROCESSOR
SLAS193 - OCTOBER 1998
TYPICAL OPERATION
Optical Black Pixel Period CCD Reset Feedthrough CCD Reset Level CCD Signal Level CCD Input Dummy Black/Blanking Period Signal Period
SHR Input
SHV Input
2 s (typ)
CLP2 Input Optical Black Level 1.66 V
(Internal) AGC Output
Black Level
SH-Pulse (Input) OBCLP Input 1.66 V (Internal) BLK 10 s (typ)
BLK-PULSE (Input)
1.66 V
DRIVE-OUT (Output)
Figure 3. CCD Input Mode Timing Diagram
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TLC976C 10-BIT, 20 MSPS, AREA CCD SIGNAL PROCESSOR
SLAS193 - OCTOBER 1998
APPLICATION INFORMATION
AVDD
0.1 F 1 2 3 4 5 0.1 F 6 7 8 9 10 11 12 13 AGND 14 15 16 17 18 19 20 0.1 F 21 22 23 24 25 26 27 28 DGND DVSS AVDD AVSS AVDD AVDD DVSS DVDD A-SUB D-SUB DVSS GND2 VCC2 A-SUB DVDD AVSS AVSS D-SUB AVSS VCC3 GND3 GND1 VCC1 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 0.1 F 0.1 F
DVDD NOTE A: A-SUB and D-SUB should be connected to Analog GND.
Figure 4. Typical Connection Diagram Table 1. Standby, Output Enable
PIN 8 31 30 PIN NAME CDS-STBY AD-STBY OE FUNCTION Standby mode for CDS/AGC Standby mode for AD converter AD output OPERATION L L L STAND-BY OR DISABLE H H H
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TLC976C 10-BIT, 20 MSPS, AREA CCD SIGNAL PROCESSOR
SLAS193 - OCTOBER 1998
APPLICATION INFORMATION
0.1 F
AGCCLP SHR SHV AGCGAIN OBCLP
CCD-IN
1 F PIN SH DATA-IN 1 F CLP1 SH
AGCCLP SH-PULSE LPF AGC SH SH BLK BLK-PULSE VRB-OUT VRB VRT VRT-OUT
CLP2 CLP2 OFFSET-IN DRV
CDS-STBY
DRIVE-OUT Auto Calibration Circuit D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Reference Voltage VRB-IN AD-STBY OE Lower Data Latch DAC - Lower Data Latch Lower Sampling Comparators VRT-IN + (see Note A) Upper Data Latch Upper Data Latch RESET
Upper Sampling Comparators
S&H
VIN
(see Note A)
Clock Generator CLK
NOTE A: The 0.1 F capacitors are necessary when you need to protect the noise.
Figure 5. Typical Application
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TLC976C 10-BIT, 20 MSPS, AREA CCD SIGNAL PROCESSOR
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PRINCIPLES OF OPERATION CDS/AGC signal processor
The output from the CCD sensor is first fed to a correlated double sampler (CDS). The CCD signal is sampled and held during both the reset reference interval and the video signal interval. By subtracting two resulting voltage levels, the CDS removes low frequency noise from the output of the CCD sensor. Two sample/hold control pulses (SHR and SHV) are required to perform the CDS function. The CCD output is capacitively coupled to the TLC976. The AC coupling capacitor is clamped to establish proper dc bias during the dummy pixel interval by the CLP2 input. The bias at the input to the TLC976 is set to 2.7 V at VCC = 4.75 V. Normally, the CLP2 is applied at the sensor's line rate. The signal is sent to AGC after the CDS function is complete. The AGC gain can be adjusted from 5 dB to 39 dB by applying variable dc voltage from 0 V to 3 V at the AGCGAIN terminal. A low-pass filter is installed at the AGC output to improve signal-to-noise ratio. After its output settles, it is sampled and held by the SH-PULSE input for digitization. The SH-PULSE should synchronize with the ADC clock. The basic black level reference is established by clamping the AGC output to 1.66 V internally by the OBCLP input during the optical black pixel period. A capacitor of 0.1 F should be connected to the AGCCLP pin. To prevent the black level from falling below the basic black level (1.66 V) during the blanking period, the AGC output level is kept at 1.66 V by the BLK PULSE input. It is recommended that the BLK PULSE be kept low during the entire blanking period. The DRV block drives the ADC and adjusts the signal offset at the DRIVE OUT output. The offset can be adjusted from -450 mV to 550 mV by applying control voltage on the OFFSET pin. The VRT (3.5 V) and VRB (1.5 V) outputs provide voltage references for the ADC. They should be connected to the VRT-IN and VRB-IN input pins externally.
analog-to-digital converter (ADC)
The A/DC in the TLC976 performs high-speed analog-to-digital conversion with 10-bit resolution using semi-flash technique. The latency of the data output valid is 2.5 clocks. Table 2. ADC Output Code
INPUT VOLTAGE VRT * * * * * * * * * * VRB STEPS 0 * * * * 511 512 * * * * 1023 DIGITAL OUTPUT CODE MSB 1111111111 * * * * 1000000000 0111111111 * * * * 0000000000 LSB
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TLC976C 10-BIT, 20 MSPS, AREA CCD SIGNAL PROCESSOR
SLAS193 - OCTOBER 1998
PRINCIPLES OF OPERATION
twh twl
CLOCK N+2 INPUT SIGNAL N N+1
N+3
N+4
DATA OUTPUT
N-3
N-2
N-1
N
N+1
tpd
Figure 6. ADC Operation Sequence
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TLC976C 10-BIT, 20 MSPS, AREA CCD SIGNAL PROCESSOR
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PRINCIPLES OF OPERATION ADC internal calibration
start-up calibration at power up After power is turned on, the start-up calibration starts under the following conditions: 1. The voltage between VRT and VRB is over 1 V when the voltage between AVDD and AVSS is over 2.5 V. 2. The voltage between DVDD and DVSS is over 2.5 V. 3. The RESET terminal (pin 26) is high. 4. The AD-STBY terminal (pin 31) is low. The calibration sequence starts after condition 2 is met (see Figure 7). The following equation calculates the time required for the start-up calibration after the above conditions are met. Start-up calibration time = main clock pulse period x 16 x 16384 For example, if the main clock frequency is 15 MHz, the time required for startup calibration is 17.5 ms.
Reset = HIGH, AD-STBY = LOW
5V
AVDD VRT DVDD
2.5 V
1V
VRB
CALIBRATION START
Figure 7. Start-Up Calibration
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TLC976C 10-BIT, 20 MSPS, AREA CCD SIGNAL PROCESSOR
SLAS193 - OCTOBER 1998
PRINCIPLES OF OPERATION
start-up calibration using RESET terminal If start-up characteristics are not stable, the start-up calibration can be performed using the AD-STBY terminal (pin 31) or the RESET terminal (pin 26). Start-up calibration can be initiated properly by connecting RC components to the RESET pin as shown in Figure 8. The RC components delay the start-up until the supply voltage stablizes.
AVDD M AVDD R RESET 26 C VRB VRT RESET
AVSS (t)
Figure 8. Start-Up Calibration Using RESET Terminal
14
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TLC976C 10-BIT, 20 MSPS, AREA CCD SIGNAL PROCESSOR
SLAS193 - OCTOBER 1998
MECHANICAL DATA
DGG (R-PDSO-G**)
48 PIN SHOWN
PLASTIC SMALL-OUTLINE PACKAGE
0,50 48
0,27 0,17 25
0,08 M
6,20 6,00
8,30 7,90
0,15 NOM
Gage Plane 0,25 0- 8 A 0,75 0,50
1
24
Seating Plane 1,20 MAX 0,15 0,05 0,10
PINS ** DIM A MAX
48
56
64
12,60
14,10
17,10
A MIN
12,40
13,90
16,90 4040078 / F 12/97
NOTES: B. C. D. E.
All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold protrusion not to exceed 0,15. Falls within JEDEC MO-153
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Copyright (c) 1999, Texas Instruments Incorporated

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