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S i 3 2 2 5 P P T- E V B
EVALUATION B O A R D F O R T H E Si3225 DU A L PROS LIC
Description
This document describes the operation of the Silicon Laboratories Si3225 Dual ProSLICTM device evaluation platform. The Dual ProSLIC evaluation platform is designed to provide observation of the ProSLIC's functionality. The Dual ProSLIC platform consists of a ProSLIC motherboard, an Si3225 daughter card (Si3225DC0-EVB), and the ProSLIC LINCTM software. The ProSLIC LINC software is a GUI-based program that can run in Microsoft Windows(R) environments. Equipment requirements:
! ! ! ! ! ! !
Features
! ! ! ! ! ! ! ! ! !
PC running Windows 95, 98, ME, NT, or 2000 5 V, 1 A power supply 3 V, 1 A power supply (optional) -24 V, 0.5 A power supply -57 V, 0.5 A power supply External ringing source Balanced audio generator and analyzer (optional)
(e.g., Audio Precision System 2 and/or HP TIMS set and/or Wandel and Goltermann PCM-4)
Silicon Laboratories Dual ProSLIC device Stackable cards for up to 16 channels All components necessary for linecard implementation Ringing source connector, relay, and resistor Layout for optional secondary protections Control I/O through standard parallel port On-board oscillator for stand-alone operation PCM I/O set up for Audio Precision System 2 or Wandel and Goltermann PCM-4 Full access to PCM highway ProSLIC power selection (3 V or 5 V)
!
8 kHz PCM signal generator and analyzer (optional)
(e.g., Audio Precision System 2 and Audio Precision SIA-2322 and/or Wandel and Goltermann PCM-4)
Function Block Diagram
VBHI, VBLO, +3 V, +5 V Power In Parallel Port
PCM Transmit Si3225
Si3200
PCM Receive
Si3200
Si3225DC0-EVB
Rev. 1.0 4/03
Copyright (c) 2003 by Silicon Laboratories
SI3225PPT-EVB-10
SI3225PPT-EVB
ProSLIC LINC Evaluation Software
The ProSLIC LINC software is an executable program that allows control and monitoring of the ProSLIC. It utilizes the primary LPT port of a standard PC to communicate with the ProSLIC's SPI port. To install the software, insert the Silicon Laboratories ProSLIC CD into the computer. The setup routine can be invoked by running the setup.exe program in the root directory of the CD. Invoking the ProSLIC LINC is achieved by double clicking the ProSLIC LINC icon. Refer to the ProSLIC LINC User Guide for software operation. clock source or an external PCM clock source. The ProSLIC motherboard has been designed to directly connect to an Audio Precision SIA-2322 Serial Interface Adapter through the 15 pin d-connectors, P2 and P3. See Table 2 for the Audio Precision settings. The ProSLIC evaluation board has also been designed to interface with a Wandel and Goltermann PCM-4 through J8, J9, J10, and J11. See Table 3 for PCM-4 settings. A header, J5, allows access to the ProSLIC's PCM signals for connection to other PCM testing devices or an actual telephone system PCM bus. TIP and RING of the two-wire analog interface are present at the RJ-11 connectors, J1 and J11, of the Dual ProSLIC daughter card. The schematics of the ProSLIC motherboard are found in Figures 7, 8, and 9. Figure 7 shows the connections from the motherboard to the daughter card. Figure 8 illustrates the LPT port connection to the SPI drivers. The PCM highway and LED indicators are shown in Figure 9. The ProSLIC evaluation board is voltage-programmable with specific jumper settings. JP1 selects 3 V or 5 V ProSLIC operation. JP2 selects 3 V or 5 V PCM source level compatibility. These should be placed on the expected setting. Power is connected to the ProSLIC at J2, J3, and J4. 5 V is always required for the buffers, U2 and U3, to interface to the parallel port. The ProSLIC can be powered from 5 V or 3 V with the placement of a jumper on JP1. The Protection Return connections on J6 should be connected to an appropriate ground for TIP/RING fault testing. This return is tied to signal ground on-board though it has a dedicated trace for high-current conditions. Serial control of the ProSLIC is achieved by toggling select bits of a standard parallel port. The parallel port connection is available at P1 and J1. Multiple dual ProSLIC cards can be daisy-chained by stacking the cards. Stack up to eight cards by aligning JS1-JS5 and pressing together. The ProSLIC LINC Software allows channel selection for RAM and register manipulation.
SI3225PPT-EVB Dual ProSLIC Evaluation Board Description
The schematics for the Dual ProSLIC evaluation daughter card are shown in Figures 1 through 3. The schematic in Figure 1 shows the Dual ProSLIC linecard implementation. All circuitry pertaining to the telephony function of the Dual ProSLIC is found here. Figure 2 contains a number of options for secondary fault protection. Secondary protection components can be selected for a given level of protection against expected faults. Figure 3 illustrates the serial control interface, PCM interface, daisy chain ports, and power supply filtering and connections. These schematics represent typical linefeed components for the ProSLIC. The layout of the Dual ProSLIC evaluation daughter card is found in Figures 4, 5, and 6. Figure 4 shows the component placement while Figures 5 and 6 show the two layers of component interconnect. For optimum thermal performance of the Si3200, the daughter card has inner VDD and GND layers. These layers are omitted from the figures in this data sheet. The signal flow is digital PCM on the left to two-wire analog on the right. Signal requirements for ProSLIC operation are PCLK (PCM clock), FS (frame sync), and Serial IO. The ProSLIC motherboard has a local oscillator with a programmable logic device to provide the ProSLIC PCLK and FS signals. The DIP switch (S2) sets the PCLK frequency and controls the FS enable. See Table 1 for S2 settings. JP3 and JP4 select this internal
2
Rev. 1.0
SI3225PPT-EVB
SI3225PPT-EVB Dual ProSLIC Evaluation Platform Setup
To prepare the Dual ProSLIC evaluation platform for use, perform the following steps:
1. Set power supplies to 3.3 V, 5 V, -24 V, and -75 V. 2. Connect ringing source to J5. 3. With these supplies off, connect them to J2, J3, and J4 corresponding to the silk screen designators. 4. Connect the PC's parallel port (LPT1) to P1 (or J1) using a 25 pin D male-to-male cable. 5. Select the on-board PCM clock source or select external PCM source with JP3, JP4 and connect an Audio Precision SIA-2322 to P2 and P3 or a Wandel and Goltermann PCM-4 to J8, J9, J10, and J11. 6. TIP/RING connection can be made from the RJ-11s to a phone or telephony test equipment. 7. Invoke the ProSLIC LINC software. 8. Turn the power supplies on and press the ProSLIC motherboard reset button (S1). 9. Click the "Reinitialize" button in the ProSLIC LINC software panel.
The Dual ProSLIC is now ready to perform its linecard function. To achieve an end-to-end connection with 600 , perform the following steps:
1. Verify that R11 on the motherboard is shorted. 2. Click RESET. 3. Click REINITIALIZE. 4. Click REGISTER SET. 5. Click BROADCAST BOX. 6. Write "1" to LINEFEED REGISTER.
The evaluation platform is now connected end-to-end per daughter card RJ-11 connector pairs.
Table 1. On-Board PCLK Settings (S2)
S2-1,2,3 PCLK frequency 0,0,0 = 8.192 MHz 0,0,1 = 4.096 MHz 0,1,0 = 2.048 MHz 0,1,1 = 1.024 MHz 1,x,x = 512 kHz
Note: 1 = on.
S2-4 unused x
S2-5 unused x
S2-6 unused x
S2-7 unused x
S2-8 FS enable 0 = FS disabled 1 = FS enabled
Table 2. Audio Precision SIA-2322 DIP Switch Setting
Receiver Mode 10111001 00000110 01111101 01111001 1000001 Transmitter Mode 00000110 01111101 01111001
Note: 256 kHz PCLK and 8 kHz FS.
Table 3. Wandel and Goltermann PCM-4 Settings
General Configuration General Configuration General Configuration General Configuration General Configuration 2.14 3.13 4.13 7.12 7.22
For -law add the following:
Rev. 1.0
3
1
1
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
C3 10n 100V R8 R7 C5 1u 6V R10 C15 1u 6V R17 R18 182 182 1u 6V C16 40.2k 1u 6V C6 182 182 TP5 TP6 TP7 TP8 GNDGNDGNDGND
C4 10n 100V
STIPDCa STIPACa SRINGACa SRINGDCa ITIPNa IRINGNa ITIPPa VDD1 GND1 IRINGPa THERMa BLKRNG RTRPa TRD1a TRD2a BATSELa
1
1
1
1
R11 C11 R13 R14 R12 U3 TIPb 402k 4.7k 4.7k C12
402k J5 RR Db
1
1
Rev. 1.0
0.1u 100V X7R 0.1u 100V X7R VDD Protection TIPb_ext RINGb_ext RINGb
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
STIPDCb STIPACb SRINGACb SRINGDCb ITIPNb IRINGNb ITIPPb VDD2 GND2 IRINGPb THERMb RTRPb TRD1b TRD2b RRDb BATSELb
4
R21 RNGNGa VDD 510 U2 TIPa R9 806k VDD R6 R2 C2 R3 TRD1a R4 J3 TRD2a R1 402k 4.7k 4.7k J2 C1 402k 40.2k 806k R20 VRNGSOURCE Protection C30 0.1u 100V Si3200 C32 0.1u 100V
J1
TP1 Tip A
K1
2
3
TIPa_ext
4 9
RINGa_ext RINGa
6 5 4 3 2 1 1 2 3 4 5 6 7 8 TIP NC RING VBAT VBATH VBATL GND VDD GND epad ITIPP ITIPN THERM IRINGP IRINGN NC NC BATSEL 16 15 14 13 12 11 10 9
VDD
8
7
RJ-11 SMD
1
RR Da VBHI VBLO
10
DPDT
Ring A TP2 0.1u 100V X7R 0.1u 100V X7R
1 2
TRD1a
1 2
J4
TRD2a
SI3225PPT-EVB
U1
1 2
RRDa
R5
806k
RR Da /CS SDITHRU SDI SDO SCLK /INT PCLK DTX DRX FSYNC /RESET
C13 10n 100V R15 806k
C14 10n 100V
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SVBATa RPOa RPIa RNIa RNOa CAPPa CAPMa QGND IREF CAPMb CAPPb RNOb RNIb RPIb RPOb SVBATb
Si3225
RRDa /CS SDITHRU SDI SDO SCLK VDD4 GND4 /INT PCLK GND3 VDD3 DTX DRX FSYNC /RST
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
1 2
J6 TRD2b
RRDb
J11
1 2
J7 TRD1b
TRD2b
TP3 Tip B
K2
2
3
4 9
1 2
TRD1b
6 5 4 3 2 1 1 2 3 4 5 6 7 8 TIP NC RING VBAT VBATH VBATL GND VDD
R16 Si3200 VBLO
VDD
8
7
C31 0.1u 100V C33 0.1u 100V
RJ-11 SMD
1 epad
RR Db
10 GND
ITIPP ITIPN THERM IRINGP IRINGN NC NC BATSEL
16 15 14 13 12 11 10 9
40.2k
DPDT VBHI
Ring B TP4
R19 806k R22 RNGNGb 510 VRNGSOURCE
Figure 1. Si3225DC-EVB Evaluation Circuit (1 of 3)
RF1
1
F1250T RF3 TS600-170 RF5 TS250-130-RA L11A050AA TIPA
2
NI
NI
NI
TIPa_ext
RF7A D3 RV1
c
P0721SC
1 TIP VREF GND RING
NI B1161UC
NC 5 4
6
2 3 NC
c
D4 P0721SC VBHI
C36 0.1u 100V
RF7B RINGA L11A050AA RF6 RF11
RINGa_ext
NI
1
TS250-130-RA F1250T RF13 RF4 NI TS600-170 RF2 RF15 TS600-170
2
NI
NI
1
NI NI TIPb_ext RF17A D13
c
2
TS250-130-RA L11A030A F1250T
c
Rev. 1.0
D14 RF17B RINGb_ext NI L11A030A RF16 NI TS250-130-RA RF14 NI TS600-170 RF12
TIPB
RV2 P0721SC
1 2 3
VBHI P0721SC C37 0.1u 100V
TIP
NC VREF GND RING NC
NI B1161UC
6 5 4
RINGB
1
2
F1250T
Note 1: Choose desired protection scenario and do not install other components
SI3225PPT-EVB
Figure 2. Si3225DC-EVB Evaluation Circuit (protection) (2 of 3)
5
4 4 2 2
10 10 8 8 6 6 4 4 2 2
JS2 JS2 JP1 JP1
9 9 7 7 5 5 3 3 1 1
34 34 12 12
9 9 7 7 5 5 3 3 1 1
3 3 1 1
1 1 3 3
CONN SOCKET 5x2 CONN SOCKET 5x2
CONN SOCKET 2x2/SM CONN SOCKET 2x2/SM
12 12 34 34
CONN HEADER 2x2/SM CONN HEADER 2x2/SM (Farside) (Farside) SDITHRU SDITHRU SDI SDI
SI3225PPT-EVB
JS4 JS4 22 44 66 88 10 10 22 44 66 88 10 10 VBLO VBLO VBHI VBHI PCLK PCLK DRX DRX DTX DTX FSYNC FSYNC /RESET /RESET 11 33 55 77 99 CONN SOCKET 5x2 CONN SOCKET 5x2 11 33 55 77 99
VDD VDD SDO SDO SCLK SCLK /CS /CS /INT /INT
2 2 4 4
JS1 JS1
10 10 8 8 6 6 4 4 2 2
1 1 3 3 5 5 7 7 9 9
VDD VDD
2 2 4 4 6 6 8 8 10 10
2 2 4 4 6 6 8 8 10 10
Rev. 1.0
1 1 3 3 5 5 7 7 9 9
JS5 JS5 CONN SOCKET 5x2 CONN SOCKET 5x2 VBLO VBLO C22 C22 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u C23 C23 C24 C24 C25 C25 C34 C34 0.1u 0.1u 100V 100V
6
JS3 JS3 99 77 55 33 11 99 77 55 33 11 10 10 88 66 44 22 10 10 88 66 44 22 CONN SOCKET 5x2 CONN SOCKET 5x2 VRNGSOURCE VRNGSOURCE C35 C35 0.1u 0.1u 100V 100V
C20 C20
C21 C21
0.1u 0.1u
0.1u 0.1u
Figure 3. Si3225DC-EVB Evaluation Circuit (interconnect) (3 of 3)
SI3225PPT-EVB
Bill of Materials
Table 4. Si3225DC0-EVB Application Circuit
Component(s) C1, C2, C11, C12 C3, C4, C13, C14 C5, C15 C6, C16 C30, C31, C32, C33 C20-C25 R1, R2, R11, R12 R3, R4, R13, R14 R5, R15 R6, R16 R7, R8, R17, R18 R9, R19, R20 R10 RRING *Note: Example power rating. Value 100 nF, 100 V, X7R, 20% 10 nF, 100 V, X7R, 20% 1 F, 6.3 V, X7R, 20% 1 F, 6.3 V, X7R, 20% 0.1 F, 100 V, Y5V 0.1 F, 10 V, Y5V 402 k, 1/10 W, 1% 4.7 k, 1/10 W, 1% 806 k, 1/10 W, 1% 40.2 k, 1/10 W, 5% 182 , 1/10 W, 1% 806 k, 1/10 W, 1% 40.2 k, 1/10 W, 1% 510 , 2 W, 2%* Function Filter capacitors for TIP, RING ac sensing inputs. TIP/RING compensation capacitors. Low pass filter capacitors to stabilize common mode SLIC feedback loops. Low pass filter capacitors to stabilize differential SLIC feedback loops. Decoupling for battery voltage supply pins. Decoupling for analog and digital chip supply pins. Sense resistors for TIP and RING voltage sensing nodes. Sense resistors for TIP, RING ac sensing inputs. Sense resistor for battery voltage sensing nodes. Sets bias current for battery switching circuit. Bias resistors for internal transconductance amplifier. Sense registers for ringing generator feed. Generates a high accuracy reference current. Feed resistor for ringing generator source.
Table 5. Si3225DC0-EVB Protection Circuit
Component(s) D3, D4, D13, D14 RF1, RF2, RF11, RF12 RF3*, RF4*, RF13*, RF14* RF5*, RF6*, RF15*, RF16* RF7A*, RF7B*, RF17A*, RF17B* RV1, RV11 with C36, C37 Description Teccor P0721SC Sidactor Teccor F1250T, 250 V, 1.25 A, TeleLink(R) fuse Raychem TS600-170 Raychem TS250-130-RA MMC L11A050AA Teccor B1161UC Function/Comments Overvoltage protection Overcurrent protection Overcurrent protection PTC (optional) Overcurrent protection PTC (optional) Overcurrent protection resistor (optional) Overvoltage protection device (optional)
*Note: Not used on Si3225DC0-EVB. Usage depends on application.
Rev. 1.0
7
8
SI3225PPT-EVB
Rev. 1.0
Figure 4. Si3225DC-EVB Silkscreen
Rev. 1.0
SI3225PPT-EVB
Figure 5. Si3225DC-EVB Component Side
9
10
SI3225PPT-EVB
Rev. 1.0
Figure 6. Si3225DC-EVB Solder Side
4 2 10 8 6 4 2
JS1 JS2 JS3 CONN SOCKET 2x2
3 1 4 2 3 1
CONN SOCKET 5x2
9 7 5 3 1
9 7 5 3 1
10 8 6 4 2
+VIN VDD VBRNG
9 7 5 3 1
9 7 5 3 1
10 8 6 4 2
10 8 6 4 2 CONN SOCKET 5x2
JS4
SDI DIN TEST SDO SCLK /CS /INT DOUT
2 4 6 8 10 VBLO VBHI
1 3 5 7 9
2 4 6 8 10 PCLK DRX DTX FSYNC /RESET
1 3 5 7 9
1 3 5 7 9
VRNGSOURCE
1 3 5 7 9 2 4 6 8 10 2 4 6 8 10
Rev. 1.0
JS5 CONN SOCKET 5x2
CONN SOCKET 5x2
SI3225PPT-EVB
Figure 7. ProSLIC Motherboard (ProSLIC IF)
11
8 7 6 5
8 7 6 5
U1 200k S1 Reset Push Button 200k
8 7 6 5
1 2 3 4
1 2 3 4
1 2 3 4
8 7 6 5
8 7 6 5
1 2 3 4
1 2 3 4
Ringing Battery High Battery Low Battery
Common Common Common
+3V +5V +Vin
1 2 3
1 2 3
J2 +5V VBRNG VBHI +5V
J3
J4
1 2 3
VRNGSOURCE NC RNG Source Return
Protection Return Protection Return Protection Return
1 2 3
1 2 3
12
VDD R1 R2 R3 +5V P1 /RST /CS_IN SDI_IN SCLK_IN R6 C1 100 pF 0.1 uF 6Vmin D7 J1 /ACK BUSY PAPEREND SELECT U2 C2 DIN D5 D6 TEST_IN 470 OUT_EN TP D5 /RESET TEST /CS SDI DIN SCLK VDD 4245A D5 D6 D7 SCLK /RESET TEST /CS SDI DIN 13 14 15 16 17 18 19 20 21 22 23 24 GND B8 B7 B6 B5 B4 B3 B2 B1 OEB VCCB VCCB GND GND A8 A7 A6 A5 A4 A3 A2 A1 DIR VCCA 12 11 10 9 8 7 6 5 4 3 2 1 /STROBE /AUTOFD D0 ERROR D1 INIT D2 /SELECT D3 D4
SI3225PPT-EVB
TP D6
Two Package Widths
R7 R5 10k NI R4 10k
1 14 2 15 3 16 4 17 5 18 6 19 7 20 8 21 9 22 10 23 11 24 12 25 13 1 3 5 7 9 11 13 15 17 19 21 23 25 2 4 6 8 10 12 14 16 18 20 22 24 26 HEADER 13X2 Parallel Port Hdr DB25F Parallel port
DTX DOUT SDO /INT TEST
DTX DOUT SDO /INT TEST
13 14 15 16 17 18 19 20 21 22 23 24 GND B8 B7 B6 B5 B4 B3 B2 B1 OEB VCCB VCCB 4245A GND GND A8 A7 A6 A5 A4 A3 A2 A1 DIR VCCA
12 11 10 9 8 7 6 5 4 3 2 1
Rev. 1.0
Two Package Widths
CON3 CON3 CON3 +VIN VDD +3V JP1 VBLO CON3 J6 CON3 1 23 J5 C14 100uF 10Vmin VRNGSOURCE Single point connection to ground plane Zener 6.8V D2 EMI Filt L2 1 2 3 3V or 5V oper
SPARE DIGITAL OUT SDO_OUT /INT_OUT TEST _OUT
SDO_OUT
+5V
VDD
+3V
C3 0.1 uF 6Vmin 1-2 : 3V operation 2-3 : 5V operation
C4 0.1 uF 6Vmin
C5 0.1 uF 6Vmin
C6 0.1 uF 6Vmin
C7 0.1 uF 6Vmin
C8 0.1 uF 6Vmin
C9 0.1 uF 6Vmin
C10 0.1 uF 6Vmin
C11 0.1 uF 6Vmin
L1
3 21
EMI Filt
D1
C12
C13
Zener 6.8V
0.1 uF 6Vmin
100uF 10Vmin
Component Power Selection
Ringing Source Input
Figure 8. ProSLIC Motherboard (LPT to SPI)
+5V +5V +3V
VDD +5V
PCM bus
8 7 6 5
8 7 6 5
PCMVDD R8 330 JP2 C15 0.1 uF 6Vmin D4
1 2 3
1-2 : 3V 2-3 : 5V
R9 330
1 2 3 4
D3 +5V
/INT LED
SDO LED
/CS LED
SDI LED
PCLK LED
FSYNC LED
1 9 2 10 3 11 4 12 5 13 6 14 7 15 8
4 GND OUT 32.768MHz
12 34
5 INTFSYNC
EXTFSYNC JP6 EXTDRX FS
VCC VCC
U6 FPGA PLCC-44
EXTDRX
FS
/RESET
EXTPCLK JP3 JP5 INTPCLK EXTFSYNC
EXTDTX NI S2 DIP Switch
10 8 6 4 2
9 7 5 3 1
1-2: Int 2-3: Ext
1 2 3
12 11 10 9 8 7 6 5 4 3 2 1
GND GND A8 A7 A6 A5 A4 A3 A2 A1 DIR VCCA 4245A
EXTDRX INTDRX EXTDTX INTDTX EXTFSYNC INTFSYNC EXTPCLK INTPCLK
GND B8 B7 B6 B5 B4 B3 B2 B1 OEB VCCB VCCB
13 14 15 16 17 18 19 20 21 22 23 24
DRX FSYNC PCLK
Two Package Widths
R11 NI DTX/DRX loopback U4 PCK
1 9 2 10 3 11 4 12 5 13 6 14 7 15 8
GND GND
1 23
EXTPCLK C17
2 1
EXTDTX
8 7 6 5
External PCM
On-board PCM Clocks
SI3225PPT-EVB
Figure 9. ProSLIC Motherboard (PCM)
1 2 3 4
Rev. 1.0
NI CLK 11 35 33 SDO/IN1 Y0 Y1/RESET Y2/SCLK 24
DB15M To Audio Prec RX
P3
1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9
S1 S2 S3 S4 S5 S6 S7 S8
15 16 17 18 19 20 21 22 25 26 27 28 29 30 31 32 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31
37 38 39 40 41 42 43 44 3 4 5 6 7 8 9 10
1-2: Int 1 2 2-3: Ext 3
JP4 EXTPCLK
PCLK
12 34 56 78 9 10
To ProSLICs
} LED drive
J8
Omit Pin 5
J9
/CS LED SCLK LED /INT LED SDO LED SDI LED EXTDTX
/CS SCLK /INT SDO_OUT SDI DTX
EXTDRX +5V
EXTFSYNC
1 2 3 4 5 6 7 8 13 14 36 2 ispEN SDI/IN0 MODE/IN2 GOE0/IN3
J7 HEADER 8X1
12 11 10 9 8 7 6 5 4 3 2 1 TEST_IN D7 D7 C16 R10 10k 0.1 uF 6Vmin
GND GND A8 A7 A6 A5 A4 A3 A2 A1 DIR VCCA 4245A
GND B8 B7 B6 B5 B4 B3 B2 B1 OEB VCCB VCCB
13 14 15 16 17 18 19 20 21 22 23 24
J13 NI
Two Package Widths
J10
J11
0.01 uF 6Vmin
/RST LED
1 OE VDD
8
SCLK LED
DB15F To Audio Prec TX U5
P2
U3
1 2 3 4
13
SI3225PPT-EVB
Document Change List:
Revision 0.92 to Revision 1.0
!
"SI3225PPT-EVB Dual ProSLIC Evaluation Board Description" on page 2 updated. ! "SI3225PPT-EVB Dual ProSLIC Evaluation Platform Setup" on page 3 updated. ! Figures 1-6 updated.
14
Rev. 1.0
SI3225PPT-EVB
Notes:
Rev. 1.0
15
SI3225PPT-EVB
Contact Information
Silicon Laboratories Inc. 4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: productinfo@silabs.com Internet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories, Silicon Labs, ProSLIC, and LINC are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
16
Rev. 1.0

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