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PCI2050
PCI to PCI Bridge
Implementation Guide
August 2000
MSDS PCI
SCPU009
IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 2000, Texas Instruments Incorporated
Contents
Section
1 2 3 4
Title
Page
1-1 2-1 3-1 4-1 4-1 4-2 4-2 4-2 5-1 5-1 5-1 5-2 5-2 5-2 5-2 5-3 5-3
5
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI2050 Feature Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 Pullup Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 Power and Signal Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 Bypass Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4 Secondary Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 External Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 PCI Interrupts and IDSEL Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.1 CompactPCI Hot-Swap Mode . . . . . . . . . . . . . . . . . . . . . . . . 5.4 PCI Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 GPIO Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.1 Serial Clock Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6 Sample Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iii
List of Illustrations
Figure Title Page 5-1 External Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5-2 Serial Clock Mask Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
List of Tables
Table Title Page 3-1 208-Pin LQFP Signal Names Sorted by Terminal Number . . . . . . . . . . . . . . 3-1 4-1 Minimum and Typical PCI Pullup Resistor Values . . . . . . . . . . . . . . . . . . . . . 4-1 4-2 PCI2050 Pullups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4-3 Optional Pullups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4-4 Signals Which Could Be Hardwired to GND or 3.3 V . . . . . . . . . . . . . . . . . . . 4-2 4-5 VCC Combinations Based on Signaling Environment . . . . . . . . . . . . . . . . . . 4-2 4-6 PCI2050 Power Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 5-1 Interrupt Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5-2 Mode Select Terminals Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
iv
1 Introduction
This document is provided to assist platform developers who are using the PCI2050 PCI-to-PCI bridge controller. Chapter 2 is a list of the features of the PCI2050. Chapter 3 is a listing of the device terminals, with corresponding signal names for each terminal. Chapter 4 is the electrical guidelines. This chapter explains the pullup resistors and voltage level capacitors required for proper implementation of the PCI2050. The PCI specification requires all signals to be driven to a known level. This is accomplished with pullup resistors or by the PCI device. Some small capacitors are recommended on the power connections of the PCI2050. This is standard practice in board design to provide a stable supply voltage when large loads are placed on the system. Chapter 5 describes a number of functional considerations in implementing a PCI2050 solution, including proper use of an external arbiter with the PCI2050, an explanation of how PCI interrupts and IDSEL mappings interrelate, how to implement PCI hot-swap with the PCI2050, implementing PCI power management, and an an explanation of the GPIO interface.
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1-2
2 PCI2050 Feature Set
The PCI2050 provides the following features. * * * * * * * * * * * * * Supports PCI Local Bus Specification Revision 2.2 and PCI-PCI Bridge Specification 1.1 3.3-V core logic with universal PCI interfaces compatible with 3.3-V and 5.0-V PCI signaling environments Supports two 32-bit, 33-MHz PCI buses Provides internal arbitration for up to nine external secondary bus masters with programmable control Provides ten secondary PCI bus clock outputs Supports sustained pass-through bandwidth of 132 MBps Packaged in high technology 208-terminal LQFP or 209-terminal MicroStar BGATM package Support for PCI clock run on both buses External arbiter option Support for bus locking Support for CompactPCITM hot-swap Independent read and write buffers for each direction Provides VGA/palette decoding options
MicroStar BGA is a trademark of Texas Instruments. CompactPCI is a trademark of PICMG - PCI Industrial Computer Manufacturers Group, Inc. Other trademarks are the property of their respective owners.
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3 Terminal Assignments
Table 3-1. 208-Pin LQFP Signal Names Sorted by Terminal Number
PDV NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 GHK NO. D1 E3 F5 G6 E2 E1 F3 F2 G5 F1 H6 G3 G2 G1 H5 H3 H2 H1 J1 J2 J3 J5 J6 K1 K2 K3 K5 K6 L1 L2 L3 L6 L5 M1 M2 M3 M6 M5 N1 N2 N3 N6 P1 SIGNAL NAME VCC S_REQ1 S_REQ2 S_REQ3 S_REQ4 S_REQ5 S_REQ6 S_REQ7 S_REQ8 S_GNT0 S_GNT1 GND S_GNT2 S_GNT3 S_GNT4 S_GNT5 S_GNT6 S_GNT7 S_GNT8 GND S_CLK S_RST S_CFN HSSWITCH/GPIO3 GPIO2 VCC GPIO1 GPIO0 S_CLKOUT0 S_CLKOUT1 GND S_CLKOUT2 S_CLKOUT3 VCC S_CLKOUT4 S_CLKOUT5 GND S_CLKOUT6 S_CLKOUT7 VCC S_CLKOUT8 S_CLKOUT9 P_RST PDV NO. 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 GHK NO. P2 N5 P3 R1 P6 R2 P5 R3 T1 W4 U5 R6 P7 V5 W5 U6 V6 R7 W6 P8 U7 V7 W7 R8 U8 V8 W8 W9 V9 U9 R9 P9 W10 V10 U10 R10 P10 W11 V11 U11 P11 R11 W12 SIGNAL NAME BPCCE P_CLK P_GNT P_REQ GND P_AD31 P_AD30 VCC GND VCC GND P_AD29 VCC P_AD28 P_AD27 GND P_AD26 P_AD25 VCC P_AD24 P_C/BE3 P_IDSEL GND P_AD23 P_AD22 VCC P_AD21 P_AD20 GND P_AD19 P_AD18 VCC P_AD17 P_AD16 GND P_C/BE2 P_FRAME VCC P_IRDY P_TRDY P_DEVSEL P_STOP GND PDV NO. 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 GHK NO. V12 U12 P12 R12 W13 V13 U13 P13 W14 V14 R13 U14 W15 P14 V15 R14 U15 W16 T19 R17 P15 N14 R18 R19 P17 P18 N15 P19 M14 N17 N18 N19 M15 M17 M18 M19 L19 L18 L17 L15 L14 K19 K18 SIGNAL NAME P_LOCK P_PERR P_SERR P_PAR VCC P_C/BE1 P_AD15 GND P_AD14 P_AD13 VCC P_AD12 P_AD11 GND P_AD10 NC VCC GND VCC MS1 P_AD9 VCC P_AD8 P_C/BE0 GND P_AD7 P_AD6 VCC P_AD5 P_AD4 GND P_AD3 P_AD2 VCC P_AD1 P_AD0 GND P_VCCP NC MSK_IN HSENUM HSLED TDI PDV NO. 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 GHK NO. K17 K15 K14 J19 J18 J17 J14 J15 H19 H18 H17 H14 H15 G19 G18 G17 G14 F19 F18 G15 F17 E19 F14 E18 F15 E17 D19 A16 C15 E14 F13 B15 A15 C14 B14 E13 A14 F12 C13 B13 A13 E12 C12 SIGNAL NAME TDO VCC TMS TCLK TRST S_VCCP GND S_AD0 S_AD1 VCC S_AD2 S_AD3 GND S_AD4 S_AD5 VCC S_AD6 S_AD7 GND S_C/BE0 S_AD8 VCC S_AD9 S_M66ENA S_AD10 MS0 GND VCC GND S_AD11 GND S_AD12 S_AD13 VCC S_AD14 S_AD15 GND S_C/BE1 S_PAR S_SERR VCC S_PERR S_LOCK
3-1
Table 3-1. 208-Pin LQFP Signal Names Sorted by Terminal Number (continued)
PDV NO. 173 174 175 176 177 178 179 180 181 GHK NO. B12 A12 A11 B11 C11 E11 F11 A10 B10 SIGNAL NAME S_STOP GND S_DEVSEL S_TRDY S_IRDY VCC S_FRAME S_C/BE2 GND PDV NO. 182 183 184 185 186 187 188 189 190 GHK NO. C10 E10 F10 A9 B9 C9 F9 E9 A8 SIGNAL NAME S_AD16 S_AD17 VCC S_AD18 S_AD19 GND S_AD20 S_AD21 VCC PDV NO. 191 192 193 194 195 196 197 198 199 GHK NO. B8 C8 F8 E8 A7 B7 C7 F7 A6 SIGNAL NAME S_AD22 S_AD23 GND S_C/BE3 S_AD24 VCC S_AD25 S_AD26 GND PDV NO. 200 201 202 203 204 205 206 207 208 GHK NO. B6 E7 C6 A5 F6 B5 E6 C5 A4 SIGNAL NAME S_AD27 S_AD28 VCC S_AD29 S_AD30 GND S_AD31 S_REQ0 VCC
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4 Electrical Guidelines
4.1 Pullup Resistors
This discussion on PCI pullup requirements is taken from the PCI Local Bus Specification Rev 2.2, and is provided for reference in designing in the PCI2050. PCI control signals always require pullup resistors on the motherboard (NOT the expansion board) to ensure that they contain stable values when no agent is actively driving the bus. This includes, FRAME, TRDY, IRDY, DEVSEL, STOP, SERR, PERR, LOCK, INTA, INTB, INTC, INTD, and when used, REQ64, and ACK64. The point-to-point and shared 32-bit signals do not require pullups; bus parking ensures their stability. Table 4-1. Minimum and Typical PCI Pullup Resistor Values
SIGNALING RAIL 5.0 V 3.3 V RMIN 963 2.42 k RTYPICAL 2.7 k at 10% 8.2 k at 10% RMAX Dependent on number of loads. See equation 1. Dependent on number of loads. See equation 1.
Equation to calculate RMAX: R MAX + V CC(MIN) * V X Where: VX = 2.7 V for 5.0-V signaling and VX = 2.3 V for 3.3-V signaling. In addition to those specified by PCI, the table below contains both PCI control signals and other PCI2050 specific signals which should have pullup (keeper) resistors. Texas Instruments also recommends, when possible, that the signals be pulled up to 3.3 V to reduce leakage current. Table 4-2. PCI2050 Pullups
TERMINAL NO. TERMINAL NAME S_DEVSEL S_FRAME S_IRDY S_LOCK S_PERR S_REQ0 PDV 175 179 177 172 171 207 GHK A11 F11 C11 C12 E12 C5 TERMINAL NAME S_REQ1 S_REQ2 S_REQ3 S_REQ4 S_REQ5 S_REQ6 TERMINAL NO. PDV 2 3 4 5 6 7 GHK E3 F5 G6 E2 E1 F3 TERMINAL NAME S_REQ7 S_REQ8 S_RST S_SERR S_STOP S_TRDY TERMINAL NO. PDV 8 9 22 169 173 176 GHK F2 G5 J5 B13 B12 B11
num_loads
I IH
(1)
The signals in Table 4-3 may need pullups. The designer should refer to the section related to the signal to determine if a pullup resistor is necessary. Table 4-3. Optional Pullups
TERMINAL NO. TERMINAL NAME S_CFN HSENUM HS_SWITCH/GPIO3 PDV 23 127 24 GHK J6 L14 K1 REFER TO SECTION ON External arbiter cPCI hot swap cPCI hot swap GPIO interface TERMINAL NAME GPIO2 GPIO1 GPIO0 TERMINAL NO. PDV 25 27 28 GHK K2 K5 K6 REFER TO SECTION ON GPIO interface GPIO interface GPIO interface
The signals listed in Table 4-4 can be hardwired to GND or 3.3 V, if they are not going to be used in the design. Texas Instruments strongly recommends that all active-low signals listed in Table 4-4 be hardwired to 3.3 V. All other signals can be hardwired to GND or 3.3 V.
4-1
Table 4-4. Signals Which Could Be Hardwired to GND or 3.3 V
TERMINAL NO. TERMINAL NAME S_CFN S_REQ0 S_REQ1 S_REQ2 S_REQ3 PDV 23 207 2 3 4 GHK J6 C5 E3 F5 G6 TERMINAL NAME S_REQ4 S_REQ5 S_REQ6 S_REQ7 S_REQ8 TERMINAL NO. PDV 5 6 7 8 9 GHK E2 E1 F3 F2 G5 TERMINAL NAME HS_SWITCH/GPIO3 GPIO1 MSK_IN TERMINAL NO. PDV 24 27 126 GHK K1 K5 L15
4.2 Power and Signal Levels
The PCI2050 supports both 3.3-V and 5.0-V signaling environments. This is accomplished by the P_VCCP and S_VCCP clamping rails. These two rails are not power rails. They only clamp the signals at the rail voltage (3.3 V or 5.0 V). All I/O buffers are powered by the VCC rail. Because VCC powers both the core and the I/O buffers, it must always be at 3.3 V. The table below depicts the signaling combinations supported by the PCI2050 and the P_VCCP and S_VCCP voltages needed to operate in these signaling environments. Table 4-5. VCC Combinations Based on Signaling Environment
PRIMARY BUS SIGNALING ENVIRONMENT [V] 5.0 5.0 3.3 3.3 SECONDARY BUS SIGNALING ENVIRONMENT [V] 5.0 3.3 5.0 3.3 P_VCCP [V] 5.0 5.0 3.3 3.3 S_VCC [V] 5.0 3.3 5.0 3.3 VCC [V] 3.3 3.3 3.3 3.3
Table 4-6 contains the power measurements for the PCI2050. The measurements were taken under the following conditions: 33-MHz PCI bus clock, VCC = 3.3 V, P_VCCP = 5.0 V, and S_VCCP = 5.0 V. Table 4-6. PCI2050 Power Measurements
DEVICE STATE D0 D1 D2 D3Hot IVCC (mA) 55 50 15 15 IP_VCCP (A) 500 500 500 500 IS_VCCP (A) 500 500 500 500
4.3 Bypass Capacitors
Standard design rules for the supply bypass should be followed. Low-inductance ceramic-chip capacitors are best for bypass capacitors. A value of 0.1 F is recommended for each of the power supply terminals VCC, P_VCCP, and S_VCCP.
4.4 Secondary Clocks
The PCI2050 has ten secondary clocks based on the primary PCI clock. Each secondary clock can be enabled or disabled through the secondary clock control register located at PCI offset 68h. We suggest the configuration software or BIOS disable any clocks which are not in use to conserve power. When a secondary clock is disabled, the PCI2050 will drive the clock signal low, until the clock is reenabled. Texas Instruments also recommends the use of a 50- series terminator resistor to be connected to each secondary clock to reduce reflections.
4-2
The primary clock and the secondary clocks have the following relationships: * * * * They all operate at the same frequency. The maximum clock frequency is 33 MHz. The skew between P_CLK and S_CLKOUT0-S_CLKOUT9 has a range of 2.72 ns at 0C to 5.8 ns at 115C. The skew between secondary clocks is less than 0.1 ns with similar loading.
To ensure that the skew between the S_CLK input and the clock inputs to the secondary devices is minimized, the trace length between S_CLKOUT9 and S_CLK should match the trace length of the other S_CLKOUT traces. If one or more of the S_CLKOUT terminals is being routed to a socket, then the clock trace lengths to the built-on devices should be 2.5 inches longer than the clock traces to the sockets.
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5 Functional Considerations
5.1 External Arbiter
The PCI2050 allows an external arbiter to be used in place of the default internal arbiter. This function is controlled by S_CFN. In order to use an external arbiter with the PCI2050, S_CFN must be pulled up with a 10-k resistor or hardwired to 3.3 V. If an external arbiter is not going to be used (the PCI2050 internal arbiter will be used instead), then S_CFN must be hardwired to GND. When an external secondary bus arbiter is used, the PCI2050 internally reconfigures the S_REQ0 and S_GNT0 signals so that S_REQ0 becomes the secondary bus master grant for the bridge and the S_GNT0 becomes the secondary bus master request for the PCI2050. This is done because S_REQ0 is an input and can be used to provide the grant input to the bridge, and S_GNT0 is an output and can provide the request output from the bridge.
VCC PCI2050 S_CFN S_GNT0 S_REQ0 REQ GNT External Arbiter
Figure 5-1. External Arbiter When an external arbiter is used, all unused secondary bus grant outputs (S_GNT8-SGNT1) are in a high-impedance state. Any unused secondary bus request lines (S_REQ8-S_REQ1) should be pulled high or hardwired to 3.3 V, to prevent the inputs from oscillating.
5.2 PCI Interrupts and IDSEL Mapping
The PCI2050 can support up to nine devices on the secondary side. Each device IDSEL should be connected to a secondary address line (S_AD31-S_AD16). In order to reduce capacitive load on the secondary address line, the connection can be made through a 1-k series resistor. Because the PCI2050 is a bridge device, all parallel PCI interrupts on the secondary interface must be routed as sideband signals to the PCI interrupts on the primary interface. When using multiple devices behind the PCI2050, a device ID and how the PCI interrupts are routed should be very important considerations in a design. Some operating systems like Windows 95TM, expect a device PCI interrupt to be routed to a specific interrupt on the motherboard based on its ID number. For example, if a device ID is 4 and its PCI INTA is routed to PCI INTB on the motherboard, Windows 95TM will not configure the device properly. In order to reduce any chance of incompatibilities, we suggest the designer implement the interrupt routing scheme outlined in Section 2.2.6 of the PCI Local Bus Specification Revision 2.2. Table 5-1 summarizes Section 2.2.6.
Windows 95 is a trademark of Microsoft Corporation.
5-1
Table 5-1. Interrupt Routing
DEVICE NUMBER ON SECONDARY BUS INTERRUPT TERMINAL ON DEVICE INTA INTB INTC INTD INTA INTB INTC INTD INTA INTB INTC INTD INTA INTB INTC INTD INTERRUPT TERMINAL ON CONNECTOR INTA INTB INTC INTD INTB INTC INTD INTA INTC INTD INTA INTB INTD INTA INTB INTC
0, 4, 8, 16, 20, 24, 28
1, 5, 9, 13, 17, 21, 25, 29
2, 6, 10, 14, 18, 22, 26, 30
3, 7, 11, 15, 19, 23, 27, 31
5.3 Mode Selection
The PCI2050 can be programmed to operate in three separate modes: TI compact PCI mode, TI power management mode, and IntelTM 21150 compatible mode. Table 5-2 lists the mode-select-terminal logic values corresponding to each operating mode. Table 5-2. Mode Select Terminals Definition
MS0 0 0 1 MS1 0 1 X MODE TI hot-swap TI power management IntelTM 21150 compatible
5.3.1
CompactPCI Hot-Swap Mode
In CompactPCI hot-swap mode, the PCI2050 HS_SWITCH/GPIO3 and HSENUM must be pulled up to ensure the proper functionality of the hot-swap logic.
5.4 PCI Power Management
When using the PCI2050 in a power managed environment, it is important to remember that PME and 3.3 Vaux are sideband signals as far as the bridge is concerned. If any devices on the secondary bus need PME or 3.3 Vaux, these signals must be routed around the bridge.
5.5 GPIO Interface
The PCI2050 GPIO terminals default to inputs, after reset, and should be pulled up to prevent oscillation if this interface is not going to be used.
Intel is a trademark of Intel Corporation.
5-2
5.5.1
Serial Clock Mask
GPIO0 and GPIO2 provides the control signals to two external 74F166 shift registers to shift in the serial clock mask. If the external shift registers are not used, MSK_IN can be tied low to enable all secondary clocks, or tied high to disable all secondary clocks.
MSK_IN U1 74F166 Q7 2 3 4 5 10 11 12 5V 14 D0 D1 D2 D3 D4 D5 D6 D7 DS 1 U2 74F166 Q7 PRSNT0[0] PRSNT0[1] PRSNT1[0] PRSNT1[1] PRSNT2[0] PRSNT2[1] PRSNT3[0] PRSNT3[1] 2 3 4 5 10 11 12 14 D0 D1 D2 D3 D4 D5 D6 D7 DS 1 GND 8 74F166 CE CP MR PE 6 7 9 15 GPIO2 GPIO0 GND 8 74F166 CE CP MR PE 6 7 9 15 GPIO2 GPIO0 5V 13
VCC
16
13
VCC
16
Figure 5-2. Serial Clock Mask Circuit
5.6
Sample Schematics
For sample schematics, see the PCI2050 EVM Users Guide, (TI Literature Number SCPU005).
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