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PCI2250
PCI to PCI Bridge
Implementation Guide
2000
MSDS PCI
SCPU008
IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 2000, Texas Instruments Incorporated
Contents
Section
1 2 3 4
Title
Page
1-1 2-1 3-1 4-1 4-1 4-2 4-2 4-2 5-1 5-1 5-1 5-2 5-2 5-2 5-3 5-3 5-3
5
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI2250 Feature Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 Pullup Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 Power and Signal Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 Bypass Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4 Secondary Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 External Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 PCI Interrupts and IDSEL Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3 Multifunction Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.1 CompactPCI Hot-Swap Mode . . . . . . . . . . . . . . . . . . . . . . . . 5.3.2 Clock Run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.3 Intel 21152 Compatible Mode . . . . . . . . . . . . . . . . . . . . . . . . 5.4 Clock Run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 Sample Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iii
List of Illustrations
Figure Title Page 5-1 External Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
List of Tables
Table Title Page 3-1 176-Terminal LQFP Signal Names Sorted by Terminal Number . . . . . . . . . 3-1 3-2 160-Terminal PQFP Signal Names Sorted by Terminal Number . . . . . . . . . 3-2 4-1 Minimum and Typical PCI Pullup Resistor Values . . . . . . . . . . . . . . . . . . . . . 4-1 4-2 PCI2250 Pullups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4-3 Optional Pullups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4-4 Signals Which Could Be Hardwired to GND or 3.3 V . . . . . . . . . . . . . . . . . . . 4-2 4-5 VCC Combinations Based on Signaling Environment . . . . . . . . . . . . . . . . . . 4-2 4-6 PCI2250 Power Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 5-1 Interrupt Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5-2 Multifunction Terminal Definition Based on Mode Select Terminals . . . . . . . 5-2
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1 Introduction
This document is provided to assist platform developers who are using the PCI2250 PCI-to-PCI bridge controller. Chapter 2 is a list of the features of the PCI2250. Chapter 3 is a listing of the device terminals, with the corresponding signal names for each terminal. Chapter 4 is the electrical guidelines. This section explains pullup resistors and voltage level capacitors required for proper implementation of the PCI2250. The PCI specification requires all signals to be driven to a known level. This is accomplished with pullup resistors or by the PCI device. Some small capacitors are recommended on the power connections of the PCI2250. This is standard practice in board design to provide a stable supply voltage when large loads are placed on the system. Chapter 5 describes a number of functional considerations in implementing a PCI2050 solution, including proper use of an external arbiter with the PCI2250, how PCI interrupts and IDSEL mappings interrelate, how to implement clock run, lock, and cPCI hot-swap with the PCI2250, and implementing PCI power management.
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2 PCI2250 Feature Set
The PCI2250 provides the following features. * * * * * * * * * * * * * * * Supports PCI Local Bus Specification Revision 2.2 and PCI-PCI Bridge Specification 1.1 3.3-V core logic with universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling environments Supports two 32-bit, 33-MHz PCI buses Provides internal arbitration for up to four external secondary bus masters with programmable control Provides five secondary PCI bus clock outputs Supports sustained pass-through bandwidth of 132 MBps Packaged in high technology 176-terminal TQFP or 160-terminal PQFP Supports for PCI clock run on both buses External arbiter option Support for bus locking Support for CompactPCITM hot-swap Independent read and write buffers for each direction Secondary positive, negative, and subtractive decode Two extension windows Provides VGA/palette, memory, I/O, and subtractive decoding options
CompactPCI is a trademark of PCIMG - PCI Industrial Computer Manufacturers Group, Inc. Other trademarks are the property of their respective owners.
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3 Terminal Assignments
Table 3-1. 176-Terminal LQFP Signal Names Sorted by Terminal Number
NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 SIGNAL NAME GND NC S_PAR NC S_SERR S_PERR S_MFUNC S_STOP S_DEVSEL VCC S_TRDY S_IRDY S_FRAME GND S_C/BE2 S_AD16 VCC S_AD17 S_AD18 S_AD19 GND S_AD20 S_AD21 S_AD22 VCC S_AD23 S_C/BE3 S_AD24 GND S_AD25 S_AD26 VCC S_AD27 S_AD28 S_AD29 GND S_AD30 S_AD31 S_REQ0 S_REQ1 NC S_REQ2 NC VCC NO. 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 SIGNAL NAME GND NC S_REQ3 NC S_GNT0 S_GNT1 S_GNT2 VCC S_GNT3 S_RST S_CFN GND S_CLK S_VCCP S_CLKOUT0 GND S_CLKOUT1 VCC S_CLKOUT2 GND S_CLKOUT3 VCC S_CLKOUT4 NO/HSLED GOZ P_RST GND P_CLK P_VCCP P_GNT P_REQ P_AD32 GND P_AD30 P_AD29 P_AD28 VCC P_AD27 P_AD26 P_AD25 NC P_AD24 NC VCC NO. 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 SIGNAL NAME GND NC P_C/BE3 NC P_IDSEL P_AD23 P_AD22 GND P_AD21 P_AD20 P_AD19 VCC P_AD18 P_AD17 P_AD16 GND P_C/BE2 P_FRAME P_IRDY VCC P_TRDY P_DEVSEL P_STOP P_MFUNC GND P_PERR P_SERR P_PAR P_C/BE1 VCC P_AD15 P_AD14 P_AD13 GND P_AD12 P_AD11 P_AD10 VCC P_AD9 P_AD8 NC GND NC MSO NO. 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 SIGNAL NAME GND NC P_C/BE0 NC P_AD7 P_AD6 VCC P_AD5 P_AD4 GND P_AD3 P_AD2 VCC P_AD1 P_AD0 S_AD0 GND S_AD1 S_AD2 S_AD3 VCC S_AD4 S_AD5 S_AD6 GND S_AD7 S_C/BE0 S_AD8 VCC S_AD9 S_AD10 S_AD11 GND S_AD12 S_AD13 VCC S_AD14 S_AD15 GND S_C/BE1 NC MS1/BPCC NC VCC
3-1
Table 3-2. 160-Terminal PQFP Signal Names Sorted by Terminal Number
NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 SIGNAL NAME GND S_PAR S_SERR S_PERR S_MFUNC S_STOP S_DEVSEL VCC S_TRDY S_IRDY S_FRAME GND S_C/BE2 S_AD16 VCC S_AD17 S_AD18 S_AD19 GND S_AD20 S_AD21 S_AD22 VCC S_AD23 S_C/BE3 S_AD24 GND S_AD25 S_AD26 VCC S_AD27 S_AD28 S_AD29 GND S_AD30 S_AD31 S_REQ0 S_REQ1 S_REQ2 VCC NO. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 SIGNAL NAME GND S_REQ3 S_GNT0 S_GNT1 S_GNT2 VCC S_GNT3 S_RST S_CFN GND S_CLK S_VCCP S_CLKOUT0 GND S_CLKOUT1 VCC S_CLKOUT2 GND S_CLKOUT3 VCC S_CLKOUT4 NO/HSLED GOZ P_RST GND P_CLK P_VCCP P_GNT P_REQ P_AD32 GND P_AD30 P_AD29 P_AD28 VCC P_AD27 P_AD26 P_AD25 P_AD24 VCC NO. 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 SIGNAL NAME GND P_C/BE3 P_IDSEL P_AD23 P_AD22 GND P_AD21 P_AD20 P_AD19 VCC P_AD18 P_AD17 P_AD16 GND P_C/BE2 P_FRAME P_IRDY VCC P_TRDY P_DEVSEL P_STOP P_MFUNC GND P_PERR P_SERR P_PAR P_C/BE1 VCC P_AD15 P_AD14 P_AD13 GND P_AD12 P_AD11 P_AD10 VCC P_AD9 P_AD8 GND MSO NO. 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 SIGNAL NAME GND P_C/BE0 P_AD7 P_AD6 VCC P_AD5 P_AD4 GND P_AD3 P_AD2 VCC P_AD1 P_AD0 S_AD0 GND S_AD1 S_AD2 S_AD3 VCC S_AD4 S_AD5 S_AD6 GND S_AD7 S_C/BE0 S_AD8 VCC S_AD9 S_AD10 S_AD11 GND S_AD12 S_AD13 VCC S_AD14 S_AD15 GND S_C/BE1 MS1/BPCC VCC
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4 Electrical Guidelines
4.1 Pullup Resistors
This discussion on PCI pullup requirements is taken from the PCI Local Bus Specification Rev 2.2, and is provided for reference in designing in the PCI2250. PCI control signals always require pullup resistors on the motherboard (NOT the expansion board) to ensure that they contain stable values when no agent is actively driving the bus. This includes, FRAME, TRDY, IRDY, DEVSEL, STOP, SERR, PERR, LOCK, INTD, INTC, INTB, INTA, and when used, REQ64, and ACK64. The point-to-point and shared 32-bit signals do not require pullups; bus parking ensures their stability. Table 4-1. Minimum and Typical PCI Pullup Resistor Values
SIGNALING RAIL 5.0 V 3.3 V RMIN 963 W 2.42 kW RTYPICAL 2.7 k at 10% 8.2 k at 10% RMAX Dependent on number of loads. See equation 1. Dependent on number of loads. See equation 1.
Equation to calculate RMAX: R MAX + V CC(MIN) * V X Where: VX = 2.7 V for 5.0-V signaling and VX = 2.3 V for 3.3-V signaling. In addition to those specified by PCI, the table below contains both PCI control signals and other PCI2250 specific signals which should have pullup (keeper) resistors. Texas Instruments also recommends, when possible, that the signals be pulled up to 3.3 V to reduce leakage current. Table 4-2. PCI2250 Pullups
160 PQFP TERMINAL NO. 7 11 10 4 37 38 176 LQFP TERMINAL NO. 9 13 12 6 39 40 TERMINAL NAME S_DEVSEL S_FRAME S_IRDY S_PERR S_REQ0 S_REQ1 160 PQFP TERMINAL NO. 39 42 48 3 6 9 176 LQFP TERMINAL NO. 42 47 54 5 8 11 TERMINAL NAME S_REQ2 S_REQ3 S_RST S_SERR S_STOP S_TRDY
num_loads
I IH
(1)
The signals in Table 4-3 may need pullups. The designer should refer to the section related to the signal to determine if a pullup resistor is necessary. Table 4-3. Optional Pullups
160 PQFP TERMINAL NO. 63 102 49 5 176 LQFP TERMINAL NO. 69 112 55 7 TERMINAL NAME GOZ P_MFUNC S_CFN S_MFUNC REFER TO SECTION ON N/A Multifunction terminals External arbiter Multifunction terminals
The signals listed in Table 4-4 can be hardwired to GND or 3.3 V, if they are not going to be used in the design. Texas Instruments strongly recommends that all active-low signals listed in Table 4-4, be hardwired to 3.3 V. All other signals can be hardwired to GND or 3.3 V.
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Table 4-4. Signals Which Could Be Hardwired to GND or 3.3 V
160 PQFP TERMINAL NO. 63 37 38 176 LQFP TERMINAL NO. 69 39 40 TERMINAL NAME GOZ S_REQ0 S_REQ1 160 PQFP TERMINAL NO. 39 42 176 LQFP TERMINAL NO. 42 47 TERMINAL NAME S_REQ2 S_REQ3
4.2 Power and Signal Levels
The PCI2250 supports both 3.3-V and 5.0-V signaling environments. This is accomplished by the P_VCCP and S_VCCP clamping rails. These two rails are not power rails. They only clamp the signals at the rail voltage (3.3 V or 5 V). All I/O buffers are powered by the VCC rail. Because VCC powers both the core and the I/O buffers, it must always be at 3.3 V. The table below depicts the signaling combinations supported by the PCI2250 and the P_VCCP and S_VCCP voltages needed to operate in these signaling environments. Table 4-5. VCC Combinations Based on Signaling Environment
PRIMARY BUS SIGNALING ENVIRONMENT [V] 5 5 3.3 3.3 SECONDARY BUS SIGNALING ENVIRONMENT [V] 5 3.3 5 3.3 P_VCCP [V] 5 5 3.3 3.3 S_VCC [V] 5 3.3 5 3.3 VCC [V] 3.3 3.3 3.3 3.3
Table 4-6 contains the power measurements for the PCI2250. The measurements were taken under the following conditions: 33-MHz PCI bus clock, VCC = 3.3 V, P_VCCP = 5.0 V, and S_VCCP = 5.0 V. Table 4-6. PCI2250 Power Measurements
DEVICE STATE D0 D1 D2 D3Hot IVCC (mA) 55 50 15 15 IP_VCCP (A) 500 500 500 500 IS_VCCP (A) 500 500 500 500
4.3 Bypass Capacitors
Standard design rules for the supply bypass should be followed. Low-inductance ceramic-chip capacitors are best for bypass capacitors. A value of 0.1 F is recommended for each of the power supply terminals VCC, P_VCCP, and S_VCCP.
4.4 Secondary Clocks
The PCI2250 has five secondary clocks based on the primary PCI clock. Each secondary clock can be enabled or disabled through the secondary clock control register located at PCI offset 68h. We suggest the configuration software or BIOS disable any clocks which are not in use to conserve power. When a secondary clock is disabled, the PCI2250 will drive the clock signal low until the clock is reenabled. Texas Instruments also recommends the use of a 50- series terminator resistor to be connected to each secondary clock to reduce reflections. The primary clock and the secondary clocks have the following relationships: * * They both operate at the same frequency. The maximum clock frequency is 33 MHz.
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* *
The skew between P_CLK and S_CLKOUT[0:4] has a range of 2.72 ns at 0C to 5.8 ns at 115C. The skew between secondary clocks is less than 0.1 ns with similar loading.
To ensure that the skew between the S_CLK input and the clock inputs to the secondary devices is minimized, the trace length between S_CLKOUT4 and S_CLK should match the trace length of the other S_CLKOUT traces. If one or more of the S_CLKOUT terminals is being routed to a socket, then the clock trace lengths to the built-on devices should be 2.5 inches longer than the clock traces to the sockets.
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5 Functional Considerations
5.1 External Arbiter
The PCI2250 allows an external arbiter to be used in place of the default internal arbiter. This function is controlled by terminal 63 (GOZ). In order to use an external arbiter with the PCI2250, terminal 63 must be pulled up with a 10-k resistor or hardwired to 3.3 V. If an external arbiter is not going to be used (the PCI2250 internal arbiter will be used instead), then terminal 63 must be hardwired to GND. When an external secondary bus arbiter is used, the PCI2250 internally reconfigures the S_REQ0 and S_GNT0 signals, so that S_REQ0 becomes the secondary bus master grant for the bridge and the S_GNT0 becomes the secondary bus master request for the PCI2250. This is done because S_REQ0 is an input and can be used to provide the grant input to the bridge and S_GNT0 is an output and can provide the request output from the bridge.
VCC PCI2250 GOZ S_GNT0 S_REQ0 REQ GNT External Arbiter
Figure 5-1. External Arbiter When an external arbiter is used, all unused secondary bus grant outputs (S_GNT3-S_GNT1) are in a high-impedance state. Any unused secondary bus request lines (S_REQ3-S_REQ1) should be pulled high or hardwired to 3.3 V, to prevent the inputs from oscillating.
5.2 PCI Interrupts and IDSEL Mapping
The PCI2250 can support up to four devices on the secondary side. Each device IDSEL should be connected to a secondary address line (S_AD[31:16]). In order to reduce capacitive load on the secondary address line, the connection can be made through a 1-k series resistor. Because the PCI2250 is a bridge device, all parallel PCI interrupts on the secondary interface must be routed as sideband signals to the PCI interrupts on the primary interface. When using multiple devices behind the PCI2250, a device ID and how the PCI interrupts are routed should be very important considerations in a design. Some operating systems like Windows 95TM expect a device PCI interrupt to be routed to a specific interrupt on the motherboard based on its ID number. For example, if a device ID is 4 and its PCI INTA is routed to PCI INTB on the motherboard, Windows 95TM will not configure the device properly. In order to reduce any chance of incompatibilities, we suggest the designer implement the interrupt routing scheme outlined in section 2.2.6 of the PCI Local Bus Specification Revision 2.2. Table 6-1 summarizes section 2.2.6.
Windows 95 is a trademark of Microsoft Corporation.
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Table 5-1. Interrupt Routing
DEVICE NUMBER ON SECONDARY BUS INTERRUPT TERMINAL ON DEVICE INTA INTB INTC INTD INTA INTB INTC INTD INTA INTB INTC INTD INTA INTB INTC INTD INTERRUPT TERMINAL ON CONNECTOR INTA INTB INTC INTD INTB INTC INTD INTA INTC INTD INTA INTB INTD INTA INTB INTC
0, 4, 8, 16, 20, 24, 28
1, 5, 9, 13, 17, 21, 25, 29
2, 6, 10, 14, 18, 22, 26, 30
3, 7, 11, 15, 19, 23, 27, 31
5.3 Multifunction Terminals
The PCI2250 has two multifunction terminals that can be used in three different modes of operation. The modes are IntelTM 21152 compatible mode, TI clock run mode, and TI cPCI hot-swap mode. The mode of operation is controlled by the mode select terminals MS0 and MS1 as shown in the Table 7-1. Table 5-2. Multifunction Terminal Definition Based on Mode Select Terminals
MS0 0 0 1 MS1 0 1 BPCC P_MFUNC HS_ENUM P_CLKRUN P_LOCK S_MFUNC HS_SWITCH S_CLKRUN S_LOCK MODE TI hot-swap TI clock run Intel
5.3.1
CompactPCI Hot-Swap Mode
In cPCI hot-swap mode, the PCI2250 uses P_MFUNC to signal ENUM, S_MFUNC as the input for the switch, and the NAND out pin as the output for the blue LED.
5.3.2
Clock Run Mode
The PCI2250 supports the PCI clock run protocol as defined in the PCI Mobile Design Guide, Revision 1.0. Clock run functionality is implemented in the PCI2250 to reduce power during periods of inactivity. Clock run is typically implemented in mobile computers, but can also be used in desktop systems if there is additional hardware support (chipset, PAL, etc.). In order to use the PCI2250 clock run functionality, a couple of things must be done in hardware. First, MS0 should be tied to GND and MS1 should be tied to 3.3 V. Second, a 10-k pullup resistor should be connected to the secondary clock run signal (terminal 5). Third, determine if a pullup resistor is needed on the primary clock run signal (terminal 102). Typically, a pullup resistor is already installed on the motherboard. If one is not already installed, Texas Instruments recommends using a 10-k pullup resistor on the primary clock run signal. Next, the operating system must determine how to initialize the PCI2250 to stop the primary clock and secondary clocks. All clock run initializing is done through the clock run control register at PCI configuration offset 5Bh.
Intel is a trademark of Intel Corporation.
5-2
The operating system should do the following to initialize the PCI2250 for clock run support. * Set bits 3 and 1 to enable primary and secondary clock run. If the designer is only going to support clock run on the secondary interface and not on the primary interface, only set bit 1 to enable secondary clock run. Determine the clock run mode in bit 4. PCI2250 supports two modes for clock run. One is to stop the secondary clock only on request from the primary bus which is the default operation. The second is to stop the secondary clock whenever the secondary bus is idle and there are no requests from the primary bus. Determine if the PCI2250 wants to keep the primary bus running if the secondary bus is stopped. This is set in bit 2. NOTE: If clock run is not going to be supported on the primary bus, the primary clock run signal must be hardwired to GND. Failure to do so will result in the bridge functioning unpredictably.
*
*
5.3.3
Intel 21152 Compatible Mode
In Intel 21152 compatible mode P_MFUNC and S_MFUNC are used as the PCI LOCK signals. When supporting LOCK, P_MFUNC and S_MFUNC should be pulled up.
5.4 Clock Run Mode
When using the PCI2250 in a power managed environment, it is important to remember that PME and 3.3 Vaux are sideband signals as far as the bridge is concerned. If any devices on the secondary bus need PME or 3.3 Vaux, these signals must be routed around the bridge.
5.5 Sample Schematics
For sample schematics see the PCI2250 Evaluation Module Users Guide, TI Literature Number - SCPU005.
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