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SN54LV367A, SN74LV367A HEX BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS
SCLS398C - APRIL 1998 - REVISED MAY 2000
D D D D D D D D
EPIC TM (Enhanced-Performance Implanted CMOS) Process Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25C Typical VOHV (Output VOH Undershoot) >2.3 V at VCC = 3.3 V, TA = 25C 2-V to 5.5-V VCC Operation Support Mixed-Mode Voltage Operation on All Ports Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD-22 - 2000-V Human-Body Model (A114-A) - 200-V Machine Model (A115-A) - 1000-V Charged-Device Model (C101) Package Options Include Plastic Small-Outline (D, NS), Shrink Small-Outline (DB), Thin Very Small-Outline (DGV), and Thin Shrink Small-Outline (PW) Packages, Ceramic Flat (W) Packages, Chip Carriers (FK), and DIPs (J)
SN54LV367A . . . J OR W PACKAGE SN74LV367A . . . D, DB, DGV, NS, OR PW PACKAGE (TOP VIEW)
1OE 1A1 1Y1 1A2 1Y2 1A3 1Y3 GND
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VCC 2OE 2A2 2Y2 2A1 2Y1 1A4 1Y4
SN54LV367A . . . FK PACKAGE (TOP VIEW)
1A1 1OE NC VCC 2OE 1Y1 1A2 NC 1Y2 1A3
4 5 6 7 8 3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
2A2 2Y2 NC 2A1 2Y1
The 'LV367A devices are hex buffers and line drivers designed for 2-V to 5.5-V VCC operation. These devices are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.
NC - No internal connection
The 'LV367A devices are organized as dual 4-line and 2-line buffers/drivers with active-low output-enable (1OE and 2OE) inputs. When OE is low, the device passes noninverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54LV367A is characterized for operation over the full military temperature range of -55C to 125C. The SN74LV367A is characterized for operation from -40C to 85C.
FUNCTION TABLE (each buffer/driver) INPUTS OE L L H A H L X OUTPUT Y H L Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303
Copyright (c) 2000, Texas Instruments Incorporated
* DALLAS, TEXAS 75265
1Y3 GND NC 1Y4 1A4
description
1
SN54LV367A, SN74LV367A HEX BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS
SCLS398C - APRIL 1998 - REVISED MAY 2000
logic symbol
1 1OE 2 4 6 10 EN 3 5 7 9
1A1 1A2 1A3 1A4
1Y1 1Y2 1Y3 1Y4
15 2OE 12 14
EN 11 13
2A1 2A2
2Y1 2Y2
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages.
logic diagram (positive logic)
1OE 1 2OE 15
1A1
2
3
1Y1
2A1
12
11
2Y1
To Three Other Channels Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages.
To One Other Channel
2
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN54LV367A, SN74LV367A HEX BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS
SCLS398C - APRIL 1998 - REVISED MAY 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Output voltage range applied in the high or low state, VO (see Notes 1 and 2) . . . . . . -0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 mA Package thermal impedance, JA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 5.5 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51.
POST OFFICE BOX 655303
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3
SN54LV367A, SN74LV367A HEX BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS
SCLS398C - APRIL 1998 - REVISED MAY 2000
recommended operating conditions (see Note 4)
SN54LV367A MIN VCC Supply voltage VCC = 2 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V VCC = 2 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V 0 High or low state 3-state VCC = 2 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V VCC = 2 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V 0 0 0 0 2 1.5 VCC x 0.7 VCC x 0.7 VCC x 0.7 0.5 VCC x 0.3 VCC x 0.3 VCC x 0.3 5.5 VCC 5.5 -50 -2 -8 -16 50 2 8 16 200 100 0 0 0 0 0 MAX 5.5 SN74LV367A MIN 2 1.5 VCC x 0.7 VCC x 0.7 VCC x 0.7 0.5 VCC x 0.3 VCC x 0.3 VCC x 0.3 5.5 VCC 5.5 -50 -2 -8 -16 50 2 8 16 200 100 ns/V mA A mA V V MAX 5.5 UNIT V
VIH
High-level High level input voltage
VIL
Low-level Low level input voltage
VI VO
Input voltage Output voltage
V V A
IOH
High-level High level output current
IOL
Low-level Low level output current
t/v
Input transition rise or fall rate
VCC = 4.5 V to 5.5 V 0 20 0 20 TA Operating free-air temperature -55 125 -40 85 C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
4
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN54LV367A, SN74LV367A HEX BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS
SCLS398C - APRIL 1998 - REVISED MAY 2000
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS IOH = -50 A IOH = -2 mA IOH = -8 mA IOH = -16 mA IOL = 50 A IOL = 2 mA IOL = 8 mA IOL = 16 mA VI = VCC or GND VO = VCC or GND VI = VCC or GND, IO = 0 VI or VO = 0 to 5.5 V VI = VCC or GND VI = VCC or GND SN54LV367A VCC 2 V to 5.5 V 2.3 V 3V 4.5 V 2 V to 5.5 V 2.3 V 3V 4.5 V 0 V to 5.5 V 5.5 V 5.5 V 0V 3.3 V 3.3 V 3 5.2 MIN VCC-0.1 2 2.48 3.8 0.1 0.4 0.44 0.55 1 5 20 5 3 5.2 TYP MAX SN74LV367A MIN VCC-0.1 2 2.48 3.8 0.1 0.4 0.44 0.55 1 5 20 5 A A A A pF pF V TYP MAX UNIT
VOH
V
VOL
II IOZ ICC Ioff Ci Co
switching characteristics over recommended operating VCC = 2.5 V 0.2 V (unless otherwise noted) (see Figure 1)
PARAMETER tpd ten tdis tpd ten tdis tsk(o) FROM (INPUT) A OE OE A OE OE TO (OUTPUT) Y Y Y Y Y Y CL = 50 pF CL = 50 pF CL = 15 pF LOAD CAPACITANCE
free-air
temperature
SN74LV367A MIN 1 1 1 1 1 1 MAX 16 20 20 21 25 25 2
range,
UNIT
TA = 25C MIN TYP MAX 6.4* 6.9* 6.4* 8.6 9.4 10.1 12.7* 14.9* 14.9* 17.5 19.7 19.7 2
SN54LV367A MIN 1* 1* 1* 1 1 1 MAX 16* 20* 20* 21 25 25
ns
ns
ns
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
switching characteristics over recommended operating VCC = 3.3 V 0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER tpd ten tdis tpd ten tdis tsk(o) FROM (INPUT) A OE OE A OE OE TO (OUTPUT) Y Y Y Y Y Y CL = 50 pF CL = 50 pF CL = 15 pF LOAD CAPACITANCE
free-air
temperature
SN74LV367A MIN 1 1 1 1 1 1 MAX 10 12.5 12.5 13.5 16 15.5 1.5
range,
UNIT
TA = 25C MIN TYP MAX 4.7* 5.1* 4.9* 6.2 6.8 7.3 8.3* 10.5* 10.5* 11.8 14 13.6 1.5
SN54LV367A MIN 1* 1* 1* 1 1 1 MAX 10* 12.5* 12.5* 13.5 16 15.5
ns
ns
ns
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
5
SN54LV367A, SN74LV367A HEX BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS
SCLS398C - APRIL 1998 - REVISED MAY 2000
switching characteristics over recommended operating VCC = 5 V 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER tpd ten tdis tpd ten tdis tsk(o) FROM (INPUT) A OE OE A OE OE TO (OUTPUT) Y Y Y Y Y Y CL = 50 pF CL = 50 pF CL = 15 pF LOAD CAPACITANCE MIN
free-air
temperature
SN74LV367A MIN 1 1 0 1 1 0 MAX 7 8.5 8.5 9 10.5 10.5 1
range,
UNIT
TA = 25C TYP MAX 3.6* 3.8* 2.6* 4.5 4.9 4.5 5.9* 7.2* 7.2* 7.9 9.2 9.2 1
SN54LV367A MIN 1* 1* 1* 1 1 1 MAX 7* 8.5* 8.5* 9 10.5 10.5
ns
ns
ns
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
noise characteristics, VCC = 3.3 V, CL = 50 pF, TA = 25C (see Note 5)
PARAMETER VOL(P) VOL(V) VOH(V) VIH(D) Quiet output, maximum dynamic VOL Quiet output, minimum dynamic VOL Quiet output, minimum dynamic VOH High-level dynamic input voltage 2.31 0.99 SN74LV367A MIN TYP 0.5 -0.2 3 MAX 0.8 -0.8 UNIT V V V V V
VIL(D) Low-level dynamic input voltage NOTE 5: Characteristics are for surface-mount packages only.
operating characteristics, TA = 25C
PARAMETER Cpd d Power dissipation capacitance TEST CONDITIONS CL = 50 pF pF, f = 10 MHz VCC 3.3 V 5V TYP 14.9 17.4 UNIT pF
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
6
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN54LV367A, SN74LV367A HEX BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS
SCLS398C - APRIL 1998 - REVISED MAY 2000
PARAMETER MEASUREMENT INFORMATION
RL = 1 k S1 VCC Open GND
From Output Under Test CL (see Note A)
Test Point
From Output Under Test CL (see Note A)
TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain
S1 Open VCC GND VCC
LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS
LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS VCC Timing Input 50% VCC 0V VCC tsu Data Input 0V 50% VCC th VCC 50% VCC 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC VCC 50% VCC tPZL Output Waveform 1 S1 at VCC (see Note B) tPZH Output Waveform 2 S1 at GND (see Note B) 50% VCC 50% VCC 50% VCC 0V tPLZ VCC VOL + 0.3 V VOL tPHZ VOH - 0.3 V VOH 0 V
tw
Input
50% VCC
50% VCC
VOLTAGE WAVEFORMS PULSE DURATION
Input tPLH In-Phase Output tPHL Out-of-Phase Output
50% VCC
50% VCC tPHL
0V
Output Control
50% VCC
VOH 50% VCC VOL tPLH
50% VCC
VOH 50% VCC VOL
VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr 3 ns, tf 3 ns. D. The outputs are measured one at a time with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPHL and tPLH are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
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Copyright (c) 2000, Texas Instruments Incorporated

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